drivers/gpu/drm/i915/display/skl_scaler.c

   1 // SPDX-License-Identifier: MIT
   2 /*
   3  * Copyright © 2020 Intel Corporation
   4  */
   5
   6 #include "i915_reg.h"
   7 #include "intel_de.h"
   8 #include "intel_display_types.h"
   9 #include "intel_fb.h"
  10 #include "skl_scaler.h"
  11 #include "skl_universal_plane.h"
  12
  13 /*
  14  * The hardware phase 0.0 refers to the center of the pixel.
  15  * We want to start from the top/left edge which is phase
  16  * -0.5. That matches how the hardware calculates the scaling
  17  * factors (from top-left of the first pixel to bottom-right
  18  * of the last pixel, as opposed to the pixel centers).
  19  *
  20  * For 4:2:0 subsampled chroma planes we obviously have to
  21  * adjust that so that the chroma sample position lands in
  22  * the right spot.
  23  *
  24  * Note that for packed YCbCr 4:2:2 formats there is no way to
  25  * control chroma siting. The hardware simply replicates the
  26  * chroma samples for both of the luma samples, and thus we don't
  27  * actually get the expected MPEG2 chroma siting convention :(
  28  * The same behaviour is observed on pre-SKL platforms as well.
  29  *
  30  * Theory behind the formula (note that we ignore sub-pixel
  31  * source coordinates):
  32  * s = source sample position
  33  * d = destination sample position
  34  *
  35  * Downscaling 4:1:
  36  * -0.5
  37  * | 0.0
  38  * | |     1.5 (initial phase)
  39  * | |     |
  40  * v v     v
  41  * | s | s | s | s |
  42  * |       d       |
  43  *
  44  * Upscaling 1:4:
  45  * -0.5
  46  * | -0.375 (initial phase)
  47  * | |     0.0
  48  * | |     |
  49  * v v     v
  50  * |       s       |
  51  * | d | d | d | d |
  52  */
  53 static u16 skl_scaler_calc_phase(int sub, int scale, bool chroma_cosited)
  54 {
  55         int phase = -0x8000;
  56         u16 trip = 0;
  57
  58         if (chroma_cosited)
  59                 phase += (sub - 1) * 0x8000 / sub;
  60
  61         phase += scale / (2 * sub);
  62
  63         /*
  64          * Hardware initial phase limited to [-0.5:1.5].
  65          * Since the max hardware scale factor is 3.0, we
  66          * should never actually excdeed 1.0 here.
  67          */
  68         WARN_ON(phase < -0x8000 || phase > 0x18000);
  69
  70         if (phase < 0)
  71                 phase = 0x10000 + phase;
  72         else
  73                 trip = PS_PHASE_TRIP;
  74
  75         return ((phase >> 2) & PS_PHASE_MASK) | trip;
  76 }
  77
  78 #define SKL_MIN_SRC_W 8
  79 #define SKL_MAX_SRC_W 4096
  80 #define SKL_MIN_SRC_H 8
  81 #define SKL_MAX_SRC_H 4096
  82 #define SKL_MIN_DST_W 8
  83 #define SKL_MAX_DST_W 4096
  84 #define SKL_MIN_DST_H 8
  85 #define SKL_MAX_DST_H 4096
  86 #define ICL_MAX_SRC_W 5120
  87 #define ICL_MAX_SRC_H 4096
  88 #define ICL_MAX_DST_W 5120
  89 #define ICL_MAX_DST_H 4096
  90 #define TGL_MAX_SRC_W 5120
  91 #define TGL_MAX_SRC_H 8192
  92 #define TGL_MAX_DST_W 8192
  93 #define TGL_MAX_DST_H 8192
  94 #define MTL_MAX_SRC_W 4096
  95 #define MTL_MAX_SRC_H 8192
  96 #define MTL_MAX_DST_W 8192
  97 #define MTL_MAX_DST_H 8192
  98 #define SKL_MIN_YUV_420_SRC_W 16
  99 #define SKL_MIN_YUV_420_SRC_H 16
 100
 101 static int
 102 skl_update_scaler(struct intel_crtc_state *crtc_state, bool force_detach,
 103                   unsigned int scaler_user, int *scaler_id,
 104                   int src_w, int src_h, int dst_w, int dst_h,
 105                   const struct drm_format_info *format,
 106                   u64 modifier, bool need_scaler)
 107 {
 108         struct intel_crtc_scaler_state *scaler_state =
 109                 &crtc_state->scaler_state;
 110         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
 111         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 112         const struct drm_display_mode *adjusted_mode =
 113                 &crtc_state->hw.adjusted_mode;
 114         int pipe_src_w = drm_rect_width(&crtc_state->pipe_src);
 115         int pipe_src_h = drm_rect_height(&crtc_state->pipe_src);
 116         int min_src_w, min_src_h, min_dst_w, min_dst_h;
 117         int max_src_w, max_src_h, max_dst_w, max_dst_h;
 118
 119         /*
 120          * Src coordinates are already rotated by 270 degrees for
 121          * the 90/270 degree plane rotation cases (to match the
 122          * GTT mapping), hence no need to account for rotation here.
 123          */
 124         if (src_w != dst_w || src_h != dst_h)
 125                 need_scaler = true;
 126
 127         /*
 128          * Scaling/fitting not supported in IF-ID mode in GEN9+
 129          * TODO: Interlace fetch mode doesn't support YUV420 planar formats.
 130          * Once NV12 is enabled, handle it here while allocating scaler
 131          * for NV12.
 132          */
 133         if (DISPLAY_VER(dev_priv) >= 9 && crtc_state->hw.enable &&
 134             need_scaler && adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
 135                 drm_dbg_kms(&dev_priv->drm,
 136                             "Pipe/Plane scaling not supported with IF-ID mode\n");
 137                 return -EINVAL;
 138         }
 139
 140         /*
 141          * if plane is being disabled or scaler is no more required or force detach
 142          *  - free scaler binded to this plane/crtc
 143          *  - in order to do this, update crtc->scaler_usage
 144          *
 145          * Here scaler state in crtc_state is set free so that
 146          * scaler can be assigned to other user. Actual register
 147          * update to free the scaler is done in plane/panel-fit programming.
 148          * For this purpose crtc/plane_state->scaler_id isn't reset here.
 149          */
 150         if (force_detach || !need_scaler) {
 151                 if (*scaler_id >= 0) {
 152                         scaler_state->scaler_users &= ~(1 << scaler_user);
 153                         scaler_state->scalers[*scaler_id].in_use = 0;
 154
 155                         drm_dbg_kms(&dev_priv->drm,
 156                                     "scaler_user index %u.%u: "
 157                                     "Staged freeing scaler id %d scaler_users = 0x%x\n",
 158                                     crtc->pipe, scaler_user, *scaler_id,
 159                                     scaler_state->scaler_users);
 160                         *scaler_id = -1;
 161                 }
 162                 return 0;
 163         }
 164
 165         if (format && intel_format_info_is_yuv_semiplanar(format, modifier) &&
 166             (src_h < SKL_MIN_YUV_420_SRC_H || src_w < SKL_MIN_YUV_420_SRC_W)) {
 167                 drm_dbg_kms(&dev_priv->drm,
 168                             "Planar YUV: src dimensions not met\n");
 169                 return -EINVAL;
 170         }
 171
 172         min_src_w = SKL_MIN_SRC_W;
 173         min_src_h = SKL_MIN_SRC_H;
 174         min_dst_w = SKL_MIN_DST_W;
 175         min_dst_h = SKL_MIN_DST_H;
 176
 177         if (DISPLAY_VER(dev_priv) < 11) {
 178                 max_src_w = SKL_MAX_SRC_W;
 179                 max_src_h = SKL_MAX_SRC_H;
 180                 max_dst_w = SKL_MAX_DST_W;
 181                 max_dst_h = SKL_MAX_DST_H;
 182         } else if (DISPLAY_VER(dev_priv) < 12) {
 183                 max_src_w = ICL_MAX_SRC_W;
 184                 max_src_h = ICL_MAX_SRC_H;
 185                 max_dst_w = ICL_MAX_DST_W;
 186                 max_dst_h = ICL_MAX_DST_H;
 187         } else if (DISPLAY_VER(dev_priv) < 14) {
 188                 max_src_w = TGL_MAX_SRC_W;
 189                 max_src_h = TGL_MAX_SRC_H;
 190                 max_dst_w = TGL_MAX_DST_W;
 191                 max_dst_h = TGL_MAX_DST_H;
 192         } else {
 193                 max_src_w = MTL_MAX_SRC_W;
 194                 max_src_h = MTL_MAX_SRC_H;
 195                 max_dst_w = MTL_MAX_DST_W;
 196                 max_dst_h = MTL_MAX_DST_H;
 197         }
 198
 199         /* range checks */
 200         if (src_w < min_src_w || src_h < min_src_h ||
 201             dst_w < min_dst_w || dst_h < min_dst_h ||
 202             src_w > max_src_w || src_h > max_src_h ||
 203             dst_w > max_dst_w || dst_h > max_dst_h) {
 204                 drm_dbg_kms(&dev_priv->drm,
 205                             "scaler_user index %u.%u: src %ux%u dst %ux%u "
 206                             "size is out of scaler range\n",
 207                             crtc->pipe, scaler_user, src_w, src_h,
 208                             dst_w, dst_h);
 209                 return -EINVAL;
 210         }
 211
 212         /*
 213          * The pipe scaler does not use all the bits of PIPESRC, at least
 214          * on the earlier platforms. So even when we're scaling a plane
 215          * the *pipe* source size must not be too large. For simplicity
 216          * we assume the limits match the scaler source size limits. Might
 217          * not be 100% accurate on all platforms, but good enough for now.
 218          */
 219         if (pipe_src_w > max_src_w || pipe_src_h > max_src_h) {
 220                 drm_dbg_kms(&dev_priv->drm,
 221                             "scaler_user index %u.%u: pipe src size %ux%u "
 222                             "is out of scaler range\n",
 223                             crtc->pipe, scaler_user, pipe_src_w, pipe_src_h);
 224                 return -EINVAL;
 225         }
 226
 227         /* mark this plane as a scaler user in crtc_state */
 228         scaler_state->scaler_users |= (1 << scaler_user);
 229         drm_dbg_kms(&dev_priv->drm, "scaler_user index %u.%u: "
 230                     "staged scaling request for %ux%u->%ux%u scaler_users = 0x%x\n",
 231                     crtc->pipe, scaler_user, src_w, src_h, dst_w, dst_h,
 232                     scaler_state->scaler_users);
 233
 234         return 0;
 235 }
 236
 237 int skl_update_scaler_crtc(struct intel_crtc_state *crtc_state)
 238 {
 239         const struct drm_display_mode *pipe_mode = &crtc_state->hw.pipe_mode;
 240         int width, height;
 241
 242         if (crtc_state->pch_pfit.enabled) {
 243                 width = drm_rect_width(&crtc_state->pch_pfit.dst);
 244                 height = drm_rect_height(&crtc_state->pch_pfit.dst);
 245         } else {
 246                 width = pipe_mode->crtc_hdisplay;
 247                 height = pipe_mode->crtc_vdisplay;
 248         }
 249         return skl_update_scaler(crtc_state, !crtc_state->hw.active,
 250                                  SKL_CRTC_INDEX,
 251                                  &crtc_state->scaler_state.scaler_id,
 252                                  drm_rect_width(&crtc_state->pipe_src),
 253                                  drm_rect_height(&crtc_state->pipe_src),
 254                                  width, height, NULL, 0,
 255                                  crtc_state->pch_pfit.enabled);
 256 }
 257
 258 /**
 259  * skl_update_scaler_plane - Stages update to scaler state for a given plane.
 260  * @crtc_state: crtc's scaler state
 261  * @plane_state: atomic plane state to update
 262  *
 263  * Return
 264  *     0 - scaler_usage updated successfully
 265  *    error - requested scaling cannot be supported or other error condition
 266  */
 267 int skl_update_scaler_plane(struct intel_crtc_state *crtc_state,
 268                             struct intel_plane_state *plane_state)
 269 {
 270         struct intel_plane *intel_plane =
 271                 to_intel_plane(plane_state->uapi.plane);
 272         struct drm_i915_private *dev_priv = to_i915(intel_plane->base.dev);
 273         struct drm_framebuffer *fb = plane_state->hw.fb;
 274         int ret;
 275         bool force_detach = !fb || !plane_state->uapi.visible;
 276         bool need_scaler = false;
 277
 278         /* Pre-gen11 and SDR planes always need a scaler for planar formats. */
 279         if (!icl_is_hdr_plane(dev_priv, intel_plane->id) &&
 280             fb && intel_format_info_is_yuv_semiplanar(fb->format, fb->modifier))
 281                 need_scaler = true;
 282
 283         ret = skl_update_scaler(crtc_state, force_detach,
 284                                 drm_plane_index(&intel_plane->base),
 285                                 &plane_state->scaler_id,
 286                                 drm_rect_width(&plane_state->uapi.src) >> 16,
 287                                 drm_rect_height(&plane_state->uapi.src) >> 16,
 288                                 drm_rect_width(&plane_state->uapi.dst),
 289                                 drm_rect_height(&plane_state->uapi.dst),
 290                                 fb ? fb->format : NULL,
 291                                 fb ? fb->modifier : 0,
 292                                 need_scaler);
 293
 294         if (ret || plane_state->scaler_id < 0)
 295                 return ret;
 296
 297         /* check colorkey */
 298         if (plane_state->ckey.flags) {
 299                 drm_dbg_kms(&dev_priv->drm,
 300                             "[PLANE:%d:%s] scaling with color key not allowed",
 301                             intel_plane->base.base.id,
 302                             intel_plane->base.name);
 303                 return -EINVAL;
 304         }
 305
 306         /* Check src format */
 307         switch (fb->format->format) {
 308         case DRM_FORMAT_RGB565:
 309         case DRM_FORMAT_XBGR8888:
 310         case DRM_FORMAT_XRGB8888:
 311         case DRM_FORMAT_ABGR8888:
 312         case DRM_FORMAT_ARGB8888:
 313         case DRM_FORMAT_XRGB2101010:
 314         case DRM_FORMAT_XBGR2101010:
 315         case DRM_FORMAT_ARGB2101010:
 316         case DRM_FORMAT_ABGR2101010:
 317         case DRM_FORMAT_YUYV:
 318         case DRM_FORMAT_YVYU:
 319         case DRM_FORMAT_UYVY:
 320         case DRM_FORMAT_VYUY:
 321         case DRM_FORMAT_NV12:
 322         case DRM_FORMAT_XYUV8888:
 323         case DRM_FORMAT_P010:
 324         case DRM_FORMAT_P012:
 325         case DRM_FORMAT_P016:
 326         case DRM_FORMAT_Y210:
 327         case DRM_FORMAT_Y212:
 328         case DRM_FORMAT_Y216:
 329         case DRM_FORMAT_XVYU2101010:
 330         case DRM_FORMAT_XVYU12_16161616:
 331         case DRM_FORMAT_XVYU16161616:
 332                 break;
 333         case DRM_FORMAT_XBGR16161616F:
 334         case DRM_FORMAT_ABGR16161616F:
 335         case DRM_FORMAT_XRGB16161616F:
 336         case DRM_FORMAT_ARGB16161616F:
 337                 if (DISPLAY_VER(dev_priv) >= 11)
 338                         break;
 339                 fallthrough;
 340         default:
 341                 drm_dbg_kms(&dev_priv->drm,
 342                             "[PLANE:%d:%s] FB:%d unsupported scaling format 0x%x\n",
 343                             intel_plane->base.base.id, intel_plane->base.name,
 344                             fb->base.id, fb->format->format);
 345                 return -EINVAL;
 346         }
 347
 348         return 0;
 349 }
 350
 351 static int glk_coef_tap(int i)
 352 {
 353         return i % 7;
 354 }
 355
 356 static u16 glk_nearest_filter_coef(int t)
 357 {
 358         return t == 3 ? 0x0800 : 0x3000;
 359 }
 360
 361 /*
 362  *  Theory behind setting nearest-neighbor integer scaling:
 363  *
 364  *  17 phase of 7 taps requires 119 coefficients in 60 dwords per set.
 365  *  The letter represents the filter tap (D is the center tap) and the number
 366  *  represents the coefficient set for a phase (0-16).
 367  *
 368  *         +------------+------------------------+------------------------+
 369  *         |Index value | Data value coeffient 1 | Data value coeffient 2 |
 370  *         +------------+------------------------+------------------------+
 371  *         |   00h      |          B0            |          A0            |
 372  *         +------------+------------------------+------------------------+
 373  *         |   01h      |          D0            |          C0            |
 374  *         +------------+------------------------+------------------------+
 375  *         |   02h      |          F0            |          E0            |
 376  *         +------------+------------------------+------------------------+
 377  *         |   03h      |          A1            |          G0            |
 378  *         +------------+------------------------+------------------------+
 379  *         |   04h      |          C1            |          B1            |
 380  *         +------------+------------------------+------------------------+
 381  *         |   ...      |          ...           |          ...           |
 382  *         +------------+------------------------+------------------------+
 383  *         |   38h      |          B16           |          A16           |
 384  *         +------------+------------------------+------------------------+
 385  *         |   39h      |          D16           |          C16           |
 386  *         +------------+------------------------+------------------------+
 387  *         |   3Ah      |          F16           |          C16           |
 388  *         +------------+------------------------+------------------------+
 389  *         |   3Bh      |        Reserved        |          G16           |
 390  *         +------------+------------------------+------------------------+
 391  *
 392  *  To enable nearest-neighbor scaling:  program scaler coefficents with
 393  *  the center tap (Dxx) values set to 1 and all other values set to 0 as per
 394  *  SCALER_COEFFICIENT_FORMAT
 395  *
 396  */
 397
 398 static void glk_program_nearest_filter_coefs(struct drm_i915_private *dev_priv,
 399                                              enum pipe pipe, int id, int set)
 400 {
 401         int i;
 402
 403         intel_de_write_fw(dev_priv, GLK_PS_COEF_INDEX_SET(pipe, id, set),
 404                           PS_COEE_INDEX_AUTO_INC);
 405
 406         for (i = 0; i < 17 * 7; i += 2) {
 407                 u32 tmp;
 408                 int t;
 409
 410                 t = glk_coef_tap(i);
 411                 tmp = glk_nearest_filter_coef(t);
 412
 413                 t = glk_coef_tap(i + 1);
 414                 tmp |= glk_nearest_filter_coef(t) << 16;
 415
 416                 intel_de_write_fw(dev_priv, GLK_PS_COEF_DATA_SET(pipe, id, set),
 417                                   tmp);
 418         }
 419
 420         intel_de_write_fw(dev_priv, GLK_PS_COEF_INDEX_SET(pipe, id, set), 0);
 421 }
 422
 423 static u32 skl_scaler_get_filter_select(enum drm_scaling_filter filter, int set)
 424 {
 425         if (filter == DRM_SCALING_FILTER_NEAREST_NEIGHBOR) {
 426                 return (PS_FILTER_PROGRAMMED |
 427                         PS_Y_VERT_FILTER_SELECT(set) |
 428                         PS_Y_HORZ_FILTER_SELECT(set) |
 429                         PS_UV_VERT_FILTER_SELECT(set) |
 430                         PS_UV_HORZ_FILTER_SELECT(set));
 431         }
 432
 433         return PS_FILTER_MEDIUM;
 434 }
 435
 436 static void skl_scaler_setup_filter(struct drm_i915_private *dev_priv, enum pipe pipe,
 437                                     int id, int set, enum drm_scaling_filter filter)
 438 {
 439         switch (filter) {
 440         case DRM_SCALING_FILTER_DEFAULT:
 441                 break;
 442         case DRM_SCALING_FILTER_NEAREST_NEIGHBOR:
 443                 glk_program_nearest_filter_coefs(dev_priv, pipe, id, set);
 444                 break;
 445         default:
 446                 MISSING_CASE(filter);
 447         }
 448 }
 449
 450 void skl_pfit_enable(const struct intel_crtc_state *crtc_state)
 451 {
 452         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
 453         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 454         const struct intel_crtc_scaler_state *scaler_state =
 455                 &crtc_state->scaler_state;
 456         const struct drm_rect *dst = &crtc_state->pch_pfit.dst;
 457         u16 uv_rgb_hphase, uv_rgb_vphase;
 458         enum pipe pipe = crtc->pipe;
 459         int width = drm_rect_width(dst);
 460         int height = drm_rect_height(dst);
 461         int x = dst->x1;
 462         int y = dst->y1;
 463         int hscale, vscale;
 464         struct drm_rect src;
 465         int id;
 466         u32 ps_ctrl;
 467
 468         if (!crtc_state->pch_pfit.enabled)
 469                 return;
 470
 471         if (drm_WARN_ON(&dev_priv->drm,
 472                         crtc_state->scaler_state.scaler_id < 0))
 473                 return;
 474
 475         drm_rect_init(&src, 0, 0,
 476                       drm_rect_width(&crtc_state->pipe_src) << 16,
 477                       drm_rect_height(&crtc_state->pipe_src) << 16);
 478
 479         hscale = drm_rect_calc_hscale(&src, dst, 0, INT_MAX);
 480         vscale = drm_rect_calc_vscale(&src, dst, 0, INT_MAX);
 481
 482         uv_rgb_hphase = skl_scaler_calc_phase(1, hscale, false);
 483         uv_rgb_vphase = skl_scaler_calc_phase(1, vscale, false);
 484
 485         id = scaler_state->scaler_id;
 486
 487         ps_ctrl = skl_scaler_get_filter_select(crtc_state->hw.scaling_filter, 0);
 488         ps_ctrl |=  PS_SCALER_EN | scaler_state->scalers[id].mode;
 489
 490         skl_scaler_setup_filter(dev_priv, pipe, id, 0,
 491                                 crtc_state->hw.scaling_filter);
 492
 493         intel_de_write_fw(dev_priv, SKL_PS_CTRL(pipe, id), ps_ctrl);
 494
 495         intel_de_write_fw(dev_priv, SKL_PS_VPHASE(pipe, id),
 496                           PS_Y_PHASE(0) | PS_UV_RGB_PHASE(uv_rgb_vphase));
 497         intel_de_write_fw(dev_priv, SKL_PS_HPHASE(pipe, id),
 498                           PS_Y_PHASE(0) | PS_UV_RGB_PHASE(uv_rgb_hphase));
 499         intel_de_write_fw(dev_priv, SKL_PS_WIN_POS(pipe, id),
 500                           x << 16 | y);
 501         intel_de_write_fw(dev_priv, SKL_PS_WIN_SZ(pipe, id),
 502                           width << 16 | height);
 503 }
 504
 505 void
 506 skl_program_plane_scaler(struct intel_plane *plane,
 507                          const struct intel_crtc_state *crtc_state,
 508                          const struct intel_plane_state *plane_state)
 509 {
 510         struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
 511         const struct drm_framebuffer *fb = plane_state->hw.fb;
 512         enum pipe pipe = plane->pipe;
 513         int scaler_id = plane_state->scaler_id;
 514         const struct intel_scaler *scaler =
 515                 &crtc_state->scaler_state.scalers[scaler_id];
 516         int crtc_x = plane_state->uapi.dst.x1;
 517         int crtc_y = plane_state->uapi.dst.y1;
 518         u32 crtc_w = drm_rect_width(&plane_state->uapi.dst);
 519         u32 crtc_h = drm_rect_height(&plane_state->uapi.dst);
 520         u16 y_hphase, uv_rgb_hphase;
 521         u16 y_vphase, uv_rgb_vphase;
 522         int hscale, vscale;
 523         u32 ps_ctrl;
 524
 525         hscale = drm_rect_calc_hscale(&plane_state->uapi.src,
 526                                       &plane_state->uapi.dst,
 527                                       0, INT_MAX);
 528         vscale = drm_rect_calc_vscale(&plane_state->uapi.src,
 529                                       &plane_state->uapi.dst,
 530                                       0, INT_MAX);
 531
 532         /* TODO: handle sub-pixel coordinates */
 533         if (intel_format_info_is_yuv_semiplanar(fb->format, fb->modifier) &&
 534             !icl_is_hdr_plane(dev_priv, plane->id)) {
 535                 y_hphase = skl_scaler_calc_phase(1, hscale, false);
 536                 y_vphase = skl_scaler_calc_phase(1, vscale, false);
 537
 538                 /* MPEG2 chroma siting convention */
 539                 uv_rgb_hphase = skl_scaler_calc_phase(2, hscale, true);
 540                 uv_rgb_vphase = skl_scaler_calc_phase(2, vscale, false);
 541         } else {
 542                 /* not used */
 543                 y_hphase = 0;
 544                 y_vphase = 0;
 545
 546                 uv_rgb_hphase = skl_scaler_calc_phase(1, hscale, false);
 547                 uv_rgb_vphase = skl_scaler_calc_phase(1, vscale, false);
 548         }
 549
 550         ps_ctrl = skl_scaler_get_filter_select(plane_state->hw.scaling_filter, 0);
 551         ps_ctrl |= PS_SCALER_EN | PS_PLANE_SEL(plane->id) | scaler->mode;
 552
 553         skl_scaler_setup_filter(dev_priv, pipe, scaler_id, 0,
 554                                 plane_state->hw.scaling_filter);
 555
 556         intel_de_write_fw(dev_priv, SKL_PS_CTRL(pipe, scaler_id), ps_ctrl);
 557         intel_de_write_fw(dev_priv, SKL_PS_VPHASE(pipe, scaler_id),
 558                           PS_Y_PHASE(y_vphase) | PS_UV_RGB_PHASE(uv_rgb_vphase));
 559         intel_de_write_fw(dev_priv, SKL_PS_HPHASE(pipe, scaler_id),
 560                           PS_Y_PHASE(y_hphase) | PS_UV_RGB_PHASE(uv_rgb_hphase));
 561         intel_de_write_fw(dev_priv, SKL_PS_WIN_POS(pipe, scaler_id),
 562                           (crtc_x << 16) | crtc_y);
 563         intel_de_write_fw(dev_priv, SKL_PS_WIN_SZ(pipe, scaler_id),
 564                           (crtc_w << 16) | crtc_h);
 565 }
 566
 567 static void skl_detach_scaler(struct intel_crtc *crtc, int id)
 568 {
 569         struct drm_device *dev = crtc->base.dev;
 570         struct drm_i915_private *dev_priv = to_i915(dev);
 571
 572         intel_de_write_fw(dev_priv, SKL_PS_CTRL(crtc->pipe, id), 0);
 573         intel_de_write_fw(dev_priv, SKL_PS_WIN_POS(crtc->pipe, id), 0);
 574         intel_de_write_fw(dev_priv, SKL_PS_WIN_SZ(crtc->pipe, id), 0);
 575 }
 576
 577 /*
 578  * This function detaches (aka. unbinds) unused scalers in hardware
 579  */
 580 void skl_detach_scalers(const struct intel_crtc_state *crtc_state)
 581 {
 582         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
 583         const struct intel_crtc_scaler_state *scaler_state =
 584                 &crtc_state->scaler_state;
 585         int i;
 586
 587         /* loop through and disable scalers that aren't in use */
 588         for (i = 0; i < crtc->num_scalers; i++) {
 589                 if (!scaler_state->scalers[i].in_use)
 590                         skl_detach_scaler(crtc, i);
 591         }
 592 }
 593
 594 void skl_scaler_disable(const struct intel_crtc_state *old_crtc_state)
 595 {
 596         struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc);
 597         int i;
 598
 599         for (i = 0; i < crtc->num_scalers; i++)
 600                 skl_detach_scaler(crtc, i);
 601 }