drivers/gpu/drm/i915/display/intel_fbc.c

   1 /*
   2  * Copyright © 2014 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  21  * DEALINGS IN THE SOFTWARE.
  22  */
  23
  24 /**
  25  * DOC: Frame Buffer Compression (FBC)
  26  *
  27  * FBC tries to save memory bandwidth (and so power consumption) by
  28  * compressing the amount of memory used by the display. It is total
  29  * transparent to user space and completely handled in the kernel.
  30  *
  31  * The benefits of FBC are mostly visible with solid backgrounds and
  32  * variation-less patterns. It comes from keeping the memory footprint small
  33  * and having fewer memory pages opened and accessed for refreshing the display.
  34  *
  35  * i915 is responsible to reserve stolen memory for FBC and configure its
  36  * offset on proper registers. The hardware takes care of all
  37  * compress/decompress. However there are many known cases where we have to
  38  * forcibly disable it to allow proper screen updates.
  39  */
  40
  41 #include <linux/string_helpers.h>
  42
  43 #include <drm/drm_blend.h>
  44 #include <drm/drm_fourcc.h>
  45
  46 #include "i915_drv.h"
  47 #include "i915_utils.h"
  48 #include "i915_vgpu.h"
  49 #include "intel_cdclk.h"
  50 #include "intel_de.h"
  51 #include "intel_display_trace.h"
  52 #include "intel_display_types.h"
  53 #include "intel_fbc.h"
  54 #include "intel_frontbuffer.h"
  55
  56 #define for_each_fbc_id(__dev_priv, __fbc_id) \
  57         for ((__fbc_id) = INTEL_FBC_A; (__fbc_id) < I915_MAX_FBCS; (__fbc_id)++) \
  58                 for_each_if(RUNTIME_INFO(__dev_priv)->fbc_mask & BIT(__fbc_id))
  59
  60 #define for_each_intel_fbc(__dev_priv, __fbc, __fbc_id) \
  61         for_each_fbc_id((__dev_priv), (__fbc_id)) \
  62                 for_each_if((__fbc) = (__dev_priv)->display.fbc[(__fbc_id)])
  63
  64 struct intel_fbc_funcs {
  65         void (*activate)(struct intel_fbc *fbc);
  66         void (*deactivate)(struct intel_fbc *fbc);
  67         bool (*is_active)(struct intel_fbc *fbc);
  68         bool (*is_compressing)(struct intel_fbc *fbc);
  69         void (*nuke)(struct intel_fbc *fbc);
  70         void (*program_cfb)(struct intel_fbc *fbc);
  71         void (*set_false_color)(struct intel_fbc *fbc, bool enable);
  72 };
  73
  74 struct intel_fbc_state {
  75         struct intel_plane *plane;
  76         unsigned int cfb_stride;
  77         unsigned int cfb_size;
  78         unsigned int fence_y_offset;
  79         u16 override_cfb_stride;
  80         u16 interval;
  81         s8 fence_id;
  82 };
  83
  84 struct intel_fbc {
  85         struct drm_i915_private *i915;
  86         const struct intel_fbc_funcs *funcs;
  87
  88         /*
  89          * This is always the inner lock when overlapping with
  90          * struct_mutex and it's the outer lock when overlapping
  91          * with stolen_lock.
  92          */
  93         struct mutex lock;
  94         unsigned int busy_bits;
  95
  96         struct drm_mm_node compressed_fb;
  97         struct drm_mm_node compressed_llb;
  98
  99         enum intel_fbc_id id;
 100
 101         u8 limit;
 102
 103         bool false_color;
 104
 105         bool active;
 106         bool activated;
 107         bool flip_pending;
 108
 109         bool underrun_detected;
 110         struct work_struct underrun_work;
 111
 112         /*
 113          * This structure contains everything that's relevant to program the
 114          * hardware registers. When we want to figure out if we need to disable
 115          * and re-enable FBC for a new configuration we just check if there's
 116          * something different in the struct. The genx_fbc_activate functions
 117          * are supposed to read from it in order to program the registers.
 118          */
 119         struct intel_fbc_state state;
 120         const char *no_fbc_reason;
 121 };
 122
 123 /* plane stride in pixels */
 124 static unsigned int intel_fbc_plane_stride(const struct intel_plane_state *plane_state)
 125 {
 126         const struct drm_framebuffer *fb = plane_state->hw.fb;
 127         unsigned int stride;
 128
 129         stride = plane_state->view.color_plane[0].mapping_stride;
 130         if (!drm_rotation_90_or_270(plane_state->hw.rotation))
 131                 stride /= fb->format->cpp[0];
 132
 133         return stride;
 134 }
 135
 136 /* plane stride based cfb stride in bytes, assuming 1:1 compression limit */
 137 static unsigned int _intel_fbc_cfb_stride(const struct intel_plane_state *plane_state)
 138 {
 139         unsigned int cpp = 4; /* FBC always 4 bytes per pixel */
 140
 141         return intel_fbc_plane_stride(plane_state) * cpp;
 142 }
 143
 144 /* minimum acceptable cfb stride in bytes, assuming 1:1 compression limit */
 145 static unsigned int skl_fbc_min_cfb_stride(const struct intel_plane_state *plane_state)
 146 {
 147         struct drm_i915_private *i915 = to_i915(plane_state->uapi.plane->dev);
 148         unsigned int limit = 4; /* 1:4 compression limit is the worst case */
 149         unsigned int cpp = 4; /* FBC always 4 bytes per pixel */
 150         unsigned int width = drm_rect_width(&plane_state->uapi.src) >> 16;
 151         unsigned int height = 4; /* FBC segment is 4 lines */
 152         unsigned int stride;
 153
 154         /* minimum segment stride we can use */
 155         stride = width * cpp * height / limit;
 156
 157         /*
 158          * Wa_16011863758: icl+
 159          * Avoid some hardware segment address miscalculation.
 160          */
 161         if (DISPLAY_VER(i915) >= 11)
 162                 stride += 64;
 163
 164         /*
 165          * At least some of the platforms require each 4 line segment to
 166          * be 512 byte aligned. Just do it always for simplicity.
 167          */
 168         stride = ALIGN(stride, 512);
 169
 170         /* convert back to single line equivalent with 1:1 compression limit */
 171         return stride * limit / height;
 172 }
 173
 174 /* properly aligned cfb stride in bytes, assuming 1:1 compression limit */
 175 static unsigned int intel_fbc_cfb_stride(const struct intel_plane_state *plane_state)
 176 {
 177         struct drm_i915_private *i915 = to_i915(plane_state->uapi.plane->dev);
 178         unsigned int stride = _intel_fbc_cfb_stride(plane_state);
 179
 180         /*
 181          * At least some of the platforms require each 4 line segment to
 182          * be 512 byte aligned. Aligning each line to 512 bytes guarantees
 183          * that regardless of the compression limit we choose later.
 184          */
 185         if (DISPLAY_VER(i915) >= 9)
 186                 return max(ALIGN(stride, 512), skl_fbc_min_cfb_stride(plane_state));
 187         else
 188                 return stride;
 189 }
 190
 191 static unsigned int intel_fbc_cfb_size(const struct intel_plane_state *plane_state)
 192 {
 193         struct drm_i915_private *i915 = to_i915(plane_state->uapi.plane->dev);
 194         int lines = drm_rect_height(&plane_state->uapi.src) >> 16;
 195
 196         if (DISPLAY_VER(i915) == 7)
 197                 lines = min(lines, 2048);
 198         else if (DISPLAY_VER(i915) >= 8)
 199                 lines = min(lines, 2560);
 200
 201         return lines * intel_fbc_cfb_stride(plane_state);
 202 }
 203
 204 static u16 intel_fbc_override_cfb_stride(const struct intel_plane_state *plane_state)
 205 {
 206         struct drm_i915_private *i915 = to_i915(plane_state->uapi.plane->dev);
 207         unsigned int stride_aligned = intel_fbc_cfb_stride(plane_state);
 208         unsigned int stride = _intel_fbc_cfb_stride(plane_state);
 209         const struct drm_framebuffer *fb = plane_state->hw.fb;
 210
 211         /*
 212          * Override stride in 64 byte units per 4 line segment.
 213          *
 214          * Gen9 hw miscalculates cfb stride for linear as
 215          * PLANE_STRIDE*512 instead of PLANE_STRIDE*64, so
 216          * we always need to use the override there.
 217          */
 218         if (stride != stride_aligned ||
 219             (DISPLAY_VER(i915) == 9 && fb->modifier == DRM_FORMAT_MOD_LINEAR))
 220                 return stride_aligned * 4 / 64;
 221
 222         return 0;
 223 }
 224
 225 static u32 i8xx_fbc_ctl(struct intel_fbc *fbc)
 226 {
 227         const struct intel_fbc_state *fbc_state = &fbc->state;
 228         struct drm_i915_private *i915 = fbc->i915;
 229         unsigned int cfb_stride;
 230         u32 fbc_ctl;
 231
 232         cfb_stride = fbc_state->cfb_stride / fbc->limit;
 233
 234         /* FBC_CTL wants 32B or 64B units */
 235         if (DISPLAY_VER(i915) == 2)
 236                 cfb_stride = (cfb_stride / 32) - 1;
 237         else
 238                 cfb_stride = (cfb_stride / 64) - 1;
 239
 240         fbc_ctl = FBC_CTL_PERIODIC |
 241                 FBC_CTL_INTERVAL(fbc_state->interval) |
 242                 FBC_CTL_STRIDE(cfb_stride);
 243
 244         if (IS_I945GM(i915))
 245                 fbc_ctl |= FBC_CTL_C3_IDLE; /* 945 needs special SR handling */
 246
 247         if (fbc_state->fence_id >= 0)
 248                 fbc_ctl |= FBC_CTL_FENCENO(fbc_state->fence_id);
 249
 250         return fbc_ctl;
 251 }
 252
 253 static u32 i965_fbc_ctl2(struct intel_fbc *fbc)
 254 {
 255         const struct intel_fbc_state *fbc_state = &fbc->state;
 256         u32 fbc_ctl2;
 257
 258         fbc_ctl2 = FBC_CTL_FENCE_DBL | FBC_CTL_IDLE_IMM |
 259                 FBC_CTL_PLANE(fbc_state->plane->i9xx_plane);
 260
 261         if (fbc_state->fence_id >= 0)
 262                 fbc_ctl2 |= FBC_CTL_CPU_FENCE_EN;
 263
 264         return fbc_ctl2;
 265 }
 266
 267 static void i8xx_fbc_deactivate(struct intel_fbc *fbc)
 268 {
 269         struct drm_i915_private *i915 = fbc->i915;
 270         u32 fbc_ctl;
 271
 272         /* Disable compression */
 273         fbc_ctl = intel_de_read(i915, FBC_CONTROL);
 274         if ((fbc_ctl & FBC_CTL_EN) == 0)
 275                 return;
 276
 277         fbc_ctl &= ~FBC_CTL_EN;
 278         intel_de_write(i915, FBC_CONTROL, fbc_ctl);
 279
 280         /* Wait for compressing bit to clear */
 281         if (intel_de_wait_for_clear(i915, FBC_STATUS,
 282                                     FBC_STAT_COMPRESSING, 10)) {
 283                 drm_dbg_kms(&i915->drm, "FBC idle timed out\n");
 284                 return;
 285         }
 286 }
 287
 288 static void i8xx_fbc_activate(struct intel_fbc *fbc)
 289 {
 290         const struct intel_fbc_state *fbc_state = &fbc->state;
 291         struct drm_i915_private *i915 = fbc->i915;
 292         int i;
 293
 294         /* Clear old tags */
 295         for (i = 0; i < (FBC_LL_SIZE / 32) + 1; i++)
 296                 intel_de_write(i915, FBC_TAG(i), 0);
 297
 298         if (DISPLAY_VER(i915) == 4) {
 299                 intel_de_write(i915, FBC_CONTROL2,
 300                                i965_fbc_ctl2(fbc));
 301                 intel_de_write(i915, FBC_FENCE_OFF,
 302                                fbc_state->fence_y_offset);
 303         }
 304
 305         intel_de_write(i915, FBC_CONTROL,
 306                        FBC_CTL_EN | i8xx_fbc_ctl(fbc));
 307 }
 308
 309 static bool i8xx_fbc_is_active(struct intel_fbc *fbc)
 310 {
 311         return intel_de_read(fbc->i915, FBC_CONTROL) & FBC_CTL_EN;
 312 }
 313
 314 static bool i8xx_fbc_is_compressing(struct intel_fbc *fbc)
 315 {
 316         return intel_de_read(fbc->i915, FBC_STATUS) &
 317                 (FBC_STAT_COMPRESSING | FBC_STAT_COMPRESSED);
 318 }
 319
 320 static void i8xx_fbc_nuke(struct intel_fbc *fbc)
 321 {
 322         struct intel_fbc_state *fbc_state = &fbc->state;
 323         enum i9xx_plane_id i9xx_plane = fbc_state->plane->i9xx_plane;
 324         struct drm_i915_private *dev_priv = fbc->i915;
 325
 326         intel_de_write_fw(dev_priv, DSPADDR(i9xx_plane),
 327                           intel_de_read_fw(dev_priv, DSPADDR(i9xx_plane)));
 328 }
 329
 330 static void i8xx_fbc_program_cfb(struct intel_fbc *fbc)
 331 {
 332         struct drm_i915_private *i915 = fbc->i915;
 333
 334         GEM_BUG_ON(range_overflows_end_t(u64, i915->dsm.stolen.start,
 335                                          fbc->compressed_fb.start, U32_MAX));
 336         GEM_BUG_ON(range_overflows_end_t(u64, i915->dsm.stolen.start,
 337                                          fbc->compressed_llb.start, U32_MAX));
 338
 339         intel_de_write(i915, FBC_CFB_BASE,
 340                        i915->dsm.stolen.start + fbc->compressed_fb.start);
 341         intel_de_write(i915, FBC_LL_BASE,
 342                        i915->dsm.stolen.start + fbc->compressed_llb.start);
 343 }
 344
 345 static const struct intel_fbc_funcs i8xx_fbc_funcs = {
 346         .activate = i8xx_fbc_activate,
 347         .deactivate = i8xx_fbc_deactivate,
 348         .is_active = i8xx_fbc_is_active,
 349         .is_compressing = i8xx_fbc_is_compressing,
 350         .nuke = i8xx_fbc_nuke,
 351         .program_cfb = i8xx_fbc_program_cfb,
 352 };
 353
 354 static void i965_fbc_nuke(struct intel_fbc *fbc)
 355 {
 356         struct intel_fbc_state *fbc_state = &fbc->state;
 357         enum i9xx_plane_id i9xx_plane = fbc_state->plane->i9xx_plane;
 358         struct drm_i915_private *dev_priv = fbc->i915;
 359
 360         intel_de_write_fw(dev_priv, DSPSURF(i9xx_plane),
 361                           intel_de_read_fw(dev_priv, DSPSURF(i9xx_plane)));
 362 }
 363
 364 static const struct intel_fbc_funcs i965_fbc_funcs = {
 365         .activate = i8xx_fbc_activate,
 366         .deactivate = i8xx_fbc_deactivate,
 367         .is_active = i8xx_fbc_is_active,
 368         .is_compressing = i8xx_fbc_is_compressing,
 369         .nuke = i965_fbc_nuke,
 370         .program_cfb = i8xx_fbc_program_cfb,
 371 };
 372
 373 static u32 g4x_dpfc_ctl_limit(struct intel_fbc *fbc)
 374 {
 375         switch (fbc->limit) {
 376         default:
 377                 MISSING_CASE(fbc->limit);
 378                 fallthrough;
 379         case 1:
 380                 return DPFC_CTL_LIMIT_1X;
 381         case 2:
 382                 return DPFC_CTL_LIMIT_2X;
 383         case 4:
 384                 return DPFC_CTL_LIMIT_4X;
 385         }
 386 }
 387
 388 static u32 g4x_dpfc_ctl(struct intel_fbc *fbc)
 389 {
 390         const struct intel_fbc_state *fbc_state = &fbc->state;
 391         struct drm_i915_private *i915 = fbc->i915;
 392         u32 dpfc_ctl;
 393
 394         dpfc_ctl = g4x_dpfc_ctl_limit(fbc) |
 395                 DPFC_CTL_PLANE_G4X(fbc_state->plane->i9xx_plane);
 396
 397         if (IS_G4X(i915))
 398                 dpfc_ctl |= DPFC_CTL_SR_EN;
 399
 400         if (fbc_state->fence_id >= 0) {
 401                 dpfc_ctl |= DPFC_CTL_FENCE_EN_G4X;
 402
 403                 if (DISPLAY_VER(i915) < 6)
 404                         dpfc_ctl |= DPFC_CTL_FENCENO(fbc_state->fence_id);
 405         }
 406
 407         return dpfc_ctl;
 408 }
 409
 410 static void g4x_fbc_activate(struct intel_fbc *fbc)
 411 {
 412         const struct intel_fbc_state *fbc_state = &fbc->state;
 413         struct drm_i915_private *i915 = fbc->i915;
 414
 415         intel_de_write(i915, DPFC_FENCE_YOFF,
 416                        fbc_state->fence_y_offset);
 417
 418         intel_de_write(i915, DPFC_CONTROL,
 419                        DPFC_CTL_EN | g4x_dpfc_ctl(fbc));
 420 }
 421
 422 static void g4x_fbc_deactivate(struct intel_fbc *fbc)
 423 {
 424         struct drm_i915_private *i915 = fbc->i915;
 425         u32 dpfc_ctl;
 426
 427         /* Disable compression */
 428         dpfc_ctl = intel_de_read(i915, DPFC_CONTROL);
 429         if (dpfc_ctl & DPFC_CTL_EN) {
 430                 dpfc_ctl &= ~DPFC_CTL_EN;
 431                 intel_de_write(i915, DPFC_CONTROL, dpfc_ctl);
 432         }
 433 }
 434
 435 static bool g4x_fbc_is_active(struct intel_fbc *fbc)
 436 {
 437         return intel_de_read(fbc->i915, DPFC_CONTROL) & DPFC_CTL_EN;
 438 }
 439
 440 static bool g4x_fbc_is_compressing(struct intel_fbc *fbc)
 441 {
 442         return intel_de_read(fbc->i915, DPFC_STATUS) & DPFC_COMP_SEG_MASK;
 443 }
 444
 445 static void g4x_fbc_program_cfb(struct intel_fbc *fbc)
 446 {
 447         struct drm_i915_private *i915 = fbc->i915;
 448
 449         intel_de_write(i915, DPFC_CB_BASE, fbc->compressed_fb.start);
 450 }
 451
 452 static const struct intel_fbc_funcs g4x_fbc_funcs = {
 453         .activate = g4x_fbc_activate,
 454         .deactivate = g4x_fbc_deactivate,
 455         .is_active = g4x_fbc_is_active,
 456         .is_compressing = g4x_fbc_is_compressing,
 457         .nuke = i965_fbc_nuke,
 458         .program_cfb = g4x_fbc_program_cfb,
 459 };
 460
 461 static void ilk_fbc_activate(struct intel_fbc *fbc)
 462 {
 463         struct intel_fbc_state *fbc_state = &fbc->state;
 464         struct drm_i915_private *i915 = fbc->i915;
 465
 466         intel_de_write(i915, ILK_DPFC_FENCE_YOFF(fbc->id),
 467                        fbc_state->fence_y_offset);
 468
 469         intel_de_write(i915, ILK_DPFC_CONTROL(fbc->id),
 470                        DPFC_CTL_EN | g4x_dpfc_ctl(fbc));
 471 }
 472
 473 static void ilk_fbc_deactivate(struct intel_fbc *fbc)
 474 {
 475         struct drm_i915_private *i915 = fbc->i915;
 476         u32 dpfc_ctl;
 477
 478         /* Disable compression */
 479         dpfc_ctl = intel_de_read(i915, ILK_DPFC_CONTROL(fbc->id));
 480         if (dpfc_ctl & DPFC_CTL_EN) {
 481                 dpfc_ctl &= ~DPFC_CTL_EN;
 482                 intel_de_write(i915, ILK_DPFC_CONTROL(fbc->id), dpfc_ctl);
 483         }
 484 }
 485
 486 static bool ilk_fbc_is_active(struct intel_fbc *fbc)
 487 {
 488         return intel_de_read(fbc->i915, ILK_DPFC_CONTROL(fbc->id)) & DPFC_CTL_EN;
 489 }
 490
 491 static bool ilk_fbc_is_compressing(struct intel_fbc *fbc)
 492 {
 493         return intel_de_read(fbc->i915, ILK_DPFC_STATUS(fbc->id)) & DPFC_COMP_SEG_MASK;
 494 }
 495
 496 static void ilk_fbc_program_cfb(struct intel_fbc *fbc)
 497 {
 498         struct drm_i915_private *i915 = fbc->i915;
 499
 500         intel_de_write(i915, ILK_DPFC_CB_BASE(fbc->id), fbc->compressed_fb.start);
 501 }
 502
 503 static const struct intel_fbc_funcs ilk_fbc_funcs = {
 504         .activate = ilk_fbc_activate,
 505         .deactivate = ilk_fbc_deactivate,
 506         .is_active = ilk_fbc_is_active,
 507         .is_compressing = ilk_fbc_is_compressing,
 508         .nuke = i965_fbc_nuke,
 509         .program_cfb = ilk_fbc_program_cfb,
 510 };
 511
 512 static void snb_fbc_program_fence(struct intel_fbc *fbc)
 513 {
 514         const struct intel_fbc_state *fbc_state = &fbc->state;
 515         struct drm_i915_private *i915 = fbc->i915;
 516         u32 ctl = 0;
 517
 518         if (fbc_state->fence_id >= 0)
 519                 ctl = SNB_DPFC_FENCE_EN | SNB_DPFC_FENCENO(fbc_state->fence_id);
 520
 521         intel_de_write(i915, SNB_DPFC_CTL_SA, ctl);
 522         intel_de_write(i915, SNB_DPFC_CPU_FENCE_OFFSET, fbc_state->fence_y_offset);
 523 }
 524
 525 static void snb_fbc_activate(struct intel_fbc *fbc)
 526 {
 527         snb_fbc_program_fence(fbc);
 528
 529         ilk_fbc_activate(fbc);
 530 }
 531
 532 static void snb_fbc_nuke(struct intel_fbc *fbc)
 533 {
 534         struct drm_i915_private *i915 = fbc->i915;
 535
 536         intel_de_write(i915, MSG_FBC_REND_STATE(fbc->id), FBC_REND_NUKE);
 537         intel_de_posting_read(i915, MSG_FBC_REND_STATE(fbc->id));
 538 }
 539
 540 static const struct intel_fbc_funcs snb_fbc_funcs = {
 541         .activate = snb_fbc_activate,
 542         .deactivate = ilk_fbc_deactivate,
 543         .is_active = ilk_fbc_is_active,
 544         .is_compressing = ilk_fbc_is_compressing,
 545         .nuke = snb_fbc_nuke,
 546         .program_cfb = ilk_fbc_program_cfb,
 547 };
 548
 549 static void glk_fbc_program_cfb_stride(struct intel_fbc *fbc)
 550 {
 551         const struct intel_fbc_state *fbc_state = &fbc->state;
 552         struct drm_i915_private *i915 = fbc->i915;
 553         u32 val = 0;
 554
 555         if (fbc_state->override_cfb_stride)
 556                 val |= FBC_STRIDE_OVERRIDE |
 557                         FBC_STRIDE(fbc_state->override_cfb_stride / fbc->limit);
 558
 559         intel_de_write(i915, GLK_FBC_STRIDE(fbc->id), val);
 560 }
 561
 562 static void skl_fbc_program_cfb_stride(struct intel_fbc *fbc)
 563 {
 564         const struct intel_fbc_state *fbc_state = &fbc->state;
 565         struct drm_i915_private *i915 = fbc->i915;
 566         u32 val = 0;
 567
 568         /* Display WA #0529: skl, kbl, bxt. */
 569         if (fbc_state->override_cfb_stride)
 570                 val |= CHICKEN_FBC_STRIDE_OVERRIDE |
 571                         CHICKEN_FBC_STRIDE(fbc_state->override_cfb_stride / fbc->limit);
 572
 573         intel_de_rmw(i915, CHICKEN_MISC_4,
 574                      CHICKEN_FBC_STRIDE_OVERRIDE |
 575                      CHICKEN_FBC_STRIDE_MASK, val);
 576 }
 577
 578 static u32 ivb_dpfc_ctl(struct intel_fbc *fbc)
 579 {
 580         const struct intel_fbc_state *fbc_state = &fbc->state;
 581         struct drm_i915_private *i915 = fbc->i915;
 582         u32 dpfc_ctl;
 583
 584         dpfc_ctl = g4x_dpfc_ctl_limit(fbc);
 585
 586         if (IS_IVYBRIDGE(i915))
 587                 dpfc_ctl |= DPFC_CTL_PLANE_IVB(fbc_state->plane->i9xx_plane);
 588
 589         if (fbc_state->fence_id >= 0)
 590                 dpfc_ctl |= DPFC_CTL_FENCE_EN_IVB;
 591
 592         if (fbc->false_color)
 593                 dpfc_ctl |= DPFC_CTL_FALSE_COLOR;
 594
 595         return dpfc_ctl;
 596 }
 597
 598 static void ivb_fbc_activate(struct intel_fbc *fbc)
 599 {
 600         struct drm_i915_private *i915 = fbc->i915;
 601
 602         if (DISPLAY_VER(i915) >= 10)
 603                 glk_fbc_program_cfb_stride(fbc);
 604         else if (DISPLAY_VER(i915) == 9)
 605                 skl_fbc_program_cfb_stride(fbc);
 606
 607         if (to_gt(i915)->ggtt->num_fences)
 608                 snb_fbc_program_fence(fbc);
 609
 610         intel_de_write(i915, ILK_DPFC_CONTROL(fbc->id),
 611                        DPFC_CTL_EN | ivb_dpfc_ctl(fbc));
 612 }
 613
 614 static bool ivb_fbc_is_compressing(struct intel_fbc *fbc)
 615 {
 616         return intel_de_read(fbc->i915, ILK_DPFC_STATUS2(fbc->id)) & DPFC_COMP_SEG_MASK_IVB;
 617 }
 618
 619 static void ivb_fbc_set_false_color(struct intel_fbc *fbc,
 620                                     bool enable)
 621 {
 622         intel_de_rmw(fbc->i915, ILK_DPFC_CONTROL(fbc->id),
 623                      DPFC_CTL_FALSE_COLOR, enable ? DPFC_CTL_FALSE_COLOR : 0);
 624 }
 625
 626 static const struct intel_fbc_funcs ivb_fbc_funcs = {
 627         .activate = ivb_fbc_activate,
 628         .deactivate = ilk_fbc_deactivate,
 629         .is_active = ilk_fbc_is_active,
 630         .is_compressing = ivb_fbc_is_compressing,
 631         .nuke = snb_fbc_nuke,
 632         .program_cfb = ilk_fbc_program_cfb,
 633         .set_false_color = ivb_fbc_set_false_color,
 634 };
 635
 636 static bool intel_fbc_hw_is_active(struct intel_fbc *fbc)
 637 {
 638         return fbc->funcs->is_active(fbc);
 639 }
 640
 641 static void intel_fbc_hw_activate(struct intel_fbc *fbc)
 642 {
 643         trace_intel_fbc_activate(fbc->state.plane);
 644
 645         fbc->active = true;
 646         fbc->activated = true;
 647
 648         fbc->funcs->activate(fbc);
 649 }
 650
 651 static void intel_fbc_hw_deactivate(struct intel_fbc *fbc)
 652 {
 653         trace_intel_fbc_deactivate(fbc->state.plane);
 654
 655         fbc->active = false;
 656
 657         fbc->funcs->deactivate(fbc);
 658 }
 659
 660 static bool intel_fbc_is_compressing(struct intel_fbc *fbc)
 661 {
 662         return fbc->funcs->is_compressing(fbc);
 663 }
 664
 665 static void intel_fbc_nuke(struct intel_fbc *fbc)
 666 {
 667         struct drm_i915_private *i915 = fbc->i915;
 668
 669         lockdep_assert_held(&fbc->lock);
 670         drm_WARN_ON(&i915->drm, fbc->flip_pending);
 671
 672         trace_intel_fbc_nuke(fbc->state.plane);
 673
 674         fbc->funcs->nuke(fbc);
 675 }
 676
 677 static void intel_fbc_activate(struct intel_fbc *fbc)
 678 {
 679         lockdep_assert_held(&fbc->lock);
 680
 681         intel_fbc_hw_activate(fbc);
 682         intel_fbc_nuke(fbc);
 683
 684         fbc->no_fbc_reason = NULL;
 685 }
 686
 687 static void intel_fbc_deactivate(struct intel_fbc *fbc, const char *reason)
 688 {
 689         lockdep_assert_held(&fbc->lock);
 690
 691         if (fbc->active)
 692                 intel_fbc_hw_deactivate(fbc);
 693
 694         fbc->no_fbc_reason = reason;
 695 }
 696
 697 static u64 intel_fbc_cfb_base_max(struct drm_i915_private *i915)
 698 {
 699         if (DISPLAY_VER(i915) >= 5 || IS_G4X(i915))
 700                 return BIT_ULL(28);
 701         else
 702                 return BIT_ULL(32);
 703 }
 704
 705 static u64 intel_fbc_stolen_end(struct drm_i915_private *i915)
 706 {
 707         u64 end;
 708
 709         /* The FBC hardware for BDW/SKL doesn't have access to the stolen
 710          * reserved range size, so it always assumes the maximum (8mb) is used.
 711          * If we enable FBC using a CFB on that memory range we'll get FIFO
 712          * underruns, even if that range is not reserved by the BIOS. */
 713         if (IS_BROADWELL(i915) ||
 714             (DISPLAY_VER(i915) == 9 && !IS_BROXTON(i915)))
 715                 end = resource_size(&i915->dsm.stolen) - 8 * 1024 * 1024;
 716         else
 717                 end = U64_MAX;
 718
 719         return min(end, intel_fbc_cfb_base_max(i915));
 720 }
 721
 722 static int intel_fbc_min_limit(const struct intel_plane_state *plane_state)
 723 {
 724         return plane_state->hw.fb->format->cpp[0] == 2 ? 2 : 1;
 725 }
 726
 727 static int intel_fbc_max_limit(struct drm_i915_private *i915)
 728 {
 729         /* WaFbcOnly1to1Ratio:ctg */
 730         if (IS_G4X(i915))
 731                 return 1;
 732
 733         /*
 734          * FBC2 can only do 1:1, 1:2, 1:4, we limit
 735          * FBC1 to the same out of convenience.
 736          */
 737         return 4;
 738 }
 739
 740 static int find_compression_limit(struct intel_fbc *fbc,
 741                                   unsigned int size, int min_limit)
 742 {
 743         struct drm_i915_private *i915 = fbc->i915;
 744         u64 end = intel_fbc_stolen_end(i915);
 745         int ret, limit = min_limit;
 746
 747         size /= limit;
 748
 749         /* Try to over-allocate to reduce reallocations and fragmentation. */
 750         ret = i915_gem_stolen_insert_node_in_range(i915, &fbc->compressed_fb,
 751                                                    size <<= 1, 4096, 0, end);
 752         if (ret == 0)
 753                 return limit;
 754
 755         for (; limit <= intel_fbc_max_limit(i915); limit <<= 1) {
 756                 ret = i915_gem_stolen_insert_node_in_range(i915, &fbc->compressed_fb,
 757                                                            size >>= 1, 4096, 0, end);
 758                 if (ret == 0)
 759                         return limit;
 760         }
 761
 762         return 0;
 763 }
 764
 765 static int intel_fbc_alloc_cfb(struct intel_fbc *fbc,
 766                                unsigned int size, int min_limit)
 767 {
 768         struct drm_i915_private *i915 = fbc->i915;
 769         int ret;
 770
 771         drm_WARN_ON(&i915->drm,
 772                     drm_mm_node_allocated(&fbc->compressed_fb));
 773         drm_WARN_ON(&i915->drm,
 774                     drm_mm_node_allocated(&fbc->compressed_llb));
 775
 776         if (DISPLAY_VER(i915) < 5 && !IS_G4X(i915)) {
 777                 ret = i915_gem_stolen_insert_node(i915, &fbc->compressed_llb,
 778                                                   4096, 4096);
 779                 if (ret)
 780                         goto err;
 781         }
 782
 783         ret = find_compression_limit(fbc, size, min_limit);
 784         if (!ret)
 785                 goto err_llb;
 786         else if (ret > min_limit)
 787                 drm_info_once(&i915->drm,
 788                               "Reducing the compressed framebuffer size. This may lead to less power savings than a non-reduced-size. Try to increase stolen memory size if available in BIOS.\n");
 789
 790         fbc->limit = ret;
 791
 792         drm_dbg_kms(&i915->drm,
 793                     "reserved %llu bytes of contiguous stolen space for FBC, limit: %d\n",
 794                     fbc->compressed_fb.size, fbc->limit);
 795
 796         return 0;
 797
 798 err_llb:
 799         if (drm_mm_node_allocated(&fbc->compressed_llb))
 800                 i915_gem_stolen_remove_node(i915, &fbc->compressed_llb);
 801 err:
 802         if (drm_mm_initialized(&i915->mm.stolen))
 803                 drm_info_once(&i915->drm, "not enough stolen space for compressed buffer (need %d more bytes), disabling. Hint: you may be able to increase stolen memory size in the BIOS to avoid this.\n", size);
 804         return -ENOSPC;
 805 }
 806
 807 static void intel_fbc_program_cfb(struct intel_fbc *fbc)
 808 {
 809         fbc->funcs->program_cfb(fbc);
 810 }
 811
 812 static void intel_fbc_program_workarounds(struct intel_fbc *fbc)
 813 {
 814         /* Wa_22014263786:icl,jsl,tgl,dg1,rkl,adls,adlp,mtl */
 815         if (DISPLAY_VER(fbc->i915) >= 11 && !IS_DG2(fbc->i915))
 816                 intel_de_rmw(fbc->i915, ILK_DPFC_CHICKEN(fbc->id), 0,
 817                              DPFC_CHICKEN_FORCE_SLB_INVALIDATION);
 818 }
 819
 820 static void __intel_fbc_cleanup_cfb(struct intel_fbc *fbc)
 821 {
 822         struct drm_i915_private *i915 = fbc->i915;
 823
 824         if (WARN_ON(intel_fbc_hw_is_active(fbc)))
 825                 return;
 826
 827         if (drm_mm_node_allocated(&fbc->compressed_llb))
 828                 i915_gem_stolen_remove_node(i915, &fbc->compressed_llb);
 829         if (drm_mm_node_allocated(&fbc->compressed_fb))
 830                 i915_gem_stolen_remove_node(i915, &fbc->compressed_fb);
 831 }
 832
 833 void intel_fbc_cleanup(struct drm_i915_private *i915)
 834 {
 835         struct intel_fbc *fbc;
 836         enum intel_fbc_id fbc_id;
 837
 838         for_each_intel_fbc(i915, fbc, fbc_id) {
 839                 mutex_lock(&fbc->lock);
 840                 __intel_fbc_cleanup_cfb(fbc);
 841                 mutex_unlock(&fbc->lock);
 842
 843                 kfree(fbc);
 844         }
 845 }
 846
 847 static bool stride_is_valid(const struct intel_plane_state *plane_state)
 848 {
 849         struct drm_i915_private *i915 = to_i915(plane_state->uapi.plane->dev);
 850         const struct drm_framebuffer *fb = plane_state->hw.fb;
 851         unsigned int stride = intel_fbc_plane_stride(plane_state) *
 852                 fb->format->cpp[0];
 853
 854         /* This should have been caught earlier. */
 855         if (drm_WARN_ON_ONCE(&i915->drm, (stride & (64 - 1)) != 0))
 856                 return false;
 857
 858         /* Below are the additional FBC restrictions. */
 859         if (stride < 512)
 860                 return false;
 861
 862         if (DISPLAY_VER(i915) == 2 || DISPLAY_VER(i915) == 3)
 863                 return stride == 4096 || stride == 8192;
 864
 865         if (DISPLAY_VER(i915) == 4 && !IS_G4X(i915) && stride < 2048)
 866                 return false;
 867
 868         /* Display WA #1105: skl,bxt,kbl,cfl,glk */
 869         if ((DISPLAY_VER(i915) == 9 || IS_GEMINILAKE(i915)) &&
 870             fb->modifier == DRM_FORMAT_MOD_LINEAR && stride & 511)
 871                 return false;
 872
 873         if (stride > 16384)
 874                 return false;
 875
 876         return true;
 877 }
 878
 879 static bool pixel_format_is_valid(const struct intel_plane_state *plane_state)
 880 {
 881         struct drm_i915_private *i915 = to_i915(plane_state->uapi.plane->dev);
 882         const struct drm_framebuffer *fb = plane_state->hw.fb;
 883
 884         switch (fb->format->format) {
 885         case DRM_FORMAT_XRGB8888:
 886         case DRM_FORMAT_XBGR8888:
 887                 return true;
 888         case DRM_FORMAT_XRGB1555:
 889         case DRM_FORMAT_RGB565:
 890                 /* 16bpp not supported on gen2 */
 891                 if (DISPLAY_VER(i915) == 2)
 892                         return false;
 893                 /* WaFbcOnly1to1Ratio:ctg */
 894                 if (IS_G4X(i915))
 895                         return false;
 896                 return true;
 897         default:
 898                 return false;
 899         }
 900 }
 901
 902 static bool rotation_is_valid(const struct intel_plane_state *plane_state)
 903 {
 904         struct drm_i915_private *i915 = to_i915(plane_state->uapi.plane->dev);
 905         const struct drm_framebuffer *fb = plane_state->hw.fb;
 906         unsigned int rotation = plane_state->hw.rotation;
 907
 908         if (DISPLAY_VER(i915) >= 9 && fb->format->format == DRM_FORMAT_RGB565 &&
 909             drm_rotation_90_or_270(rotation))
 910                 return false;
 911         else if (DISPLAY_VER(i915) <= 4 && !IS_G4X(i915) &&
 912                  rotation != DRM_MODE_ROTATE_0)
 913                 return false;
 914
 915         return true;
 916 }
 917
 918 /*
 919  * For some reason, the hardware tracking starts looking at whatever we
 920  * programmed as the display plane base address register. It does not look at
 921  * the X and Y offset registers. That's why we include the src x/y offsets
 922  * instead of just looking at the plane size.
 923  */
 924 static bool intel_fbc_hw_tracking_covers_screen(const struct intel_plane_state *plane_state)
 925 {
 926         struct drm_i915_private *i915 = to_i915(plane_state->uapi.plane->dev);
 927         unsigned int effective_w, effective_h, max_w, max_h;
 928
 929         if (DISPLAY_VER(i915) >= 10) {
 930                 max_w = 5120;
 931                 max_h = 4096;
 932         } else if (DISPLAY_VER(i915) >= 8 || IS_HASWELL(i915)) {
 933                 max_w = 4096;
 934                 max_h = 4096;
 935         } else if (IS_G4X(i915) || DISPLAY_VER(i915) >= 5) {
 936                 max_w = 4096;
 937                 max_h = 2048;
 938         } else {
 939                 max_w = 2048;
 940                 max_h = 1536;
 941         }
 942
 943         effective_w = plane_state->view.color_plane[0].x +
 944                 (drm_rect_width(&plane_state->uapi.src) >> 16);
 945         effective_h = plane_state->view.color_plane[0].y +
 946                 (drm_rect_height(&plane_state->uapi.src) >> 16);
 947
 948         return effective_w <= max_w && effective_h <= max_h;
 949 }
 950
 951 static bool tiling_is_valid(const struct intel_plane_state *plane_state)
 952 {
 953         struct drm_i915_private *i915 = to_i915(plane_state->uapi.plane->dev);
 954         const struct drm_framebuffer *fb = plane_state->hw.fb;
 955
 956         switch (fb->modifier) {
 957         case DRM_FORMAT_MOD_LINEAR:
 958         case I915_FORMAT_MOD_Y_TILED:
 959         case I915_FORMAT_MOD_Yf_TILED:
 960                 return DISPLAY_VER(i915) >= 9;
 961         case I915_FORMAT_MOD_4_TILED:
 962         case I915_FORMAT_MOD_X_TILED:
 963                 return true;
 964         default:
 965                 return false;
 966         }
 967 }
 968
 969 static void intel_fbc_update_state(struct intel_atomic_state *state,
 970                                    struct intel_crtc *crtc,
 971                                    struct intel_plane *plane)
 972 {
 973         struct drm_i915_private *i915 = to_i915(state->base.dev);
 974         const struct intel_crtc_state *crtc_state =
 975                 intel_atomic_get_new_crtc_state(state, crtc);
 976         const struct intel_plane_state *plane_state =
 977                 intel_atomic_get_new_plane_state(state, plane);
 978         struct intel_fbc *fbc = plane->fbc;
 979         struct intel_fbc_state *fbc_state = &fbc->state;
 980
 981         WARN_ON(plane_state->no_fbc_reason);
 982         WARN_ON(fbc_state->plane && fbc_state->plane != plane);
 983
 984         fbc_state->plane = plane;
 985
 986         /* FBC1 compression interval: arbitrary choice of 1 second */
 987         fbc_state->interval = drm_mode_vrefresh(&crtc_state->hw.adjusted_mode);
 988
 989         fbc_state->fence_y_offset = intel_plane_fence_y_offset(plane_state);
 990
 991         drm_WARN_ON(&i915->drm, plane_state->flags & PLANE_HAS_FENCE &&
 992                     !plane_state->ggtt_vma->fence);
 993
 994         if (plane_state->flags & PLANE_HAS_FENCE &&
 995             plane_state->ggtt_vma->fence)
 996                 fbc_state->fence_id = plane_state->ggtt_vma->fence->id;
 997         else
 998                 fbc_state->fence_id = -1;
 999
1000         fbc_state->cfb_stride = intel_fbc_cfb_stride(plane_state);
1001         fbc_state->cfb_size = intel_fbc_cfb_size(plane_state);
1002         fbc_state->override_cfb_stride = intel_fbc_override_cfb_stride(plane_state);
1003 }
1004
1005 static bool intel_fbc_is_fence_ok(const struct intel_plane_state *plane_state)
1006 {
1007         struct drm_i915_private *i915 = to_i915(plane_state->uapi.plane->dev);
1008
1009         /*
1010          * The use of a CPU fence is one of two ways to detect writes by the
1011          * CPU to the scanout and trigger updates to the FBC.
1012          *
1013          * The other method is by software tracking (see
1014          * intel_fbc_invalidate/flush()), it will manually notify FBC and nuke
1015          * the current compressed buffer and recompress it.
1016          *
1017          * Note that is possible for a tiled surface to be unmappable (and
1018          * so have no fence associated with it) due to aperture constraints
1019          * at the time of pinning.
1020          */
1021         return DISPLAY_VER(i915) >= 9 ||
1022                 (plane_state->flags & PLANE_HAS_FENCE &&
1023                  plane_state->ggtt_vma->fence);
1024 }
1025
1026 static bool intel_fbc_is_cfb_ok(const struct intel_plane_state *plane_state)
1027 {
1028         struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);
1029         struct intel_fbc *fbc = plane->fbc;
1030
1031         return intel_fbc_min_limit(plane_state) <= fbc->limit &&
1032                 intel_fbc_cfb_size(plane_state) <= fbc->compressed_fb.size * fbc->limit;
1033 }
1034
1035 static bool intel_fbc_is_ok(const struct intel_plane_state *plane_state)
1036 {
1037         return !plane_state->no_fbc_reason &&
1038                 intel_fbc_is_fence_ok(plane_state) &&
1039                 intel_fbc_is_cfb_ok(plane_state);
1040 }
1041
1042 static int intel_fbc_check_plane(struct intel_atomic_state *state,
1043                                  struct intel_plane *plane)
1044 {
1045         struct drm_i915_private *i915 = to_i915(state->base.dev);
1046         struct intel_plane_state *plane_state =
1047                 intel_atomic_get_new_plane_state(state, plane);
1048         const struct drm_framebuffer *fb = plane_state->hw.fb;
1049         struct intel_crtc *crtc = to_intel_crtc(plane_state->hw.crtc);
1050         const struct intel_crtc_state *crtc_state;
1051         struct intel_fbc *fbc = plane->fbc;
1052
1053         if (!fbc)
1054                 return 0;
1055
1056         if (intel_vgpu_active(i915)) {
1057                 plane_state->no_fbc_reason = "VGPU active";
1058                 return 0;
1059         }
1060
1061         if (!i915->params.enable_fbc) {
1062                 plane_state->no_fbc_reason = "disabled per module param or by default";
1063                 return 0;
1064         }
1065
1066         if (!plane_state->uapi.visible) {
1067                 plane_state->no_fbc_reason = "plane not visible";
1068                 return 0;
1069         }
1070
1071         crtc_state = intel_atomic_get_new_crtc_state(state, crtc);
1072
1073         if (crtc_state->hw.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) {
1074                 plane_state->no_fbc_reason = "interlaced mode not supported";
1075                 return 0;
1076         }
1077
1078         if (crtc_state->double_wide) {
1079                 plane_state->no_fbc_reason = "double wide pipe not supported";
1080                 return 0;
1081         }
1082
1083         /*
1084          * Display 12+ is not supporting FBC with PSR2.
1085          * Recommendation is to keep this combination disabled
1086          * Bspec: 50422 HSD: 14010260002
1087          */
1088         if (DISPLAY_VER(i915) >= 12 && crtc_state->has_psr2) {
1089                 plane_state->no_fbc_reason = "PSR2 enabled";
1090                 return 0;
1091         }
1092
1093         /* Wa_14016291713 */
1094         if ((IS_DISPLAY_VER(i915, 12, 13) ||
1095              IS_MTL_DISPLAY_STEP(i915, STEP_A0, STEP_C0)) &&
1096             crtc_state->has_psr) {
1097                 plane_state->no_fbc_reason = "PSR1 enabled (Wa_14016291713)";
1098                 return 0;
1099         }
1100
1101         if (!pixel_format_is_valid(plane_state)) {
1102                 plane_state->no_fbc_reason = "pixel format not supported";
1103                 return 0;
1104         }
1105
1106         if (!tiling_is_valid(plane_state)) {
1107                 plane_state->no_fbc_reason = "tiling not supported";
1108                 return 0;
1109         }
1110
1111         if (!rotation_is_valid(plane_state)) {
1112                 plane_state->no_fbc_reason = "rotation not supported";
1113                 return 0;
1114         }
1115
1116         if (!stride_is_valid(plane_state)) {
1117                 plane_state->no_fbc_reason = "stride not supported";
1118                 return 0;
1119         }
1120
1121         if (plane_state->hw.pixel_blend_mode != DRM_MODE_BLEND_PIXEL_NONE &&
1122             fb->format->has_alpha) {
1123                 plane_state->no_fbc_reason = "per-pixel alpha not supported";
1124                 return 0;
1125         }
1126
1127         if (!intel_fbc_hw_tracking_covers_screen(plane_state)) {
1128                 plane_state->no_fbc_reason = "plane size too big";
1129                 return 0;
1130         }
1131
1132         /*
1133          * Work around a problem on GEN9+ HW, where enabling FBC on a plane
1134          * having a Y offset that isn't divisible by 4 causes FIFO underrun
1135          * and screen flicker.
1136          */
1137         if (DISPLAY_VER(i915) >= 9 &&
1138             plane_state->view.color_plane[0].y & 3) {
1139                 plane_state->no_fbc_reason = "plane start Y offset misaligned";
1140                 return 0;
1141         }
1142
1143         /* Wa_22010751166: icl, ehl, tgl, dg1, rkl */
1144         if (DISPLAY_VER(i915) >= 11 &&
1145             (plane_state->view.color_plane[0].y +
1146              (drm_rect_height(&plane_state->uapi.src) >> 16)) & 3) {
1147                 plane_state->no_fbc_reason = "plane end Y offset misaligned";
1148                 return 0;
1149         }
1150
1151         /* WaFbcExceedCdClockThreshold:hsw,bdw */
1152         if (IS_HASWELL(i915) || IS_BROADWELL(i915)) {
1153                 const struct intel_cdclk_state *cdclk_state;
1154
1155                 cdclk_state = intel_atomic_get_cdclk_state(state);
1156                 if (IS_ERR(cdclk_state))
1157                         return PTR_ERR(cdclk_state);
1158
1159                 if (crtc_state->pixel_rate >= cdclk_state->logical.cdclk * 95 / 100) {
1160                         plane_state->no_fbc_reason = "pixel rate too high";
1161                         return 0;
1162                 }
1163         }
1164
1165         plane_state->no_fbc_reason = NULL;
1166
1167         return 0;
1168 }
1169
1170
1171 static bool intel_fbc_can_flip_nuke(struct intel_atomic_state *state,
1172                                     struct intel_crtc *crtc,
1173                                     struct intel_plane *plane)
1174 {
1175         const struct intel_crtc_state *new_crtc_state =
1176                 intel_atomic_get_new_crtc_state(state, crtc);
1177         const struct intel_plane_state *old_plane_state =
1178                 intel_atomic_get_old_plane_state(state, plane);
1179         const struct intel_plane_state *new_plane_state =
1180                 intel_atomic_get_new_plane_state(state, plane);
1181         const struct drm_framebuffer *old_fb = old_plane_state->hw.fb;
1182         const struct drm_framebuffer *new_fb = new_plane_state->hw.fb;
1183
1184         if (intel_crtc_needs_modeset(new_crtc_state))
1185                 return false;
1186
1187         if (!intel_fbc_is_ok(old_plane_state) ||
1188             !intel_fbc_is_ok(new_plane_state))
1189                 return false;
1190
1191         if (old_fb->format->format != new_fb->format->format)
1192                 return false;
1193
1194         if (old_fb->modifier != new_fb->modifier)
1195                 return false;
1196
1197         if (intel_fbc_plane_stride(old_plane_state) !=
1198             intel_fbc_plane_stride(new_plane_state))
1199                 return false;
1200
1201         if (intel_fbc_cfb_stride(old_plane_state) !=
1202             intel_fbc_cfb_stride(new_plane_state))
1203                 return false;
1204
1205         if (intel_fbc_cfb_size(old_plane_state) !=
1206             intel_fbc_cfb_size(new_plane_state))
1207                 return false;
1208
1209         if (intel_fbc_override_cfb_stride(old_plane_state) !=
1210             intel_fbc_override_cfb_stride(new_plane_state))
1211                 return false;
1212
1213         return true;
1214 }
1215
1216 static bool __intel_fbc_pre_update(struct intel_atomic_state *state,
1217                                    struct intel_crtc *crtc,
1218                                    struct intel_plane *plane)
1219 {
1220         struct drm_i915_private *i915 = to_i915(state->base.dev);
1221         struct intel_fbc *fbc = plane->fbc;
1222         bool need_vblank_wait = false;
1223
1224         lockdep_assert_held(&fbc->lock);
1225
1226         fbc->flip_pending = true;
1227
1228         if (intel_fbc_can_flip_nuke(state, crtc, plane))
1229                 return need_vblank_wait;
1230
1231         intel_fbc_deactivate(fbc, "update pending");
1232
1233         /*
1234          * Display WA #1198: glk+
1235          * Need an extra vblank wait between FBC disable and most plane
1236          * updates. Bspec says this is only needed for plane disable, but
1237          * that is not true. Touching most plane registers will cause the
1238          * corruption to appear. Also SKL/derivatives do not seem to be
1239          * affected.
1240          *
1241          * TODO: could optimize this a bit by sampling the frame
1242          * counter when we disable FBC (if it was already done earlier)
1243          * and skipping the extra vblank wait before the plane update
1244          * if at least one frame has already passed.
1245          */
1246         if (fbc->activated && DISPLAY_VER(i915) >= 10)
1247                 need_vblank_wait = true;
1248         fbc->activated = false;
1249
1250         return need_vblank_wait;
1251 }
1252
1253 bool intel_fbc_pre_update(struct intel_atomic_state *state,
1254                           struct intel_crtc *crtc)
1255 {
1256         const struct intel_plane_state *plane_state;
1257         bool need_vblank_wait = false;
1258         struct intel_plane *plane;
1259         int i;
1260
1261         for_each_new_intel_plane_in_state(state, plane, plane_state, i) {
1262                 struct intel_fbc *fbc = plane->fbc;
1263
1264                 if (!fbc || plane->pipe != crtc->pipe)
1265                         continue;
1266
1267                 mutex_lock(&fbc->lock);
1268
1269                 if (fbc->state.plane == plane)
1270                         need_vblank_wait |= __intel_fbc_pre_update(state, crtc, plane);
1271
1272                 mutex_unlock(&fbc->lock);
1273         }
1274
1275         return need_vblank_wait;
1276 }
1277
1278 static void __intel_fbc_disable(struct intel_fbc *fbc)
1279 {
1280         struct drm_i915_private *i915 = fbc->i915;
1281         struct intel_plane *plane = fbc->state.plane;
1282
1283         lockdep_assert_held(&fbc->lock);
1284         drm_WARN_ON(&i915->drm, fbc->active);
1285
1286         drm_dbg_kms(&i915->drm, "Disabling FBC on [PLANE:%d:%s]\n",
1287                     plane->base.base.id, plane->base.name);
1288
1289         __intel_fbc_cleanup_cfb(fbc);
1290
1291         fbc->state.plane = NULL;
1292         fbc->flip_pending = false;
1293         fbc->busy_bits = 0;
1294 }
1295
1296 static void __intel_fbc_post_update(struct intel_fbc *fbc)
1297 {
1298         lockdep_assert_held(&fbc->lock);
1299
1300         fbc->flip_pending = false;
1301
1302         if (!fbc->busy_bits)
1303                 intel_fbc_activate(fbc);
1304         else
1305                 intel_fbc_deactivate(fbc, "frontbuffer write");
1306 }
1307
1308 void intel_fbc_post_update(struct intel_atomic_state *state,
1309                            struct intel_crtc *crtc)
1310 {
1311         const struct intel_plane_state *plane_state;
1312         struct intel_plane *plane;
1313         int i;
1314
1315         for_each_new_intel_plane_in_state(state, plane, plane_state, i) {
1316                 struct intel_fbc *fbc = plane->fbc;
1317
1318                 if (!fbc || plane->pipe != crtc->pipe)
1319                         continue;
1320
1321                 mutex_lock(&fbc->lock);
1322
1323                 if (fbc->state.plane == plane)
1324                         __intel_fbc_post_update(fbc);
1325
1326                 mutex_unlock(&fbc->lock);
1327         }
1328 }
1329
1330 static unsigned int intel_fbc_get_frontbuffer_bit(struct intel_fbc *fbc)
1331 {
1332         if (fbc->state.plane)
1333                 return fbc->state.plane->frontbuffer_bit;
1334         else
1335                 return 0;
1336 }
1337
1338 static void __intel_fbc_invalidate(struct intel_fbc *fbc,
1339                                    unsigned int frontbuffer_bits,
1340                                    enum fb_op_origin origin)
1341 {
1342         if (origin == ORIGIN_FLIP || origin == ORIGIN_CURSOR_UPDATE)
1343                 return;
1344
1345         mutex_lock(&fbc->lock);
1346
1347         frontbuffer_bits &= intel_fbc_get_frontbuffer_bit(fbc);
1348         if (!frontbuffer_bits)
1349                 goto out;
1350
1351         fbc->busy_bits |= frontbuffer_bits;
1352         intel_fbc_deactivate(fbc, "frontbuffer write");
1353
1354 out:
1355         mutex_unlock(&fbc->lock);
1356 }
1357
1358 void intel_fbc_invalidate(struct drm_i915_private *i915,
1359                           unsigned int frontbuffer_bits,
1360                           enum fb_op_origin origin)
1361 {
1362         struct intel_fbc *fbc;
1363         enum intel_fbc_id fbc_id;
1364
1365         for_each_intel_fbc(i915, fbc, fbc_id)
1366                 __intel_fbc_invalidate(fbc, frontbuffer_bits, origin);
1367
1368 }
1369
1370 static void __intel_fbc_flush(struct intel_fbc *fbc,
1371                               unsigned int frontbuffer_bits,
1372                               enum fb_op_origin origin)
1373 {
1374         mutex_lock(&fbc->lock);
1375
1376         frontbuffer_bits &= intel_fbc_get_frontbuffer_bit(fbc);
1377         if (!frontbuffer_bits)
1378                 goto out;
1379
1380         fbc->busy_bits &= ~frontbuffer_bits;
1381
1382         if (origin == ORIGIN_FLIP || origin == ORIGIN_CURSOR_UPDATE)
1383                 goto out;
1384
1385         if (fbc->busy_bits || fbc->flip_pending)
1386                 goto out;
1387
1388         if (fbc->active)
1389                 intel_fbc_nuke(fbc);
1390         else
1391                 intel_fbc_activate(fbc);
1392
1393 out:
1394         mutex_unlock(&fbc->lock);
1395 }
1396
1397 void intel_fbc_flush(struct drm_i915_private *i915,
1398                      unsigned int frontbuffer_bits,
1399                      enum fb_op_origin origin)
1400 {
1401         struct intel_fbc *fbc;
1402         enum intel_fbc_id fbc_id;
1403
1404         for_each_intel_fbc(i915, fbc, fbc_id)
1405                 __intel_fbc_flush(fbc, frontbuffer_bits, origin);
1406 }
1407
1408 int intel_fbc_atomic_check(struct intel_atomic_state *state)
1409 {
1410         struct intel_plane_state *plane_state;
1411         struct intel_plane *plane;
1412         int i;
1413
1414         for_each_new_intel_plane_in_state(state, plane, plane_state, i) {
1415                 int ret;
1416
1417                 ret = intel_fbc_check_plane(state, plane);
1418                 if (ret)
1419                         return ret;
1420         }
1421
1422         return 0;
1423 }
1424
1425 static void __intel_fbc_enable(struct intel_atomic_state *state,
1426                                struct intel_crtc *crtc,
1427                                struct intel_plane *plane)
1428 {
1429         struct drm_i915_private *i915 = to_i915(state->base.dev);
1430         const struct intel_plane_state *plane_state =
1431                 intel_atomic_get_new_plane_state(state, plane);
1432         struct intel_fbc *fbc = plane->fbc;
1433
1434         lockdep_assert_held(&fbc->lock);
1435
1436         if (fbc->state.plane) {
1437                 if (fbc->state.plane != plane)
1438                         return;
1439
1440                 if (intel_fbc_is_ok(plane_state)) {
1441                         intel_fbc_update_state(state, crtc, plane);
1442                         return;
1443                 }
1444
1445                 __intel_fbc_disable(fbc);
1446         }
1447
1448         drm_WARN_ON(&i915->drm, fbc->active);
1449
1450         fbc->no_fbc_reason = plane_state->no_fbc_reason;
1451         if (fbc->no_fbc_reason)
1452                 return;
1453
1454         if (!intel_fbc_is_fence_ok(plane_state)) {
1455                 fbc->no_fbc_reason = "framebuffer not fenced";
1456                 return;
1457         }
1458
1459         if (fbc->underrun_detected) {
1460                 fbc->no_fbc_reason = "FIFO underrun";
1461                 return;
1462         }
1463
1464         if (intel_fbc_alloc_cfb(fbc, intel_fbc_cfb_size(plane_state),
1465                                 intel_fbc_min_limit(plane_state))) {
1466                 fbc->no_fbc_reason = "not enough stolen memory";
1467                 return;
1468         }
1469
1470         drm_dbg_kms(&i915->drm, "Enabling FBC on [PLANE:%d:%s]\n",
1471                     plane->base.base.id, plane->base.name);
1472         fbc->no_fbc_reason = "FBC enabled but not active yet\n";
1473
1474         intel_fbc_update_state(state, crtc, plane);
1475
1476         intel_fbc_program_workarounds(fbc);
1477         intel_fbc_program_cfb(fbc);
1478 }
1479
1480 /**
1481  * intel_fbc_disable - disable FBC if it's associated with crtc
1482  * @crtc: the CRTC
1483  *
1484  * This function disables FBC if it's associated with the provided CRTC.
1485  */
1486 void intel_fbc_disable(struct intel_crtc *crtc)
1487 {
1488         struct drm_i915_private *i915 = to_i915(crtc->base.dev);
1489         struct intel_plane *plane;
1490
1491         for_each_intel_plane(&i915->drm, plane) {
1492                 struct intel_fbc *fbc = plane->fbc;
1493
1494                 if (!fbc || plane->pipe != crtc->pipe)
1495                         continue;
1496
1497                 mutex_lock(&fbc->lock);
1498                 if (fbc->state.plane == plane)
1499                         __intel_fbc_disable(fbc);
1500                 mutex_unlock(&fbc->lock);
1501         }
1502 }
1503
1504 void intel_fbc_update(struct intel_atomic_state *state,
1505                       struct intel_crtc *crtc)
1506 {
1507         const struct intel_crtc_state *crtc_state =
1508                 intel_atomic_get_new_crtc_state(state, crtc);
1509         const struct intel_plane_state *plane_state;
1510         struct intel_plane *plane;
1511         int i;
1512
1513         for_each_new_intel_plane_in_state(state, plane, plane_state, i) {
1514                 struct intel_fbc *fbc = plane->fbc;
1515
1516                 if (!fbc || plane->pipe != crtc->pipe)
1517                         continue;
1518
1519                 mutex_lock(&fbc->lock);
1520
1521                 if (intel_crtc_needs_fastset(crtc_state) &&
1522                     plane_state->no_fbc_reason) {
1523                         if (fbc->state.plane == plane)
1524                                 __intel_fbc_disable(fbc);
1525                 } else {
1526                         __intel_fbc_enable(state, crtc, plane);
1527                 }
1528
1529                 mutex_unlock(&fbc->lock);
1530         }
1531 }
1532
1533 static void intel_fbc_underrun_work_fn(struct work_struct *work)
1534 {
1535         struct intel_fbc *fbc = container_of(work, typeof(*fbc), underrun_work);
1536         struct drm_i915_private *i915 = fbc->i915;
1537
1538         mutex_lock(&fbc->lock);
1539
1540         /* Maybe we were scheduled twice. */
1541         if (fbc->underrun_detected || !fbc->state.plane)
1542                 goto out;
1543
1544         drm_dbg_kms(&i915->drm, "Disabling FBC due to FIFO underrun.\n");
1545         fbc->underrun_detected = true;
1546
1547         intel_fbc_deactivate(fbc, "FIFO underrun");
1548         if (!fbc->flip_pending)
1549                 intel_crtc_wait_for_next_vblank(intel_crtc_for_pipe(i915, fbc->state.plane->pipe));
1550         __intel_fbc_disable(fbc);
1551 out:
1552         mutex_unlock(&fbc->lock);
1553 }
1554
1555 static void __intel_fbc_reset_underrun(struct intel_fbc *fbc)
1556 {
1557         struct drm_i915_private *i915 = fbc->i915;
1558
1559         cancel_work_sync(&fbc->underrun_work);
1560
1561         mutex_lock(&fbc->lock);
1562
1563         if (fbc->underrun_detected) {
1564                 drm_dbg_kms(&i915->drm,
1565                             "Re-allowing FBC after fifo underrun\n");
1566                 fbc->no_fbc_reason = "FIFO underrun cleared";
1567         }
1568
1569         fbc->underrun_detected = false;
1570         mutex_unlock(&fbc->lock);
1571 }
1572
1573 /*
1574  * intel_fbc_reset_underrun - reset FBC fifo underrun status.
1575  * @i915: the i915 device
1576  *
1577  * See intel_fbc_handle_fifo_underrun_irq(). For automated testing we
1578  * want to re-enable FBC after an underrun to increase test coverage.
1579  */
1580 void intel_fbc_reset_underrun(struct drm_i915_private *i915)
1581 {
1582         struct intel_fbc *fbc;
1583         enum intel_fbc_id fbc_id;
1584
1585         for_each_intel_fbc(i915, fbc, fbc_id)
1586                 __intel_fbc_reset_underrun(fbc);
1587 }
1588
1589 static void __intel_fbc_handle_fifo_underrun_irq(struct intel_fbc *fbc)
1590 {
1591         /*
1592          * There's no guarantee that underrun_detected won't be set to true
1593          * right after this check and before the work is scheduled, but that's
1594          * not a problem since we'll check it again under the work function
1595          * while FBC is locked. This check here is just to prevent us from
1596          * unnecessarily scheduling the work, and it relies on the fact that we
1597          * never switch underrun_detect back to false after it's true.
1598          */
1599         if (READ_ONCE(fbc->underrun_detected))
1600                 return;
1601
1602         schedule_work(&fbc->underrun_work);
1603 }
1604
1605 /**
1606  * intel_fbc_handle_fifo_underrun_irq - disable FBC when we get a FIFO underrun
1607  * @i915: i915 device
1608  *
1609  * Without FBC, most underruns are harmless and don't really cause too many
1610  * problems, except for an annoying message on dmesg. With FBC, underruns can
1611  * become black screens or even worse, especially when paired with bad
1612  * watermarks. So in order for us to be on the safe side, completely disable FBC
1613  * in case we ever detect a FIFO underrun on any pipe. An underrun on any pipe
1614  * already suggests that watermarks may be bad, so try to be as safe as
1615  * possible.
1616  *
1617  * This function is called from the IRQ handler.
1618  */
1619 void intel_fbc_handle_fifo_underrun_irq(struct drm_i915_private *i915)
1620 {
1621         struct intel_fbc *fbc;
1622         enum intel_fbc_id fbc_id;
1623
1624         for_each_intel_fbc(i915, fbc, fbc_id)
1625                 __intel_fbc_handle_fifo_underrun_irq(fbc);
1626 }
1627
1628 /*
1629  * The DDX driver changes its behavior depending on the value it reads from
1630  * i915.enable_fbc, so sanitize it by translating the default value into either
1631  * 0 or 1 in order to allow it to know what's going on.
1632  *
1633  * Notice that this is done at driver initialization and we still allow user
1634  * space to change the value during runtime without sanitizing it again. IGT
1635  * relies on being able to change i915.enable_fbc at runtime.
1636  */
1637 static int intel_sanitize_fbc_option(struct drm_i915_private *i915)
1638 {
1639         if (i915->params.enable_fbc >= 0)
1640                 return !!i915->params.enable_fbc;
1641
1642         if (!HAS_FBC(i915))
1643                 return 0;
1644
1645         if (IS_BROADWELL(i915) || DISPLAY_VER(i915) >= 9)
1646                 return 1;
1647
1648         return 0;
1649 }
1650
1651 static bool need_fbc_vtd_wa(struct drm_i915_private *i915)
1652 {
1653         /* WaFbcTurnOffFbcWhenHyperVisorIsUsed:skl,bxt */
1654         if (i915_vtd_active(i915) &&
1655             (IS_SKYLAKE(i915) || IS_BROXTON(i915))) {
1656                 drm_info(&i915->drm,
1657                          "Disabling framebuffer compression (FBC) to prevent screen flicker with VT-d enabled\n");
1658                 return true;
1659         }
1660
1661         return false;
1662 }
1663
1664 void intel_fbc_add_plane(struct intel_fbc *fbc, struct intel_plane *plane)
1665 {
1666         plane->fbc = fbc;
1667 }
1668
1669 static struct intel_fbc *intel_fbc_create(struct drm_i915_private *i915,
1670                                           enum intel_fbc_id fbc_id)
1671 {
1672         struct intel_fbc *fbc;
1673
1674         fbc = kzalloc(sizeof(*fbc), GFP_KERNEL);
1675         if (!fbc)
1676                 return NULL;
1677
1678         fbc->id = fbc_id;
1679         fbc->i915 = i915;
1680         INIT_WORK(&fbc->underrun_work, intel_fbc_underrun_work_fn);
1681         mutex_init(&fbc->lock);
1682
1683         if (DISPLAY_VER(i915) >= 7)
1684                 fbc->funcs = &ivb_fbc_funcs;
1685         else if (DISPLAY_VER(i915) == 6)
1686                 fbc->funcs = &snb_fbc_funcs;
1687         else if (DISPLAY_VER(i915) == 5)
1688                 fbc->funcs = &ilk_fbc_funcs;
1689         else if (IS_G4X(i915))
1690                 fbc->funcs = &g4x_fbc_funcs;
1691         else if (DISPLAY_VER(i915) == 4)
1692                 fbc->funcs = &i965_fbc_funcs;
1693         else
1694                 fbc->funcs = &i8xx_fbc_funcs;
1695
1696         return fbc;
1697 }
1698
1699 /**
1700  * intel_fbc_init - Initialize FBC
1701  * @i915: the i915 device
1702  *
1703  * This function might be called during PM init process.
1704  */
1705 void intel_fbc_init(struct drm_i915_private *i915)
1706 {
1707         enum intel_fbc_id fbc_id;
1708
1709         if (!drm_mm_initialized(&i915->mm.stolen))
1710                 RUNTIME_INFO(i915)->fbc_mask = 0;
1711
1712         if (need_fbc_vtd_wa(i915))
1713                 RUNTIME_INFO(i915)->fbc_mask = 0;
1714
1715         i915->params.enable_fbc = intel_sanitize_fbc_option(i915);
1716         drm_dbg_kms(&i915->drm, "Sanitized enable_fbc value: %d\n",
1717                     i915->params.enable_fbc);
1718
1719         for_each_fbc_id(i915, fbc_id)
1720                 i915->display.fbc[fbc_id] = intel_fbc_create(i915, fbc_id);
1721 }
1722
1723 /**
1724  * intel_fbc_sanitize - Sanitize FBC
1725  * @i915: the i915 device
1726  *
1727  * Make sure FBC is initially disabled since we have no
1728  * idea eg. into which parts of stolen it might be scribbling
1729  * into.
1730  */
1731 void intel_fbc_sanitize(struct drm_i915_private *i915)
1732 {
1733         struct intel_fbc *fbc;
1734         enum intel_fbc_id fbc_id;
1735
1736         for_each_intel_fbc(i915, fbc, fbc_id) {
1737                 if (intel_fbc_hw_is_active(fbc))
1738                         intel_fbc_hw_deactivate(fbc);
1739         }
1740 }
1741
1742 static int intel_fbc_debugfs_status_show(struct seq_file *m, void *unused)
1743 {
1744         struct intel_fbc *fbc = m->private;
1745         struct drm_i915_private *i915 = fbc->i915;
1746         struct intel_plane *plane;
1747         intel_wakeref_t wakeref;
1748
1749         drm_modeset_lock_all(&i915->drm);
1750
1751         wakeref = intel_runtime_pm_get(&i915->runtime_pm);
1752         mutex_lock(&fbc->lock);
1753
1754         if (fbc->active) {
1755                 seq_puts(m, "FBC enabled\n");
1756                 seq_printf(m, "Compressing: %s\n",
1757                            str_yes_no(intel_fbc_is_compressing(fbc)));
1758         } else {
1759                 seq_printf(m, "FBC disabled: %s\n", fbc->no_fbc_reason);
1760         }
1761
1762         for_each_intel_plane(&i915->drm, plane) {
1763                 const struct intel_plane_state *plane_state =
1764                         to_intel_plane_state(plane->base.state);
1765
1766                 if (plane->fbc != fbc)
1767                         continue;
1768
1769                 seq_printf(m, "%c [PLANE:%d:%s]: %s\n",
1770                            fbc->state.plane == plane ? '*' : ' ',
1771                            plane->base.base.id, plane->base.name,
1772                            plane_state->no_fbc_reason ?: "FBC possible");
1773         }
1774
1775         mutex_unlock(&fbc->lock);
1776         intel_runtime_pm_put(&i915->runtime_pm, wakeref);
1777
1778         drm_modeset_unlock_all(&i915->drm);
1779
1780         return 0;
1781 }
1782
1783 DEFINE_SHOW_ATTRIBUTE(intel_fbc_debugfs_status);
1784
1785 static int intel_fbc_debugfs_false_color_get(void *data, u64 *val)
1786 {
1787         struct intel_fbc *fbc = data;
1788
1789         *val = fbc->false_color;
1790
1791         return 0;
1792 }
1793
1794 static int intel_fbc_debugfs_false_color_set(void *data, u64 val)
1795 {
1796         struct intel_fbc *fbc = data;
1797
1798         mutex_lock(&fbc->lock);
1799
1800         fbc->false_color = val;
1801
1802         if (fbc->active)
1803                 fbc->funcs->set_false_color(fbc, fbc->false_color);
1804
1805         mutex_unlock(&fbc->lock);
1806
1807         return 0;
1808 }
1809
1810 DEFINE_DEBUGFS_ATTRIBUTE(intel_fbc_debugfs_false_color_fops,
1811                          intel_fbc_debugfs_false_color_get,
1812                          intel_fbc_debugfs_false_color_set,
1813                          "%llu\n");
1814
1815 static void intel_fbc_debugfs_add(struct intel_fbc *fbc,
1816                                   struct dentry *parent)
1817 {
1818         debugfs_create_file("i915_fbc_status", 0444, parent,
1819                             fbc, &intel_fbc_debugfs_status_fops);
1820
1821         if (fbc->funcs->set_false_color)
1822                 debugfs_create_file_unsafe("i915_fbc_false_color", 0644, parent,
1823                                            fbc, &intel_fbc_debugfs_false_color_fops);
1824 }
1825
1826 void intel_fbc_crtc_debugfs_add(struct intel_crtc *crtc)
1827 {
1828         struct intel_plane *plane = to_intel_plane(crtc->base.primary);
1829
1830         if (plane->fbc)
1831                 intel_fbc_debugfs_add(plane->fbc, crtc->base.debugfs_entry);
1832 }
1833
1834 /* FIXME: remove this once igt is on board with per-crtc stuff */
1835 void intel_fbc_debugfs_register(struct drm_i915_private *i915)
1836 {
1837         struct drm_minor *minor = i915->drm.primary;
1838         struct intel_fbc *fbc;
1839
1840         fbc = i915->display.fbc[INTEL_FBC_A];
1841         if (fbc)
1842                 intel_fbc_debugfs_add(fbc, minor->debugfs_root);
1843 }