drivers/gpu/drm/i915/display/intel_dp.h

   1 /* SPDX-License-Identifier: MIT */
   2 /*
   3  * Copyright © 2019 Intel Corporation
   4  */
   5
   6 #ifndef __INTEL_DP_H__
   7 #define __INTEL_DP_H__
   8
   9 #include <linux/types.h>
  10
  11 enum intel_output_format;
  12 enum pipe;
  13 enum port;
  14 struct drm_connector_state;
  15 struct drm_encoder;
  16 struct drm_i915_private;
  17 struct drm_modeset_acquire_ctx;
  18 struct drm_dp_vsc_sdp;
  19 struct intel_atomic_state;
  20 struct intel_connector;
  21 struct intel_crtc_state;
  22 struct intel_digital_port;
  23 struct intel_dp;
  24 struct intel_encoder;
  25
  26 struct link_config_limits {
  27         int min_rate, max_rate;
  28         int min_lane_count, max_lane_count;
  29         int min_bpp, max_bpp;
  30 };
  31
  32 void intel_edp_fixup_vbt_bpp(struct intel_encoder *encoder, int pipe_bpp);
  33 void intel_dp_adjust_compliance_config(struct intel_dp *intel_dp,
  34                                        struct intel_crtc_state *pipe_config,
  35                                        struct link_config_limits *limits);
  36 bool intel_dp_limited_color_range(const struct intel_crtc_state *crtc_state,
  37                                   const struct drm_connector_state *conn_state);
  38 int intel_dp_min_bpp(enum intel_output_format output_format);
  39 bool intel_dp_init_connector(struct intel_digital_port *dig_port,
  40                              struct intel_connector *intel_connector);
  41 void intel_dp_set_link_params(struct intel_dp *intel_dp,
  42                               int link_rate, int lane_count);
  43 int intel_dp_get_link_train_fallback_values(struct intel_dp *intel_dp,
  44                                             int link_rate, u8 lane_count);
  45 int intel_dp_retrain_link(struct intel_encoder *encoder,
  46                           struct drm_modeset_acquire_ctx *ctx);
  47 void intel_dp_set_power(struct intel_dp *intel_dp, u8 mode);
  48 void intel_dp_configure_protocol_converter(struct intel_dp *intel_dp,
  49                                            const struct intel_crtc_state *crtc_state);
  50 void intel_dp_sink_set_decompression_state(struct intel_dp *intel_dp,
  51                                            const struct intel_crtc_state *crtc_state,
  52                                            bool enable);
  53 void intel_dp_encoder_suspend(struct intel_encoder *intel_encoder);
  54 void intel_dp_encoder_shutdown(struct intel_encoder *intel_encoder);
  55 void intel_dp_encoder_flush_work(struct drm_encoder *encoder);
  56 int intel_dp_compute_config(struct intel_encoder *encoder,
  57                             struct intel_crtc_state *pipe_config,
  58                             struct drm_connector_state *conn_state);
  59 int intel_dp_dsc_compute_config(struct intel_dp *intel_dp,
  60                                 struct intel_crtc_state *pipe_config,
  61                                 struct drm_connector_state *conn_state,
  62                                 struct link_config_limits *limits,
  63                                 int timeslots,
  64                                 bool recompute_pipe_bpp);
  65 bool intel_dp_is_edp(struct intel_dp *intel_dp);
  66 bool intel_dp_is_uhbr(const struct intel_crtc_state *crtc_state);
  67 bool intel_dp_is_port_edp(struct drm_i915_private *dev_priv, enum port port);
  68 enum irqreturn intel_dp_hpd_pulse(struct intel_digital_port *dig_port,
  69                                   bool long_hpd);
  70 void intel_edp_backlight_on(const struct intel_crtc_state *crtc_state,
  71                             const struct drm_connector_state *conn_state);
  72 void intel_edp_backlight_off(const struct drm_connector_state *conn_state);
  73 void intel_edp_fixup_vbt_bpp(struct intel_encoder *encoder, int pipe_bpp);
  74 void intel_dp_mst_suspend(struct drm_i915_private *dev_priv);
  75 void intel_dp_mst_resume(struct drm_i915_private *dev_priv);
  76 int intel_dp_max_link_rate(struct intel_dp *intel_dp);
  77 int intel_dp_max_lane_count(struct intel_dp *intel_dp);
  78 int intel_dp_rate_select(struct intel_dp *intel_dp, int rate);
  79
  80 void intel_dp_compute_rate(struct intel_dp *intel_dp, int port_clock,
  81                            u8 *link_bw, u8 *rate_select);
  82 bool intel_dp_source_supports_tps3(struct drm_i915_private *i915);
  83 bool intel_dp_source_supports_tps4(struct drm_i915_private *i915);
  84
  85 bool intel_dp_get_colorimetry_status(struct intel_dp *intel_dp);
  86 int intel_dp_link_required(int pixel_clock, int bpp);
  87 int intel_dp_max_data_rate(int max_link_rate, int max_lanes);
  88 bool intel_dp_can_bigjoiner(struct intel_dp *intel_dp);
  89 bool intel_dp_needs_vsc_sdp(const struct intel_crtc_state *crtc_state,
  90                             const struct drm_connector_state *conn_state);
  91 void intel_dp_compute_psr_vsc_sdp(struct intel_dp *intel_dp,
  92                                   const struct intel_crtc_state *crtc_state,
  93                                   const struct drm_connector_state *conn_state,
  94                                   struct drm_dp_vsc_sdp *vsc);
  95 void intel_write_dp_vsc_sdp(struct intel_encoder *encoder,
  96                             const struct intel_crtc_state *crtc_state,
  97                             const struct drm_dp_vsc_sdp *vsc);
  98 void intel_dp_set_infoframes(struct intel_encoder *encoder, bool enable,
  99                              const struct intel_crtc_state *crtc_state,
 100                              const struct drm_connector_state *conn_state);
 101 void intel_read_dp_sdp(struct intel_encoder *encoder,
 102                        struct intel_crtc_state *crtc_state,
 103                        unsigned int type);
 104 bool intel_digital_port_connected(struct intel_encoder *encoder);
 105 int intel_dp_dsc_compute_bpp(struct intel_dp *intel_dp, u8 dsc_max_bpc);
 106 u16 intel_dp_dsc_get_output_bpp(struct drm_i915_private *i915,
 107                                 u32 link_clock, u32 lane_count,
 108                                 u32 mode_clock, u32 mode_hdisplay,
 109                                 bool bigjoiner,
 110                                 u32 pipe_bpp,
 111                                 u32 timeslots);
 112 u8 intel_dp_dsc_get_slice_count(struct intel_dp *intel_dp,
 113                                 int mode_clock, int mode_hdisplay,
 114                                 bool bigjoiner);
 115 bool intel_dp_need_bigjoiner(struct intel_dp *intel_dp,
 116                              int hdisplay, int clock);
 117
 118 static inline unsigned int intel_dp_unused_lane_mask(int lane_count)
 119 {
 120         return ~((1 << lane_count) - 1) & 0xf;
 121 }
 122
 123 u32 intel_dp_mode_to_fec_clock(u32 mode_clock);
 124 u32 intel_dp_dsc_nearest_valid_bpp(struct drm_i915_private *i915, u32 bpp, u32 pipe_bpp);
 125
 126 void intel_ddi_update_pipe(struct intel_atomic_state *state,
 127                            struct intel_encoder *encoder,
 128                            const struct intel_crtc_state *crtc_state,
 129                            const struct drm_connector_state *conn_state);
 130
 131 bool intel_dp_initial_fastset_check(struct intel_encoder *encoder,
 132                                     struct intel_crtc_state *crtc_state);
 133 void intel_dp_sync_state(struct intel_encoder *encoder,
 134                          const struct intel_crtc_state *crtc_state);
 135
 136 void intel_dp_check_frl_training(struct intel_dp *intel_dp);
 137 void intel_dp_pcon_dsc_configure(struct intel_dp *intel_dp,
 138                                  const struct intel_crtc_state *crtc_state);
 139 void intel_dp_phy_test(struct intel_encoder *encoder);
 140
 141 void intel_dp_wait_source_oui(struct intel_dp *intel_dp);
 142
 143 #endif /* __INTEL_DP_H__ */