drivers/gpu/drm/i915/display/intel_display.c

   1 /*
   2  * Copyright © 2006-2007 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  21  * DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *      Eric Anholt <[email protected]>
  25  */
  26
  27 #include <linux/dma-resv.h>
  28 #include <linux/i2c.h>
  29 #include <linux/input.h>
  30 #include <linux/kernel.h>
  31 #include <linux/module.h>
  32 #include <linux/slab.h>
  33 #include <linux/string_helpers.h>
  34 #include <linux/vga_switcheroo.h>
  35 #include <acpi/video.h>
  36
  37 #include <drm/display/drm_dp_helper.h>
  38 #include <drm/drm_atomic.h>
  39 #include <drm/drm_atomic_helper.h>
  40 #include <drm/drm_atomic_uapi.h>
  41 #include <drm/drm_damage_helper.h>
  42 #include <drm/drm_edid.h>
  43 #include <drm/drm_fourcc.h>
  44 #include <drm/drm_privacy_screen_consumer.h>
  45 #include <drm/drm_probe_helper.h>
  46 #include <drm/drm_rect.h>
  47
  48 #include "gem/i915_gem_lmem.h"
  49 #include "gem/i915_gem_object.h"
  50
  51 #include "g4x_dp.h"
  52 #include "g4x_hdmi.h"
  53 #include "hsw_ips.h"
  54 #include "i915_drv.h"
  55 #include "i915_reg.h"
  56 #include "i915_utils.h"
  57 #include "i9xx_plane.h"
  58 #include "i9xx_wm.h"
  59 #include "icl_dsi.h"
  60 #include "intel_acpi.h"
  61 #include "intel_atomic.h"
  62 #include "intel_atomic_plane.h"
  63 #include "intel_audio.h"
  64 #include "intel_bw.h"
  65 #include "intel_cdclk.h"
  66 #include "intel_clock_gating.h"
  67 #include "intel_color.h"
  68 #include "intel_crt.h"
  69 #include "intel_crtc.h"
  70 #include "intel_crtc_state_dump.h"
  71 #include "intel_ddi.h"
  72 #include "intel_de.h"
  73 #include "intel_display_debugfs.h"
  74 #include "intel_display_power.h"
  75 #include "intel_display_types.h"
  76 #include "intel_dmc.h"
  77 #include "intel_dp.h"
  78 #include "intel_dp_link_training.h"
  79 #include "intel_dp_mst.h"
  80 #include "intel_dpio_phy.h"
  81 #include "intel_dpll.h"
  82 #include "intel_dpll_mgr.h"
  83 #include "intel_dpt.h"
  84 #include "intel_drrs.h"
  85 #include "intel_dsi.h"
  86 #include "intel_dvo.h"
  87 #include "intel_fb.h"
  88 #include "intel_fbc.h"
  89 #include "intel_fbdev.h"
  90 #include "intel_fdi.h"
  91 #include "intel_fifo_underrun.h"
  92 #include "intel_frontbuffer.h"
  93 #include "intel_gmbus.h"
  94 #include "intel_hdcp.h"
  95 #include "intel_hdmi.h"
  96 #include "intel_hotplug.h"
  97 #include "intel_hti.h"
  98 #include "intel_lvds.h"
  99 #include "intel_lvds_regs.h"
 100 #include "intel_modeset_setup.h"
 101 #include "intel_modeset_verify.h"
 102 #include "intel_overlay.h"
 103 #include "intel_panel.h"
 104 #include "intel_pch_display.h"
 105 #include "intel_pch_refclk.h"
 106 #include "intel_pcode.h"
 107 #include "intel_pipe_crc.h"
 108 #include "intel_plane_initial.h"
 109 #include "intel_pps.h"
 110 #include "intel_psr.h"
 111 #include "intel_quirks.h"
 112 #include "intel_sdvo.h"
 113 #include "intel_snps_phy.h"
 114 #include "intel_tc.h"
 115 #include "intel_tv.h"
 116 #include "intel_vblank.h"
 117 #include "intel_vdsc.h"
 118 #include "intel_vdsc_regs.h"
 119 #include "intel_vga.h"
 120 #include "intel_vrr.h"
 121 #include "intel_wm.h"
 122 #include "skl_scaler.h"
 123 #include "skl_universal_plane.h"
 124 #include "skl_watermark.h"
 125 #include "vlv_dsi.h"
 126 #include "vlv_dsi_pll.h"
 127 #include "vlv_dsi_regs.h"
 128 #include "vlv_sideband.h"
 129
 130 static void intel_set_transcoder_timings(const struct intel_crtc_state *crtc_state);
 131 static void intel_set_pipe_src_size(const struct intel_crtc_state *crtc_state);
 132 static void hsw_set_transconf(const struct intel_crtc_state *crtc_state);
 133 static void bdw_set_pipe_misc(const struct intel_crtc_state *crtc_state);
 134 static void ilk_pfit_enable(const struct intel_crtc_state *crtc_state);
 135
 136 /* returns HPLL frequency in kHz */
 137 int vlv_get_hpll_vco(struct drm_i915_private *dev_priv)
 138 {
 139         int hpll_freq, vco_freq[] = { 800, 1600, 2000, 2400 };
 140
 141         /* Obtain SKU information */
 142         hpll_freq = vlv_cck_read(dev_priv, CCK_FUSE_REG) &
 143                 CCK_FUSE_HPLL_FREQ_MASK;
 144
 145         return vco_freq[hpll_freq] * 1000;
 146 }
 147
 148 int vlv_get_cck_clock(struct drm_i915_private *dev_priv,
 149                       const char *name, u32 reg, int ref_freq)
 150 {
 151         u32 val;
 152         int divider;
 153
 154         val = vlv_cck_read(dev_priv, reg);
 155         divider = val & CCK_FREQUENCY_VALUES;
 156
 157         drm_WARN(&dev_priv->drm, (val & CCK_FREQUENCY_STATUS) !=
 158                  (divider << CCK_FREQUENCY_STATUS_SHIFT),
 159                  "%s change in progress\n", name);
 160
 161         return DIV_ROUND_CLOSEST(ref_freq << 1, divider + 1);
 162 }
 163
 164 int vlv_get_cck_clock_hpll(struct drm_i915_private *dev_priv,
 165                            const char *name, u32 reg)
 166 {
 167         int hpll;
 168
 169         vlv_cck_get(dev_priv);
 170
 171         if (dev_priv->hpll_freq == 0)
 172                 dev_priv->hpll_freq = vlv_get_hpll_vco(dev_priv);
 173
 174         hpll = vlv_get_cck_clock(dev_priv, name, reg, dev_priv->hpll_freq);
 175
 176         vlv_cck_put(dev_priv);
 177
 178         return hpll;
 179 }
 180
 181 static void intel_update_czclk(struct drm_i915_private *dev_priv)
 182 {
 183         if (!(IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)))
 184                 return;
 185
 186         dev_priv->czclk_freq = vlv_get_cck_clock_hpll(dev_priv, "czclk",
 187                                                       CCK_CZ_CLOCK_CONTROL);
 188
 189         drm_dbg(&dev_priv->drm, "CZ clock rate: %d kHz\n",
 190                 dev_priv->czclk_freq);
 191 }
 192
 193 static bool is_hdr_mode(const struct intel_crtc_state *crtc_state)
 194 {
 195         return (crtc_state->active_planes &
 196                 ~(icl_hdr_plane_mask() | BIT(PLANE_CURSOR))) == 0;
 197 }
 198
 199 /* WA Display #0827: Gen9:all */
 200 static void
 201 skl_wa_827(struct drm_i915_private *dev_priv, enum pipe pipe, bool enable)
 202 {
 203         if (enable)
 204                 intel_de_rmw(dev_priv, CLKGATE_DIS_PSL(pipe),
 205                              0, DUPS1_GATING_DIS | DUPS2_GATING_DIS);
 206         else
 207                 intel_de_rmw(dev_priv, CLKGATE_DIS_PSL(pipe),
 208                              DUPS1_GATING_DIS | DUPS2_GATING_DIS, 0);
 209 }
 210
 211 /* Wa_2006604312:icl,ehl */
 212 static void
 213 icl_wa_scalerclkgating(struct drm_i915_private *dev_priv, enum pipe pipe,
 214                        bool enable)
 215 {
 216         if (enable)
 217                 intel_de_rmw(dev_priv, CLKGATE_DIS_PSL(pipe), 0, DPFR_GATING_DIS);
 218         else
 219                 intel_de_rmw(dev_priv, CLKGATE_DIS_PSL(pipe), DPFR_GATING_DIS, 0);
 220 }
 221
 222 /* Wa_1604331009:icl,jsl,ehl */
 223 static void
 224 icl_wa_cursorclkgating(struct drm_i915_private *dev_priv, enum pipe pipe,
 225                        bool enable)
 226 {
 227         intel_de_rmw(dev_priv, CLKGATE_DIS_PSL(pipe), CURSOR_GATING_DIS,
 228                      enable ? CURSOR_GATING_DIS : 0);
 229 }
 230
 231 static bool
 232 is_trans_port_sync_slave(const struct intel_crtc_state *crtc_state)
 233 {
 234         return crtc_state->master_transcoder != INVALID_TRANSCODER;
 235 }
 236
 237 static bool
 238 is_trans_port_sync_master(const struct intel_crtc_state *crtc_state)
 239 {
 240         return crtc_state->sync_mode_slaves_mask != 0;
 241 }
 242
 243 bool
 244 is_trans_port_sync_mode(const struct intel_crtc_state *crtc_state)
 245 {
 246         return is_trans_port_sync_master(crtc_state) ||
 247                 is_trans_port_sync_slave(crtc_state);
 248 }
 249
 250 static enum pipe bigjoiner_master_pipe(const struct intel_crtc_state *crtc_state)
 251 {
 252         return ffs(crtc_state->bigjoiner_pipes) - 1;
 253 }
 254
 255 u8 intel_crtc_bigjoiner_slave_pipes(const struct intel_crtc_state *crtc_state)
 256 {
 257         if (crtc_state->bigjoiner_pipes)
 258                 return crtc_state->bigjoiner_pipes & ~BIT(bigjoiner_master_pipe(crtc_state));
 259         else
 260                 return 0;
 261 }
 262
 263 bool intel_crtc_is_bigjoiner_slave(const struct intel_crtc_state *crtc_state)
 264 {
 265         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
 266
 267         return crtc_state->bigjoiner_pipes &&
 268                 crtc->pipe != bigjoiner_master_pipe(crtc_state);
 269 }
 270
 271 bool intel_crtc_is_bigjoiner_master(const struct intel_crtc_state *crtc_state)
 272 {
 273         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
 274
 275         return crtc_state->bigjoiner_pipes &&
 276                 crtc->pipe == bigjoiner_master_pipe(crtc_state);
 277 }
 278
 279 static int intel_bigjoiner_num_pipes(const struct intel_crtc_state *crtc_state)
 280 {
 281         return hweight8(crtc_state->bigjoiner_pipes);
 282 }
 283
 284 struct intel_crtc *intel_master_crtc(const struct intel_crtc_state *crtc_state)
 285 {
 286         struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev);
 287
 288         if (intel_crtc_is_bigjoiner_slave(crtc_state))
 289                 return intel_crtc_for_pipe(i915, bigjoiner_master_pipe(crtc_state));
 290         else
 291                 return to_intel_crtc(crtc_state->uapi.crtc);
 292 }
 293
 294 static void
 295 intel_wait_for_pipe_off(const struct intel_crtc_state *old_crtc_state)
 296 {
 297         struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc);
 298         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 299
 300         if (DISPLAY_VER(dev_priv) >= 4) {
 301                 enum transcoder cpu_transcoder = old_crtc_state->cpu_transcoder;
 302
 303                 /* Wait for the Pipe State to go off */
 304                 if (intel_de_wait_for_clear(dev_priv, TRANSCONF(cpu_transcoder),
 305                                             TRANSCONF_STATE_ENABLE, 100))
 306                         drm_WARN(&dev_priv->drm, 1, "pipe_off wait timed out\n");
 307         } else {
 308                 intel_wait_for_pipe_scanline_stopped(crtc);
 309         }
 310 }
 311
 312 void assert_transcoder(struct drm_i915_private *dev_priv,
 313                        enum transcoder cpu_transcoder, bool state)
 314 {
 315         bool cur_state;
 316         enum intel_display_power_domain power_domain;
 317         intel_wakeref_t wakeref;
 318
 319         /* we keep both pipes enabled on 830 */
 320         if (IS_I830(dev_priv))
 321                 state = true;
 322
 323         power_domain = POWER_DOMAIN_TRANSCODER(cpu_transcoder);
 324         wakeref = intel_display_power_get_if_enabled(dev_priv, power_domain);
 325         if (wakeref) {
 326                 u32 val = intel_de_read(dev_priv, TRANSCONF(cpu_transcoder));
 327                 cur_state = !!(val & TRANSCONF_ENABLE);
 328
 329                 intel_display_power_put(dev_priv, power_domain, wakeref);
 330         } else {
 331                 cur_state = false;
 332         }
 333
 334         I915_STATE_WARN(cur_state != state,
 335                         "transcoder %s assertion failure (expected %s, current %s)\n",
 336                         transcoder_name(cpu_transcoder),
 337                         str_on_off(state), str_on_off(cur_state));
 338 }
 339
 340 static void assert_plane(struct intel_plane *plane, bool state)
 341 {
 342         enum pipe pipe;
 343         bool cur_state;
 344
 345         cur_state = plane->get_hw_state(plane, &pipe);
 346
 347         I915_STATE_WARN(cur_state != state,
 348                         "%s assertion failure (expected %s, current %s)\n",
 349                         plane->base.name, str_on_off(state),
 350                         str_on_off(cur_state));
 351 }
 352
 353 #define assert_plane_enabled(p) assert_plane(p, true)
 354 #define assert_plane_disabled(p) assert_plane(p, false)
 355
 356 static void assert_planes_disabled(struct intel_crtc *crtc)
 357 {
 358         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 359         struct intel_plane *plane;
 360
 361         for_each_intel_plane_on_crtc(&dev_priv->drm, crtc, plane)
 362                 assert_plane_disabled(plane);
 363 }
 364
 365 void vlv_wait_port_ready(struct drm_i915_private *dev_priv,
 366                          struct intel_digital_port *dig_port,
 367                          unsigned int expected_mask)
 368 {
 369         u32 port_mask;
 370         i915_reg_t dpll_reg;
 371
 372         switch (dig_port->base.port) {
 373         default:
 374                 MISSING_CASE(dig_port->base.port);
 375                 fallthrough;
 376         case PORT_B:
 377                 port_mask = DPLL_PORTB_READY_MASK;
 378                 dpll_reg = DPLL(0);
 379                 break;
 380         case PORT_C:
 381                 port_mask = DPLL_PORTC_READY_MASK;
 382                 dpll_reg = DPLL(0);
 383                 expected_mask <<= 4;
 384                 break;
 385         case PORT_D:
 386                 port_mask = DPLL_PORTD_READY_MASK;
 387                 dpll_reg = DPIO_PHY_STATUS;
 388                 break;
 389         }
 390
 391         if (intel_de_wait_for_register(dev_priv, dpll_reg,
 392                                        port_mask, expected_mask, 1000))
 393                 drm_WARN(&dev_priv->drm, 1,
 394                          "timed out waiting for [ENCODER:%d:%s] port ready: got 0x%x, expected 0x%x\n",
 395                          dig_port->base.base.base.id, dig_port->base.base.name,
 396                          intel_de_read(dev_priv, dpll_reg) & port_mask,
 397                          expected_mask);
 398 }
 399
 400 void intel_enable_transcoder(const struct intel_crtc_state *new_crtc_state)
 401 {
 402         struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->uapi.crtc);
 403         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 404         enum transcoder cpu_transcoder = new_crtc_state->cpu_transcoder;
 405         enum pipe pipe = crtc->pipe;
 406         i915_reg_t reg;
 407         u32 val;
 408
 409         drm_dbg_kms(&dev_priv->drm, "enabling pipe %c\n", pipe_name(pipe));
 410
 411         assert_planes_disabled(crtc);
 412
 413         /*
 414          * A pipe without a PLL won't actually be able to drive bits from
 415          * a plane.  On ILK+ the pipe PLLs are integrated, so we don't
 416          * need the check.
 417          */
 418         if (HAS_GMCH(dev_priv)) {
 419                 if (intel_crtc_has_type(new_crtc_state, INTEL_OUTPUT_DSI))
 420                         assert_dsi_pll_enabled(dev_priv);
 421                 else
 422                         assert_pll_enabled(dev_priv, pipe);
 423         } else {
 424                 if (new_crtc_state->has_pch_encoder) {
 425                         /* if driving the PCH, we need FDI enabled */
 426                         assert_fdi_rx_pll_enabled(dev_priv,
 427                                                   intel_crtc_pch_transcoder(crtc));
 428                         assert_fdi_tx_pll_enabled(dev_priv,
 429                                                   (enum pipe) cpu_transcoder);
 430                 }
 431                 /* FIXME: assert CPU port conditions for SNB+ */
 432         }
 433
 434         /* Wa_22012358565:adl-p */
 435         if (DISPLAY_VER(dev_priv) == 13)
 436                 intel_de_rmw(dev_priv, PIPE_ARB_CTL(pipe),
 437                              0, PIPE_ARB_USE_PROG_SLOTS);
 438
 439         reg = TRANSCONF(cpu_transcoder);
 440         val = intel_de_read(dev_priv, reg);
 441         if (val & TRANSCONF_ENABLE) {
 442                 /* we keep both pipes enabled on 830 */
 443                 drm_WARN_ON(&dev_priv->drm, !IS_I830(dev_priv));
 444                 return;
 445         }
 446
 447         intel_de_write(dev_priv, reg, val | TRANSCONF_ENABLE);
 448         intel_de_posting_read(dev_priv, reg);
 449
 450         /*
 451          * Until the pipe starts PIPEDSL reads will return a stale value,
 452          * which causes an apparent vblank timestamp jump when PIPEDSL
 453          * resets to its proper value. That also messes up the frame count
 454          * when it's derived from the timestamps. So let's wait for the
 455          * pipe to start properly before we call drm_crtc_vblank_on()
 456          */
 457         if (intel_crtc_max_vblank_count(new_crtc_state) == 0)
 458                 intel_wait_for_pipe_scanline_moving(crtc);
 459 }
 460
 461 void intel_disable_transcoder(const struct intel_crtc_state *old_crtc_state)
 462 {
 463         struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc);
 464         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 465         enum transcoder cpu_transcoder = old_crtc_state->cpu_transcoder;
 466         enum pipe pipe = crtc->pipe;
 467         i915_reg_t reg;
 468         u32 val;
 469
 470         drm_dbg_kms(&dev_priv->drm, "disabling pipe %c\n", pipe_name(pipe));
 471
 472         /*
 473          * Make sure planes won't keep trying to pump pixels to us,
 474          * or we might hang the display.
 475          */
 476         assert_planes_disabled(crtc);
 477
 478         reg = TRANSCONF(cpu_transcoder);
 479         val = intel_de_read(dev_priv, reg);
 480         if ((val & TRANSCONF_ENABLE) == 0)
 481                 return;
 482
 483         /*
 484          * Double wide has implications for planes
 485          * so best keep it disabled when not needed.
 486          */
 487         if (old_crtc_state->double_wide)
 488                 val &= ~TRANSCONF_DOUBLE_WIDE;
 489
 490         /* Don't disable pipe or pipe PLLs if needed */
 491         if (!IS_I830(dev_priv))
 492                 val &= ~TRANSCONF_ENABLE;
 493
 494         if (DISPLAY_VER(dev_priv) >= 14)
 495                 intel_de_rmw(dev_priv, MTL_CHICKEN_TRANS(cpu_transcoder),
 496                              FECSTALL_DIS_DPTSTREAM_DPTTG, 0);
 497         else if (DISPLAY_VER(dev_priv) >= 12)
 498                 intel_de_rmw(dev_priv, CHICKEN_TRANS(cpu_transcoder),
 499                              FECSTALL_DIS_DPTSTREAM_DPTTG, 0);
 500
 501         intel_de_write(dev_priv, reg, val);
 502         if ((val & TRANSCONF_ENABLE) == 0)
 503                 intel_wait_for_pipe_off(old_crtc_state);
 504 }
 505
 506 unsigned int intel_rotation_info_size(const struct intel_rotation_info *rot_info)
 507 {
 508         unsigned int size = 0;
 509         int i;
 510
 511         for (i = 0 ; i < ARRAY_SIZE(rot_info->plane); i++)
 512                 size += rot_info->plane[i].dst_stride * rot_info->plane[i].width;
 513
 514         return size;
 515 }
 516
 517 unsigned int intel_remapped_info_size(const struct intel_remapped_info *rem_info)
 518 {
 519         unsigned int size = 0;
 520         int i;
 521
 522         for (i = 0 ; i < ARRAY_SIZE(rem_info->plane); i++) {
 523                 unsigned int plane_size;
 524
 525                 if (rem_info->plane[i].linear)
 526                         plane_size = rem_info->plane[i].size;
 527                 else
 528                         plane_size = rem_info->plane[i].dst_stride * rem_info->plane[i].height;
 529
 530                 if (plane_size == 0)
 531                         continue;
 532
 533                 if (rem_info->plane_alignment)
 534                         size = ALIGN(size, rem_info->plane_alignment);
 535
 536                 size += plane_size;
 537         }
 538
 539         return size;
 540 }
 541
 542 bool intel_plane_uses_fence(const struct intel_plane_state *plane_state)
 543 {
 544         struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);
 545         struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
 546
 547         return DISPLAY_VER(dev_priv) < 4 ||
 548                 (plane->fbc &&
 549                  plane_state->view.gtt.type == I915_GTT_VIEW_NORMAL);
 550 }
 551
 552 /*
 553  * Convert the x/y offsets into a linear offset.
 554  * Only valid with 0/180 degree rotation, which is fine since linear
 555  * offset is only used with linear buffers on pre-hsw and tiled buffers
 556  * with gen2/3, and 90/270 degree rotations isn't supported on any of them.
 557  */
 558 u32 intel_fb_xy_to_linear(int x, int y,
 559                           const struct intel_plane_state *state,
 560                           int color_plane)
 561 {
 562         const struct drm_framebuffer *fb = state->hw.fb;
 563         unsigned int cpp = fb->format->cpp[color_plane];
 564         unsigned int pitch = state->view.color_plane[color_plane].mapping_stride;
 565
 566         return y * pitch + x * cpp;
 567 }
 568
 569 /*
 570  * Add the x/y offsets derived from fb->offsets[] to the user
 571  * specified plane src x/y offsets. The resulting x/y offsets
 572  * specify the start of scanout from the beginning of the gtt mapping.
 573  */
 574 void intel_add_fb_offsets(int *x, int *y,
 575                           const struct intel_plane_state *state,
 576                           int color_plane)
 577
 578 {
 579         *x += state->view.color_plane[color_plane].x;
 580         *y += state->view.color_plane[color_plane].y;
 581 }
 582
 583 u32 intel_plane_fb_max_stride(struct drm_i915_private *dev_priv,
 584                               u32 pixel_format, u64 modifier)
 585 {
 586         struct intel_crtc *crtc;
 587         struct intel_plane *plane;
 588
 589         if (!HAS_DISPLAY(dev_priv))
 590                 return 0;
 591
 592         /*
 593          * We assume the primary plane for pipe A has
 594          * the highest stride limits of them all,
 595          * if in case pipe A is disabled, use the first pipe from pipe_mask.
 596          */
 597         crtc = intel_first_crtc(dev_priv);
 598         if (!crtc)
 599                 return 0;
 600
 601         plane = to_intel_plane(crtc->base.primary);
 602
 603         return plane->max_stride(plane, pixel_format, modifier,
 604                                  DRM_MODE_ROTATE_0);
 605 }
 606
 607 void intel_set_plane_visible(struct intel_crtc_state *crtc_state,
 608                              struct intel_plane_state *plane_state,
 609                              bool visible)
 610 {
 611         struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);
 612
 613         plane_state->uapi.visible = visible;
 614
 615         if (visible)
 616                 crtc_state->uapi.plane_mask |= drm_plane_mask(&plane->base);
 617         else
 618                 crtc_state->uapi.plane_mask &= ~drm_plane_mask(&plane->base);
 619 }
 620
 621 void intel_plane_fixup_bitmasks(struct intel_crtc_state *crtc_state)
 622 {
 623         struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
 624         struct drm_plane *plane;
 625
 626         /*
 627          * Active_planes aliases if multiple "primary" or cursor planes
 628          * have been used on the same (or wrong) pipe. plane_mask uses
 629          * unique ids, hence we can use that to reconstruct active_planes.
 630          */
 631         crtc_state->enabled_planes = 0;
 632         crtc_state->active_planes = 0;
 633
 634         drm_for_each_plane_mask(plane, &dev_priv->drm,
 635                                 crtc_state->uapi.plane_mask) {
 636                 crtc_state->enabled_planes |= BIT(to_intel_plane(plane)->id);
 637                 crtc_state->active_planes |= BIT(to_intel_plane(plane)->id);
 638         }
 639 }
 640
 641 void intel_plane_disable_noatomic(struct intel_crtc *crtc,
 642                                   struct intel_plane *plane)
 643 {
 644         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 645         struct intel_crtc_state *crtc_state =
 646                 to_intel_crtc_state(crtc->base.state);
 647         struct intel_plane_state *plane_state =
 648                 to_intel_plane_state(plane->base.state);
 649
 650         drm_dbg_kms(&dev_priv->drm,
 651                     "Disabling [PLANE:%d:%s] on [CRTC:%d:%s]\n",
 652                     plane->base.base.id, plane->base.name,
 653                     crtc->base.base.id, crtc->base.name);
 654
 655         intel_set_plane_visible(crtc_state, plane_state, false);
 656         intel_plane_fixup_bitmasks(crtc_state);
 657         crtc_state->data_rate[plane->id] = 0;
 658         crtc_state->data_rate_y[plane->id] = 0;
 659         crtc_state->rel_data_rate[plane->id] = 0;
 660         crtc_state->rel_data_rate_y[plane->id] = 0;
 661         crtc_state->min_cdclk[plane->id] = 0;
 662
 663         if ((crtc_state->active_planes & ~BIT(PLANE_CURSOR)) == 0 &&
 664             hsw_ips_disable(crtc_state)) {
 665                 crtc_state->ips_enabled = false;
 666                 intel_crtc_wait_for_next_vblank(crtc);
 667         }
 668
 669         /*
 670          * Vblank time updates from the shadow to live plane control register
 671          * are blocked if the memory self-refresh mode is active at that
 672          * moment. So to make sure the plane gets truly disabled, disable
 673          * first the self-refresh mode. The self-refresh enable bit in turn
 674          * will be checked/applied by the HW only at the next frame start
 675          * event which is after the vblank start event, so we need to have a
 676          * wait-for-vblank between disabling the plane and the pipe.
 677          */
 678         if (HAS_GMCH(dev_priv) &&
 679             intel_set_memory_cxsr(dev_priv, false))
 680                 intel_crtc_wait_for_next_vblank(crtc);
 681
 682         /*
 683          * Gen2 reports pipe underruns whenever all planes are disabled.
 684          * So disable underrun reporting before all the planes get disabled.
 685          */
 686         if (DISPLAY_VER(dev_priv) == 2 && !crtc_state->active_planes)
 687                 intel_set_cpu_fifo_underrun_reporting(dev_priv, crtc->pipe, false);
 688
 689         intel_plane_disable_arm(plane, crtc_state);
 690         intel_crtc_wait_for_next_vblank(crtc);
 691 }
 692
 693 unsigned int
 694 intel_plane_fence_y_offset(const struct intel_plane_state *plane_state)
 695 {
 696         int x = 0, y = 0;
 697
 698         intel_plane_adjust_aligned_offset(&x, &y, plane_state, 0,
 699                                           plane_state->view.color_plane[0].offset, 0);
 700
 701         return y;
 702 }
 703
 704 static int
 705 intel_display_commit_duplicated_state(struct intel_atomic_state *state,
 706                                       struct drm_modeset_acquire_ctx *ctx)
 707 {
 708         struct drm_i915_private *i915 = to_i915(state->base.dev);
 709         int ret;
 710
 711         ret = drm_atomic_helper_commit_duplicated_state(&state->base, ctx);
 712
 713         drm_WARN_ON(&i915->drm, ret == -EDEADLK);
 714
 715         return ret;
 716 }
 717
 718 static int
 719 __intel_display_resume(struct drm_i915_private *i915,
 720                        struct drm_atomic_state *state,
 721                        struct drm_modeset_acquire_ctx *ctx)
 722 {
 723         struct drm_crtc_state *crtc_state;
 724         struct drm_crtc *crtc;
 725         int i;
 726
 727         intel_modeset_setup_hw_state(i915, ctx);
 728         intel_vga_redisable(i915);
 729
 730         if (!state)
 731                 return 0;
 732
 733         /*
 734          * We've duplicated the state, pointers to the old state are invalid.
 735          *
 736          * Don't attempt to use the old state until we commit the duplicated state.
 737          */
 738         for_each_new_crtc_in_state(state, crtc, crtc_state, i) {
 739                 /*
 740                  * Force recalculation even if we restore
 741                  * current state. With fast modeset this may not result
 742                  * in a modeset when the state is compatible.
 743                  */
 744                 crtc_state->mode_changed = true;
 745         }
 746
 747         /* ignore any reset values/BIOS leftovers in the WM registers */
 748         if (!HAS_GMCH(i915))
 749                 to_intel_atomic_state(state)->skip_intermediate_wm = true;
 750
 751         return intel_display_commit_duplicated_state(to_intel_atomic_state(state), ctx);
 752 }
 753
 754 static bool gpu_reset_clobbers_display(struct drm_i915_private *dev_priv)
 755 {
 756         return (INTEL_INFO(dev_priv)->gpu_reset_clobbers_display &&
 757                 intel_has_gpu_reset(to_gt(dev_priv)));
 758 }
 759
 760 void intel_display_prepare_reset(struct drm_i915_private *dev_priv)
 761 {
 762         struct drm_modeset_acquire_ctx *ctx = &dev_priv->display.restore.reset_ctx;
 763         struct drm_atomic_state *state;
 764         int ret;
 765
 766         if (!HAS_DISPLAY(dev_priv))
 767                 return;
 768
 769         /* reset doesn't touch the display */
 770         if (!dev_priv->params.force_reset_modeset_test &&
 771             !gpu_reset_clobbers_display(dev_priv))
 772                 return;
 773
 774         /* We have a modeset vs reset deadlock, defensively unbreak it. */
 775         set_bit(I915_RESET_MODESET, &to_gt(dev_priv)->reset.flags);
 776         smp_mb__after_atomic();
 777         wake_up_bit(&to_gt(dev_priv)->reset.flags, I915_RESET_MODESET);
 778
 779         if (atomic_read(&dev_priv->gpu_error.pending_fb_pin)) {
 780                 drm_dbg_kms(&dev_priv->drm,
 781                             "Modeset potentially stuck, unbreaking through wedging\n");
 782                 intel_gt_set_wedged(to_gt(dev_priv));
 783         }
 784
 785         /*
 786          * Need mode_config.mutex so that we don't
 787          * trample ongoing ->detect() and whatnot.
 788          */
 789         mutex_lock(&dev_priv->drm.mode_config.mutex);
 790         drm_modeset_acquire_init(ctx, 0);
 791         while (1) {
 792                 ret = drm_modeset_lock_all_ctx(&dev_priv->drm, ctx);
 793                 if (ret != -EDEADLK)
 794                         break;
 795
 796                 drm_modeset_backoff(ctx);
 797         }
 798         /*
 799          * Disabling the crtcs gracefully seems nicer. Also the
 800          * g33 docs say we should at least disable all the planes.
 801          */
 802         state = drm_atomic_helper_duplicate_state(&dev_priv->drm, ctx);
 803         if (IS_ERR(state)) {
 804                 ret = PTR_ERR(state);
 805                 drm_err(&dev_priv->drm, "Duplicating state failed with %i\n",
 806                         ret);
 807                 return;
 808         }
 809
 810         ret = drm_atomic_helper_disable_all(&dev_priv->drm, ctx);
 811         if (ret) {
 812                 drm_err(&dev_priv->drm, "Suspending crtc's failed with %i\n",
 813                         ret);
 814                 drm_atomic_state_put(state);
 815                 return;
 816         }
 817
 818         dev_priv->display.restore.modeset_state = state;
 819         state->acquire_ctx = ctx;
 820 }
 821
 822 void intel_display_finish_reset(struct drm_i915_private *i915)
 823 {
 824         struct drm_modeset_acquire_ctx *ctx = &i915->display.restore.reset_ctx;
 825         struct drm_atomic_state *state;
 826         int ret;
 827
 828         if (!HAS_DISPLAY(i915))
 829                 return;
 830
 831         /* reset doesn't touch the display */
 832         if (!test_bit(I915_RESET_MODESET, &to_gt(i915)->reset.flags))
 833                 return;
 834
 835         state = fetch_and_zero(&i915->display.restore.modeset_state);
 836         if (!state)
 837                 goto unlock;
 838
 839         /* reset doesn't touch the display */
 840         if (!gpu_reset_clobbers_display(i915)) {
 841                 /* for testing only restore the display */
 842                 ret = intel_display_commit_duplicated_state(to_intel_atomic_state(state), ctx);
 843                 if (ret)
 844                         drm_err(&i915->drm,
 845                                 "Restoring old state failed with %i\n", ret);
 846         } else {
 847                 /*
 848                  * The display has been reset as well,
 849                  * so need a full re-initialization.
 850                  */
 851                 intel_pps_unlock_regs_wa(i915);
 852                 intel_modeset_init_hw(i915);
 853                 intel_clock_gating_init(i915);
 854                 intel_hpd_init(i915);
 855
 856                 ret = __intel_display_resume(i915, state, ctx);
 857                 if (ret)
 858                         drm_err(&i915->drm,
 859                                 "Restoring old state failed with %i\n", ret);
 860
 861                 intel_hpd_poll_disable(i915);
 862         }
 863
 864         drm_atomic_state_put(state);
 865 unlock:
 866         drm_modeset_drop_locks(ctx);
 867         drm_modeset_acquire_fini(ctx);
 868         mutex_unlock(&i915->drm.mode_config.mutex);
 869
 870         clear_bit_unlock(I915_RESET_MODESET, &to_gt(i915)->reset.flags);
 871 }
 872
 873 static void icl_set_pipe_chicken(const struct intel_crtc_state *crtc_state)
 874 {
 875         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
 876         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 877         enum pipe pipe = crtc->pipe;
 878         u32 tmp;
 879
 880         tmp = intel_de_read(dev_priv, PIPE_CHICKEN(pipe));
 881
 882         /*
 883          * Display WA #1153: icl
 884          * enable hardware to bypass the alpha math
 885          * and rounding for per-pixel values 00 and 0xff
 886          */
 887         tmp |= PER_PIXEL_ALPHA_BYPASS_EN;
 888         /*
 889          * Display WA # 1605353570: icl
 890          * Set the pixel rounding bit to 1 for allowing
 891          * passthrough of Frame buffer pixels unmodified
 892          * across pipe
 893          */
 894         tmp |= PIXEL_ROUNDING_TRUNC_FB_PASSTHRU;
 895
 896         /*
 897          * Underrun recovery must always be disabled on display 13+.
 898          * DG2 chicken bit meaning is inverted compared to other platforms.
 899          */
 900         if (IS_DG2(dev_priv))
 901                 tmp &= ~UNDERRUN_RECOVERY_ENABLE_DG2;
 902         else if (DISPLAY_VER(dev_priv) >= 13)
 903                 tmp |= UNDERRUN_RECOVERY_DISABLE_ADLP;
 904
 905         /* Wa_14010547955:dg2 */
 906         if (IS_DG2_DISPLAY_STEP(dev_priv, STEP_B0, STEP_FOREVER))
 907                 tmp |= DG2_RENDER_CCSTAG_4_3_EN;
 908
 909         intel_de_write(dev_priv, PIPE_CHICKEN(pipe), tmp);
 910 }
 911
 912 bool intel_has_pending_fb_unpin(struct drm_i915_private *dev_priv)
 913 {
 914         struct drm_crtc *crtc;
 915         bool cleanup_done;
 916
 917         drm_for_each_crtc(crtc, &dev_priv->drm) {
 918                 struct drm_crtc_commit *commit;
 919                 spin_lock(&crtc->commit_lock);
 920                 commit = list_first_entry_or_null(&crtc->commit_list,
 921                                                   struct drm_crtc_commit, commit_entry);
 922                 cleanup_done = commit ?
 923                         try_wait_for_completion(&commit->cleanup_done) : true;
 924                 spin_unlock(&crtc->commit_lock);
 925
 926                 if (cleanup_done)
 927                         continue;
 928
 929                 intel_crtc_wait_for_next_vblank(to_intel_crtc(crtc));
 930
 931                 return true;
 932         }
 933
 934         return false;
 935 }
 936
 937 /*
 938  * Finds the encoder associated with the given CRTC. This can only be
 939  * used when we know that the CRTC isn't feeding multiple encoders!
 940  */
 941 struct intel_encoder *
 942 intel_get_crtc_new_encoder(const struct intel_atomic_state *state,
 943                            const struct intel_crtc_state *crtc_state)
 944 {
 945         const struct drm_connector_state *connector_state;
 946         const struct drm_connector *connector;
 947         struct intel_encoder *encoder = NULL;
 948         struct intel_crtc *master_crtc;
 949         int num_encoders = 0;
 950         int i;
 951
 952         master_crtc = intel_master_crtc(crtc_state);
 953
 954         for_each_new_connector_in_state(&state->base, connector, connector_state, i) {
 955                 if (connector_state->crtc != &master_crtc->base)
 956                         continue;
 957
 958                 encoder = to_intel_encoder(connector_state->best_encoder);
 959                 num_encoders++;
 960         }
 961
 962         drm_WARN(state->base.dev, num_encoders != 1,
 963                  "%d encoders for pipe %c\n",
 964                  num_encoders, pipe_name(master_crtc->pipe));
 965
 966         return encoder;
 967 }
 968
 969 static void ilk_pfit_enable(const struct intel_crtc_state *crtc_state)
 970 {
 971         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
 972         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 973         const struct drm_rect *dst = &crtc_state->pch_pfit.dst;
 974         enum pipe pipe = crtc->pipe;
 975         int width = drm_rect_width(dst);
 976         int height = drm_rect_height(dst);
 977         int x = dst->x1;
 978         int y = dst->y1;
 979
 980         if (!crtc_state->pch_pfit.enabled)
 981                 return;
 982
 983         /* Force use of hard-coded filter coefficients
 984          * as some pre-programmed values are broken,
 985          * e.g. x201.
 986          */
 987         if (IS_IVYBRIDGE(dev_priv) || IS_HASWELL(dev_priv))
 988                 intel_de_write_fw(dev_priv, PF_CTL(pipe), PF_ENABLE |
 989                                   PF_FILTER_MED_3x3 | PF_PIPE_SEL_IVB(pipe));
 990         else
 991                 intel_de_write_fw(dev_priv, PF_CTL(pipe), PF_ENABLE |
 992                                   PF_FILTER_MED_3x3);
 993         intel_de_write_fw(dev_priv, PF_WIN_POS(pipe), x << 16 | y);
 994         intel_de_write_fw(dev_priv, PF_WIN_SZ(pipe), width << 16 | height);
 995 }
 996
 997 static void intel_crtc_dpms_overlay_disable(struct intel_crtc *crtc)
 998 {
 999         if (crtc->overlay)
1000                 (void) intel_overlay_switch_off(crtc->overlay);
1001
1002         /* Let userspace switch the overlay on again. In most cases userspace
1003          * has to recompute where to put it anyway.
1004          */
1005 }
1006
1007 static bool needs_nv12_wa(const struct intel_crtc_state *crtc_state)
1008 {
1009         struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
1010
1011         if (!crtc_state->nv12_planes)
1012                 return false;
1013
1014         /* WA Display #0827: Gen9:all */
1015         if (DISPLAY_VER(dev_priv) == 9)
1016                 return true;
1017
1018         return false;
1019 }
1020
1021 static bool needs_scalerclk_wa(const struct intel_crtc_state *crtc_state)
1022 {
1023         struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
1024
1025         /* Wa_2006604312:icl,ehl */
1026         if (crtc_state->scaler_state.scaler_users > 0 && DISPLAY_VER(dev_priv) == 11)
1027                 return true;
1028
1029         return false;
1030 }
1031
1032 static bool needs_cursorclk_wa(const struct intel_crtc_state *crtc_state)
1033 {
1034         struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
1035
1036         /* Wa_1604331009:icl,jsl,ehl */
1037         if (is_hdr_mode(crtc_state) &&
1038             crtc_state->active_planes & BIT(PLANE_CURSOR) &&
1039             DISPLAY_VER(dev_priv) == 11)
1040                 return true;
1041
1042         return false;
1043 }
1044
1045 static void intel_async_flip_vtd_wa(struct drm_i915_private *i915,
1046                                     enum pipe pipe, bool enable)
1047 {
1048         if (DISPLAY_VER(i915) == 9) {
1049                 /*
1050                  * "Plane N strech max must be programmed to 11b (x1)
1051                  *  when Async flips are enabled on that plane."
1052                  */
1053                 intel_de_rmw(i915, CHICKEN_PIPESL_1(pipe),
1054                              SKL_PLANE1_STRETCH_MAX_MASK,
1055                              enable ? SKL_PLANE1_STRETCH_MAX_X1 : SKL_PLANE1_STRETCH_MAX_X8);
1056         } else {
1057                 /* Also needed on HSW/BDW albeit undocumented */
1058                 intel_de_rmw(i915, CHICKEN_PIPESL_1(pipe),
1059                              HSW_PRI_STRETCH_MAX_MASK,
1060                              enable ? HSW_PRI_STRETCH_MAX_X1 : HSW_PRI_STRETCH_MAX_X8);
1061         }
1062 }
1063
1064 static bool needs_async_flip_vtd_wa(const struct intel_crtc_state *crtc_state)
1065 {
1066         struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev);
1067
1068         return crtc_state->uapi.async_flip && i915_vtd_active(i915) &&
1069                 (DISPLAY_VER(i915) == 9 || IS_BROADWELL(i915) || IS_HASWELL(i915));
1070 }
1071
1072 static bool planes_enabling(const struct intel_crtc_state *old_crtc_state,
1073                             const struct intel_crtc_state *new_crtc_state)
1074 {
1075         return (!old_crtc_state->active_planes || intel_crtc_needs_modeset(new_crtc_state)) &&
1076                 new_crtc_state->active_planes;
1077 }
1078
1079 static bool planes_disabling(const struct intel_crtc_state *old_crtc_state,
1080                              const struct intel_crtc_state *new_crtc_state)
1081 {
1082         return old_crtc_state->active_planes &&
1083                 (!new_crtc_state->active_planes || intel_crtc_needs_modeset(new_crtc_state));
1084 }
1085
1086 static void intel_post_plane_update(struct intel_atomic_state *state,
1087                                     struct intel_crtc *crtc)
1088 {
1089         struct drm_i915_private *dev_priv = to_i915(state->base.dev);
1090         const struct intel_crtc_state *old_crtc_state =
1091                 intel_atomic_get_old_crtc_state(state, crtc);
1092         const struct intel_crtc_state *new_crtc_state =
1093                 intel_atomic_get_new_crtc_state(state, crtc);
1094         enum pipe pipe = crtc->pipe;
1095
1096         intel_frontbuffer_flip(dev_priv, new_crtc_state->fb_bits);
1097
1098         if (new_crtc_state->update_wm_post && new_crtc_state->hw.active)
1099                 intel_update_watermarks(dev_priv);
1100
1101         intel_fbc_post_update(state, crtc);
1102
1103         if (needs_async_flip_vtd_wa(old_crtc_state) &&
1104             !needs_async_flip_vtd_wa(new_crtc_state))
1105                 intel_async_flip_vtd_wa(dev_priv, pipe, false);
1106
1107         if (needs_nv12_wa(old_crtc_state) &&
1108             !needs_nv12_wa(new_crtc_state))
1109                 skl_wa_827(dev_priv, pipe, false);
1110
1111         if (needs_scalerclk_wa(old_crtc_state) &&
1112             !needs_scalerclk_wa(new_crtc_state))
1113                 icl_wa_scalerclkgating(dev_priv, pipe, false);
1114
1115         if (needs_cursorclk_wa(old_crtc_state) &&
1116             !needs_cursorclk_wa(new_crtc_state))
1117                 icl_wa_cursorclkgating(dev_priv, pipe, false);
1118
1119         if (intel_crtc_needs_color_update(new_crtc_state))
1120                 intel_color_post_update(new_crtc_state);
1121 }
1122
1123 static void intel_crtc_enable_flip_done(struct intel_atomic_state *state,
1124                                         struct intel_crtc *crtc)
1125 {
1126         const struct intel_crtc_state *crtc_state =
1127                 intel_atomic_get_new_crtc_state(state, crtc);
1128         u8 update_planes = crtc_state->update_planes;
1129         const struct intel_plane_state *plane_state;
1130         struct intel_plane *plane;
1131         int i;
1132
1133         for_each_new_intel_plane_in_state(state, plane, plane_state, i) {
1134                 if (plane->pipe == crtc->pipe &&
1135                     update_planes & BIT(plane->id))
1136                         plane->enable_flip_done(plane);
1137         }
1138 }
1139
1140 static void intel_crtc_disable_flip_done(struct intel_atomic_state *state,
1141                                          struct intel_crtc *crtc)
1142 {
1143         const struct intel_crtc_state *crtc_state =
1144                 intel_atomic_get_new_crtc_state(state, crtc);
1145         u8 update_planes = crtc_state->update_planes;
1146         const struct intel_plane_state *plane_state;
1147         struct intel_plane *plane;
1148         int i;
1149
1150         for_each_new_intel_plane_in_state(state, plane, plane_state, i) {
1151                 if (plane->pipe == crtc->pipe &&
1152                     update_planes & BIT(plane->id))
1153                         plane->disable_flip_done(plane);
1154         }
1155 }
1156
1157 static void intel_crtc_async_flip_disable_wa(struct intel_atomic_state *state,
1158                                              struct intel_crtc *crtc)
1159 {
1160         const struct intel_crtc_state *old_crtc_state =
1161                 intel_atomic_get_old_crtc_state(state, crtc);
1162         const struct intel_crtc_state *new_crtc_state =
1163                 intel_atomic_get_new_crtc_state(state, crtc);
1164         u8 disable_async_flip_planes = old_crtc_state->async_flip_planes &
1165                                        ~new_crtc_state->async_flip_planes;
1166         const struct intel_plane_state *old_plane_state;
1167         struct intel_plane *plane;
1168         bool need_vbl_wait = false;
1169         int i;
1170
1171         for_each_old_intel_plane_in_state(state, plane, old_plane_state, i) {
1172                 if (plane->need_async_flip_disable_wa &&
1173                     plane->pipe == crtc->pipe &&
1174                     disable_async_flip_planes & BIT(plane->id)) {
1175                         /*
1176                          * Apart from the async flip bit we want to
1177                          * preserve the old state for the plane.
1178                          */
1179                         plane->async_flip(plane, old_crtc_state,
1180                                           old_plane_state, false);
1181                         need_vbl_wait = true;
1182                 }
1183         }
1184
1185         if (need_vbl_wait)
1186                 intel_crtc_wait_for_next_vblank(crtc);
1187 }
1188
1189 static void intel_pre_plane_update(struct intel_atomic_state *state,
1190                                    struct intel_crtc *crtc)
1191 {
1192         struct drm_i915_private *dev_priv = to_i915(state->base.dev);
1193         const struct intel_crtc_state *old_crtc_state =
1194                 intel_atomic_get_old_crtc_state(state, crtc);
1195         const struct intel_crtc_state *new_crtc_state =
1196                 intel_atomic_get_new_crtc_state(state, crtc);
1197         enum pipe pipe = crtc->pipe;
1198
1199         intel_drrs_deactivate(old_crtc_state);
1200
1201         intel_psr_pre_plane_update(state, crtc);
1202
1203         if (hsw_ips_pre_update(state, crtc))
1204                 intel_crtc_wait_for_next_vblank(crtc);
1205
1206         if (intel_fbc_pre_update(state, crtc))
1207                 intel_crtc_wait_for_next_vblank(crtc);
1208
1209         if (!needs_async_flip_vtd_wa(old_crtc_state) &&
1210             needs_async_flip_vtd_wa(new_crtc_state))
1211                 intel_async_flip_vtd_wa(dev_priv, pipe, true);
1212
1213         /* Display WA 827 */
1214         if (!needs_nv12_wa(old_crtc_state) &&
1215             needs_nv12_wa(new_crtc_state))
1216                 skl_wa_827(dev_priv, pipe, true);
1217
1218         /* Wa_2006604312:icl,ehl */
1219         if (!needs_scalerclk_wa(old_crtc_state) &&
1220             needs_scalerclk_wa(new_crtc_state))
1221                 icl_wa_scalerclkgating(dev_priv, pipe, true);
1222
1223         /* Wa_1604331009:icl,jsl,ehl */
1224         if (!needs_cursorclk_wa(old_crtc_state) &&
1225             needs_cursorclk_wa(new_crtc_state))
1226                 icl_wa_cursorclkgating(dev_priv, pipe, true);
1227
1228         /*
1229          * Vblank time updates from the shadow to live plane control register
1230          * are blocked if the memory self-refresh mode is active at that
1231          * moment. So to make sure the plane gets truly disabled, disable
1232          * first the self-refresh mode. The self-refresh enable bit in turn
1233          * will be checked/applied by the HW only at the next frame start
1234          * event which is after the vblank start event, so we need to have a
1235          * wait-for-vblank between disabling the plane and the pipe.
1236          */
1237         if (HAS_GMCH(dev_priv) && old_crtc_state->hw.active &&
1238             new_crtc_state->disable_cxsr && intel_set_memory_cxsr(dev_priv, false))
1239                 intel_crtc_wait_for_next_vblank(crtc);
1240
1241         /*
1242          * IVB workaround: must disable low power watermarks for at least
1243          * one frame before enabling scaling.  LP watermarks can be re-enabled
1244          * when scaling is disabled.
1245          *
1246          * WaCxSRDisabledForSpriteScaling:ivb
1247          */
1248         if (old_crtc_state->hw.active &&
1249             new_crtc_state->disable_lp_wm && ilk_disable_lp_wm(dev_priv))
1250                 intel_crtc_wait_for_next_vblank(crtc);
1251
1252         /*
1253          * If we're doing a modeset we don't need to do any
1254          * pre-vblank watermark programming here.
1255          */
1256         if (!intel_crtc_needs_modeset(new_crtc_state)) {
1257                 /*
1258                  * For platforms that support atomic watermarks, program the
1259                  * 'intermediate' watermarks immediately.  On pre-gen9 platforms, these
1260                  * will be the intermediate values that are safe for both pre- and
1261                  * post- vblank; when vblank happens, the 'active' values will be set
1262                  * to the final 'target' values and we'll do this again to get the
1263                  * optimal watermarks.  For gen9+ platforms, the values we program here
1264                  * will be the final target values which will get automatically latched
1265                  * at vblank time; no further programming will be necessary.
1266                  *
1267                  * If a platform hasn't been transitioned to atomic watermarks yet,
1268                  * we'll continue to update watermarks the old way, if flags tell
1269                  * us to.
1270                  */
1271                 if (!intel_initial_watermarks(state, crtc))
1272                         if (new_crtc_state->update_wm_pre)
1273                                 intel_update_watermarks(dev_priv);
1274         }
1275
1276         /*
1277          * Gen2 reports pipe underruns whenever all planes are disabled.
1278          * So disable underrun reporting before all the planes get disabled.
1279          *
1280          * We do this after .initial_watermarks() so that we have a
1281          * chance of catching underruns with the intermediate watermarks
1282          * vs. the old plane configuration.
1283          */
1284         if (DISPLAY_VER(dev_priv) == 2 && planes_disabling(old_crtc_state, new_crtc_state))
1285                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
1286
1287         /*
1288          * WA for platforms where async address update enable bit
1289          * is double buffered and only latched at start of vblank.
1290          */
1291         if (old_crtc_state->async_flip_planes & ~new_crtc_state->async_flip_planes)
1292                 intel_crtc_async_flip_disable_wa(state, crtc);
1293 }
1294
1295 static void intel_crtc_disable_planes(struct intel_atomic_state *state,
1296                                       struct intel_crtc *crtc)
1297 {
1298         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1299         const struct intel_crtc_state *new_crtc_state =
1300                 intel_atomic_get_new_crtc_state(state, crtc);
1301         unsigned int update_mask = new_crtc_state->update_planes;
1302         const struct intel_plane_state *old_plane_state;
1303         struct intel_plane *plane;
1304         unsigned fb_bits = 0;
1305         int i;
1306
1307         intel_crtc_dpms_overlay_disable(crtc);
1308
1309         for_each_old_intel_plane_in_state(state, plane, old_plane_state, i) {
1310                 if (crtc->pipe != plane->pipe ||
1311                     !(update_mask & BIT(plane->id)))
1312                         continue;
1313
1314                 intel_plane_disable_arm(plane, new_crtc_state);
1315
1316                 if (old_plane_state->uapi.visible)
1317                         fb_bits |= plane->frontbuffer_bit;
1318         }
1319
1320         intel_frontbuffer_flip(dev_priv, fb_bits);
1321 }
1322
1323 static void intel_encoders_update_prepare(struct intel_atomic_state *state)
1324 {
1325         struct drm_i915_private *i915 = to_i915(state->base.dev);
1326         struct intel_crtc_state *new_crtc_state, *old_crtc_state;
1327         struct intel_crtc *crtc;
1328         int i;
1329
1330         /*
1331          * Make sure the DPLL state is up-to-date for fastset TypeC ports after non-blocking commits.
1332          * TODO: Update the DPLL state for all cases in the encoder->update_prepare() hook.
1333          */
1334         if (i915->display.dpll.mgr) {
1335                 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
1336                         if (intel_crtc_needs_modeset(new_crtc_state))
1337                                 continue;
1338
1339                         new_crtc_state->shared_dpll = old_crtc_state->shared_dpll;
1340                         new_crtc_state->dpll_hw_state = old_crtc_state->dpll_hw_state;
1341                 }
1342         }
1343 }
1344
1345 static void intel_encoders_pre_pll_enable(struct intel_atomic_state *state,
1346                                           struct intel_crtc *crtc)
1347 {
1348         const struct intel_crtc_state *crtc_state =
1349                 intel_atomic_get_new_crtc_state(state, crtc);
1350         const struct drm_connector_state *conn_state;
1351         struct drm_connector *conn;
1352         int i;
1353
1354         for_each_new_connector_in_state(&state->base, conn, conn_state, i) {
1355                 struct intel_encoder *encoder =
1356                         to_intel_encoder(conn_state->best_encoder);
1357
1358                 if (conn_state->crtc != &crtc->base)
1359                         continue;
1360
1361                 if (encoder->pre_pll_enable)
1362                         encoder->pre_pll_enable(state, encoder,
1363                                                 crtc_state, conn_state);
1364         }
1365 }
1366
1367 static void intel_encoders_pre_enable(struct intel_atomic_state *state,
1368                                       struct intel_crtc *crtc)
1369 {
1370         const struct intel_crtc_state *crtc_state =
1371                 intel_atomic_get_new_crtc_state(state, crtc);
1372         const struct drm_connector_state *conn_state;
1373         struct drm_connector *conn;
1374         int i;
1375
1376         for_each_new_connector_in_state(&state->base, conn, conn_state, i) {
1377                 struct intel_encoder *encoder =
1378                         to_intel_encoder(conn_state->best_encoder);
1379
1380                 if (conn_state->crtc != &crtc->base)
1381                         continue;
1382
1383                 if (encoder->pre_enable)
1384                         encoder->pre_enable(state, encoder,
1385                                             crtc_state, conn_state);
1386         }
1387 }
1388
1389 static void intel_encoders_enable(struct intel_atomic_state *state,
1390                                   struct intel_crtc *crtc)
1391 {
1392         const struct intel_crtc_state *crtc_state =
1393                 intel_atomic_get_new_crtc_state(state, crtc);
1394         const struct drm_connector_state *conn_state;
1395         struct drm_connector *conn;
1396         int i;
1397
1398         for_each_new_connector_in_state(&state->base, conn, conn_state, i) {
1399                 struct intel_encoder *encoder =
1400                         to_intel_encoder(conn_state->best_encoder);
1401
1402                 if (conn_state->crtc != &crtc->base)
1403                         continue;
1404
1405                 if (encoder->enable)
1406                         encoder->enable(state, encoder,
1407                                         crtc_state, conn_state);
1408                 intel_opregion_notify_encoder(encoder, true);
1409         }
1410 }
1411
1412 static void intel_encoders_disable(struct intel_atomic_state *state,
1413                                    struct intel_crtc *crtc)
1414 {
1415         const struct intel_crtc_state *old_crtc_state =
1416                 intel_atomic_get_old_crtc_state(state, crtc);
1417         const struct drm_connector_state *old_conn_state;
1418         struct drm_connector *conn;
1419         int i;
1420
1421         for_each_old_connector_in_state(&state->base, conn, old_conn_state, i) {
1422                 struct intel_encoder *encoder =
1423                         to_intel_encoder(old_conn_state->best_encoder);
1424
1425                 if (old_conn_state->crtc != &crtc->base)
1426                         continue;
1427
1428                 intel_opregion_notify_encoder(encoder, false);
1429                 if (encoder->disable)
1430                         encoder->disable(state, encoder,
1431                                          old_crtc_state, old_conn_state);
1432         }
1433 }
1434
1435 static void intel_encoders_post_disable(struct intel_atomic_state *state,
1436                                         struct intel_crtc *crtc)
1437 {
1438         const struct intel_crtc_state *old_crtc_state =
1439                 intel_atomic_get_old_crtc_state(state, crtc);
1440         const struct drm_connector_state *old_conn_state;
1441         struct drm_connector *conn;
1442         int i;
1443
1444         for_each_old_connector_in_state(&state->base, conn, old_conn_state, i) {
1445                 struct intel_encoder *encoder =
1446                         to_intel_encoder(old_conn_state->best_encoder);
1447
1448                 if (old_conn_state->crtc != &crtc->base)
1449                         continue;
1450
1451                 if (encoder->post_disable)
1452                         encoder->post_disable(state, encoder,
1453                                               old_crtc_state, old_conn_state);
1454         }
1455 }
1456
1457 static void intel_encoders_post_pll_disable(struct intel_atomic_state *state,
1458                                             struct intel_crtc *crtc)
1459 {
1460         const struct intel_crtc_state *old_crtc_state =
1461                 intel_atomic_get_old_crtc_state(state, crtc);
1462         const struct drm_connector_state *old_conn_state;
1463         struct drm_connector *conn;
1464         int i;
1465
1466         for_each_old_connector_in_state(&state->base, conn, old_conn_state, i) {
1467                 struct intel_encoder *encoder =
1468                         to_intel_encoder(old_conn_state->best_encoder);
1469
1470                 if (old_conn_state->crtc != &crtc->base)
1471                         continue;
1472
1473                 if (encoder->post_pll_disable)
1474                         encoder->post_pll_disable(state, encoder,
1475                                                   old_crtc_state, old_conn_state);
1476         }
1477 }
1478
1479 static void intel_encoders_update_pipe(struct intel_atomic_state *state,
1480                                        struct intel_crtc *crtc)
1481 {
1482         const struct intel_crtc_state *crtc_state =
1483                 intel_atomic_get_new_crtc_state(state, crtc);
1484         const struct drm_connector_state *conn_state;
1485         struct drm_connector *conn;
1486         int i;
1487
1488         for_each_new_connector_in_state(&state->base, conn, conn_state, i) {
1489                 struct intel_encoder *encoder =
1490                         to_intel_encoder(conn_state->best_encoder);
1491
1492                 if (conn_state->crtc != &crtc->base)
1493                         continue;
1494
1495                 if (encoder->update_pipe)
1496                         encoder->update_pipe(state, encoder,
1497                                              crtc_state, conn_state);
1498         }
1499 }
1500
1501 static void intel_disable_primary_plane(const struct intel_crtc_state *crtc_state)
1502 {
1503         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
1504         struct intel_plane *plane = to_intel_plane(crtc->base.primary);
1505
1506         plane->disable_arm(plane, crtc_state);
1507 }
1508
1509 static void ilk_configure_cpu_transcoder(const struct intel_crtc_state *crtc_state)
1510 {
1511         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
1512         enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
1513
1514         if (crtc_state->has_pch_encoder) {
1515                 intel_cpu_transcoder_set_m1_n1(crtc, cpu_transcoder,
1516                                                &crtc_state->fdi_m_n);
1517         } else if (intel_crtc_has_dp_encoder(crtc_state)) {
1518                 intel_cpu_transcoder_set_m1_n1(crtc, cpu_transcoder,
1519                                                &crtc_state->dp_m_n);
1520                 intel_cpu_transcoder_set_m2_n2(crtc, cpu_transcoder,
1521                                                &crtc_state->dp_m2_n2);
1522         }
1523
1524         intel_set_transcoder_timings(crtc_state);
1525
1526         ilk_set_pipeconf(crtc_state);
1527 }
1528
1529 static void ilk_crtc_enable(struct intel_atomic_state *state,
1530                             struct intel_crtc *crtc)
1531 {
1532         const struct intel_crtc_state *new_crtc_state =
1533                 intel_atomic_get_new_crtc_state(state, crtc);
1534         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1535         enum pipe pipe = crtc->pipe;
1536
1537         if (drm_WARN_ON(&dev_priv->drm, crtc->active))
1538                 return;
1539
1540         /*
1541          * Sometimes spurious CPU pipe underruns happen during FDI
1542          * training, at least with VGA+HDMI cloning. Suppress them.
1543          *
1544          * On ILK we get an occasional spurious CPU pipe underruns
1545          * between eDP port A enable and vdd enable. Also PCH port
1546          * enable seems to result in the occasional CPU pipe underrun.
1547          *
1548          * Spurious PCH underruns also occur during PCH enabling.
1549          */
1550         intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
1551         intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false);
1552
1553         ilk_configure_cpu_transcoder(new_crtc_state);
1554
1555         intel_set_pipe_src_size(new_crtc_state);
1556
1557         crtc->active = true;
1558
1559         intel_encoders_pre_enable(state, crtc);
1560
1561         if (new_crtc_state->has_pch_encoder) {
1562                 ilk_pch_pre_enable(state, crtc);
1563         } else {
1564                 assert_fdi_tx_disabled(dev_priv, pipe);
1565                 assert_fdi_rx_disabled(dev_priv, pipe);
1566         }
1567
1568         ilk_pfit_enable(new_crtc_state);
1569
1570         /*
1571          * On ILK+ LUT must be loaded before the pipe is running but with
1572          * clocks enabled
1573          */
1574         intel_color_load_luts(new_crtc_state);
1575         intel_color_commit_noarm(new_crtc_state);
1576         intel_color_commit_arm(new_crtc_state);
1577         /* update DSPCNTR to configure gamma for pipe bottom color */
1578         intel_disable_primary_plane(new_crtc_state);
1579
1580         intel_initial_watermarks(state, crtc);
1581         intel_enable_transcoder(new_crtc_state);
1582
1583         if (new_crtc_state->has_pch_encoder)
1584                 ilk_pch_enable(state, crtc);
1585
1586         intel_crtc_vblank_on(new_crtc_state);
1587
1588         intel_encoders_enable(state, crtc);
1589
1590         if (HAS_PCH_CPT(dev_priv))
1591                 intel_wait_for_pipe_scanline_moving(crtc);
1592
1593         /*
1594          * Must wait for vblank to avoid spurious PCH FIFO underruns.
1595          * And a second vblank wait is needed at least on ILK with
1596          * some interlaced HDMI modes. Let's do the double wait always
1597          * in case there are more corner cases we don't know about.
1598          */
1599         if (new_crtc_state->has_pch_encoder) {
1600                 intel_crtc_wait_for_next_vblank(crtc);
1601                 intel_crtc_wait_for_next_vblank(crtc);
1602         }
1603         intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
1604         intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true);
1605 }
1606
1607 static void glk_pipe_scaler_clock_gating_wa(struct drm_i915_private *dev_priv,
1608                                             enum pipe pipe, bool apply)
1609 {
1610         u32 val = intel_de_read(dev_priv, CLKGATE_DIS_PSL(pipe));
1611         u32 mask = DPF_GATING_DIS | DPF_RAM_GATING_DIS | DPFR_GATING_DIS;
1612
1613         if (apply)
1614                 val |= mask;
1615         else
1616                 val &= ~mask;
1617
1618         intel_de_write(dev_priv, CLKGATE_DIS_PSL(pipe), val);
1619 }
1620
1621 static void hsw_set_linetime_wm(const struct intel_crtc_state *crtc_state)
1622 {
1623         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
1624         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1625
1626         intel_de_write(dev_priv, WM_LINETIME(crtc->pipe),
1627                        HSW_LINETIME(crtc_state->linetime) |
1628                        HSW_IPS_LINETIME(crtc_state->ips_linetime));
1629 }
1630
1631 static void hsw_set_frame_start_delay(const struct intel_crtc_state *crtc_state)
1632 {
1633         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
1634         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1635         enum transcoder transcoder = crtc_state->cpu_transcoder;
1636         i915_reg_t reg = DISPLAY_VER(dev_priv) >= 14 ? MTL_CHICKEN_TRANS(transcoder) :
1637                          CHICKEN_TRANS(transcoder);
1638
1639         intel_de_rmw(dev_priv, reg,
1640                      HSW_FRAME_START_DELAY_MASK,
1641                      HSW_FRAME_START_DELAY(crtc_state->framestart_delay - 1));
1642 }
1643
1644 static void icl_ddi_bigjoiner_pre_enable(struct intel_atomic_state *state,
1645                                          const struct intel_crtc_state *crtc_state)
1646 {
1647         struct intel_crtc *master_crtc = intel_master_crtc(crtc_state);
1648
1649         /*
1650          * Enable sequence steps 1-7 on bigjoiner master
1651          */
1652         if (intel_crtc_is_bigjoiner_slave(crtc_state))
1653                 intel_encoders_pre_pll_enable(state, master_crtc);
1654
1655         if (crtc_state->shared_dpll)
1656                 intel_enable_shared_dpll(crtc_state);
1657
1658         if (intel_crtc_is_bigjoiner_slave(crtc_state))
1659                 intel_encoders_pre_enable(state, master_crtc);
1660 }
1661
1662 static void hsw_configure_cpu_transcoder(const struct intel_crtc_state *crtc_state)
1663 {
1664         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
1665         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1666         enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
1667
1668         if (crtc_state->has_pch_encoder) {
1669                 intel_cpu_transcoder_set_m1_n1(crtc, cpu_transcoder,
1670                                                &crtc_state->fdi_m_n);
1671         } else if (intel_crtc_has_dp_encoder(crtc_state)) {
1672                 intel_cpu_transcoder_set_m1_n1(crtc, cpu_transcoder,
1673                                                &crtc_state->dp_m_n);
1674                 intel_cpu_transcoder_set_m2_n2(crtc, cpu_transcoder,
1675                                                &crtc_state->dp_m2_n2);
1676         }
1677
1678         intel_set_transcoder_timings(crtc_state);
1679
1680         if (cpu_transcoder != TRANSCODER_EDP)
1681                 intel_de_write(dev_priv, TRANS_MULT(cpu_transcoder),
1682                                crtc_state->pixel_multiplier - 1);
1683
1684         hsw_set_frame_start_delay(crtc_state);
1685
1686         hsw_set_transconf(crtc_state);
1687 }
1688
1689 static void hsw_crtc_enable(struct intel_atomic_state *state,
1690                             struct intel_crtc *crtc)
1691 {
1692         const struct intel_crtc_state *new_crtc_state =
1693                 intel_atomic_get_new_crtc_state(state, crtc);
1694         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1695         enum pipe pipe = crtc->pipe, hsw_workaround_pipe;
1696         enum transcoder cpu_transcoder = new_crtc_state->cpu_transcoder;
1697         bool psl_clkgate_wa;
1698
1699         if (drm_WARN_ON(&dev_priv->drm, crtc->active))
1700                 return;
1701
1702         intel_dmc_enable_pipe(dev_priv, crtc->pipe);
1703
1704         if (!new_crtc_state->bigjoiner_pipes) {
1705                 intel_encoders_pre_pll_enable(state, crtc);
1706
1707                 if (new_crtc_state->shared_dpll)
1708                         intel_enable_shared_dpll(new_crtc_state);
1709
1710                 intel_encoders_pre_enable(state, crtc);
1711         } else {
1712                 icl_ddi_bigjoiner_pre_enable(state, new_crtc_state);
1713         }
1714
1715         intel_dsc_enable(new_crtc_state);
1716
1717         if (DISPLAY_VER(dev_priv) >= 13)
1718                 intel_uncompressed_joiner_enable(new_crtc_state);
1719
1720         intel_set_pipe_src_size(new_crtc_state);
1721         if (DISPLAY_VER(dev_priv) >= 9 || IS_BROADWELL(dev_priv))
1722                 bdw_set_pipe_misc(new_crtc_state);
1723
1724         if (!intel_crtc_is_bigjoiner_slave(new_crtc_state) &&
1725             !transcoder_is_dsi(cpu_transcoder))
1726                 hsw_configure_cpu_transcoder(new_crtc_state);
1727
1728         crtc->active = true;
1729
1730         /* Display WA #1180: WaDisableScalarClockGating: glk */
1731         psl_clkgate_wa = DISPLAY_VER(dev_priv) == 10 &&
1732                 new_crtc_state->pch_pfit.enabled;
1733         if (psl_clkgate_wa)
1734                 glk_pipe_scaler_clock_gating_wa(dev_priv, pipe, true);
1735
1736         if (DISPLAY_VER(dev_priv) >= 9)
1737                 skl_pfit_enable(new_crtc_state);
1738         else
1739                 ilk_pfit_enable(new_crtc_state);
1740
1741         /*
1742          * On ILK+ LUT must be loaded before the pipe is running but with
1743          * clocks enabled
1744          */
1745         intel_color_load_luts(new_crtc_state);
1746         intel_color_commit_noarm(new_crtc_state);
1747         intel_color_commit_arm(new_crtc_state);
1748         /* update DSPCNTR to configure gamma/csc for pipe bottom color */
1749         if (DISPLAY_VER(dev_priv) < 9)
1750                 intel_disable_primary_plane(new_crtc_state);
1751
1752         hsw_set_linetime_wm(new_crtc_state);
1753
1754         if (DISPLAY_VER(dev_priv) >= 11)
1755                 icl_set_pipe_chicken(new_crtc_state);
1756
1757         intel_initial_watermarks(state, crtc);
1758
1759         if (intel_crtc_is_bigjoiner_slave(new_crtc_state))
1760                 intel_crtc_vblank_on(new_crtc_state);
1761
1762         intel_encoders_enable(state, crtc);
1763
1764         if (psl_clkgate_wa) {
1765                 intel_crtc_wait_for_next_vblank(crtc);
1766                 glk_pipe_scaler_clock_gating_wa(dev_priv, pipe, false);
1767         }
1768
1769         /* If we change the relative order between pipe/planes enabling, we need
1770          * to change the workaround. */
1771         hsw_workaround_pipe = new_crtc_state->hsw_workaround_pipe;
1772         if (IS_HASWELL(dev_priv) && hsw_workaround_pipe != INVALID_PIPE) {
1773                 struct intel_crtc *wa_crtc;
1774
1775                 wa_crtc = intel_crtc_for_pipe(dev_priv, hsw_workaround_pipe);
1776
1777                 intel_crtc_wait_for_next_vblank(wa_crtc);
1778                 intel_crtc_wait_for_next_vblank(wa_crtc);
1779         }
1780 }
1781
1782 void ilk_pfit_disable(const struct intel_crtc_state *old_crtc_state)
1783 {
1784         struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc);
1785         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1786         enum pipe pipe = crtc->pipe;
1787
1788         /* To avoid upsetting the power well on haswell only disable the pfit if
1789          * it's in use. The hw state code will make sure we get this right. */
1790         if (!old_crtc_state->pch_pfit.enabled)
1791                 return;
1792
1793         intel_de_write_fw(dev_priv, PF_CTL(pipe), 0);
1794         intel_de_write_fw(dev_priv, PF_WIN_POS(pipe), 0);
1795         intel_de_write_fw(dev_priv, PF_WIN_SZ(pipe), 0);
1796 }
1797
1798 static void ilk_crtc_disable(struct intel_atomic_state *state,
1799                              struct intel_crtc *crtc)
1800 {
1801         const struct intel_crtc_state *old_crtc_state =
1802                 intel_atomic_get_old_crtc_state(state, crtc);
1803         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1804         enum pipe pipe = crtc->pipe;
1805
1806         /*
1807          * Sometimes spurious CPU pipe underruns happen when the
1808          * pipe is already disabled, but FDI RX/TX is still enabled.
1809          * Happens at least with VGA+HDMI cloning. Suppress them.
1810          */
1811         intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
1812         intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false);
1813
1814         intel_encoders_disable(state, crtc);
1815
1816         intel_crtc_vblank_off(old_crtc_state);
1817
1818         intel_disable_transcoder(old_crtc_state);
1819
1820         ilk_pfit_disable(old_crtc_state);
1821
1822         if (old_crtc_state->has_pch_encoder)
1823                 ilk_pch_disable(state, crtc);
1824
1825         intel_encoders_post_disable(state, crtc);
1826
1827         if (old_crtc_state->has_pch_encoder)
1828                 ilk_pch_post_disable(state, crtc);
1829
1830         intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
1831         intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true);
1832
1833         intel_disable_shared_dpll(old_crtc_state);
1834 }
1835
1836 static void hsw_crtc_disable(struct intel_atomic_state *state,
1837                              struct intel_crtc *crtc)
1838 {
1839         const struct intel_crtc_state *old_crtc_state =
1840                 intel_atomic_get_old_crtc_state(state, crtc);
1841         struct drm_i915_private *i915 = to_i915(crtc->base.dev);
1842
1843         /*
1844          * FIXME collapse everything to one hook.
1845          * Need care with mst->ddi interactions.
1846          */
1847         if (!intel_crtc_is_bigjoiner_slave(old_crtc_state)) {
1848                 intel_encoders_disable(state, crtc);
1849                 intel_encoders_post_disable(state, crtc);
1850         }
1851
1852         intel_disable_shared_dpll(old_crtc_state);
1853
1854         if (!intel_crtc_is_bigjoiner_slave(old_crtc_state)) {
1855                 struct intel_crtc *slave_crtc;
1856
1857                 intel_encoders_post_pll_disable(state, crtc);
1858
1859                 intel_dmc_disable_pipe(i915, crtc->pipe);
1860
1861                 for_each_intel_crtc_in_pipe_mask(&i915->drm, slave_crtc,
1862                                                  intel_crtc_bigjoiner_slave_pipes(old_crtc_state))
1863                         intel_dmc_disable_pipe(i915, slave_crtc->pipe);
1864         }
1865 }
1866
1867 static void i9xx_pfit_enable(const struct intel_crtc_state *crtc_state)
1868 {
1869         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
1870         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1871
1872         if (!crtc_state->gmch_pfit.control)
1873                 return;
1874
1875         /*
1876          * The panel fitter should only be adjusted whilst the pipe is disabled,
1877          * according to register description and PRM.
1878          */
1879         drm_WARN_ON(&dev_priv->drm,
1880                     intel_de_read(dev_priv, PFIT_CONTROL) & PFIT_ENABLE);
1881         assert_transcoder_disabled(dev_priv, crtc_state->cpu_transcoder);
1882
1883         intel_de_write(dev_priv, PFIT_PGM_RATIOS,
1884                        crtc_state->gmch_pfit.pgm_ratios);
1885         intel_de_write(dev_priv, PFIT_CONTROL, crtc_state->gmch_pfit.control);
1886
1887         /* Border color in case we don't scale up to the full screen. Black by
1888          * default, change to something else for debugging. */
1889         intel_de_write(dev_priv, BCLRPAT(crtc->pipe), 0);
1890 }
1891
1892 bool intel_phy_is_combo(struct drm_i915_private *dev_priv, enum phy phy)
1893 {
1894         if (phy == PHY_NONE)
1895                 return false;
1896         else if (IS_ALDERLAKE_S(dev_priv))
1897                 return phy <= PHY_E;
1898         else if (IS_DG1(dev_priv) || IS_ROCKETLAKE(dev_priv))
1899                 return phy <= PHY_D;
1900         else if (IS_JSL_EHL(dev_priv))
1901                 return phy <= PHY_C;
1902         else if (IS_ALDERLAKE_P(dev_priv) || IS_DISPLAY_VER(dev_priv, 11, 12))
1903                 return phy <= PHY_B;
1904         else
1905                 /*
1906                  * DG2 outputs labelled as "combo PHY" in the bspec use
1907                  * SNPS PHYs with completely different programming,
1908                  * hence we always return false here.
1909                  */
1910                 return false;
1911 }
1912
1913 bool intel_phy_is_tc(struct drm_i915_private *dev_priv, enum phy phy)
1914 {
1915         if (IS_DG2(dev_priv))
1916                 /* DG2's "TC1" output uses a SNPS PHY */
1917                 return false;
1918         else if (IS_ALDERLAKE_P(dev_priv))
1919                 return phy >= PHY_F && phy <= PHY_I;
1920         else if (IS_TIGERLAKE(dev_priv))
1921                 return phy >= PHY_D && phy <= PHY_I;
1922         else if (IS_ICELAKE(dev_priv))
1923                 return phy >= PHY_C && phy <= PHY_F;
1924         else
1925                 return false;
1926 }
1927
1928 bool intel_phy_is_snps(struct drm_i915_private *dev_priv, enum phy phy)
1929 {
1930         if (phy == PHY_NONE)
1931                 return false;
1932         else if (IS_DG2(dev_priv))
1933                 /*
1934                  * All four "combo" ports and the TC1 port (PHY E) use
1935                  * Synopsis PHYs.
1936                  */
1937                 return phy <= PHY_E;
1938
1939         return false;
1940 }
1941
1942 enum phy intel_port_to_phy(struct drm_i915_private *i915, enum port port)
1943 {
1944         if (DISPLAY_VER(i915) >= 13 && port >= PORT_D_XELPD)
1945                 return PHY_D + port - PORT_D_XELPD;
1946         else if (DISPLAY_VER(i915) >= 13 && port >= PORT_TC1)
1947                 return PHY_F + port - PORT_TC1;
1948         else if (IS_ALDERLAKE_S(i915) && port >= PORT_TC1)
1949                 return PHY_B + port - PORT_TC1;
1950         else if ((IS_DG1(i915) || IS_ROCKETLAKE(i915)) && port >= PORT_TC1)
1951                 return PHY_C + port - PORT_TC1;
1952         else if (IS_JSL_EHL(i915) && port == PORT_D)
1953                 return PHY_A;
1954
1955         return PHY_A + port - PORT_A;
1956 }
1957
1958 enum tc_port intel_port_to_tc(struct drm_i915_private *dev_priv, enum port port)
1959 {
1960         if (!intel_phy_is_tc(dev_priv, intel_port_to_phy(dev_priv, port)))
1961                 return TC_PORT_NONE;
1962
1963         if (DISPLAY_VER(dev_priv) >= 12)
1964                 return TC_PORT_1 + port - PORT_TC1;
1965         else
1966                 return TC_PORT_1 + port - PORT_C;
1967 }
1968
1969 enum intel_display_power_domain
1970 intel_aux_power_domain(struct intel_digital_port *dig_port)
1971 {
1972         struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
1973
1974         if (intel_tc_port_in_tbt_alt_mode(dig_port))
1975                 return intel_display_power_tbt_aux_domain(i915, dig_port->aux_ch);
1976
1977         return intel_display_power_legacy_aux_domain(i915, dig_port->aux_ch);
1978 }
1979
1980 static void get_crtc_power_domains(struct intel_crtc_state *crtc_state,
1981                                    struct intel_power_domain_mask *mask)
1982 {
1983         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
1984         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1985         enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
1986         struct drm_encoder *encoder;
1987         enum pipe pipe = crtc->pipe;
1988
1989         bitmap_zero(mask->bits, POWER_DOMAIN_NUM);
1990
1991         if (!crtc_state->hw.active)
1992                 return;
1993
1994         set_bit(POWER_DOMAIN_PIPE(pipe), mask->bits);
1995         set_bit(POWER_DOMAIN_TRANSCODER(cpu_transcoder), mask->bits);
1996         if (crtc_state->pch_pfit.enabled ||
1997             crtc_state->pch_pfit.force_thru)
1998                 set_bit(POWER_DOMAIN_PIPE_PANEL_FITTER(pipe), mask->bits);
1999
2000         drm_for_each_encoder_mask(encoder, &dev_priv->drm,
2001                                   crtc_state->uapi.encoder_mask) {
2002                 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
2003
2004                 set_bit(intel_encoder->power_domain, mask->bits);
2005         }
2006
2007         if (HAS_DDI(dev_priv) && crtc_state->has_audio)
2008                 set_bit(POWER_DOMAIN_AUDIO_MMIO, mask->bits);
2009
2010         if (crtc_state->shared_dpll)
2011                 set_bit(POWER_DOMAIN_DISPLAY_CORE, mask->bits);
2012
2013         if (crtc_state->dsc.compression_enable)
2014                 set_bit(intel_dsc_power_domain(crtc, cpu_transcoder), mask->bits);
2015 }
2016
2017 void intel_modeset_get_crtc_power_domains(struct intel_crtc_state *crtc_state,
2018                                           struct intel_power_domain_mask *old_domains)
2019 {
2020         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
2021         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
2022         enum intel_display_power_domain domain;
2023         struct intel_power_domain_mask domains, new_domains;
2024
2025         get_crtc_power_domains(crtc_state, &domains);
2026
2027         bitmap_andnot(new_domains.bits,
2028                       domains.bits,
2029                       crtc->enabled_power_domains.mask.bits,
2030                       POWER_DOMAIN_NUM);
2031         bitmap_andnot(old_domains->bits,
2032                       crtc->enabled_power_domains.mask.bits,
2033                       domains.bits,
2034                       POWER_DOMAIN_NUM);
2035
2036         for_each_power_domain(domain, &new_domains)
2037                 intel_display_power_get_in_set(dev_priv,
2038                                                &crtc->enabled_power_domains,
2039                                                domain);
2040 }
2041
2042 void intel_modeset_put_crtc_power_domains(struct intel_crtc *crtc,
2043                                           struct intel_power_domain_mask *domains)
2044 {
2045         intel_display_power_put_mask_in_set(to_i915(crtc->base.dev),
2046                                             &crtc->enabled_power_domains,
2047                                             domains);
2048 }
2049
2050 static void i9xx_configure_cpu_transcoder(const struct intel_crtc_state *crtc_state)
2051 {
2052         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
2053         enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
2054
2055         if (intel_crtc_has_dp_encoder(crtc_state)) {
2056                 intel_cpu_transcoder_set_m1_n1(crtc, cpu_transcoder,
2057                                                &crtc_state->dp_m_n);
2058                 intel_cpu_transcoder_set_m2_n2(crtc, cpu_transcoder,
2059                                                &crtc_state->dp_m2_n2);
2060         }
2061
2062         intel_set_transcoder_timings(crtc_state);
2063
2064         i9xx_set_pipeconf(crtc_state);
2065 }
2066
2067 static void valleyview_crtc_enable(struct intel_atomic_state *state,
2068                                    struct intel_crtc *crtc)
2069 {
2070         const struct intel_crtc_state *new_crtc_state =
2071                 intel_atomic_get_new_crtc_state(state, crtc);
2072         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
2073         enum pipe pipe = crtc->pipe;
2074
2075         if (drm_WARN_ON(&dev_priv->drm, crtc->active))
2076                 return;
2077
2078         i9xx_configure_cpu_transcoder(new_crtc_state);
2079
2080         intel_set_pipe_src_size(new_crtc_state);
2081
2082         intel_de_write(dev_priv, VLV_PIPE_MSA_MISC(pipe), 0);
2083
2084         if (IS_CHERRYVIEW(dev_priv) && pipe == PIPE_B) {
2085                 intel_de_write(dev_priv, CHV_BLEND(pipe), CHV_BLEND_LEGACY);
2086                 intel_de_write(dev_priv, CHV_CANVAS(pipe), 0);
2087         }
2088
2089         crtc->active = true;
2090
2091         intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
2092
2093         intel_encoders_pre_pll_enable(state, crtc);
2094
2095         if (IS_CHERRYVIEW(dev_priv))
2096                 chv_enable_pll(new_crtc_state);
2097         else
2098                 vlv_enable_pll(new_crtc_state);
2099
2100         intel_encoders_pre_enable(state, crtc);
2101
2102         i9xx_pfit_enable(new_crtc_state);
2103
2104         intel_color_load_luts(new_crtc_state);
2105         intel_color_commit_noarm(new_crtc_state);
2106         intel_color_commit_arm(new_crtc_state);
2107         /* update DSPCNTR to configure gamma for pipe bottom color */
2108         intel_disable_primary_plane(new_crtc_state);
2109
2110         intel_initial_watermarks(state, crtc);
2111         intel_enable_transcoder(new_crtc_state);
2112
2113         intel_crtc_vblank_on(new_crtc_state);
2114
2115         intel_encoders_enable(state, crtc);
2116 }
2117
2118 static void i9xx_crtc_enable(struct intel_atomic_state *state,
2119                              struct intel_crtc *crtc)
2120 {
2121         const struct intel_crtc_state *new_crtc_state =
2122                 intel_atomic_get_new_crtc_state(state, crtc);
2123         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
2124         enum pipe pipe = crtc->pipe;
2125
2126         if (drm_WARN_ON(&dev_priv->drm, crtc->active))
2127                 return;
2128
2129         i9xx_configure_cpu_transcoder(new_crtc_state);
2130
2131         intel_set_pipe_src_size(new_crtc_state);
2132
2133         crtc->active = true;
2134
2135         if (DISPLAY_VER(dev_priv) != 2)
2136                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
2137
2138         intel_encoders_pre_enable(state, crtc);
2139
2140         i9xx_enable_pll(new_crtc_state);
2141
2142         i9xx_pfit_enable(new_crtc_state);
2143
2144         intel_color_load_luts(new_crtc_state);
2145         intel_color_commit_noarm(new_crtc_state);
2146         intel_color_commit_arm(new_crtc_state);
2147         /* update DSPCNTR to configure gamma for pipe bottom color */
2148         intel_disable_primary_plane(new_crtc_state);
2149
2150         if (!intel_initial_watermarks(state, crtc))
2151                 intel_update_watermarks(dev_priv);
2152         intel_enable_transcoder(new_crtc_state);
2153
2154         intel_crtc_vblank_on(new_crtc_state);
2155
2156         intel_encoders_enable(state, crtc);
2157
2158         /* prevents spurious underruns */
2159         if (DISPLAY_VER(dev_priv) == 2)
2160                 intel_crtc_wait_for_next_vblank(crtc);
2161 }
2162
2163 static void i9xx_pfit_disable(const struct intel_crtc_state *old_crtc_state)
2164 {
2165         struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc);
2166         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
2167
2168         if (!old_crtc_state->gmch_pfit.control)
2169                 return;
2170
2171         assert_transcoder_disabled(dev_priv, old_crtc_state->cpu_transcoder);
2172
2173         drm_dbg_kms(&dev_priv->drm, "disabling pfit, current: 0x%08x\n",
2174                     intel_de_read(dev_priv, PFIT_CONTROL));
2175         intel_de_write(dev_priv, PFIT_CONTROL, 0);
2176 }
2177
2178 static void i9xx_crtc_disable(struct intel_atomic_state *state,
2179                               struct intel_crtc *crtc)
2180 {
2181         struct intel_crtc_state *old_crtc_state =
2182                 intel_atomic_get_old_crtc_state(state, crtc);
2183         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
2184         enum pipe pipe = crtc->pipe;
2185
2186         /*
2187          * On gen2 planes are double buffered but the pipe isn't, so we must
2188          * wait for planes to fully turn off before disabling the pipe.
2189          */
2190         if (DISPLAY_VER(dev_priv) == 2)
2191                 intel_crtc_wait_for_next_vblank(crtc);
2192
2193         intel_encoders_disable(state, crtc);
2194
2195         intel_crtc_vblank_off(old_crtc_state);
2196
2197         intel_disable_transcoder(old_crtc_state);
2198
2199         i9xx_pfit_disable(old_crtc_state);
2200
2201         intel_encoders_post_disable(state, crtc);
2202
2203         if (!intel_crtc_has_type(old_crtc_state, INTEL_OUTPUT_DSI)) {
2204                 if (IS_CHERRYVIEW(dev_priv))
2205                         chv_disable_pll(dev_priv, pipe);
2206                 else if (IS_VALLEYVIEW(dev_priv))
2207                         vlv_disable_pll(dev_priv, pipe);
2208                 else
2209                         i9xx_disable_pll(old_crtc_state);
2210         }
2211
2212         intel_encoders_post_pll_disable(state, crtc);
2213
2214         if (DISPLAY_VER(dev_priv) != 2)
2215                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
2216
2217         if (!dev_priv->display.funcs.wm->initial_watermarks)
2218                 intel_update_watermarks(dev_priv);
2219
2220         /* clock the pipe down to 640x480@60 to potentially save power */
2221         if (IS_I830(dev_priv))
2222                 i830_enable_pipe(dev_priv, pipe);
2223 }
2224
2225
2226 /*
2227  * turn all crtc's off, but do not adjust state
2228  * This has to be paired with a call to intel_modeset_setup_hw_state.
2229  */
2230 int intel_display_suspend(struct drm_device *dev)
2231 {
2232         struct drm_i915_private *dev_priv = to_i915(dev);
2233         struct drm_atomic_state *state;
2234         int ret;
2235
2236         if (!HAS_DISPLAY(dev_priv))
2237                 return 0;
2238
2239         state = drm_atomic_helper_suspend(dev);
2240         ret = PTR_ERR_OR_ZERO(state);
2241         if (ret)
2242                 drm_err(&dev_priv->drm, "Suspending crtc's failed with %i\n",
2243                         ret);
2244         else
2245                 dev_priv->display.restore.modeset_state = state;
2246         return ret;
2247 }
2248
2249 void intel_encoder_destroy(struct drm_encoder *encoder)
2250 {
2251         struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
2252
2253         drm_encoder_cleanup(encoder);
2254         kfree(intel_encoder);
2255 }
2256
2257 static bool intel_crtc_supports_double_wide(const struct intel_crtc *crtc)
2258 {
2259         const struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
2260
2261         /* GDG double wide on either pipe, otherwise pipe A only */
2262         return DISPLAY_VER(dev_priv) < 4 &&
2263                 (crtc->pipe == PIPE_A || IS_I915G(dev_priv));
2264 }
2265
2266 static u32 ilk_pipe_pixel_rate(const struct intel_crtc_state *crtc_state)
2267 {
2268         u32 pixel_rate = crtc_state->hw.pipe_mode.crtc_clock;
2269         struct drm_rect src;
2270
2271         /*
2272          * We only use IF-ID interlacing. If we ever use
2273          * PF-ID we'll need to adjust the pixel_rate here.
2274          */
2275
2276         if (!crtc_state->pch_pfit.enabled)
2277                 return pixel_rate;
2278
2279         drm_rect_init(&src, 0, 0,
2280                       drm_rect_width(&crtc_state->pipe_src) << 16,
2281                       drm_rect_height(&crtc_state->pipe_src) << 16);
2282
2283         return intel_adjusted_rate(&src, &crtc_state->pch_pfit.dst,
2284                                    pixel_rate);
2285 }
2286
2287 static void intel_mode_from_crtc_timings(struct drm_display_mode *mode,
2288                                          const struct drm_display_mode *timings)
2289 {
2290         mode->hdisplay = timings->crtc_hdisplay;
2291         mode->htotal = timings->crtc_htotal;
2292         mode->hsync_start = timings->crtc_hsync_start;
2293         mode->hsync_end = timings->crtc_hsync_end;
2294
2295         mode->vdisplay = timings->crtc_vdisplay;
2296         mode->vtotal = timings->crtc_vtotal;
2297         mode->vsync_start = timings->crtc_vsync_start;
2298         mode->vsync_end = timings->crtc_vsync_end;
2299
2300         mode->flags = timings->flags;
2301         mode->type = DRM_MODE_TYPE_DRIVER;
2302
2303         mode->clock = timings->crtc_clock;
2304
2305         drm_mode_set_name(mode);
2306 }
2307
2308 static void intel_crtc_compute_pixel_rate(struct intel_crtc_state *crtc_state)
2309 {
2310         struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
2311
2312         if (HAS_GMCH(dev_priv))
2313                 /* FIXME calculate proper pipe pixel rate for GMCH pfit */
2314                 crtc_state->pixel_rate =
2315                         crtc_state->hw.pipe_mode.crtc_clock;
2316         else
2317                 crtc_state->pixel_rate =
2318                         ilk_pipe_pixel_rate(crtc_state);
2319 }
2320
2321 static void intel_bigjoiner_adjust_timings(const struct intel_crtc_state *crtc_state,
2322                                            struct drm_display_mode *mode)
2323 {
2324         int num_pipes = intel_bigjoiner_num_pipes(crtc_state);
2325
2326         if (num_pipes < 2)
2327                 return;
2328
2329         mode->crtc_clock /= num_pipes;
2330         mode->crtc_hdisplay /= num_pipes;
2331         mode->crtc_hblank_start /= num_pipes;
2332         mode->crtc_hblank_end /= num_pipes;
2333         mode->crtc_hsync_start /= num_pipes;
2334         mode->crtc_hsync_end /= num_pipes;
2335         mode->crtc_htotal /= num_pipes;
2336 }
2337
2338 static void intel_splitter_adjust_timings(const struct intel_crtc_state *crtc_state,
2339                                           struct drm_display_mode *mode)
2340 {
2341         int overlap = crtc_state->splitter.pixel_overlap;
2342         int n = crtc_state->splitter.link_count;
2343
2344         if (!crtc_state->splitter.enable)
2345                 return;
2346
2347         /*
2348          * eDP MSO uses segment timings from EDID for transcoder
2349          * timings, but full mode for everything else.
2350          *
2351          * h_full = (h_segment - pixel_overlap) * link_count
2352          */
2353         mode->crtc_hdisplay = (mode->crtc_hdisplay - overlap) * n;
2354         mode->crtc_hblank_start = (mode->crtc_hblank_start - overlap) * n;
2355         mode->crtc_hblank_end = (mode->crtc_hblank_end - overlap) * n;
2356         mode->crtc_hsync_start = (mode->crtc_hsync_start - overlap) * n;
2357         mode->crtc_hsync_end = (mode->crtc_hsync_end - overlap) * n;
2358         mode->crtc_htotal = (mode->crtc_htotal - overlap) * n;
2359         mode->crtc_clock *= n;
2360 }
2361
2362 static void intel_crtc_readout_derived_state(struct intel_crtc_state *crtc_state)
2363 {
2364         struct drm_display_mode *mode = &crtc_state->hw.mode;
2365         struct drm_display_mode *pipe_mode = &crtc_state->hw.pipe_mode;
2366         struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode;
2367
2368         /*
2369          * Start with the adjusted_mode crtc timings, which
2370          * have been filled with the transcoder timings.
2371          */
2372         drm_mode_copy(pipe_mode, adjusted_mode);
2373
2374         /* Expand MSO per-segment transcoder timings to full */
2375         intel_splitter_adjust_timings(crtc_state, pipe_mode);
2376
2377         /*
2378          * We want the full numbers in adjusted_mode normal timings,
2379          * adjusted_mode crtc timings are left with the raw transcoder
2380          * timings.
2381          */
2382         intel_mode_from_crtc_timings(adjusted_mode, pipe_mode);
2383
2384         /* Populate the "user" mode with full numbers */
2385         drm_mode_copy(mode, pipe_mode);
2386         intel_mode_from_crtc_timings(mode, mode);
2387         mode->hdisplay = drm_rect_width(&crtc_state->pipe_src) *
2388                 (intel_bigjoiner_num_pipes(crtc_state) ?: 1);
2389         mode->vdisplay = drm_rect_height(&crtc_state->pipe_src);
2390
2391         /* Derive per-pipe timings in case bigjoiner is used */
2392         intel_bigjoiner_adjust_timings(crtc_state, pipe_mode);
2393         intel_mode_from_crtc_timings(pipe_mode, pipe_mode);
2394
2395         intel_crtc_compute_pixel_rate(crtc_state);
2396 }
2397
2398 void intel_encoder_get_config(struct intel_encoder *encoder,
2399                               struct intel_crtc_state *crtc_state)
2400 {
2401         encoder->get_config(encoder, crtc_state);
2402
2403         intel_crtc_readout_derived_state(crtc_state);
2404 }
2405
2406 static void intel_bigjoiner_compute_pipe_src(struct intel_crtc_state *crtc_state)
2407 {
2408         int num_pipes = intel_bigjoiner_num_pipes(crtc_state);
2409         int width, height;
2410
2411         if (num_pipes < 2)
2412                 return;
2413
2414         width = drm_rect_width(&crtc_state->pipe_src);
2415         height = drm_rect_height(&crtc_state->pipe_src);
2416
2417         drm_rect_init(&crtc_state->pipe_src, 0, 0,
2418                       width / num_pipes, height);
2419 }
2420
2421 static int intel_crtc_compute_pipe_src(struct intel_crtc_state *crtc_state)
2422 {
2423         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
2424         struct drm_i915_private *i915 = to_i915(crtc->base.dev);
2425
2426         intel_bigjoiner_compute_pipe_src(crtc_state);
2427
2428         /*
2429          * Pipe horizontal size must be even in:
2430          * - DVO ganged mode
2431          * - LVDS dual channel mode
2432          * - Double wide pipe
2433          */
2434         if (drm_rect_width(&crtc_state->pipe_src) & 1) {
2435                 if (crtc_state->double_wide) {
2436                         drm_dbg_kms(&i915->drm,
2437                                     "[CRTC:%d:%s] Odd pipe source width not supported with double wide pipe\n",
2438                                     crtc->base.base.id, crtc->base.name);
2439                         return -EINVAL;
2440                 }
2441
2442                 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS) &&
2443                     intel_is_dual_link_lvds(i915)) {
2444                         drm_dbg_kms(&i915->drm,
2445                                     "[CRTC:%d:%s] Odd pipe source width not supported with dual link LVDS\n",
2446                                     crtc->base.base.id, crtc->base.name);
2447                         return -EINVAL;
2448                 }
2449         }
2450
2451         return 0;
2452 }
2453
2454 static int intel_crtc_compute_pipe_mode(struct intel_crtc_state *crtc_state)
2455 {
2456         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
2457         struct drm_i915_private *i915 = to_i915(crtc->base.dev);
2458         struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode;
2459         struct drm_display_mode *pipe_mode = &crtc_state->hw.pipe_mode;
2460         int clock_limit = i915->max_dotclk_freq;
2461
2462         /*
2463          * Start with the adjusted_mode crtc timings, which
2464          * have been filled with the transcoder timings.
2465          */
2466         drm_mode_copy(pipe_mode, adjusted_mode);
2467
2468         /* Expand MSO per-segment transcoder timings to full */
2469         intel_splitter_adjust_timings(crtc_state, pipe_mode);
2470
2471         /* Derive per-pipe timings in case bigjoiner is used */
2472         intel_bigjoiner_adjust_timings(crtc_state, pipe_mode);
2473         intel_mode_from_crtc_timings(pipe_mode, pipe_mode);
2474
2475         if (DISPLAY_VER(i915) < 4) {
2476                 clock_limit = i915->display.cdclk.max_cdclk_freq * 9 / 10;
2477
2478                 /*
2479                  * Enable double wide mode when the dot clock
2480                  * is > 90% of the (display) core speed.
2481                  */
2482                 if (intel_crtc_supports_double_wide(crtc) &&
2483                     pipe_mode->crtc_clock > clock_limit) {
2484                         clock_limit = i915->max_dotclk_freq;
2485                         crtc_state->double_wide = true;
2486                 }
2487         }
2488
2489         if (pipe_mode->crtc_clock > clock_limit) {
2490                 drm_dbg_kms(&i915->drm,
2491                             "[CRTC:%d:%s] requested pixel clock (%d kHz) too high (max: %d kHz, double wide: %s)\n",
2492                             crtc->base.base.id, crtc->base.name,
2493                             pipe_mode->crtc_clock, clock_limit,
2494                             str_yes_no(crtc_state->double_wide));
2495                 return -EINVAL;
2496         }
2497
2498         return 0;
2499 }
2500
2501 static int intel_crtc_compute_config(struct intel_atomic_state *state,
2502                                      struct intel_crtc *crtc)
2503 {
2504         struct intel_crtc_state *crtc_state =
2505                 intel_atomic_get_new_crtc_state(state, crtc);
2506         int ret;
2507
2508         ret = intel_dpll_crtc_compute_clock(state, crtc);
2509         if (ret)
2510                 return ret;
2511
2512         ret = intel_crtc_compute_pipe_src(crtc_state);
2513         if (ret)
2514                 return ret;
2515
2516         ret = intel_crtc_compute_pipe_mode(crtc_state);
2517         if (ret)
2518                 return ret;
2519
2520         intel_crtc_compute_pixel_rate(crtc_state);
2521
2522         if (crtc_state->has_pch_encoder)
2523                 return ilk_fdi_compute_config(crtc, crtc_state);
2524
2525         return 0;
2526 }
2527
2528 static void
2529 intel_reduce_m_n_ratio(u32 *num, u32 *den)
2530 {
2531         while (*num > DATA_LINK_M_N_MASK ||
2532                *den > DATA_LINK_M_N_MASK) {
2533                 *num >>= 1;
2534                 *den >>= 1;
2535         }
2536 }
2537
2538 static void compute_m_n(u32 *ret_m, u32 *ret_n,
2539                         u32 m, u32 n, u32 constant_n)
2540 {
2541         if (constant_n)
2542                 *ret_n = constant_n;
2543         else
2544                 *ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX);
2545
2546         *ret_m = div_u64(mul_u32_u32(m, *ret_n), n);
2547         intel_reduce_m_n_ratio(ret_m, ret_n);
2548 }
2549
2550 void
2551 intel_link_compute_m_n(u16 bits_per_pixel, int nlanes,
2552                        int pixel_clock, int link_clock,
2553                        struct intel_link_m_n *m_n,
2554                        bool fec_enable)
2555 {
2556         u32 data_clock = bits_per_pixel * pixel_clock;
2557
2558         if (fec_enable)
2559                 data_clock = intel_dp_mode_to_fec_clock(data_clock);
2560
2561         /*
2562          * Windows/BIOS uses fixed M/N values always. Follow suit.
2563          *
2564          * Also several DP dongles in particular seem to be fussy
2565          * about too large link M/N values. Presumably the 20bit
2566          * value used by Windows/BIOS is acceptable to everyone.
2567          */
2568         m_n->tu = 64;
2569         compute_m_n(&m_n->data_m, &m_n->data_n,
2570                     data_clock, link_clock * nlanes * 8,
2571                     0x8000000);
2572
2573         compute_m_n(&m_n->link_m, &m_n->link_n,
2574                     pixel_clock, link_clock,
2575                     0x80000);
2576 }
2577
2578 static void intel_panel_sanitize_ssc(struct drm_i915_private *dev_priv)
2579 {
2580         /*
2581          * There may be no VBT; and if the BIOS enabled SSC we can
2582          * just keep using it to avoid unnecessary flicker.  Whereas if the
2583          * BIOS isn't using it, don't assume it will work even if the VBT
2584          * indicates as much.
2585          */
2586         if (HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv)) {
2587                 bool bios_lvds_use_ssc = intel_de_read(dev_priv,
2588                                                        PCH_DREF_CONTROL) &
2589                         DREF_SSC1_ENABLE;
2590
2591                 if (dev_priv->display.vbt.lvds_use_ssc != bios_lvds_use_ssc) {
2592                         drm_dbg_kms(&dev_priv->drm,
2593                                     "SSC %s by BIOS, overriding VBT which says %s\n",
2594                                     str_enabled_disabled(bios_lvds_use_ssc),
2595                                     str_enabled_disabled(dev_priv->display.vbt.lvds_use_ssc));
2596                         dev_priv->display.vbt.lvds_use_ssc = bios_lvds_use_ssc;
2597                 }
2598         }
2599 }
2600
2601 void intel_zero_m_n(struct intel_link_m_n *m_n)
2602 {
2603         /* corresponds to 0 register value */
2604         memset(m_n, 0, sizeof(*m_n));
2605         m_n->tu = 1;
2606 }
2607
2608 void intel_set_m_n(struct drm_i915_private *i915,
2609                    const struct intel_link_m_n *m_n,
2610                    i915_reg_t data_m_reg, i915_reg_t data_n_reg,
2611                    i915_reg_t link_m_reg, i915_reg_t link_n_reg)
2612 {
2613         intel_de_write(i915, data_m_reg, TU_SIZE(m_n->tu) | m_n->data_m);
2614         intel_de_write(i915, data_n_reg, m_n->data_n);
2615         intel_de_write(i915, link_m_reg, m_n->link_m);
2616         /*
2617          * On BDW+ writing LINK_N arms the double buffered update
2618          * of all the M/N registers, so it must be written last.
2619          */
2620         intel_de_write(i915, link_n_reg, m_n->link_n);
2621 }
2622
2623 bool intel_cpu_transcoder_has_m2_n2(struct drm_i915_private *dev_priv,
2624                                     enum transcoder transcoder)
2625 {
2626         if (IS_HASWELL(dev_priv))
2627                 return transcoder == TRANSCODER_EDP;
2628
2629         return IS_DISPLAY_VER(dev_priv, 5, 7) || IS_CHERRYVIEW(dev_priv);
2630 }
2631
2632 void intel_cpu_transcoder_set_m1_n1(struct intel_crtc *crtc,
2633                                     enum transcoder transcoder,
2634                                     const struct intel_link_m_n *m_n)
2635 {
2636         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
2637         enum pipe pipe = crtc->pipe;
2638
2639         if (DISPLAY_VER(dev_priv) >= 5)
2640                 intel_set_m_n(dev_priv, m_n,
2641                               PIPE_DATA_M1(transcoder), PIPE_DATA_N1(transcoder),
2642                               PIPE_LINK_M1(transcoder), PIPE_LINK_N1(transcoder));
2643         else
2644                 intel_set_m_n(dev_priv, m_n,
2645                               PIPE_DATA_M_G4X(pipe), PIPE_DATA_N_G4X(pipe),
2646                               PIPE_LINK_M_G4X(pipe), PIPE_LINK_N_G4X(pipe));
2647 }
2648
2649 void intel_cpu_transcoder_set_m2_n2(struct intel_crtc *crtc,
2650                                     enum transcoder transcoder,
2651                                     const struct intel_link_m_n *m_n)
2652 {
2653         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
2654
2655         if (!intel_cpu_transcoder_has_m2_n2(dev_priv, transcoder))
2656                 return;
2657
2658         intel_set_m_n(dev_priv, m_n,
2659                       PIPE_DATA_M2(transcoder), PIPE_DATA_N2(transcoder),
2660                       PIPE_LINK_M2(transcoder), PIPE_LINK_N2(transcoder));
2661 }
2662
2663 static void intel_set_transcoder_timings(const struct intel_crtc_state *crtc_state)
2664 {
2665         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
2666         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
2667         enum pipe pipe = crtc->pipe;
2668         enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
2669         const struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode;
2670         u32 crtc_vdisplay, crtc_vtotal, crtc_vblank_start, crtc_vblank_end;
2671         int vsyncshift = 0;
2672
2673         /* We need to be careful not to changed the adjusted mode, for otherwise
2674          * the hw state checker will get angry at the mismatch. */
2675         crtc_vdisplay = adjusted_mode->crtc_vdisplay;
2676         crtc_vtotal = adjusted_mode->crtc_vtotal;
2677         crtc_vblank_start = adjusted_mode->crtc_vblank_start;
2678         crtc_vblank_end = adjusted_mode->crtc_vblank_end;
2679
2680         if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
2681                 /* the chip adds 2 halflines automatically */
2682                 crtc_vtotal -= 1;
2683                 crtc_vblank_end -= 1;
2684
2685                 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO))
2686                         vsyncshift = (adjusted_mode->crtc_htotal - 1) / 2;
2687                 else
2688                         vsyncshift = adjusted_mode->crtc_hsync_start -
2689                                 adjusted_mode->crtc_htotal / 2;
2690                 if (vsyncshift < 0)
2691                         vsyncshift += adjusted_mode->crtc_htotal;
2692         }
2693
2694         /*
2695          * VBLANK_START no longer works on ADL+, instead we must use
2696          * TRANS_SET_CONTEXT_LATENCY to configure the pipe vblank start.
2697          */
2698         if (DISPLAY_VER(dev_priv) >= 13) {
2699                 intel_de_write(dev_priv, TRANS_SET_CONTEXT_LATENCY(cpu_transcoder),
2700                                crtc_vblank_start - crtc_vdisplay);
2701
2702                 /*
2703                  * VBLANK_START not used by hw, just clear it
2704                  * to make it stand out in register dumps.
2705                  */
2706                 crtc_vblank_start = 1;
2707         }
2708
2709         if (DISPLAY_VER(dev_priv) > 3)
2710                 intel_de_write(dev_priv, TRANS_VSYNCSHIFT(cpu_transcoder),
2711                                vsyncshift);
2712
2713         intel_de_write(dev_priv, TRANS_HTOTAL(cpu_transcoder),
2714                        HACTIVE(adjusted_mode->crtc_hdisplay - 1) |
2715                        HTOTAL(adjusted_mode->crtc_htotal - 1));
2716         intel_de_write(dev_priv, TRANS_HBLANK(cpu_transcoder),
2717                        HBLANK_START(adjusted_mode->crtc_hblank_start - 1) |
2718                        HBLANK_END(adjusted_mode->crtc_hblank_end - 1));
2719         intel_de_write(dev_priv, TRANS_HSYNC(cpu_transcoder),
2720                        HSYNC_START(adjusted_mode->crtc_hsync_start - 1) |
2721                        HSYNC_END(adjusted_mode->crtc_hsync_end - 1));
2722
2723         intel_de_write(dev_priv, TRANS_VTOTAL(cpu_transcoder),
2724                        VACTIVE(crtc_vdisplay - 1) |
2725                        VTOTAL(crtc_vtotal - 1));
2726         intel_de_write(dev_priv, TRANS_VBLANK(cpu_transcoder),
2727                        VBLANK_START(crtc_vblank_start - 1) |
2728                        VBLANK_END(crtc_vblank_end - 1));
2729         intel_de_write(dev_priv, TRANS_VSYNC(cpu_transcoder),
2730                        VSYNC_START(adjusted_mode->crtc_vsync_start - 1) |
2731                        VSYNC_END(adjusted_mode->crtc_vsync_end - 1));
2732
2733         /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
2734          * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
2735          * documented on the DDI_FUNC_CTL register description, EDP Input Select
2736          * bits. */
2737         if (IS_HASWELL(dev_priv) && cpu_transcoder == TRANSCODER_EDP &&
2738             (pipe == PIPE_B || pipe == PIPE_C))
2739                 intel_de_write(dev_priv, TRANS_VTOTAL(pipe),
2740                                VACTIVE(crtc_vdisplay - 1) |
2741                                VTOTAL(crtc_vtotal - 1));
2742 }
2743
2744 static void intel_set_pipe_src_size(const struct intel_crtc_state *crtc_state)
2745 {
2746         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
2747         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
2748         int width = drm_rect_width(&crtc_state->pipe_src);
2749         int height = drm_rect_height(&crtc_state->pipe_src);
2750         enum pipe pipe = crtc->pipe;
2751
2752         /* pipesrc controls the size that is scaled from, which should
2753          * always be the user's requested size.
2754          */
2755         intel_de_write(dev_priv, PIPESRC(pipe),
2756                        PIPESRC_WIDTH(width - 1) | PIPESRC_HEIGHT(height - 1));
2757 }
2758
2759 static bool intel_pipe_is_interlaced(const struct intel_crtc_state *crtc_state)
2760 {
2761         struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
2762         enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
2763
2764         if (DISPLAY_VER(dev_priv) == 2)
2765                 return false;
2766
2767         if (DISPLAY_VER(dev_priv) >= 9 ||
2768             IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv))
2769                 return intel_de_read(dev_priv, TRANSCONF(cpu_transcoder)) & TRANSCONF_INTERLACE_MASK_HSW;
2770         else
2771                 return intel_de_read(dev_priv, TRANSCONF(cpu_transcoder)) & TRANSCONF_INTERLACE_MASK;
2772 }
2773
2774 static void intel_get_transcoder_timings(struct intel_crtc *crtc,
2775                                          struct intel_crtc_state *pipe_config)
2776 {
2777         struct drm_device *dev = crtc->base.dev;
2778         struct drm_i915_private *dev_priv = to_i915(dev);
2779         enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
2780         struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode;
2781         u32 tmp;
2782
2783         tmp = intel_de_read(dev_priv, TRANS_HTOTAL(cpu_transcoder));
2784         adjusted_mode->crtc_hdisplay = REG_FIELD_GET(HACTIVE_MASK, tmp) + 1;
2785         adjusted_mode->crtc_htotal = REG_FIELD_GET(HTOTAL_MASK, tmp) + 1;
2786
2787         if (!transcoder_is_dsi(cpu_transcoder)) {
2788                 tmp = intel_de_read(dev_priv, TRANS_HBLANK(cpu_transcoder));
2789                 adjusted_mode->crtc_hblank_start = REG_FIELD_GET(HBLANK_START_MASK, tmp) + 1;
2790                 adjusted_mode->crtc_hblank_end = REG_FIELD_GET(HBLANK_END_MASK, tmp) + 1;
2791         }
2792
2793         tmp = intel_de_read(dev_priv, TRANS_HSYNC(cpu_transcoder));
2794         adjusted_mode->crtc_hsync_start = REG_FIELD_GET(HSYNC_START_MASK, tmp) + 1;
2795         adjusted_mode->crtc_hsync_end = REG_FIELD_GET(HSYNC_END_MASK, tmp) + 1;
2796
2797         tmp = intel_de_read(dev_priv, TRANS_VTOTAL(cpu_transcoder));
2798         adjusted_mode->crtc_vdisplay = REG_FIELD_GET(VACTIVE_MASK, tmp) + 1;
2799         adjusted_mode->crtc_vtotal = REG_FIELD_GET(VTOTAL_MASK, tmp) + 1;
2800
2801         /* FIXME TGL+ DSI transcoders have this! */
2802         if (!transcoder_is_dsi(cpu_transcoder)) {
2803                 tmp = intel_de_read(dev_priv, TRANS_VBLANK(cpu_transcoder));
2804                 adjusted_mode->crtc_vblank_start = REG_FIELD_GET(VBLANK_START_MASK, tmp) + 1;
2805                 adjusted_mode->crtc_vblank_end = REG_FIELD_GET(VBLANK_END_MASK, tmp) + 1;
2806         }
2807         tmp = intel_de_read(dev_priv, TRANS_VSYNC(cpu_transcoder));
2808         adjusted_mode->crtc_vsync_start = REG_FIELD_GET(VSYNC_START_MASK, tmp) + 1;
2809         adjusted_mode->crtc_vsync_end = REG_FIELD_GET(VSYNC_END_MASK, tmp) + 1;
2810
2811         if (intel_pipe_is_interlaced(pipe_config)) {
2812                 adjusted_mode->flags |= DRM_MODE_FLAG_INTERLACE;
2813                 adjusted_mode->crtc_vtotal += 1;
2814                 adjusted_mode->crtc_vblank_end += 1;
2815         }
2816
2817         if (DISPLAY_VER(dev_priv) >= 13 && !transcoder_is_dsi(cpu_transcoder))
2818                 adjusted_mode->crtc_vblank_start =
2819                         adjusted_mode->crtc_vdisplay +
2820                         intel_de_read(dev_priv, TRANS_SET_CONTEXT_LATENCY(cpu_transcoder));
2821 }
2822
2823 static void intel_bigjoiner_adjust_pipe_src(struct intel_crtc_state *crtc_state)
2824 {
2825         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
2826         int num_pipes = intel_bigjoiner_num_pipes(crtc_state);
2827         enum pipe master_pipe, pipe = crtc->pipe;
2828         int width;
2829
2830         if (num_pipes < 2)
2831                 return;
2832
2833         master_pipe = bigjoiner_master_pipe(crtc_state);
2834         width = drm_rect_width(&crtc_state->pipe_src);
2835
2836         drm_rect_translate_to(&crtc_state->pipe_src,
2837                               (pipe - master_pipe) * width, 0);
2838 }
2839
2840 static void intel_get_pipe_src_size(struct intel_crtc *crtc,
2841                                     struct intel_crtc_state *pipe_config)
2842 {
2843         struct drm_device *dev = crtc->base.dev;
2844         struct drm_i915_private *dev_priv = to_i915(dev);
2845         u32 tmp;
2846
2847         tmp = intel_de_read(dev_priv, PIPESRC(crtc->pipe));
2848
2849         drm_rect_init(&pipe_config->pipe_src, 0, 0,
2850                       REG_FIELD_GET(PIPESRC_WIDTH_MASK, tmp) + 1,
2851                       REG_FIELD_GET(PIPESRC_HEIGHT_MASK, tmp) + 1);
2852
2853         intel_bigjoiner_adjust_pipe_src(pipe_config);
2854 }
2855
2856 void i9xx_set_pipeconf(const struct intel_crtc_state *crtc_state)
2857 {
2858         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
2859         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
2860         enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
2861         u32 val = 0;
2862
2863         /*
2864          * - We keep both pipes enabled on 830
2865          * - During modeset the pipe is still disabled and must remain so
2866          * - During fastset the pipe is already enabled and must remain so
2867          */
2868         if (IS_I830(dev_priv) || !intel_crtc_needs_modeset(crtc_state))
2869                 val |= TRANSCONF_ENABLE;
2870
2871         if (crtc_state->double_wide)
2872                 val |= TRANSCONF_DOUBLE_WIDE;
2873
2874         /* only g4x and later have fancy bpc/dither controls */
2875         if (IS_G4X(dev_priv) || IS_VALLEYVIEW(dev_priv) ||
2876             IS_CHERRYVIEW(dev_priv)) {
2877                 /* Bspec claims that we can't use dithering for 30bpp pipes. */
2878                 if (crtc_state->dither && crtc_state->pipe_bpp != 30)
2879                         val |= TRANSCONF_DITHER_EN |
2880                                 TRANSCONF_DITHER_TYPE_SP;
2881
2882                 switch (crtc_state->pipe_bpp) {
2883                 default:
2884                         /* Case prevented by intel_choose_pipe_bpp_dither. */
2885                         MISSING_CASE(crtc_state->pipe_bpp);
2886                         fallthrough;
2887                 case 18:
2888                         val |= TRANSCONF_BPC_6;
2889                         break;
2890                 case 24:
2891                         val |= TRANSCONF_BPC_8;
2892                         break;
2893                 case 30:
2894                         val |= TRANSCONF_BPC_10;
2895                         break;
2896                 }
2897         }
2898
2899         if (crtc_state->hw.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) {
2900                 if (DISPLAY_VER(dev_priv) < 4 ||
2901                     intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO))
2902                         val |= TRANSCONF_INTERLACE_W_FIELD_INDICATION;
2903                 else
2904                         val |= TRANSCONF_INTERLACE_W_SYNC_SHIFT;
2905         } else {
2906                 val |= TRANSCONF_INTERLACE_PROGRESSIVE;
2907         }
2908
2909         if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) &&
2910              crtc_state->limited_color_range)
2911                 val |= TRANSCONF_COLOR_RANGE_SELECT;
2912
2913         val |= TRANSCONF_GAMMA_MODE(crtc_state->gamma_mode);
2914
2915         val |= TRANSCONF_FRAME_START_DELAY(crtc_state->framestart_delay - 1);
2916
2917         intel_de_write(dev_priv, TRANSCONF(cpu_transcoder), val);
2918         intel_de_posting_read(dev_priv, TRANSCONF(cpu_transcoder));
2919 }
2920
2921 static bool i9xx_has_pfit(struct drm_i915_private *dev_priv)
2922 {
2923         if (IS_I830(dev_priv))
2924                 return false;
2925
2926         return DISPLAY_VER(dev_priv) >= 4 ||
2927                 IS_PINEVIEW(dev_priv) || IS_MOBILE(dev_priv);
2928 }
2929
2930 static void i9xx_get_pfit_config(struct intel_crtc_state *crtc_state)
2931 {
2932         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
2933         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
2934         u32 tmp;
2935
2936         if (!i9xx_has_pfit(dev_priv))
2937                 return;
2938
2939         tmp = intel_de_read(dev_priv, PFIT_CONTROL);
2940         if (!(tmp & PFIT_ENABLE))
2941                 return;
2942
2943         /* Check whether the pfit is attached to our pipe. */
2944         if (DISPLAY_VER(dev_priv) < 4) {
2945                 if (crtc->pipe != PIPE_B)
2946                         return;
2947         } else {
2948                 if ((tmp & PFIT_PIPE_MASK) != (crtc->pipe << PFIT_PIPE_SHIFT))
2949                         return;
2950         }
2951
2952         crtc_state->gmch_pfit.control = tmp;
2953         crtc_state->gmch_pfit.pgm_ratios =
2954                 intel_de_read(dev_priv, PFIT_PGM_RATIOS);
2955 }
2956
2957 static void vlv_crtc_clock_get(struct intel_crtc *crtc,
2958                                struct intel_crtc_state *pipe_config)
2959 {
2960         struct drm_device *dev = crtc->base.dev;
2961         struct drm_i915_private *dev_priv = to_i915(dev);
2962         enum pipe pipe = crtc->pipe;
2963         struct dpll clock;
2964         u32 mdiv;
2965         int refclk = 100000;
2966
2967         /* In case of DSI, DPLL will not be used */
2968         if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0)
2969                 return;
2970
2971         vlv_dpio_get(dev_priv);
2972         mdiv = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW3(pipe));
2973         vlv_dpio_put(dev_priv);
2974
2975         clock.m1 = (mdiv >> DPIO_M1DIV_SHIFT) & 7;
2976         clock.m2 = mdiv & DPIO_M2DIV_MASK;
2977         clock.n = (mdiv >> DPIO_N_SHIFT) & 0xf;
2978         clock.p1 = (mdiv >> DPIO_P1_SHIFT) & 7;
2979         clock.p2 = (mdiv >> DPIO_P2_SHIFT) & 0x1f;
2980
2981         pipe_config->port_clock = vlv_calc_dpll_params(refclk, &clock);
2982 }
2983
2984 static void chv_crtc_clock_get(struct intel_crtc *crtc,
2985                                struct intel_crtc_state *pipe_config)
2986 {
2987         struct drm_device *dev = crtc->base.dev;
2988         struct drm_i915_private *dev_priv = to_i915(dev);
2989         enum pipe pipe = crtc->pipe;
2990         enum dpio_channel port = vlv_pipe_to_channel(pipe);
2991         struct dpll clock;
2992         u32 cmn_dw13, pll_dw0, pll_dw1, pll_dw2, pll_dw3;
2993         int refclk = 100000;
2994
2995         /* In case of DSI, DPLL will not be used */
2996         if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0)
2997                 return;
2998
2999         vlv_dpio_get(dev_priv);
3000         cmn_dw13 = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW13(port));
3001         pll_dw0 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW0(port));
3002         pll_dw1 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW1(port));
3003         pll_dw2 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW2(port));
3004         pll_dw3 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port));
3005         vlv_dpio_put(dev_priv);
3006
3007         clock.m1 = (pll_dw1 & 0x7) == DPIO_CHV_M1_DIV_BY_2 ? 2 : 0;
3008         clock.m2 = (pll_dw0 & 0xff) << 22;
3009         if (pll_dw3 & DPIO_CHV_FRAC_DIV_EN)
3010                 clock.m2 |= pll_dw2 & 0x3fffff;
3011         clock.n = (pll_dw1 >> DPIO_CHV_N_DIV_SHIFT) & 0xf;
3012         clock.p1 = (cmn_dw13 >> DPIO_CHV_P1_DIV_SHIFT) & 0x7;
3013         clock.p2 = (cmn_dw13 >> DPIO_CHV_P2_DIV_SHIFT) & 0x1f;
3014
3015         pipe_config->port_clock = chv_calc_dpll_params(refclk, &clock);
3016 }
3017
3018 static enum intel_output_format
3019 bdw_get_pipe_misc_output_format(struct intel_crtc *crtc)
3020 {
3021         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
3022         u32 tmp;
3023
3024         tmp = intel_de_read(dev_priv, PIPE_MISC(crtc->pipe));
3025
3026         if (tmp & PIPE_MISC_YUV420_ENABLE) {
3027                 /* We support 4:2:0 in full blend mode only */
3028                 drm_WARN_ON(&dev_priv->drm,
3029                             (tmp & PIPE_MISC_YUV420_MODE_FULL_BLEND) == 0);
3030
3031                 return INTEL_OUTPUT_FORMAT_YCBCR420;
3032         } else if (tmp & PIPE_MISC_OUTPUT_COLORSPACE_YUV) {
3033                 return INTEL_OUTPUT_FORMAT_YCBCR444;
3034         } else {
3035                 return INTEL_OUTPUT_FORMAT_RGB;
3036         }
3037 }
3038
3039 static void i9xx_get_pipe_color_config(struct intel_crtc_state *crtc_state)
3040 {
3041         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
3042         struct intel_plane *plane = to_intel_plane(crtc->base.primary);
3043         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
3044         enum i9xx_plane_id i9xx_plane = plane->i9xx_plane;
3045         u32 tmp;
3046
3047         tmp = intel_de_read(dev_priv, DSPCNTR(i9xx_plane));
3048
3049         if (tmp & DISP_PIPE_GAMMA_ENABLE)
3050                 crtc_state->gamma_enable = true;
3051
3052         if (!HAS_GMCH(dev_priv) &&
3053             tmp & DISP_PIPE_CSC_ENABLE)
3054                 crtc_state->csc_enable = true;
3055 }
3056
3057 static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
3058                                  struct intel_crtc_state *pipe_config)
3059 {
3060         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
3061         enum intel_display_power_domain power_domain;
3062         intel_wakeref_t wakeref;
3063         u32 tmp;
3064         bool ret;
3065
3066         power_domain = POWER_DOMAIN_PIPE(crtc->pipe);
3067         wakeref = intel_display_power_get_if_enabled(dev_priv, power_domain);
3068         if (!wakeref)
3069                 return false;
3070
3071         pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB;
3072         pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
3073         pipe_config->shared_dpll = NULL;
3074
3075         ret = false;
3076
3077         tmp = intel_de_read(dev_priv, TRANSCONF(pipe_config->cpu_transcoder));
3078         if (!(tmp & TRANSCONF_ENABLE))
3079                 goto out;
3080
3081         if (IS_G4X(dev_priv) || IS_VALLEYVIEW(dev_priv) ||
3082             IS_CHERRYVIEW(dev_priv)) {
3083                 switch (tmp & TRANSCONF_BPC_MASK) {
3084                 case TRANSCONF_BPC_6:
3085                         pipe_config->pipe_bpp = 18;
3086                         break;
3087                 case TRANSCONF_BPC_8:
3088                         pipe_config->pipe_bpp = 24;
3089                         break;
3090                 case TRANSCONF_BPC_10:
3091                         pipe_config->pipe_bpp = 30;
3092                         break;
3093                 default:
3094                         MISSING_CASE(tmp);
3095                         break;
3096                 }
3097         }
3098
3099         if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) &&
3100             (tmp & TRANSCONF_COLOR_RANGE_SELECT))
3101                 pipe_config->limited_color_range = true;
3102
3103         pipe_config->gamma_mode = REG_FIELD_GET(TRANSCONF_GAMMA_MODE_MASK_I9XX, tmp);
3104
3105         pipe_config->framestart_delay = REG_FIELD_GET(TRANSCONF_FRAME_START_DELAY_MASK, tmp) + 1;
3106
3107         if (IS_CHERRYVIEW(dev_priv))
3108                 pipe_config->cgm_mode = intel_de_read(dev_priv,
3109                                                       CGM_PIPE_MODE(crtc->pipe));
3110
3111         i9xx_get_pipe_color_config(pipe_config);
3112         intel_color_get_config(pipe_config);
3113
3114         if (DISPLAY_VER(dev_priv) < 4)
3115                 pipe_config->double_wide = tmp & TRANSCONF_DOUBLE_WIDE;
3116
3117         intel_get_transcoder_timings(crtc, pipe_config);
3118         intel_get_pipe_src_size(crtc, pipe_config);
3119
3120         i9xx_get_pfit_config(pipe_config);
3121
3122         if (DISPLAY_VER(dev_priv) >= 4) {
3123                 /* No way to read it out on pipes B and C */
3124                 if (IS_CHERRYVIEW(dev_priv) && crtc->pipe != PIPE_A)
3125                         tmp = dev_priv->display.state.chv_dpll_md[crtc->pipe];
3126                 else
3127                         tmp = intel_de_read(dev_priv, DPLL_MD(crtc->pipe));
3128                 pipe_config->pixel_multiplier =
3129                         ((tmp & DPLL_MD_UDI_MULTIPLIER_MASK)
3130                          >> DPLL_MD_UDI_MULTIPLIER_SHIFT) + 1;
3131                 pipe_config->dpll_hw_state.dpll_md = tmp;
3132         } else if (IS_I945G(dev_priv) || IS_I945GM(dev_priv) ||
3133                    IS_G33(dev_priv) || IS_PINEVIEW(dev_priv)) {
3134                 tmp = intel_de_read(dev_priv, DPLL(crtc->pipe));
3135                 pipe_config->pixel_multiplier =
3136                         ((tmp & SDVO_MULTIPLIER_MASK)
3137                          >> SDVO_MULTIPLIER_SHIFT_HIRES) + 1;
3138         } else {
3139                 /* Note that on i915G/GM the pixel multiplier is in the sdvo
3140                  * port and will be fixed up in the encoder->get_config
3141                  * function. */
3142                 pipe_config->pixel_multiplier = 1;
3143         }
3144         pipe_config->dpll_hw_state.dpll = intel_de_read(dev_priv,
3145                                                         DPLL(crtc->pipe));
3146         if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv)) {
3147                 pipe_config->dpll_hw_state.fp0 = intel_de_read(dev_priv,
3148                                                                FP0(crtc->pipe));
3149                 pipe_config->dpll_hw_state.fp1 = intel_de_read(dev_priv,
3150                                                                FP1(crtc->pipe));
3151         } else {
3152                 /* Mask out read-only status bits. */
3153                 pipe_config->dpll_hw_state.dpll &= ~(DPLL_LOCK_VLV |
3154                                                      DPLL_PORTC_READY_MASK |
3155                                                      DPLL_PORTB_READY_MASK);
3156         }
3157
3158         if (IS_CHERRYVIEW(dev_priv))
3159                 chv_crtc_clock_get(crtc, pipe_config);
3160         else if (IS_VALLEYVIEW(dev_priv))
3161                 vlv_crtc_clock_get(crtc, pipe_config);
3162         else
3163                 i9xx_crtc_clock_get(crtc, pipe_config);
3164
3165         /*
3166          * Normally the dotclock is filled in by the encoder .get_config()
3167          * but in case the pipe is enabled w/o any ports we need a sane
3168          * default.
3169          */
3170         pipe_config->hw.adjusted_mode.crtc_clock =
3171                 pipe_config->port_clock / pipe_config->pixel_multiplier;
3172
3173         ret = true;
3174
3175 out:
3176         intel_display_power_put(dev_priv, power_domain, wakeref);
3177
3178         return ret;
3179 }
3180
3181 void ilk_set_pipeconf(const struct intel_crtc_state *crtc_state)
3182 {
3183         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
3184         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
3185         enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
3186         u32 val = 0;
3187
3188         /*
3189          * - During modeset the pipe is still disabled and must remain so
3190          * - During fastset the pipe is already enabled and must remain so
3191          */
3192         if (!intel_crtc_needs_modeset(crtc_state))
3193                 val |= TRANSCONF_ENABLE;
3194
3195         switch (crtc_state->pipe_bpp) {
3196         default:
3197                 /* Case prevented by intel_choose_pipe_bpp_dither. */
3198                 MISSING_CASE(crtc_state->pipe_bpp);
3199                 fallthrough;
3200         case 18:
3201                 val |= TRANSCONF_BPC_6;
3202                 break;
3203         case 24:
3204                 val |= TRANSCONF_BPC_8;
3205                 break;
3206         case 30:
3207                 val |= TRANSCONF_BPC_10;
3208                 break;
3209         case 36:
3210                 val |= TRANSCONF_BPC_12;
3211                 break;
3212         }
3213
3214         if (crtc_state->dither)
3215                 val |= TRANSCONF_DITHER_EN | TRANSCONF_DITHER_TYPE_SP;
3216
3217         if (crtc_state->hw.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
3218                 val |= TRANSCONF_INTERLACE_IF_ID_ILK;
3219         else
3220                 val |= TRANSCONF_INTERLACE_PF_PD_ILK;
3221
3222         /*
3223          * This would end up with an odd purple hue over
3224          * the entire display. Make sure we don't do it.
3225          */
3226         drm_WARN_ON(&dev_priv->drm, crtc_state->limited_color_range &&
3227                     crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB);
3228
3229         if (crtc_state->limited_color_range &&
3230             !intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO))
3231                 val |= TRANSCONF_COLOR_RANGE_SELECT;
3232
3233         if (crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB)
3234                 val |= TRANSCONF_OUTPUT_COLORSPACE_YUV709;
3235
3236         val |= TRANSCONF_GAMMA_MODE(crtc_state->gamma_mode);
3237
3238         val |= TRANSCONF_FRAME_START_DELAY(crtc_state->framestart_delay - 1);
3239         val |= TRANSCONF_MSA_TIMING_DELAY(crtc_state->msa_timing_delay);
3240
3241         intel_de_write(dev_priv, TRANSCONF(cpu_transcoder), val);
3242         intel_de_posting_read(dev_priv, TRANSCONF(cpu_transcoder));
3243 }
3244
3245 static void hsw_set_transconf(const struct intel_crtc_state *crtc_state)
3246 {
3247         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
3248         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
3249         enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
3250         u32 val = 0;
3251
3252         /*
3253          * - During modeset the pipe is still disabled and must remain so
3254          * - During fastset the pipe is already enabled and must remain so
3255          */
3256         if (!intel_crtc_needs_modeset(crtc_state))
3257                 val |= TRANSCONF_ENABLE;
3258
3259         if (IS_HASWELL(dev_priv) && crtc_state->dither)
3260                 val |= TRANSCONF_DITHER_EN | TRANSCONF_DITHER_TYPE_SP;
3261
3262         if (crtc_state->hw.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
3263                 val |= TRANSCONF_INTERLACE_IF_ID_ILK;
3264         else
3265                 val |= TRANSCONF_INTERLACE_PF_PD_ILK;
3266
3267         if (IS_HASWELL(dev_priv) &&
3268             crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB)
3269                 val |= TRANSCONF_OUTPUT_COLORSPACE_YUV_HSW;
3270
3271         intel_de_write(dev_priv, TRANSCONF(cpu_transcoder), val);
3272         intel_de_posting_read(dev_priv, TRANSCONF(cpu_transcoder));
3273 }
3274
3275 static void bdw_set_pipe_misc(const struct intel_crtc_state *crtc_state)
3276 {
3277         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
3278         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
3279         u32 val = 0;
3280
3281         switch (crtc_state->pipe_bpp) {
3282         case 18:
3283                 val |= PIPE_MISC_BPC_6;
3284                 break;
3285         case 24:
3286                 val |= PIPE_MISC_BPC_8;
3287                 break;
3288         case 30:
3289                 val |= PIPE_MISC_BPC_10;
3290                 break;
3291         case 36:
3292                 /* Port output 12BPC defined for ADLP+ */
3293                 if (DISPLAY_VER(dev_priv) > 12)
3294                         val |= PIPE_MISC_BPC_12_ADLP;
3295                 break;
3296         default:
3297                 MISSING_CASE(crtc_state->pipe_bpp);
3298                 break;
3299         }
3300
3301         if (crtc_state->dither)
3302                 val |= PIPE_MISC_DITHER_ENABLE | PIPE_MISC_DITHER_TYPE_SP;
3303
3304         if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420 ||
3305             crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR444)
3306                 val |= PIPE_MISC_OUTPUT_COLORSPACE_YUV;
3307
3308         if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420)
3309                 val |= PIPE_MISC_YUV420_ENABLE |
3310                         PIPE_MISC_YUV420_MODE_FULL_BLEND;
3311
3312         if (DISPLAY_VER(dev_priv) >= 11 && is_hdr_mode(crtc_state))
3313                 val |= PIPE_MISC_HDR_MODE_PRECISION;
3314
3315         if (DISPLAY_VER(dev_priv) >= 12)
3316                 val |= PIPE_MISC_PIXEL_ROUNDING_TRUNC;
3317
3318         intel_de_write(dev_priv, PIPE_MISC(crtc->pipe), val);
3319 }
3320
3321 int bdw_get_pipe_misc_bpp(struct intel_crtc *crtc)
3322 {
3323         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
3324         u32 tmp;
3325
3326         tmp = intel_de_read(dev_priv, PIPE_MISC(crtc->pipe));
3327
3328         switch (tmp & PIPE_MISC_BPC_MASK) {
3329         case PIPE_MISC_BPC_6:
3330                 return 18;
3331         case PIPE_MISC_BPC_8:
3332                 return 24;
3333         case PIPE_MISC_BPC_10:
3334                 return 30;
3335         /*
3336          * PORT OUTPUT 12 BPC defined for ADLP+.
3337          *
3338          * TODO:
3339          * For previous platforms with DSI interface, bits 5:7
3340          * are used for storing pipe_bpp irrespective of dithering.
3341          * Since the value of 12 BPC is not defined for these bits
3342          * on older platforms, need to find a workaround for 12 BPC
3343          * MIPI DSI HW readout.
3344          */
3345         case PIPE_MISC_BPC_12_ADLP:
3346                 if (DISPLAY_VER(dev_priv) > 12)
3347                         return 36;
3348                 fallthrough;
3349         default:
3350                 MISSING_CASE(tmp);
3351                 return 0;
3352         }
3353 }
3354
3355 int ilk_get_lanes_required(int target_clock, int link_bw, int bpp)
3356 {
3357         /*
3358          * Account for spread spectrum to avoid
3359          * oversubscribing the link. Max center spread
3360          * is 2.5%; use 5% for safety's sake.
3361          */
3362         u32 bps = target_clock * bpp * 21 / 20;
3363         return DIV_ROUND_UP(bps, link_bw * 8);
3364 }
3365
3366 void intel_get_m_n(struct drm_i915_private *i915,
3367                    struct intel_link_m_n *m_n,
3368                    i915_reg_t data_m_reg, i915_reg_t data_n_reg,
3369                    i915_reg_t link_m_reg, i915_reg_t link_n_reg)
3370 {
3371         m_n->link_m = intel_de_read(i915, link_m_reg) & DATA_LINK_M_N_MASK;
3372         m_n->link_n = intel_de_read(i915, link_n_reg) & DATA_LINK_M_N_MASK;
3373         m_n->data_m = intel_de_read(i915, data_m_reg) & DATA_LINK_M_N_MASK;
3374         m_n->data_n = intel_de_read(i915, data_n_reg) & DATA_LINK_M_N_MASK;
3375         m_n->tu = REG_FIELD_GET(TU_SIZE_MASK, intel_de_read(i915, data_m_reg)) + 1;
3376 }
3377
3378 void intel_cpu_transcoder_get_m1_n1(struct intel_crtc *crtc,
3379                                     enum transcoder transcoder,
3380                                     struct intel_link_m_n *m_n)
3381 {
3382         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
3383         enum pipe pipe = crtc->pipe;
3384
3385         if (DISPLAY_VER(dev_priv) >= 5)
3386                 intel_get_m_n(dev_priv, m_n,
3387                               PIPE_DATA_M1(transcoder), PIPE_DATA_N1(transcoder),
3388                               PIPE_LINK_M1(transcoder), PIPE_LINK_N1(transcoder));
3389         else
3390                 intel_get_m_n(dev_priv, m_n,
3391                               PIPE_DATA_M_G4X(pipe), PIPE_DATA_N_G4X(pipe),
3392                               PIPE_LINK_M_G4X(pipe), PIPE_LINK_N_G4X(pipe));
3393 }
3394
3395 void intel_cpu_transcoder_get_m2_n2(struct intel_crtc *crtc,
3396                                     enum transcoder transcoder,
3397                                     struct intel_link_m_n *m_n)
3398 {
3399         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
3400
3401         if (!intel_cpu_transcoder_has_m2_n2(dev_priv, transcoder))
3402                 return;
3403
3404         intel_get_m_n(dev_priv, m_n,
3405                       PIPE_DATA_M2(transcoder), PIPE_DATA_N2(transcoder),
3406                       PIPE_LINK_M2(transcoder), PIPE_LINK_N2(transcoder));
3407 }
3408
3409 static void ilk_get_pfit_pos_size(struct intel_crtc_state *crtc_state,
3410                                   u32 pos, u32 size)
3411 {
3412         drm_rect_init(&crtc_state->pch_pfit.dst,
3413                       pos >> 16, pos & 0xffff,
3414                       size >> 16, size & 0xffff);
3415 }
3416
3417 static void skl_get_pfit_config(struct intel_crtc_state *crtc_state)
3418 {
3419         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
3420         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
3421         struct intel_crtc_scaler_state *scaler_state = &crtc_state->scaler_state;
3422         int id = -1;
3423         int i;
3424
3425         /* find scaler attached to this pipe */
3426         for (i = 0; i < crtc->num_scalers; i++) {
3427                 u32 ctl, pos, size;
3428
3429                 ctl = intel_de_read(dev_priv, SKL_PS_CTRL(crtc->pipe, i));
3430                 if ((ctl & (PS_SCALER_EN | PS_PLANE_SEL_MASK)) != PS_SCALER_EN)
3431                         continue;
3432
3433                 id = i;
3434                 crtc_state->pch_pfit.enabled = true;
3435
3436                 pos = intel_de_read(dev_priv, SKL_PS_WIN_POS(crtc->pipe, i));
3437                 size = intel_de_read(dev_priv, SKL_PS_WIN_SZ(crtc->pipe, i));
3438
3439                 ilk_get_pfit_pos_size(crtc_state, pos, size);
3440
3441                 scaler_state->scalers[i].in_use = true;
3442                 break;
3443         }
3444
3445         scaler_state->scaler_id = id;
3446         if (id >= 0)
3447                 scaler_state->scaler_users |= (1 << SKL_CRTC_INDEX);
3448         else
3449                 scaler_state->scaler_users &= ~(1 << SKL_CRTC_INDEX);
3450 }
3451
3452 static void ilk_get_pfit_config(struct intel_crtc_state *crtc_state)
3453 {
3454         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
3455         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
3456         u32 ctl, pos, size;
3457
3458         ctl = intel_de_read(dev_priv, PF_CTL(crtc->pipe));
3459         if ((ctl & PF_ENABLE) == 0)
3460                 return;
3461
3462         crtc_state->pch_pfit.enabled = true;
3463
3464         pos = intel_de_read(dev_priv, PF_WIN_POS(crtc->pipe));
3465         size = intel_de_read(dev_priv, PF_WIN_SZ(crtc->pipe));
3466
3467         ilk_get_pfit_pos_size(crtc_state, pos, size);
3468
3469         /*
3470          * We currently do not free assignements of panel fitters on
3471          * ivb/hsw (since we don't use the higher upscaling modes which
3472          * differentiates them) so just WARN about this case for now.
3473          */
3474         drm_WARN_ON(&dev_priv->drm, DISPLAY_VER(dev_priv) == 7 &&
3475                     (ctl & PF_PIPE_SEL_MASK_IVB) != PF_PIPE_SEL_IVB(crtc->pipe));
3476 }
3477
3478 static bool ilk_get_pipe_config(struct intel_crtc *crtc,
3479                                 struct intel_crtc_state *pipe_config)
3480 {
3481         struct drm_device *dev = crtc->base.dev;
3482         struct drm_i915_private *dev_priv = to_i915(dev);
3483         enum intel_display_power_domain power_domain;
3484         intel_wakeref_t wakeref;
3485         u32 tmp;
3486         bool ret;
3487
3488         power_domain = POWER_DOMAIN_PIPE(crtc->pipe);
3489         wakeref = intel_display_power_get_if_enabled(dev_priv, power_domain);
3490         if (!wakeref)
3491                 return false;
3492
3493         pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
3494         pipe_config->shared_dpll = NULL;
3495
3496         ret = false;
3497         tmp = intel_de_read(dev_priv, TRANSCONF(pipe_config->cpu_transcoder));
3498         if (!(tmp & TRANSCONF_ENABLE))
3499                 goto out;
3500
3501         switch (tmp & TRANSCONF_BPC_MASK) {
3502         case TRANSCONF_BPC_6:
3503                 pipe_config->pipe_bpp = 18;
3504                 break;
3505         case TRANSCONF_BPC_8:
3506                 pipe_config->pipe_bpp = 24;
3507                 break;
3508         case TRANSCONF_BPC_10:
3509                 pipe_config->pipe_bpp = 30;
3510                 break;
3511         case TRANSCONF_BPC_12:
3512                 pipe_config->pipe_bpp = 36;
3513                 break;
3514         default:
3515                 break;
3516         }
3517
3518         if (tmp & TRANSCONF_COLOR_RANGE_SELECT)
3519                 pipe_config->limited_color_range = true;
3520
3521         switch (tmp & TRANSCONF_OUTPUT_COLORSPACE_MASK) {
3522         case TRANSCONF_OUTPUT_COLORSPACE_YUV601:
3523         case TRANSCONF_OUTPUT_COLORSPACE_YUV709:
3524                 pipe_config->output_format = INTEL_OUTPUT_FORMAT_YCBCR444;
3525                 break;
3526         default:
3527                 pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB;
3528                 break;
3529         }
3530
3531         pipe_config->gamma_mode = REG_FIELD_GET(TRANSCONF_GAMMA_MODE_MASK_ILK, tmp);
3532
3533         pipe_config->framestart_delay = REG_FIELD_GET(TRANSCONF_FRAME_START_DELAY_MASK, tmp) + 1;
3534
3535         pipe_config->msa_timing_delay = REG_FIELD_GET(TRANSCONF_MSA_TIMING_DELAY_MASK, tmp);
3536
3537         pipe_config->csc_mode = intel_de_read(dev_priv,
3538                                               PIPE_CSC_MODE(crtc->pipe));
3539
3540         i9xx_get_pipe_color_config(pipe_config);
3541         intel_color_get_config(pipe_config);
3542
3543         pipe_config->pixel_multiplier = 1;
3544
3545         ilk_pch_get_config(pipe_config);
3546
3547         intel_get_transcoder_timings(crtc, pipe_config);
3548         intel_get_pipe_src_size(crtc, pipe_config);
3549
3550         ilk_get_pfit_config(pipe_config);
3551
3552         ret = true;
3553
3554 out:
3555         intel_display_power_put(dev_priv, power_domain, wakeref);
3556
3557         return ret;
3558 }
3559
3560 static u8 bigjoiner_pipes(struct drm_i915_private *i915)
3561 {
3562         u8 pipes;
3563
3564         if (DISPLAY_VER(i915) >= 12)
3565                 pipes = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C) | BIT(PIPE_D);
3566         else if (DISPLAY_VER(i915) >= 11)
3567                 pipes = BIT(PIPE_B) | BIT(PIPE_C);
3568         else
3569                 pipes = 0;
3570
3571         return pipes & RUNTIME_INFO(i915)->pipe_mask;
3572 }
3573
3574 static bool transcoder_ddi_func_is_enabled(struct drm_i915_private *dev_priv,
3575                                            enum transcoder cpu_transcoder)
3576 {
3577         enum intel_display_power_domain power_domain;
3578         intel_wakeref_t wakeref;
3579         u32 tmp = 0;
3580
3581         power_domain = POWER_DOMAIN_TRANSCODER(cpu_transcoder);
3582
3583         with_intel_display_power_if_enabled(dev_priv, power_domain, wakeref)
3584                 tmp = intel_de_read(dev_priv, TRANS_DDI_FUNC_CTL(cpu_transcoder));
3585
3586         return tmp & TRANS_DDI_FUNC_ENABLE;
3587 }
3588
3589 static void enabled_bigjoiner_pipes(struct drm_i915_private *dev_priv,
3590                                     u8 *master_pipes, u8 *slave_pipes)
3591 {
3592         struct intel_crtc *crtc;
3593
3594         *master_pipes = 0;
3595         *slave_pipes = 0;
3596
3597         for_each_intel_crtc_in_pipe_mask(&dev_priv->drm, crtc,
3598                                          bigjoiner_pipes(dev_priv)) {
3599                 enum intel_display_power_domain power_domain;
3600                 enum pipe pipe = crtc->pipe;
3601                 intel_wakeref_t wakeref;
3602
3603                 power_domain = intel_dsc_power_domain(crtc, (enum transcoder) pipe);
3604                 with_intel_display_power_if_enabled(dev_priv, power_domain, wakeref) {
3605                         u32 tmp = intel_de_read(dev_priv, ICL_PIPE_DSS_CTL1(pipe));
3606
3607                         if (!(tmp & BIG_JOINER_ENABLE))
3608                                 continue;
3609
3610                         if (tmp & MASTER_BIG_JOINER_ENABLE)
3611                                 *master_pipes |= BIT(pipe);
3612                         else
3613                                 *slave_pipes |= BIT(pipe);
3614                 }
3615
3616                 if (DISPLAY_VER(dev_priv) < 13)
3617                         continue;
3618
3619                 power_domain = POWER_DOMAIN_PIPE(pipe);
3620                 with_intel_display_power_if_enabled(dev_priv, power_domain, wakeref) {
3621                         u32 tmp = intel_de_read(dev_priv, ICL_PIPE_DSS_CTL1(pipe));
3622
3623                         if (tmp & UNCOMPRESSED_JOINER_MASTER)
3624                                 *master_pipes |= BIT(pipe);
3625                         if (tmp & UNCOMPRESSED_JOINER_SLAVE)
3626                                 *slave_pipes |= BIT(pipe);
3627                 }
3628         }
3629
3630         /* Bigjoiner pipes should always be consecutive master and slave */
3631         drm_WARN(&dev_priv->drm, *slave_pipes != *master_pipes << 1,
3632                  "Bigjoiner misconfigured (master pipes 0x%x, slave pipes 0x%x)\n",
3633                  *master_pipes, *slave_pipes);
3634 }
3635
3636 static enum pipe get_bigjoiner_master_pipe(enum pipe pipe, u8 master_pipes, u8 slave_pipes)
3637 {
3638         if ((slave_pipes & BIT(pipe)) == 0)
3639                 return pipe;
3640
3641         /* ignore everything above our pipe */
3642         master_pipes &= ~GENMASK(7, pipe);
3643
3644         /* highest remaining bit should be our master pipe */
3645         return fls(master_pipes) - 1;
3646 }
3647
3648 static u8 get_bigjoiner_slave_pipes(enum pipe pipe, u8 master_pipes, u8 slave_pipes)
3649 {
3650         enum pipe master_pipe, next_master_pipe;
3651
3652         master_pipe = get_bigjoiner_master_pipe(pipe, master_pipes, slave_pipes);
3653
3654         if ((master_pipes & BIT(master_pipe)) == 0)
3655                 return 0;
3656
3657         /* ignore our master pipe and everything below it */
3658         master_pipes &= ~GENMASK(master_pipe, 0);
3659         /* make sure a high bit is set for the ffs() */
3660         master_pipes |= BIT(7);
3661         /* lowest remaining bit should be the next master pipe */
3662         next_master_pipe = ffs(master_pipes) - 1;
3663
3664         return slave_pipes & GENMASK(next_master_pipe - 1, master_pipe);
3665 }
3666
3667 static u8 hsw_panel_transcoders(struct drm_i915_private *i915)
3668 {
3669         u8 panel_transcoder_mask = BIT(TRANSCODER_EDP);
3670
3671         if (DISPLAY_VER(i915) >= 11)
3672                 panel_transcoder_mask |= BIT(TRANSCODER_DSI_0) | BIT(TRANSCODER_DSI_1);
3673
3674         return panel_transcoder_mask;
3675 }
3676
3677 static u8 hsw_enabled_transcoders(struct intel_crtc *crtc)
3678 {
3679         struct drm_device *dev = crtc->base.dev;
3680         struct drm_i915_private *dev_priv = to_i915(dev);
3681         u8 panel_transcoder_mask = hsw_panel_transcoders(dev_priv);
3682         enum transcoder cpu_transcoder;
3683         u8 master_pipes, slave_pipes;
3684         u8 enabled_transcoders = 0;
3685
3686         /*
3687          * XXX: Do intel_display_power_get_if_enabled before reading this (for
3688          * consistency and less surprising code; it's in always on power).
3689          */
3690         for_each_cpu_transcoder_masked(dev_priv, cpu_transcoder,
3691                                        panel_transcoder_mask) {
3692                 enum intel_display_power_domain power_domain;
3693                 intel_wakeref_t wakeref;
3694                 enum pipe trans_pipe;
3695                 u32 tmp = 0;
3696
3697                 power_domain = POWER_DOMAIN_TRANSCODER(cpu_transcoder);
3698                 with_intel_display_power_if_enabled(dev_priv, power_domain, wakeref)
3699                         tmp = intel_de_read(dev_priv, TRANS_DDI_FUNC_CTL(cpu_transcoder));
3700
3701                 if (!(tmp & TRANS_DDI_FUNC_ENABLE))
3702                         continue;
3703
3704                 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
3705                 default:
3706                         drm_WARN(dev, 1,
3707                                  "unknown pipe linked to transcoder %s\n",
3708                                  transcoder_name(cpu_transcoder));
3709                         fallthrough;
3710                 case TRANS_DDI_EDP_INPUT_A_ONOFF:
3711                 case TRANS_DDI_EDP_INPUT_A_ON:
3712                         trans_pipe = PIPE_A;
3713                         break;
3714                 case TRANS_DDI_EDP_INPUT_B_ONOFF:
3715                         trans_pipe = PIPE_B;
3716                         break;
3717                 case TRANS_DDI_EDP_INPUT_C_ONOFF:
3718                         trans_pipe = PIPE_C;
3719                         break;
3720                 case TRANS_DDI_EDP_INPUT_D_ONOFF:
3721                         trans_pipe = PIPE_D;
3722                         break;
3723                 }
3724
3725                 if (trans_pipe == crtc->pipe)
3726                         enabled_transcoders |= BIT(cpu_transcoder);
3727         }
3728
3729         /* single pipe or bigjoiner master */
3730         cpu_transcoder = (enum transcoder) crtc->pipe;
3731         if (transcoder_ddi_func_is_enabled(dev_priv, cpu_transcoder))
3732                 enabled_transcoders |= BIT(cpu_transcoder);
3733
3734         /* bigjoiner slave -> consider the master pipe's transcoder as well */
3735         enabled_bigjoiner_pipes(dev_priv, &master_pipes, &slave_pipes);
3736         if (slave_pipes & BIT(crtc->pipe)) {
3737                 cpu_transcoder = (enum transcoder)
3738                         get_bigjoiner_master_pipe(crtc->pipe, master_pipes, slave_pipes);
3739                 if (transcoder_ddi_func_is_enabled(dev_priv, cpu_transcoder))
3740                         enabled_transcoders |= BIT(cpu_transcoder);
3741         }
3742
3743         return enabled_transcoders;
3744 }
3745
3746 static bool has_edp_transcoders(u8 enabled_transcoders)
3747 {
3748         return enabled_transcoders & BIT(TRANSCODER_EDP);
3749 }
3750
3751 static bool has_dsi_transcoders(u8 enabled_transcoders)
3752 {
3753         return enabled_transcoders & (BIT(TRANSCODER_DSI_0) |
3754                                       BIT(TRANSCODER_DSI_1));
3755 }
3756
3757 static bool has_pipe_transcoders(u8 enabled_transcoders)
3758 {
3759         return enabled_transcoders & ~(BIT(TRANSCODER_EDP) |
3760                                        BIT(TRANSCODER_DSI_0) |
3761                                        BIT(TRANSCODER_DSI_1));
3762 }
3763
3764 static void assert_enabled_transcoders(struct drm_i915_private *i915,
3765                                        u8 enabled_transcoders)
3766 {
3767         /* Only one type of transcoder please */
3768         drm_WARN_ON(&i915->drm,
3769                     has_edp_transcoders(enabled_transcoders) +
3770                     has_dsi_transcoders(enabled_transcoders) +
3771                     has_pipe_transcoders(enabled_transcoders) > 1);
3772
3773         /* Only DSI transcoders can be ganged */
3774         drm_WARN_ON(&i915->drm,
3775                     !has_dsi_transcoders(enabled_transcoders) &&
3776                     !is_power_of_2(enabled_transcoders));
3777 }
3778
3779 static bool hsw_get_transcoder_state(struct intel_crtc *crtc,
3780                                      struct intel_crtc_state *pipe_config,
3781                                      struct intel_display_power_domain_set *power_domain_set)
3782 {
3783         struct drm_device *dev = crtc->base.dev;
3784         struct drm_i915_private *dev_priv = to_i915(dev);
3785         unsigned long enabled_transcoders;
3786         u32 tmp;
3787
3788         enabled_transcoders = hsw_enabled_transcoders(crtc);
3789         if (!enabled_transcoders)
3790                 return false;
3791
3792         assert_enabled_transcoders(dev_priv, enabled_transcoders);
3793
3794         /*
3795          * With the exception of DSI we should only ever have
3796          * a single enabled transcoder. With DSI let's just
3797          * pick the first one.
3798          */
3799         pipe_config->cpu_transcoder = ffs(enabled_transcoders) - 1;
3800
3801         if (!intel_display_power_get_in_set_if_enabled(dev_priv, power_domain_set,
3802                                                        POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder)))
3803                 return false;
3804
3805         if (hsw_panel_transcoders(dev_priv) & BIT(pipe_config->cpu_transcoder)) {
3806                 tmp = intel_de_read(dev_priv, TRANS_DDI_FUNC_CTL(pipe_config->cpu_transcoder));
3807
3808                 if ((tmp & TRANS_DDI_EDP_INPUT_MASK) == TRANS_DDI_EDP_INPUT_A_ONOFF)
3809                         pipe_config->pch_pfit.force_thru = true;
3810         }
3811
3812         tmp = intel_de_read(dev_priv, TRANSCONF(pipe_config->cpu_transcoder));
3813
3814         return tmp & TRANSCONF_ENABLE;
3815 }
3816
3817 static bool bxt_get_dsi_transcoder_state(struct intel_crtc *crtc,
3818                                          struct intel_crtc_state *pipe_config,
3819                                          struct intel_display_power_domain_set *power_domain_set)
3820 {
3821         struct drm_device *dev = crtc->base.dev;
3822         struct drm_i915_private *dev_priv = to_i915(dev);
3823         enum transcoder cpu_transcoder;
3824         enum port port;
3825         u32 tmp;
3826
3827         for_each_port_masked(port, BIT(PORT_A) | BIT(PORT_C)) {
3828                 if (port == PORT_A)
3829                         cpu_transcoder = TRANSCODER_DSI_A;
3830                 else
3831                         cpu_transcoder = TRANSCODER_DSI_C;
3832
3833                 if (!intel_display_power_get_in_set_if_enabled(dev_priv, power_domain_set,
3834                                                                POWER_DOMAIN_TRANSCODER(cpu_transcoder)))
3835                         continue;
3836
3837                 /*
3838                  * The PLL needs to be enabled with a valid divider
3839                  * configuration, otherwise accessing DSI registers will hang
3840                  * the machine. See BSpec North Display Engine
3841                  * registers/MIPI[BXT]. We can break out here early, since we
3842                  * need the same DSI PLL to be enabled for both DSI ports.
3843                  */
3844                 if (!bxt_dsi_pll_is_enabled(dev_priv))
3845                         break;
3846
3847                 /* XXX: this works for video mode only */
3848                 tmp = intel_de_read(dev_priv, BXT_MIPI_PORT_CTRL(port));
3849                 if (!(tmp & DPI_ENABLE))
3850                         continue;
3851
3852                 tmp = intel_de_read(dev_priv, MIPI_CTRL(port));
3853                 if ((tmp & BXT_PIPE_SELECT_MASK) != BXT_PIPE_SELECT(crtc->pipe))
3854                         continue;
3855
3856                 pipe_config->cpu_transcoder = cpu_transcoder;
3857                 break;
3858         }
3859
3860         return transcoder_is_dsi(pipe_config->cpu_transcoder);
3861 }
3862
3863 static void intel_bigjoiner_get_config(struct intel_crtc_state *crtc_state)
3864 {
3865         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
3866         struct drm_i915_private *i915 = to_i915(crtc->base.dev);
3867         u8 master_pipes, slave_pipes;
3868         enum pipe pipe = crtc->pipe;
3869
3870         enabled_bigjoiner_pipes(i915, &master_pipes, &slave_pipes);
3871
3872         if (((master_pipes | slave_pipes) & BIT(pipe)) == 0)
3873                 return;
3874
3875         crtc_state->bigjoiner_pipes =
3876                 BIT(get_bigjoiner_master_pipe(pipe, master_pipes, slave_pipes)) |
3877                 get_bigjoiner_slave_pipes(pipe, master_pipes, slave_pipes);
3878 }
3879
3880 static bool hsw_get_pipe_config(struct intel_crtc *crtc,
3881                                 struct intel_crtc_state *pipe_config)
3882 {
3883         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
3884         bool active;
3885         u32 tmp;
3886
3887         if (!intel_display_power_get_in_set_if_enabled(dev_priv, &crtc->hw_readout_power_domains,
3888                                                        POWER_DOMAIN_PIPE(crtc->pipe)))
3889                 return false;
3890
3891         pipe_config->shared_dpll = NULL;
3892
3893         active = hsw_get_transcoder_state(crtc, pipe_config, &crtc->hw_readout_power_domains);
3894
3895         if ((IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) &&
3896             bxt_get_dsi_transcoder_state(crtc, pipe_config, &crtc->hw_readout_power_domains)) {
3897                 drm_WARN_ON(&dev_priv->drm, active);
3898                 active = true;
3899         }
3900
3901         if (!active)
3902                 goto out;
3903
3904         intel_dsc_get_config(pipe_config);
3905         intel_bigjoiner_get_config(pipe_config);
3906
3907         if (!transcoder_is_dsi(pipe_config->cpu_transcoder) ||
3908             DISPLAY_VER(dev_priv) >= 11)
3909                 intel_get_transcoder_timings(crtc, pipe_config);
3910
3911         if (HAS_VRR(dev_priv) && !transcoder_is_dsi(pipe_config->cpu_transcoder))
3912                 intel_vrr_get_config(crtc, pipe_config);
3913
3914         intel_get_pipe_src_size(crtc, pipe_config);
3915
3916         if (IS_HASWELL(dev_priv)) {
3917                 u32 tmp = intel_de_read(dev_priv,
3918                                         TRANSCONF(pipe_config->cpu_transcoder));
3919
3920                 if (tmp & TRANSCONF_OUTPUT_COLORSPACE_YUV_HSW)
3921                         pipe_config->output_format = INTEL_OUTPUT_FORMAT_YCBCR444;
3922                 else
3923                         pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB;
3924         } else {
3925                 pipe_config->output_format =
3926                         bdw_get_pipe_misc_output_format(crtc);
3927         }
3928
3929         pipe_config->gamma_mode = intel_de_read(dev_priv,
3930                                                 GAMMA_MODE(crtc->pipe));
3931
3932         pipe_config->csc_mode = intel_de_read(dev_priv,
3933                                               PIPE_CSC_MODE(crtc->pipe));
3934
3935         if (DISPLAY_VER(dev_priv) >= 9) {
3936                 tmp = intel_de_read(dev_priv, SKL_BOTTOM_COLOR(crtc->pipe));
3937
3938                 if (tmp & SKL_BOTTOM_COLOR_GAMMA_ENABLE)
3939                         pipe_config->gamma_enable = true;
3940
3941                 if (tmp & SKL_BOTTOM_COLOR_CSC_ENABLE)
3942                         pipe_config->csc_enable = true;
3943         } else {
3944                 i9xx_get_pipe_color_config(pipe_config);
3945         }
3946
3947         intel_color_get_config(pipe_config);
3948
3949         tmp = intel_de_read(dev_priv, WM_LINETIME(crtc->pipe));
3950         pipe_config->linetime = REG_FIELD_GET(HSW_LINETIME_MASK, tmp);
3951         if (IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv))
3952                 pipe_config->ips_linetime =
3953                         REG_FIELD_GET(HSW_IPS_LINETIME_MASK, tmp);
3954
3955         if (intel_display_power_get_in_set_if_enabled(dev_priv, &crtc->hw_readout_power_domains,
3956                                                       POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe))) {
3957                 if (DISPLAY_VER(dev_priv) >= 9)
3958                         skl_get_pfit_config(pipe_config);
3959                 else
3960                         ilk_get_pfit_config(pipe_config);
3961         }
3962
3963         hsw_ips_get_config(pipe_config);
3964
3965         if (pipe_config->cpu_transcoder != TRANSCODER_EDP &&
3966             !transcoder_is_dsi(pipe_config->cpu_transcoder)) {
3967                 pipe_config->pixel_multiplier =
3968                         intel_de_read(dev_priv,
3969                                       TRANS_MULT(pipe_config->cpu_transcoder)) + 1;
3970         } else {
3971                 pipe_config->pixel_multiplier = 1;
3972         }
3973
3974         if (!transcoder_is_dsi(pipe_config->cpu_transcoder)) {
3975                 tmp = intel_de_read(dev_priv, DISPLAY_VER(dev_priv) >= 14 ?
3976                                     MTL_CHICKEN_TRANS(pipe_config->cpu_transcoder) :
3977                                     CHICKEN_TRANS(pipe_config->cpu_transcoder));
3978
3979                 pipe_config->framestart_delay = REG_FIELD_GET(HSW_FRAME_START_DELAY_MASK, tmp) + 1;
3980         } else {
3981                 /* no idea if this is correct */
3982                 pipe_config->framestart_delay = 1;
3983         }
3984
3985 out:
3986         intel_display_power_put_all_in_set(dev_priv, &crtc->hw_readout_power_domains);
3987
3988         return active;
3989 }
3990
3991 bool intel_crtc_get_pipe_config(struct intel_crtc_state *crtc_state)
3992 {
3993         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
3994         struct drm_i915_private *i915 = to_i915(crtc->base.dev);
3995
3996         if (!i915->display.funcs.display->get_pipe_config(crtc, crtc_state))
3997                 return false;
3998
3999         crtc_state->hw.active = true;
4000
4001         intel_crtc_readout_derived_state(crtc_state);
4002
4003         return true;
4004 }
4005
4006 /* VESA 640x480x72Hz mode to set on the pipe */
4007 static const struct drm_display_mode load_detect_mode = {
4008         DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
4009                  704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
4010 };
4011
4012 static int intel_modeset_disable_planes(struct drm_atomic_state *state,
4013                                         struct drm_crtc *crtc)
4014 {
4015         struct drm_plane *plane;
4016         struct drm_plane_state *plane_state;
4017         int ret, i;
4018
4019         ret = drm_atomic_add_affected_planes(state, crtc);
4020         if (ret)
4021                 return ret;
4022
4023         for_each_new_plane_in_state(state, plane, plane_state, i) {
4024                 if (plane_state->crtc != crtc)
4025                         continue;
4026
4027                 ret = drm_atomic_set_crtc_for_plane(plane_state, NULL);
4028                 if (ret)
4029                         return ret;
4030
4031                 drm_atomic_set_fb_for_plane(plane_state, NULL);
4032         }
4033
4034         return 0;
4035 }
4036
4037 int intel_get_load_detect_pipe(struct drm_connector *connector,
4038                                struct intel_load_detect_pipe *old,
4039                                struct drm_modeset_acquire_ctx *ctx)
4040 {
4041         struct intel_encoder *encoder =
4042                 intel_attached_encoder(to_intel_connector(connector));
4043         struct intel_crtc *possible_crtc;
4044         struct intel_crtc *crtc = NULL;
4045         struct drm_device *dev = encoder->base.dev;
4046         struct drm_i915_private *dev_priv = to_i915(dev);
4047         struct drm_mode_config *config = &dev->mode_config;
4048         struct drm_atomic_state *state = NULL, *restore_state = NULL;
4049         struct drm_connector_state *connector_state;
4050         struct intel_crtc_state *crtc_state;
4051         int ret;
4052
4053         drm_dbg_kms(&dev_priv->drm, "[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
4054                     connector->base.id, connector->name,
4055                     encoder->base.base.id, encoder->base.name);
4056
4057         old->restore_state = NULL;
4058
4059         drm_WARN_ON(dev, !drm_modeset_is_locked(&config->connection_mutex));
4060
4061         /*
4062          * Algorithm gets a little messy:
4063          *
4064          *   - if the connector already has an assigned crtc, use it (but make
4065          *     sure it's on first)
4066          *
4067          *   - try to find the first unused crtc that can drive this connector,
4068          *     and use that if we find one
4069          */
4070
4071         /* See if we already have a CRTC for this connector */
4072         if (connector->state->crtc) {
4073                 crtc = to_intel_crtc(connector->state->crtc);
4074
4075                 ret = drm_modeset_lock(&crtc->base.mutex, ctx);
4076                 if (ret)
4077                         goto fail;
4078
4079                 /* Make sure the crtc and connector are running */
4080                 goto found;
4081         }
4082
4083         /* Find an unused one (if possible) */
4084         for_each_intel_crtc(dev, possible_crtc) {
4085                 if (!(encoder->base.possible_crtcs &
4086                       drm_crtc_mask(&possible_crtc->base)))
4087                         continue;
4088
4089                 ret = drm_modeset_lock(&possible_crtc->base.mutex, ctx);
4090                 if (ret)
4091                         goto fail;
4092
4093                 if (possible_crtc->base.state->enable) {
4094                         drm_modeset_unlock(&possible_crtc->base.mutex);
4095                         continue;
4096                 }
4097
4098                 crtc = possible_crtc;
4099                 break;
4100         }
4101
4102         /*
4103          * If we didn't find an unused CRTC, don't use any.
4104          */
4105         if (!crtc) {
4106                 drm_dbg_kms(&dev_priv->drm,
4107                             "no pipe available for load-detect\n");
4108                 ret = -ENODEV;
4109                 goto fail;
4110         }
4111
4112 found:
4113         state = drm_atomic_state_alloc(dev);
4114         restore_state = drm_atomic_state_alloc(dev);
4115         if (!state || !restore_state) {
4116                 ret = -ENOMEM;
4117                 goto fail;
4118         }
4119
4120         state->acquire_ctx = ctx;
4121         restore_state->acquire_ctx = ctx;
4122
4123         connector_state = drm_atomic_get_connector_state(state, connector);
4124         if (IS_ERR(connector_state)) {
4125                 ret = PTR_ERR(connector_state);
4126                 goto fail;
4127         }
4128
4129         ret = drm_atomic_set_crtc_for_connector(connector_state, &crtc->base);
4130         if (ret)
4131                 goto fail;
4132
4133         crtc_state = intel_atomic_get_crtc_state(state, crtc);
4134         if (IS_ERR(crtc_state)) {
4135                 ret = PTR_ERR(crtc_state);
4136                 goto fail;
4137         }
4138
4139         crtc_state->uapi.active = true;
4140
4141         ret = drm_atomic_set_mode_for_crtc(&crtc_state->uapi,
4142                                            &load_detect_mode);
4143         if (ret)
4144                 goto fail;
4145
4146         ret = intel_modeset_disable_planes(state, &crtc->base);
4147         if (ret)
4148                 goto fail;
4149
4150         ret = PTR_ERR_OR_ZERO(drm_atomic_get_connector_state(restore_state, connector));
4151         if (!ret)
4152                 ret = PTR_ERR_OR_ZERO(drm_atomic_get_crtc_state(restore_state, &crtc->base));
4153         if (!ret)
4154                 ret = drm_atomic_add_affected_planes(restore_state, &crtc->base);
4155         if (ret) {
4156                 drm_dbg_kms(&dev_priv->drm,
4157                             "Failed to create a copy of old state to restore: %i\n",
4158                             ret);
4159                 goto fail;
4160         }
4161
4162         ret = drm_atomic_commit(state);
4163         if (ret) {
4164                 drm_dbg_kms(&dev_priv->drm,
4165                             "failed to set mode on load-detect pipe\n");
4166                 goto fail;
4167         }
4168
4169         old->restore_state = restore_state;
4170         drm_atomic_state_put(state);
4171
4172         /* let the connector get through one full cycle before testing */
4173         intel_crtc_wait_for_next_vblank(crtc);
4174
4175         return true;
4176
4177 fail:
4178         if (state) {
4179                 drm_atomic_state_put(state);
4180                 state = NULL;
4181         }
4182         if (restore_state) {
4183                 drm_atomic_state_put(restore_state);
4184                 restore_state = NULL;
4185         }
4186
4187         if (ret == -EDEADLK)
4188                 return ret;
4189
4190         return false;
4191 }
4192
4193 void intel_release_load_detect_pipe(struct drm_connector *connector,
4194                                     struct intel_load_detect_pipe *old,
4195                                     struct drm_modeset_acquire_ctx *ctx)
4196 {
4197         struct intel_encoder *intel_encoder =
4198                 intel_attached_encoder(to_intel_connector(connector));
4199         struct drm_i915_private *i915 = to_i915(intel_encoder->base.dev);
4200         struct drm_encoder *encoder = &intel_encoder->base;
4201         struct drm_atomic_state *state = old->restore_state;
4202         int ret;
4203
4204         drm_dbg_kms(&i915->drm, "[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
4205                     connector->base.id, connector->name,
4206                     encoder->base.id, encoder->name);
4207
4208         if (!state)
4209                 return;
4210
4211         ret = drm_atomic_helper_commit_duplicated_state(state, ctx);
4212         if (ret)
4213                 drm_dbg_kms(&i915->drm,
4214                             "Couldn't release load detect pipe: %i\n", ret);
4215         drm_atomic_state_put(state);
4216 }
4217
4218 static int i9xx_pll_refclk(struct drm_device *dev,
4219                            const struct intel_crtc_state *pipe_config)
4220 {
4221         struct drm_i915_private *dev_priv = to_i915(dev);
4222         u32 dpll = pipe_config->dpll_hw_state.dpll;
4223
4224         if ((dpll & PLL_REF_INPUT_MASK) == PLLB_REF_INPUT_SPREADSPECTRUMIN)
4225                 return dev_priv->display.vbt.lvds_ssc_freq;
4226         else if (HAS_PCH_SPLIT(dev_priv))
4227                 return 120000;
4228         else if (DISPLAY_VER(dev_priv) != 2)
4229                 return 96000;
4230         else
4231                 return 48000;
4232 }
4233
4234 /* Returns the clock of the currently programmed mode of the given pipe. */
4235 void i9xx_crtc_clock_get(struct intel_crtc *crtc,
4236                          struct intel_crtc_state *pipe_config)
4237 {
4238         struct drm_device *dev = crtc->base.dev;
4239         struct drm_i915_private *dev_priv = to_i915(dev);
4240         u32 dpll = pipe_config->dpll_hw_state.dpll;
4241         u32 fp;
4242         struct dpll clock;
4243         int port_clock;
4244         int refclk = i9xx_pll_refclk(dev, pipe_config);
4245
4246         if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
4247                 fp = pipe_config->dpll_hw_state.fp0;
4248         else
4249                 fp = pipe_config->dpll_hw_state.fp1;
4250
4251         clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
4252         if (IS_PINEVIEW(dev_priv)) {
4253                 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
4254                 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
4255         } else {
4256                 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
4257                 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
4258         }
4259
4260         if (DISPLAY_VER(dev_priv) != 2) {
4261                 if (IS_PINEVIEW(dev_priv))
4262                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
4263                                 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
4264                 else
4265                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
4266                                DPLL_FPA01_P1_POST_DIV_SHIFT);
4267
4268                 switch (dpll & DPLL_MODE_MASK) {
4269                 case DPLLB_MODE_DAC_SERIAL:
4270                         clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
4271                                 5 : 10;
4272                         break;
4273                 case DPLLB_MODE_LVDS:
4274                         clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
4275                                 7 : 14;
4276                         break;
4277                 default:
4278                         drm_dbg_kms(&dev_priv->drm,
4279                                     "Unknown DPLL mode %08x in programmed "
4280                                     "mode\n", (int)(dpll & DPLL_MODE_MASK));
4281                         return;
4282                 }
4283
4284                 if (IS_PINEVIEW(dev_priv))
4285                         port_clock = pnv_calc_dpll_params(refclk, &clock);
4286                 else
4287                         port_clock = i9xx_calc_dpll_params(refclk, &clock);
4288         } else {
4289                 enum pipe lvds_pipe;
4290
4291                 if (IS_I85X(dev_priv) &&
4292                     intel_lvds_port_enabled(dev_priv, LVDS, &lvds_pipe) &&
4293                     lvds_pipe == crtc->pipe) {
4294                         u32 lvds = intel_de_read(dev_priv, LVDS);
4295
4296                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
4297                                        DPLL_FPA01_P1_POST_DIV_SHIFT);
4298
4299                         if (lvds & LVDS_CLKB_POWER_UP)
4300                                 clock.p2 = 7;
4301                         else
4302                                 clock.p2 = 14;
4303                 } else {
4304                         if (dpll & PLL_P1_DIVIDE_BY_TWO)
4305                                 clock.p1 = 2;
4306                         else {
4307                                 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
4308                                             DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
4309                         }
4310                         if (dpll & PLL_P2_DIVIDE_BY_4)
4311                                 clock.p2 = 4;
4312                         else
4313                                 clock.p2 = 2;
4314                 }
4315
4316                 port_clock = i9xx_calc_dpll_params(refclk, &clock);
4317         }
4318
4319         /*
4320          * This value includes pixel_multiplier. We will use
4321          * port_clock to compute adjusted_mode.crtc_clock in the
4322          * encoder's get_config() function.
4323          */
4324         pipe_config->port_clock = port_clock;
4325 }
4326
4327 int intel_dotclock_calculate(int link_freq,
4328                              const struct intel_link_m_n *m_n)
4329 {
4330         /*
4331          * The calculation for the data clock is:
4332          * pixel_clock = ((m/n)*(link_clock * nr_lanes))/bpp
4333          * But we want to avoid losing precison if possible, so:
4334          * pixel_clock = ((m * link_clock * nr_lanes)/(n*bpp))
4335          *
4336          * and the link clock is simpler:
4337          * link_clock = (m * link_clock) / n
4338          */
4339
4340         if (!m_n->link_n)
4341                 return 0;
4342
4343         return DIV_ROUND_UP_ULL(mul_u32_u32(m_n->link_m, link_freq),
4344                                 m_n->link_n);
4345 }
4346
4347 int intel_crtc_dotclock(const struct intel_crtc_state *pipe_config)
4348 {
4349         int dotclock;
4350
4351         if (intel_crtc_has_dp_encoder(pipe_config))
4352                 dotclock = intel_dotclock_calculate(pipe_config->port_clock,
4353                                                     &pipe_config->dp_m_n);
4354         else if (pipe_config->has_hdmi_sink && pipe_config->pipe_bpp > 24)
4355                 dotclock = DIV_ROUND_CLOSEST(pipe_config->port_clock * 24,
4356                                              pipe_config->pipe_bpp);
4357         else
4358                 dotclock = pipe_config->port_clock;
4359
4360         if (pipe_config->output_format == INTEL_OUTPUT_FORMAT_YCBCR420 &&
4361             !intel_crtc_has_dp_encoder(pipe_config))
4362                 dotclock *= 2;
4363
4364         if (pipe_config->pixel_multiplier)
4365                 dotclock /= pipe_config->pixel_multiplier;
4366
4367         return dotclock;
4368 }
4369
4370 /* Returns the currently programmed mode of the given encoder. */
4371 struct drm_display_mode *
4372 intel_encoder_current_mode(struct intel_encoder *encoder)
4373 {
4374         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
4375         struct intel_crtc_state *crtc_state;
4376         struct drm_display_mode *mode;
4377         struct intel_crtc *crtc;
4378         enum pipe pipe;
4379
4380         if (!encoder->get_hw_state(encoder, &pipe))
4381                 return NULL;
4382
4383         crtc = intel_crtc_for_pipe(dev_priv, pipe);
4384
4385         mode = kzalloc(sizeof(*mode), GFP_KERNEL);
4386         if (!mode)
4387                 return NULL;
4388
4389         crtc_state = intel_crtc_state_alloc(crtc);
4390         if (!crtc_state) {
4391                 kfree(mode);
4392                 return NULL;
4393         }
4394
4395         if (!intel_crtc_get_pipe_config(crtc_state)) {
4396                 kfree(crtc_state);
4397                 kfree(mode);
4398                 return NULL;
4399         }
4400
4401         intel_encoder_get_config(encoder, crtc_state);
4402
4403         intel_mode_from_crtc_timings(mode, &crtc_state->hw.adjusted_mode);
4404
4405         kfree(crtc_state);
4406
4407         return mode;
4408 }
4409
4410 static bool encoders_cloneable(const struct intel_encoder *a,
4411                                const struct intel_encoder *b)
4412 {
4413         /* masks could be asymmetric, so check both ways */
4414         return a == b || (a->cloneable & BIT(b->type) &&
4415                           b->cloneable & BIT(a->type));
4416 }
4417
4418 static bool check_single_encoder_cloning(struct intel_atomic_state *state,
4419                                          struct intel_crtc *crtc,
4420                                          struct intel_encoder *encoder)
4421 {
4422         struct intel_encoder *source_encoder;
4423         struct drm_connector *connector;
4424         struct drm_connector_state *connector_state;
4425         int i;
4426
4427         for_each_new_connector_in_state(&state->base, connector, connector_state, i) {
4428                 if (connector_state->crtc != &crtc->base)
4429                         continue;
4430
4431                 source_encoder =
4432                         to_intel_encoder(connector_state->best_encoder);
4433                 if (!encoders_cloneable(encoder, source_encoder))
4434                         return false;
4435         }
4436
4437         return true;
4438 }
4439
4440 static int icl_add_linked_planes(struct intel_atomic_state *state)
4441 {
4442         struct intel_plane *plane, *linked;
4443         struct intel_plane_state *plane_state, *linked_plane_state;
4444         int i;
4445
4446         for_each_new_intel_plane_in_state(state, plane, plane_state, i) {
4447                 linked = plane_state->planar_linked_plane;
4448
4449                 if (!linked)
4450                         continue;
4451
4452                 linked_plane_state = intel_atomic_get_plane_state(state, linked);
4453                 if (IS_ERR(linked_plane_state))
4454                         return PTR_ERR(linked_plane_state);
4455
4456                 drm_WARN_ON(state->base.dev,
4457                             linked_plane_state->planar_linked_plane != plane);
4458                 drm_WARN_ON(state->base.dev,
4459                             linked_plane_state->planar_slave == plane_state->planar_slave);
4460         }
4461
4462         return 0;
4463 }
4464
4465 static int icl_check_nv12_planes(struct intel_crtc_state *crtc_state)
4466 {
4467         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
4468         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
4469         struct intel_atomic_state *state = to_intel_atomic_state(crtc_state->uapi.state);
4470         struct intel_plane *plane, *linked;
4471         struct intel_plane_state *plane_state;
4472         int i;
4473
4474         if (DISPLAY_VER(dev_priv) < 11)
4475                 return 0;
4476
4477         /*
4478          * Destroy all old plane links and make the slave plane invisible
4479          * in the crtc_state->active_planes mask.
4480          */
4481         for_each_new_intel_plane_in_state(state, plane, plane_state, i) {
4482                 if (plane->pipe != crtc->pipe || !plane_state->planar_linked_plane)
4483                         continue;
4484
4485                 plane_state->planar_linked_plane = NULL;
4486                 if (plane_state->planar_slave && !plane_state->uapi.visible) {
4487                         crtc_state->enabled_planes &= ~BIT(plane->id);
4488                         crtc_state->active_planes &= ~BIT(plane->id);
4489                         crtc_state->update_planes |= BIT(plane->id);
4490                         crtc_state->data_rate[plane->id] = 0;
4491                         crtc_state->rel_data_rate[plane->id] = 0;
4492                 }
4493
4494                 plane_state->planar_slave = false;
4495         }
4496
4497         if (!crtc_state->nv12_planes)
4498                 return 0;
4499
4500         for_each_new_intel_plane_in_state(state, plane, plane_state, i) {
4501                 struct intel_plane_state *linked_state = NULL;
4502
4503                 if (plane->pipe != crtc->pipe ||
4504                     !(crtc_state->nv12_planes & BIT(plane->id)))
4505                         continue;
4506
4507                 for_each_intel_plane_on_crtc(&dev_priv->drm, crtc, linked) {
4508                         if (!icl_is_nv12_y_plane(dev_priv, linked->id))
4509                                 continue;
4510
4511                         if (crtc_state->active_planes & BIT(linked->id))
4512                                 continue;
4513
4514                         linked_state = intel_atomic_get_plane_state(state, linked);
4515                         if (IS_ERR(linked_state))
4516                                 return PTR_ERR(linked_state);
4517
4518                         break;
4519                 }
4520
4521                 if (!linked_state) {
4522                         drm_dbg_kms(&dev_priv->drm,
4523                                     "Need %d free Y planes for planar YUV\n",
4524                                     hweight8(crtc_state->nv12_planes));
4525
4526                         return -EINVAL;
4527                 }
4528
4529                 plane_state->planar_linked_plane = linked;
4530
4531                 linked_state->planar_slave = true;
4532                 linked_state->planar_linked_plane = plane;
4533                 crtc_state->enabled_planes |= BIT(linked->id);
4534                 crtc_state->active_planes |= BIT(linked->id);
4535                 crtc_state->update_planes |= BIT(linked->id);
4536                 crtc_state->data_rate[linked->id] =
4537                         crtc_state->data_rate_y[plane->id];
4538                 crtc_state->rel_data_rate[linked->id] =
4539                         crtc_state->rel_data_rate_y[plane->id];
4540                 drm_dbg_kms(&dev_priv->drm, "Using %s as Y plane for %s\n",
4541                             linked->base.name, plane->base.name);
4542
4543                 /* Copy parameters to slave plane */
4544                 linked_state->ctl = plane_state->ctl | PLANE_CTL_YUV420_Y_PLANE;
4545                 linked_state->color_ctl = plane_state->color_ctl;
4546                 linked_state->view = plane_state->view;
4547                 linked_state->decrypt = plane_state->decrypt;
4548
4549                 intel_plane_copy_hw_state(linked_state, plane_state);
4550                 linked_state->uapi.src = plane_state->uapi.src;
4551                 linked_state->uapi.dst = plane_state->uapi.dst;
4552
4553                 if (icl_is_hdr_plane(dev_priv, plane->id)) {
4554                         if (linked->id == PLANE_SPRITE5)
4555                                 plane_state->cus_ctl |= PLANE_CUS_Y_PLANE_7_ICL;
4556                         else if (linked->id == PLANE_SPRITE4)
4557                                 plane_state->cus_ctl |= PLANE_CUS_Y_PLANE_6_ICL;
4558                         else if (linked->id == PLANE_SPRITE3)
4559                                 plane_state->cus_ctl |= PLANE_CUS_Y_PLANE_5_RKL;
4560                         else if (linked->id == PLANE_SPRITE2)
4561                                 plane_state->cus_ctl |= PLANE_CUS_Y_PLANE_4_RKL;
4562                         else
4563                                 MISSING_CASE(linked->id);
4564                 }
4565         }
4566
4567         return 0;
4568 }
4569
4570 static bool c8_planes_changed(const struct intel_crtc_state *new_crtc_state)
4571 {
4572         struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->uapi.crtc);
4573         struct intel_atomic_state *state =
4574                 to_intel_atomic_state(new_crtc_state->uapi.state);
4575         const struct intel_crtc_state *old_crtc_state =
4576                 intel_atomic_get_old_crtc_state(state, crtc);
4577
4578         return !old_crtc_state->c8_planes != !new_crtc_state->c8_planes;
4579 }
4580
4581 static u16 hsw_linetime_wm(const struct intel_crtc_state *crtc_state)
4582 {
4583         const struct drm_display_mode *pipe_mode =
4584                 &crtc_state->hw.pipe_mode;
4585         int linetime_wm;
4586
4587         if (!crtc_state->hw.enable)
4588                 return 0;
4589
4590         linetime_wm = DIV_ROUND_CLOSEST(pipe_mode->crtc_htotal * 1000 * 8,
4591                                         pipe_mode->crtc_clock);
4592
4593         return min(linetime_wm, 0x1ff);
4594 }
4595
4596 static u16 hsw_ips_linetime_wm(const struct intel_crtc_state *crtc_state,
4597                                const struct intel_cdclk_state *cdclk_state)
4598 {
4599         const struct drm_display_mode *pipe_mode =
4600                 &crtc_state->hw.pipe_mode;
4601         int linetime_wm;
4602
4603         if (!crtc_state->hw.enable)
4604                 return 0;
4605
4606         linetime_wm = DIV_ROUND_CLOSEST(pipe_mode->crtc_htotal * 1000 * 8,
4607                                         cdclk_state->logical.cdclk);
4608
4609         return min(linetime_wm, 0x1ff);
4610 }
4611
4612 static u16 skl_linetime_wm(const struct intel_crtc_state *crtc_state)
4613 {
4614         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
4615         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
4616         const struct drm_display_mode *pipe_mode =
4617                 &crtc_state->hw.pipe_mode;
4618         int linetime_wm;
4619
4620         if (!crtc_state->hw.enable)
4621                 return 0;
4622
4623         linetime_wm = DIV_ROUND_UP(pipe_mode->crtc_htotal * 1000 * 8,
4624                                    crtc_state->pixel_rate);
4625
4626         /* Display WA #1135: BXT:ALL GLK:ALL */
4627         if ((IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) &&
4628             skl_watermark_ipc_enabled(dev_priv))
4629                 linetime_wm /= 2;
4630
4631         return min(linetime_wm, 0x1ff);
4632 }
4633
4634 static int hsw_compute_linetime_wm(struct intel_atomic_state *state,
4635                                    struct intel_crtc *crtc)
4636 {
4637         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
4638         struct intel_crtc_state *crtc_state =
4639                 intel_atomic_get_new_crtc_state(state, crtc);
4640         const struct intel_cdclk_state *cdclk_state;
4641
4642         if (DISPLAY_VER(dev_priv) >= 9)
4643                 crtc_state->linetime = skl_linetime_wm(crtc_state);
4644         else
4645                 crtc_state->linetime = hsw_linetime_wm(crtc_state);
4646
4647         if (!hsw_crtc_supports_ips(crtc))
4648                 return 0;
4649
4650         cdclk_state = intel_atomic_get_cdclk_state(state);
4651         if (IS_ERR(cdclk_state))
4652                 return PTR_ERR(cdclk_state);
4653
4654         crtc_state->ips_linetime = hsw_ips_linetime_wm(crtc_state,
4655                                                        cdclk_state);
4656
4657         return 0;
4658 }
4659
4660 static int intel_crtc_atomic_check(struct intel_atomic_state *state,
4661                                    struct intel_crtc *crtc)
4662 {
4663         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
4664         struct intel_crtc_state *crtc_state =
4665                 intel_atomic_get_new_crtc_state(state, crtc);
4666         int ret;
4667
4668         if (DISPLAY_VER(dev_priv) < 5 && !IS_G4X(dev_priv) &&
4669             intel_crtc_needs_modeset(crtc_state) &&
4670             !crtc_state->hw.active)
4671                 crtc_state->update_wm_post = true;
4672
4673         if (intel_crtc_needs_modeset(crtc_state)) {
4674                 ret = intel_dpll_crtc_get_shared_dpll(state, crtc);
4675                 if (ret)
4676                         return ret;
4677         }
4678
4679         /*
4680          * May need to update pipe gamma enable bits
4681          * when C8 planes are getting enabled/disabled.
4682          */
4683         if (c8_planes_changed(crtc_state))
4684                 crtc_state->uapi.color_mgmt_changed = true;
4685
4686         if (intel_crtc_needs_color_update(crtc_state)) {
4687                 ret = intel_color_check(crtc_state);
4688                 if (ret)
4689                         return ret;
4690         }
4691
4692         ret = intel_compute_pipe_wm(state, crtc);
4693         if (ret) {
4694                 drm_dbg_kms(&dev_priv->drm,
4695                             "Target pipe watermarks are invalid\n");
4696                 return ret;
4697         }
4698
4699         /*
4700          * Calculate 'intermediate' watermarks that satisfy both the
4701          * old state and the new state.  We can program these
4702          * immediately.
4703          */
4704         ret = intel_compute_intermediate_wm(state, crtc);
4705         if (ret) {
4706                 drm_dbg_kms(&dev_priv->drm,
4707                             "No valid intermediate pipe watermarks are possible\n");
4708                 return ret;
4709         }
4710
4711         if (DISPLAY_VER(dev_priv) >= 9) {
4712                 if (intel_crtc_needs_modeset(crtc_state) ||
4713                     intel_crtc_needs_fastset(crtc_state)) {
4714                         ret = skl_update_scaler_crtc(crtc_state);
4715                         if (ret)
4716                                 return ret;
4717                 }
4718
4719                 ret = intel_atomic_setup_scalers(dev_priv, crtc, crtc_state);
4720                 if (ret)
4721                         return ret;
4722         }
4723
4724         if (HAS_IPS(dev_priv)) {
4725                 ret = hsw_ips_compute_config(state, crtc);
4726                 if (ret)
4727                         return ret;
4728         }
4729
4730         if (DISPLAY_VER(dev_priv) >= 9 ||
4731             IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv)) {
4732                 ret = hsw_compute_linetime_wm(state, crtc);
4733                 if (ret)
4734                         return ret;
4735
4736         }
4737
4738         ret = intel_psr2_sel_fetch_update(state, crtc);
4739         if (ret)
4740                 return ret;
4741
4742         return 0;
4743 }
4744
4745 static int
4746 compute_sink_pipe_bpp(const struct drm_connector_state *conn_state,
4747                       struct intel_crtc_state *crtc_state)
4748 {
4749         struct drm_connector *connector = conn_state->connector;
4750         struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev);
4751         const struct drm_display_info *info = &connector->display_info;
4752         int bpp;
4753
4754         switch (conn_state->max_bpc) {
4755         case 6 ... 7:
4756                 bpp = 6 * 3;
4757                 break;
4758         case 8 ... 9:
4759                 bpp = 8 * 3;
4760                 break;
4761         case 10 ... 11:
4762                 bpp = 10 * 3;
4763                 break;
4764         case 12 ... 16:
4765                 bpp = 12 * 3;
4766                 break;
4767         default:
4768                 MISSING_CASE(conn_state->max_bpc);
4769                 return -EINVAL;
4770         }
4771
4772         if (bpp < crtc_state->pipe_bpp) {
4773                 drm_dbg_kms(&i915->drm,
4774                             "[CONNECTOR:%d:%s] Limiting display bpp to %d "
4775                             "(EDID bpp %d, max requested bpp %d, max platform bpp %d)\n",
4776                             connector->base.id, connector->name,
4777                             bpp, 3 * info->bpc,
4778                             3 * conn_state->max_requested_bpc,
4779                             crtc_state->pipe_bpp);
4780
4781                 crtc_state->pipe_bpp = bpp;
4782         }
4783
4784         return 0;
4785 }
4786
4787 static int
4788 compute_baseline_pipe_bpp(struct intel_atomic_state *state,
4789                           struct intel_crtc *crtc)
4790 {
4791         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
4792         struct intel_crtc_state *crtc_state =
4793                 intel_atomic_get_new_crtc_state(state, crtc);
4794         struct drm_connector *connector;
4795         struct drm_connector_state *connector_state;
4796         int bpp, i;
4797
4798         if ((IS_G4X(dev_priv) || IS_VALLEYVIEW(dev_priv) ||
4799             IS_CHERRYVIEW(dev_priv)))
4800                 bpp = 10*3;
4801         else if (DISPLAY_VER(dev_priv) >= 5)
4802                 bpp = 12*3;
4803         else
4804                 bpp = 8*3;
4805
4806         crtc_state->pipe_bpp = bpp;
4807
4808         /* Clamp display bpp to connector max bpp */
4809         for_each_new_connector_in_state(&state->base, connector, connector_state, i) {
4810                 int ret;
4811
4812                 if (connector_state->crtc != &crtc->base)
4813                         continue;
4814
4815                 ret = compute_sink_pipe_bpp(connector_state, crtc_state);
4816                 if (ret)
4817                         return ret;
4818         }
4819
4820         return 0;
4821 }
4822
4823 static bool check_digital_port_conflicts(struct intel_atomic_state *state)
4824 {
4825         struct drm_device *dev = state->base.dev;
4826         struct drm_connector *connector;
4827         struct drm_connector_list_iter conn_iter;
4828         unsigned int used_ports = 0;
4829         unsigned int used_mst_ports = 0;
4830         bool ret = true;
4831
4832         /*
4833          * We're going to peek into connector->state,
4834          * hence connection_mutex must be held.
4835          */
4836         drm_modeset_lock_assert_held(&dev->mode_config.connection_mutex);
4837
4838         /*
4839          * Walk the connector list instead of the encoder
4840          * list to detect the problem on ddi platforms
4841          * where there's just one encoder per digital port.
4842          */
4843         drm_connector_list_iter_begin(dev, &conn_iter);
4844         drm_for_each_connector_iter(connector, &conn_iter) {
4845                 struct drm_connector_state *connector_state;
4846                 struct intel_encoder *encoder;
4847
4848                 connector_state =
4849                         drm_atomic_get_new_connector_state(&state->base,
4850                                                            connector);
4851                 if (!connector_state)
4852                         connector_state = connector->state;
4853
4854                 if (!connector_state->best_encoder)
4855                         continue;
4856
4857                 encoder = to_intel_encoder(connector_state->best_encoder);
4858
4859                 drm_WARN_ON(dev, !connector_state->crtc);
4860
4861                 switch (encoder->type) {
4862                 case INTEL_OUTPUT_DDI:
4863                         if (drm_WARN_ON(dev, !HAS_DDI(to_i915(dev))))
4864                                 break;
4865                         fallthrough;
4866                 case INTEL_OUTPUT_DP:
4867                 case INTEL_OUTPUT_HDMI:
4868                 case INTEL_OUTPUT_EDP:
4869                         /* the same port mustn't appear more than once */
4870                         if (used_ports & BIT(encoder->port))
4871                                 ret = false;
4872
4873                         used_ports |= BIT(encoder->port);
4874                         break;
4875                 case INTEL_OUTPUT_DP_MST:
4876                         used_mst_ports |=
4877                                 1 << encoder->port;
4878                         break;
4879                 default:
4880                         break;
4881                 }
4882         }
4883         drm_connector_list_iter_end(&conn_iter);
4884
4885         /* can't mix MST and SST/HDMI on the same port */
4886         if (used_ports & used_mst_ports)
4887                 return false;
4888
4889         return ret;
4890 }
4891
4892 static void
4893 intel_crtc_copy_uapi_to_hw_state_nomodeset(struct intel_atomic_state *state,
4894                                            struct intel_crtc *crtc)
4895 {
4896         struct intel_crtc_state *crtc_state =
4897                 intel_atomic_get_new_crtc_state(state, crtc);
4898
4899         WARN_ON(intel_crtc_is_bigjoiner_slave(crtc_state));
4900
4901         drm_property_replace_blob(&crtc_state->hw.degamma_lut,
4902                                   crtc_state->uapi.degamma_lut);
4903         drm_property_replace_blob(&crtc_state->hw.gamma_lut,
4904                                   crtc_state->uapi.gamma_lut);
4905         drm_property_replace_blob(&crtc_state->hw.ctm,
4906                                   crtc_state->uapi.ctm);
4907 }
4908
4909 static void
4910 intel_crtc_copy_uapi_to_hw_state_modeset(struct intel_atomic_state *state,
4911                                          struct intel_crtc *crtc)
4912 {
4913         struct intel_crtc_state *crtc_state =
4914                 intel_atomic_get_new_crtc_state(state, crtc);
4915
4916         WARN_ON(intel_crtc_is_bigjoiner_slave(crtc_state));
4917
4918         crtc_state->hw.enable = crtc_state->uapi.enable;
4919         crtc_state->hw.active = crtc_state->uapi.active;
4920         drm_mode_copy(&crtc_state->hw.mode,
4921                       &crtc_state->uapi.mode);
4922         drm_mode_copy(&crtc_state->hw.adjusted_mode,
4923                       &crtc_state->uapi.adjusted_mode);
4924         crtc_state->hw.scaling_filter = crtc_state->uapi.scaling_filter;
4925
4926         intel_crtc_copy_uapi_to_hw_state_nomodeset(state, crtc);
4927 }
4928
4929 static void
4930 copy_bigjoiner_crtc_state_nomodeset(struct intel_atomic_state *state,
4931                                     struct intel_crtc *slave_crtc)
4932 {
4933         struct intel_crtc_state *slave_crtc_state =
4934                 intel_atomic_get_new_crtc_state(state, slave_crtc);
4935         struct intel_crtc *master_crtc = intel_master_crtc(slave_crtc_state);
4936         const struct intel_crtc_state *master_crtc_state =
4937                 intel_atomic_get_new_crtc_state(state, master_crtc);
4938
4939         drm_property_replace_blob(&slave_crtc_state->hw.degamma_lut,
4940                                   master_crtc_state->hw.degamma_lut);
4941         drm_property_replace_blob(&slave_crtc_state->hw.gamma_lut,
4942                                   master_crtc_state->hw.gamma_lut);
4943         drm_property_replace_blob(&slave_crtc_state->hw.ctm,
4944                                   master_crtc_state->hw.ctm);
4945
4946         slave_crtc_state->uapi.color_mgmt_changed = master_crtc_state->uapi.color_mgmt_changed;
4947 }
4948
4949 static int
4950 copy_bigjoiner_crtc_state_modeset(struct intel_atomic_state *state,
4951                                   struct intel_crtc *slave_crtc)
4952 {
4953         struct intel_crtc_state *slave_crtc_state =
4954                 intel_atomic_get_new_crtc_state(state, slave_crtc);
4955         struct intel_crtc *master_crtc = intel_master_crtc(slave_crtc_state);
4956         const struct intel_crtc_state *master_crtc_state =
4957                 intel_atomic_get_new_crtc_state(state, master_crtc);
4958         struct intel_crtc_state *saved_state;
4959
4960         WARN_ON(master_crtc_state->bigjoiner_pipes !=
4961                 slave_crtc_state->bigjoiner_pipes);
4962
4963         saved_state = kmemdup(master_crtc_state, sizeof(*saved_state), GFP_KERNEL);
4964         if (!saved_state)
4965                 return -ENOMEM;
4966
4967         /* preserve some things from the slave's original crtc state */
4968         saved_state->uapi = slave_crtc_state->uapi;
4969         saved_state->scaler_state = slave_crtc_state->scaler_state;
4970         saved_state->shared_dpll = slave_crtc_state->shared_dpll;
4971         saved_state->dpll_hw_state = slave_crtc_state->dpll_hw_state;
4972         saved_state->crc_enabled = slave_crtc_state->crc_enabled;
4973
4974         intel_crtc_free_hw_state(slave_crtc_state);
4975         memcpy(slave_crtc_state, saved_state, sizeof(*slave_crtc_state));
4976         kfree(saved_state);
4977
4978         /* Re-init hw state */
4979         memset(&slave_crtc_state->hw, 0, sizeof(slave_crtc_state->hw));
4980         slave_crtc_state->hw.enable = master_crtc_state->hw.enable;
4981         slave_crtc_state->hw.active = master_crtc_state->hw.active;
4982         drm_mode_copy(&slave_crtc_state->hw.mode,
4983                       &master_crtc_state->hw.mode);
4984         drm_mode_copy(&slave_crtc_state->hw.pipe_mode,
4985                       &master_crtc_state->hw.pipe_mode);
4986         drm_mode_copy(&slave_crtc_state->hw.adjusted_mode,
4987                       &master_crtc_state->hw.adjusted_mode);
4988         slave_crtc_state->hw.scaling_filter = master_crtc_state->hw.scaling_filter;
4989
4990         copy_bigjoiner_crtc_state_nomodeset(state, slave_crtc);
4991
4992         slave_crtc_state->uapi.mode_changed = master_crtc_state->uapi.mode_changed;
4993         slave_crtc_state->uapi.connectors_changed = master_crtc_state->uapi.connectors_changed;
4994         slave_crtc_state->uapi.active_changed = master_crtc_state->uapi.active_changed;
4995
4996         WARN_ON(master_crtc_state->bigjoiner_pipes !=
4997                 slave_crtc_state->bigjoiner_pipes);
4998
4999         return 0;
5000 }
5001
5002 static int
5003 intel_crtc_prepare_cleared_state(struct intel_atomic_state *state,
5004                                  struct intel_crtc *crtc)
5005 {
5006         struct intel_crtc_state *crtc_state =
5007                 intel_atomic_get_new_crtc_state(state, crtc);
5008         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
5009         struct intel_crtc_state *saved_state;
5010
5011         saved_state = intel_crtc_state_alloc(crtc);
5012         if (!saved_state)
5013                 return -ENOMEM;
5014
5015         /* free the old crtc_state->hw members */
5016         intel_crtc_free_hw_state(crtc_state);
5017
5018         /* FIXME: before the switch to atomic started, a new pipe_config was
5019          * kzalloc'd. Code that depends on any field being zero should be
5020          * fixed, so that the crtc_state can be safely duplicated. For now,
5021          * only fields that are know to not cause problems are preserved. */
5022
5023         saved_state->uapi = crtc_state->uapi;
5024         saved_state->inherited = crtc_state->inherited;
5025         saved_state->scaler_state = crtc_state->scaler_state;
5026         saved_state->shared_dpll = crtc_state->shared_dpll;
5027         saved_state->dpll_hw_state = crtc_state->dpll_hw_state;
5028         memcpy(saved_state->icl_port_dplls, crtc_state->icl_port_dplls,
5029                sizeof(saved_state->icl_port_dplls));
5030         saved_state->crc_enabled = crtc_state->crc_enabled;
5031         if (IS_G4X(dev_priv) ||
5032             IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
5033                 saved_state->wm = crtc_state->wm;
5034
5035         memcpy(crtc_state, saved_state, sizeof(*crtc_state));
5036         kfree(saved_state);
5037
5038         intel_crtc_copy_uapi_to_hw_state_modeset(state, crtc);
5039
5040         return 0;
5041 }
5042
5043 static int
5044 intel_modeset_pipe_config(struct intel_atomic_state *state,
5045                           struct intel_crtc *crtc)
5046 {
5047         struct drm_i915_private *i915 = to_i915(crtc->base.dev);
5048         struct intel_crtc_state *crtc_state =
5049                 intel_atomic_get_new_crtc_state(state, crtc);
5050         struct drm_connector *connector;
5051         struct drm_connector_state *connector_state;
5052         int pipe_src_w, pipe_src_h;
5053         int base_bpp, ret, i;
5054         bool retry = true;
5055
5056         crtc_state->cpu_transcoder = (enum transcoder) crtc->pipe;
5057
5058         crtc_state->framestart_delay = 1;
5059
5060         /*
5061          * Sanitize sync polarity flags based on requested ones. If neither
5062          * positive or negative polarity is requested, treat this as meaning
5063          * negative polarity.
5064          */
5065         if (!(crtc_state->hw.adjusted_mode.flags &
5066               (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NHSYNC)))
5067                 crtc_state->hw.adjusted_mode.flags |= DRM_MODE_FLAG_NHSYNC;
5068
5069         if (!(crtc_state->hw.adjusted_mode.flags &
5070               (DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC)))
5071                 crtc_state->hw.adjusted_mode.flags |= DRM_MODE_FLAG_NVSYNC;
5072
5073         ret = compute_baseline_pipe_bpp(state, crtc);
5074         if (ret)
5075                 return ret;
5076
5077         base_bpp = crtc_state->pipe_bpp;
5078
5079         /*
5080          * Determine the real pipe dimensions. Note that stereo modes can
5081          * increase the actual pipe size due to the frame doubling and
5082          * insertion of additional space for blanks between the frame. This
5083          * is stored in the crtc timings. We use the requested mode to do this
5084          * computation to clearly distinguish it from the adjusted mode, which
5085          * can be changed by the connectors in the below retry loop.
5086          */
5087         drm_mode_get_hv_timing(&crtc_state->hw.mode,
5088                                &pipe_src_w, &pipe_src_h);
5089         drm_rect_init(&crtc_state->pipe_src, 0, 0,
5090                       pipe_src_w, pipe_src_h);
5091
5092         for_each_new_connector_in_state(&state->base, connector, connector_state, i) {
5093                 struct intel_encoder *encoder =
5094                         to_intel_encoder(connector_state->best_encoder);
5095
5096                 if (connector_state->crtc != &crtc->base)
5097                         continue;
5098
5099                 if (!check_single_encoder_cloning(state, crtc, encoder)) {
5100                         drm_dbg_kms(&i915->drm,
5101                                     "[ENCODER:%d:%s] rejecting invalid cloning configuration\n",
5102                                     encoder->base.base.id, encoder->base.name);
5103                         return -EINVAL;
5104                 }
5105
5106                 /*
5107                  * Determine output_types before calling the .compute_config()
5108                  * hooks so that the hooks can use this information safely.
5109                  */
5110                 if (encoder->compute_output_type)
5111                         crtc_state->output_types |=
5112                                 BIT(encoder->compute_output_type(encoder, crtc_state,
5113                                                                  connector_state));
5114                 else
5115                         crtc_state->output_types |= BIT(encoder->type);
5116         }
5117
5118 encoder_retry:
5119         /* Ensure the port clock defaults are reset when retrying. */
5120         crtc_state->port_clock = 0;
5121         crtc_state->pixel_multiplier = 1;
5122
5123         /* Fill in default crtc timings, allow encoders to overwrite them. */
5124         drm_mode_set_crtcinfo(&crtc_state->hw.adjusted_mode,
5125                               CRTC_STEREO_DOUBLE);
5126
5127         /* Pass our mode to the connectors and the CRTC to give them a chance to
5128          * adjust it according to limitations or connector properties, and also
5129          * a chance to reject the mode entirely.
5130          */
5131         for_each_new_connector_in_state(&state->base, connector, connector_state, i) {
5132                 struct intel_encoder *encoder =
5133                         to_intel_encoder(connector_state->best_encoder);
5134
5135                 if (connector_state->crtc != &crtc->base)
5136                         continue;
5137
5138                 ret = encoder->compute_config(encoder, crtc_state,
5139                                               connector_state);
5140                 if (ret == -EDEADLK)
5141                         return ret;
5142                 if (ret < 0) {
5143                         drm_dbg_kms(&i915->drm, "[ENCODER:%d:%s] config failure: %d\n",
5144                                     encoder->base.base.id, encoder->base.name, ret);
5145                         return ret;
5146                 }
5147         }
5148
5149         /* Set default port clock if not overwritten by the encoder. Needs to be
5150          * done afterwards in case the encoder adjusts the mode. */
5151         if (!crtc_state->port_clock)
5152                 crtc_state->port_clock = crtc_state->hw.adjusted_mode.crtc_clock
5153                         * crtc_state->pixel_multiplier;
5154
5155         ret = intel_crtc_compute_config(state, crtc);
5156         if (ret == -EDEADLK)
5157                 return ret;
5158         if (ret == -EAGAIN) {
5159                 if (drm_WARN(&i915->drm, !retry,
5160                              "[CRTC:%d:%s] loop in pipe configuration computation\n",
5161                              crtc->base.base.id, crtc->base.name))
5162                         return -EINVAL;
5163
5164                 drm_dbg_kms(&i915->drm, "[CRTC:%d:%s] bw constrained, retrying\n",
5165                             crtc->base.base.id, crtc->base.name);
5166                 retry = false;
5167                 goto encoder_retry;
5168         }
5169         if (ret < 0) {
5170                 drm_dbg_kms(&i915->drm, "[CRTC:%d:%s] config failure: %d\n",
5171                             crtc->base.base.id, crtc->base.name, ret);
5172                 return ret;
5173         }
5174
5175         /* Dithering seems to not pass-through bits correctly when it should, so
5176          * only enable it on 6bpc panels and when its not a compliance
5177          * test requesting 6bpc video pattern.
5178          */
5179         crtc_state->dither = (crtc_state->pipe_bpp == 6*3) &&
5180                 !crtc_state->dither_force_disable;
5181         drm_dbg_kms(&i915->drm,
5182                     "[CRTC:%d:%s] hw max bpp: %i, pipe bpp: %i, dithering: %i\n",
5183                     crtc->base.base.id, crtc->base.name,
5184                     base_bpp, crtc_state->pipe_bpp, crtc_state->dither);
5185
5186         return 0;
5187 }
5188
5189 static int
5190 intel_modeset_pipe_config_late(struct intel_atomic_state *state,
5191                                struct intel_crtc *crtc)
5192 {
5193         struct intel_crtc_state *crtc_state =
5194                 intel_atomic_get_new_crtc_state(state, crtc);
5195         struct drm_connector_state *conn_state;
5196         struct drm_connector *connector;
5197         int i;
5198
5199         intel_bigjoiner_adjust_pipe_src(crtc_state);
5200
5201         for_each_new_connector_in_state(&state->base, connector,
5202                                         conn_state, i) {
5203                 struct intel_encoder *encoder =
5204                         to_intel_encoder(conn_state->best_encoder);
5205                 int ret;
5206
5207                 if (conn_state->crtc != &crtc->base ||
5208                     !encoder->compute_config_late)
5209                         continue;
5210
5211                 ret = encoder->compute_config_late(encoder, crtc_state,
5212                                                    conn_state);
5213                 if (ret)
5214                         return ret;
5215         }
5216
5217         return 0;
5218 }
5219
5220 bool intel_fuzzy_clock_check(int clock1, int clock2)
5221 {
5222         int diff;
5223
5224         if (clock1 == clock2)
5225                 return true;
5226
5227         if (!clock1 || !clock2)
5228                 return false;
5229
5230         diff = abs(clock1 - clock2);
5231
5232         if (((((diff + clock1 + clock2) * 100)) / (clock1 + clock2)) < 105)
5233                 return true;
5234
5235         return false;
5236 }
5237
5238 static bool
5239 intel_compare_link_m_n(const struct intel_link_m_n *m_n,
5240                        const struct intel_link_m_n *m2_n2)
5241 {
5242         return m_n->tu == m2_n2->tu &&
5243                 m_n->data_m == m2_n2->data_m &&
5244                 m_n->data_n == m2_n2->data_n &&
5245                 m_n->link_m == m2_n2->link_m &&
5246                 m_n->link_n == m2_n2->link_n;
5247 }
5248
5249 static bool
5250 intel_compare_infoframe(const union hdmi_infoframe *a,
5251                         const union hdmi_infoframe *b)
5252 {
5253         return memcmp(a, b, sizeof(*a)) == 0;
5254 }
5255
5256 static bool
5257 intel_compare_dp_vsc_sdp(const struct drm_dp_vsc_sdp *a,
5258                          const struct drm_dp_vsc_sdp *b)
5259 {
5260         return memcmp(a, b, sizeof(*a)) == 0;
5261 }
5262
5263 static bool
5264 intel_compare_buffer(const u8 *a, const u8 *b, size_t len)
5265 {
5266         return memcmp(a, b, len) == 0;
5267 }
5268
5269 static void
5270 pipe_config_infoframe_mismatch(struct drm_i915_private *dev_priv,
5271                                bool fastset, const char *name,
5272                                const union hdmi_infoframe *a,
5273                                const union hdmi_infoframe *b)
5274 {
5275         if (fastset) {
5276                 if (!drm_debug_enabled(DRM_UT_KMS))
5277                         return;
5278
5279                 drm_dbg_kms(&dev_priv->drm,
5280                             "fastset mismatch in %s infoframe\n", name);
5281                 drm_dbg_kms(&dev_priv->drm, "expected:\n");
5282                 hdmi_infoframe_log(KERN_DEBUG, dev_priv->drm.dev, a);
5283                 drm_dbg_kms(&dev_priv->drm, "found:\n");
5284                 hdmi_infoframe_log(KERN_DEBUG, dev_priv->drm.dev, b);
5285         } else {
5286                 drm_err(&dev_priv->drm, "mismatch in %s infoframe\n", name);
5287                 drm_err(&dev_priv->drm, "expected:\n");
5288                 hdmi_infoframe_log(KERN_ERR, dev_priv->drm.dev, a);
5289                 drm_err(&dev_priv->drm, "found:\n");
5290                 hdmi_infoframe_log(KERN_ERR, dev_priv->drm.dev, b);
5291         }
5292 }
5293
5294 static void
5295 pipe_config_dp_vsc_sdp_mismatch(struct drm_i915_private *dev_priv,
5296                                 bool fastset, const char *name,
5297                                 const struct drm_dp_vsc_sdp *a,
5298                                 const struct drm_dp_vsc_sdp *b)
5299 {
5300         if (fastset) {
5301                 if (!drm_debug_enabled(DRM_UT_KMS))
5302                         return;
5303
5304                 drm_dbg_kms(&dev_priv->drm,
5305                             "fastset mismatch in %s dp sdp\n", name);
5306                 drm_dbg_kms(&dev_priv->drm, "expected:\n");
5307                 drm_dp_vsc_sdp_log(KERN_DEBUG, dev_priv->drm.dev, a);
5308                 drm_dbg_kms(&dev_priv->drm, "found:\n");
5309                 drm_dp_vsc_sdp_log(KERN_DEBUG, dev_priv->drm.dev, b);
5310         } else {
5311                 drm_err(&dev_priv->drm, "mismatch in %s dp sdp\n", name);
5312                 drm_err(&dev_priv->drm, "expected:\n");
5313                 drm_dp_vsc_sdp_log(KERN_ERR, dev_priv->drm.dev, a);
5314                 drm_err(&dev_priv->drm, "found:\n");
5315                 drm_dp_vsc_sdp_log(KERN_ERR, dev_priv->drm.dev, b);
5316         }
5317 }
5318
5319 /* Returns the length up to and including the last differing byte */
5320 static size_t
5321 memcmp_diff_len(const u8 *a, const u8 *b, size_t len)
5322 {
5323         int i;
5324
5325         for (i = len - 1; i >= 0; i--) {
5326                 if (a[i] != b[i])
5327                         return i + 1;
5328         }
5329
5330         return 0;
5331 }
5332
5333 static void
5334 pipe_config_buffer_mismatch(struct drm_i915_private *dev_priv,
5335                             bool fastset, const char *name,
5336                             const u8 *a, const u8 *b, size_t len)
5337 {
5338         if (fastset) {
5339                 if (!drm_debug_enabled(DRM_UT_KMS))
5340                         return;
5341
5342                 /* only dump up to the last difference */
5343                 len = memcmp_diff_len(a, b, len);
5344
5345                 drm_dbg_kms(&dev_priv->drm,
5346                             "fastset mismatch in %s buffer\n", name);
5347                 print_hex_dump(KERN_DEBUG, "expected: ", DUMP_PREFIX_NONE,
5348                                16, 0, a, len, false);
5349                 print_hex_dump(KERN_DEBUG, "found: ", DUMP_PREFIX_NONE,
5350                                16, 0, b, len, false);
5351         } else {
5352                 /* only dump up to the last difference */
5353                 len = memcmp_diff_len(a, b, len);
5354
5355                 drm_err(&dev_priv->drm, "mismatch in %s buffer\n", name);
5356                 print_hex_dump(KERN_ERR, "expected: ", DUMP_PREFIX_NONE,
5357                                16, 0, a, len, false);
5358                 print_hex_dump(KERN_ERR, "found: ", DUMP_PREFIX_NONE,
5359                                16, 0, b, len, false);
5360         }
5361 }
5362
5363 static void __printf(4, 5)
5364 pipe_config_mismatch(bool fastset, const struct intel_crtc *crtc,
5365                      const char *name, const char *format, ...)
5366 {
5367         struct drm_i915_private *i915 = to_i915(crtc->base.dev);
5368         struct va_format vaf;
5369         va_list args;
5370
5371         va_start(args, format);
5372         vaf.fmt = format;
5373         vaf.va = &args;
5374
5375         if (fastset)
5376                 drm_dbg_kms(&i915->drm,
5377                             "[CRTC:%d:%s] fastset mismatch in %s %pV\n",
5378                             crtc->base.base.id, crtc->base.name, name, &vaf);
5379         else
5380                 drm_err(&i915->drm, "[CRTC:%d:%s] mismatch in %s %pV\n",
5381                         crtc->base.base.id, crtc->base.name, name, &vaf);
5382
5383         va_end(args);
5384 }
5385
5386 static bool fastboot_enabled(struct drm_i915_private *dev_priv)
5387 {
5388         if (dev_priv->params.fastboot != -1)
5389                 return dev_priv->params.fastboot;
5390
5391         /* Enable fastboot by default on Skylake and newer */
5392         if (DISPLAY_VER(dev_priv) >= 9)
5393                 return true;
5394
5395         /* Enable fastboot by default on VLV and CHV */
5396         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
5397                 return true;
5398
5399         /* Disabled by default on all others */
5400         return false;
5401 }
5402
5403 bool
5404 intel_pipe_config_compare(const struct intel_crtc_state *current_config,
5405                           const struct intel_crtc_state *pipe_config,
5406                           bool fastset)
5407 {
5408         struct drm_i915_private *dev_priv = to_i915(current_config->uapi.crtc->dev);
5409         struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);
5410         bool ret = true;
5411         bool fixup_inherited = fastset &&
5412                 current_config->inherited && !pipe_config->inherited;
5413
5414         if (fixup_inherited && !fastboot_enabled(dev_priv)) {
5415                 drm_dbg_kms(&dev_priv->drm,
5416                             "initial modeset and fastboot not set\n");
5417                 ret = false;
5418         }
5419
5420 #define PIPE_CONF_CHECK_X(name) do { \
5421         if (current_config->name != pipe_config->name) { \
5422                 pipe_config_mismatch(fastset, crtc, __stringify(name), \
5423                                      "(expected 0x%08x, found 0x%08x)", \
5424                                      current_config->name, \
5425                                      pipe_config->name); \
5426                 ret = false; \
5427         } \
5428 } while (0)
5429
5430 #define PIPE_CONF_CHECK_X_WITH_MASK(name, mask) do { \
5431         if ((current_config->name & (mask)) != (pipe_config->name & (mask))) { \
5432                 pipe_config_mismatch(fastset, crtc, __stringify(name), \
5433                                      "(expected 0x%08x, found 0x%08x)", \
5434                                      current_config->name & (mask), \
5435                                      pipe_config->name & (mask)); \
5436                 ret = false; \
5437         } \
5438 } while (0)
5439
5440 #define PIPE_CONF_CHECK_I(name) do { \
5441         if (current_config->name != pipe_config->name) { \
5442                 pipe_config_mismatch(fastset, crtc, __stringify(name), \
5443                                      "(expected %i, found %i)", \
5444                                      current_config->name, \
5445                                      pipe_config->name); \
5446                 ret = false; \
5447         } \
5448 } while (0)
5449
5450 #define PIPE_CONF_CHECK_BOOL(name) do { \
5451         if (current_config->name != pipe_config->name) { \
5452                 pipe_config_mismatch(fastset, crtc,  __stringify(name), \
5453                                      "(expected %s, found %s)", \
5454                                      str_yes_no(current_config->name), \
5455                                      str_yes_no(pipe_config->name)); \
5456                 ret = false; \
5457         } \
5458 } while (0)
5459
5460 /*
5461  * Checks state where we only read out the enabling, but not the entire
5462  * state itself (like full infoframes or ELD for audio). These states
5463  * require a full modeset on bootup to fix up.
5464  */
5465 #define PIPE_CONF_CHECK_BOOL_INCOMPLETE(name) do { \
5466         if (!fixup_inherited || (!current_config->name && !pipe_config->name)) { \
5467                 PIPE_CONF_CHECK_BOOL(name); \
5468         } else { \
5469                 pipe_config_mismatch(fastset, crtc, __stringify(name), \
5470                                      "unable to verify whether state matches exactly, forcing modeset (expected %s, found %s)", \
5471                                      str_yes_no(current_config->name), \
5472                                      str_yes_no(pipe_config->name)); \
5473                 ret = false; \
5474         } \
5475 } while (0)
5476
5477 #define PIPE_CONF_CHECK_P(name) do { \
5478         if (current_config->name != pipe_config->name) { \
5479                 pipe_config_mismatch(fastset, crtc, __stringify(name), \
5480                                      "(expected %p, found %p)", \
5481                                      current_config->name, \
5482                                      pipe_config->name); \
5483                 ret = false; \
5484         } \
5485 } while (0)
5486
5487 #define PIPE_CONF_CHECK_M_N(name) do { \
5488         if (!intel_compare_link_m_n(&current_config->name, \
5489                                     &pipe_config->name)) { \
5490                 pipe_config_mismatch(fastset, crtc, __stringify(name), \
5491                                      "(expected tu %i data %i/%i link %i/%i, " \
5492                                      "found tu %i, data %i/%i link %i/%i)", \
5493                                      current_config->name.tu, \
5494                                      current_config->name.data_m, \
5495                                      current_config->name.data_n, \
5496                                      current_config->name.link_m, \
5497                                      current_config->name.link_n, \
5498                                      pipe_config->name.tu, \
5499                                      pipe_config->name.data_m, \
5500                                      pipe_config->name.data_n, \
5501                                      pipe_config->name.link_m, \
5502                                      pipe_config->name.link_n); \
5503                 ret = false; \
5504         } \
5505 } while (0)
5506
5507 #define PIPE_CONF_CHECK_TIMINGS(name) do { \
5508         PIPE_CONF_CHECK_I(name.crtc_hdisplay); \
5509         PIPE_CONF_CHECK_I(name.crtc_htotal); \
5510         PIPE_CONF_CHECK_I(name.crtc_hblank_start); \
5511         PIPE_CONF_CHECK_I(name.crtc_hblank_end); \
5512         PIPE_CONF_CHECK_I(name.crtc_hsync_start); \
5513         PIPE_CONF_CHECK_I(name.crtc_hsync_end); \
5514         PIPE_CONF_CHECK_I(name.crtc_vdisplay); \
5515         PIPE_CONF_CHECK_I(name.crtc_vtotal); \
5516         PIPE_CONF_CHECK_I(name.crtc_vblank_start); \
5517         PIPE_CONF_CHECK_I(name.crtc_vblank_end); \
5518         PIPE_CONF_CHECK_I(name.crtc_vsync_start); \
5519         PIPE_CONF_CHECK_I(name.crtc_vsync_end); \
5520 } while (0)
5521
5522 #define PIPE_CONF_CHECK_RECT(name) do { \
5523         PIPE_CONF_CHECK_I(name.x1); \
5524         PIPE_CONF_CHECK_I(name.x2); \
5525         PIPE_CONF_CHECK_I(name.y1); \
5526         PIPE_CONF_CHECK_I(name.y2); \
5527 } while (0)
5528
5529 #define PIPE_CONF_CHECK_FLAGS(name, mask) do { \
5530         if ((current_config->name ^ pipe_config->name) & (mask)) { \
5531                 pipe_config_mismatch(fastset, crtc, __stringify(name), \
5532                                      "(%x) (expected %i, found %i)", \
5533                                      (mask), \
5534                                      current_config->name & (mask), \
5535                                      pipe_config->name & (mask)); \
5536                 ret = false; \
5537         } \
5538 } while (0)
5539
5540 #define PIPE_CONF_CHECK_INFOFRAME(name) do { \
5541         if (!intel_compare_infoframe(&current_config->infoframes.name, \
5542                                      &pipe_config->infoframes.name)) { \
5543                 pipe_config_infoframe_mismatch(dev_priv, fastset, __stringify(name), \
5544                                                &current_config->infoframes.name, \
5545                                                &pipe_config->infoframes.name); \
5546                 ret = false; \
5547         } \
5548 } while (0)
5549
5550 #define PIPE_CONF_CHECK_DP_VSC_SDP(name) do { \
5551         if (!current_config->has_psr && !pipe_config->has_psr && \
5552             !intel_compare_dp_vsc_sdp(&current_config->infoframes.name, \
5553                                       &pipe_config->infoframes.name)) { \
5554                 pipe_config_dp_vsc_sdp_mismatch(dev_priv, fastset, __stringify(name), \
5555                                                 &current_config->infoframes.name, \
5556                                                 &pipe_config->infoframes.name); \
5557                 ret = false; \
5558         } \
5559 } while (0)
5560
5561 #define PIPE_CONF_CHECK_BUFFER(name, len) do { \
5562         BUILD_BUG_ON(sizeof(current_config->name) != (len)); \
5563         BUILD_BUG_ON(sizeof(pipe_config->name) != (len)); \
5564         if (!intel_compare_buffer(current_config->name, pipe_config->name, (len))) { \
5565                 pipe_config_buffer_mismatch(dev_priv, fastset, __stringify(name), \
5566                                             current_config->name, \
5567                                             pipe_config->name, \
5568                                             (len)); \
5569                 ret = false; \
5570         } \
5571 } while (0)
5572
5573 #define PIPE_CONF_CHECK_COLOR_LUT(lut, is_pre_csc_lut) do { \
5574         if (current_config->gamma_mode == pipe_config->gamma_mode && \
5575             !intel_color_lut_equal(current_config, \
5576                                    current_config->lut, pipe_config->lut, \
5577                                    is_pre_csc_lut)) {   \
5578                 pipe_config_mismatch(fastset, crtc, __stringify(lut), \
5579                                      "hw_state doesn't match sw_state"); \
5580                 ret = false; \
5581         } \
5582 } while (0)
5583
5584 #define PIPE_CONF_QUIRK(quirk) \
5585         ((current_config->quirks | pipe_config->quirks) & (quirk))
5586
5587         PIPE_CONF_CHECK_I(hw.enable);
5588         PIPE_CONF_CHECK_I(hw.active);
5589
5590         PIPE_CONF_CHECK_I(cpu_transcoder);
5591         PIPE_CONF_CHECK_I(mst_master_transcoder);
5592
5593         PIPE_CONF_CHECK_BOOL(has_pch_encoder);
5594         PIPE_CONF_CHECK_I(fdi_lanes);
5595         PIPE_CONF_CHECK_M_N(fdi_m_n);
5596
5597         PIPE_CONF_CHECK_I(lane_count);
5598         PIPE_CONF_CHECK_X(lane_lat_optim_mask);
5599
5600         if (HAS_DOUBLE_BUFFERED_M_N(dev_priv)) {
5601                 if (!fastset || !pipe_config->seamless_m_n)
5602                         PIPE_CONF_CHECK_M_N(dp_m_n);
5603         } else {
5604                 PIPE_CONF_CHECK_M_N(dp_m_n);
5605                 PIPE_CONF_CHECK_M_N(dp_m2_n2);
5606         }
5607
5608         PIPE_CONF_CHECK_X(output_types);
5609
5610         PIPE_CONF_CHECK_I(framestart_delay);
5611         PIPE_CONF_CHECK_I(msa_timing_delay);
5612
5613         PIPE_CONF_CHECK_TIMINGS(hw.pipe_mode);
5614         PIPE_CONF_CHECK_TIMINGS(hw.adjusted_mode);
5615
5616         PIPE_CONF_CHECK_I(pixel_multiplier);
5617
5618         PIPE_CONF_CHECK_FLAGS(hw.adjusted_mode.flags,
5619                               DRM_MODE_FLAG_INTERLACE);
5620
5621         if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) {
5622                 PIPE_CONF_CHECK_FLAGS(hw.adjusted_mode.flags,
5623                                       DRM_MODE_FLAG_PHSYNC);
5624                 PIPE_CONF_CHECK_FLAGS(hw.adjusted_mode.flags,
5625                                       DRM_MODE_FLAG_NHSYNC);
5626                 PIPE_CONF_CHECK_FLAGS(hw.adjusted_mode.flags,
5627                                       DRM_MODE_FLAG_PVSYNC);
5628                 PIPE_CONF_CHECK_FLAGS(hw.adjusted_mode.flags,
5629                                       DRM_MODE_FLAG_NVSYNC);
5630         }
5631
5632         PIPE_CONF_CHECK_I(output_format);
5633         PIPE_CONF_CHECK_BOOL(has_hdmi_sink);
5634         if ((DISPLAY_VER(dev_priv) < 8 && !IS_HASWELL(dev_priv)) ||
5635             IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
5636                 PIPE_CONF_CHECK_BOOL(limited_color_range);
5637
5638         PIPE_CONF_CHECK_BOOL(hdmi_scrambling);
5639         PIPE_CONF_CHECK_BOOL(hdmi_high_tmds_clock_ratio);
5640         PIPE_CONF_CHECK_BOOL(has_infoframe);
5641         PIPE_CONF_CHECK_BOOL(fec_enable);
5642
5643         PIPE_CONF_CHECK_BOOL_INCOMPLETE(has_audio);
5644         PIPE_CONF_CHECK_BUFFER(eld, MAX_ELD_BYTES);
5645
5646         PIPE_CONF_CHECK_X(gmch_pfit.control);
5647         /* pfit ratios are autocomputed by the hw on gen4+ */
5648         if (DISPLAY_VER(dev_priv) < 4)
5649                 PIPE_CONF_CHECK_X(gmch_pfit.pgm_ratios);
5650         PIPE_CONF_CHECK_X(gmch_pfit.lvds_border_bits);
5651
5652         /*
5653          * Changing the EDP transcoder input mux
5654          * (A_ONOFF vs. A_ON) requires a full modeset.
5655          */
5656         PIPE_CONF_CHECK_BOOL(pch_pfit.force_thru);
5657
5658         if (!fastset) {
5659                 PIPE_CONF_CHECK_RECT(pipe_src);
5660
5661                 PIPE_CONF_CHECK_BOOL(pch_pfit.enabled);
5662                 PIPE_CONF_CHECK_RECT(pch_pfit.dst);
5663
5664                 PIPE_CONF_CHECK_I(scaler_state.scaler_id);
5665                 PIPE_CONF_CHECK_I(pixel_rate);
5666
5667                 PIPE_CONF_CHECK_X(gamma_mode);
5668                 if (IS_CHERRYVIEW(dev_priv))
5669                         PIPE_CONF_CHECK_X(cgm_mode);
5670                 else
5671                         PIPE_CONF_CHECK_X(csc_mode);
5672                 PIPE_CONF_CHECK_BOOL(gamma_enable);
5673                 PIPE_CONF_CHECK_BOOL(csc_enable);
5674
5675                 PIPE_CONF_CHECK_I(linetime);
5676                 PIPE_CONF_CHECK_I(ips_linetime);
5677
5678                 PIPE_CONF_CHECK_COLOR_LUT(pre_csc_lut, true);
5679                 PIPE_CONF_CHECK_COLOR_LUT(post_csc_lut, false);
5680
5681                 if (current_config->active_planes) {
5682                         PIPE_CONF_CHECK_BOOL(has_psr);
5683                         PIPE_CONF_CHECK_BOOL(has_psr2);
5684                         PIPE_CONF_CHECK_BOOL(enable_psr2_sel_fetch);
5685                         PIPE_CONF_CHECK_I(dc3co_exitline);
5686                 }
5687         }
5688
5689         PIPE_CONF_CHECK_BOOL(double_wide);
5690
5691         if (dev_priv->display.dpll.mgr) {
5692                 PIPE_CONF_CHECK_P(shared_dpll);
5693
5694                 PIPE_CONF_CHECK_X(dpll_hw_state.dpll);
5695                 PIPE_CONF_CHECK_X(dpll_hw_state.dpll_md);
5696                 PIPE_CONF_CHECK_X(dpll_hw_state.fp0);
5697                 PIPE_CONF_CHECK_X(dpll_hw_state.fp1);
5698                 PIPE_CONF_CHECK_X(dpll_hw_state.wrpll);
5699                 PIPE_CONF_CHECK_X(dpll_hw_state.spll);
5700                 PIPE_CONF_CHECK_X(dpll_hw_state.ctrl1);
5701                 PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr1);
5702                 PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr2);
5703                 PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr0);
5704                 PIPE_CONF_CHECK_X(dpll_hw_state.div0);
5705                 PIPE_CONF_CHECK_X(dpll_hw_state.ebb0);
5706                 PIPE_CONF_CHECK_X(dpll_hw_state.ebb4);
5707                 PIPE_CONF_CHECK_X(dpll_hw_state.pll0);
5708                 PIPE_CONF_CHECK_X(dpll_hw_state.pll1);
5709                 PIPE_CONF_CHECK_X(dpll_hw_state.pll2);
5710                 PIPE_CONF_CHECK_X(dpll_hw_state.pll3);
5711                 PIPE_CONF_CHECK_X(dpll_hw_state.pll6);
5712                 PIPE_CONF_CHECK_X(dpll_hw_state.pll8);
5713                 PIPE_CONF_CHECK_X(dpll_hw_state.pll9);
5714                 PIPE_CONF_CHECK_X(dpll_hw_state.pll10);
5715                 PIPE_CONF_CHECK_X(dpll_hw_state.pcsdw12);
5716                 PIPE_CONF_CHECK_X(dpll_hw_state.mg_refclkin_ctl);
5717                 PIPE_CONF_CHECK_X(dpll_hw_state.mg_clktop2_coreclkctl1);
5718                 PIPE_CONF_CHECK_X(dpll_hw_state.mg_clktop2_hsclkctl);
5719                 PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_div0);
5720                 PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_div1);
5721                 PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_lf);
5722                 PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_frac_lock);
5723                 PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_ssc);
5724                 PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_bias);
5725                 PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_tdc_coldst_bias);
5726         }
5727
5728         PIPE_CONF_CHECK_X(dsi_pll.ctrl);
5729         PIPE_CONF_CHECK_X(dsi_pll.div);
5730
5731         if (IS_G4X(dev_priv) || DISPLAY_VER(dev_priv) >= 5)
5732                 PIPE_CONF_CHECK_I(pipe_bpp);
5733
5734         if (!fastset || !pipe_config->seamless_m_n) {
5735                 PIPE_CONF_CHECK_I(hw.pipe_mode.crtc_clock);
5736                 PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_clock);
5737         }
5738         PIPE_CONF_CHECK_I(port_clock);
5739
5740         PIPE_CONF_CHECK_I(min_voltage_level);
5741
5742         if (current_config->has_psr || pipe_config->has_psr)
5743                 PIPE_CONF_CHECK_X_WITH_MASK(infoframes.enable,
5744                                             ~intel_hdmi_infoframe_enable(DP_SDP_VSC));
5745         else
5746                 PIPE_CONF_CHECK_X(infoframes.enable);
5747
5748         PIPE_CONF_CHECK_X(infoframes.gcp);
5749         PIPE_CONF_CHECK_INFOFRAME(avi);
5750         PIPE_CONF_CHECK_INFOFRAME(spd);
5751         PIPE_CONF_CHECK_INFOFRAME(hdmi);
5752         PIPE_CONF_CHECK_INFOFRAME(drm);
5753         PIPE_CONF_CHECK_DP_VSC_SDP(vsc);
5754
5755         PIPE_CONF_CHECK_X(sync_mode_slaves_mask);
5756         PIPE_CONF_CHECK_I(master_transcoder);
5757         PIPE_CONF_CHECK_X(bigjoiner_pipes);
5758
5759         PIPE_CONF_CHECK_I(dsc.compression_enable);
5760         PIPE_CONF_CHECK_I(dsc.dsc_split);
5761         PIPE_CONF_CHECK_I(dsc.compressed_bpp);
5762
5763         PIPE_CONF_CHECK_BOOL(splitter.enable);
5764         PIPE_CONF_CHECK_I(splitter.link_count);
5765         PIPE_CONF_CHECK_I(splitter.pixel_overlap);
5766
5767         PIPE_CONF_CHECK_BOOL(vrr.enable);
5768         PIPE_CONF_CHECK_I(vrr.vmin);
5769         PIPE_CONF_CHECK_I(vrr.vmax);
5770         PIPE_CONF_CHECK_I(vrr.flipline);
5771         PIPE_CONF_CHECK_I(vrr.pipeline_full);
5772         PIPE_CONF_CHECK_I(vrr.guardband);
5773
5774 #undef PIPE_CONF_CHECK_X
5775 #undef PIPE_CONF_CHECK_I
5776 #undef PIPE_CONF_CHECK_BOOL
5777 #undef PIPE_CONF_CHECK_BOOL_INCOMPLETE
5778 #undef PIPE_CONF_CHECK_P
5779 #undef PIPE_CONF_CHECK_FLAGS
5780 #undef PIPE_CONF_CHECK_COLOR_LUT
5781 #undef PIPE_CONF_CHECK_TIMINGS
5782 #undef PIPE_CONF_CHECK_RECT
5783 #undef PIPE_CONF_QUIRK
5784
5785         return ret;
5786 }
5787
5788 static void
5789 intel_verify_planes(struct intel_atomic_state *state)
5790 {
5791         struct intel_plane *plane;
5792         const struct intel_plane_state *plane_state;
5793         int i;
5794
5795         for_each_new_intel_plane_in_state(state, plane,
5796                                           plane_state, i)
5797                 assert_plane(plane, plane_state->planar_slave ||
5798                              plane_state->uapi.visible);
5799 }
5800
5801 int intel_modeset_all_pipes(struct intel_atomic_state *state,
5802                             const char *reason)
5803 {
5804         struct drm_i915_private *dev_priv = to_i915(state->base.dev);
5805         struct intel_crtc *crtc;
5806
5807         /*
5808          * Add all pipes to the state, and force
5809          * a modeset on all the active ones.
5810          */
5811         for_each_intel_crtc(&dev_priv->drm, crtc) {
5812                 struct intel_crtc_state *crtc_state;
5813                 int ret;
5814
5815                 crtc_state = intel_atomic_get_crtc_state(&state->base, crtc);
5816                 if (IS_ERR(crtc_state))
5817                         return PTR_ERR(crtc_state);
5818
5819                 if (!crtc_state->hw.active ||
5820                     intel_crtc_needs_modeset(crtc_state))
5821                         continue;
5822
5823                 drm_dbg_kms(&dev_priv->drm, "[CRTC:%d:%s] Full modeset due to %s\n",
5824                             crtc->base.base.id, crtc->base.name, reason);
5825
5826                 crtc_state->uapi.mode_changed = true;
5827                 crtc_state->update_pipe = false;
5828
5829                 ret = drm_atomic_add_affected_connectors(&state->base,
5830                                                          &crtc->base);
5831                 if (ret)
5832                         return ret;
5833
5834                 ret = intel_dp_mst_add_topology_state_for_crtc(state, crtc);
5835                 if (ret)
5836                         return ret;
5837
5838                 ret = intel_atomic_add_affected_planes(state, crtc);
5839                 if (ret)
5840                         return ret;
5841
5842                 crtc_state->update_planes |= crtc_state->active_planes;
5843                 crtc_state->async_flip_planes = 0;
5844                 crtc_state->do_async_flip = false;
5845         }
5846
5847         return 0;
5848 }
5849
5850 /*
5851  * This implements the workaround described in the "notes" section of the mode
5852  * set sequence documentation. When going from no pipes or single pipe to
5853  * multiple pipes, and planes are enabled after the pipe, we need to wait at
5854  * least 2 vblanks on the first pipe before enabling planes on the second pipe.
5855  */
5856 static int hsw_mode_set_planes_workaround(struct intel_atomic_state *state)
5857 {
5858         struct intel_crtc_state *crtc_state;
5859         struct intel_crtc *crtc;
5860         struct intel_crtc_state *first_crtc_state = NULL;
5861         struct intel_crtc_state *other_crtc_state = NULL;
5862         enum pipe first_pipe = INVALID_PIPE, enabled_pipe = INVALID_PIPE;
5863         int i;
5864
5865         /* look at all crtc's that are going to be enabled in during modeset */
5866         for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) {
5867                 if (!crtc_state->hw.active ||
5868                     !intel_crtc_needs_modeset(crtc_state))
5869                         continue;
5870
5871                 if (first_crtc_state) {
5872                         other_crtc_state = crtc_state;
5873                         break;
5874                 } else {
5875                         first_crtc_state = crtc_state;
5876                         first_pipe = crtc->pipe;
5877                 }
5878         }
5879
5880         /* No workaround needed? */
5881         if (!first_crtc_state)
5882                 return 0;
5883
5884         /* w/a possibly needed, check how many crtc's are already enabled. */
5885         for_each_intel_crtc(state->base.dev, crtc) {
5886                 crtc_state = intel_atomic_get_crtc_state(&state->base, crtc);
5887                 if (IS_ERR(crtc_state))
5888                         return PTR_ERR(crtc_state);
5889
5890                 crtc_state->hsw_workaround_pipe = INVALID_PIPE;
5891
5892                 if (!crtc_state->hw.active ||
5893                     intel_crtc_needs_modeset(crtc_state))
5894                         continue;
5895
5896                 /* 2 or more enabled crtcs means no need for w/a */
5897                 if (enabled_pipe != INVALID_PIPE)
5898                         return 0;
5899
5900                 enabled_pipe = crtc->pipe;
5901         }
5902
5903         if (enabled_pipe != INVALID_PIPE)
5904                 first_crtc_state->hsw_workaround_pipe = enabled_pipe;
5905         else if (other_crtc_state)
5906                 other_crtc_state->hsw_workaround_pipe = first_pipe;
5907
5908         return 0;
5909 }
5910
5911 u8 intel_calc_active_pipes(struct intel_atomic_state *state,
5912                            u8 active_pipes)
5913 {
5914         const struct intel_crtc_state *crtc_state;
5915         struct intel_crtc *crtc;
5916         int i;
5917
5918         for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) {
5919                 if (crtc_state->hw.active)
5920                         active_pipes |= BIT(crtc->pipe);
5921                 else
5922                         active_pipes &= ~BIT(crtc->pipe);
5923         }
5924
5925         return active_pipes;
5926 }
5927
5928 static int intel_modeset_checks(struct intel_atomic_state *state)
5929 {
5930         struct drm_i915_private *dev_priv = to_i915(state->base.dev);
5931
5932         state->modeset = true;
5933
5934         if (IS_HASWELL(dev_priv))
5935                 return hsw_mode_set_planes_workaround(state);
5936
5937         return 0;
5938 }
5939
5940 static void intel_crtc_check_fastset(const struct intel_crtc_state *old_crtc_state,
5941                                      struct intel_crtc_state *new_crtc_state)
5942 {
5943         if (!intel_pipe_config_compare(old_crtc_state, new_crtc_state, true))
5944                 return;
5945
5946         new_crtc_state->uapi.mode_changed = false;
5947         if (!intel_crtc_needs_modeset(new_crtc_state))
5948                 new_crtc_state->update_pipe = true;
5949 }
5950
5951 static int intel_crtc_add_planes_to_state(struct intel_atomic_state *state,
5952                                           struct intel_crtc *crtc,
5953                                           u8 plane_ids_mask)
5954 {
5955         struct drm_i915_private *dev_priv = to_i915(state->base.dev);
5956         struct intel_plane *plane;
5957
5958         for_each_intel_plane_on_crtc(&dev_priv->drm, crtc, plane) {
5959                 struct intel_plane_state *plane_state;
5960
5961                 if ((plane_ids_mask & BIT(plane->id)) == 0)
5962                         continue;
5963
5964                 plane_state = intel_atomic_get_plane_state(state, plane);
5965                 if (IS_ERR(plane_state))
5966                         return PTR_ERR(plane_state);
5967         }
5968
5969         return 0;
5970 }
5971
5972 int intel_atomic_add_affected_planes(struct intel_atomic_state *state,
5973                                      struct intel_crtc *crtc)
5974 {
5975         const struct intel_crtc_state *old_crtc_state =
5976                 intel_atomic_get_old_crtc_state(state, crtc);
5977         const struct intel_crtc_state *new_crtc_state =
5978                 intel_atomic_get_new_crtc_state(state, crtc);
5979
5980         return intel_crtc_add_planes_to_state(state, crtc,
5981                                               old_crtc_state->enabled_planes |
5982                                               new_crtc_state->enabled_planes);
5983 }
5984
5985 static bool active_planes_affects_min_cdclk(struct drm_i915_private *dev_priv)
5986 {
5987         /* See {hsw,vlv,ivb}_plane_ratio() */
5988         return IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv) ||
5989                 IS_CHERRYVIEW(dev_priv) || IS_VALLEYVIEW(dev_priv) ||
5990                 IS_IVYBRIDGE(dev_priv);
5991 }
5992
5993 static int intel_crtc_add_bigjoiner_planes(struct intel_atomic_state *state,
5994                                            struct intel_crtc *crtc,
5995                                            struct intel_crtc *other)
5996 {
5997         const struct intel_plane_state *plane_state;
5998         struct intel_plane *plane;
5999         u8 plane_ids = 0;
6000         int i;
6001
6002         for_each_new_intel_plane_in_state(state, plane, plane_state, i) {
6003                 if (plane->pipe == crtc->pipe)
6004                         plane_ids |= BIT(plane->id);
6005         }
6006
6007         return intel_crtc_add_planes_to_state(state, other, plane_ids);
6008 }
6009
6010 static int intel_bigjoiner_add_affected_planes(struct intel_atomic_state *state)
6011 {
6012         struct drm_i915_private *i915 = to_i915(state->base.dev);
6013         const struct intel_crtc_state *crtc_state;
6014         struct intel_crtc *crtc;
6015         int i;
6016
6017         for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) {
6018                 struct intel_crtc *other;
6019
6020                 for_each_intel_crtc_in_pipe_mask(&i915->drm, other,
6021                                                  crtc_state->bigjoiner_pipes) {
6022                         int ret;
6023
6024                         if (crtc == other)
6025                                 continue;
6026
6027                         ret = intel_crtc_add_bigjoiner_planes(state, crtc, other);
6028                         if (ret)
6029                                 return ret;
6030                 }
6031         }
6032
6033         return 0;
6034 }
6035
6036 static int intel_atomic_check_planes(struct intel_atomic_state *state)
6037 {
6038         struct drm_i915_private *dev_priv = to_i915(state->base.dev);
6039         struct intel_crtc_state *old_crtc_state, *new_crtc_state;
6040         struct intel_plane_state *plane_state;
6041         struct intel_plane *plane;
6042         struct intel_crtc *crtc;
6043         int i, ret;
6044
6045         ret = icl_add_linked_planes(state);
6046         if (ret)
6047                 return ret;
6048
6049         ret = intel_bigjoiner_add_affected_planes(state);
6050         if (ret)
6051                 return ret;
6052
6053         for_each_new_intel_plane_in_state(state, plane, plane_state, i) {
6054                 ret = intel_plane_atomic_check(state, plane);
6055                 if (ret) {
6056                         drm_dbg_atomic(&dev_priv->drm,
6057                                        "[PLANE:%d:%s] atomic driver check failed\n",
6058                                        plane->base.base.id, plane->base.name);
6059                         return ret;
6060                 }
6061         }
6062
6063         for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
6064                                             new_crtc_state, i) {
6065                 u8 old_active_planes, new_active_planes;
6066
6067                 ret = icl_check_nv12_planes(new_crtc_state);
6068                 if (ret)
6069                         return ret;
6070
6071                 /*
6072                  * On some platforms the number of active planes affects
6073                  * the planes' minimum cdclk calculation. Add such planes
6074                  * to the state before we compute the minimum cdclk.
6075                  */
6076                 if (!active_planes_affects_min_cdclk(dev_priv))
6077                         continue;
6078
6079                 old_active_planes = old_crtc_state->active_planes & ~BIT(PLANE_CURSOR);
6080                 new_active_planes = new_crtc_state->active_planes & ~BIT(PLANE_CURSOR);
6081
6082                 if (hweight8(old_active_planes) == hweight8(new_active_planes))
6083                         continue;
6084
6085                 ret = intel_crtc_add_planes_to_state(state, crtc, new_active_planes);
6086                 if (ret)
6087                         return ret;
6088         }
6089
6090         return 0;
6091 }
6092
6093 static int intel_atomic_check_crtcs(struct intel_atomic_state *state)
6094 {
6095         struct intel_crtc_state *crtc_state;
6096         struct intel_crtc *crtc;
6097         int i;
6098
6099         for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) {
6100                 struct drm_i915_private *i915 = to_i915(crtc->base.dev);
6101                 int ret;
6102
6103                 ret = intel_crtc_atomic_check(state, crtc);
6104                 if (ret) {
6105                         drm_dbg_atomic(&i915->drm,
6106                                        "[CRTC:%d:%s] atomic driver check failed\n",
6107                                        crtc->base.base.id, crtc->base.name);
6108                         return ret;
6109                 }
6110         }
6111
6112         return 0;
6113 }
6114
6115 static bool intel_cpu_transcoders_need_modeset(struct intel_atomic_state *state,
6116                                                u8 transcoders)
6117 {
6118         const struct intel_crtc_state *new_crtc_state;
6119         struct intel_crtc *crtc;
6120         int i;
6121
6122         for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
6123                 if (new_crtc_state->hw.enable &&
6124                     transcoders & BIT(new_crtc_state->cpu_transcoder) &&
6125                     intel_crtc_needs_modeset(new_crtc_state))
6126                         return true;
6127         }
6128
6129         return false;
6130 }
6131
6132 static bool intel_pipes_need_modeset(struct intel_atomic_state *state,
6133                                      u8 pipes)
6134 {
6135         const struct intel_crtc_state *new_crtc_state;
6136         struct intel_crtc *crtc;
6137         int i;
6138
6139         for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
6140                 if (new_crtc_state->hw.enable &&
6141                     pipes & BIT(crtc->pipe) &&
6142                     intel_crtc_needs_modeset(new_crtc_state))
6143                         return true;
6144         }
6145
6146         return false;
6147 }
6148
6149 static int intel_atomic_check_bigjoiner(struct intel_atomic_state *state,
6150                                         struct intel_crtc *master_crtc)
6151 {
6152         struct drm_i915_private *i915 = to_i915(state->base.dev);
6153         struct intel_crtc_state *master_crtc_state =
6154                 intel_atomic_get_new_crtc_state(state, master_crtc);
6155         struct intel_crtc *slave_crtc;
6156
6157         if (!master_crtc_state->bigjoiner_pipes)
6158                 return 0;
6159
6160         /* sanity check */
6161         if (drm_WARN_ON(&i915->drm,
6162                         master_crtc->pipe != bigjoiner_master_pipe(master_crtc_state)))
6163                 return -EINVAL;
6164
6165         if (master_crtc_state->bigjoiner_pipes & ~bigjoiner_pipes(i915)) {
6166                 drm_dbg_kms(&i915->drm,
6167                             "[CRTC:%d:%s] Cannot act as big joiner master "
6168                             "(need 0x%x as pipes, only 0x%x possible)\n",
6169                             master_crtc->base.base.id, master_crtc->base.name,
6170                             master_crtc_state->bigjoiner_pipes, bigjoiner_pipes(i915));
6171                 return -EINVAL;
6172         }
6173
6174         for_each_intel_crtc_in_pipe_mask(&i915->drm, slave_crtc,
6175                                          intel_crtc_bigjoiner_slave_pipes(master_crtc_state)) {
6176                 struct intel_crtc_state *slave_crtc_state;
6177                 int ret;
6178
6179                 slave_crtc_state = intel_atomic_get_crtc_state(&state->base, slave_crtc);
6180                 if (IS_ERR(slave_crtc_state))
6181                         return PTR_ERR(slave_crtc_state);
6182
6183                 /* master being enabled, slave was already configured? */
6184                 if (slave_crtc_state->uapi.enable) {
6185                         drm_dbg_kms(&i915->drm,
6186                                     "[CRTC:%d:%s] Slave is enabled as normal CRTC, but "
6187                                     "[CRTC:%d:%s] claiming this CRTC for bigjoiner.\n",
6188                                     slave_crtc->base.base.id, slave_crtc->base.name,
6189                                     master_crtc->base.base.id, master_crtc->base.name);
6190                         return -EINVAL;
6191                 }
6192
6193                 /*
6194                  * The state copy logic assumes the master crtc gets processed
6195                  * before the slave crtc during the main compute_config loop.
6196                  * This works because the crtcs are created in pipe order,
6197                  * and the hardware requires master pipe < slave pipe as well.
6198                  * Should that change we need to rethink the logic.
6199                  */
6200                 if (WARN_ON(drm_crtc_index(&master_crtc->base) >
6201                             drm_crtc_index(&slave_crtc->base)))
6202                         return -EINVAL;
6203
6204                 drm_dbg_kms(&i915->drm,
6205                             "[CRTC:%d:%s] Used as slave for big joiner master [CRTC:%d:%s]\n",
6206                             slave_crtc->base.base.id, slave_crtc->base.name,
6207                             master_crtc->base.base.id, master_crtc->base.name);
6208
6209                 slave_crtc_state->bigjoiner_pipes =
6210                         master_crtc_state->bigjoiner_pipes;
6211
6212                 ret = copy_bigjoiner_crtc_state_modeset(state, slave_crtc);
6213                 if (ret)
6214                         return ret;
6215         }
6216
6217         return 0;
6218 }
6219
6220 static void kill_bigjoiner_slave(struct intel_atomic_state *state,
6221                                  struct intel_crtc *master_crtc)
6222 {
6223         struct drm_i915_private *i915 = to_i915(state->base.dev);
6224         struct intel_crtc_state *master_crtc_state =
6225                 intel_atomic_get_new_crtc_state(state, master_crtc);
6226         struct intel_crtc *slave_crtc;
6227
6228         for_each_intel_crtc_in_pipe_mask(&i915->drm, slave_crtc,
6229                                          intel_crtc_bigjoiner_slave_pipes(master_crtc_state)) {
6230                 struct intel_crtc_state *slave_crtc_state =
6231                         intel_atomic_get_new_crtc_state(state, slave_crtc);
6232
6233                 slave_crtc_state->bigjoiner_pipes = 0;
6234
6235                 intel_crtc_copy_uapi_to_hw_state_modeset(state, slave_crtc);
6236         }
6237
6238         master_crtc_state->bigjoiner_pipes = 0;
6239 }
6240
6241 /**
6242  * DOC: asynchronous flip implementation
6243  *
6244  * Asynchronous page flip is the implementation for the DRM_MODE_PAGE_FLIP_ASYNC
6245  * flag. Currently async flip is only supported via the drmModePageFlip IOCTL.
6246  * Correspondingly, support is currently added for primary plane only.
6247  *
6248  * Async flip can only change the plane surface address, so anything else
6249  * changing is rejected from the intel_async_flip_check_hw() function.
6250  * Once this check is cleared, flip done interrupt is enabled using
6251  * the intel_crtc_enable_flip_done() function.
6252  *
6253  * As soon as the surface address register is written, flip done interrupt is
6254  * generated and the requested events are sent to the usersapce in the interrupt
6255  * handler itself. The timestamp and sequence sent during the flip done event
6256  * correspond to the last vblank and have no relation to the actual time when
6257  * the flip done event was sent.
6258  */
6259 static int intel_async_flip_check_uapi(struct intel_atomic_state *state,
6260                                        struct intel_crtc *crtc)
6261 {
6262         struct drm_i915_private *i915 = to_i915(state->base.dev);
6263         const struct intel_crtc_state *new_crtc_state =
6264                 intel_atomic_get_new_crtc_state(state, crtc);
6265         const struct intel_plane_state *old_plane_state;
6266         struct intel_plane_state *new_plane_state;
6267         struct intel_plane *plane;
6268         int i;
6269
6270         if (!new_crtc_state->uapi.async_flip)
6271                 return 0;
6272
6273         if (!new_crtc_state->uapi.active) {
6274                 drm_dbg_kms(&i915->drm,
6275                             "[CRTC:%d:%s] not active\n",
6276                             crtc->base.base.id, crtc->base.name);
6277                 return -EINVAL;
6278         }
6279
6280         if (intel_crtc_needs_modeset(new_crtc_state)) {
6281                 drm_dbg_kms(&i915->drm,
6282                             "[CRTC:%d:%s] modeset required\n",
6283                             crtc->base.base.id, crtc->base.name);
6284                 return -EINVAL;
6285         }
6286
6287         for_each_oldnew_intel_plane_in_state(state, plane, old_plane_state,
6288                                              new_plane_state, i) {
6289                 if (plane->pipe != crtc->pipe)
6290                         continue;
6291
6292                 /*
6293                  * TODO: Async flip is only supported through the page flip IOCTL
6294                  * as of now. So support currently added for primary plane only.
6295                  * Support for other planes on platforms on which supports
6296                  * this(vlv/chv and icl+) should be added when async flip is
6297                  * enabled in the atomic IOCTL path.
6298                  */
6299                 if (!plane->async_flip) {
6300                         drm_dbg_kms(&i915->drm,
6301                                     "[PLANE:%d:%s] async flip not supported\n",
6302                                     plane->base.base.id, plane->base.name);
6303                         return -EINVAL;
6304                 }
6305
6306                 if (!old_plane_state->uapi.fb || !new_plane_state->uapi.fb) {
6307                         drm_dbg_kms(&i915->drm,
6308                                     "[PLANE:%d:%s] no old or new framebuffer\n",
6309                                     plane->base.base.id, plane->base.name);
6310                         return -EINVAL;
6311                 }
6312         }
6313
6314         return 0;
6315 }
6316
6317 static int intel_async_flip_check_hw(struct intel_atomic_state *state, struct intel_crtc *crtc)
6318 {
6319         struct drm_i915_private *i915 = to_i915(state->base.dev);
6320         const struct intel_crtc_state *old_crtc_state, *new_crtc_state;
6321         const struct intel_plane_state *new_plane_state, *old_plane_state;
6322         struct intel_plane *plane;
6323         int i;
6324
6325         old_crtc_state = intel_atomic_get_old_crtc_state(state, crtc);
6326         new_crtc_state = intel_atomic_get_new_crtc_state(state, crtc);
6327
6328         if (!new_crtc_state->uapi.async_flip)
6329                 return 0;
6330
6331         if (!new_crtc_state->hw.active) {
6332                 drm_dbg_kms(&i915->drm,
6333                             "[CRTC:%d:%s] not active\n",
6334                             crtc->base.base.id, crtc->base.name);
6335                 return -EINVAL;
6336         }
6337
6338         if (intel_crtc_needs_modeset(new_crtc_state)) {
6339                 drm_dbg_kms(&i915->drm,
6340                             "[CRTC:%d:%s] modeset required\n",
6341                             crtc->base.base.id, crtc->base.name);
6342                 return -EINVAL;
6343         }
6344
6345         if (old_crtc_state->active_planes != new_crtc_state->active_planes) {
6346                 drm_dbg_kms(&i915->drm,
6347                             "[CRTC:%d:%s] Active planes cannot be in async flip\n",
6348                             crtc->base.base.id, crtc->base.name);
6349                 return -EINVAL;
6350         }
6351
6352         for_each_oldnew_intel_plane_in_state(state, plane, old_plane_state,
6353                                              new_plane_state, i) {
6354                 if (plane->pipe != crtc->pipe)
6355                         continue;
6356
6357                 /*
6358                  * Only async flip capable planes should be in the state
6359                  * if we're really about to ask the hardware to perform
6360                  * an async flip. We should never get this far otherwise.
6361                  */
6362                 if (drm_WARN_ON(&i915->drm,
6363                                 new_crtc_state->do_async_flip && !plane->async_flip))
6364                         return -EINVAL;
6365
6366                 /*
6367                  * Only check async flip capable planes other planes
6368                  * may be involved in the initial commit due to
6369                  * the wm0/ddb optimization.
6370                  *
6371                  * TODO maybe should track which planes actually
6372                  * were requested to do the async flip...
6373                  */
6374                 if (!plane->async_flip)
6375                         continue;
6376
6377                 /*
6378                  * FIXME: This check is kept generic for all platforms.
6379                  * Need to verify this for all gen9 platforms to enable
6380                  * this selectively if required.
6381                  */
6382                 switch (new_plane_state->hw.fb->modifier) {
6383                 case I915_FORMAT_MOD_X_TILED:
6384                 case I915_FORMAT_MOD_Y_TILED:
6385                 case I915_FORMAT_MOD_Yf_TILED:
6386                 case I915_FORMAT_MOD_4_TILED:
6387                         break;
6388                 default:
6389                         drm_dbg_kms(&i915->drm,
6390                                     "[PLANE:%d:%s] Modifier does not support async flips\n",
6391                                     plane->base.base.id, plane->base.name);
6392                         return -EINVAL;
6393                 }
6394
6395                 if (new_plane_state->hw.fb->format->num_planes > 1) {
6396                         drm_dbg_kms(&i915->drm,
6397                                     "[PLANE:%d:%s] Planar formats do not support async flips\n",
6398                                     plane->base.base.id, plane->base.name);
6399                         return -EINVAL;
6400                 }
6401
6402                 if (old_plane_state->view.color_plane[0].mapping_stride !=
6403                     new_plane_state->view.color_plane[0].mapping_stride) {
6404                         drm_dbg_kms(&i915->drm,
6405                                     "[PLANE:%d:%s] Stride cannot be changed in async flip\n",
6406                                     plane->base.base.id, plane->base.name);
6407                         return -EINVAL;
6408                 }
6409
6410                 if (old_plane_state->hw.fb->modifier !=
6411                     new_plane_state->hw.fb->modifier) {
6412                         drm_dbg_kms(&i915->drm,
6413                                     "[PLANE:%d:%s] Modifier cannot be changed in async flip\n",
6414                                     plane->base.base.id, plane->base.name);
6415                         return -EINVAL;
6416                 }
6417
6418                 if (old_plane_state->hw.fb->format !=
6419                     new_plane_state->hw.fb->format) {
6420                         drm_dbg_kms(&i915->drm,
6421                                     "[PLANE:%d:%s] Pixel format cannot be changed in async flip\n",
6422                                     plane->base.base.id, plane->base.name);
6423                         return -EINVAL;
6424                 }
6425
6426                 if (old_plane_state->hw.rotation !=
6427                     new_plane_state->hw.rotation) {
6428                         drm_dbg_kms(&i915->drm,
6429                                     "[PLANE:%d:%s] Rotation cannot be changed in async flip\n",
6430                                     plane->base.base.id, plane->base.name);
6431                         return -EINVAL;
6432                 }
6433
6434                 if (!drm_rect_equals(&old_plane_state->uapi.src, &new_plane_state->uapi.src) ||
6435                     !drm_rect_equals(&old_plane_state->uapi.dst, &new_plane_state->uapi.dst)) {
6436                         drm_dbg_kms(&i915->drm,
6437                                     "[PLANE:%d:%s] Size/co-ordinates cannot be changed in async flip\n",
6438                                     plane->base.base.id, plane->base.name);
6439                         return -EINVAL;
6440                 }
6441
6442                 if (old_plane_state->hw.alpha != new_plane_state->hw.alpha) {
6443                         drm_dbg_kms(&i915->drm,
6444                                     "[PLANES:%d:%s] Alpha value cannot be changed in async flip\n",
6445                                     plane->base.base.id, plane->base.name);
6446                         return -EINVAL;
6447                 }
6448
6449                 if (old_plane_state->hw.pixel_blend_mode !=
6450                     new_plane_state->hw.pixel_blend_mode) {
6451                         drm_dbg_kms(&i915->drm,
6452                                     "[PLANE:%d:%s] Pixel blend mode cannot be changed in async flip\n",
6453                                     plane->base.base.id, plane->base.name);
6454                         return -EINVAL;
6455                 }
6456
6457                 if (old_plane_state->hw.color_encoding != new_plane_state->hw.color_encoding) {
6458                         drm_dbg_kms(&i915->drm,
6459                                     "[PLANE:%d:%s] Color encoding cannot be changed in async flip\n",
6460                                     plane->base.base.id, plane->base.name);
6461                         return -EINVAL;
6462                 }
6463
6464                 if (old_plane_state->hw.color_range != new_plane_state->hw.color_range) {
6465                         drm_dbg_kms(&i915->drm,
6466                                     "[PLANE:%d:%s] Color range cannot be changed in async flip\n",
6467                                     plane->base.base.id, plane->base.name);
6468                         return -EINVAL;
6469                 }
6470
6471                 /* plane decryption is allow to change only in synchronous flips */
6472                 if (old_plane_state->decrypt != new_plane_state->decrypt) {
6473                         drm_dbg_kms(&i915->drm,
6474                                     "[PLANE:%d:%s] Decryption cannot be changed in async flip\n",
6475                                     plane->base.base.id, plane->base.name);
6476                         return -EINVAL;
6477                 }
6478         }
6479
6480         return 0;
6481 }
6482
6483 static int intel_bigjoiner_add_affected_crtcs(struct intel_atomic_state *state)
6484 {
6485         struct drm_i915_private *i915 = to_i915(state->base.dev);
6486         struct intel_crtc_state *crtc_state;
6487         struct intel_crtc *crtc;
6488         u8 affected_pipes = 0;
6489         u8 modeset_pipes = 0;
6490         int i;
6491
6492         for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) {
6493                 affected_pipes |= crtc_state->bigjoiner_pipes;
6494                 if (intel_crtc_needs_modeset(crtc_state))
6495                         modeset_pipes |= crtc_state->bigjoiner_pipes;
6496         }
6497
6498         for_each_intel_crtc_in_pipe_mask(&i915->drm, crtc, affected_pipes) {
6499                 crtc_state = intel_atomic_get_crtc_state(&state->base, crtc);
6500                 if (IS_ERR(crtc_state))
6501                         return PTR_ERR(crtc_state);
6502         }
6503
6504         for_each_intel_crtc_in_pipe_mask(&i915->drm, crtc, modeset_pipes) {
6505                 int ret;
6506
6507                 crtc_state = intel_atomic_get_new_crtc_state(state, crtc);
6508
6509                 crtc_state->uapi.mode_changed = true;
6510
6511                 ret = drm_atomic_add_affected_connectors(&state->base, &crtc->base);
6512                 if (ret)
6513                         return ret;
6514
6515                 ret = intel_atomic_add_affected_planes(state, crtc);
6516                 if (ret)
6517                         return ret;
6518         }
6519
6520         for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) {
6521                 /* Kill old bigjoiner link, we may re-establish afterwards */
6522                 if (intel_crtc_needs_modeset(crtc_state) &&
6523                     intel_crtc_is_bigjoiner_master(crtc_state))
6524                         kill_bigjoiner_slave(state, crtc);
6525         }
6526
6527         return 0;
6528 }
6529
6530 /**
6531  * intel_atomic_check - validate state object
6532  * @dev: drm device
6533  * @_state: state to validate
6534  */
6535 int intel_atomic_check(struct drm_device *dev,
6536                        struct drm_atomic_state *_state)
6537 {
6538         struct drm_i915_private *dev_priv = to_i915(dev);
6539         struct intel_atomic_state *state = to_intel_atomic_state(_state);
6540         struct intel_crtc_state *old_crtc_state, *new_crtc_state;
6541         struct intel_crtc *crtc;
6542         int ret, i;
6543         bool any_ms = false;
6544
6545         for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
6546                                             new_crtc_state, i) {
6547                 if (new_crtc_state->inherited != old_crtc_state->inherited)
6548                         new_crtc_state->uapi.mode_changed = true;
6549
6550                 if (new_crtc_state->uapi.scaling_filter !=
6551                     old_crtc_state->uapi.scaling_filter)
6552                         new_crtc_state->uapi.mode_changed = true;
6553         }
6554
6555         intel_vrr_check_modeset(state);
6556
6557         ret = drm_atomic_helper_check_modeset(dev, &state->base);
6558         if (ret)
6559                 goto fail;
6560
6561         for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
6562                 ret = intel_async_flip_check_uapi(state, crtc);
6563                 if (ret)
6564                         return ret;
6565         }
6566
6567         ret = intel_bigjoiner_add_affected_crtcs(state);
6568         if (ret)
6569                 goto fail;
6570
6571         for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
6572                                             new_crtc_state, i) {
6573                 if (!intel_crtc_needs_modeset(new_crtc_state)) {
6574                         if (intel_crtc_is_bigjoiner_slave(new_crtc_state))
6575                                 copy_bigjoiner_crtc_state_nomodeset(state, crtc);
6576                         else
6577                                 intel_crtc_copy_uapi_to_hw_state_nomodeset(state, crtc);
6578                         continue;
6579                 }
6580
6581                 if (intel_crtc_is_bigjoiner_slave(new_crtc_state)) {
6582                         drm_WARN_ON(&dev_priv->drm, new_crtc_state->uapi.enable);
6583                         continue;
6584                 }
6585
6586                 ret = intel_crtc_prepare_cleared_state(state, crtc);
6587                 if (ret)
6588                         goto fail;
6589
6590                 if (!new_crtc_state->hw.enable)
6591                         continue;
6592
6593                 ret = intel_modeset_pipe_config(state, crtc);
6594                 if (ret)
6595                         goto fail;
6596
6597                 ret = intel_atomic_check_bigjoiner(state, crtc);
6598                 if (ret)
6599                         goto fail;
6600         }
6601
6602         for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
6603                                             new_crtc_state, i) {
6604                 if (!intel_crtc_needs_modeset(new_crtc_state))
6605                         continue;
6606
6607                 if (new_crtc_state->hw.enable) {
6608                         ret = intel_modeset_pipe_config_late(state, crtc);
6609                         if (ret)
6610                                 goto fail;
6611                 }
6612
6613                 intel_crtc_check_fastset(old_crtc_state, new_crtc_state);
6614         }
6615
6616         /**
6617          * Check if fastset is allowed by external dependencies like other
6618          * pipes and transcoders.
6619          *
6620          * Right now it only forces a fullmodeset when the MST master
6621          * transcoder did not changed but the pipe of the master transcoder
6622          * needs a fullmodeset so all slaves also needs to do a fullmodeset or
6623          * in case of port synced crtcs, if one of the synced crtcs
6624          * needs a full modeset, all other synced crtcs should be
6625          * forced a full modeset.
6626          */
6627         for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
6628                 if (!new_crtc_state->hw.enable || intel_crtc_needs_modeset(new_crtc_state))
6629                         continue;
6630
6631                 if (intel_dp_mst_is_slave_trans(new_crtc_state)) {
6632                         enum transcoder master = new_crtc_state->mst_master_transcoder;
6633
6634                         if (intel_cpu_transcoders_need_modeset(state, BIT(master))) {
6635                                 new_crtc_state->uapi.mode_changed = true;
6636                                 new_crtc_state->update_pipe = false;
6637                         }
6638                 }
6639
6640                 if (is_trans_port_sync_mode(new_crtc_state)) {
6641                         u8 trans = new_crtc_state->sync_mode_slaves_mask;
6642
6643                         if (new_crtc_state->master_transcoder != INVALID_TRANSCODER)
6644                                 trans |= BIT(new_crtc_state->master_transcoder);
6645
6646                         if (intel_cpu_transcoders_need_modeset(state, trans)) {
6647                                 new_crtc_state->uapi.mode_changed = true;
6648                                 new_crtc_state->update_pipe = false;
6649                         }
6650                 }
6651
6652                 if (new_crtc_state->bigjoiner_pipes) {
6653                         if (intel_pipes_need_modeset(state, new_crtc_state->bigjoiner_pipes)) {
6654                                 new_crtc_state->uapi.mode_changed = true;
6655                                 new_crtc_state->update_pipe = false;
6656                         }
6657                 }
6658         }
6659
6660         for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
6661                                             new_crtc_state, i) {
6662                 if (!intel_crtc_needs_modeset(new_crtc_state))
6663                         continue;
6664
6665                 any_ms = true;
6666
6667                 intel_release_shared_dplls(state, crtc);
6668         }
6669
6670         if (any_ms && !check_digital_port_conflicts(state)) {
6671                 drm_dbg_kms(&dev_priv->drm,
6672                             "rejecting conflicting digital port configuration\n");
6673                 ret = -EINVAL;
6674                 goto fail;
6675         }
6676
6677         ret = drm_dp_mst_atomic_check(&state->base);
6678         if (ret)
6679                 goto fail;
6680
6681         ret = intel_atomic_check_planes(state);
6682         if (ret)
6683                 goto fail;
6684
6685         ret = intel_compute_global_watermarks(state);
6686         if (ret)
6687                 goto fail;
6688
6689         ret = intel_bw_atomic_check(state);
6690         if (ret)
6691                 goto fail;
6692
6693         ret = intel_cdclk_atomic_check(state, &any_ms);
6694         if (ret)
6695                 goto fail;
6696
6697         if (intel_any_crtc_needs_modeset(state))
6698                 any_ms = true;
6699
6700         if (any_ms) {
6701                 ret = intel_modeset_checks(state);
6702                 if (ret)
6703                         goto fail;
6704
6705                 ret = intel_modeset_calc_cdclk(state);
6706                 if (ret)
6707                         return ret;
6708         }
6709
6710         ret = intel_atomic_check_crtcs(state);
6711         if (ret)
6712                 goto fail;
6713
6714         ret = intel_fbc_atomic_check(state);
6715         if (ret)
6716                 goto fail;
6717
6718         for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
6719                                             new_crtc_state, i) {
6720                 intel_color_assert_luts(new_crtc_state);
6721
6722                 ret = intel_async_flip_check_hw(state, crtc);
6723                 if (ret)
6724                         goto fail;
6725
6726                 /* Either full modeset or fastset (or neither), never both */
6727                 drm_WARN_ON(&dev_priv->drm,
6728                             intel_crtc_needs_modeset(new_crtc_state) &&
6729                             intel_crtc_needs_fastset(new_crtc_state));
6730
6731                 if (!intel_crtc_needs_modeset(new_crtc_state) &&
6732                     !intel_crtc_needs_fastset(new_crtc_state))
6733                         continue;
6734
6735                 intel_crtc_state_dump(new_crtc_state, state,
6736                                       intel_crtc_needs_modeset(new_crtc_state) ?
6737                                       "modeset" : "fastset");
6738         }
6739
6740         return 0;
6741
6742  fail:
6743         if (ret == -EDEADLK)
6744                 return ret;
6745
6746         /*
6747          * FIXME would probably be nice to know which crtc specifically
6748          * caused the failure, in cases where we can pinpoint it.
6749          */
6750         for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
6751                                             new_crtc_state, i)
6752                 intel_crtc_state_dump(new_crtc_state, state, "failed");
6753
6754         return ret;
6755 }
6756
6757 static int intel_atomic_prepare_commit(struct intel_atomic_state *state)
6758 {
6759         struct intel_crtc_state *crtc_state;
6760         struct intel_crtc *crtc;
6761         int i, ret;
6762
6763         ret = drm_atomic_helper_prepare_planes(state->base.dev, &state->base);
6764         if (ret < 0)
6765                 return ret;
6766
6767         for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) {
6768                 if (intel_crtc_needs_color_update(crtc_state))
6769                         intel_color_prepare_commit(crtc_state);
6770         }
6771
6772         return 0;
6773 }
6774
6775 void intel_crtc_arm_fifo_underrun(struct intel_crtc *crtc,
6776                                   struct intel_crtc_state *crtc_state)
6777 {
6778         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
6779
6780         if (DISPLAY_VER(dev_priv) != 2 || crtc_state->active_planes)
6781                 intel_set_cpu_fifo_underrun_reporting(dev_priv, crtc->pipe, true);
6782
6783         if (crtc_state->has_pch_encoder) {
6784                 enum pipe pch_transcoder =
6785                         intel_crtc_pch_transcoder(crtc);
6786
6787                 intel_set_pch_fifo_underrun_reporting(dev_priv, pch_transcoder, true);
6788         }
6789 }
6790
6791 static void intel_pipe_fastset(const struct intel_crtc_state *old_crtc_state,
6792                                const struct intel_crtc_state *new_crtc_state)
6793 {
6794         struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->uapi.crtc);
6795         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
6796
6797         /*
6798          * Update pipe size and adjust fitter if needed: the reason for this is
6799          * that in compute_mode_changes we check the native mode (not the pfit
6800          * mode) to see if we can flip rather than do a full mode set. In the
6801          * fastboot case, we'll flip, but if we don't update the pipesrc and
6802          * pfit state, we'll end up with a big fb scanned out into the wrong
6803          * sized surface.
6804          */
6805         intel_set_pipe_src_size(new_crtc_state);
6806
6807         /* on skylake this is done by detaching scalers */
6808         if (DISPLAY_VER(dev_priv) >= 9) {
6809                 if (new_crtc_state->pch_pfit.enabled)
6810                         skl_pfit_enable(new_crtc_state);
6811         } else if (HAS_PCH_SPLIT(dev_priv)) {
6812                 if (new_crtc_state->pch_pfit.enabled)
6813                         ilk_pfit_enable(new_crtc_state);
6814                 else if (old_crtc_state->pch_pfit.enabled)
6815                         ilk_pfit_disable(old_crtc_state);
6816         }
6817
6818         /*
6819          * The register is supposedly single buffered so perhaps
6820          * not 100% correct to do this here. But SKL+ calculate
6821          * this based on the adjust pixel rate so pfit changes do
6822          * affect it and so it must be updated for fastsets.
6823          * HSW/BDW only really need this here for fastboot, after
6824          * that the value should not change without a full modeset.
6825          */
6826         if (DISPLAY_VER(dev_priv) >= 9 ||
6827             IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv))
6828                 hsw_set_linetime_wm(new_crtc_state);
6829
6830         if (new_crtc_state->seamless_m_n)
6831                 intel_cpu_transcoder_set_m1_n1(crtc, new_crtc_state->cpu_transcoder,
6832                                                &new_crtc_state->dp_m_n);
6833 }
6834
6835 static void commit_pipe_pre_planes(struct intel_atomic_state *state,
6836                                    struct intel_crtc *crtc)
6837 {
6838         struct drm_i915_private *dev_priv = to_i915(state->base.dev);
6839         const struct intel_crtc_state *old_crtc_state =
6840                 intel_atomic_get_old_crtc_state(state, crtc);
6841         const struct intel_crtc_state *new_crtc_state =
6842                 intel_atomic_get_new_crtc_state(state, crtc);
6843         bool modeset = intel_crtc_needs_modeset(new_crtc_state);
6844
6845         /*
6846          * During modesets pipe configuration was programmed as the
6847          * CRTC was enabled.
6848          */
6849         if (!modeset) {
6850                 if (intel_crtc_needs_color_update(new_crtc_state))
6851                         intel_color_commit_arm(new_crtc_state);
6852
6853                 if (DISPLAY_VER(dev_priv) >= 9 || IS_BROADWELL(dev_priv))
6854                         bdw_set_pipe_misc(new_crtc_state);
6855
6856                 if (intel_crtc_needs_fastset(new_crtc_state))
6857                         intel_pipe_fastset(old_crtc_state, new_crtc_state);
6858         }
6859
6860         intel_psr2_program_trans_man_trk_ctl(new_crtc_state);
6861
6862         intel_atomic_update_watermarks(state, crtc);
6863 }
6864
6865 static void commit_pipe_post_planes(struct intel_atomic_state *state,
6866                                     struct intel_crtc *crtc)
6867 {
6868         struct drm_i915_private *dev_priv = to_i915(state->base.dev);
6869         const struct intel_crtc_state *new_crtc_state =
6870                 intel_atomic_get_new_crtc_state(state, crtc);
6871
6872         /*
6873          * Disable the scaler(s) after the plane(s) so that we don't
6874          * get a catastrophic underrun even if the two operations
6875          * end up happening in two different frames.
6876          */
6877         if (DISPLAY_VER(dev_priv) >= 9 &&
6878             !intel_crtc_needs_modeset(new_crtc_state))
6879                 skl_detach_scalers(new_crtc_state);
6880 }
6881
6882 static void intel_enable_crtc(struct intel_atomic_state *state,
6883                               struct intel_crtc *crtc)
6884 {
6885         struct drm_i915_private *dev_priv = to_i915(state->base.dev);
6886         const struct intel_crtc_state *new_crtc_state =
6887                 intel_atomic_get_new_crtc_state(state, crtc);
6888
6889         if (!intel_crtc_needs_modeset(new_crtc_state))
6890                 return;
6891
6892         intel_crtc_update_active_timings(new_crtc_state);
6893
6894         dev_priv->display.funcs.display->crtc_enable(state, crtc);
6895
6896         if (intel_crtc_is_bigjoiner_slave(new_crtc_state))
6897                 return;
6898
6899         /* vblanks work again, re-enable pipe CRC. */
6900         intel_crtc_enable_pipe_crc(crtc);
6901 }
6902
6903 static void intel_update_crtc(struct intel_atomic_state *state,
6904                               struct intel_crtc *crtc)
6905 {
6906         struct drm_i915_private *i915 = to_i915(state->base.dev);
6907         const struct intel_crtc_state *old_crtc_state =
6908                 intel_atomic_get_old_crtc_state(state, crtc);
6909         struct intel_crtc_state *new_crtc_state =
6910                 intel_atomic_get_new_crtc_state(state, crtc);
6911         bool modeset = intel_crtc_needs_modeset(new_crtc_state);
6912
6913         if (old_crtc_state->inherited ||
6914             intel_crtc_needs_modeset(new_crtc_state)) {
6915                 if (HAS_DPT(i915))
6916                         intel_dpt_configure(crtc);
6917         }
6918
6919         if (!modeset) {
6920                 if (new_crtc_state->preload_luts &&
6921                     intel_crtc_needs_color_update(new_crtc_state))
6922                         intel_color_load_luts(new_crtc_state);
6923
6924                 intel_pre_plane_update(state, crtc);
6925
6926                 if (intel_crtc_needs_fastset(new_crtc_state))
6927                         intel_encoders_update_pipe(state, crtc);
6928
6929                 if (DISPLAY_VER(i915) >= 11 &&
6930                     intel_crtc_needs_fastset(new_crtc_state))
6931                         icl_set_pipe_chicken(new_crtc_state);
6932         }
6933
6934         intel_fbc_update(state, crtc);
6935
6936         drm_WARN_ON(&i915->drm, !intel_display_power_is_enabled(i915, POWER_DOMAIN_DC_OFF));
6937
6938         if (!modeset &&
6939             intel_crtc_needs_color_update(new_crtc_state))
6940                 intel_color_commit_noarm(new_crtc_state);
6941
6942         intel_crtc_planes_update_noarm(state, crtc);
6943
6944         /* Perform vblank evasion around commit operation */
6945         intel_pipe_update_start(new_crtc_state);
6946
6947         commit_pipe_pre_planes(state, crtc);
6948
6949         intel_crtc_planes_update_arm(state, crtc);
6950
6951         commit_pipe_post_planes(state, crtc);
6952
6953         intel_pipe_update_end(new_crtc_state);
6954
6955         /*
6956          * We usually enable FIFO underrun interrupts as part of the
6957          * CRTC enable sequence during modesets.  But when we inherit a
6958          * valid pipe configuration from the BIOS we need to take care
6959          * of enabling them on the CRTC's first fastset.
6960          */
6961         if (intel_crtc_needs_fastset(new_crtc_state) && !modeset &&
6962             old_crtc_state->inherited)
6963                 intel_crtc_arm_fifo_underrun(crtc, new_crtc_state);
6964 }
6965
6966 static void intel_old_crtc_state_disables(struct intel_atomic_state *state,
6967                                           struct intel_crtc_state *old_crtc_state,
6968                                           struct intel_crtc_state *new_crtc_state,
6969                                           struct intel_crtc *crtc)
6970 {
6971         struct drm_i915_private *dev_priv = to_i915(state->base.dev);
6972
6973         /*
6974          * We need to disable pipe CRC before disabling the pipe,
6975          * or we race against vblank off.
6976          */
6977         intel_crtc_disable_pipe_crc(crtc);
6978
6979         dev_priv->display.funcs.display->crtc_disable(state, crtc);
6980         crtc->active = false;
6981         intel_fbc_disable(crtc);
6982
6983         if (!new_crtc_state->hw.active)
6984                 intel_initial_watermarks(state, crtc);
6985 }
6986
6987 static void intel_commit_modeset_disables(struct intel_atomic_state *state)
6988 {
6989         struct intel_crtc_state *new_crtc_state, *old_crtc_state;
6990         struct intel_crtc *crtc;
6991         u32 handled = 0;
6992         int i;
6993
6994         for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
6995                                             new_crtc_state, i) {
6996                 if (!intel_crtc_needs_modeset(new_crtc_state))
6997                         continue;
6998
6999                 if (!old_crtc_state->hw.active)
7000                         continue;
7001
7002                 intel_pre_plane_update(state, crtc);
7003                 intel_crtc_disable_planes(state, crtc);
7004         }
7005
7006         /* Only disable port sync and MST slaves */
7007         for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
7008                                             new_crtc_state, i) {
7009                 if (!intel_crtc_needs_modeset(new_crtc_state))
7010                         continue;
7011
7012                 if (!old_crtc_state->hw.active)
7013                         continue;
7014
7015                 /* In case of Transcoder port Sync master slave CRTCs can be
7016                  * assigned in any order and we need to make sure that
7017                  * slave CRTCs are disabled first and then master CRTC since
7018                  * Slave vblanks are masked till Master Vblanks.
7019                  */
7020                 if (!is_trans_port_sync_slave(old_crtc_state) &&
7021                     !intel_dp_mst_is_slave_trans(old_crtc_state) &&
7022                     !intel_crtc_is_bigjoiner_slave(old_crtc_state))
7023                         continue;
7024
7025                 intel_old_crtc_state_disables(state, old_crtc_state,
7026                                               new_crtc_state, crtc);
7027                 handled |= BIT(crtc->pipe);
7028         }
7029
7030         /* Disable everything else left on */
7031         for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
7032                                             new_crtc_state, i) {
7033                 if (!intel_crtc_needs_modeset(new_crtc_state) ||
7034                     (handled & BIT(crtc->pipe)))
7035                         continue;
7036
7037                 if (!old_crtc_state->hw.active)
7038                         continue;
7039
7040                 intel_old_crtc_state_disables(state, old_crtc_state,
7041                                               new_crtc_state, crtc);
7042         }
7043 }
7044
7045 static void intel_commit_modeset_enables(struct intel_atomic_state *state)
7046 {
7047         struct intel_crtc_state *new_crtc_state;
7048         struct intel_crtc *crtc;
7049         int i;
7050
7051         for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
7052                 if (!new_crtc_state->hw.active)
7053                         continue;
7054
7055                 intel_enable_crtc(state, crtc);
7056                 intel_update_crtc(state, crtc);
7057         }
7058 }
7059
7060 static void skl_commit_modeset_enables(struct intel_atomic_state *state)
7061 {
7062         struct drm_i915_private *dev_priv = to_i915(state->base.dev);
7063         struct intel_crtc *crtc;
7064         struct intel_crtc_state *old_crtc_state, *new_crtc_state;
7065         struct skl_ddb_entry entries[I915_MAX_PIPES] = {};
7066         u8 update_pipes = 0, modeset_pipes = 0;
7067         int i;
7068
7069         for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
7070                 enum pipe pipe = crtc->pipe;
7071
7072                 if (!new_crtc_state->hw.active)
7073                         continue;
7074
7075                 /* ignore allocations for crtc's that have been turned off. */
7076                 if (!intel_crtc_needs_modeset(new_crtc_state)) {
7077                         entries[pipe] = old_crtc_state->wm.skl.ddb;
7078                         update_pipes |= BIT(pipe);
7079                 } else {
7080                         modeset_pipes |= BIT(pipe);
7081                 }
7082         }
7083
7084         /*
7085          * Whenever the number of active pipes changes, we need to make sure we
7086          * update the pipes in the right order so that their ddb allocations
7087          * never overlap with each other between CRTC updates. Otherwise we'll
7088          * cause pipe underruns and other bad stuff.
7089          *
7090          * So first lets enable all pipes that do not need a fullmodeset as
7091          * those don't have any external dependency.
7092          */
7093         while (update_pipes) {
7094                 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
7095                                                     new_crtc_state, i) {
7096                         enum pipe pipe = crtc->pipe;
7097
7098                         if ((update_pipes & BIT(pipe)) == 0)
7099                                 continue;
7100
7101                         if (skl_ddb_allocation_overlaps(&new_crtc_state->wm.skl.ddb,
7102                                                         entries, I915_MAX_PIPES, pipe))
7103                                 continue;
7104
7105                         entries[pipe] = new_crtc_state->wm.skl.ddb;
7106                         update_pipes &= ~BIT(pipe);
7107
7108                         intel_update_crtc(state, crtc);
7109
7110                         /*
7111                          * If this is an already active pipe, it's DDB changed,
7112                          * and this isn't the last pipe that needs updating
7113                          * then we need to wait for a vblank to pass for the
7114                          * new ddb allocation to take effect.
7115                          */
7116                         if (!skl_ddb_entry_equal(&new_crtc_state->wm.skl.ddb,
7117                                                  &old_crtc_state->wm.skl.ddb) &&
7118                             (update_pipes | modeset_pipes))
7119                                 intel_crtc_wait_for_next_vblank(crtc);
7120                 }
7121         }
7122
7123         update_pipes = modeset_pipes;
7124
7125         /*
7126          * Enable all pipes that needs a modeset and do not depends on other
7127          * pipes
7128          */
7129         for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
7130                 enum pipe pipe = crtc->pipe;
7131
7132                 if ((modeset_pipes & BIT(pipe)) == 0)
7133                         continue;
7134
7135                 if (intel_dp_mst_is_slave_trans(new_crtc_state) ||
7136                     is_trans_port_sync_master(new_crtc_state) ||
7137                     intel_crtc_is_bigjoiner_master(new_crtc_state))
7138                         continue;
7139
7140                 modeset_pipes &= ~BIT(pipe);
7141
7142                 intel_enable_crtc(state, crtc);
7143         }
7144
7145         /*
7146          * Then we enable all remaining pipes that depend on other
7147          * pipes: MST slaves and port sync masters, big joiner master
7148          */
7149         for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
7150                 enum pipe pipe = crtc->pipe;
7151
7152                 if ((modeset_pipes & BIT(pipe)) == 0)
7153                         continue;
7154
7155                 modeset_pipes &= ~BIT(pipe);
7156
7157                 intel_enable_crtc(state, crtc);
7158         }
7159
7160         /*
7161          * Finally we do the plane updates/etc. for all pipes that got enabled.
7162          */
7163         for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
7164                 enum pipe pipe = crtc->pipe;
7165
7166                 if ((update_pipes & BIT(pipe)) == 0)
7167                         continue;
7168
7169                 drm_WARN_ON(&dev_priv->drm, skl_ddb_allocation_overlaps(&new_crtc_state->wm.skl.ddb,
7170                                                                         entries, I915_MAX_PIPES, pipe));
7171
7172                 entries[pipe] = new_crtc_state->wm.skl.ddb;
7173                 update_pipes &= ~BIT(pipe);
7174
7175                 intel_update_crtc(state, crtc);
7176         }
7177
7178         drm_WARN_ON(&dev_priv->drm, modeset_pipes);
7179         drm_WARN_ON(&dev_priv->drm, update_pipes);
7180 }
7181
7182 static void intel_atomic_helper_free_state(struct drm_i915_private *dev_priv)
7183 {
7184         struct intel_atomic_state *state, *next;
7185         struct llist_node *freed;
7186
7187         freed = llist_del_all(&dev_priv->display.atomic_helper.free_list);
7188         llist_for_each_entry_safe(state, next, freed, freed)
7189                 drm_atomic_state_put(&state->base);
7190 }
7191
7192 static void intel_atomic_helper_free_state_worker(struct work_struct *work)
7193 {
7194         struct drm_i915_private *dev_priv =
7195                 container_of(work, typeof(*dev_priv), display.atomic_helper.free_work);
7196
7197         intel_atomic_helper_free_state(dev_priv);
7198 }
7199
7200 static void intel_atomic_commit_fence_wait(struct intel_atomic_state *intel_state)
7201 {
7202         struct wait_queue_entry wait_fence, wait_reset;
7203         struct drm_i915_private *dev_priv = to_i915(intel_state->base.dev);
7204
7205         init_wait_entry(&wait_fence, 0);
7206         init_wait_entry(&wait_reset, 0);
7207         for (;;) {
7208                 prepare_to_wait(&intel_state->commit_ready.wait,
7209                                 &wait_fence, TASK_UNINTERRUPTIBLE);
7210                 prepare_to_wait(bit_waitqueue(&to_gt(dev_priv)->reset.flags,
7211                                               I915_RESET_MODESET),
7212                                 &wait_reset, TASK_UNINTERRUPTIBLE);
7213
7214
7215                 if (i915_sw_fence_done(&intel_state->commit_ready) ||
7216                     test_bit(I915_RESET_MODESET, &to_gt(dev_priv)->reset.flags))
7217                         break;
7218
7219                 schedule();
7220         }
7221         finish_wait(&intel_state->commit_ready.wait, &wait_fence);
7222         finish_wait(bit_waitqueue(&to_gt(dev_priv)->reset.flags,
7223                                   I915_RESET_MODESET),
7224                     &wait_reset);
7225 }
7226
7227 static void intel_atomic_cleanup_work(struct work_struct *work)
7228 {
7229         struct intel_atomic_state *state =
7230                 container_of(work, struct intel_atomic_state, base.commit_work);
7231         struct drm_i915_private *i915 = to_i915(state->base.dev);
7232         struct intel_crtc_state *old_crtc_state;
7233         struct intel_crtc *crtc;
7234         int i;
7235
7236         for_each_old_intel_crtc_in_state(state, crtc, old_crtc_state, i)
7237                 intel_color_cleanup_commit(old_crtc_state);
7238
7239         drm_atomic_helper_cleanup_planes(&i915->drm, &state->base);
7240         drm_atomic_helper_commit_cleanup_done(&state->base);
7241         drm_atomic_state_put(&state->base);
7242
7243         intel_atomic_helper_free_state(i915);
7244 }
7245
7246 static void intel_atomic_prepare_plane_clear_colors(struct intel_atomic_state *state)
7247 {
7248         struct drm_i915_private *i915 = to_i915(state->base.dev);
7249         struct intel_plane *plane;
7250         struct intel_plane_state *plane_state;
7251         int i;
7252
7253         for_each_new_intel_plane_in_state(state, plane, plane_state, i) {
7254                 struct drm_framebuffer *fb = plane_state->hw.fb;
7255                 int cc_plane;
7256                 int ret;
7257
7258                 if (!fb)
7259                         continue;
7260
7261                 cc_plane = intel_fb_rc_ccs_cc_plane(fb);
7262                 if (cc_plane < 0)
7263                         continue;
7264
7265                 /*
7266                  * The layout of the fast clear color value expected by HW
7267                  * (the DRM ABI requiring this value to be located in fb at
7268                  * offset 0 of cc plane, plane #2 previous generations or
7269                  * plane #1 for flat ccs):
7270                  * - 4 x 4 bytes per-channel value
7271                  *   (in surface type specific float/int format provided by the fb user)
7272                  * - 8 bytes native color value used by the display
7273                  *   (converted/written by GPU during a fast clear operation using the
7274                  *    above per-channel values)
7275                  *
7276                  * The commit's FB prepare hook already ensured that FB obj is pinned and the
7277                  * caller made sure that the object is synced wrt. the related color clear value
7278                  * GPU write on it.
7279                  */
7280                 ret = i915_gem_object_read_from_page(intel_fb_obj(fb),
7281                                                      fb->offsets[cc_plane] + 16,
7282                                                      &plane_state->ccval,
7283                                                      sizeof(plane_state->ccval));
7284                 /* The above could only fail if the FB obj has an unexpected backing store type. */
7285                 drm_WARN_ON(&i915->drm, ret);
7286         }
7287 }
7288
7289 static void intel_atomic_commit_tail(struct intel_atomic_state *state)
7290 {
7291         struct drm_device *dev = state->base.dev;
7292         struct drm_i915_private *dev_priv = to_i915(dev);
7293         struct intel_crtc_state *new_crtc_state, *old_crtc_state;
7294         struct intel_crtc *crtc;
7295         struct intel_power_domain_mask put_domains[I915_MAX_PIPES] = {};
7296         intel_wakeref_t wakeref = 0;
7297         int i;
7298
7299         intel_atomic_commit_fence_wait(state);
7300
7301         drm_atomic_helper_wait_for_dependencies(&state->base);
7302         drm_dp_mst_atomic_wait_for_dependencies(&state->base);
7303
7304         /*
7305          * During full modesets we write a lot of registers, wait
7306          * for PLLs, etc. Doing that while DC states are enabled
7307          * is not a good idea.
7308          *
7309          * During fastsets and other updates we also need to
7310          * disable DC states due to the following scenario:
7311          * 1. DC5 exit and PSR exit happen
7312          * 2. Some or all _noarm() registers are written
7313          * 3. Due to some long delay PSR is re-entered
7314          * 4. DC5 entry -> DMC saves the already written new
7315          *    _noarm() registers and the old not yet written
7316          *    _arm() registers
7317          * 5. DC5 exit -> DMC restores a mixture of old and
7318          *    new register values and arms the update
7319          * 6. PSR exit -> hardware latches a mixture of old and
7320          *    new register values -> corrupted frame, or worse
7321          * 7. New _arm() registers are finally written
7322          * 8. Hardware finally latches a complete set of new
7323          *    register values, and subsequent frames will be OK again
7324          */
7325         wakeref = intel_display_power_get(dev_priv, POWER_DOMAIN_DC_OFF);
7326
7327         intel_atomic_prepare_plane_clear_colors(state);
7328
7329         for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
7330                                             new_crtc_state, i) {
7331                 if (intel_crtc_needs_modeset(new_crtc_state) ||
7332                     intel_crtc_needs_fastset(new_crtc_state))
7333                         intel_modeset_get_crtc_power_domains(new_crtc_state, &put_domains[crtc->pipe]);
7334         }
7335
7336         intel_commit_modeset_disables(state);
7337
7338         /* FIXME: Eventually get rid of our crtc->config pointer */
7339         for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i)
7340                 crtc->config = new_crtc_state;
7341
7342         if (state->modeset) {
7343                 drm_atomic_helper_update_legacy_modeset_state(dev, &state->base);
7344
7345                 intel_set_cdclk_pre_plane_update(state);
7346
7347                 intel_modeset_verify_disabled(dev_priv, state);
7348         }
7349
7350         intel_sagv_pre_plane_update(state);
7351
7352         /* Complete the events for pipes that have now been disabled */
7353         for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
7354                 bool modeset = intel_crtc_needs_modeset(new_crtc_state);
7355
7356                 /* Complete events for now disable pipes here. */
7357                 if (modeset && !new_crtc_state->hw.active && new_crtc_state->uapi.event) {
7358                         spin_lock_irq(&dev->event_lock);
7359                         drm_crtc_send_vblank_event(&crtc->base,
7360                                                    new_crtc_state->uapi.event);
7361                         spin_unlock_irq(&dev->event_lock);
7362
7363                         new_crtc_state->uapi.event = NULL;
7364                 }
7365         }
7366
7367         intel_encoders_update_prepare(state);
7368
7369         intel_dbuf_pre_plane_update(state);
7370         intel_mbus_dbox_update(state);
7371
7372         for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
7373                 if (new_crtc_state->do_async_flip)
7374                         intel_crtc_enable_flip_done(state, crtc);
7375         }
7376
7377         /* Now enable the clocks, plane, pipe, and connectors that we set up. */
7378         dev_priv->display.funcs.display->commit_modeset_enables(state);
7379
7380         if (state->modeset)
7381                 intel_set_cdclk_post_plane_update(state);
7382
7383         intel_wait_for_vblank_workers(state);
7384
7385         /* FIXME: We should call drm_atomic_helper_commit_hw_done() here
7386          * already, but still need the state for the delayed optimization. To
7387          * fix this:
7388          * - wrap the optimization/post_plane_update stuff into a per-crtc work.
7389          * - schedule that vblank worker _before_ calling hw_done
7390          * - at the start of commit_tail, cancel it _synchrously
7391          * - switch over to the vblank wait helper in the core after that since
7392          *   we don't need out special handling any more.
7393          */
7394         drm_atomic_helper_wait_for_flip_done(dev, &state->base);
7395
7396         for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
7397                 if (new_crtc_state->do_async_flip)
7398                         intel_crtc_disable_flip_done(state, crtc);
7399         }
7400
7401         /*
7402          * Now that the vblank has passed, we can go ahead and program the
7403          * optimal watermarks on platforms that need two-step watermark
7404          * programming.
7405          *
7406          * TODO: Move this (and other cleanup) to an async worker eventually.
7407          */
7408         for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
7409                                             new_crtc_state, i) {
7410                 /*
7411                  * Gen2 reports pipe underruns whenever all planes are disabled.
7412                  * So re-enable underrun reporting after some planes get enabled.
7413                  *
7414                  * We do this before .optimize_watermarks() so that we have a
7415                  * chance of catching underruns with the intermediate watermarks
7416                  * vs. the new plane configuration.
7417                  */
7418                 if (DISPLAY_VER(dev_priv) == 2 && planes_enabling(old_crtc_state, new_crtc_state))
7419                         intel_set_cpu_fifo_underrun_reporting(dev_priv, crtc->pipe, true);
7420
7421                 intel_optimize_watermarks(state, crtc);
7422         }
7423
7424         intel_dbuf_post_plane_update(state);
7425         intel_psr_post_plane_update(state);
7426
7427         for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
7428                 intel_post_plane_update(state, crtc);
7429
7430                 intel_modeset_put_crtc_power_domains(crtc, &put_domains[crtc->pipe]);
7431
7432                 intel_modeset_verify_crtc(crtc, state, old_crtc_state, new_crtc_state);
7433
7434                 /* Must be done after gamma readout due to HSW split gamma vs. IPS w/a */
7435                 hsw_ips_post_update(state, crtc);
7436
7437                 /*
7438                  * Activate DRRS after state readout to avoid
7439                  * dp_m_n vs. dp_m2_n2 confusion on BDW+.
7440                  */
7441                 intel_drrs_activate(new_crtc_state);
7442
7443                 /*
7444                  * DSB cleanup is done in cleanup_work aligning with framebuffer
7445                  * cleanup. So copy and reset the dsb structure to sync with
7446                  * commit_done and later do dsb cleanup in cleanup_work.
7447                  *
7448                  * FIXME get rid of this funny new->old swapping
7449                  */
7450                 old_crtc_state->dsb = fetch_and_zero(&new_crtc_state->dsb);
7451         }
7452
7453         /* Underruns don't always raise interrupts, so check manually */
7454         intel_check_cpu_fifo_underruns(dev_priv);
7455         intel_check_pch_fifo_underruns(dev_priv);
7456
7457         if (state->modeset)
7458                 intel_verify_planes(state);
7459
7460         intel_sagv_post_plane_update(state);
7461
7462         drm_atomic_helper_commit_hw_done(&state->base);
7463
7464         if (state->modeset) {
7465                 /* As one of the primary mmio accessors, KMS has a high
7466                  * likelihood of triggering bugs in unclaimed access. After we
7467                  * finish modesetting, see if an error has been flagged, and if
7468                  * so enable debugging for the next modeset - and hope we catch
7469                  * the culprit.
7470                  */
7471                 intel_uncore_arm_unclaimed_mmio_detection(&dev_priv->uncore);
7472         }
7473         intel_display_power_put(dev_priv, POWER_DOMAIN_DC_OFF, wakeref);
7474         intel_runtime_pm_put(&dev_priv->runtime_pm, state->wakeref);
7475
7476         /*
7477          * Defer the cleanup of the old state to a separate worker to not
7478          * impede the current task (userspace for blocking modesets) that
7479          * are executed inline. For out-of-line asynchronous modesets/flips,
7480          * deferring to a new worker seems overkill, but we would place a
7481          * schedule point (cond_resched()) here anyway to keep latencies
7482          * down.
7483          */
7484         INIT_WORK(&state->base.commit_work, intel_atomic_cleanup_work);
7485         queue_work(system_highpri_wq, &state->base.commit_work);
7486 }
7487
7488 static void intel_atomic_commit_work(struct work_struct *work)
7489 {
7490         struct intel_atomic_state *state =
7491                 container_of(work, struct intel_atomic_state, base.commit_work);
7492
7493         intel_atomic_commit_tail(state);
7494 }
7495
7496 static int
7497 intel_atomic_commit_ready(struct i915_sw_fence *fence,
7498                           enum i915_sw_fence_notify notify)
7499 {
7500         struct intel_atomic_state *state =
7501                 container_of(fence, struct intel_atomic_state, commit_ready);
7502
7503         switch (notify) {
7504         case FENCE_COMPLETE:
7505                 /* we do blocking waits in the worker, nothing to do here */
7506                 break;
7507         case FENCE_FREE:
7508                 {
7509                         struct intel_atomic_helper *helper =
7510                                 &to_i915(state->base.dev)->display.atomic_helper;
7511
7512                         if (llist_add(&state->freed, &helper->free_list))
7513                                 schedule_work(&helper->free_work);
7514                         break;
7515                 }
7516         }
7517
7518         return NOTIFY_DONE;
7519 }
7520
7521 static void intel_atomic_track_fbs(struct intel_atomic_state *state)
7522 {
7523         struct intel_plane_state *old_plane_state, *new_plane_state;
7524         struct intel_plane *plane;
7525         int i;
7526
7527         for_each_oldnew_intel_plane_in_state(state, plane, old_plane_state,
7528                                              new_plane_state, i)
7529                 intel_frontbuffer_track(to_intel_frontbuffer(old_plane_state->hw.fb),
7530                                         to_intel_frontbuffer(new_plane_state->hw.fb),
7531                                         plane->frontbuffer_bit);
7532 }
7533
7534 static int intel_atomic_commit(struct drm_device *dev,
7535                                struct drm_atomic_state *_state,
7536                                bool nonblock)
7537 {
7538         struct intel_atomic_state *state = to_intel_atomic_state(_state);
7539         struct drm_i915_private *dev_priv = to_i915(dev);
7540         int ret = 0;
7541
7542         state->wakeref = intel_runtime_pm_get(&dev_priv->runtime_pm);
7543
7544         drm_atomic_state_get(&state->base);
7545         i915_sw_fence_init(&state->commit_ready,
7546                            intel_atomic_commit_ready);
7547
7548         /*
7549          * The intel_legacy_cursor_update() fast path takes care
7550          * of avoiding the vblank waits for simple cursor
7551          * movement and flips. For cursor on/off and size changes,
7552          * we want to perform the vblank waits so that watermark
7553          * updates happen during the correct frames. Gen9+ have
7554          * double buffered watermarks and so shouldn't need this.
7555          *
7556          * Unset state->legacy_cursor_update before the call to
7557          * drm_atomic_helper_setup_commit() because otherwise
7558          * drm_atomic_helper_wait_for_flip_done() is a noop and
7559          * we get FIFO underruns because we didn't wait
7560          * for vblank.
7561          *
7562          * FIXME doing watermarks and fb cleanup from a vblank worker
7563          * (assuming we had any) would solve these problems.
7564          */
7565         if (DISPLAY_VER(dev_priv) < 9 && state->base.legacy_cursor_update) {
7566                 struct intel_crtc_state *new_crtc_state;
7567                 struct intel_crtc *crtc;
7568                 int i;
7569
7570                 for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i)
7571                         if (new_crtc_state->wm.need_postvbl_update ||
7572                             new_crtc_state->update_wm_post)
7573                                 state->base.legacy_cursor_update = false;
7574         }
7575
7576         ret = intel_atomic_prepare_commit(state);
7577         if (ret) {
7578                 drm_dbg_atomic(&dev_priv->drm,
7579                                "Preparing state failed with %i\n", ret);
7580                 i915_sw_fence_commit(&state->commit_ready);
7581                 intel_runtime_pm_put(&dev_priv->runtime_pm, state->wakeref);
7582                 return ret;
7583         }
7584
7585         ret = drm_atomic_helper_setup_commit(&state->base, nonblock);
7586         if (!ret)
7587                 ret = drm_atomic_helper_swap_state(&state->base, true);
7588         if (!ret)
7589                 intel_atomic_swap_global_state(state);
7590
7591         if (ret) {
7592                 struct intel_crtc_state *new_crtc_state;
7593                 struct intel_crtc *crtc;
7594                 int i;
7595
7596                 i915_sw_fence_commit(&state->commit_ready);
7597
7598                 for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i)
7599                         intel_color_cleanup_commit(new_crtc_state);
7600
7601                 drm_atomic_helper_cleanup_planes(dev, &state->base);
7602                 intel_runtime_pm_put(&dev_priv->runtime_pm, state->wakeref);
7603                 return ret;
7604         }
7605         intel_shared_dpll_swap_state(state);
7606         intel_atomic_track_fbs(state);
7607
7608         drm_atomic_state_get(&state->base);
7609         INIT_WORK(&state->base.commit_work, intel_atomic_commit_work);
7610
7611         i915_sw_fence_commit(&state->commit_ready);
7612         if (nonblock && state->modeset) {
7613                 queue_work(dev_priv->display.wq.modeset, &state->base.commit_work);
7614         } else if (nonblock) {
7615                 queue_work(dev_priv->display.wq.flip, &state->base.commit_work);
7616         } else {
7617                 if (state->modeset)
7618                         flush_workqueue(dev_priv->display.wq.modeset);
7619                 intel_atomic_commit_tail(state);
7620         }
7621
7622         return 0;
7623 }
7624
7625 /**
7626  * intel_plane_destroy - destroy a plane
7627  * @plane: plane to destroy
7628  *
7629  * Common destruction function for all types of planes (primary, cursor,
7630  * sprite).
7631  */
7632 void intel_plane_destroy(struct drm_plane *plane)
7633 {
7634         drm_plane_cleanup(plane);
7635         kfree(to_intel_plane(plane));
7636 }
7637
7638 static void intel_plane_possible_crtcs_init(struct drm_i915_private *dev_priv)
7639 {
7640         struct intel_plane *plane;
7641
7642         for_each_intel_plane(&dev_priv->drm, plane) {
7643                 struct intel_crtc *crtc = intel_crtc_for_pipe(dev_priv,
7644                                                               plane->pipe);
7645
7646                 plane->base.possible_crtcs = drm_crtc_mask(&crtc->base);
7647         }
7648 }
7649
7650
7651 int intel_get_pipe_from_crtc_id_ioctl(struct drm_device *dev, void *data,
7652                                       struct drm_file *file)
7653 {
7654         struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
7655         struct drm_crtc *drmmode_crtc;
7656         struct intel_crtc *crtc;
7657
7658         drmmode_crtc = drm_crtc_find(dev, file, pipe_from_crtc_id->crtc_id);
7659         if (!drmmode_crtc)
7660                 return -ENOENT;
7661
7662         crtc = to_intel_crtc(drmmode_crtc);
7663         pipe_from_crtc_id->pipe = crtc->pipe;
7664
7665         return 0;
7666 }
7667
7668 static u32 intel_encoder_possible_clones(struct intel_encoder *encoder)
7669 {
7670         struct drm_device *dev = encoder->base.dev;
7671         struct intel_encoder *source_encoder;
7672         u32 possible_clones = 0;
7673
7674         for_each_intel_encoder(dev, source_encoder) {
7675                 if (encoders_cloneable(encoder, source_encoder))
7676                         possible_clones |= drm_encoder_mask(&source_encoder->base);
7677         }
7678
7679         return possible_clones;
7680 }
7681
7682 static u32 intel_encoder_possible_crtcs(struct intel_encoder *encoder)
7683 {
7684         struct drm_device *dev = encoder->base.dev;
7685         struct intel_crtc *crtc;
7686         u32 possible_crtcs = 0;
7687
7688         for_each_intel_crtc_in_pipe_mask(dev, crtc, encoder->pipe_mask)
7689                 possible_crtcs |= drm_crtc_mask(&crtc->base);
7690
7691         return possible_crtcs;
7692 }
7693
7694 static bool ilk_has_edp_a(struct drm_i915_private *dev_priv)
7695 {
7696         if (!IS_MOBILE(dev_priv))
7697                 return false;
7698
7699         if ((intel_de_read(dev_priv, DP_A) & DP_DETECTED) == 0)
7700                 return false;
7701
7702         if (IS_IRONLAKE(dev_priv) && (intel_de_read(dev_priv, FUSE_STRAP) & ILK_eDP_A_DISABLE))
7703                 return false;
7704
7705         return true;
7706 }
7707
7708 static bool intel_ddi_crt_present(struct drm_i915_private *dev_priv)
7709 {
7710         if (DISPLAY_VER(dev_priv) >= 9)
7711                 return false;
7712
7713         if (IS_HSW_ULT(dev_priv) || IS_BDW_ULT(dev_priv))
7714                 return false;
7715
7716         if (HAS_PCH_LPT_H(dev_priv) &&
7717             intel_de_read(dev_priv, SFUSE_STRAP) & SFUSE_STRAP_CRT_DISABLED)
7718                 return false;
7719
7720         /* DDI E can't be used if DDI A requires 4 lanes */
7721         if (intel_de_read(dev_priv, DDI_BUF_CTL(PORT_A)) & DDI_A_4_LANES)
7722                 return false;
7723
7724         if (!dev_priv->display.vbt.int_crt_support)
7725                 return false;
7726
7727         return true;
7728 }
7729
7730 static void intel_setup_outputs(struct drm_i915_private *dev_priv)
7731 {
7732         struct intel_encoder *encoder;
7733         bool dpd_is_edp = false;
7734
7735         intel_pps_unlock_regs_wa(dev_priv);
7736
7737         if (!HAS_DISPLAY(dev_priv))
7738                 return;
7739
7740         if (IS_DG2(dev_priv)) {
7741                 intel_ddi_init(dev_priv, PORT_A);
7742                 intel_ddi_init(dev_priv, PORT_B);
7743                 intel_ddi_init(dev_priv, PORT_C);
7744                 intel_ddi_init(dev_priv, PORT_D_XELPD);
7745                 intel_ddi_init(dev_priv, PORT_TC1);
7746         } else if (IS_ALDERLAKE_P(dev_priv)) {
7747                 intel_ddi_init(dev_priv, PORT_A);
7748                 intel_ddi_init(dev_priv, PORT_B);
7749                 intel_ddi_init(dev_priv, PORT_TC1);
7750                 intel_ddi_init(dev_priv, PORT_TC2);
7751                 intel_ddi_init(dev_priv, PORT_TC3);
7752                 intel_ddi_init(dev_priv, PORT_TC4);
7753                 icl_dsi_init(dev_priv);
7754         } else if (IS_ALDERLAKE_S(dev_priv)) {
7755                 intel_ddi_init(dev_priv, PORT_A);
7756                 intel_ddi_init(dev_priv, PORT_TC1);
7757                 intel_ddi_init(dev_priv, PORT_TC2);
7758                 intel_ddi_init(dev_priv, PORT_TC3);
7759                 intel_ddi_init(dev_priv, PORT_TC4);
7760         } else if (IS_DG1(dev_priv) || IS_ROCKETLAKE(dev_priv)) {
7761                 intel_ddi_init(dev_priv, PORT_A);
7762                 intel_ddi_init(dev_priv, PORT_B);
7763                 intel_ddi_init(dev_priv, PORT_TC1);
7764                 intel_ddi_init(dev_priv, PORT_TC2);
7765         } else if (DISPLAY_VER(dev_priv) >= 12) {
7766                 intel_ddi_init(dev_priv, PORT_A);
7767                 intel_ddi_init(dev_priv, PORT_B);
7768                 intel_ddi_init(dev_priv, PORT_TC1);
7769                 intel_ddi_init(dev_priv, PORT_TC2);
7770                 intel_ddi_init(dev_priv, PORT_TC3);
7771                 intel_ddi_init(dev_priv, PORT_TC4);
7772                 intel_ddi_init(dev_priv, PORT_TC5);
7773                 intel_ddi_init(dev_priv, PORT_TC6);
7774                 icl_dsi_init(dev_priv);
7775         } else if (IS_JSL_EHL(dev_priv)) {
7776                 intel_ddi_init(dev_priv, PORT_A);
7777                 intel_ddi_init(dev_priv, PORT_B);
7778                 intel_ddi_init(dev_priv, PORT_C);
7779                 intel_ddi_init(dev_priv, PORT_D);
7780                 icl_dsi_init(dev_priv);
7781         } else if (DISPLAY_VER(dev_priv) == 11) {
7782                 intel_ddi_init(dev_priv, PORT_A);
7783                 intel_ddi_init(dev_priv, PORT_B);
7784                 intel_ddi_init(dev_priv, PORT_C);
7785                 intel_ddi_init(dev_priv, PORT_D);
7786                 intel_ddi_init(dev_priv, PORT_E);
7787                 intel_ddi_init(dev_priv, PORT_F);
7788                 icl_dsi_init(dev_priv);
7789         } else if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) {
7790                 intel_ddi_init(dev_priv, PORT_A);
7791                 intel_ddi_init(dev_priv, PORT_B);
7792                 intel_ddi_init(dev_priv, PORT_C);
7793                 vlv_dsi_init(dev_priv);
7794         } else if (DISPLAY_VER(dev_priv) >= 9) {
7795                 intel_ddi_init(dev_priv, PORT_A);
7796                 intel_ddi_init(dev_priv, PORT_B);
7797                 intel_ddi_init(dev_priv, PORT_C);
7798                 intel_ddi_init(dev_priv, PORT_D);
7799                 intel_ddi_init(dev_priv, PORT_E);
7800         } else if (HAS_DDI(dev_priv)) {
7801                 u32 found;
7802
7803                 if (intel_ddi_crt_present(dev_priv))
7804                         intel_crt_init(dev_priv);
7805
7806                 /* Haswell uses DDI functions to detect digital outputs. */
7807                 found = intel_de_read(dev_priv, DDI_BUF_CTL(PORT_A)) & DDI_INIT_DISPLAY_DETECTED;
7808                 if (found)
7809                         intel_ddi_init(dev_priv, PORT_A);
7810
7811                 found = intel_de_read(dev_priv, SFUSE_STRAP);
7812                 if (found & SFUSE_STRAP_DDIB_DETECTED)
7813                         intel_ddi_init(dev_priv, PORT_B);
7814                 if (found & SFUSE_STRAP_DDIC_DETECTED)
7815                         intel_ddi_init(dev_priv, PORT_C);
7816                 if (found & SFUSE_STRAP_DDID_DETECTED)
7817                         intel_ddi_init(dev_priv, PORT_D);
7818                 if (found & SFUSE_STRAP_DDIF_DETECTED)
7819                         intel_ddi_init(dev_priv, PORT_F);
7820         } else if (HAS_PCH_SPLIT(dev_priv)) {
7821                 int found;
7822
7823                 /*
7824                  * intel_edp_init_connector() depends on this completing first,
7825                  * to prevent the registration of both eDP and LVDS and the
7826                  * incorrect sharing of the PPS.
7827                  */
7828                 intel_lvds_init(dev_priv);
7829                 intel_crt_init(dev_priv);
7830
7831                 dpd_is_edp = intel_dp_is_port_edp(dev_priv, PORT_D);
7832
7833                 if (ilk_has_edp_a(dev_priv))
7834                         g4x_dp_init(dev_priv, DP_A, PORT_A);
7835
7836                 if (intel_de_read(dev_priv, PCH_HDMIB) & SDVO_DETECTED) {
7837                         /* PCH SDVOB multiplex with HDMIB */
7838                         found = intel_sdvo_init(dev_priv, PCH_SDVOB, PORT_B);
7839                         if (!found)
7840                                 g4x_hdmi_init(dev_priv, PCH_HDMIB, PORT_B);
7841                         if (!found && (intel_de_read(dev_priv, PCH_DP_B) & DP_DETECTED))
7842                                 g4x_dp_init(dev_priv, PCH_DP_B, PORT_B);
7843                 }
7844
7845                 if (intel_de_read(dev_priv, PCH_HDMIC) & SDVO_DETECTED)
7846                         g4x_hdmi_init(dev_priv, PCH_HDMIC, PORT_C);
7847
7848                 if (!dpd_is_edp && intel_de_read(dev_priv, PCH_HDMID) & SDVO_DETECTED)
7849                         g4x_hdmi_init(dev_priv, PCH_HDMID, PORT_D);
7850
7851                 if (intel_de_read(dev_priv, PCH_DP_C) & DP_DETECTED)
7852                         g4x_dp_init(dev_priv, PCH_DP_C, PORT_C);
7853
7854                 if (intel_de_read(dev_priv, PCH_DP_D) & DP_DETECTED)
7855                         g4x_dp_init(dev_priv, PCH_DP_D, PORT_D);
7856         } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
7857                 bool has_edp, has_port;
7858
7859                 if (IS_VALLEYVIEW(dev_priv) && dev_priv->display.vbt.int_crt_support)
7860                         intel_crt_init(dev_priv);
7861
7862                 /*
7863                  * The DP_DETECTED bit is the latched state of the DDC
7864                  * SDA pin at boot. However since eDP doesn't require DDC
7865                  * (no way to plug in a DP->HDMI dongle) the DDC pins for
7866                  * eDP ports may have been muxed to an alternate function.
7867                  * Thus we can't rely on the DP_DETECTED bit alone to detect
7868                  * eDP ports. Consult the VBT as well as DP_DETECTED to
7869                  * detect eDP ports.
7870                  *
7871                  * Sadly the straps seem to be missing sometimes even for HDMI
7872                  * ports (eg. on Voyo V3 - CHT x7-Z8700), so check both strap
7873                  * and VBT for the presence of the port. Additionally we can't
7874                  * trust the port type the VBT declares as we've seen at least
7875                  * HDMI ports that the VBT claim are DP or eDP.
7876                  */
7877                 has_edp = intel_dp_is_port_edp(dev_priv, PORT_B);
7878                 has_port = intel_bios_is_port_present(dev_priv, PORT_B);
7879                 if (intel_de_read(dev_priv, VLV_DP_B) & DP_DETECTED || has_port)
7880                         has_edp &= g4x_dp_init(dev_priv, VLV_DP_B, PORT_B);
7881                 if ((intel_de_read(dev_priv, VLV_HDMIB) & SDVO_DETECTED || has_port) && !has_edp)
7882                         g4x_hdmi_init(dev_priv, VLV_HDMIB, PORT_B);
7883
7884                 has_edp = intel_dp_is_port_edp(dev_priv, PORT_C);
7885                 has_port = intel_bios_is_port_present(dev_priv, PORT_C);
7886                 if (intel_de_read(dev_priv, VLV_DP_C) & DP_DETECTED || has_port)
7887                         has_edp &= g4x_dp_init(dev_priv, VLV_DP_C, PORT_C);
7888                 if ((intel_de_read(dev_priv, VLV_HDMIC) & SDVO_DETECTED || has_port) && !has_edp)
7889                         g4x_hdmi_init(dev_priv, VLV_HDMIC, PORT_C);
7890
7891                 if (IS_CHERRYVIEW(dev_priv)) {
7892                         /*
7893                          * eDP not supported on port D,
7894                          * so no need to worry about it
7895                          */
7896                         has_port = intel_bios_is_port_present(dev_priv, PORT_D);
7897                         if (intel_de_read(dev_priv, CHV_DP_D) & DP_DETECTED || has_port)
7898                                 g4x_dp_init(dev_priv, CHV_DP_D, PORT_D);
7899                         if (intel_de_read(dev_priv, CHV_HDMID) & SDVO_DETECTED || has_port)
7900                                 g4x_hdmi_init(dev_priv, CHV_HDMID, PORT_D);
7901                 }
7902
7903                 vlv_dsi_init(dev_priv);
7904         } else if (IS_PINEVIEW(dev_priv)) {
7905                 intel_lvds_init(dev_priv);
7906                 intel_crt_init(dev_priv);
7907         } else if (IS_DISPLAY_VER(dev_priv, 3, 4)) {
7908                 bool found = false;
7909
7910                 if (IS_MOBILE(dev_priv))
7911                         intel_lvds_init(dev_priv);
7912
7913                 intel_crt_init(dev_priv);
7914
7915                 if (intel_de_read(dev_priv, GEN3_SDVOB) & SDVO_DETECTED) {
7916                         drm_dbg_kms(&dev_priv->drm, "probing SDVOB\n");
7917                         found = intel_sdvo_init(dev_priv, GEN3_SDVOB, PORT_B);
7918                         if (!found && IS_G4X(dev_priv)) {
7919                                 drm_dbg_kms(&dev_priv->drm,
7920                                             "probing HDMI on SDVOB\n");
7921                                 g4x_hdmi_init(dev_priv, GEN4_HDMIB, PORT_B);
7922                         }
7923
7924                         if (!found && IS_G4X(dev_priv))
7925                                 g4x_dp_init(dev_priv, DP_B, PORT_B);
7926                 }
7927
7928                 /* Before G4X SDVOC doesn't have its own detect register */
7929
7930                 if (intel_de_read(dev_priv, GEN3_SDVOB) & SDVO_DETECTED) {
7931                         drm_dbg_kms(&dev_priv->drm, "probing SDVOC\n");
7932                         found = intel_sdvo_init(dev_priv, GEN3_SDVOC, PORT_C);
7933                 }
7934
7935                 if (!found && (intel_de_read(dev_priv, GEN3_SDVOC) & SDVO_DETECTED)) {
7936
7937                         if (IS_G4X(dev_priv)) {
7938                                 drm_dbg_kms(&dev_priv->drm,
7939                                             "probing HDMI on SDVOC\n");
7940                                 g4x_hdmi_init(dev_priv, GEN4_HDMIC, PORT_C);
7941                         }
7942                         if (IS_G4X(dev_priv))
7943                                 g4x_dp_init(dev_priv, DP_C, PORT_C);
7944                 }
7945
7946                 if (IS_G4X(dev_priv) && (intel_de_read(dev_priv, DP_D) & DP_DETECTED))
7947                         g4x_dp_init(dev_priv, DP_D, PORT_D);
7948
7949                 if (SUPPORTS_TV(dev_priv))
7950                         intel_tv_init(dev_priv);
7951         } else if (DISPLAY_VER(dev_priv) == 2) {
7952                 if (IS_I85X(dev_priv))
7953                         intel_lvds_init(dev_priv);
7954
7955                 intel_crt_init(dev_priv);
7956                 intel_dvo_init(dev_priv);
7957         }
7958
7959         for_each_intel_encoder(&dev_priv->drm, encoder) {
7960                 encoder->base.possible_crtcs =
7961                         intel_encoder_possible_crtcs(encoder);
7962                 encoder->base.possible_clones =
7963                         intel_encoder_possible_clones(encoder);
7964         }
7965
7966         intel_init_pch_refclk(dev_priv);
7967
7968         drm_helper_move_panel_connectors_to_head(&dev_priv->drm);
7969 }
7970
7971 static int max_dotclock(struct drm_i915_private *i915)
7972 {
7973         int max_dotclock = i915->max_dotclk_freq;
7974
7975         /* icl+ might use bigjoiner */
7976         if (DISPLAY_VER(i915) >= 11)
7977                 max_dotclock *= 2;
7978
7979         return max_dotclock;
7980 }
7981
7982 static enum drm_mode_status
7983 intel_mode_valid(struct drm_device *dev,
7984                  const struct drm_display_mode *mode)
7985 {
7986         struct drm_i915_private *dev_priv = to_i915(dev);
7987         int hdisplay_max, htotal_max;
7988         int vdisplay_max, vtotal_max;
7989
7990         /*
7991          * Can't reject DBLSCAN here because Xorg ddxen can add piles
7992          * of DBLSCAN modes to the output's mode list when they detect
7993          * the scaling mode property on the connector. And they don't
7994          * ask the kernel to validate those modes in any way until
7995          * modeset time at which point the client gets a protocol error.
7996          * So in order to not upset those clients we silently ignore the
7997          * DBLSCAN flag on such connectors. For other connectors we will
7998          * reject modes with the DBLSCAN flag in encoder->compute_config().
7999          * And we always reject DBLSCAN modes in connector->mode_valid()
8000          * as we never want such modes on the connector's mode list.
8001          */
8002
8003         if (mode->vscan > 1)
8004                 return MODE_NO_VSCAN;
8005
8006         if (mode->flags & DRM_MODE_FLAG_HSKEW)
8007                 return MODE_H_ILLEGAL;
8008
8009         if (mode->flags & (DRM_MODE_FLAG_CSYNC |
8010                            DRM_MODE_FLAG_NCSYNC |
8011                            DRM_MODE_FLAG_PCSYNC))
8012                 return MODE_HSYNC;
8013
8014         if (mode->flags & (DRM_MODE_FLAG_BCAST |
8015                            DRM_MODE_FLAG_PIXMUX |
8016                            DRM_MODE_FLAG_CLKDIV2))
8017                 return MODE_BAD;
8018
8019         /*
8020          * Reject clearly excessive dotclocks early to
8021          * avoid having to worry about huge integers later.
8022          */
8023         if (mode->clock > max_dotclock(dev_priv))
8024                 return MODE_CLOCK_HIGH;
8025
8026         /* Transcoder timing limits */
8027         if (DISPLAY_VER(dev_priv) >= 11) {
8028                 hdisplay_max = 16384;
8029                 vdisplay_max = 8192;
8030                 htotal_max = 16384;
8031                 vtotal_max = 8192;
8032         } else if (DISPLAY_VER(dev_priv) >= 9 ||
8033                    IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv)) {
8034                 hdisplay_max = 8192; /* FDI max 4096 handled elsewhere */
8035                 vdisplay_max = 4096;
8036                 htotal_max = 8192;
8037                 vtotal_max = 8192;
8038         } else if (DISPLAY_VER(dev_priv) >= 3) {
8039                 hdisplay_max = 4096;
8040                 vdisplay_max = 4096;
8041                 htotal_max = 8192;
8042                 vtotal_max = 8192;
8043         } else {
8044                 hdisplay_max = 2048;
8045                 vdisplay_max = 2048;
8046                 htotal_max = 4096;
8047                 vtotal_max = 4096;
8048         }
8049
8050         if (mode->hdisplay > hdisplay_max ||
8051             mode->hsync_start > htotal_max ||
8052             mode->hsync_end > htotal_max ||
8053             mode->htotal > htotal_max)
8054                 return MODE_H_ILLEGAL;
8055
8056         if (mode->vdisplay > vdisplay_max ||
8057             mode->vsync_start > vtotal_max ||
8058             mode->vsync_end > vtotal_max ||
8059             mode->vtotal > vtotal_max)
8060                 return MODE_V_ILLEGAL;
8061
8062         if (DISPLAY_VER(dev_priv) >= 5) {
8063                 if (mode->hdisplay < 64 ||
8064                     mode->htotal - mode->hdisplay < 32)
8065                         return MODE_H_ILLEGAL;
8066
8067                 if (mode->vtotal - mode->vdisplay < 5)
8068                         return MODE_V_ILLEGAL;
8069         } else {
8070                 if (mode->htotal - mode->hdisplay < 32)
8071                         return MODE_H_ILLEGAL;
8072
8073                 if (mode->vtotal - mode->vdisplay < 3)
8074                         return MODE_V_ILLEGAL;
8075         }
8076
8077         /*
8078          * Cantiga+ cannot handle modes with a hsync front porch of 0.
8079          * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw.
8080          */
8081         if ((DISPLAY_VER(dev_priv) > 4 || IS_G4X(dev_priv)) &&
8082             mode->hsync_start == mode->hdisplay)
8083                 return MODE_H_ILLEGAL;
8084
8085         return MODE_OK;
8086 }
8087
8088 enum drm_mode_status
8089 intel_mode_valid_max_plane_size(struct drm_i915_private *dev_priv,
8090                                 const struct drm_display_mode *mode,
8091                                 bool bigjoiner)
8092 {
8093         int plane_width_max, plane_height_max;
8094
8095         /*
8096          * intel_mode_valid() should be
8097          * sufficient on older platforms.
8098          */
8099         if (DISPLAY_VER(dev_priv) < 9)
8100                 return MODE_OK;
8101
8102         /*
8103          * Most people will probably want a fullscreen
8104          * plane so let's not advertize modes that are
8105          * too big for that.
8106          */
8107         if (DISPLAY_VER(dev_priv) >= 11) {
8108                 plane_width_max = 5120 << bigjoiner;
8109                 plane_height_max = 4320;
8110         } else {
8111                 plane_width_max = 5120;
8112                 plane_height_max = 4096;
8113         }
8114
8115         if (mode->hdisplay > plane_width_max)
8116                 return MODE_H_ILLEGAL;
8117
8118         if (mode->vdisplay > plane_height_max)
8119                 return MODE_V_ILLEGAL;
8120
8121         return MODE_OK;
8122 }
8123
8124 static const struct drm_mode_config_funcs intel_mode_funcs = {
8125         .fb_create = intel_user_framebuffer_create,
8126         .get_format_info = intel_fb_get_format_info,
8127         .output_poll_changed = intel_fbdev_output_poll_changed,
8128         .mode_valid = intel_mode_valid,
8129         .atomic_check = intel_atomic_check,
8130         .atomic_commit = intel_atomic_commit,
8131         .atomic_state_alloc = intel_atomic_state_alloc,
8132         .atomic_state_clear = intel_atomic_state_clear,
8133         .atomic_state_free = intel_atomic_state_free,
8134 };
8135
8136 static const struct intel_display_funcs skl_display_funcs = {
8137         .get_pipe_config = hsw_get_pipe_config,
8138         .crtc_enable = hsw_crtc_enable,
8139         .crtc_disable = hsw_crtc_disable,
8140         .commit_modeset_enables = skl_commit_modeset_enables,
8141         .get_initial_plane_config = skl_get_initial_plane_config,
8142 };
8143
8144 static const struct intel_display_funcs ddi_display_funcs = {
8145         .get_pipe_config = hsw_get_pipe_config,
8146         .crtc_enable = hsw_crtc_enable,
8147         .crtc_disable = hsw_crtc_disable,
8148         .commit_modeset_enables = intel_commit_modeset_enables,
8149         .get_initial_plane_config = i9xx_get_initial_plane_config,
8150 };
8151
8152 static const struct intel_display_funcs pch_split_display_funcs = {
8153         .get_pipe_config = ilk_get_pipe_config,
8154         .crtc_enable = ilk_crtc_enable,
8155         .crtc_disable = ilk_crtc_disable,
8156         .commit_modeset_enables = intel_commit_modeset_enables,
8157         .get_initial_plane_config = i9xx_get_initial_plane_config,
8158 };
8159
8160 static const struct intel_display_funcs vlv_display_funcs = {
8161         .get_pipe_config = i9xx_get_pipe_config,
8162         .crtc_enable = valleyview_crtc_enable,
8163         .crtc_disable = i9xx_crtc_disable,
8164         .commit_modeset_enables = intel_commit_modeset_enables,
8165         .get_initial_plane_config = i9xx_get_initial_plane_config,
8166 };
8167
8168 static const struct intel_display_funcs i9xx_display_funcs = {
8169         .get_pipe_config = i9xx_get_pipe_config,
8170         .crtc_enable = i9xx_crtc_enable,
8171         .crtc_disable = i9xx_crtc_disable,
8172         .commit_modeset_enables = intel_commit_modeset_enables,
8173         .get_initial_plane_config = i9xx_get_initial_plane_config,
8174 };
8175
8176 /**
8177  * intel_init_display_hooks - initialize the display modesetting hooks
8178  * @dev_priv: device private
8179  */
8180 void intel_init_display_hooks(struct drm_i915_private *dev_priv)
8181 {
8182         if (!HAS_DISPLAY(dev_priv))
8183                 return;
8184
8185         intel_color_init_hooks(dev_priv);
8186         intel_init_cdclk_hooks(dev_priv);
8187         intel_audio_hooks_init(dev_priv);
8188
8189         intel_dpll_init_clock_hook(dev_priv);
8190
8191         if (DISPLAY_VER(dev_priv) >= 9) {
8192                 dev_priv->display.funcs.display = &skl_display_funcs;
8193         } else if (HAS_DDI(dev_priv)) {
8194                 dev_priv->display.funcs.display = &ddi_display_funcs;
8195         } else if (HAS_PCH_SPLIT(dev_priv)) {
8196                 dev_priv->display.funcs.display = &pch_split_display_funcs;
8197         } else if (IS_CHERRYVIEW(dev_priv) ||
8198                    IS_VALLEYVIEW(dev_priv)) {
8199                 dev_priv->display.funcs.display = &vlv_display_funcs;
8200         } else {
8201                 dev_priv->display.funcs.display = &i9xx_display_funcs;
8202         }
8203
8204         intel_fdi_init_hook(dev_priv);
8205 }
8206
8207 void intel_modeset_init_hw(struct drm_i915_private *i915)
8208 {
8209         struct intel_cdclk_state *cdclk_state;
8210
8211         if (!HAS_DISPLAY(i915))
8212                 return;
8213
8214         cdclk_state = to_intel_cdclk_state(i915->display.cdclk.obj.state);
8215
8216         intel_update_cdclk(i915);
8217         intel_cdclk_dump_config(i915, &i915->display.cdclk.hw, "Current CDCLK");
8218         cdclk_state->logical = cdclk_state->actual = i915->display.cdclk.hw;
8219 }
8220
8221 static int intel_initial_commit(struct drm_device *dev)
8222 {
8223         struct drm_atomic_state *state = NULL;
8224         struct drm_modeset_acquire_ctx ctx;
8225         struct intel_crtc *crtc;
8226         int ret = 0;
8227
8228         state = drm_atomic_state_alloc(dev);
8229         if (!state)
8230                 return -ENOMEM;
8231
8232         drm_modeset_acquire_init(&ctx, 0);
8233
8234 retry:
8235         state->acquire_ctx = &ctx;
8236
8237         for_each_intel_crtc(dev, crtc) {
8238                 struct intel_crtc_state *crtc_state =
8239                         intel_atomic_get_crtc_state(state, crtc);
8240
8241                 if (IS_ERR(crtc_state)) {
8242                         ret = PTR_ERR(crtc_state);
8243                         goto out;
8244                 }
8245
8246                 if (crtc_state->hw.active) {
8247                         struct intel_encoder *encoder;
8248
8249                         /*
8250                          * We've not yet detected sink capabilities
8251                          * (audio,infoframes,etc.) and thus we don't want to
8252                          * force a full state recomputation yet. We want that to
8253                          * happen only for the first real commit from userspace.
8254                          * So preserve the inherited flag for the time being.
8255                          */
8256                         crtc_state->inherited = true;
8257
8258                         ret = drm_atomic_add_affected_planes(state, &crtc->base);
8259                         if (ret)
8260                                 goto out;
8261
8262                         /*
8263                          * FIXME hack to force a LUT update to avoid the
8264                          * plane update forcing the pipe gamma on without
8265                          * having a proper LUT loaded. Remove once we
8266                          * have readout for pipe gamma enable.
8267                          */
8268                         crtc_state->uapi.color_mgmt_changed = true;
8269
8270                         for_each_intel_encoder_mask(dev, encoder,
8271                                                     crtc_state->uapi.encoder_mask) {
8272                                 if (encoder->initial_fastset_check &&
8273                                     !encoder->initial_fastset_check(encoder, crtc_state)) {
8274                                         ret = drm_atomic_add_affected_connectors(state,
8275                                                                                  &crtc->base);
8276                                         if (ret)
8277                                                 goto out;
8278                                 }
8279                         }
8280                 }
8281         }
8282
8283         ret = drm_atomic_commit(state);
8284
8285 out:
8286         if (ret == -EDEADLK) {
8287                 drm_atomic_state_clear(state);
8288                 drm_modeset_backoff(&ctx);
8289                 goto retry;
8290         }
8291
8292         drm_atomic_state_put(state);
8293
8294         drm_modeset_drop_locks(&ctx);
8295         drm_modeset_acquire_fini(&ctx);
8296
8297         return ret;
8298 }
8299
8300 static const struct drm_mode_config_helper_funcs intel_mode_config_funcs = {
8301         .atomic_commit_setup = drm_dp_mst_atomic_setup_commit,
8302 };
8303
8304 static void intel_mode_config_init(struct drm_i915_private *i915)
8305 {
8306         struct drm_mode_config *mode_config = &i915->drm.mode_config;
8307
8308         drm_mode_config_init(&i915->drm);
8309         INIT_LIST_HEAD(&i915->display.global.obj_list);
8310
8311         mode_config->min_width = 0;
8312         mode_config->min_height = 0;
8313
8314         mode_config->preferred_depth = 24;
8315         mode_config->prefer_shadow = 1;
8316
8317         mode_config->funcs = &intel_mode_funcs;
8318         mode_config->helper_private = &intel_mode_config_funcs;
8319
8320         mode_config->async_page_flip = HAS_ASYNC_FLIPS(i915);
8321
8322         /*
8323          * Maximum framebuffer dimensions, chosen to match
8324          * the maximum render engine surface size on gen4+.
8325          */
8326         if (DISPLAY_VER(i915) >= 7) {
8327                 mode_config->max_width = 16384;
8328                 mode_config->max_height = 16384;
8329         } else if (DISPLAY_VER(i915) >= 4) {
8330                 mode_config->max_width = 8192;
8331                 mode_config->max_height = 8192;
8332         } else if (DISPLAY_VER(i915) == 3) {
8333                 mode_config->max_width = 4096;
8334                 mode_config->max_height = 4096;
8335         } else {
8336                 mode_config->max_width = 2048;
8337                 mode_config->max_height = 2048;
8338         }
8339
8340         if (IS_I845G(i915) || IS_I865G(i915)) {
8341                 mode_config->cursor_width = IS_I845G(i915) ? 64 : 512;
8342                 mode_config->cursor_height = 1023;
8343         } else if (IS_I830(i915) || IS_I85X(i915) ||
8344                    IS_I915G(i915) || IS_I915GM(i915)) {
8345                 mode_config->cursor_width = 64;
8346                 mode_config->cursor_height = 64;
8347         } else {
8348                 mode_config->cursor_width = 256;
8349                 mode_config->cursor_height = 256;
8350         }
8351 }
8352
8353 static void intel_mode_config_cleanup(struct drm_i915_private *i915)
8354 {
8355         intel_atomic_global_obj_cleanup(i915);
8356         drm_mode_config_cleanup(&i915->drm);
8357 }
8358
8359 /* part #1: call before irq install */
8360 int intel_modeset_init_noirq(struct drm_i915_private *i915)
8361 {
8362         int ret;
8363
8364         if (i915_inject_probe_failure(i915))
8365                 return -ENODEV;
8366
8367         if (HAS_DISPLAY(i915)) {
8368                 ret = drm_vblank_init(&i915->drm,
8369                                       INTEL_NUM_PIPES(i915));
8370                 if (ret)
8371                         return ret;
8372         }
8373
8374         intel_bios_init(i915);
8375
8376         ret = intel_vga_register(i915);
8377         if (ret)
8378                 goto cleanup_bios;
8379
8380         /* FIXME: completely on the wrong abstraction layer */
8381         ret = intel_power_domains_init(i915);
8382         if (ret < 0)
8383                 goto cleanup_vga;
8384
8385         intel_power_domains_init_hw(i915, false);
8386
8387         if (!HAS_DISPLAY(i915))
8388                 return 0;
8389
8390         intel_dmc_init(i915);
8391
8392         i915->display.wq.modeset = alloc_ordered_workqueue("i915_modeset", 0);
8393         i915->display.wq.flip = alloc_workqueue("i915_flip", WQ_HIGHPRI |
8394                                                 WQ_UNBOUND, WQ_UNBOUND_MAX_ACTIVE);
8395
8396         intel_mode_config_init(i915);
8397
8398         ret = intel_cdclk_init(i915);
8399         if (ret)
8400                 goto cleanup_vga_client_pw_domain_dmc;
8401
8402         ret = intel_color_init(i915);
8403         if (ret)
8404                 goto cleanup_vga_client_pw_domain_dmc;
8405
8406         ret = intel_dbuf_init(i915);
8407         if (ret)
8408                 goto cleanup_vga_client_pw_domain_dmc;
8409
8410         ret = intel_bw_init(i915);
8411         if (ret)
8412                 goto cleanup_vga_client_pw_domain_dmc;
8413
8414         init_llist_head(&i915->display.atomic_helper.free_list);
8415         INIT_WORK(&i915->display.atomic_helper.free_work,
8416                   intel_atomic_helper_free_state_worker);
8417
8418         intel_init_quirks(i915);
8419
8420         intel_fbc_init(i915);
8421
8422         return 0;
8423
8424 cleanup_vga_client_pw_domain_dmc:
8425         intel_dmc_fini(i915);
8426         intel_power_domains_driver_remove(i915);
8427 cleanup_vga:
8428         intel_vga_unregister(i915);
8429 cleanup_bios:
8430         intel_bios_driver_remove(i915);
8431
8432         return ret;
8433 }
8434
8435 /* part #2: call after irq install, but before gem init */
8436 int intel_modeset_init_nogem(struct drm_i915_private *i915)
8437 {
8438         struct drm_device *dev = &i915->drm;
8439         enum pipe pipe;
8440         struct intel_crtc *crtc;
8441         int ret;
8442
8443         if (!HAS_DISPLAY(i915))
8444                 return 0;
8445
8446         intel_wm_init(i915);
8447
8448         intel_panel_sanitize_ssc(i915);
8449
8450         intel_pps_setup(i915);
8451
8452         intel_gmbus_setup(i915);
8453
8454         drm_dbg_kms(&i915->drm, "%d display pipe%s available.\n",
8455                     INTEL_NUM_PIPES(i915),
8456                     INTEL_NUM_PIPES(i915) > 1 ? "s" : "");
8457
8458         for_each_pipe(i915, pipe) {
8459                 ret = intel_crtc_init(i915, pipe);
8460                 if (ret) {
8461                         intel_mode_config_cleanup(i915);
8462                         return ret;
8463                 }
8464         }
8465
8466         intel_plane_possible_crtcs_init(i915);
8467         intel_shared_dpll_init(i915);
8468         intel_fdi_pll_freq_update(i915);
8469
8470         intel_update_czclk(i915);
8471         intel_modeset_init_hw(i915);
8472         intel_dpll_update_ref_clks(i915);
8473
8474         intel_hdcp_component_init(i915);
8475
8476         if (i915->display.cdclk.max_cdclk_freq == 0)
8477                 intel_update_max_cdclk(i915);
8478
8479         intel_hti_init(i915);
8480
8481         /* Just disable it once at startup */
8482         intel_vga_disable(i915);
8483         intel_setup_outputs(i915);
8484
8485         drm_modeset_lock_all(dev);
8486         intel_modeset_setup_hw_state(i915, dev->mode_config.acquire_ctx);
8487         intel_acpi_assign_connector_fwnodes(i915);
8488         drm_modeset_unlock_all(dev);
8489
8490         for_each_intel_crtc(dev, crtc) {
8491                 if (!to_intel_crtc_state(crtc->base.state)->uapi.active)
8492                         continue;
8493                 intel_crtc_initial_plane_config(crtc);
8494         }
8495
8496         /*
8497          * Make sure hardware watermarks really match the state we read out.
8498          * Note that we need to do this after reconstructing the BIOS fb's
8499          * since the watermark calculation done here will use pstate->fb.
8500          */
8501         if (!HAS_GMCH(i915))
8502                 ilk_wm_sanitize(i915);
8503
8504         return 0;
8505 }
8506
8507 /* part #3: call after gem init */
8508 int intel_modeset_init(struct drm_i915_private *i915)
8509 {
8510         int ret;
8511
8512         if (!HAS_DISPLAY(i915))
8513                 return 0;
8514
8515         /*
8516          * Force all active planes to recompute their states. So that on
8517          * mode_setcrtc after probe, all the intel_plane_state variables
8518          * are already calculated and there is no assert_plane warnings
8519          * during bootup.
8520          */
8521         ret = intel_initial_commit(&i915->drm);
8522         if (ret)
8523                 drm_dbg_kms(&i915->drm, "Initial modeset failed, %d\n", ret);
8524
8525         intel_overlay_setup(i915);
8526
8527         ret = intel_fbdev_init(&i915->drm);
8528         if (ret)
8529                 return ret;
8530
8531         /* Only enable hotplug handling once the fbdev is fully set up. */
8532         intel_hpd_init(i915);
8533         intel_hpd_poll_disable(i915);
8534
8535         skl_watermark_ipc_init(i915);
8536
8537         return 0;
8538 }
8539
8540 void i830_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe)
8541 {
8542         struct intel_crtc *crtc = intel_crtc_for_pipe(dev_priv, pipe);
8543         enum transcoder cpu_transcoder = (enum transcoder)pipe;
8544         /* 640x480@60Hz, ~25175 kHz */
8545         struct dpll clock = {
8546                 .m1 = 18,
8547                 .m2 = 7,
8548                 .p1 = 13,
8549                 .p2 = 4,
8550                 .n = 2,
8551         };
8552         u32 dpll, fp;
8553         int i;
8554
8555         drm_WARN_ON(&dev_priv->drm,
8556                     i9xx_calc_dpll_params(48000, &clock) != 25154);
8557
8558         drm_dbg_kms(&dev_priv->drm,
8559                     "enabling pipe %c due to force quirk (vco=%d dot=%d)\n",
8560                     pipe_name(pipe), clock.vco, clock.dot);
8561
8562         fp = i9xx_dpll_compute_fp(&clock);
8563         dpll = DPLL_DVO_2X_MODE |
8564                 DPLL_VGA_MODE_DIS |
8565                 ((clock.p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT) |
8566                 PLL_P2_DIVIDE_BY_4 |
8567                 PLL_REF_INPUT_DREFCLK |
8568                 DPLL_VCO_ENABLE;
8569
8570         intel_de_write(dev_priv, TRANS_HTOTAL(cpu_transcoder),
8571                        HACTIVE(640 - 1) | HTOTAL(800 - 1));
8572         intel_de_write(dev_priv, TRANS_HBLANK(cpu_transcoder),
8573                        HBLANK_START(640 - 1) | HBLANK_END(800 - 1));
8574         intel_de_write(dev_priv, TRANS_HSYNC(cpu_transcoder),
8575                        HSYNC_START(656 - 1) | HSYNC_END(752 - 1));
8576         intel_de_write(dev_priv, TRANS_VTOTAL(cpu_transcoder),
8577                        VACTIVE(480 - 1) | VTOTAL(525 - 1));
8578         intel_de_write(dev_priv, TRANS_VBLANK(cpu_transcoder),
8579                        VBLANK_START(480 - 1) | VBLANK_END(525 - 1));
8580         intel_de_write(dev_priv, TRANS_VSYNC(cpu_transcoder),
8581                        VSYNC_START(490 - 1) | VSYNC_END(492 - 1));
8582         intel_de_write(dev_priv, PIPESRC(pipe),
8583                        PIPESRC_WIDTH(640 - 1) | PIPESRC_HEIGHT(480 - 1));
8584
8585         intel_de_write(dev_priv, FP0(pipe), fp);
8586         intel_de_write(dev_priv, FP1(pipe), fp);
8587
8588         /*
8589          * Apparently we need to have VGA mode enabled prior to changing
8590          * the P1/P2 dividers. Otherwise the DPLL will keep using the old
8591          * dividers, even though the register value does change.
8592          */
8593         intel_de_write(dev_priv, DPLL(pipe), dpll & ~DPLL_VGA_MODE_DIS);
8594         intel_de_write(dev_priv, DPLL(pipe), dpll);
8595
8596         /* Wait for the clocks to stabilize. */
8597         intel_de_posting_read(dev_priv, DPLL(pipe));
8598         udelay(150);
8599
8600         /* The pixel multiplier can only be updated once the
8601          * DPLL is enabled and the clocks are stable.
8602          *
8603          * So write it again.
8604          */
8605         intel_de_write(dev_priv, DPLL(pipe), dpll);
8606
8607         /* We do this three times for luck */
8608         for (i = 0; i < 3 ; i++) {
8609                 intel_de_write(dev_priv, DPLL(pipe), dpll);
8610                 intel_de_posting_read(dev_priv, DPLL(pipe));
8611                 udelay(150); /* wait for warmup */
8612         }
8613
8614         intel_de_write(dev_priv, TRANSCONF(pipe), TRANSCONF_ENABLE);
8615         intel_de_posting_read(dev_priv, TRANSCONF(pipe));
8616
8617         intel_wait_for_pipe_scanline_moving(crtc);
8618 }
8619
8620 void i830_disable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe)
8621 {
8622         struct intel_crtc *crtc = intel_crtc_for_pipe(dev_priv, pipe);
8623
8624         drm_dbg_kms(&dev_priv->drm, "disabling pipe %c due to force quirk\n",
8625                     pipe_name(pipe));
8626
8627         drm_WARN_ON(&dev_priv->drm,
8628                     intel_de_read(dev_priv, DSPCNTR(PLANE_A)) & DISP_ENABLE);
8629         drm_WARN_ON(&dev_priv->drm,
8630                     intel_de_read(dev_priv, DSPCNTR(PLANE_B)) & DISP_ENABLE);
8631         drm_WARN_ON(&dev_priv->drm,
8632                     intel_de_read(dev_priv, DSPCNTR(PLANE_C)) & DISP_ENABLE);
8633         drm_WARN_ON(&dev_priv->drm,
8634                     intel_de_read(dev_priv, CURCNTR(PIPE_A)) & MCURSOR_MODE_MASK);
8635         drm_WARN_ON(&dev_priv->drm,
8636                     intel_de_read(dev_priv, CURCNTR(PIPE_B)) & MCURSOR_MODE_MASK);
8637
8638         intel_de_write(dev_priv, TRANSCONF(pipe), 0);
8639         intel_de_posting_read(dev_priv, TRANSCONF(pipe));
8640
8641         intel_wait_for_pipe_scanline_stopped(crtc);
8642
8643         intel_de_write(dev_priv, DPLL(pipe), DPLL_VGA_MODE_DIS);
8644         intel_de_posting_read(dev_priv, DPLL(pipe));
8645 }
8646
8647 void intel_display_resume(struct drm_device *dev)
8648 {
8649         struct drm_i915_private *i915 = to_i915(dev);
8650         struct drm_atomic_state *state = i915->display.restore.modeset_state;
8651         struct drm_modeset_acquire_ctx ctx;
8652         int ret;
8653
8654         if (!HAS_DISPLAY(i915))
8655                 return;
8656
8657         i915->display.restore.modeset_state = NULL;
8658         if (state)
8659                 state->acquire_ctx = &ctx;
8660
8661         drm_modeset_acquire_init(&ctx, 0);
8662
8663         while (1) {
8664                 ret = drm_modeset_lock_all_ctx(dev, &ctx);
8665                 if (ret != -EDEADLK)
8666                         break;
8667
8668                 drm_modeset_backoff(&ctx);
8669         }
8670
8671         if (!ret)
8672                 ret = __intel_display_resume(i915, state, &ctx);
8673
8674         skl_watermark_ipc_update(i915);
8675         drm_modeset_drop_locks(&ctx);
8676         drm_modeset_acquire_fini(&ctx);
8677
8678         if (ret)
8679                 drm_err(&i915->drm,
8680                         "Restoring old state failed with %i\n", ret);
8681         if (state)
8682                 drm_atomic_state_put(state);
8683 }
8684
8685 static void intel_hpd_poll_fini(struct drm_i915_private *i915)
8686 {
8687         struct intel_connector *connector;
8688         struct drm_connector_list_iter conn_iter;
8689
8690         /* Kill all the work that may have been queued by hpd. */
8691         drm_connector_list_iter_begin(&i915->drm, &conn_iter);
8692         for_each_intel_connector_iter(connector, &conn_iter) {
8693                 if (connector->modeset_retry_work.func)
8694                         cancel_work_sync(&connector->modeset_retry_work);
8695                 if (connector->hdcp.shim) {
8696                         cancel_delayed_work_sync(&connector->hdcp.check_work);
8697                         cancel_work_sync(&connector->hdcp.prop_work);
8698                 }
8699         }
8700         drm_connector_list_iter_end(&conn_iter);
8701 }
8702
8703 /* part #1: call before irq uninstall */
8704 void intel_modeset_driver_remove(struct drm_i915_private *i915)
8705 {
8706         if (!HAS_DISPLAY(i915))
8707                 return;
8708
8709         flush_workqueue(i915->display.wq.flip);
8710         flush_workqueue(i915->display.wq.modeset);
8711
8712         flush_work(&i915->display.atomic_helper.free_work);
8713         drm_WARN_ON(&i915->drm, !llist_empty(&i915->display.atomic_helper.free_list));
8714
8715         /*
8716          * MST topology needs to be suspended so we don't have any calls to
8717          * fbdev after it's finalized. MST will be destroyed later as part of
8718          * drm_mode_config_cleanup()
8719          */
8720         intel_dp_mst_suspend(i915);
8721 }
8722
8723 /* part #2: call after irq uninstall */
8724 void intel_modeset_driver_remove_noirq(struct drm_i915_private *i915)
8725 {
8726         if (!HAS_DISPLAY(i915))
8727                 return;
8728
8729         /*
8730          * Due to the hpd irq storm handling the hotplug work can re-arm the
8731          * poll handlers. Hence disable polling after hpd handling is shut down.
8732          */
8733         intel_hpd_poll_fini(i915);
8734
8735         /* poll work can call into fbdev, hence clean that up afterwards */
8736         intel_fbdev_fini(i915);
8737
8738         intel_unregister_dsm_handler();
8739
8740         /* flush any delayed tasks or pending work */
8741         flush_scheduled_work();
8742
8743         intel_hdcp_component_fini(i915);
8744
8745         intel_mode_config_cleanup(i915);
8746
8747         intel_overlay_cleanup(i915);
8748
8749         intel_gmbus_teardown(i915);
8750
8751         destroy_workqueue(i915->display.wq.flip);
8752         destroy_workqueue(i915->display.wq.modeset);
8753
8754         intel_fbc_cleanup(i915);
8755 }
8756
8757 /* part #3: call after gem init */
8758 void intel_modeset_driver_remove_nogem(struct drm_i915_private *i915)
8759 {
8760         intel_dmc_fini(i915);
8761
8762         intel_power_domains_driver_remove(i915);
8763
8764         intel_vga_unregister(i915);
8765
8766         intel_bios_driver_remove(i915);
8767 }
8768
8769 bool intel_modeset_probe_defer(struct pci_dev *pdev)
8770 {
8771         struct drm_privacy_screen *privacy_screen;
8772
8773         /*
8774          * apple-gmux is needed on dual GPU MacBook Pro
8775          * to probe the panel if we're the inactive GPU.
8776          */
8777         if (vga_switcheroo_client_probe_defer(pdev))
8778                 return true;
8779
8780         /* If the LCD panel has a privacy-screen, wait for it */
8781         privacy_screen = drm_privacy_screen_get(&pdev->dev, NULL);
8782         if (IS_ERR(privacy_screen) && PTR_ERR(privacy_screen) == -EPROBE_DEFER)
8783                 return true;
8784
8785         drm_privacy_screen_put(privacy_screen);
8786
8787         return false;
8788 }
8789
8790 void intel_display_driver_register(struct drm_i915_private *i915)
8791 {
8792         if (!HAS_DISPLAY(i915))
8793                 return;
8794
8795         /* Must be done after probing outputs */
8796         intel_opregion_register(i915);
8797         intel_acpi_video_register(i915);
8798
8799         intel_audio_init(i915);
8800
8801         intel_display_debugfs_register(i915);
8802
8803         /*
8804          * Some ports require correctly set-up hpd registers for
8805          * detection to work properly (leading to ghost connected
8806          * connector status), e.g. VGA on gm45.  Hence we can only set
8807          * up the initial fbdev config after hpd irqs are fully
8808          * enabled. We do it last so that the async config cannot run
8809          * before the connectors are registered.
8810          */
8811         intel_fbdev_initial_config_async(i915);
8812
8813         /*
8814          * We need to coordinate the hotplugs with the asynchronous
8815          * fbdev configuration, for which we use the
8816          * fbdev->async_cookie.
8817          */
8818         drm_kms_helper_poll_init(&i915->drm);
8819 }
8820
8821 void intel_display_driver_unregister(struct drm_i915_private *i915)
8822 {
8823         if (!HAS_DISPLAY(i915))
8824                 return;
8825
8826         intel_fbdev_unregister(i915);
8827         intel_audio_deinit(i915);
8828
8829         /*
8830          * After flushing the fbdev (incl. a late async config which
8831          * will have delayed queuing of a hotplug event), then flush
8832          * the hotplug events.
8833          */
8834         drm_kms_helper_poll_fini(&i915->drm);
8835         drm_atomic_helper_shutdown(&i915->drm);
8836
8837         acpi_video_unregister();
8838         intel_opregion_unregister(i915);
8839 }
8840
8841 bool intel_scanout_needs_vtd_wa(struct drm_i915_private *i915)
8842 {
8843         return DISPLAY_VER(i915) >= 6 && i915_vtd_active(i915);
8844 }