drivers/gpu/drm/i915/display/intel_ddi.c

   1 /*
   2  * Copyright © 2012 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *    Eugeni Dodonov <[email protected]>
  25  *
  26  */
  27
  28 #include <linux/string_helpers.h>
  29
  30 #include <drm/display/drm_scdc_helper.h>
  31 #include <drm/drm_privacy_screen_consumer.h>
  32
  33 #include "i915_drv.h"
  34 #include "i915_reg.h"
  35 #include "intel_audio.h"
  36 #include "intel_audio_regs.h"
  37 #include "intel_backlight.h"
  38 #include "intel_combo_phy.h"
  39 #include "intel_combo_phy_regs.h"
  40 #include "intel_connector.h"
  41 #include "intel_crtc.h"
  42 #include "intel_ddi.h"
  43 #include "intel_ddi_buf_trans.h"
  44 #include "intel_de.h"
  45 #include "intel_display_power.h"
  46 #include "intel_display_types.h"
  47 #include "intel_dkl_phy.h"
  48 #include "intel_dkl_phy_regs.h"
  49 #include "intel_dp.h"
  50 #include "intel_dp_aux.h"
  51 #include "intel_dp_link_training.h"
  52 #include "intel_dp_mst.h"
  53 #include "intel_dpio_phy.h"
  54 #include "intel_dsi.h"
  55 #include "intel_fdi.h"
  56 #include "intel_fifo_underrun.h"
  57 #include "intel_gmbus.h"
  58 #include "intel_hdcp.h"
  59 #include "intel_hdmi.h"
  60 #include "intel_hotplug.h"
  61 #include "intel_hti.h"
  62 #include "intel_lspcon.h"
  63 #include "intel_mg_phy_regs.h"
  64 #include "intel_pps.h"
  65 #include "intel_psr.h"
  66 #include "intel_quirks.h"
  67 #include "intel_snps_phy.h"
  68 #include "intel_tc.h"
  69 #include "intel_vdsc.h"
  70 #include "intel_vdsc_regs.h"
  71 #include "intel_vrr.h"
  72 #include "skl_scaler.h"
  73 #include "skl_universal_plane.h"
  74
  75 static const u8 index_to_dp_signal_levels[] = {
  76         [0] = DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_0,
  77         [1] = DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_1,
  78         [2] = DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_2,
  79         [3] = DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_3,
  80         [4] = DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_0,
  81         [5] = DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_1,
  82         [6] = DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_2,
  83         [7] = DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_0,
  84         [8] = DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_1,
  85         [9] = DP_TRAIN_VOLTAGE_SWING_LEVEL_3 | DP_TRAIN_PRE_EMPH_LEVEL_0,
  86 };
  87
  88 static int intel_ddi_hdmi_level(struct intel_encoder *encoder,
  89                                 const struct intel_ddi_buf_trans *trans)
  90 {
  91         int level;
  92
  93         level = intel_bios_hdmi_level_shift(encoder->devdata);
  94         if (level < 0)
  95                 level = trans->hdmi_default_entry;
  96
  97         return level;
  98 }
  99
 100 static bool has_buf_trans_select(struct drm_i915_private *i915)
 101 {
 102         return DISPLAY_VER(i915) < 10 && !IS_BROXTON(i915);
 103 }
 104
 105 static bool has_iboost(struct drm_i915_private *i915)
 106 {
 107         return DISPLAY_VER(i915) == 9 && !IS_BROXTON(i915);
 108 }
 109
 110 /*
 111  * Starting with Haswell, DDI port buffers must be programmed with correct
 112  * values in advance. This function programs the correct values for
 113  * DP/eDP/FDI use cases.
 114  */
 115 void hsw_prepare_dp_ddi_buffers(struct intel_encoder *encoder,
 116                                 const struct intel_crtc_state *crtc_state)
 117 {
 118         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 119         u32 iboost_bit = 0;
 120         int i, n_entries;
 121         enum port port = encoder->port;
 122         const struct intel_ddi_buf_trans *trans;
 123
 124         trans = encoder->get_buf_trans(encoder, crtc_state, &n_entries);
 125         if (drm_WARN_ON_ONCE(&dev_priv->drm, !trans))
 126                 return;
 127
 128         /* If we're boosting the current, set bit 31 of trans1 */
 129         if (has_iboost(dev_priv) &&
 130             intel_bios_dp_boost_level(encoder->devdata))
 131                 iboost_bit = DDI_BUF_BALANCE_LEG_ENABLE;
 132
 133         for (i = 0; i < n_entries; i++) {
 134                 intel_de_write(dev_priv, DDI_BUF_TRANS_LO(port, i),
 135                                trans->entries[i].hsw.trans1 | iboost_bit);
 136                 intel_de_write(dev_priv, DDI_BUF_TRANS_HI(port, i),
 137                                trans->entries[i].hsw.trans2);
 138         }
 139 }
 140
 141 /*
 142  * Starting with Haswell, DDI port buffers must be programmed with correct
 143  * values in advance. This function programs the correct values for
 144  * HDMI/DVI use cases.
 145  */
 146 static void hsw_prepare_hdmi_ddi_buffers(struct intel_encoder *encoder,
 147                                          const struct intel_crtc_state *crtc_state)
 148 {
 149         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 150         int level = intel_ddi_level(encoder, crtc_state, 0);
 151         u32 iboost_bit = 0;
 152         int n_entries;
 153         enum port port = encoder->port;
 154         const struct intel_ddi_buf_trans *trans;
 155
 156         trans = encoder->get_buf_trans(encoder, crtc_state, &n_entries);
 157         if (drm_WARN_ON_ONCE(&dev_priv->drm, !trans))
 158                 return;
 159
 160         /* If we're boosting the current, set bit 31 of trans1 */
 161         if (has_iboost(dev_priv) &&
 162             intel_bios_hdmi_boost_level(encoder->devdata))
 163                 iboost_bit = DDI_BUF_BALANCE_LEG_ENABLE;
 164
 165         /* Entry 9 is for HDMI: */
 166         intel_de_write(dev_priv, DDI_BUF_TRANS_LO(port, 9),
 167                        trans->entries[level].hsw.trans1 | iboost_bit);
 168         intel_de_write(dev_priv, DDI_BUF_TRANS_HI(port, 9),
 169                        trans->entries[level].hsw.trans2);
 170 }
 171
 172 void intel_wait_ddi_buf_idle(struct drm_i915_private *dev_priv,
 173                              enum port port)
 174 {
 175         if (IS_BROXTON(dev_priv)) {
 176                 udelay(16);
 177                 return;
 178         }
 179
 180         if (wait_for_us((intel_de_read(dev_priv, DDI_BUF_CTL(port)) &
 181                          DDI_BUF_IS_IDLE), 8))
 182                 drm_err(&dev_priv->drm, "Timeout waiting for DDI BUF %c to get idle\n",
 183                         port_name(port));
 184 }
 185
 186 static void intel_wait_ddi_buf_active(struct drm_i915_private *dev_priv,
 187                                       enum port port)
 188 {
 189         enum phy phy = intel_port_to_phy(dev_priv, port);
 190         int timeout_us;
 191         int ret;
 192
 193         /* Wait > 518 usecs for DDI_BUF_CTL to be non idle */
 194         if (DISPLAY_VER(dev_priv) < 10) {
 195                 usleep_range(518, 1000);
 196                 return;
 197         }
 198
 199         if (IS_DG2(dev_priv)) {
 200                 timeout_us = 1200;
 201         } else if (DISPLAY_VER(dev_priv) >= 12) {
 202                 if (intel_phy_is_tc(dev_priv, phy))
 203                         timeout_us = 3000;
 204                 else
 205                         timeout_us = 1000;
 206         } else {
 207                 timeout_us = 500;
 208         }
 209
 210         ret = _wait_for(!(intel_de_read(dev_priv, DDI_BUF_CTL(port)) &
 211                           DDI_BUF_IS_IDLE), timeout_us, 10, 10);
 212
 213         if (ret)
 214                 drm_err(&dev_priv->drm, "Timeout waiting for DDI BUF %c to get active\n",
 215                         port_name(port));
 216 }
 217
 218 static u32 hsw_pll_to_ddi_pll_sel(const struct intel_shared_dpll *pll)
 219 {
 220         switch (pll->info->id) {
 221         case DPLL_ID_WRPLL1:
 222                 return PORT_CLK_SEL_WRPLL1;
 223         case DPLL_ID_WRPLL2:
 224                 return PORT_CLK_SEL_WRPLL2;
 225         case DPLL_ID_SPLL:
 226                 return PORT_CLK_SEL_SPLL;
 227         case DPLL_ID_LCPLL_810:
 228                 return PORT_CLK_SEL_LCPLL_810;
 229         case DPLL_ID_LCPLL_1350:
 230                 return PORT_CLK_SEL_LCPLL_1350;
 231         case DPLL_ID_LCPLL_2700:
 232                 return PORT_CLK_SEL_LCPLL_2700;
 233         default:
 234                 MISSING_CASE(pll->info->id);
 235                 return PORT_CLK_SEL_NONE;
 236         }
 237 }
 238
 239 static u32 icl_pll_to_ddi_clk_sel(struct intel_encoder *encoder,
 240                                   const struct intel_crtc_state *crtc_state)
 241 {
 242         const struct intel_shared_dpll *pll = crtc_state->shared_dpll;
 243         int clock = crtc_state->port_clock;
 244         const enum intel_dpll_id id = pll->info->id;
 245
 246         switch (id) {
 247         default:
 248                 /*
 249                  * DPLL_ID_ICL_DPLL0 and DPLL_ID_ICL_DPLL1 should not be used
 250                  * here, so do warn if this get passed in
 251                  */
 252                 MISSING_CASE(id);
 253                 return DDI_CLK_SEL_NONE;
 254         case DPLL_ID_ICL_TBTPLL:
 255                 switch (clock) {
 256                 case 162000:
 257                         return DDI_CLK_SEL_TBT_162;
 258                 case 270000:
 259                         return DDI_CLK_SEL_TBT_270;
 260                 case 540000:
 261                         return DDI_CLK_SEL_TBT_540;
 262                 case 810000:
 263                         return DDI_CLK_SEL_TBT_810;
 264                 default:
 265                         MISSING_CASE(clock);
 266                         return DDI_CLK_SEL_NONE;
 267                 }
 268         case DPLL_ID_ICL_MGPLL1:
 269         case DPLL_ID_ICL_MGPLL2:
 270         case DPLL_ID_ICL_MGPLL3:
 271         case DPLL_ID_ICL_MGPLL4:
 272         case DPLL_ID_TGL_MGPLL5:
 273         case DPLL_ID_TGL_MGPLL6:
 274                 return DDI_CLK_SEL_MG;
 275         }
 276 }
 277
 278 static u32 ddi_buf_phy_link_rate(int port_clock)
 279 {
 280         switch (port_clock) {
 281         case 162000:
 282                 return DDI_BUF_PHY_LINK_RATE(0);
 283         case 216000:
 284                 return DDI_BUF_PHY_LINK_RATE(4);
 285         case 243000:
 286                 return DDI_BUF_PHY_LINK_RATE(5);
 287         case 270000:
 288                 return DDI_BUF_PHY_LINK_RATE(1);
 289         case 324000:
 290                 return DDI_BUF_PHY_LINK_RATE(6);
 291         case 432000:
 292                 return DDI_BUF_PHY_LINK_RATE(7);
 293         case 540000:
 294                 return DDI_BUF_PHY_LINK_RATE(2);
 295         case 810000:
 296                 return DDI_BUF_PHY_LINK_RATE(3);
 297         default:
 298                 MISSING_CASE(port_clock);
 299                 return DDI_BUF_PHY_LINK_RATE(0);
 300         }
 301 }
 302
 303 static void intel_ddi_init_dp_buf_reg(struct intel_encoder *encoder,
 304                                       const struct intel_crtc_state *crtc_state)
 305 {
 306         struct drm_i915_private *i915 = to_i915(encoder->base.dev);
 307         struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
 308         struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
 309         enum phy phy = intel_port_to_phy(i915, encoder->port);
 310
 311         /* DDI_BUF_CTL_ENABLE will be set by intel_ddi_prepare_link_retrain() later */
 312         intel_dp->DP = dig_port->saved_port_bits |
 313                 DDI_PORT_WIDTH(crtc_state->lane_count) |
 314                 DDI_BUF_TRANS_SELECT(0);
 315
 316         if (IS_ALDERLAKE_P(i915) && intel_phy_is_tc(i915, phy)) {
 317                 intel_dp->DP |= ddi_buf_phy_link_rate(crtc_state->port_clock);
 318                 if (!intel_tc_port_in_tbt_alt_mode(dig_port))
 319                         intel_dp->DP |= DDI_BUF_CTL_TC_PHY_OWNERSHIP;
 320         }
 321 }
 322
 323 static int icl_calc_tbt_pll_link(struct drm_i915_private *dev_priv,
 324                                  enum port port)
 325 {
 326         u32 val = intel_de_read(dev_priv, DDI_CLK_SEL(port)) & DDI_CLK_SEL_MASK;
 327
 328         switch (val) {
 329         case DDI_CLK_SEL_NONE:
 330                 return 0;
 331         case DDI_CLK_SEL_TBT_162:
 332                 return 162000;
 333         case DDI_CLK_SEL_TBT_270:
 334                 return 270000;
 335         case DDI_CLK_SEL_TBT_540:
 336                 return 540000;
 337         case DDI_CLK_SEL_TBT_810:
 338                 return 810000;
 339         default:
 340                 MISSING_CASE(val);
 341                 return 0;
 342         }
 343 }
 344
 345 static void ddi_dotclock_get(struct intel_crtc_state *pipe_config)
 346 {
 347         /* CRT dotclock is determined via other means */
 348         if (pipe_config->has_pch_encoder)
 349                 return;
 350
 351         pipe_config->hw.adjusted_mode.crtc_clock =
 352                 intel_crtc_dotclock(pipe_config);
 353 }
 354
 355 void intel_ddi_set_dp_msa(const struct intel_crtc_state *crtc_state,
 356                           const struct drm_connector_state *conn_state)
 357 {
 358         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
 359         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 360         enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
 361         u32 temp;
 362
 363         if (!intel_crtc_has_dp_encoder(crtc_state))
 364                 return;
 365
 366         drm_WARN_ON(&dev_priv->drm, transcoder_is_dsi(cpu_transcoder));
 367
 368         temp = DP_MSA_MISC_SYNC_CLOCK;
 369
 370         switch (crtc_state->pipe_bpp) {
 371         case 18:
 372                 temp |= DP_MSA_MISC_6_BPC;
 373                 break;
 374         case 24:
 375                 temp |= DP_MSA_MISC_8_BPC;
 376                 break;
 377         case 30:
 378                 temp |= DP_MSA_MISC_10_BPC;
 379                 break;
 380         case 36:
 381                 temp |= DP_MSA_MISC_12_BPC;
 382                 break;
 383         default:
 384                 MISSING_CASE(crtc_state->pipe_bpp);
 385                 break;
 386         }
 387
 388         /* nonsense combination */
 389         drm_WARN_ON(&dev_priv->drm, crtc_state->limited_color_range &&
 390                     crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB);
 391
 392         if (crtc_state->limited_color_range)
 393                 temp |= DP_MSA_MISC_COLOR_CEA_RGB;
 394
 395         /*
 396          * As per DP 1.2 spec section 2.3.4.3 while sending
 397          * YCBCR 444 signals we should program MSA MISC1/0 fields with
 398          * colorspace information.
 399          */
 400         if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR444)
 401                 temp |= DP_MSA_MISC_COLOR_YCBCR_444_BT709;
 402
 403         /*
 404          * As per DP 1.4a spec section 2.2.4.3 [MSA Field for Indication
 405          * of Color Encoding Format and Content Color Gamut] while sending
 406          * YCBCR 420, HDR BT.2020 signals we should program MSA MISC1 fields
 407          * which indicate VSC SDP for the Pixel Encoding/Colorimetry Format.
 408          */
 409         if (intel_dp_needs_vsc_sdp(crtc_state, conn_state))
 410                 temp |= DP_MSA_MISC_COLOR_VSC_SDP;
 411
 412         intel_de_write(dev_priv, TRANS_MSA_MISC(cpu_transcoder), temp);
 413 }
 414
 415 static u32 bdw_trans_port_sync_master_select(enum transcoder master_transcoder)
 416 {
 417         if (master_transcoder == TRANSCODER_EDP)
 418                 return 0;
 419         else
 420                 return master_transcoder + 1;
 421 }
 422
 423 static void
 424 intel_ddi_config_transcoder_dp2(struct intel_encoder *encoder,
 425                                 const struct intel_crtc_state *crtc_state)
 426 {
 427         struct drm_i915_private *i915 = to_i915(encoder->base.dev);
 428         enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
 429         u32 val = 0;
 430
 431         if (intel_dp_is_uhbr(crtc_state))
 432                 val = TRANS_DP2_128B132B_CHANNEL_CODING;
 433
 434         intel_de_write(i915, TRANS_DP2_CTL(cpu_transcoder), val);
 435 }
 436
 437 /*
 438  * Returns the TRANS_DDI_FUNC_CTL value based on CRTC state.
 439  *
 440  * Only intended to be used by intel_ddi_enable_transcoder_func() and
 441  * intel_ddi_config_transcoder_func().
 442  */
 443 static u32
 444 intel_ddi_transcoder_func_reg_val_get(struct intel_encoder *encoder,
 445                                       const struct intel_crtc_state *crtc_state)
 446 {
 447         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
 448         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 449         enum pipe pipe = crtc->pipe;
 450         enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
 451         enum port port = encoder->port;
 452         u32 temp;
 453
 454         /* Enable TRANS_DDI_FUNC_CTL for the pipe to work in HDMI mode */
 455         temp = TRANS_DDI_FUNC_ENABLE;
 456         if (DISPLAY_VER(dev_priv) >= 12)
 457                 temp |= TGL_TRANS_DDI_SELECT_PORT(port);
 458         else
 459                 temp |= TRANS_DDI_SELECT_PORT(port);
 460
 461         switch (crtc_state->pipe_bpp) {
 462         default:
 463                 MISSING_CASE(crtc_state->pipe_bpp);
 464                 fallthrough;
 465         case 18:
 466                 temp |= TRANS_DDI_BPC_6;
 467                 break;
 468         case 24:
 469                 temp |= TRANS_DDI_BPC_8;
 470                 break;
 471         case 30:
 472                 temp |= TRANS_DDI_BPC_10;
 473                 break;
 474         case 36:
 475                 temp |= TRANS_DDI_BPC_12;
 476                 break;
 477         }
 478
 479         if (crtc_state->hw.adjusted_mode.flags & DRM_MODE_FLAG_PVSYNC)
 480                 temp |= TRANS_DDI_PVSYNC;
 481         if (crtc_state->hw.adjusted_mode.flags & DRM_MODE_FLAG_PHSYNC)
 482                 temp |= TRANS_DDI_PHSYNC;
 483
 484         if (cpu_transcoder == TRANSCODER_EDP) {
 485                 switch (pipe) {
 486                 default:
 487                         MISSING_CASE(pipe);
 488                         fallthrough;
 489                 case PIPE_A:
 490                         /* On Haswell, can only use the always-on power well for
 491                          * eDP when not using the panel fitter, and when not
 492                          * using motion blur mitigation (which we don't
 493                          * support). */
 494                         if (crtc_state->pch_pfit.force_thru)
 495                                 temp |= TRANS_DDI_EDP_INPUT_A_ONOFF;
 496                         else
 497                                 temp |= TRANS_DDI_EDP_INPUT_A_ON;
 498                         break;
 499                 case PIPE_B:
 500                         temp |= TRANS_DDI_EDP_INPUT_B_ONOFF;
 501                         break;
 502                 case PIPE_C:
 503                         temp |= TRANS_DDI_EDP_INPUT_C_ONOFF;
 504                         break;
 505                 }
 506         }
 507
 508         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) {
 509                 if (crtc_state->has_hdmi_sink)
 510                         temp |= TRANS_DDI_MODE_SELECT_HDMI;
 511                 else
 512                         temp |= TRANS_DDI_MODE_SELECT_DVI;
 513
 514                 if (crtc_state->hdmi_scrambling)
 515                         temp |= TRANS_DDI_HDMI_SCRAMBLING;
 516                 if (crtc_state->hdmi_high_tmds_clock_ratio)
 517                         temp |= TRANS_DDI_HIGH_TMDS_CHAR_RATE;
 518         } else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_ANALOG)) {
 519                 temp |= TRANS_DDI_MODE_SELECT_FDI_OR_128B132B;
 520                 temp |= (crtc_state->fdi_lanes - 1) << 1;
 521         } else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST)) {
 522                 if (intel_dp_is_uhbr(crtc_state))
 523                         temp |= TRANS_DDI_MODE_SELECT_FDI_OR_128B132B;
 524                 else
 525                         temp |= TRANS_DDI_MODE_SELECT_DP_MST;
 526                 temp |= DDI_PORT_WIDTH(crtc_state->lane_count);
 527
 528                 if (DISPLAY_VER(dev_priv) >= 12) {
 529                         enum transcoder master;
 530
 531                         master = crtc_state->mst_master_transcoder;
 532                         drm_WARN_ON(&dev_priv->drm,
 533                                     master == INVALID_TRANSCODER);
 534                         temp |= TRANS_DDI_MST_TRANSPORT_SELECT(master);
 535                 }
 536         } else {
 537                 temp |= TRANS_DDI_MODE_SELECT_DP_SST;
 538                 temp |= DDI_PORT_WIDTH(crtc_state->lane_count);
 539         }
 540
 541         if (IS_DISPLAY_VER(dev_priv, 8, 10) &&
 542             crtc_state->master_transcoder != INVALID_TRANSCODER) {
 543                 u8 master_select =
 544                         bdw_trans_port_sync_master_select(crtc_state->master_transcoder);
 545
 546                 temp |= TRANS_DDI_PORT_SYNC_ENABLE |
 547                         TRANS_DDI_PORT_SYNC_MASTER_SELECT(master_select);
 548         }
 549
 550         return temp;
 551 }
 552
 553 void intel_ddi_enable_transcoder_func(struct intel_encoder *encoder,
 554                                       const struct intel_crtc_state *crtc_state)
 555 {
 556         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
 557         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 558         enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
 559
 560         if (DISPLAY_VER(dev_priv) >= 11) {
 561                 enum transcoder master_transcoder = crtc_state->master_transcoder;
 562                 u32 ctl2 = 0;
 563
 564                 if (master_transcoder != INVALID_TRANSCODER) {
 565                         u8 master_select =
 566                                 bdw_trans_port_sync_master_select(master_transcoder);
 567
 568                         ctl2 |= PORT_SYNC_MODE_ENABLE |
 569                                 PORT_SYNC_MODE_MASTER_SELECT(master_select);
 570                 }
 571
 572                 intel_de_write(dev_priv,
 573                                TRANS_DDI_FUNC_CTL2(cpu_transcoder), ctl2);
 574         }
 575
 576         intel_de_write(dev_priv, TRANS_DDI_FUNC_CTL(cpu_transcoder),
 577                        intel_ddi_transcoder_func_reg_val_get(encoder,
 578                                                              crtc_state));
 579 }
 580
 581 /*
 582  * Same as intel_ddi_enable_transcoder_func(), but it does not set the enable
 583  * bit.
 584  */
 585 static void
 586 intel_ddi_config_transcoder_func(struct intel_encoder *encoder,
 587                                  const struct intel_crtc_state *crtc_state)
 588 {
 589         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
 590         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 591         enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
 592         u32 ctl;
 593
 594         ctl = intel_ddi_transcoder_func_reg_val_get(encoder, crtc_state);
 595         ctl &= ~TRANS_DDI_FUNC_ENABLE;
 596         intel_de_write(dev_priv, TRANS_DDI_FUNC_CTL(cpu_transcoder), ctl);
 597 }
 598
 599 void intel_ddi_disable_transcoder_func(const struct intel_crtc_state *crtc_state)
 600 {
 601         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
 602         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 603         enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
 604         u32 ctl;
 605
 606         if (DISPLAY_VER(dev_priv) >= 11)
 607                 intel_de_write(dev_priv,
 608                                TRANS_DDI_FUNC_CTL2(cpu_transcoder), 0);
 609
 610         ctl = intel_de_read(dev_priv, TRANS_DDI_FUNC_CTL(cpu_transcoder));
 611
 612         drm_WARN_ON(crtc->base.dev, ctl & TRANS_DDI_HDCP_SIGNALLING);
 613
 614         ctl &= ~TRANS_DDI_FUNC_ENABLE;
 615
 616         if (IS_DISPLAY_VER(dev_priv, 8, 10))
 617                 ctl &= ~(TRANS_DDI_PORT_SYNC_ENABLE |
 618                          TRANS_DDI_PORT_SYNC_MASTER_SELECT_MASK);
 619
 620         if (DISPLAY_VER(dev_priv) >= 12) {
 621                 if (!intel_dp_mst_is_master_trans(crtc_state)) {
 622                         ctl &= ~(TGL_TRANS_DDI_PORT_MASK |
 623                                  TRANS_DDI_MODE_SELECT_MASK);
 624                 }
 625         } else {
 626                 ctl &= ~(TRANS_DDI_PORT_MASK | TRANS_DDI_MODE_SELECT_MASK);
 627         }
 628
 629         intel_de_write(dev_priv, TRANS_DDI_FUNC_CTL(cpu_transcoder), ctl);
 630
 631         if (intel_has_quirk(dev_priv, QUIRK_INCREASE_DDI_DISABLED_TIME) &&
 632             intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) {
 633                 drm_dbg_kms(&dev_priv->drm,
 634                             "Quirk Increase DDI disabled time\n");
 635                 /* Quirk time at 100ms for reliable operation */
 636                 msleep(100);
 637         }
 638 }
 639
 640 int intel_ddi_toggle_hdcp_bits(struct intel_encoder *intel_encoder,
 641                                enum transcoder cpu_transcoder,
 642                                bool enable, u32 hdcp_mask)
 643 {
 644         struct drm_device *dev = intel_encoder->base.dev;
 645         struct drm_i915_private *dev_priv = to_i915(dev);
 646         intel_wakeref_t wakeref;
 647         int ret = 0;
 648
 649         wakeref = intel_display_power_get_if_enabled(dev_priv,
 650                                                      intel_encoder->power_domain);
 651         if (drm_WARN_ON(dev, !wakeref))
 652                 return -ENXIO;
 653
 654         intel_de_rmw(dev_priv, TRANS_DDI_FUNC_CTL(cpu_transcoder),
 655                      hdcp_mask, enable ? hdcp_mask : 0);
 656         intel_display_power_put(dev_priv, intel_encoder->power_domain, wakeref);
 657         return ret;
 658 }
 659
 660 bool intel_ddi_connector_get_hw_state(struct intel_connector *intel_connector)
 661 {
 662         struct drm_device *dev = intel_connector->base.dev;
 663         struct drm_i915_private *dev_priv = to_i915(dev);
 664         struct intel_encoder *encoder = intel_attached_encoder(intel_connector);
 665         int type = intel_connector->base.connector_type;
 666         enum port port = encoder->port;
 667         enum transcoder cpu_transcoder;
 668         intel_wakeref_t wakeref;
 669         enum pipe pipe = 0;
 670         u32 tmp;
 671         bool ret;
 672
 673         wakeref = intel_display_power_get_if_enabled(dev_priv,
 674                                                      encoder->power_domain);
 675         if (!wakeref)
 676                 return false;
 677
 678         if (!encoder->get_hw_state(encoder, &pipe)) {
 679                 ret = false;
 680                 goto out;
 681         }
 682
 683         if (HAS_TRANSCODER(dev_priv, TRANSCODER_EDP) && port == PORT_A)
 684                 cpu_transcoder = TRANSCODER_EDP;
 685         else
 686                 cpu_transcoder = (enum transcoder) pipe;
 687
 688         tmp = intel_de_read(dev_priv, TRANS_DDI_FUNC_CTL(cpu_transcoder));
 689
 690         switch (tmp & TRANS_DDI_MODE_SELECT_MASK) {
 691         case TRANS_DDI_MODE_SELECT_HDMI:
 692         case TRANS_DDI_MODE_SELECT_DVI:
 693                 ret = type == DRM_MODE_CONNECTOR_HDMIA;
 694                 break;
 695
 696         case TRANS_DDI_MODE_SELECT_DP_SST:
 697                 ret = type == DRM_MODE_CONNECTOR_eDP ||
 698                       type == DRM_MODE_CONNECTOR_DisplayPort;
 699                 break;
 700
 701         case TRANS_DDI_MODE_SELECT_DP_MST:
 702                 /* if the transcoder is in MST state then
 703                  * connector isn't connected */
 704                 ret = false;
 705                 break;
 706
 707         case TRANS_DDI_MODE_SELECT_FDI_OR_128B132B:
 708                 if (HAS_DP20(dev_priv))
 709                         /* 128b/132b */
 710                         ret = false;
 711                 else
 712                         /* FDI */
 713                         ret = type == DRM_MODE_CONNECTOR_VGA;
 714                 break;
 715
 716         default:
 717                 ret = false;
 718                 break;
 719         }
 720
 721 out:
 722         intel_display_power_put(dev_priv, encoder->power_domain, wakeref);
 723
 724         return ret;
 725 }
 726
 727 static void intel_ddi_get_encoder_pipes(struct intel_encoder *encoder,
 728                                         u8 *pipe_mask, bool *is_dp_mst)
 729 {
 730         struct drm_device *dev = encoder->base.dev;
 731         struct drm_i915_private *dev_priv = to_i915(dev);
 732         enum port port = encoder->port;
 733         intel_wakeref_t wakeref;
 734         enum pipe p;
 735         u32 tmp;
 736         u8 mst_pipe_mask;
 737
 738         *pipe_mask = 0;
 739         *is_dp_mst = false;
 740
 741         wakeref = intel_display_power_get_if_enabled(dev_priv,
 742                                                      encoder->power_domain);
 743         if (!wakeref)
 744                 return;
 745
 746         tmp = intel_de_read(dev_priv, DDI_BUF_CTL(port));
 747         if (!(tmp & DDI_BUF_CTL_ENABLE))
 748                 goto out;
 749
 750         if (HAS_TRANSCODER(dev_priv, TRANSCODER_EDP) && port == PORT_A) {
 751                 tmp = intel_de_read(dev_priv,
 752                                     TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
 753
 754                 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
 755                 default:
 756                         MISSING_CASE(tmp & TRANS_DDI_EDP_INPUT_MASK);
 757                         fallthrough;
 758                 case TRANS_DDI_EDP_INPUT_A_ON:
 759                 case TRANS_DDI_EDP_INPUT_A_ONOFF:
 760                         *pipe_mask = BIT(PIPE_A);
 761                         break;
 762                 case TRANS_DDI_EDP_INPUT_B_ONOFF:
 763                         *pipe_mask = BIT(PIPE_B);
 764                         break;
 765                 case TRANS_DDI_EDP_INPUT_C_ONOFF:
 766                         *pipe_mask = BIT(PIPE_C);
 767                         break;
 768                 }
 769
 770                 goto out;
 771         }
 772
 773         mst_pipe_mask = 0;
 774         for_each_pipe(dev_priv, p) {
 775                 enum transcoder cpu_transcoder = (enum transcoder)p;
 776                 unsigned int port_mask, ddi_select;
 777                 intel_wakeref_t trans_wakeref;
 778
 779                 trans_wakeref = intel_display_power_get_if_enabled(dev_priv,
 780                                                                    POWER_DOMAIN_TRANSCODER(cpu_transcoder));
 781                 if (!trans_wakeref)
 782                         continue;
 783
 784                 if (DISPLAY_VER(dev_priv) >= 12) {
 785                         port_mask = TGL_TRANS_DDI_PORT_MASK;
 786                         ddi_select = TGL_TRANS_DDI_SELECT_PORT(port);
 787                 } else {
 788                         port_mask = TRANS_DDI_PORT_MASK;
 789                         ddi_select = TRANS_DDI_SELECT_PORT(port);
 790                 }
 791
 792                 tmp = intel_de_read(dev_priv,
 793                                     TRANS_DDI_FUNC_CTL(cpu_transcoder));
 794                 intel_display_power_put(dev_priv, POWER_DOMAIN_TRANSCODER(cpu_transcoder),
 795                                         trans_wakeref);
 796
 797                 if ((tmp & port_mask) != ddi_select)
 798                         continue;
 799
 800                 if ((tmp & TRANS_DDI_MODE_SELECT_MASK) == TRANS_DDI_MODE_SELECT_DP_MST ||
 801                     (HAS_DP20(dev_priv) &&
 802                      (tmp & TRANS_DDI_MODE_SELECT_MASK) == TRANS_DDI_MODE_SELECT_FDI_OR_128B132B))
 803                         mst_pipe_mask |= BIT(p);
 804
 805                 *pipe_mask |= BIT(p);
 806         }
 807
 808         if (!*pipe_mask)
 809                 drm_dbg_kms(&dev_priv->drm,
 810                             "No pipe for [ENCODER:%d:%s] found\n",
 811                             encoder->base.base.id, encoder->base.name);
 812
 813         if (!mst_pipe_mask && hweight8(*pipe_mask) > 1) {
 814                 drm_dbg_kms(&dev_priv->drm,
 815                             "Multiple pipes for [ENCODER:%d:%s] (pipe_mask %02x)\n",
 816                             encoder->base.base.id, encoder->base.name,
 817                             *pipe_mask);
 818                 *pipe_mask = BIT(ffs(*pipe_mask) - 1);
 819         }
 820
 821         if (mst_pipe_mask && mst_pipe_mask != *pipe_mask)
 822                 drm_dbg_kms(&dev_priv->drm,
 823                             "Conflicting MST and non-MST state for [ENCODER:%d:%s] (pipe_mask %02x mst_pipe_mask %02x)\n",
 824                             encoder->base.base.id, encoder->base.name,
 825                             *pipe_mask, mst_pipe_mask);
 826         else
 827                 *is_dp_mst = mst_pipe_mask;
 828
 829 out:
 830         if (*pipe_mask && (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv))) {
 831                 tmp = intel_de_read(dev_priv, BXT_PHY_CTL(port));
 832                 if ((tmp & (BXT_PHY_CMNLANE_POWERDOWN_ACK |
 833                             BXT_PHY_LANE_POWERDOWN_ACK |
 834                             BXT_PHY_LANE_ENABLED)) != BXT_PHY_LANE_ENABLED)
 835                         drm_err(&dev_priv->drm,
 836                                 "[ENCODER:%d:%s] enabled but PHY powered down? (PHY_CTL %08x)\n",
 837                                 encoder->base.base.id, encoder->base.name, tmp);
 838         }
 839
 840         intel_display_power_put(dev_priv, encoder->power_domain, wakeref);
 841 }
 842
 843 bool intel_ddi_get_hw_state(struct intel_encoder *encoder,
 844                             enum pipe *pipe)
 845 {
 846         u8 pipe_mask;
 847         bool is_mst;
 848
 849         intel_ddi_get_encoder_pipes(encoder, &pipe_mask, &is_mst);
 850
 851         if (is_mst || !pipe_mask)
 852                 return false;
 853
 854         *pipe = ffs(pipe_mask) - 1;
 855
 856         return true;
 857 }
 858
 859 static enum intel_display_power_domain
 860 intel_ddi_main_link_aux_domain(struct intel_digital_port *dig_port,
 861                                const struct intel_crtc_state *crtc_state)
 862 {
 863         struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
 864         enum phy phy = intel_port_to_phy(i915, dig_port->base.port);
 865
 866         /*
 867          * ICL+ HW requires corresponding AUX IOs to be powered up for PSR with
 868          * DC states enabled at the same time, while for driver initiated AUX
 869          * transfers we need the same AUX IOs to be powered but with DC states
 870          * disabled. Accordingly use the AUX_IO_<port> power domain here which
 871          * leaves DC states enabled.
 872          *
 873          * Before MTL TypeC PHYs (in all TypeC modes and both DP/HDMI) also require
 874          * AUX IO to be enabled, but all these require DC_OFF to be enabled as
 875          * well, so we can acquire a wider AUX_<port> power domain reference
 876          * instead of a specific AUX_IO_<port> reference without powering up any
 877          * extra wells.
 878          */
 879         if (intel_encoder_can_psr(&dig_port->base))
 880                 return intel_display_power_aux_io_domain(i915, dig_port->aux_ch);
 881         else if (DISPLAY_VER(i915) < 14 &&
 882                  (intel_crtc_has_dp_encoder(crtc_state) ||
 883                   intel_phy_is_tc(i915, phy)))
 884                 return intel_aux_power_domain(dig_port);
 885         else
 886                 return POWER_DOMAIN_INVALID;
 887 }
 888
 889 static void
 890 main_link_aux_power_domain_get(struct intel_digital_port *dig_port,
 891                                const struct intel_crtc_state *crtc_state)
 892 {
 893         struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
 894         enum intel_display_power_domain domain =
 895                 intel_ddi_main_link_aux_domain(dig_port, crtc_state);
 896
 897         drm_WARN_ON(&i915->drm, dig_port->aux_wakeref);
 898
 899         if (domain == POWER_DOMAIN_INVALID)
 900                 return;
 901
 902         dig_port->aux_wakeref = intel_display_power_get(i915, domain);
 903 }
 904
 905 static void
 906 main_link_aux_power_domain_put(struct intel_digital_port *dig_port,
 907                                const struct intel_crtc_state *crtc_state)
 908 {
 909         struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
 910         enum intel_display_power_domain domain =
 911                 intel_ddi_main_link_aux_domain(dig_port, crtc_state);
 912         intel_wakeref_t wf;
 913
 914         wf = fetch_and_zero(&dig_port->aux_wakeref);
 915         if (!wf)
 916                 return;
 917
 918         intel_display_power_put(i915, domain, wf);
 919 }
 920
 921 static void intel_ddi_get_power_domains(struct intel_encoder *encoder,
 922                                         struct intel_crtc_state *crtc_state)
 923 {
 924         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 925         struct intel_digital_port *dig_port;
 926
 927         /*
 928          * TODO: Add support for MST encoders. Atm, the following should never
 929          * happen since fake-MST encoders don't set their get_power_domains()
 930          * hook.
 931          */
 932         if (drm_WARN_ON(&dev_priv->drm,
 933                         intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST)))
 934                 return;
 935
 936         dig_port = enc_to_dig_port(encoder);
 937
 938         if (!intel_tc_port_in_tbt_alt_mode(dig_port)) {
 939                 drm_WARN_ON(&dev_priv->drm, dig_port->ddi_io_wakeref);
 940                 dig_port->ddi_io_wakeref = intel_display_power_get(dev_priv,
 941                                                                    dig_port->ddi_io_power_domain);
 942         }
 943
 944         main_link_aux_power_domain_get(dig_port, crtc_state);
 945 }
 946
 947 void intel_ddi_enable_transcoder_clock(struct intel_encoder *encoder,
 948                                        const struct intel_crtc_state *crtc_state)
 949 {
 950         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
 951         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 952         enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
 953         enum phy phy = intel_port_to_phy(dev_priv, encoder->port);
 954         u32 val;
 955
 956         if (cpu_transcoder == TRANSCODER_EDP)
 957                 return;
 958
 959         if (DISPLAY_VER(dev_priv) >= 13)
 960                 val = TGL_TRANS_CLK_SEL_PORT(phy);
 961         else if (DISPLAY_VER(dev_priv) >= 12)
 962                 val = TGL_TRANS_CLK_SEL_PORT(encoder->port);
 963         else
 964                 val = TRANS_CLK_SEL_PORT(encoder->port);
 965
 966         intel_de_write(dev_priv, TRANS_CLK_SEL(cpu_transcoder), val);
 967 }
 968
 969 void intel_ddi_disable_transcoder_clock(const struct intel_crtc_state *crtc_state)
 970 {
 971         struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
 972         enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
 973         u32 val;
 974
 975         if (cpu_transcoder == TRANSCODER_EDP)
 976                 return;
 977
 978         if (DISPLAY_VER(dev_priv) >= 12)
 979                 val = TGL_TRANS_CLK_SEL_DISABLED;
 980         else
 981                 val = TRANS_CLK_SEL_DISABLED;
 982
 983         intel_de_write(dev_priv, TRANS_CLK_SEL(cpu_transcoder), val);
 984 }
 985
 986 static void _skl_ddi_set_iboost(struct drm_i915_private *dev_priv,
 987                                 enum port port, u8 iboost)
 988 {
 989         u32 tmp;
 990
 991         tmp = intel_de_read(dev_priv, DISPIO_CR_TX_BMU_CR0);
 992         tmp &= ~(BALANCE_LEG_MASK(port) | BALANCE_LEG_DISABLE(port));
 993         if (iboost)
 994                 tmp |= iboost << BALANCE_LEG_SHIFT(port);
 995         else
 996                 tmp |= BALANCE_LEG_DISABLE(port);
 997         intel_de_write(dev_priv, DISPIO_CR_TX_BMU_CR0, tmp);
 998 }
 999
1000 static void skl_ddi_set_iboost(struct intel_encoder *encoder,
1001                                const struct intel_crtc_state *crtc_state,
1002                                int level)
1003 {
1004         struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
1005         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1006         u8 iboost;
1007
1008         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
1009                 iboost = intel_bios_hdmi_boost_level(encoder->devdata);
1010         else
1011                 iboost = intel_bios_dp_boost_level(encoder->devdata);
1012
1013         if (iboost == 0) {
1014                 const struct intel_ddi_buf_trans *trans;
1015                 int n_entries;
1016
1017                 trans = encoder->get_buf_trans(encoder, crtc_state, &n_entries);
1018                 if (drm_WARN_ON_ONCE(&dev_priv->drm, !trans))
1019                         return;
1020
1021                 iboost = trans->entries[level].hsw.i_boost;
1022         }
1023
1024         /* Make sure that the requested I_boost is valid */
1025         if (iboost && iboost != 0x1 && iboost != 0x3 && iboost != 0x7) {
1026                 drm_err(&dev_priv->drm, "Invalid I_boost value %u\n", iboost);
1027                 return;
1028         }
1029
1030         _skl_ddi_set_iboost(dev_priv, encoder->port, iboost);
1031
1032         if (encoder->port == PORT_A && dig_port->max_lanes == 4)
1033                 _skl_ddi_set_iboost(dev_priv, PORT_E, iboost);
1034 }
1035
1036 static u8 intel_ddi_dp_voltage_max(struct intel_dp *intel_dp,
1037                                    const struct intel_crtc_state *crtc_state)
1038 {
1039         struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
1040         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1041         int n_entries;
1042
1043         encoder->get_buf_trans(encoder, crtc_state, &n_entries);
1044
1045         if (drm_WARN_ON(&dev_priv->drm, n_entries < 1))
1046                 n_entries = 1;
1047         if (drm_WARN_ON(&dev_priv->drm,
1048                         n_entries > ARRAY_SIZE(index_to_dp_signal_levels)))
1049                 n_entries = ARRAY_SIZE(index_to_dp_signal_levels);
1050
1051         return index_to_dp_signal_levels[n_entries - 1] &
1052                 DP_TRAIN_VOLTAGE_SWING_MASK;
1053 }
1054
1055 /*
1056  * We assume that the full set of pre-emphasis values can be
1057  * used on all DDI platforms. Should that change we need to
1058  * rethink this code.
1059  */
1060 static u8 intel_ddi_dp_preemph_max(struct intel_dp *intel_dp)
1061 {
1062         return DP_TRAIN_PRE_EMPH_LEVEL_3;
1063 }
1064
1065 static u32 icl_combo_phy_loadgen_select(const struct intel_crtc_state *crtc_state,
1066                                         int lane)
1067 {
1068         if (crtc_state->port_clock > 600000)
1069                 return 0;
1070
1071         if (crtc_state->lane_count == 4)
1072                 return lane >= 1 ? LOADGEN_SELECT : 0;
1073         else
1074                 return lane == 1 || lane == 2 ? LOADGEN_SELECT : 0;
1075 }
1076
1077 static void icl_ddi_combo_vswing_program(struct intel_encoder *encoder,
1078                                          const struct intel_crtc_state *crtc_state)
1079 {
1080         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1081         const struct intel_ddi_buf_trans *trans;
1082         enum phy phy = intel_port_to_phy(dev_priv, encoder->port);
1083         int n_entries, ln;
1084         u32 val;
1085
1086         trans = encoder->get_buf_trans(encoder, crtc_state, &n_entries);
1087         if (drm_WARN_ON_ONCE(&dev_priv->drm, !trans))
1088                 return;
1089
1090         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP)) {
1091                 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
1092
1093                 val = EDP4K2K_MODE_OVRD_EN | EDP4K2K_MODE_OVRD_OPTIMIZED;
1094                 intel_dp->hobl_active = is_hobl_buf_trans(trans);
1095                 intel_de_rmw(dev_priv, ICL_PORT_CL_DW10(phy), val,
1096                              intel_dp->hobl_active ? val : 0);
1097         }
1098
1099         /* Set PORT_TX_DW5 */
1100         val = intel_de_read(dev_priv, ICL_PORT_TX_DW5_LN(0, phy));
1101         val &= ~(SCALING_MODE_SEL_MASK | RTERM_SELECT_MASK |
1102                   TAP2_DISABLE | TAP3_DISABLE);
1103         val |= SCALING_MODE_SEL(0x2);
1104         val |= RTERM_SELECT(0x6);
1105         val |= TAP3_DISABLE;
1106         intel_de_write(dev_priv, ICL_PORT_TX_DW5_GRP(phy), val);
1107
1108         /* Program PORT_TX_DW2 */
1109         for (ln = 0; ln < 4; ln++) {
1110                 int level = intel_ddi_level(encoder, crtc_state, ln);
1111
1112                 intel_de_rmw(dev_priv, ICL_PORT_TX_DW2_LN(ln, phy),
1113                              SWING_SEL_UPPER_MASK | SWING_SEL_LOWER_MASK | RCOMP_SCALAR_MASK,
1114                              SWING_SEL_UPPER(trans->entries[level].icl.dw2_swing_sel) |
1115                              SWING_SEL_LOWER(trans->entries[level].icl.dw2_swing_sel) |
1116                              RCOMP_SCALAR(0x98));
1117         }
1118
1119         /* Program PORT_TX_DW4 */
1120         /* We cannot write to GRP. It would overwrite individual loadgen. */
1121         for (ln = 0; ln < 4; ln++) {
1122                 int level = intel_ddi_level(encoder, crtc_state, ln);
1123
1124                 intel_de_rmw(dev_priv, ICL_PORT_TX_DW4_LN(ln, phy),
1125                              POST_CURSOR_1_MASK | POST_CURSOR_2_MASK | CURSOR_COEFF_MASK,
1126                              POST_CURSOR_1(trans->entries[level].icl.dw4_post_cursor_1) |
1127                              POST_CURSOR_2(trans->entries[level].icl.dw4_post_cursor_2) |
1128                              CURSOR_COEFF(trans->entries[level].icl.dw4_cursor_coeff));
1129         }
1130
1131         /* Program PORT_TX_DW7 */
1132         for (ln = 0; ln < 4; ln++) {
1133                 int level = intel_ddi_level(encoder, crtc_state, ln);
1134
1135                 intel_de_rmw(dev_priv, ICL_PORT_TX_DW7_LN(ln, phy),
1136                              N_SCALAR_MASK,
1137                              N_SCALAR(trans->entries[level].icl.dw7_n_scalar));
1138         }
1139 }
1140
1141 static void icl_combo_phy_set_signal_levels(struct intel_encoder *encoder,
1142                                             const struct intel_crtc_state *crtc_state)
1143 {
1144         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1145         enum phy phy = intel_port_to_phy(dev_priv, encoder->port);
1146         u32 val;
1147         int ln;
1148
1149         /*
1150          * 1. If port type is eDP or DP,
1151          * set PORT_PCS_DW1 cmnkeeper_enable to 1b,
1152          * else clear to 0b.
1153          */
1154         val = intel_de_read(dev_priv, ICL_PORT_PCS_DW1_LN(0, phy));
1155         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
1156                 val &= ~COMMON_KEEPER_EN;
1157         else
1158                 val |= COMMON_KEEPER_EN;
1159         intel_de_write(dev_priv, ICL_PORT_PCS_DW1_GRP(phy), val);
1160
1161         /* 2. Program loadgen select */
1162         /*
1163          * Program PORT_TX_DW4 depending on Bit rate and used lanes
1164          * <= 6 GHz and 4 lanes (LN0=0, LN1=1, LN2=1, LN3=1)
1165          * <= 6 GHz and 1,2 lanes (LN0=0, LN1=1, LN2=1, LN3=0)
1166          * > 6 GHz (LN0=0, LN1=0, LN2=0, LN3=0)
1167          */
1168         for (ln = 0; ln < 4; ln++) {
1169                 intel_de_rmw(dev_priv, ICL_PORT_TX_DW4_LN(ln, phy),
1170                              LOADGEN_SELECT,
1171                              icl_combo_phy_loadgen_select(crtc_state, ln));
1172         }
1173
1174         /* 3. Set PORT_CL_DW5 SUS Clock Config to 11b */
1175         intel_de_rmw(dev_priv, ICL_PORT_CL_DW5(phy),
1176                      0, SUS_CLOCK_CONFIG);
1177
1178         /* 4. Clear training enable to change swing values */
1179         val = intel_de_read(dev_priv, ICL_PORT_TX_DW5_LN(0, phy));
1180         val &= ~TX_TRAINING_EN;
1181         intel_de_write(dev_priv, ICL_PORT_TX_DW5_GRP(phy), val);
1182
1183         /* 5. Program swing and de-emphasis */
1184         icl_ddi_combo_vswing_program(encoder, crtc_state);
1185
1186         /* 6. Set training enable to trigger update */
1187         val = intel_de_read(dev_priv, ICL_PORT_TX_DW5_LN(0, phy));
1188         val |= TX_TRAINING_EN;
1189         intel_de_write(dev_priv, ICL_PORT_TX_DW5_GRP(phy), val);
1190 }
1191
1192 static void icl_mg_phy_set_signal_levels(struct intel_encoder *encoder,
1193                                          const struct intel_crtc_state *crtc_state)
1194 {
1195         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1196         enum tc_port tc_port = intel_port_to_tc(dev_priv, encoder->port);
1197         const struct intel_ddi_buf_trans *trans;
1198         int n_entries, ln;
1199
1200         if (intel_tc_port_in_tbt_alt_mode(enc_to_dig_port(encoder)))
1201                 return;
1202
1203         trans = encoder->get_buf_trans(encoder, crtc_state, &n_entries);
1204         if (drm_WARN_ON_ONCE(&dev_priv->drm, !trans))
1205                 return;
1206
1207         for (ln = 0; ln < 2; ln++) {
1208                 intel_de_rmw(dev_priv, MG_TX1_LINK_PARAMS(ln, tc_port),
1209                              CRI_USE_FS32, 0);
1210                 intel_de_rmw(dev_priv, MG_TX2_LINK_PARAMS(ln, tc_port),
1211                              CRI_USE_FS32, 0);
1212         }
1213
1214         /* Program MG_TX_SWINGCTRL with values from vswing table */
1215         for (ln = 0; ln < 2; ln++) {
1216                 int level;
1217
1218                 level = intel_ddi_level(encoder, crtc_state, 2*ln+0);
1219
1220                 intel_de_rmw(dev_priv, MG_TX1_SWINGCTRL(ln, tc_port),
1221                              CRI_TXDEEMPH_OVERRIDE_17_12_MASK,
1222                              CRI_TXDEEMPH_OVERRIDE_17_12(trans->entries[level].mg.cri_txdeemph_override_17_12));
1223
1224                 level = intel_ddi_level(encoder, crtc_state, 2*ln+1);
1225
1226                 intel_de_rmw(dev_priv, MG_TX2_SWINGCTRL(ln, tc_port),
1227                              CRI_TXDEEMPH_OVERRIDE_17_12_MASK,
1228                              CRI_TXDEEMPH_OVERRIDE_17_12(trans->entries[level].mg.cri_txdeemph_override_17_12));
1229         }
1230
1231         /* Program MG_TX_DRVCTRL with values from vswing table */
1232         for (ln = 0; ln < 2; ln++) {
1233                 int level;
1234
1235                 level = intel_ddi_level(encoder, crtc_state, 2*ln+0);
1236
1237                 intel_de_rmw(dev_priv, MG_TX1_DRVCTRL(ln, tc_port),
1238                              CRI_TXDEEMPH_OVERRIDE_11_6_MASK |
1239                              CRI_TXDEEMPH_OVERRIDE_5_0_MASK,
1240                              CRI_TXDEEMPH_OVERRIDE_11_6(trans->entries[level].mg.cri_txdeemph_override_11_6) |
1241                              CRI_TXDEEMPH_OVERRIDE_5_0(trans->entries[level].mg.cri_txdeemph_override_5_0) |
1242                              CRI_TXDEEMPH_OVERRIDE_EN);
1243
1244                 level = intel_ddi_level(encoder, crtc_state, 2*ln+1);
1245
1246                 intel_de_rmw(dev_priv, MG_TX2_DRVCTRL(ln, tc_port),
1247                              CRI_TXDEEMPH_OVERRIDE_11_6_MASK |
1248                              CRI_TXDEEMPH_OVERRIDE_5_0_MASK,
1249                              CRI_TXDEEMPH_OVERRIDE_11_6(trans->entries[level].mg.cri_txdeemph_override_11_6) |
1250                              CRI_TXDEEMPH_OVERRIDE_5_0(trans->entries[level].mg.cri_txdeemph_override_5_0) |
1251                              CRI_TXDEEMPH_OVERRIDE_EN);
1252
1253                 /* FIXME: Program CRI_LOADGEN_SEL after the spec is updated */
1254         }
1255
1256         /*
1257          * Program MG_CLKHUB<LN, port being used> with value from frequency table
1258          * In case of Legacy mode on MG PHY, both TX1 and TX2 enabled so use the
1259          * values from table for which TX1 and TX2 enabled.
1260          */
1261         for (ln = 0; ln < 2; ln++) {
1262                 intel_de_rmw(dev_priv, MG_CLKHUB(ln, tc_port),
1263                              CFG_LOW_RATE_LKREN_EN,
1264                              crtc_state->port_clock < 300000 ? CFG_LOW_RATE_LKREN_EN : 0);
1265         }
1266
1267         /* Program the MG_TX_DCC<LN, port being used> based on the link frequency */
1268         for (ln = 0; ln < 2; ln++) {
1269                 intel_de_rmw(dev_priv, MG_TX1_DCC(ln, tc_port),
1270                              CFG_AMI_CK_DIV_OVERRIDE_VAL_MASK |
1271                              CFG_AMI_CK_DIV_OVERRIDE_EN,
1272                              crtc_state->port_clock > 500000 ?
1273                              CFG_AMI_CK_DIV_OVERRIDE_VAL(1) |
1274                              CFG_AMI_CK_DIV_OVERRIDE_EN : 0);
1275
1276                 intel_de_rmw(dev_priv, MG_TX2_DCC(ln, tc_port),
1277                              CFG_AMI_CK_DIV_OVERRIDE_VAL_MASK |
1278                              CFG_AMI_CK_DIV_OVERRIDE_EN,
1279                              crtc_state->port_clock > 500000 ?
1280                              CFG_AMI_CK_DIV_OVERRIDE_VAL(1) |
1281                              CFG_AMI_CK_DIV_OVERRIDE_EN : 0);
1282         }
1283
1284         /* Program MG_TX_PISO_READLOAD with values from vswing table */
1285         for (ln = 0; ln < 2; ln++) {
1286                 intel_de_rmw(dev_priv, MG_TX1_PISO_READLOAD(ln, tc_port),
1287                              0, CRI_CALCINIT);
1288                 intel_de_rmw(dev_priv, MG_TX2_PISO_READLOAD(ln, tc_port),
1289                              0, CRI_CALCINIT);
1290         }
1291 }
1292
1293 static void tgl_dkl_phy_set_signal_levels(struct intel_encoder *encoder,
1294                                           const struct intel_crtc_state *crtc_state)
1295 {
1296         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1297         enum tc_port tc_port = intel_port_to_tc(dev_priv, encoder->port);
1298         const struct intel_ddi_buf_trans *trans;
1299         int n_entries, ln;
1300
1301         if (intel_tc_port_in_tbt_alt_mode(enc_to_dig_port(encoder)))
1302                 return;
1303
1304         trans = encoder->get_buf_trans(encoder, crtc_state, &n_entries);
1305         if (drm_WARN_ON_ONCE(&dev_priv->drm, !trans))
1306                 return;
1307
1308         for (ln = 0; ln < 2; ln++) {
1309                 int level;
1310
1311                 intel_dkl_phy_write(dev_priv, DKL_TX_PMD_LANE_SUS(tc_port, ln), 0);
1312
1313                 level = intel_ddi_level(encoder, crtc_state, 2*ln+0);
1314
1315                 intel_dkl_phy_rmw(dev_priv, DKL_TX_DPCNTL0(tc_port, ln),
1316                                   DKL_TX_PRESHOOT_COEFF_MASK |
1317                                   DKL_TX_DE_EMPAHSIS_COEFF_MASK |
1318                                   DKL_TX_VSWING_CONTROL_MASK,
1319                                   DKL_TX_PRESHOOT_COEFF(trans->entries[level].dkl.preshoot) |
1320                                   DKL_TX_DE_EMPHASIS_COEFF(trans->entries[level].dkl.de_emphasis) |
1321                                   DKL_TX_VSWING_CONTROL(trans->entries[level].dkl.vswing));
1322
1323                 level = intel_ddi_level(encoder, crtc_state, 2*ln+1);
1324
1325                 intel_dkl_phy_rmw(dev_priv, DKL_TX_DPCNTL1(tc_port, ln),
1326                                   DKL_TX_PRESHOOT_COEFF_MASK |
1327                                   DKL_TX_DE_EMPAHSIS_COEFF_MASK |
1328                                   DKL_TX_VSWING_CONTROL_MASK,
1329                                   DKL_TX_PRESHOOT_COEFF(trans->entries[level].dkl.preshoot) |
1330                                   DKL_TX_DE_EMPHASIS_COEFF(trans->entries[level].dkl.de_emphasis) |
1331                                   DKL_TX_VSWING_CONTROL(trans->entries[level].dkl.vswing));
1332
1333                 intel_dkl_phy_rmw(dev_priv, DKL_TX_DPCNTL2(tc_port, ln),
1334                                   DKL_TX_DP20BITMODE, 0);
1335
1336                 if (IS_ALDERLAKE_P(dev_priv)) {
1337                         u32 val;
1338
1339                         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) {
1340                                 if (ln == 0) {
1341                                         val = DKL_TX_DPCNTL2_CFG_LOADGENSELECT_TX1(0);
1342                                         val |= DKL_TX_DPCNTL2_CFG_LOADGENSELECT_TX2(2);
1343                                 } else {
1344                                         val = DKL_TX_DPCNTL2_CFG_LOADGENSELECT_TX1(3);
1345                                         val |= DKL_TX_DPCNTL2_CFG_LOADGENSELECT_TX2(3);
1346                                 }
1347                         } else {
1348                                 val = DKL_TX_DPCNTL2_CFG_LOADGENSELECT_TX1(0);
1349                                 val |= DKL_TX_DPCNTL2_CFG_LOADGENSELECT_TX2(0);
1350                         }
1351
1352                         intel_dkl_phy_rmw(dev_priv, DKL_TX_DPCNTL2(tc_port, ln),
1353                                           DKL_TX_DPCNTL2_CFG_LOADGENSELECT_TX1_MASK |
1354                                           DKL_TX_DPCNTL2_CFG_LOADGENSELECT_TX2_MASK,
1355                                           val);
1356                 }
1357         }
1358 }
1359
1360 static int translate_signal_level(struct intel_dp *intel_dp,
1361                                   u8 signal_levels)
1362 {
1363         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
1364         int i;
1365
1366         for (i = 0; i < ARRAY_SIZE(index_to_dp_signal_levels); i++) {
1367                 if (index_to_dp_signal_levels[i] == signal_levels)
1368                         return i;
1369         }
1370
1371         drm_WARN(&i915->drm, 1,
1372                  "Unsupported voltage swing/pre-emphasis level: 0x%x\n",
1373                  signal_levels);
1374
1375         return 0;
1376 }
1377
1378 static int intel_ddi_dp_level(struct intel_dp *intel_dp,
1379                               const struct intel_crtc_state *crtc_state,
1380                               int lane)
1381 {
1382         u8 train_set = intel_dp->train_set[lane];
1383
1384         if (intel_dp_is_uhbr(crtc_state)) {
1385                 return train_set & DP_TX_FFE_PRESET_VALUE_MASK;
1386         } else {
1387                 u8 signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
1388                                                 DP_TRAIN_PRE_EMPHASIS_MASK);
1389
1390                 return translate_signal_level(intel_dp, signal_levels);
1391         }
1392 }
1393
1394 int intel_ddi_level(struct intel_encoder *encoder,
1395                     const struct intel_crtc_state *crtc_state,
1396                     int lane)
1397 {
1398         struct drm_i915_private *i915 = to_i915(encoder->base.dev);
1399         const struct intel_ddi_buf_trans *trans;
1400         int level, n_entries;
1401
1402         trans = encoder->get_buf_trans(encoder, crtc_state, &n_entries);
1403         if (drm_WARN_ON_ONCE(&i915->drm, !trans))
1404                 return 0;
1405
1406         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
1407                 level = intel_ddi_hdmi_level(encoder, trans);
1408         else
1409                 level = intel_ddi_dp_level(enc_to_intel_dp(encoder), crtc_state,
1410                                            lane);
1411
1412         if (drm_WARN_ON_ONCE(&i915->drm, level >= n_entries))
1413                 level = n_entries - 1;
1414
1415         return level;
1416 }
1417
1418 static void
1419 hsw_set_signal_levels(struct intel_encoder *encoder,
1420                       const struct intel_crtc_state *crtc_state)
1421 {
1422         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1423         struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
1424         int level = intel_ddi_level(encoder, crtc_state, 0);
1425         enum port port = encoder->port;
1426         u32 signal_levels;
1427
1428         if (has_iboost(dev_priv))
1429                 skl_ddi_set_iboost(encoder, crtc_state, level);
1430
1431         /* HDMI ignores the rest */
1432         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
1433                 return;
1434
1435         signal_levels = DDI_BUF_TRANS_SELECT(level);
1436
1437         drm_dbg_kms(&dev_priv->drm, "Using signal levels %08x\n",
1438                     signal_levels);
1439
1440         intel_dp->DP &= ~DDI_BUF_EMP_MASK;
1441         intel_dp->DP |= signal_levels;
1442
1443         intel_de_write(dev_priv, DDI_BUF_CTL(port), intel_dp->DP);
1444         intel_de_posting_read(dev_priv, DDI_BUF_CTL(port));
1445 }
1446
1447 static void _icl_ddi_enable_clock(struct drm_i915_private *i915, i915_reg_t reg,
1448                                   u32 clk_sel_mask, u32 clk_sel, u32 clk_off)
1449 {
1450         mutex_lock(&i915->display.dpll.lock);
1451
1452         intel_de_rmw(i915, reg, clk_sel_mask, clk_sel);
1453
1454         /*
1455          * "This step and the step before must be
1456          *  done with separate register writes."
1457          */
1458         intel_de_rmw(i915, reg, clk_off, 0);
1459
1460         mutex_unlock(&i915->display.dpll.lock);
1461 }
1462
1463 static void _icl_ddi_disable_clock(struct drm_i915_private *i915, i915_reg_t reg,
1464                                    u32 clk_off)
1465 {
1466         mutex_lock(&i915->display.dpll.lock);
1467
1468         intel_de_rmw(i915, reg, 0, clk_off);
1469
1470         mutex_unlock(&i915->display.dpll.lock);
1471 }
1472
1473 static bool _icl_ddi_is_clock_enabled(struct drm_i915_private *i915, i915_reg_t reg,
1474                                       u32 clk_off)
1475 {
1476         return !(intel_de_read(i915, reg) & clk_off);
1477 }
1478
1479 static struct intel_shared_dpll *
1480 _icl_ddi_get_pll(struct drm_i915_private *i915, i915_reg_t reg,
1481                  u32 clk_sel_mask, u32 clk_sel_shift)
1482 {
1483         enum intel_dpll_id id;
1484
1485         id = (intel_de_read(i915, reg) & clk_sel_mask) >> clk_sel_shift;
1486
1487         return intel_get_shared_dpll_by_id(i915, id);
1488 }
1489
1490 static void adls_ddi_enable_clock(struct intel_encoder *encoder,
1491                                   const struct intel_crtc_state *crtc_state)
1492 {
1493         struct drm_i915_private *i915 = to_i915(encoder->base.dev);
1494         const struct intel_shared_dpll *pll = crtc_state->shared_dpll;
1495         enum phy phy = intel_port_to_phy(i915, encoder->port);
1496
1497         if (drm_WARN_ON(&i915->drm, !pll))
1498                 return;
1499
1500         _icl_ddi_enable_clock(i915, ADLS_DPCLKA_CFGCR(phy),
1501                               ADLS_DPCLKA_CFGCR_DDI_CLK_SEL_MASK(phy),
1502                               pll->info->id << ADLS_DPCLKA_CFGCR_DDI_SHIFT(phy),
1503                               ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy));
1504 }
1505
1506 static void adls_ddi_disable_clock(struct intel_encoder *encoder)
1507 {
1508         struct drm_i915_private *i915 = to_i915(encoder->base.dev);
1509         enum phy phy = intel_port_to_phy(i915, encoder->port);
1510
1511         _icl_ddi_disable_clock(i915, ADLS_DPCLKA_CFGCR(phy),
1512                                ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy));
1513 }
1514
1515 static bool adls_ddi_is_clock_enabled(struct intel_encoder *encoder)
1516 {
1517         struct drm_i915_private *i915 = to_i915(encoder->base.dev);
1518         enum phy phy = intel_port_to_phy(i915, encoder->port);
1519
1520         return _icl_ddi_is_clock_enabled(i915, ADLS_DPCLKA_CFGCR(phy),
1521                                          ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy));
1522 }
1523
1524 static struct intel_shared_dpll *adls_ddi_get_pll(struct intel_encoder *encoder)
1525 {
1526         struct drm_i915_private *i915 = to_i915(encoder->base.dev);
1527         enum phy phy = intel_port_to_phy(i915, encoder->port);
1528
1529         return _icl_ddi_get_pll(i915, ADLS_DPCLKA_CFGCR(phy),
1530                                 ADLS_DPCLKA_CFGCR_DDI_CLK_SEL_MASK(phy),
1531                                 ADLS_DPCLKA_CFGCR_DDI_SHIFT(phy));
1532 }
1533
1534 static void rkl_ddi_enable_clock(struct intel_encoder *encoder,
1535                                  const struct intel_crtc_state *crtc_state)
1536 {
1537         struct drm_i915_private *i915 = to_i915(encoder->base.dev);
1538         const struct intel_shared_dpll *pll = crtc_state->shared_dpll;
1539         enum phy phy = intel_port_to_phy(i915, encoder->port);
1540
1541         if (drm_WARN_ON(&i915->drm, !pll))
1542                 return;
1543
1544         _icl_ddi_enable_clock(i915, ICL_DPCLKA_CFGCR0,
1545                               RKL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy),
1546                               RKL_DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, phy),
1547                               RKL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy));
1548 }
1549
1550 static void rkl_ddi_disable_clock(struct intel_encoder *encoder)
1551 {
1552         struct drm_i915_private *i915 = to_i915(encoder->base.dev);
1553         enum phy phy = intel_port_to_phy(i915, encoder->port);
1554
1555         _icl_ddi_disable_clock(i915, ICL_DPCLKA_CFGCR0,
1556                                RKL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy));
1557 }
1558
1559 static bool rkl_ddi_is_clock_enabled(struct intel_encoder *encoder)
1560 {
1561         struct drm_i915_private *i915 = to_i915(encoder->base.dev);
1562         enum phy phy = intel_port_to_phy(i915, encoder->port);
1563
1564         return _icl_ddi_is_clock_enabled(i915, ICL_DPCLKA_CFGCR0,
1565                                          RKL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy));
1566 }
1567
1568 static struct intel_shared_dpll *rkl_ddi_get_pll(struct intel_encoder *encoder)
1569 {
1570         struct drm_i915_private *i915 = to_i915(encoder->base.dev);
1571         enum phy phy = intel_port_to_phy(i915, encoder->port);
1572
1573         return _icl_ddi_get_pll(i915, ICL_DPCLKA_CFGCR0,
1574                                 RKL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy),
1575                                 RKL_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy));
1576 }
1577
1578 static void dg1_ddi_enable_clock(struct intel_encoder *encoder,
1579                                  const struct intel_crtc_state *crtc_state)
1580 {
1581         struct drm_i915_private *i915 = to_i915(encoder->base.dev);
1582         const struct intel_shared_dpll *pll = crtc_state->shared_dpll;
1583         enum phy phy = intel_port_to_phy(i915, encoder->port);
1584
1585         if (drm_WARN_ON(&i915->drm, !pll))
1586                 return;
1587
1588         /*
1589          * If we fail this, something went very wrong: first 2 PLLs should be
1590          * used by first 2 phys and last 2 PLLs by last phys
1591          */
1592         if (drm_WARN_ON(&i915->drm,
1593                         (pll->info->id < DPLL_ID_DG1_DPLL2 && phy >= PHY_C) ||
1594                         (pll->info->id >= DPLL_ID_DG1_DPLL2 && phy < PHY_C)))
1595                 return;
1596
1597         _icl_ddi_enable_clock(i915, DG1_DPCLKA_CFGCR0(phy),
1598                               DG1_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy),
1599                               DG1_DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, phy),
1600                               DG1_DPCLKA_CFGCR0_DDI_CLK_OFF(phy));
1601 }
1602
1603 static void dg1_ddi_disable_clock(struct intel_encoder *encoder)
1604 {
1605         struct drm_i915_private *i915 = to_i915(encoder->base.dev);
1606         enum phy phy = intel_port_to_phy(i915, encoder->port);
1607
1608         _icl_ddi_disable_clock(i915, DG1_DPCLKA_CFGCR0(phy),
1609                                DG1_DPCLKA_CFGCR0_DDI_CLK_OFF(phy));
1610 }
1611
1612 static bool dg1_ddi_is_clock_enabled(struct intel_encoder *encoder)
1613 {
1614         struct drm_i915_private *i915 = to_i915(encoder->base.dev);
1615         enum phy phy = intel_port_to_phy(i915, encoder->port);
1616
1617         return _icl_ddi_is_clock_enabled(i915, DG1_DPCLKA_CFGCR0(phy),
1618                                          DG1_DPCLKA_CFGCR0_DDI_CLK_OFF(phy));
1619 }
1620
1621 static struct intel_shared_dpll *dg1_ddi_get_pll(struct intel_encoder *encoder)
1622 {
1623         struct drm_i915_private *i915 = to_i915(encoder->base.dev);
1624         enum phy phy = intel_port_to_phy(i915, encoder->port);
1625         enum intel_dpll_id id;
1626         u32 val;
1627
1628         val = intel_de_read(i915, DG1_DPCLKA_CFGCR0(phy));
1629         val &= DG1_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy);
1630         val >>= DG1_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy);
1631         id = val;
1632
1633         /*
1634          * _DG1_DPCLKA0_CFGCR0 maps between DPLL 0 and 1 with one bit for phy A
1635          * and B while _DG1_DPCLKA1_CFGCR0 maps between DPLL 2 and 3 with one
1636          * bit for phy C and D.
1637          */
1638         if (phy >= PHY_C)
1639                 id += DPLL_ID_DG1_DPLL2;
1640
1641         return intel_get_shared_dpll_by_id(i915, id);
1642 }
1643
1644 static void icl_ddi_combo_enable_clock(struct intel_encoder *encoder,
1645                                        const struct intel_crtc_state *crtc_state)
1646 {
1647         struct drm_i915_private *i915 = to_i915(encoder->base.dev);
1648         const struct intel_shared_dpll *pll = crtc_state->shared_dpll;
1649         enum phy phy = intel_port_to_phy(i915, encoder->port);
1650
1651         if (drm_WARN_ON(&i915->drm, !pll))
1652                 return;
1653
1654         _icl_ddi_enable_clock(i915, ICL_DPCLKA_CFGCR0,
1655                               ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy),
1656                               ICL_DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, phy),
1657                               ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy));
1658 }
1659
1660 static void icl_ddi_combo_disable_clock(struct intel_encoder *encoder)
1661 {
1662         struct drm_i915_private *i915 = to_i915(encoder->base.dev);
1663         enum phy phy = intel_port_to_phy(i915, encoder->port);
1664
1665         _icl_ddi_disable_clock(i915, ICL_DPCLKA_CFGCR0,
1666                                ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy));
1667 }
1668
1669 static bool icl_ddi_combo_is_clock_enabled(struct intel_encoder *encoder)
1670 {
1671         struct drm_i915_private *i915 = to_i915(encoder->base.dev);
1672         enum phy phy = intel_port_to_phy(i915, encoder->port);
1673
1674         return _icl_ddi_is_clock_enabled(i915, ICL_DPCLKA_CFGCR0,
1675                                          ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy));
1676 }
1677
1678 struct intel_shared_dpll *icl_ddi_combo_get_pll(struct intel_encoder *encoder)
1679 {
1680         struct drm_i915_private *i915 = to_i915(encoder->base.dev);
1681         enum phy phy = intel_port_to_phy(i915, encoder->port);
1682
1683         return _icl_ddi_get_pll(i915, ICL_DPCLKA_CFGCR0,
1684                                 ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy),
1685                                 ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy));
1686 }
1687
1688 static void jsl_ddi_tc_enable_clock(struct intel_encoder *encoder,
1689                                     const struct intel_crtc_state *crtc_state)
1690 {
1691         struct drm_i915_private *i915 = to_i915(encoder->base.dev);
1692         const struct intel_shared_dpll *pll = crtc_state->shared_dpll;
1693         enum port port = encoder->port;
1694
1695         if (drm_WARN_ON(&i915->drm, !pll))
1696                 return;
1697
1698         /*
1699          * "For DDIC and DDID, program DDI_CLK_SEL to map the MG clock to the port.
1700          *  MG does not exist, but the programming is required to ungate DDIC and DDID."
1701          */
1702         intel_de_write(i915, DDI_CLK_SEL(port), DDI_CLK_SEL_MG);
1703
1704         icl_ddi_combo_enable_clock(encoder, crtc_state);
1705 }
1706
1707 static void jsl_ddi_tc_disable_clock(struct intel_encoder *encoder)
1708 {
1709         struct drm_i915_private *i915 = to_i915(encoder->base.dev);
1710         enum port port = encoder->port;
1711
1712         icl_ddi_combo_disable_clock(encoder);
1713
1714         intel_de_write(i915, DDI_CLK_SEL(port), DDI_CLK_SEL_NONE);
1715 }
1716
1717 static bool jsl_ddi_tc_is_clock_enabled(struct intel_encoder *encoder)
1718 {
1719         struct drm_i915_private *i915 = to_i915(encoder->base.dev);
1720         enum port port = encoder->port;
1721         u32 tmp;
1722
1723         tmp = intel_de_read(i915, DDI_CLK_SEL(port));
1724
1725         if ((tmp & DDI_CLK_SEL_MASK) == DDI_CLK_SEL_NONE)
1726                 return false;
1727
1728         return icl_ddi_combo_is_clock_enabled(encoder);
1729 }
1730
1731 static void icl_ddi_tc_enable_clock(struct intel_encoder *encoder,
1732                                     const struct intel_crtc_state *crtc_state)
1733 {
1734         struct drm_i915_private *i915 = to_i915(encoder->base.dev);
1735         const struct intel_shared_dpll *pll = crtc_state->shared_dpll;
1736         enum tc_port tc_port = intel_port_to_tc(i915, encoder->port);
1737         enum port port = encoder->port;
1738
1739         if (drm_WARN_ON(&i915->drm, !pll))
1740                 return;
1741
1742         intel_de_write(i915, DDI_CLK_SEL(port),
1743                        icl_pll_to_ddi_clk_sel(encoder, crtc_state));
1744
1745         mutex_lock(&i915->display.dpll.lock);
1746
1747         intel_de_rmw(i915, ICL_DPCLKA_CFGCR0,
1748                      ICL_DPCLKA_CFGCR0_TC_CLK_OFF(tc_port), 0);
1749
1750         mutex_unlock(&i915->display.dpll.lock);
1751 }
1752
1753 static void icl_ddi_tc_disable_clock(struct intel_encoder *encoder)
1754 {
1755         struct drm_i915_private *i915 = to_i915(encoder->base.dev);
1756         enum tc_port tc_port = intel_port_to_tc(i915, encoder->port);
1757         enum port port = encoder->port;
1758
1759         mutex_lock(&i915->display.dpll.lock);
1760
1761         intel_de_rmw(i915, ICL_DPCLKA_CFGCR0,
1762                      0, ICL_DPCLKA_CFGCR0_TC_CLK_OFF(tc_port));
1763
1764         mutex_unlock(&i915->display.dpll.lock);
1765
1766         intel_de_write(i915, DDI_CLK_SEL(port), DDI_CLK_SEL_NONE);
1767 }
1768
1769 static bool icl_ddi_tc_is_clock_enabled(struct intel_encoder *encoder)
1770 {
1771         struct drm_i915_private *i915 = to_i915(encoder->base.dev);
1772         enum tc_port tc_port = intel_port_to_tc(i915, encoder->port);
1773         enum port port = encoder->port;
1774         u32 tmp;
1775
1776         tmp = intel_de_read(i915, DDI_CLK_SEL(port));
1777
1778         if ((tmp & DDI_CLK_SEL_MASK) == DDI_CLK_SEL_NONE)
1779                 return false;
1780
1781         tmp = intel_de_read(i915, ICL_DPCLKA_CFGCR0);
1782
1783         return !(tmp & ICL_DPCLKA_CFGCR0_TC_CLK_OFF(tc_port));
1784 }
1785
1786 static struct intel_shared_dpll *icl_ddi_tc_get_pll(struct intel_encoder *encoder)
1787 {
1788         struct drm_i915_private *i915 = to_i915(encoder->base.dev);
1789         enum tc_port tc_port = intel_port_to_tc(i915, encoder->port);
1790         enum port port = encoder->port;
1791         enum intel_dpll_id id;
1792         u32 tmp;
1793
1794         tmp = intel_de_read(i915, DDI_CLK_SEL(port));
1795
1796         switch (tmp & DDI_CLK_SEL_MASK) {
1797         case DDI_CLK_SEL_TBT_162:
1798         case DDI_CLK_SEL_TBT_270:
1799         case DDI_CLK_SEL_TBT_540:
1800         case DDI_CLK_SEL_TBT_810:
1801                 id = DPLL_ID_ICL_TBTPLL;
1802                 break;
1803         case DDI_CLK_SEL_MG:
1804                 id = icl_tc_port_to_pll_id(tc_port);
1805                 break;
1806         default:
1807                 MISSING_CASE(tmp);
1808                 fallthrough;
1809         case DDI_CLK_SEL_NONE:
1810                 return NULL;
1811         }
1812
1813         return intel_get_shared_dpll_by_id(i915, id);
1814 }
1815
1816 static struct intel_shared_dpll *bxt_ddi_get_pll(struct intel_encoder *encoder)
1817 {
1818         struct drm_i915_private *i915 = to_i915(encoder->base.dev);
1819         enum intel_dpll_id id;
1820
1821         switch (encoder->port) {
1822         case PORT_A:
1823                 id = DPLL_ID_SKL_DPLL0;
1824                 break;
1825         case PORT_B:
1826                 id = DPLL_ID_SKL_DPLL1;
1827                 break;
1828         case PORT_C:
1829                 id = DPLL_ID_SKL_DPLL2;
1830                 break;
1831         default:
1832                 MISSING_CASE(encoder->port);
1833                 return NULL;
1834         }
1835
1836         return intel_get_shared_dpll_by_id(i915, id);
1837 }
1838
1839 static void skl_ddi_enable_clock(struct intel_encoder *encoder,
1840                                  const struct intel_crtc_state *crtc_state)
1841 {
1842         struct drm_i915_private *i915 = to_i915(encoder->base.dev);
1843         const struct intel_shared_dpll *pll = crtc_state->shared_dpll;
1844         enum port port = encoder->port;
1845
1846         if (drm_WARN_ON(&i915->drm, !pll))
1847                 return;
1848
1849         mutex_lock(&i915->display.dpll.lock);
1850
1851         intel_de_rmw(i915, DPLL_CTRL2,
1852                      DPLL_CTRL2_DDI_CLK_OFF(port) |
1853                      DPLL_CTRL2_DDI_CLK_SEL_MASK(port),
1854                      DPLL_CTRL2_DDI_CLK_SEL(pll->info->id, port) |
1855                      DPLL_CTRL2_DDI_SEL_OVERRIDE(port));
1856
1857         mutex_unlock(&i915->display.dpll.lock);
1858 }
1859
1860 static void skl_ddi_disable_clock(struct intel_encoder *encoder)
1861 {
1862         struct drm_i915_private *i915 = to_i915(encoder->base.dev);
1863         enum port port = encoder->port;
1864
1865         mutex_lock(&i915->display.dpll.lock);
1866
1867         intel_de_rmw(i915, DPLL_CTRL2,
1868                      0, DPLL_CTRL2_DDI_CLK_OFF(port));
1869
1870         mutex_unlock(&i915->display.dpll.lock);
1871 }
1872
1873 static bool skl_ddi_is_clock_enabled(struct intel_encoder *encoder)
1874 {
1875         struct drm_i915_private *i915 = to_i915(encoder->base.dev);
1876         enum port port = encoder->port;
1877
1878         /*
1879          * FIXME Not sure if the override affects both
1880          * the PLL selection and the CLK_OFF bit.
1881          */
1882         return !(intel_de_read(i915, DPLL_CTRL2) & DPLL_CTRL2_DDI_CLK_OFF(port));
1883 }
1884
1885 static struct intel_shared_dpll *skl_ddi_get_pll(struct intel_encoder *encoder)
1886 {
1887         struct drm_i915_private *i915 = to_i915(encoder->base.dev);
1888         enum port port = encoder->port;
1889         enum intel_dpll_id id;
1890         u32 tmp;
1891
1892         tmp = intel_de_read(i915, DPLL_CTRL2);
1893
1894         /*
1895          * FIXME Not sure if the override affects both
1896          * the PLL selection and the CLK_OFF bit.
1897          */
1898         if ((tmp & DPLL_CTRL2_DDI_SEL_OVERRIDE(port)) == 0)
1899                 return NULL;
1900
1901         id = (tmp & DPLL_CTRL2_DDI_CLK_SEL_MASK(port)) >>
1902                 DPLL_CTRL2_DDI_CLK_SEL_SHIFT(port);
1903
1904         return intel_get_shared_dpll_by_id(i915, id);
1905 }
1906
1907 void hsw_ddi_enable_clock(struct intel_encoder *encoder,
1908                           const struct intel_crtc_state *crtc_state)
1909 {
1910         struct drm_i915_private *i915 = to_i915(encoder->base.dev);
1911         const struct intel_shared_dpll *pll = crtc_state->shared_dpll;
1912         enum port port = encoder->port;
1913
1914         if (drm_WARN_ON(&i915->drm, !pll))
1915                 return;
1916
1917         intel_de_write(i915, PORT_CLK_SEL(port), hsw_pll_to_ddi_pll_sel(pll));
1918 }
1919
1920 void hsw_ddi_disable_clock(struct intel_encoder *encoder)
1921 {
1922         struct drm_i915_private *i915 = to_i915(encoder->base.dev);
1923         enum port port = encoder->port;
1924
1925         intel_de_write(i915, PORT_CLK_SEL(port), PORT_CLK_SEL_NONE);
1926 }
1927
1928 bool hsw_ddi_is_clock_enabled(struct intel_encoder *encoder)
1929 {
1930         struct drm_i915_private *i915 = to_i915(encoder->base.dev);
1931         enum port port = encoder->port;
1932
1933         return intel_de_read(i915, PORT_CLK_SEL(port)) != PORT_CLK_SEL_NONE;
1934 }
1935
1936 static struct intel_shared_dpll *hsw_ddi_get_pll(struct intel_encoder *encoder)
1937 {
1938         struct drm_i915_private *i915 = to_i915(encoder->base.dev);
1939         enum port port = encoder->port;
1940         enum intel_dpll_id id;
1941         u32 tmp;
1942
1943         tmp = intel_de_read(i915, PORT_CLK_SEL(port));
1944
1945         switch (tmp & PORT_CLK_SEL_MASK) {
1946         case PORT_CLK_SEL_WRPLL1:
1947                 id = DPLL_ID_WRPLL1;
1948                 break;
1949         case PORT_CLK_SEL_WRPLL2:
1950                 id = DPLL_ID_WRPLL2;
1951                 break;
1952         case PORT_CLK_SEL_SPLL:
1953                 id = DPLL_ID_SPLL;
1954                 break;
1955         case PORT_CLK_SEL_LCPLL_810:
1956                 id = DPLL_ID_LCPLL_810;
1957                 break;
1958         case PORT_CLK_SEL_LCPLL_1350:
1959                 id = DPLL_ID_LCPLL_1350;
1960                 break;
1961         case PORT_CLK_SEL_LCPLL_2700:
1962                 id = DPLL_ID_LCPLL_2700;
1963                 break;
1964         default:
1965                 MISSING_CASE(tmp);
1966                 fallthrough;
1967         case PORT_CLK_SEL_NONE:
1968                 return NULL;
1969         }
1970
1971         return intel_get_shared_dpll_by_id(i915, id);
1972 }
1973
1974 void intel_ddi_enable_clock(struct intel_encoder *encoder,
1975                             const struct intel_crtc_state *crtc_state)
1976 {
1977         if (encoder->enable_clock)
1978                 encoder->enable_clock(encoder, crtc_state);
1979 }
1980
1981 void intel_ddi_disable_clock(struct intel_encoder *encoder)
1982 {
1983         if (encoder->disable_clock)
1984                 encoder->disable_clock(encoder);
1985 }
1986
1987 void intel_ddi_sanitize_encoder_pll_mapping(struct intel_encoder *encoder)
1988 {
1989         struct drm_i915_private *i915 = to_i915(encoder->base.dev);
1990         u32 port_mask;
1991         bool ddi_clk_needed;
1992
1993         /*
1994          * In case of DP MST, we sanitize the primary encoder only, not the
1995          * virtual ones.
1996          */
1997         if (encoder->type == INTEL_OUTPUT_DP_MST)
1998                 return;
1999
2000         if (!encoder->base.crtc && intel_encoder_is_dp(encoder)) {
2001                 u8 pipe_mask;
2002                 bool is_mst;
2003
2004                 intel_ddi_get_encoder_pipes(encoder, &pipe_mask, &is_mst);
2005                 /*
2006                  * In the unlikely case that BIOS enables DP in MST mode, just
2007                  * warn since our MST HW readout is incomplete.
2008                  */
2009                 if (drm_WARN_ON(&i915->drm, is_mst))
2010                         return;
2011         }
2012
2013         port_mask = BIT(encoder->port);
2014         ddi_clk_needed = encoder->base.crtc;
2015
2016         if (encoder->type == INTEL_OUTPUT_DSI) {
2017                 struct intel_encoder *other_encoder;
2018
2019                 port_mask = intel_dsi_encoder_ports(encoder);
2020                 /*
2021                  * Sanity check that we haven't incorrectly registered another
2022                  * encoder using any of the ports of this DSI encoder.
2023                  */
2024                 for_each_intel_encoder(&i915->drm, other_encoder) {
2025                         if (other_encoder == encoder)
2026                                 continue;
2027
2028                         if (drm_WARN_ON(&i915->drm,
2029                                         port_mask & BIT(other_encoder->port)))
2030                                 return;
2031                 }
2032                 /*
2033                  * For DSI we keep the ddi clocks gated
2034                  * except during enable/disable sequence.
2035                  */
2036                 ddi_clk_needed = false;
2037         }
2038
2039         if (ddi_clk_needed || !encoder->is_clock_enabled ||
2040             !encoder->is_clock_enabled(encoder))
2041                 return;
2042
2043         drm_notice(&i915->drm,
2044                    "[ENCODER:%d:%s] is disabled/in DSI mode with an ungated DDI clock, gate it\n",
2045                    encoder->base.base.id, encoder->base.name);
2046
2047         encoder->disable_clock(encoder);
2048 }
2049
2050 static void
2051 icl_program_mg_dp_mode(struct intel_digital_port *dig_port,
2052                        const struct intel_crtc_state *crtc_state)
2053 {
2054         struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
2055         enum tc_port tc_port = intel_port_to_tc(dev_priv, dig_port->base.port);
2056         enum phy phy = intel_port_to_phy(dev_priv, dig_port->base.port);
2057         u32 ln0, ln1, pin_assignment;
2058         u8 width;
2059
2060         if (!intel_phy_is_tc(dev_priv, phy) ||
2061             intel_tc_port_in_tbt_alt_mode(dig_port))
2062                 return;
2063
2064         if (DISPLAY_VER(dev_priv) >= 12) {
2065                 ln0 = intel_dkl_phy_read(dev_priv, DKL_DP_MODE(tc_port, 0));
2066                 ln1 = intel_dkl_phy_read(dev_priv, DKL_DP_MODE(tc_port, 1));
2067         } else {
2068                 ln0 = intel_de_read(dev_priv, MG_DP_MODE(0, tc_port));
2069                 ln1 = intel_de_read(dev_priv, MG_DP_MODE(1, tc_port));
2070         }
2071
2072         ln0 &= ~(MG_DP_MODE_CFG_DP_X1_MODE | MG_DP_MODE_CFG_DP_X2_MODE);
2073         ln1 &= ~(MG_DP_MODE_CFG_DP_X1_MODE | MG_DP_MODE_CFG_DP_X2_MODE);
2074
2075         /* DPPATC */
2076         pin_assignment = intel_tc_port_get_pin_assignment_mask(dig_port);
2077         width = crtc_state->lane_count;
2078
2079         switch (pin_assignment) {
2080         case 0x0:
2081                 drm_WARN_ON(&dev_priv->drm,
2082                             !intel_tc_port_in_legacy_mode(dig_port));
2083                 if (width == 1) {
2084                         ln1 |= MG_DP_MODE_CFG_DP_X1_MODE;
2085                 } else {
2086                         ln0 |= MG_DP_MODE_CFG_DP_X2_MODE;
2087                         ln1 |= MG_DP_MODE_CFG_DP_X2_MODE;
2088                 }
2089                 break;
2090         case 0x1:
2091                 if (width == 4) {
2092                         ln0 |= MG_DP_MODE_CFG_DP_X2_MODE;
2093                         ln1 |= MG_DP_MODE_CFG_DP_X2_MODE;
2094                 }
2095                 break;
2096         case 0x2:
2097                 if (width == 2) {
2098                         ln0 |= MG_DP_MODE_CFG_DP_X2_MODE;
2099                         ln1 |= MG_DP_MODE_CFG_DP_X2_MODE;
2100                 }
2101                 break;
2102         case 0x3:
2103         case 0x5:
2104                 if (width == 1) {
2105                         ln0 |= MG_DP_MODE_CFG_DP_X1_MODE;
2106                         ln1 |= MG_DP_MODE_CFG_DP_X1_MODE;
2107                 } else {
2108                         ln0 |= MG_DP_MODE_CFG_DP_X2_MODE;
2109                         ln1 |= MG_DP_MODE_CFG_DP_X2_MODE;
2110                 }
2111                 break;
2112         case 0x4:
2113         case 0x6:
2114                 if (width == 1) {
2115                         ln0 |= MG_DP_MODE_CFG_DP_X1_MODE;
2116                         ln1 |= MG_DP_MODE_CFG_DP_X1_MODE;
2117                 } else {
2118                         ln0 |= MG_DP_MODE_CFG_DP_X2_MODE;
2119                         ln1 |= MG_DP_MODE_CFG_DP_X2_MODE;
2120                 }
2121                 break;
2122         default:
2123                 MISSING_CASE(pin_assignment);
2124         }
2125
2126         if (DISPLAY_VER(dev_priv) >= 12) {
2127                 intel_dkl_phy_write(dev_priv, DKL_DP_MODE(tc_port, 0), ln0);
2128                 intel_dkl_phy_write(dev_priv, DKL_DP_MODE(tc_port, 1), ln1);
2129         } else {
2130                 intel_de_write(dev_priv, MG_DP_MODE(0, tc_port), ln0);
2131                 intel_de_write(dev_priv, MG_DP_MODE(1, tc_port), ln1);
2132         }
2133 }
2134
2135 static enum transcoder
2136 tgl_dp_tp_transcoder(const struct intel_crtc_state *crtc_state)
2137 {
2138         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST))
2139                 return crtc_state->mst_master_transcoder;
2140         else
2141                 return crtc_state->cpu_transcoder;
2142 }
2143
2144 i915_reg_t dp_tp_ctl_reg(struct intel_encoder *encoder,
2145                          const struct intel_crtc_state *crtc_state)
2146 {
2147         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2148
2149         if (DISPLAY_VER(dev_priv) >= 12)
2150                 return TGL_DP_TP_CTL(tgl_dp_tp_transcoder(crtc_state));
2151         else
2152                 return DP_TP_CTL(encoder->port);
2153 }
2154
2155 i915_reg_t dp_tp_status_reg(struct intel_encoder *encoder,
2156                             const struct intel_crtc_state *crtc_state)
2157 {
2158         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2159
2160         if (DISPLAY_VER(dev_priv) >= 12)
2161                 return TGL_DP_TP_STATUS(tgl_dp_tp_transcoder(crtc_state));
2162         else
2163                 return DP_TP_STATUS(encoder->port);
2164 }
2165
2166 static void intel_dp_sink_set_msa_timing_par_ignore_state(struct intel_dp *intel_dp,
2167                                                           const struct intel_crtc_state *crtc_state,
2168                                                           bool enable)
2169 {
2170         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
2171
2172         if (!crtc_state->vrr.enable)
2173                 return;
2174
2175         if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_DOWNSPREAD_CTRL,
2176                                enable ? DP_MSA_TIMING_PAR_IGNORE_EN : 0) <= 0)
2177                 drm_dbg_kms(&i915->drm,
2178                             "Failed to %s MSA_TIMING_PAR_IGNORE in the sink\n",
2179                             str_enable_disable(enable));
2180 }
2181
2182 static void intel_dp_sink_set_fec_ready(struct intel_dp *intel_dp,
2183                                         const struct intel_crtc_state *crtc_state)
2184 {
2185         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
2186
2187         if (!crtc_state->fec_enable)
2188                 return;
2189
2190         if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_FEC_CONFIGURATION, DP_FEC_READY) <= 0)
2191                 drm_dbg_kms(&i915->drm,
2192                             "Failed to set FEC_READY in the sink\n");
2193 }
2194
2195 static void intel_ddi_enable_fec(struct intel_encoder *encoder,
2196                                  const struct intel_crtc_state *crtc_state)
2197 {
2198         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2199         struct intel_dp *intel_dp;
2200
2201         if (!crtc_state->fec_enable)
2202                 return;
2203
2204         intel_dp = enc_to_intel_dp(encoder);
2205         intel_de_rmw(dev_priv, dp_tp_ctl_reg(encoder, crtc_state),
2206                      0, DP_TP_CTL_FEC_ENABLE);
2207 }
2208
2209 static void intel_ddi_disable_fec_state(struct intel_encoder *encoder,
2210                                         const struct intel_crtc_state *crtc_state)
2211 {
2212         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2213         struct intel_dp *intel_dp;
2214
2215         if (!crtc_state->fec_enable)
2216                 return;
2217
2218         intel_dp = enc_to_intel_dp(encoder);
2219         intel_de_rmw(dev_priv, dp_tp_ctl_reg(encoder, crtc_state),
2220                      DP_TP_CTL_FEC_ENABLE, 0);
2221         intel_de_posting_read(dev_priv, dp_tp_ctl_reg(encoder, crtc_state));
2222 }
2223
2224 static void intel_ddi_power_up_lanes(struct intel_encoder *encoder,
2225                                      const struct intel_crtc_state *crtc_state)
2226 {
2227         struct drm_i915_private *i915 = to_i915(encoder->base.dev);
2228         struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
2229         enum phy phy = intel_port_to_phy(i915, encoder->port);
2230
2231         if (intel_phy_is_combo(i915, phy)) {
2232                 bool lane_reversal =
2233                         dig_port->saved_port_bits & DDI_BUF_PORT_REVERSAL;
2234
2235                 intel_combo_phy_power_up_lanes(i915, phy, false,
2236                                                crtc_state->lane_count,
2237                                                lane_reversal);
2238         }
2239 }
2240
2241 /* Splitter enable for eDP MSO is limited to certain pipes. */
2242 static u8 intel_ddi_splitter_pipe_mask(struct drm_i915_private *i915)
2243 {
2244         if (IS_ALDERLAKE_P(i915))
2245                 return BIT(PIPE_A) | BIT(PIPE_B);
2246         else
2247                 return BIT(PIPE_A);
2248 }
2249
2250 static void intel_ddi_mso_get_config(struct intel_encoder *encoder,
2251                                      struct intel_crtc_state *pipe_config)
2252 {
2253         struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);
2254         struct drm_i915_private *i915 = to_i915(crtc->base.dev);
2255         enum pipe pipe = crtc->pipe;
2256         u32 dss1;
2257
2258         if (!HAS_MSO(i915))
2259                 return;
2260
2261         dss1 = intel_de_read(i915, ICL_PIPE_DSS_CTL1(pipe));
2262
2263         pipe_config->splitter.enable = dss1 & SPLITTER_ENABLE;
2264         if (!pipe_config->splitter.enable)
2265                 return;
2266
2267         if (drm_WARN_ON(&i915->drm, !(intel_ddi_splitter_pipe_mask(i915) & BIT(pipe)))) {
2268                 pipe_config->splitter.enable = false;
2269                 return;
2270         }
2271
2272         switch (dss1 & SPLITTER_CONFIGURATION_MASK) {
2273         default:
2274                 drm_WARN(&i915->drm, true,
2275                          "Invalid splitter configuration, dss1=0x%08x\n", dss1);
2276                 fallthrough;
2277         case SPLITTER_CONFIGURATION_2_SEGMENT:
2278                 pipe_config->splitter.link_count = 2;
2279                 break;
2280         case SPLITTER_CONFIGURATION_4_SEGMENT:
2281                 pipe_config->splitter.link_count = 4;
2282                 break;
2283         }
2284
2285         pipe_config->splitter.pixel_overlap = REG_FIELD_GET(OVERLAP_PIXELS_MASK, dss1);
2286 }
2287
2288 static void intel_ddi_mso_configure(const struct intel_crtc_state *crtc_state)
2289 {
2290         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
2291         struct drm_i915_private *i915 = to_i915(crtc->base.dev);
2292         enum pipe pipe = crtc->pipe;
2293         u32 dss1 = 0;
2294
2295         if (!HAS_MSO(i915))
2296                 return;
2297
2298         if (crtc_state->splitter.enable) {
2299                 dss1 |= SPLITTER_ENABLE;
2300                 dss1 |= OVERLAP_PIXELS(crtc_state->splitter.pixel_overlap);
2301                 if (crtc_state->splitter.link_count == 2)
2302                         dss1 |= SPLITTER_CONFIGURATION_2_SEGMENT;
2303                 else
2304                         dss1 |= SPLITTER_CONFIGURATION_4_SEGMENT;
2305         }
2306
2307         intel_de_rmw(i915, ICL_PIPE_DSS_CTL1(pipe),
2308                      SPLITTER_ENABLE | SPLITTER_CONFIGURATION_MASK |
2309                      OVERLAP_PIXELS_MASK, dss1);
2310 }
2311
2312 static void tgl_ddi_pre_enable_dp(struct intel_atomic_state *state,
2313                                   struct intel_encoder *encoder,
2314                                   const struct intel_crtc_state *crtc_state,
2315                                   const struct drm_connector_state *conn_state)
2316 {
2317         struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
2318         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2319         struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
2320         bool is_mst = intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST);
2321
2322         intel_dp_set_link_params(intel_dp,
2323                                  crtc_state->port_clock,
2324                                  crtc_state->lane_count);
2325
2326         /*
2327          * We only configure what the register value will be here.  Actual
2328          * enabling happens during link training farther down.
2329          */
2330         intel_ddi_init_dp_buf_reg(encoder, crtc_state);
2331
2332         /*
2333          * 1. Enable Power Wells
2334          *
2335          * This was handled at the beginning of intel_atomic_commit_tail(),
2336          * before we called down into this function.
2337          */
2338
2339         /* 2. Enable Panel Power if PPS is required */
2340         intel_pps_on(intel_dp);
2341
2342         /*
2343          * 3. For non-TBT Type-C ports, set FIA lane count
2344          * (DFLEXDPSP.DPX4TXLATC)
2345          *
2346          * This was done before tgl_ddi_pre_enable_dp by
2347          * hsw_crtc_enable()->intel_encoders_pre_pll_enable().
2348          */
2349
2350         /*
2351          * 4. Enable the port PLL.
2352          *
2353          * The PLL enabling itself was already done before this function by
2354          * hsw_crtc_enable()->intel_enable_shared_dpll().  We need only
2355          * configure the PLL to port mapping here.
2356          */
2357         intel_ddi_enable_clock(encoder, crtc_state);
2358
2359         /* 5. If IO power is controlled through PWR_WELL_CTL, Enable IO Power */
2360         if (!intel_tc_port_in_tbt_alt_mode(dig_port)) {
2361                 drm_WARN_ON(&dev_priv->drm, dig_port->ddi_io_wakeref);
2362                 dig_port->ddi_io_wakeref = intel_display_power_get(dev_priv,
2363                                                                    dig_port->ddi_io_power_domain);
2364         }
2365
2366         /* 6. Program DP_MODE */
2367         icl_program_mg_dp_mode(dig_port, crtc_state);
2368
2369         /*
2370          * 7. The rest of the below are substeps under the bspec's "Enable and
2371          * Train Display Port" step.  Note that steps that are specific to
2372          * MST will be handled by intel_mst_pre_enable_dp() before/after it
2373          * calls into this function.  Also intel_mst_pre_enable_dp() only calls
2374          * us when active_mst_links==0, so any steps designated for "single
2375          * stream or multi-stream master transcoder" can just be performed
2376          * unconditionally here.
2377          */
2378
2379         /*
2380          * 7.a Configure Transcoder Clock Select to direct the Port clock to the
2381          * Transcoder.
2382          */
2383         intel_ddi_enable_transcoder_clock(encoder, crtc_state);
2384
2385         if (HAS_DP20(dev_priv))
2386                 intel_ddi_config_transcoder_dp2(encoder, crtc_state);
2387
2388         /*
2389          * 7.b Configure TRANS_DDI_FUNC_CTL DDI Select, DDI Mode Select & MST
2390          * Transport Select
2391          */
2392         intel_ddi_config_transcoder_func(encoder, crtc_state);
2393
2394         /*
2395          * 7.c Configure & enable DP_TP_CTL with link training pattern 1
2396          * selected
2397          *
2398          * This will be handled by the intel_dp_start_link_train() farther
2399          * down this function.
2400          */
2401
2402         /* 7.e Configure voltage swing and related IO settings */
2403         encoder->set_signal_levels(encoder, crtc_state);
2404
2405         /*
2406          * 7.f Combo PHY: Configure PORT_CL_DW10 Static Power Down to power up
2407          * the used lanes of the DDI.
2408          */
2409         intel_ddi_power_up_lanes(encoder, crtc_state);
2410
2411         /*
2412          * 7.g Program CoG/MSO configuration bits in DSS_CTL1 if selected.
2413          */
2414         intel_ddi_mso_configure(crtc_state);
2415
2416         if (!is_mst)
2417                 intel_dp_set_power(intel_dp, DP_SET_POWER_D0);
2418
2419         intel_dp_configure_protocol_converter(intel_dp, crtc_state);
2420         intel_dp_sink_set_decompression_state(intel_dp, crtc_state, true);
2421         /*
2422          * DDI FEC: "anticipates enabling FEC encoding sets the FEC_READY bit
2423          * in the FEC_CONFIGURATION register to 1 before initiating link
2424          * training
2425          */
2426         intel_dp_sink_set_fec_ready(intel_dp, crtc_state);
2427
2428         intel_dp_check_frl_training(intel_dp);
2429         intel_dp_pcon_dsc_configure(intel_dp, crtc_state);
2430
2431         /*
2432          * 7.i Follow DisplayPort specification training sequence (see notes for
2433          *     failure handling)
2434          * 7.j If DisplayPort multi-stream - Set DP_TP_CTL link training to Idle
2435          *     Pattern, wait for 5 idle patterns (DP_TP_STATUS Min_Idles_Sent)
2436          *     (timeout after 800 us)
2437          */
2438         intel_dp_start_link_train(intel_dp, crtc_state);
2439
2440         /* 7.k Set DP_TP_CTL link training to Normal */
2441         if (!is_trans_port_sync_mode(crtc_state))
2442                 intel_dp_stop_link_train(intel_dp, crtc_state);
2443
2444         /* 7.l Configure and enable FEC if needed */
2445         intel_ddi_enable_fec(encoder, crtc_state);
2446
2447         intel_dsc_dp_pps_write(encoder, crtc_state);
2448 }
2449
2450 static void hsw_ddi_pre_enable_dp(struct intel_atomic_state *state,
2451                                   struct intel_encoder *encoder,
2452                                   const struct intel_crtc_state *crtc_state,
2453                                   const struct drm_connector_state *conn_state)
2454 {
2455         struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
2456         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2457         enum port port = encoder->port;
2458         struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
2459         bool is_mst = intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST);
2460
2461         if (DISPLAY_VER(dev_priv) < 11)
2462                 drm_WARN_ON(&dev_priv->drm,
2463                             is_mst && (port == PORT_A || port == PORT_E));
2464         else
2465                 drm_WARN_ON(&dev_priv->drm, is_mst && port == PORT_A);
2466
2467         intel_dp_set_link_params(intel_dp,
2468                                  crtc_state->port_clock,
2469                                  crtc_state->lane_count);
2470
2471         /*
2472          * We only configure what the register value will be here.  Actual
2473          * enabling happens during link training farther down.
2474          */
2475         intel_ddi_init_dp_buf_reg(encoder, crtc_state);
2476
2477         intel_pps_on(intel_dp);
2478
2479         intel_ddi_enable_clock(encoder, crtc_state);
2480
2481         if (!intel_tc_port_in_tbt_alt_mode(dig_port)) {
2482                 drm_WARN_ON(&dev_priv->drm, dig_port->ddi_io_wakeref);
2483                 dig_port->ddi_io_wakeref = intel_display_power_get(dev_priv,
2484                                                                    dig_port->ddi_io_power_domain);
2485         }
2486
2487         icl_program_mg_dp_mode(dig_port, crtc_state);
2488
2489         if (has_buf_trans_select(dev_priv))
2490                 hsw_prepare_dp_ddi_buffers(encoder, crtc_state);
2491
2492         encoder->set_signal_levels(encoder, crtc_state);
2493
2494         intel_ddi_power_up_lanes(encoder, crtc_state);
2495
2496         if (!is_mst)
2497                 intel_dp_set_power(intel_dp, DP_SET_POWER_D0);
2498         intel_dp_configure_protocol_converter(intel_dp, crtc_state);
2499         intel_dp_sink_set_decompression_state(intel_dp, crtc_state,
2500                                               true);
2501         intel_dp_sink_set_fec_ready(intel_dp, crtc_state);
2502         intel_dp_start_link_train(intel_dp, crtc_state);
2503         if ((port != PORT_A || DISPLAY_VER(dev_priv) >= 9) &&
2504             !is_trans_port_sync_mode(crtc_state))
2505                 intel_dp_stop_link_train(intel_dp, crtc_state);
2506
2507         intel_ddi_enable_fec(encoder, crtc_state);
2508
2509         if (!is_mst)
2510                 intel_ddi_enable_transcoder_clock(encoder, crtc_state);
2511
2512         intel_dsc_dp_pps_write(encoder, crtc_state);
2513 }
2514
2515 static void intel_ddi_pre_enable_dp(struct intel_atomic_state *state,
2516                                     struct intel_encoder *encoder,
2517                                     const struct intel_crtc_state *crtc_state,
2518                                     const struct drm_connector_state *conn_state)
2519 {
2520         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2521
2522         if (HAS_DP20(dev_priv))
2523                 intel_dp_128b132b_sdp_crc16(enc_to_intel_dp(encoder),
2524                                             crtc_state);
2525
2526         if (DISPLAY_VER(dev_priv) >= 12)
2527                 tgl_ddi_pre_enable_dp(state, encoder, crtc_state, conn_state);
2528         else
2529                 hsw_ddi_pre_enable_dp(state, encoder, crtc_state, conn_state);
2530
2531         /* MST will call a setting of MSA after an allocating of Virtual Channel
2532          * from MST encoder pre_enable callback.
2533          */
2534         if (!intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST))
2535                 intel_ddi_set_dp_msa(crtc_state, conn_state);
2536 }
2537
2538 static void intel_ddi_pre_enable_hdmi(struct intel_atomic_state *state,
2539                                       struct intel_encoder *encoder,
2540                                       const struct intel_crtc_state *crtc_state,
2541                                       const struct drm_connector_state *conn_state)
2542 {
2543         struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
2544         struct intel_hdmi *intel_hdmi = &dig_port->hdmi;
2545         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2546
2547         intel_dp_dual_mode_set_tmds_output(intel_hdmi, true);
2548         intel_ddi_enable_clock(encoder, crtc_state);
2549
2550         drm_WARN_ON(&dev_priv->drm, dig_port->ddi_io_wakeref);
2551         dig_port->ddi_io_wakeref = intel_display_power_get(dev_priv,
2552                                                            dig_port->ddi_io_power_domain);
2553
2554         icl_program_mg_dp_mode(dig_port, crtc_state);
2555
2556         intel_ddi_enable_transcoder_clock(encoder, crtc_state);
2557
2558         dig_port->set_infoframes(encoder,
2559                                  crtc_state->has_infoframe,
2560                                  crtc_state, conn_state);
2561 }
2562
2563 static void intel_ddi_pre_enable(struct intel_atomic_state *state,
2564                                  struct intel_encoder *encoder,
2565                                  const struct intel_crtc_state *crtc_state,
2566                                  const struct drm_connector_state *conn_state)
2567 {
2568         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
2569         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
2570         enum pipe pipe = crtc->pipe;
2571
2572         /*
2573          * When called from DP MST code:
2574          * - conn_state will be NULL
2575          * - encoder will be the main encoder (ie. mst->primary)
2576          * - the main connector associated with this port
2577          *   won't be active or linked to a crtc
2578          * - crtc_state will be the state of the first stream to
2579          *   be activated on this port, and it may not be the same
2580          *   stream that will be deactivated last, but each stream
2581          *   should have a state that is identical when it comes to
2582          *   the DP link parameteres
2583          */
2584
2585         drm_WARN_ON(&dev_priv->drm, crtc_state->has_pch_encoder);
2586
2587         intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
2588
2589         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) {
2590                 intel_ddi_pre_enable_hdmi(state, encoder, crtc_state,
2591                                           conn_state);
2592         } else {
2593                 struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
2594
2595                 intel_ddi_pre_enable_dp(state, encoder, crtc_state,
2596                                         conn_state);
2597
2598                 /* FIXME precompute everything properly */
2599                 /* FIXME how do we turn infoframes off again? */
2600                 if (dig_port->lspcon.active && dig_port->dp.has_hdmi_sink)
2601                         dig_port->set_infoframes(encoder,
2602                                                  crtc_state->has_infoframe,
2603                                                  crtc_state, conn_state);
2604         }
2605 }
2606
2607 static void intel_disable_ddi_buf(struct intel_encoder *encoder,
2608                                   const struct intel_crtc_state *crtc_state)
2609 {
2610         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2611         enum port port = encoder->port;
2612         bool wait = false;
2613         u32 val;
2614
2615         val = intel_de_read(dev_priv, DDI_BUF_CTL(port));
2616         if (val & DDI_BUF_CTL_ENABLE) {
2617                 val &= ~DDI_BUF_CTL_ENABLE;
2618                 intel_de_write(dev_priv, DDI_BUF_CTL(port), val);
2619                 wait = true;
2620         }
2621
2622         if (intel_crtc_has_dp_encoder(crtc_state))
2623                 intel_de_rmw(dev_priv, dp_tp_ctl_reg(encoder, crtc_state),
2624                              DP_TP_CTL_ENABLE, 0);
2625
2626         /* Disable FEC in DP Sink */
2627         intel_ddi_disable_fec_state(encoder, crtc_state);
2628
2629         if (wait)
2630                 intel_wait_ddi_buf_idle(dev_priv, port);
2631 }
2632
2633 static void intel_ddi_post_disable_dp(struct intel_atomic_state *state,
2634                                       struct intel_encoder *encoder,
2635                                       const struct intel_crtc_state *old_crtc_state,
2636                                       const struct drm_connector_state *old_conn_state)
2637 {
2638         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2639         struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
2640         struct intel_dp *intel_dp = &dig_port->dp;
2641         bool is_mst = intel_crtc_has_type(old_crtc_state,
2642                                           INTEL_OUTPUT_DP_MST);
2643
2644         if (!is_mst)
2645                 intel_dp_set_infoframes(encoder, false,
2646                                         old_crtc_state, old_conn_state);
2647
2648         /*
2649          * Power down sink before disabling the port, otherwise we end
2650          * up getting interrupts from the sink on detecting link loss.
2651          */
2652         intel_dp_set_power(intel_dp, DP_SET_POWER_D3);
2653
2654         if (DISPLAY_VER(dev_priv) >= 12) {
2655                 if (is_mst) {
2656                         enum transcoder cpu_transcoder = old_crtc_state->cpu_transcoder;
2657
2658                         intel_de_rmw(dev_priv, TRANS_DDI_FUNC_CTL(cpu_transcoder),
2659                                      TGL_TRANS_DDI_PORT_MASK | TRANS_DDI_MODE_SELECT_MASK,
2660                                      0);
2661                 }
2662         } else {
2663                 if (!is_mst)
2664                         intel_ddi_disable_transcoder_clock(old_crtc_state);
2665         }
2666
2667         intel_disable_ddi_buf(encoder, old_crtc_state);
2668
2669         /*
2670          * From TGL spec: "If single stream or multi-stream master transcoder:
2671          * Configure Transcoder Clock select to direct no clock to the
2672          * transcoder"
2673          */
2674         if (DISPLAY_VER(dev_priv) >= 12)
2675                 intel_ddi_disable_transcoder_clock(old_crtc_state);
2676
2677         intel_pps_vdd_on(intel_dp);
2678         intel_pps_off(intel_dp);
2679
2680         if (!intel_tc_port_in_tbt_alt_mode(dig_port))
2681                 intel_display_power_put(dev_priv,
2682                                         dig_port->ddi_io_power_domain,
2683                                         fetch_and_zero(&dig_port->ddi_io_wakeref));
2684
2685         intel_ddi_disable_clock(encoder);
2686 }
2687
2688 static void intel_ddi_post_disable_hdmi(struct intel_atomic_state *state,
2689                                         struct intel_encoder *encoder,
2690                                         const struct intel_crtc_state *old_crtc_state,
2691                                         const struct drm_connector_state *old_conn_state)
2692 {
2693         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2694         struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
2695         struct intel_hdmi *intel_hdmi = &dig_port->hdmi;
2696
2697         dig_port->set_infoframes(encoder, false,
2698                                  old_crtc_state, old_conn_state);
2699
2700         if (DISPLAY_VER(dev_priv) < 12)
2701                 intel_ddi_disable_transcoder_clock(old_crtc_state);
2702
2703         intel_disable_ddi_buf(encoder, old_crtc_state);
2704
2705         if (DISPLAY_VER(dev_priv) >= 12)
2706                 intel_ddi_disable_transcoder_clock(old_crtc_state);
2707
2708         intel_display_power_put(dev_priv,
2709                                 dig_port->ddi_io_power_domain,
2710                                 fetch_and_zero(&dig_port->ddi_io_wakeref));
2711
2712         intel_ddi_disable_clock(encoder);
2713
2714         intel_dp_dual_mode_set_tmds_output(intel_hdmi, false);
2715 }
2716
2717 static void intel_ddi_post_disable(struct intel_atomic_state *state,
2718                                    struct intel_encoder *encoder,
2719                                    const struct intel_crtc_state *old_crtc_state,
2720                                    const struct drm_connector_state *old_conn_state)
2721 {
2722         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2723         struct intel_crtc *slave_crtc;
2724
2725         if (!intel_crtc_has_type(old_crtc_state, INTEL_OUTPUT_DP_MST)) {
2726                 intel_crtc_vblank_off(old_crtc_state);
2727
2728                 intel_vrr_disable(old_crtc_state);
2729
2730                 intel_disable_transcoder(old_crtc_state);
2731
2732                 intel_ddi_disable_transcoder_func(old_crtc_state);
2733
2734                 intel_dsc_disable(old_crtc_state);
2735
2736                 if (DISPLAY_VER(dev_priv) >= 9)
2737                         skl_scaler_disable(old_crtc_state);
2738                 else
2739                         ilk_pfit_disable(old_crtc_state);
2740         }
2741
2742         for_each_intel_crtc_in_pipe_mask(&dev_priv->drm, slave_crtc,
2743                                          intel_crtc_bigjoiner_slave_pipes(old_crtc_state)) {
2744                 const struct intel_crtc_state *old_slave_crtc_state =
2745                         intel_atomic_get_old_crtc_state(state, slave_crtc);
2746
2747                 intel_crtc_vblank_off(old_slave_crtc_state);
2748
2749                 intel_dsc_disable(old_slave_crtc_state);
2750                 skl_scaler_disable(old_slave_crtc_state);
2751         }
2752
2753         /*
2754          * When called from DP MST code:
2755          * - old_conn_state will be NULL
2756          * - encoder will be the main encoder (ie. mst->primary)
2757          * - the main connector associated with this port
2758          *   won't be active or linked to a crtc
2759          * - old_crtc_state will be the state of the last stream to
2760          *   be deactivated on this port, and it may not be the same
2761          *   stream that was activated last, but each stream
2762          *   should have a state that is identical when it comes to
2763          *   the DP link parameteres
2764          */
2765
2766         if (intel_crtc_has_type(old_crtc_state, INTEL_OUTPUT_HDMI))
2767                 intel_ddi_post_disable_hdmi(state, encoder, old_crtc_state,
2768                                             old_conn_state);
2769         else
2770                 intel_ddi_post_disable_dp(state, encoder, old_crtc_state,
2771                                           old_conn_state);
2772 }
2773
2774 static void intel_ddi_post_pll_disable(struct intel_atomic_state *state,
2775                                        struct intel_encoder *encoder,
2776                                        const struct intel_crtc_state *old_crtc_state,
2777                                        const struct drm_connector_state *old_conn_state)
2778 {
2779         struct drm_i915_private *i915 = to_i915(encoder->base.dev);
2780         struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
2781         enum phy phy = intel_port_to_phy(i915, encoder->port);
2782         bool is_tc_port = intel_phy_is_tc(i915, phy);
2783
2784         main_link_aux_power_domain_put(dig_port, old_crtc_state);
2785
2786         if (is_tc_port)
2787                 intel_tc_port_put_link(dig_port);
2788 }
2789
2790 static void trans_port_sync_stop_link_train(struct intel_atomic_state *state,
2791                                             struct intel_encoder *encoder,
2792                                             const struct intel_crtc_state *crtc_state)
2793 {
2794         const struct drm_connector_state *conn_state;
2795         struct drm_connector *conn;
2796         int i;
2797
2798         if (!crtc_state->sync_mode_slaves_mask)
2799                 return;
2800
2801         for_each_new_connector_in_state(&state->base, conn, conn_state, i) {
2802                 struct intel_encoder *slave_encoder =
2803                         to_intel_encoder(conn_state->best_encoder);
2804                 struct intel_crtc *slave_crtc = to_intel_crtc(conn_state->crtc);
2805                 const struct intel_crtc_state *slave_crtc_state;
2806
2807                 if (!slave_crtc)
2808                         continue;
2809
2810                 slave_crtc_state =
2811                         intel_atomic_get_new_crtc_state(state, slave_crtc);
2812
2813                 if (slave_crtc_state->master_transcoder !=
2814                     crtc_state->cpu_transcoder)
2815                         continue;
2816
2817                 intel_dp_stop_link_train(enc_to_intel_dp(slave_encoder),
2818                                          slave_crtc_state);
2819         }
2820
2821         usleep_range(200, 400);
2822
2823         intel_dp_stop_link_train(enc_to_intel_dp(encoder),
2824                                  crtc_state);
2825 }
2826
2827 static void intel_enable_ddi_dp(struct intel_atomic_state *state,
2828                                 struct intel_encoder *encoder,
2829                                 const struct intel_crtc_state *crtc_state,
2830                                 const struct drm_connector_state *conn_state)
2831 {
2832         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2833         struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
2834         struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
2835         enum port port = encoder->port;
2836
2837         if (port == PORT_A && DISPLAY_VER(dev_priv) < 9)
2838                 intel_dp_stop_link_train(intel_dp, crtc_state);
2839
2840         drm_connector_update_privacy_screen(conn_state);
2841         intel_edp_backlight_on(crtc_state, conn_state);
2842
2843         if (!dig_port->lspcon.active || dig_port->dp.has_hdmi_sink)
2844                 intel_dp_set_infoframes(encoder, true, crtc_state, conn_state);
2845
2846         intel_audio_codec_enable(encoder, crtc_state, conn_state);
2847
2848         trans_port_sync_stop_link_train(state, encoder, crtc_state);
2849 }
2850
2851 static i915_reg_t
2852 gen9_chicken_trans_reg_by_port(struct drm_i915_private *dev_priv,
2853                                enum port port)
2854 {
2855         static const enum transcoder trans[] = {
2856                 [PORT_A] = TRANSCODER_EDP,
2857                 [PORT_B] = TRANSCODER_A,
2858                 [PORT_C] = TRANSCODER_B,
2859                 [PORT_D] = TRANSCODER_C,
2860                 [PORT_E] = TRANSCODER_A,
2861         };
2862
2863         drm_WARN_ON(&dev_priv->drm, DISPLAY_VER(dev_priv) < 9);
2864
2865         if (drm_WARN_ON(&dev_priv->drm, port < PORT_A || port > PORT_E))
2866                 port = PORT_A;
2867
2868         return CHICKEN_TRANS(trans[port]);
2869 }
2870
2871 static void intel_enable_ddi_hdmi(struct intel_atomic_state *state,
2872                                   struct intel_encoder *encoder,
2873                                   const struct intel_crtc_state *crtc_state,
2874                                   const struct drm_connector_state *conn_state)
2875 {
2876         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2877         struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
2878         struct drm_connector *connector = conn_state->connector;
2879         enum port port = encoder->port;
2880         enum phy phy = intel_port_to_phy(dev_priv, port);
2881         u32 buf_ctl;
2882
2883         if (!intel_hdmi_handle_sink_scrambling(encoder, connector,
2884                                                crtc_state->hdmi_high_tmds_clock_ratio,
2885                                                crtc_state->hdmi_scrambling))
2886                 drm_dbg_kms(&dev_priv->drm,
2887                             "[CONNECTOR:%d:%s] Failed to configure sink scrambling/TMDS bit clock ratio\n",
2888                             connector->base.id, connector->name);
2889
2890         if (has_buf_trans_select(dev_priv))
2891                 hsw_prepare_hdmi_ddi_buffers(encoder, crtc_state);
2892
2893         encoder->set_signal_levels(encoder, crtc_state);
2894
2895         /* Display WA #1143: skl,kbl,cfl */
2896         if (DISPLAY_VER(dev_priv) == 9 && !IS_BROXTON(dev_priv)) {
2897                 /*
2898                  * For some reason these chicken bits have been
2899                  * stuffed into a transcoder register, event though
2900                  * the bits affect a specific DDI port rather than
2901                  * a specific transcoder.
2902                  */
2903                 i915_reg_t reg = gen9_chicken_trans_reg_by_port(dev_priv, port);
2904                 u32 val;
2905
2906                 val = intel_de_read(dev_priv, reg);
2907
2908                 if (port == PORT_E)
2909                         val |= DDIE_TRAINING_OVERRIDE_ENABLE |
2910                                 DDIE_TRAINING_OVERRIDE_VALUE;
2911                 else
2912                         val |= DDI_TRAINING_OVERRIDE_ENABLE |
2913                                 DDI_TRAINING_OVERRIDE_VALUE;
2914
2915                 intel_de_write(dev_priv, reg, val);
2916                 intel_de_posting_read(dev_priv, reg);
2917
2918                 udelay(1);
2919
2920                 if (port == PORT_E)
2921                         val &= ~(DDIE_TRAINING_OVERRIDE_ENABLE |
2922                                  DDIE_TRAINING_OVERRIDE_VALUE);
2923                 else
2924                         val &= ~(DDI_TRAINING_OVERRIDE_ENABLE |
2925                                  DDI_TRAINING_OVERRIDE_VALUE);
2926
2927                 intel_de_write(dev_priv, reg, val);
2928         }
2929
2930         intel_ddi_power_up_lanes(encoder, crtc_state);
2931
2932         /* In HDMI/DVI mode, the port width, and swing/emphasis values
2933          * are ignored so nothing special needs to be done besides
2934          * enabling the port.
2935          *
2936          * On ADL_P the PHY link rate and lane count must be programmed but
2937          * these are both 0 for HDMI.
2938          */
2939         buf_ctl = dig_port->saved_port_bits | DDI_BUF_CTL_ENABLE;
2940         if (IS_ALDERLAKE_P(dev_priv) && intel_phy_is_tc(dev_priv, phy)) {
2941                 drm_WARN_ON(&dev_priv->drm, !intel_tc_port_in_legacy_mode(dig_port));
2942                 buf_ctl |= DDI_BUF_CTL_TC_PHY_OWNERSHIP;
2943         }
2944         intel_de_write(dev_priv, DDI_BUF_CTL(port), buf_ctl);
2945
2946         intel_wait_ddi_buf_active(dev_priv, port);
2947
2948         intel_audio_codec_enable(encoder, crtc_state, conn_state);
2949 }
2950
2951 static void intel_enable_ddi(struct intel_atomic_state *state,
2952                              struct intel_encoder *encoder,
2953                              const struct intel_crtc_state *crtc_state,
2954                              const struct drm_connector_state *conn_state)
2955 {
2956         drm_WARN_ON(state->base.dev, crtc_state->has_pch_encoder);
2957
2958         if (!intel_crtc_is_bigjoiner_slave(crtc_state))
2959                 intel_ddi_enable_transcoder_func(encoder, crtc_state);
2960
2961         /* Enable/Disable DP2.0 SDP split config before transcoder */
2962         intel_audio_sdp_split_update(encoder, crtc_state);
2963
2964         intel_enable_transcoder(crtc_state);
2965
2966         intel_vrr_enable(encoder, crtc_state);
2967
2968         intel_crtc_vblank_on(crtc_state);
2969
2970         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
2971                 intel_enable_ddi_hdmi(state, encoder, crtc_state, conn_state);
2972         else
2973                 intel_enable_ddi_dp(state, encoder, crtc_state, conn_state);
2974
2975         /* Enable hdcp if it's desired */
2976         if (conn_state->content_protection ==
2977             DRM_MODE_CONTENT_PROTECTION_DESIRED)
2978                 intel_hdcp_enable(to_intel_connector(conn_state->connector),
2979                                   crtc_state,
2980                                   (u8)conn_state->hdcp_content_type);
2981 }
2982
2983 static void intel_disable_ddi_dp(struct intel_atomic_state *state,
2984                                  struct intel_encoder *encoder,
2985                                  const struct intel_crtc_state *old_crtc_state,
2986                                  const struct drm_connector_state *old_conn_state)
2987 {
2988         struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
2989
2990         intel_dp->link_trained = false;
2991
2992         intel_audio_codec_disable(encoder, old_crtc_state, old_conn_state);
2993
2994         intel_psr_disable(intel_dp, old_crtc_state);
2995         intel_edp_backlight_off(old_conn_state);
2996         /* Disable the decompression in DP Sink */
2997         intel_dp_sink_set_decompression_state(intel_dp, old_crtc_state,
2998                                               false);
2999         /* Disable Ignore_MSA bit in DP Sink */
3000         intel_dp_sink_set_msa_timing_par_ignore_state(intel_dp, old_crtc_state,
3001                                                       false);
3002 }
3003
3004 static void intel_disable_ddi_hdmi(struct intel_atomic_state *state,
3005                                    struct intel_encoder *encoder,
3006                                    const struct intel_crtc_state *old_crtc_state,
3007                                    const struct drm_connector_state *old_conn_state)
3008 {
3009         struct drm_i915_private *i915 = to_i915(encoder->base.dev);
3010         struct drm_connector *connector = old_conn_state->connector;
3011
3012         intel_audio_codec_disable(encoder, old_crtc_state, old_conn_state);
3013
3014         if (!intel_hdmi_handle_sink_scrambling(encoder, connector,
3015                                                false, false))
3016                 drm_dbg_kms(&i915->drm,
3017                             "[CONNECTOR:%d:%s] Failed to reset sink scrambling/TMDS bit clock ratio\n",
3018                             connector->base.id, connector->name);
3019 }
3020
3021 static void intel_disable_ddi(struct intel_atomic_state *state,
3022                               struct intel_encoder *encoder,
3023                               const struct intel_crtc_state *old_crtc_state,
3024                               const struct drm_connector_state *old_conn_state)
3025 {
3026         intel_hdcp_disable(to_intel_connector(old_conn_state->connector));
3027
3028         if (intel_crtc_has_type(old_crtc_state, INTEL_OUTPUT_HDMI))
3029                 intel_disable_ddi_hdmi(state, encoder, old_crtc_state,
3030                                        old_conn_state);
3031         else
3032                 intel_disable_ddi_dp(state, encoder, old_crtc_state,
3033                                      old_conn_state);
3034 }
3035
3036 static void intel_ddi_update_pipe_dp(struct intel_atomic_state *state,
3037                                      struct intel_encoder *encoder,
3038                                      const struct intel_crtc_state *crtc_state,
3039                                      const struct drm_connector_state *conn_state)
3040 {
3041         intel_ddi_set_dp_msa(crtc_state, conn_state);
3042
3043         intel_dp_set_infoframes(encoder, true, crtc_state, conn_state);
3044
3045         intel_backlight_update(state, encoder, crtc_state, conn_state);
3046         drm_connector_update_privacy_screen(conn_state);
3047 }
3048
3049 void intel_ddi_update_pipe(struct intel_atomic_state *state,
3050                            struct intel_encoder *encoder,
3051                            const struct intel_crtc_state *crtc_state,
3052                            const struct drm_connector_state *conn_state)
3053 {
3054
3055         if (!intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI) &&
3056             !intel_encoder_is_mst(encoder))
3057                 intel_ddi_update_pipe_dp(state, encoder, crtc_state,
3058                                          conn_state);
3059
3060         intel_hdcp_update_pipe(state, encoder, crtc_state, conn_state);
3061 }
3062
3063 void intel_ddi_update_active_dpll(struct intel_atomic_state *state,
3064                                   struct intel_encoder *encoder,
3065                                   struct intel_crtc *crtc)
3066 {
3067         struct drm_i915_private *i915 = to_i915(encoder->base.dev);
3068         struct intel_crtc_state *crtc_state =
3069                 intel_atomic_get_new_crtc_state(state, crtc);
3070         struct intel_crtc *slave_crtc;
3071         enum phy phy = intel_port_to_phy(i915, encoder->port);
3072
3073         if (!intel_phy_is_tc(i915, phy))
3074                 return;
3075
3076         intel_update_active_dpll(state, crtc, encoder);
3077         for_each_intel_crtc_in_pipe_mask(&i915->drm, slave_crtc,
3078                                          intel_crtc_bigjoiner_slave_pipes(crtc_state))
3079                 intel_update_active_dpll(state, slave_crtc, encoder);
3080 }
3081
3082 static void
3083 intel_ddi_pre_pll_enable(struct intel_atomic_state *state,
3084                          struct intel_encoder *encoder,
3085                          const struct intel_crtc_state *crtc_state,
3086                          const struct drm_connector_state *conn_state)
3087 {
3088         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3089         struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
3090         enum phy phy = intel_port_to_phy(dev_priv, encoder->port);
3091         bool is_tc_port = intel_phy_is_tc(dev_priv, phy);
3092
3093         if (is_tc_port) {
3094                 struct intel_crtc *master_crtc =
3095                         to_intel_crtc(crtc_state->uapi.crtc);
3096
3097                 intel_tc_port_get_link(dig_port, crtc_state->lane_count);
3098                 intel_ddi_update_active_dpll(state, encoder, master_crtc);
3099         }
3100
3101         main_link_aux_power_domain_get(dig_port, crtc_state);
3102
3103         if (is_tc_port && !intel_tc_port_in_tbt_alt_mode(dig_port))
3104                 /*
3105                  * Program the lane count for static/dynamic connections on
3106                  * Type-C ports.  Skip this step for TBT.
3107                  */
3108                 intel_tc_port_set_fia_lane_count(dig_port, crtc_state->lane_count);
3109         else if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv))
3110                 bxt_ddi_phy_set_lane_optim_mask(encoder,
3111                                                 crtc_state->lane_lat_optim_mask);
3112 }
3113
3114 static void adlp_tbt_to_dp_alt_switch_wa(struct intel_encoder *encoder)
3115 {
3116         struct drm_i915_private *i915 = to_i915(encoder->base.dev);
3117         enum tc_port tc_port = intel_port_to_tc(i915, encoder->port);
3118         int ln;
3119
3120         for (ln = 0; ln < 2; ln++)
3121                 intel_dkl_phy_rmw(i915, DKL_PCS_DW5(tc_port, ln), DKL_PCS_DW5_CORE_SOFTRESET, 0);
3122 }
3123
3124 static void intel_ddi_prepare_link_retrain(struct intel_dp *intel_dp,
3125                                            const struct intel_crtc_state *crtc_state)
3126 {
3127         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
3128         struct intel_encoder *encoder = &dig_port->base;
3129         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3130         enum port port = encoder->port;
3131         u32 dp_tp_ctl, ddi_buf_ctl;
3132         bool wait = false;
3133
3134         dp_tp_ctl = intel_de_read(dev_priv, dp_tp_ctl_reg(encoder, crtc_state));
3135
3136         if (dp_tp_ctl & DP_TP_CTL_ENABLE) {
3137                 ddi_buf_ctl = intel_de_read(dev_priv, DDI_BUF_CTL(port));
3138                 if (ddi_buf_ctl & DDI_BUF_CTL_ENABLE) {
3139                         intel_de_write(dev_priv, DDI_BUF_CTL(port),
3140                                        ddi_buf_ctl & ~DDI_BUF_CTL_ENABLE);
3141                         wait = true;
3142                 }
3143
3144                 dp_tp_ctl &= ~DP_TP_CTL_ENABLE;
3145                 intel_de_write(dev_priv, dp_tp_ctl_reg(encoder, crtc_state), dp_tp_ctl);
3146                 intel_de_posting_read(dev_priv, dp_tp_ctl_reg(encoder, crtc_state));
3147
3148                 if (wait)
3149                         intel_wait_ddi_buf_idle(dev_priv, port);
3150         }
3151
3152         dp_tp_ctl = DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_PAT1;
3153         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST)) {
3154                 dp_tp_ctl |= DP_TP_CTL_MODE_MST;
3155         } else {
3156                 dp_tp_ctl |= DP_TP_CTL_MODE_SST;
3157                 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
3158                         dp_tp_ctl |= DP_TP_CTL_ENHANCED_FRAME_ENABLE;
3159         }
3160         intel_de_write(dev_priv, dp_tp_ctl_reg(encoder, crtc_state), dp_tp_ctl);
3161         intel_de_posting_read(dev_priv, dp_tp_ctl_reg(encoder, crtc_state));
3162
3163         if (IS_ALDERLAKE_P(dev_priv) &&
3164             (intel_tc_port_in_dp_alt_mode(dig_port) || intel_tc_port_in_legacy_mode(dig_port)))
3165                 adlp_tbt_to_dp_alt_switch_wa(encoder);
3166
3167         intel_dp->DP |= DDI_BUF_CTL_ENABLE;
3168         intel_de_write(dev_priv, DDI_BUF_CTL(port), intel_dp->DP);
3169         intel_de_posting_read(dev_priv, DDI_BUF_CTL(port));
3170
3171         intel_wait_ddi_buf_active(dev_priv, port);
3172 }
3173
3174 static void intel_ddi_set_link_train(struct intel_dp *intel_dp,
3175                                      const struct intel_crtc_state *crtc_state,
3176                                      u8 dp_train_pat)
3177 {
3178         struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
3179         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3180         u32 temp;
3181
3182         temp = intel_de_read(dev_priv, dp_tp_ctl_reg(encoder, crtc_state));
3183
3184         temp &= ~DP_TP_CTL_LINK_TRAIN_MASK;
3185         switch (intel_dp_training_pattern_symbol(dp_train_pat)) {
3186         case DP_TRAINING_PATTERN_DISABLE:
3187                 temp |= DP_TP_CTL_LINK_TRAIN_NORMAL;
3188                 break;
3189         case DP_TRAINING_PATTERN_1:
3190                 temp |= DP_TP_CTL_LINK_TRAIN_PAT1;
3191                 break;
3192         case DP_TRAINING_PATTERN_2:
3193                 temp |= DP_TP_CTL_LINK_TRAIN_PAT2;
3194                 break;
3195         case DP_TRAINING_PATTERN_3:
3196                 temp |= DP_TP_CTL_LINK_TRAIN_PAT3;
3197                 break;
3198         case DP_TRAINING_PATTERN_4:
3199                 temp |= DP_TP_CTL_LINK_TRAIN_PAT4;
3200                 break;
3201         }
3202
3203         intel_de_write(dev_priv, dp_tp_ctl_reg(encoder, crtc_state), temp);
3204 }
3205
3206 static void intel_ddi_set_idle_link_train(struct intel_dp *intel_dp,
3207                                           const struct intel_crtc_state *crtc_state)
3208 {
3209         struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
3210         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3211         enum port port = encoder->port;
3212
3213         intel_de_rmw(dev_priv, dp_tp_ctl_reg(encoder, crtc_state),
3214                      DP_TP_CTL_LINK_TRAIN_MASK, DP_TP_CTL_LINK_TRAIN_IDLE);
3215
3216         /*
3217          * Until TGL on PORT_A we can have only eDP in SST mode. There the only
3218          * reason we need to set idle transmission mode is to work around a HW
3219          * issue where we enable the pipe while not in idle link-training mode.
3220          * In this case there is requirement to wait for a minimum number of
3221          * idle patterns to be sent.
3222          */
3223         if (port == PORT_A && DISPLAY_VER(dev_priv) < 12)
3224                 return;
3225
3226         if (intel_de_wait_for_set(dev_priv,
3227                                   dp_tp_status_reg(encoder, crtc_state),
3228                                   DP_TP_STATUS_IDLE_DONE, 1))
3229                 drm_err(&dev_priv->drm,
3230                         "Timed out waiting for DP idle patterns\n");
3231 }
3232
3233 static bool intel_ddi_is_audio_enabled(struct drm_i915_private *dev_priv,
3234                                        enum transcoder cpu_transcoder)
3235 {
3236         if (cpu_transcoder == TRANSCODER_EDP)
3237                 return false;
3238
3239         if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_AUDIO_MMIO))
3240                 return false;
3241
3242         return intel_de_read(dev_priv, HSW_AUD_PIN_ELD_CP_VLD) &
3243                 AUDIO_OUTPUT_ENABLE(cpu_transcoder);
3244 }
3245
3246 void intel_ddi_compute_min_voltage_level(struct drm_i915_private *dev_priv,
3247                                          struct intel_crtc_state *crtc_state)
3248 {
3249         if (DISPLAY_VER(dev_priv) >= 12 && crtc_state->port_clock > 594000)
3250                 crtc_state->min_voltage_level = 2;
3251         else if (IS_JSL_EHL(dev_priv) && crtc_state->port_clock > 594000)
3252                 crtc_state->min_voltage_level = 3;
3253         else if (DISPLAY_VER(dev_priv) >= 11 && crtc_state->port_clock > 594000)
3254                 crtc_state->min_voltage_level = 1;
3255 }
3256
3257 static enum transcoder bdw_transcoder_master_readout(struct drm_i915_private *dev_priv,
3258                                                      enum transcoder cpu_transcoder)
3259 {
3260         u32 master_select;
3261
3262         if (DISPLAY_VER(dev_priv) >= 11) {
3263                 u32 ctl2 = intel_de_read(dev_priv, TRANS_DDI_FUNC_CTL2(cpu_transcoder));
3264
3265                 if ((ctl2 & PORT_SYNC_MODE_ENABLE) == 0)
3266                         return INVALID_TRANSCODER;
3267
3268                 master_select = REG_FIELD_GET(PORT_SYNC_MODE_MASTER_SELECT_MASK, ctl2);
3269         } else {
3270                 u32 ctl = intel_de_read(dev_priv, TRANS_DDI_FUNC_CTL(cpu_transcoder));
3271
3272                 if ((ctl & TRANS_DDI_PORT_SYNC_ENABLE) == 0)
3273                         return INVALID_TRANSCODER;
3274
3275                 master_select = REG_FIELD_GET(TRANS_DDI_PORT_SYNC_MASTER_SELECT_MASK, ctl);
3276         }
3277
3278         if (master_select == 0)
3279                 return TRANSCODER_EDP;
3280         else
3281                 return master_select - 1;
3282 }
3283
3284 static void bdw_get_trans_port_sync_config(struct intel_crtc_state *crtc_state)
3285 {
3286         struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
3287         u32 transcoders = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) |
3288                 BIT(TRANSCODER_C) | BIT(TRANSCODER_D);
3289         enum transcoder cpu_transcoder;
3290
3291         crtc_state->master_transcoder =
3292                 bdw_transcoder_master_readout(dev_priv, crtc_state->cpu_transcoder);
3293
3294         for_each_cpu_transcoder_masked(dev_priv, cpu_transcoder, transcoders) {
3295                 enum intel_display_power_domain power_domain;
3296                 intel_wakeref_t trans_wakeref;
3297
3298                 power_domain = POWER_DOMAIN_TRANSCODER(cpu_transcoder);
3299                 trans_wakeref = intel_display_power_get_if_enabled(dev_priv,
3300                                                                    power_domain);
3301
3302                 if (!trans_wakeref)
3303                         continue;
3304
3305                 if (bdw_transcoder_master_readout(dev_priv, cpu_transcoder) ==
3306                     crtc_state->cpu_transcoder)
3307                         crtc_state->sync_mode_slaves_mask |= BIT(cpu_transcoder);
3308
3309                 intel_display_power_put(dev_priv, power_domain, trans_wakeref);
3310         }
3311
3312         drm_WARN_ON(&dev_priv->drm,
3313                     crtc_state->master_transcoder != INVALID_TRANSCODER &&
3314                     crtc_state->sync_mode_slaves_mask);
3315 }
3316
3317 static void intel_ddi_read_func_ctl(struct intel_encoder *encoder,
3318                                     struct intel_crtc_state *pipe_config)
3319 {
3320         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3321         struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);
3322         enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
3323         struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
3324         u32 temp, flags = 0;
3325
3326         temp = intel_de_read(dev_priv, TRANS_DDI_FUNC_CTL(cpu_transcoder));
3327         if (temp & TRANS_DDI_PHSYNC)
3328                 flags |= DRM_MODE_FLAG_PHSYNC;
3329         else
3330                 flags |= DRM_MODE_FLAG_NHSYNC;
3331         if (temp & TRANS_DDI_PVSYNC)
3332                 flags |= DRM_MODE_FLAG_PVSYNC;
3333         else
3334                 flags |= DRM_MODE_FLAG_NVSYNC;
3335
3336         pipe_config->hw.adjusted_mode.flags |= flags;
3337
3338         switch (temp & TRANS_DDI_BPC_MASK) {
3339         case TRANS_DDI_BPC_6:
3340                 pipe_config->pipe_bpp = 18;
3341                 break;
3342         case TRANS_DDI_BPC_8:
3343                 pipe_config->pipe_bpp = 24;
3344                 break;
3345         case TRANS_DDI_BPC_10:
3346                 pipe_config->pipe_bpp = 30;
3347                 break;
3348         case TRANS_DDI_BPC_12:
3349                 pipe_config->pipe_bpp = 36;
3350                 break;
3351         default:
3352                 break;
3353         }
3354
3355         switch (temp & TRANS_DDI_MODE_SELECT_MASK) {
3356         case TRANS_DDI_MODE_SELECT_HDMI:
3357                 pipe_config->has_hdmi_sink = true;
3358
3359                 pipe_config->infoframes.enable |=
3360                         intel_hdmi_infoframes_enabled(encoder, pipe_config);
3361
3362                 if (pipe_config->infoframes.enable)
3363                         pipe_config->has_infoframe = true;
3364
3365                 if (temp & TRANS_DDI_HDMI_SCRAMBLING)
3366                         pipe_config->hdmi_scrambling = true;
3367                 if (temp & TRANS_DDI_HIGH_TMDS_CHAR_RATE)
3368                         pipe_config->hdmi_high_tmds_clock_ratio = true;
3369                 fallthrough;
3370         case TRANS_DDI_MODE_SELECT_DVI:
3371                 pipe_config->output_types |= BIT(INTEL_OUTPUT_HDMI);
3372                 pipe_config->lane_count = 4;
3373                 break;
3374         case TRANS_DDI_MODE_SELECT_DP_SST:
3375                 if (encoder->type == INTEL_OUTPUT_EDP)
3376                         pipe_config->output_types |= BIT(INTEL_OUTPUT_EDP);
3377                 else
3378                         pipe_config->output_types |= BIT(INTEL_OUTPUT_DP);
3379                 pipe_config->lane_count =
3380                         ((temp & DDI_PORT_WIDTH_MASK) >> DDI_PORT_WIDTH_SHIFT) + 1;
3381
3382                 intel_cpu_transcoder_get_m1_n1(crtc, cpu_transcoder,
3383                                                &pipe_config->dp_m_n);
3384                 intel_cpu_transcoder_get_m2_n2(crtc, cpu_transcoder,
3385                                                &pipe_config->dp_m2_n2);
3386
3387                 if (DISPLAY_VER(dev_priv) >= 11) {
3388                         i915_reg_t dp_tp_ctl = dp_tp_ctl_reg(encoder, pipe_config);
3389
3390                         pipe_config->fec_enable =
3391                                 intel_de_read(dev_priv, dp_tp_ctl) & DP_TP_CTL_FEC_ENABLE;
3392
3393                         drm_dbg_kms(&dev_priv->drm,
3394                                     "[ENCODER:%d:%s] Fec status: %u\n",
3395                                     encoder->base.base.id, encoder->base.name,
3396                                     pipe_config->fec_enable);
3397                 }
3398
3399                 if (dig_port->lspcon.active && dig_port->dp.has_hdmi_sink)
3400                         pipe_config->infoframes.enable |=
3401                                 intel_lspcon_infoframes_enabled(encoder, pipe_config);
3402                 else
3403                         pipe_config->infoframes.enable |=
3404                                 intel_hdmi_infoframes_enabled(encoder, pipe_config);
3405                 break;
3406         case TRANS_DDI_MODE_SELECT_FDI_OR_128B132B:
3407                 if (!HAS_DP20(dev_priv)) {
3408                         /* FDI */
3409                         pipe_config->output_types |= BIT(INTEL_OUTPUT_ANALOG);
3410                         break;
3411                 }
3412                 fallthrough; /* 128b/132b */
3413         case TRANS_DDI_MODE_SELECT_DP_MST:
3414                 pipe_config->output_types |= BIT(INTEL_OUTPUT_DP_MST);
3415                 pipe_config->lane_count =
3416                         ((temp & DDI_PORT_WIDTH_MASK) >> DDI_PORT_WIDTH_SHIFT) + 1;
3417
3418                 if (DISPLAY_VER(dev_priv) >= 12)
3419                         pipe_config->mst_master_transcoder =
3420                                         REG_FIELD_GET(TRANS_DDI_MST_TRANSPORT_SELECT_MASK, temp);
3421
3422                 intel_cpu_transcoder_get_m1_n1(crtc, cpu_transcoder,
3423                                                &pipe_config->dp_m_n);
3424
3425                 pipe_config->infoframes.enable |=
3426                         intel_hdmi_infoframes_enabled(encoder, pipe_config);
3427                 break;
3428         default:
3429                 break;
3430         }
3431 }
3432
3433 static void intel_ddi_get_config(struct intel_encoder *encoder,
3434                                  struct intel_crtc_state *pipe_config)
3435 {
3436         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3437         enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
3438
3439         /* XXX: DSI transcoder paranoia */
3440         if (drm_WARN_ON(&dev_priv->drm, transcoder_is_dsi(cpu_transcoder)))
3441                 return;
3442
3443         intel_ddi_read_func_ctl(encoder, pipe_config);
3444
3445         intel_ddi_mso_get_config(encoder, pipe_config);
3446
3447         pipe_config->has_audio =
3448                 intel_ddi_is_audio_enabled(dev_priv, cpu_transcoder);
3449
3450         if (encoder->type == INTEL_OUTPUT_EDP)
3451                 intel_edp_fixup_vbt_bpp(encoder, pipe_config->pipe_bpp);
3452
3453         ddi_dotclock_get(pipe_config);
3454
3455         if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv))
3456                 pipe_config->lane_lat_optim_mask =
3457                         bxt_ddi_phy_get_lane_lat_optim_mask(encoder);
3458
3459         intel_ddi_compute_min_voltage_level(dev_priv, pipe_config);
3460
3461         intel_hdmi_read_gcp_infoframe(encoder, pipe_config);
3462
3463         intel_read_infoframe(encoder, pipe_config,
3464                              HDMI_INFOFRAME_TYPE_AVI,
3465                              &pipe_config->infoframes.avi);
3466         intel_read_infoframe(encoder, pipe_config,
3467                              HDMI_INFOFRAME_TYPE_SPD,
3468                              &pipe_config->infoframes.spd);
3469         intel_read_infoframe(encoder, pipe_config,
3470                              HDMI_INFOFRAME_TYPE_VENDOR,
3471                              &pipe_config->infoframes.hdmi);
3472         intel_read_infoframe(encoder, pipe_config,
3473                              HDMI_INFOFRAME_TYPE_DRM,
3474                              &pipe_config->infoframes.drm);
3475
3476         if (DISPLAY_VER(dev_priv) >= 8)
3477                 bdw_get_trans_port_sync_config(pipe_config);
3478
3479         intel_read_dp_sdp(encoder, pipe_config, HDMI_PACKET_TYPE_GAMUT_METADATA);
3480         intel_read_dp_sdp(encoder, pipe_config, DP_SDP_VSC);
3481
3482         intel_psr_get_config(encoder, pipe_config);
3483
3484         intel_audio_codec_get_config(encoder, pipe_config);
3485 }
3486
3487 void intel_ddi_get_clock(struct intel_encoder *encoder,
3488                          struct intel_crtc_state *crtc_state,
3489                          struct intel_shared_dpll *pll)
3490 {
3491         struct drm_i915_private *i915 = to_i915(encoder->base.dev);
3492         enum icl_port_dpll_id port_dpll_id = ICL_PORT_DPLL_DEFAULT;
3493         struct icl_port_dpll *port_dpll = &crtc_state->icl_port_dplls[port_dpll_id];
3494         bool pll_active;
3495
3496         if (drm_WARN_ON(&i915->drm, !pll))
3497                 return;
3498
3499         port_dpll->pll = pll;
3500         pll_active = intel_dpll_get_hw_state(i915, pll, &port_dpll->hw_state);
3501         drm_WARN_ON(&i915->drm, !pll_active);
3502
3503         icl_set_active_port_dpll(crtc_state, port_dpll_id);
3504
3505         crtc_state->port_clock = intel_dpll_get_freq(i915, crtc_state->shared_dpll,
3506                                                      &crtc_state->dpll_hw_state);
3507 }
3508
3509 static void dg2_ddi_get_config(struct intel_encoder *encoder,
3510                                 struct intel_crtc_state *crtc_state)
3511 {
3512         intel_mpllb_readout_hw_state(encoder, &crtc_state->mpllb_state);
3513         crtc_state->port_clock = intel_mpllb_calc_port_clock(encoder, &crtc_state->mpllb_state);
3514
3515         intel_ddi_get_config(encoder, crtc_state);
3516 }
3517
3518 static void adls_ddi_get_config(struct intel_encoder *encoder,
3519                                 struct intel_crtc_state *crtc_state)
3520 {
3521         intel_ddi_get_clock(encoder, crtc_state, adls_ddi_get_pll(encoder));
3522         intel_ddi_get_config(encoder, crtc_state);
3523 }
3524
3525 static void rkl_ddi_get_config(struct intel_encoder *encoder,
3526                                struct intel_crtc_state *crtc_state)
3527 {
3528         intel_ddi_get_clock(encoder, crtc_state, rkl_ddi_get_pll(encoder));
3529         intel_ddi_get_config(encoder, crtc_state);
3530 }
3531
3532 static void dg1_ddi_get_config(struct intel_encoder *encoder,
3533                                struct intel_crtc_state *crtc_state)
3534 {
3535         intel_ddi_get_clock(encoder, crtc_state, dg1_ddi_get_pll(encoder));
3536         intel_ddi_get_config(encoder, crtc_state);
3537 }
3538
3539 static void icl_ddi_combo_get_config(struct intel_encoder *encoder,
3540                                      struct intel_crtc_state *crtc_state)
3541 {
3542         intel_ddi_get_clock(encoder, crtc_state, icl_ddi_combo_get_pll(encoder));
3543         intel_ddi_get_config(encoder, crtc_state);
3544 }
3545
3546 static bool icl_ddi_tc_pll_is_tbt(const struct intel_shared_dpll *pll)
3547 {
3548         return pll->info->id == DPLL_ID_ICL_TBTPLL;
3549 }
3550
3551 static enum icl_port_dpll_id
3552 icl_ddi_tc_port_pll_type(struct intel_encoder *encoder,
3553                          const struct intel_crtc_state *crtc_state)
3554 {
3555         struct drm_i915_private *i915 = to_i915(encoder->base.dev);
3556         const struct intel_shared_dpll *pll = crtc_state->shared_dpll;
3557
3558         if (drm_WARN_ON(&i915->drm, !pll))
3559                 return ICL_PORT_DPLL_DEFAULT;
3560
3561         if (icl_ddi_tc_pll_is_tbt(pll))
3562                 return ICL_PORT_DPLL_DEFAULT;
3563         else
3564                 return ICL_PORT_DPLL_MG_PHY;
3565 }
3566
3567 enum icl_port_dpll_id
3568 intel_ddi_port_pll_type(struct intel_encoder *encoder,
3569                         const struct intel_crtc_state *crtc_state)
3570 {
3571         if (!encoder->port_pll_type)
3572                 return ICL_PORT_DPLL_DEFAULT;
3573
3574         return encoder->port_pll_type(encoder, crtc_state);
3575 }
3576
3577 static void icl_ddi_tc_get_clock(struct intel_encoder *encoder,
3578                                  struct intel_crtc_state *crtc_state,
3579                                  struct intel_shared_dpll *pll)
3580 {
3581         struct drm_i915_private *i915 = to_i915(encoder->base.dev);
3582         enum icl_port_dpll_id port_dpll_id;
3583         struct icl_port_dpll *port_dpll;
3584         bool pll_active;
3585
3586         if (drm_WARN_ON(&i915->drm, !pll))
3587                 return;
3588
3589         if (icl_ddi_tc_pll_is_tbt(pll))
3590                 port_dpll_id = ICL_PORT_DPLL_DEFAULT;
3591         else
3592                 port_dpll_id = ICL_PORT_DPLL_MG_PHY;
3593
3594         port_dpll = &crtc_state->icl_port_dplls[port_dpll_id];
3595
3596         port_dpll->pll = pll;
3597         pll_active = intel_dpll_get_hw_state(i915, pll, &port_dpll->hw_state);
3598         drm_WARN_ON(&i915->drm, !pll_active);
3599
3600         icl_set_active_port_dpll(crtc_state, port_dpll_id);
3601
3602         if (icl_ddi_tc_pll_is_tbt(crtc_state->shared_dpll))
3603                 crtc_state->port_clock = icl_calc_tbt_pll_link(i915, encoder->port);
3604         else
3605                 crtc_state->port_clock = intel_dpll_get_freq(i915, crtc_state->shared_dpll,
3606                                                              &crtc_state->dpll_hw_state);
3607 }
3608
3609 static void icl_ddi_tc_get_config(struct intel_encoder *encoder,
3610                                   struct intel_crtc_state *crtc_state)
3611 {
3612         icl_ddi_tc_get_clock(encoder, crtc_state, icl_ddi_tc_get_pll(encoder));
3613         intel_ddi_get_config(encoder, crtc_state);
3614 }
3615
3616 static void bxt_ddi_get_config(struct intel_encoder *encoder,
3617                                struct intel_crtc_state *crtc_state)
3618 {
3619         intel_ddi_get_clock(encoder, crtc_state, bxt_ddi_get_pll(encoder));
3620         intel_ddi_get_config(encoder, crtc_state);
3621 }
3622
3623 static void skl_ddi_get_config(struct intel_encoder *encoder,
3624                                struct intel_crtc_state *crtc_state)
3625 {
3626         intel_ddi_get_clock(encoder, crtc_state, skl_ddi_get_pll(encoder));
3627         intel_ddi_get_config(encoder, crtc_state);
3628 }
3629
3630 void hsw_ddi_get_config(struct intel_encoder *encoder,
3631                         struct intel_crtc_state *crtc_state)
3632 {
3633         intel_ddi_get_clock(encoder, crtc_state, hsw_ddi_get_pll(encoder));
3634         intel_ddi_get_config(encoder, crtc_state);
3635 }
3636
3637 static void intel_ddi_sync_state(struct intel_encoder *encoder,
3638                                  const struct intel_crtc_state *crtc_state)
3639 {
3640         struct drm_i915_private *i915 = to_i915(encoder->base.dev);
3641         enum phy phy = intel_port_to_phy(i915, encoder->port);
3642
3643         if (intel_phy_is_tc(i915, phy))
3644                 intel_tc_port_sanitize_mode(enc_to_dig_port(encoder),
3645                                             crtc_state);
3646
3647         if (crtc_state && intel_crtc_has_dp_encoder(crtc_state))
3648                 intel_dp_sync_state(encoder, crtc_state);
3649 }
3650
3651 static bool intel_ddi_initial_fastset_check(struct intel_encoder *encoder,
3652                                             struct intel_crtc_state *crtc_state)
3653 {
3654         struct drm_i915_private *i915 = to_i915(encoder->base.dev);
3655         enum phy phy = intel_port_to_phy(i915, encoder->port);
3656         bool fastset = true;
3657
3658         if (intel_phy_is_tc(i915, phy)) {
3659                 drm_dbg_kms(&i915->drm, "[ENCODER:%d:%s] Forcing full modeset to compute TC port DPLLs\n",
3660                             encoder->base.base.id, encoder->base.name);
3661                 crtc_state->uapi.mode_changed = true;
3662                 fastset = false;
3663         }
3664
3665         if (intel_crtc_has_dp_encoder(crtc_state) &&
3666             !intel_dp_initial_fastset_check(encoder, crtc_state))
3667                 fastset = false;
3668
3669         return fastset;
3670 }
3671
3672 static enum intel_output_type
3673 intel_ddi_compute_output_type(struct intel_encoder *encoder,
3674                               struct intel_crtc_state *crtc_state,
3675                               struct drm_connector_state *conn_state)
3676 {
3677         switch (conn_state->connector->connector_type) {
3678         case DRM_MODE_CONNECTOR_HDMIA:
3679                 return INTEL_OUTPUT_HDMI;
3680         case DRM_MODE_CONNECTOR_eDP:
3681                 return INTEL_OUTPUT_EDP;
3682         case DRM_MODE_CONNECTOR_DisplayPort:
3683                 return INTEL_OUTPUT_DP;
3684         default:
3685                 MISSING_CASE(conn_state->connector->connector_type);
3686                 return INTEL_OUTPUT_UNUSED;
3687         }
3688 }
3689
3690 static int intel_ddi_compute_config(struct intel_encoder *encoder,
3691                                     struct intel_crtc_state *pipe_config,
3692                                     struct drm_connector_state *conn_state)
3693 {
3694         struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);
3695         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3696         enum port port = encoder->port;
3697         int ret;
3698
3699         if (HAS_TRANSCODER(dev_priv, TRANSCODER_EDP) && port == PORT_A)
3700                 pipe_config->cpu_transcoder = TRANSCODER_EDP;
3701
3702         if (intel_crtc_has_type(pipe_config, INTEL_OUTPUT_HDMI)) {
3703                 ret = intel_hdmi_compute_config(encoder, pipe_config, conn_state);
3704         } else {
3705                 ret = intel_dp_compute_config(encoder, pipe_config, conn_state);
3706         }
3707
3708         if (ret)
3709                 return ret;
3710
3711         if (IS_HASWELL(dev_priv) && crtc->pipe == PIPE_A &&
3712             pipe_config->cpu_transcoder == TRANSCODER_EDP)
3713                 pipe_config->pch_pfit.force_thru =
3714                         pipe_config->pch_pfit.enabled ||
3715                         pipe_config->crc_enabled;
3716
3717         if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv))
3718                 pipe_config->lane_lat_optim_mask =
3719                         bxt_ddi_phy_calc_lane_lat_optim_mask(pipe_config->lane_count);
3720
3721         intel_ddi_compute_min_voltage_level(dev_priv, pipe_config);
3722
3723         return 0;
3724 }
3725
3726 static bool mode_equal(const struct drm_display_mode *mode1,
3727                        const struct drm_display_mode *mode2)
3728 {
3729         return drm_mode_match(mode1, mode2,
3730                               DRM_MODE_MATCH_TIMINGS |
3731                               DRM_MODE_MATCH_FLAGS |
3732                               DRM_MODE_MATCH_3D_FLAGS) &&
3733                 mode1->clock == mode2->clock; /* we want an exact match */
3734 }
3735
3736 static bool m_n_equal(const struct intel_link_m_n *m_n_1,
3737                       const struct intel_link_m_n *m_n_2)
3738 {
3739         return m_n_1->tu == m_n_2->tu &&
3740                 m_n_1->data_m == m_n_2->data_m &&
3741                 m_n_1->data_n == m_n_2->data_n &&
3742                 m_n_1->link_m == m_n_2->link_m &&
3743                 m_n_1->link_n == m_n_2->link_n;
3744 }
3745
3746 static bool crtcs_port_sync_compatible(const struct intel_crtc_state *crtc_state1,
3747                                        const struct intel_crtc_state *crtc_state2)
3748 {
3749         return crtc_state1->hw.active && crtc_state2->hw.active &&
3750                 crtc_state1->output_types == crtc_state2->output_types &&
3751                 crtc_state1->output_format == crtc_state2->output_format &&
3752                 crtc_state1->lane_count == crtc_state2->lane_count &&
3753                 crtc_state1->port_clock == crtc_state2->port_clock &&
3754                 mode_equal(&crtc_state1->hw.adjusted_mode,
3755                            &crtc_state2->hw.adjusted_mode) &&
3756                 m_n_equal(&crtc_state1->dp_m_n, &crtc_state2->dp_m_n);
3757 }
3758
3759 static u8
3760 intel_ddi_port_sync_transcoders(const struct intel_crtc_state *ref_crtc_state,
3761                                 int tile_group_id)
3762 {
3763         struct drm_connector *connector;
3764         const struct drm_connector_state *conn_state;
3765         struct drm_i915_private *dev_priv = to_i915(ref_crtc_state->uapi.crtc->dev);
3766         struct intel_atomic_state *state =
3767                 to_intel_atomic_state(ref_crtc_state->uapi.state);
3768         u8 transcoders = 0;
3769         int i;
3770
3771         /*
3772          * We don't enable port sync on BDW due to missing w/as and
3773          * due to not having adjusted the modeset sequence appropriately.
3774          */
3775         if (DISPLAY_VER(dev_priv) < 9)
3776                 return 0;
3777
3778         if (!intel_crtc_has_type(ref_crtc_state, INTEL_OUTPUT_DP))
3779                 return 0;
3780
3781         for_each_new_connector_in_state(&state->base, connector, conn_state, i) {
3782                 struct intel_crtc *crtc = to_intel_crtc(conn_state->crtc);
3783                 const struct intel_crtc_state *crtc_state;
3784
3785                 if (!crtc)
3786                         continue;
3787
3788                 if (!connector->has_tile ||
3789                     connector->tile_group->id !=
3790                     tile_group_id)
3791                         continue;
3792                 crtc_state = intel_atomic_get_new_crtc_state(state,
3793                                                              crtc);
3794                 if (!crtcs_port_sync_compatible(ref_crtc_state,
3795                                                 crtc_state))
3796                         continue;
3797                 transcoders |= BIT(crtc_state->cpu_transcoder);
3798         }
3799
3800         return transcoders;
3801 }
3802
3803 static int intel_ddi_compute_config_late(struct intel_encoder *encoder,
3804                                          struct intel_crtc_state *crtc_state,
3805                                          struct drm_connector_state *conn_state)
3806 {
3807         struct drm_i915_private *i915 = to_i915(encoder->base.dev);
3808         struct drm_connector *connector = conn_state->connector;
3809         u8 port_sync_transcoders = 0;
3810
3811         drm_dbg_kms(&i915->drm, "[ENCODER:%d:%s] [CRTC:%d:%s]",
3812                     encoder->base.base.id, encoder->base.name,
3813                     crtc_state->uapi.crtc->base.id, crtc_state->uapi.crtc->name);
3814
3815         if (connector->has_tile)
3816                 port_sync_transcoders = intel_ddi_port_sync_transcoders(crtc_state,
3817                                                                         connector->tile_group->id);
3818
3819         /*
3820          * EDP Transcoders cannot be ensalved
3821          * make them a master always when present
3822          */
3823         if (port_sync_transcoders & BIT(TRANSCODER_EDP))
3824                 crtc_state->master_transcoder = TRANSCODER_EDP;
3825         else
3826                 crtc_state->master_transcoder = ffs(port_sync_transcoders) - 1;
3827
3828         if (crtc_state->master_transcoder == crtc_state->cpu_transcoder) {
3829                 crtc_state->master_transcoder = INVALID_TRANSCODER;
3830                 crtc_state->sync_mode_slaves_mask =
3831                         port_sync_transcoders & ~BIT(crtc_state->cpu_transcoder);
3832         }
3833
3834         return 0;
3835 }
3836
3837 static void intel_ddi_encoder_destroy(struct drm_encoder *encoder)
3838 {
3839         struct drm_i915_private *i915 = to_i915(encoder->dev);
3840         struct intel_digital_port *dig_port = enc_to_dig_port(to_intel_encoder(encoder));
3841         enum phy phy = intel_port_to_phy(i915, dig_port->base.port);
3842
3843         intel_dp_encoder_flush_work(encoder);
3844         if (intel_phy_is_tc(i915, phy))
3845                 intel_tc_port_cleanup(dig_port);
3846         intel_display_power_flush_work(i915);
3847
3848         drm_encoder_cleanup(encoder);
3849         kfree(dig_port->hdcp_port_data.streams);
3850         kfree(dig_port);
3851 }
3852
3853 static void intel_ddi_encoder_reset(struct drm_encoder *encoder)
3854 {
3855         struct drm_i915_private *i915 = to_i915(encoder->dev);
3856         struct intel_dp *intel_dp = enc_to_intel_dp(to_intel_encoder(encoder));
3857         struct intel_digital_port *dig_port = enc_to_dig_port(to_intel_encoder(encoder));
3858         enum phy phy = intel_port_to_phy(i915, dig_port->base.port);
3859
3860         intel_dp->reset_link_params = true;
3861
3862         intel_pps_encoder_reset(intel_dp);
3863
3864         if (intel_phy_is_tc(i915, phy))
3865                 intel_tc_port_init_mode(dig_port);
3866 }
3867
3868 static const struct drm_encoder_funcs intel_ddi_funcs = {
3869         .reset = intel_ddi_encoder_reset,
3870         .destroy = intel_ddi_encoder_destroy,
3871 };
3872
3873 static struct intel_connector *
3874 intel_ddi_init_dp_connector(struct intel_digital_port *dig_port)
3875 {
3876         struct intel_connector *connector;
3877         enum port port = dig_port->base.port;
3878
3879         connector = intel_connector_alloc();
3880         if (!connector)
3881                 return NULL;
3882
3883         dig_port->dp.output_reg = DDI_BUF_CTL(port);
3884         dig_port->dp.prepare_link_retrain = intel_ddi_prepare_link_retrain;
3885         dig_port->dp.set_link_train = intel_ddi_set_link_train;
3886         dig_port->dp.set_idle_link_train = intel_ddi_set_idle_link_train;
3887
3888         dig_port->dp.voltage_max = intel_ddi_dp_voltage_max;
3889         dig_port->dp.preemph_max = intel_ddi_dp_preemph_max;
3890
3891         if (!intel_dp_init_connector(dig_port, connector)) {
3892                 kfree(connector);
3893                 return NULL;
3894         }
3895
3896         if (dig_port->base.type == INTEL_OUTPUT_EDP) {
3897                 struct drm_device *dev = dig_port->base.base.dev;
3898                 struct drm_privacy_screen *privacy_screen;
3899
3900                 privacy_screen = drm_privacy_screen_get(dev->dev, NULL);
3901                 if (!IS_ERR(privacy_screen)) {
3902                         drm_connector_attach_privacy_screen_provider(&connector->base,
3903                                                                      privacy_screen);
3904                 } else if (PTR_ERR(privacy_screen) != -ENODEV) {
3905                         drm_warn(dev, "Error getting privacy-screen\n");
3906                 }
3907         }
3908
3909         return connector;
3910 }
3911
3912 static int modeset_pipe(struct drm_crtc *crtc,
3913                         struct drm_modeset_acquire_ctx *ctx)
3914 {
3915         struct drm_atomic_state *state;
3916         struct drm_crtc_state *crtc_state;
3917         int ret;
3918
3919         state = drm_atomic_state_alloc(crtc->dev);
3920         if (!state)
3921                 return -ENOMEM;
3922
3923         state->acquire_ctx = ctx;
3924
3925         crtc_state = drm_atomic_get_crtc_state(state, crtc);
3926         if (IS_ERR(crtc_state)) {
3927                 ret = PTR_ERR(crtc_state);
3928                 goto out;
3929         }
3930
3931         crtc_state->connectors_changed = true;
3932
3933         ret = drm_atomic_commit(state);
3934 out:
3935         drm_atomic_state_put(state);
3936
3937         return ret;
3938 }
3939
3940 static int intel_hdmi_reset_link(struct intel_encoder *encoder,
3941                                  struct drm_modeset_acquire_ctx *ctx)
3942 {
3943         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3944         struct intel_hdmi *hdmi = enc_to_intel_hdmi(encoder);
3945         struct intel_connector *connector = hdmi->attached_connector;
3946         struct i2c_adapter *adapter =
3947                 intel_gmbus_get_adapter(dev_priv, hdmi->ddc_bus);
3948         struct drm_connector_state *conn_state;
3949         struct intel_crtc_state *crtc_state;
3950         struct intel_crtc *crtc;
3951         u8 config;
3952         int ret;
3953
3954         if (!connector || connector->base.status != connector_status_connected)
3955                 return 0;
3956
3957         ret = drm_modeset_lock(&dev_priv->drm.mode_config.connection_mutex,
3958                                ctx);
3959         if (ret)
3960                 return ret;
3961
3962         conn_state = connector->base.state;
3963
3964         crtc = to_intel_crtc(conn_state->crtc);
3965         if (!crtc)
3966                 return 0;
3967
3968         ret = drm_modeset_lock(&crtc->base.mutex, ctx);
3969         if (ret)
3970                 return ret;
3971
3972         crtc_state = to_intel_crtc_state(crtc->base.state);
3973
3974         drm_WARN_ON(&dev_priv->drm,
3975                     !intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI));
3976
3977         if (!crtc_state->hw.active)
3978                 return 0;
3979
3980         if (!crtc_state->hdmi_high_tmds_clock_ratio &&
3981             !crtc_state->hdmi_scrambling)
3982                 return 0;
3983
3984         if (conn_state->commit &&
3985             !try_wait_for_completion(&conn_state->commit->hw_done))
3986                 return 0;
3987
3988         ret = drm_scdc_readb(adapter, SCDC_TMDS_CONFIG, &config);
3989         if (ret < 0) {
3990                 drm_err(&dev_priv->drm, "[CONNECTOR:%d:%s] Failed to read TMDS config: %d\n",
3991                         connector->base.base.id, connector->base.name, ret);
3992                 return 0;
3993         }
3994
3995         if (!!(config & SCDC_TMDS_BIT_CLOCK_RATIO_BY_40) ==
3996             crtc_state->hdmi_high_tmds_clock_ratio &&
3997             !!(config & SCDC_SCRAMBLING_ENABLE) ==
3998             crtc_state->hdmi_scrambling)
3999                 return 0;
4000
4001         /*
4002          * HDMI 2.0 says that one should not send scrambled data
4003          * prior to configuring the sink scrambling, and that
4004          * TMDS clock/data transmission should be suspended when
4005          * changing the TMDS clock rate in the sink. So let's
4006          * just do a full modeset here, even though some sinks
4007          * would be perfectly happy if were to just reconfigure
4008          * the SCDC settings on the fly.
4009          */
4010         return modeset_pipe(&crtc->base, ctx);
4011 }
4012
4013 static enum intel_hotplug_state
4014 intel_ddi_hotplug(struct intel_encoder *encoder,
4015                   struct intel_connector *connector)
4016 {
4017         struct drm_i915_private *i915 = to_i915(encoder->base.dev);
4018         struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
4019         struct intel_dp *intel_dp = &dig_port->dp;
4020         enum phy phy = intel_port_to_phy(i915, encoder->port);
4021         bool is_tc = intel_phy_is_tc(i915, phy);
4022         struct drm_modeset_acquire_ctx ctx;
4023         enum intel_hotplug_state state;
4024         int ret;
4025
4026         if (intel_dp->compliance.test_active &&
4027             intel_dp->compliance.test_type == DP_TEST_LINK_PHY_TEST_PATTERN) {
4028                 intel_dp_phy_test(encoder);
4029                 /* just do the PHY test and nothing else */
4030                 return INTEL_HOTPLUG_UNCHANGED;
4031         }
4032
4033         state = intel_encoder_hotplug(encoder, connector);
4034
4035         drm_modeset_acquire_init(&ctx, 0);
4036
4037         for (;;) {
4038                 if (connector->base.connector_type == DRM_MODE_CONNECTOR_HDMIA)
4039                         ret = intel_hdmi_reset_link(encoder, &ctx);
4040                 else
4041                         ret = intel_dp_retrain_link(encoder, &ctx);
4042
4043                 if (ret == -EDEADLK) {
4044                         drm_modeset_backoff(&ctx);
4045                         continue;
4046                 }
4047
4048                 break;
4049         }
4050
4051         drm_modeset_drop_locks(&ctx);
4052         drm_modeset_acquire_fini(&ctx);
4053         drm_WARN(encoder->base.dev, ret,
4054                  "Acquiring modeset locks failed with %i\n", ret);
4055
4056         /*
4057          * Unpowered type-c dongles can take some time to boot and be
4058          * responsible, so here giving some time to those dongles to power up
4059          * and then retrying the probe.
4060          *
4061          * On many platforms the HDMI live state signal is known to be
4062          * unreliable, so we can't use it to detect if a sink is connected or
4063          * not. Instead we detect if it's connected based on whether we can
4064          * read the EDID or not. That in turn has a problem during disconnect,
4065          * since the HPD interrupt may be raised before the DDC lines get
4066          * disconnected (due to how the required length of DDC vs. HPD
4067          * connector pins are specified) and so we'll still be able to get a
4068          * valid EDID. To solve this schedule another detection cycle if this
4069          * time around we didn't detect any change in the sink's connection
4070          * status.
4071          *
4072          * Type-c connectors which get their HPD signal deasserted then
4073          * reasserted, without unplugging/replugging the sink from the
4074          * connector, introduce a delay until the AUX channel communication
4075          * becomes functional. Retry the detection for 5 seconds on type-c
4076          * connectors to account for this delay.
4077          */
4078         if (state == INTEL_HOTPLUG_UNCHANGED &&
4079             connector->hotplug_retries < (is_tc ? 5 : 1) &&
4080             !dig_port->dp.is_mst)
4081                 state = INTEL_HOTPLUG_RETRY;
4082
4083         return state;
4084 }
4085
4086 static bool lpt_digital_port_connected(struct intel_encoder *encoder)
4087 {
4088         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
4089         u32 bit = dev_priv->display.hotplug.pch_hpd[encoder->hpd_pin];
4090
4091         return intel_de_read(dev_priv, SDEISR) & bit;
4092 }
4093
4094 static bool hsw_digital_port_connected(struct intel_encoder *encoder)
4095 {
4096         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
4097         u32 bit = dev_priv->display.hotplug.hpd[encoder->hpd_pin];
4098
4099         return intel_de_read(dev_priv, DEISR) & bit;
4100 }
4101
4102 static bool bdw_digital_port_connected(struct intel_encoder *encoder)
4103 {
4104         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
4105         u32 bit = dev_priv->display.hotplug.hpd[encoder->hpd_pin];
4106
4107         return intel_de_read(dev_priv, GEN8_DE_PORT_ISR) & bit;
4108 }
4109
4110 static struct intel_connector *
4111 intel_ddi_init_hdmi_connector(struct intel_digital_port *dig_port)
4112 {
4113         struct intel_connector *connector;
4114         enum port port = dig_port->base.port;
4115
4116         connector = intel_connector_alloc();
4117         if (!connector)
4118                 return NULL;
4119
4120         dig_port->hdmi.hdmi_reg = DDI_BUF_CTL(port);
4121         intel_hdmi_init_connector(dig_port, connector);
4122
4123         return connector;
4124 }
4125
4126 static bool intel_ddi_a_force_4_lanes(struct intel_digital_port *dig_port)
4127 {
4128         struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
4129
4130         if (dig_port->base.port != PORT_A)
4131                 return false;
4132
4133         if (dig_port->saved_port_bits & DDI_A_4_LANES)
4134                 return false;
4135
4136         /* Broxton/Geminilake: Bspec says that DDI_A_4_LANES is the only
4137          *                     supported configuration
4138          */
4139         if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv))
4140                 return true;
4141
4142         return false;
4143 }
4144
4145 static int
4146 intel_ddi_max_lanes(struct intel_digital_port *dig_port)
4147 {
4148         struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
4149         enum port port = dig_port->base.port;
4150         int max_lanes = 4;
4151
4152         if (DISPLAY_VER(dev_priv) >= 11)
4153                 return max_lanes;
4154
4155         if (port == PORT_A || port == PORT_E) {
4156                 if (intel_de_read(dev_priv, DDI_BUF_CTL(PORT_A)) & DDI_A_4_LANES)
4157                         max_lanes = port == PORT_A ? 4 : 0;
4158                 else
4159                         /* Both A and E share 2 lanes */
4160                         max_lanes = 2;
4161         }
4162
4163         /*
4164          * Some BIOS might fail to set this bit on port A if eDP
4165          * wasn't lit up at boot.  Force this bit set when needed
4166          * so we use the proper lane count for our calculations.
4167          */
4168         if (intel_ddi_a_force_4_lanes(dig_port)) {
4169                 drm_dbg_kms(&dev_priv->drm,
4170                             "Forcing DDI_A_4_LANES for port A\n");
4171                 dig_port->saved_port_bits |= DDI_A_4_LANES;
4172                 max_lanes = 4;
4173         }
4174
4175         return max_lanes;
4176 }
4177
4178 static enum hpd_pin xelpd_hpd_pin(struct drm_i915_private *dev_priv,
4179                                   enum port port)
4180 {
4181         if (port >= PORT_D_XELPD)
4182                 return HPD_PORT_D + port - PORT_D_XELPD;
4183         else if (port >= PORT_TC1)
4184                 return HPD_PORT_TC1 + port - PORT_TC1;
4185         else
4186                 return HPD_PORT_A + port - PORT_A;
4187 }
4188
4189 static enum hpd_pin dg1_hpd_pin(struct drm_i915_private *dev_priv,
4190                                 enum port port)
4191 {
4192         if (port >= PORT_TC1)
4193                 return HPD_PORT_C + port - PORT_TC1;
4194         else
4195                 return HPD_PORT_A + port - PORT_A;
4196 }
4197
4198 static enum hpd_pin tgl_hpd_pin(struct drm_i915_private *dev_priv,
4199                                 enum port port)
4200 {
4201         if (port >= PORT_TC1)
4202                 return HPD_PORT_TC1 + port - PORT_TC1;
4203         else
4204                 return HPD_PORT_A + port - PORT_A;
4205 }
4206
4207 static enum hpd_pin rkl_hpd_pin(struct drm_i915_private *dev_priv,
4208                                 enum port port)
4209 {
4210         if (HAS_PCH_TGP(dev_priv))
4211                 return tgl_hpd_pin(dev_priv, port);
4212
4213         if (port >= PORT_TC1)
4214                 return HPD_PORT_C + port - PORT_TC1;
4215         else
4216                 return HPD_PORT_A + port - PORT_A;
4217 }
4218
4219 static enum hpd_pin icl_hpd_pin(struct drm_i915_private *dev_priv,
4220                                 enum port port)
4221 {
4222         if (port >= PORT_C)
4223                 return HPD_PORT_TC1 + port - PORT_C;
4224         else
4225                 return HPD_PORT_A + port - PORT_A;
4226 }
4227
4228 static enum hpd_pin ehl_hpd_pin(struct drm_i915_private *dev_priv,
4229                                 enum port port)
4230 {
4231         if (port == PORT_D)
4232                 return HPD_PORT_A;
4233
4234         if (HAS_PCH_TGP(dev_priv))
4235                 return icl_hpd_pin(dev_priv, port);
4236
4237         return HPD_PORT_A + port - PORT_A;
4238 }
4239
4240 static enum hpd_pin skl_hpd_pin(struct drm_i915_private *dev_priv, enum port port)
4241 {
4242         if (HAS_PCH_TGP(dev_priv))
4243                 return icl_hpd_pin(dev_priv, port);
4244
4245         return HPD_PORT_A + port - PORT_A;
4246 }
4247
4248 static bool intel_ddi_is_tc(struct drm_i915_private *i915, enum port port)
4249 {
4250         if (DISPLAY_VER(i915) >= 12)
4251                 return port >= PORT_TC1;
4252         else if (DISPLAY_VER(i915) >= 11)
4253                 return port >= PORT_C;
4254         else
4255                 return false;
4256 }
4257
4258 static void intel_ddi_encoder_suspend(struct intel_encoder *encoder)
4259 {
4260         struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
4261         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
4262         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
4263         enum phy phy = intel_port_to_phy(i915, encoder->port);
4264
4265         intel_dp_encoder_suspend(encoder);
4266
4267         if (!intel_phy_is_tc(i915, phy))
4268                 return;
4269
4270         intel_tc_port_flush_work(dig_port);
4271 }
4272
4273 static void intel_ddi_encoder_shutdown(struct intel_encoder *encoder)
4274 {
4275         struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
4276         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
4277         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
4278         enum phy phy = intel_port_to_phy(i915, encoder->port);
4279
4280         intel_dp_encoder_shutdown(encoder);
4281         intel_hdmi_encoder_shutdown(encoder);
4282
4283         if (!intel_phy_is_tc(i915, phy))
4284                 return;
4285
4286         intel_tc_port_cleanup(dig_port);
4287 }
4288
4289 #define port_tc_name(port) ((port) - PORT_TC1 + '1')
4290 #define tc_port_name(tc_port) ((tc_port) - TC_PORT_1 + '1')
4291
4292 void intel_ddi_init(struct drm_i915_private *dev_priv, enum port port)
4293 {
4294         struct intel_digital_port *dig_port;
4295         struct intel_encoder *encoder;
4296         const struct intel_bios_encoder_data *devdata;
4297         bool init_hdmi, init_dp;
4298         enum phy phy = intel_port_to_phy(dev_priv, port);
4299
4300         /*
4301          * On platforms with HTI (aka HDPORT), if it's enabled at boot it may
4302          * have taken over some of the PHYs and made them unavailable to the
4303          * driver.  In that case we should skip initializing the corresponding
4304          * outputs.
4305          */
4306         if (intel_hti_uses_phy(dev_priv, phy)) {
4307                 drm_dbg_kms(&dev_priv->drm, "PORT %c / PHY %c reserved by HTI\n",
4308                             port_name(port), phy_name(phy));
4309                 return;
4310         }
4311
4312         devdata = intel_bios_encoder_data_lookup(dev_priv, port);
4313         if (!devdata) {
4314                 drm_dbg_kms(&dev_priv->drm,
4315                             "VBT says port %c is not present\n",
4316                             port_name(port));
4317                 return;
4318         }
4319
4320         init_hdmi = intel_bios_encoder_supports_dvi(devdata) ||
4321                 intel_bios_encoder_supports_hdmi(devdata);
4322         init_dp = intel_bios_encoder_supports_dp(devdata);
4323
4324         if (intel_bios_encoder_is_lspcon(devdata)) {
4325                 /*
4326                  * Lspcon device needs to be driven with DP connector
4327                  * with special detection sequence. So make sure DP
4328                  * is initialized before lspcon.
4329                  */
4330                 init_dp = true;
4331                 init_hdmi = false;
4332                 drm_dbg_kms(&dev_priv->drm, "VBT says port %c has lspcon\n",
4333                             port_name(port));
4334         }
4335
4336         if (!init_dp && !init_hdmi) {
4337                 drm_dbg_kms(&dev_priv->drm,
4338                             "VBT says port %c is not DVI/HDMI/DP compatible, respect it\n",
4339                             port_name(port));
4340                 return;
4341         }
4342
4343         if (intel_phy_is_snps(dev_priv, phy) &&
4344             dev_priv->display.snps.phy_failed_calibration & BIT(phy)) {
4345                 drm_dbg_kms(&dev_priv->drm,
4346                             "SNPS PHY %c failed to calibrate, proceeding anyway\n",
4347                             phy_name(phy));
4348         }
4349
4350         dig_port = kzalloc(sizeof(*dig_port), GFP_KERNEL);
4351         if (!dig_port)
4352                 return;
4353
4354         encoder = &dig_port->base;
4355         encoder->devdata = devdata;
4356
4357         if (DISPLAY_VER(dev_priv) >= 13 && port >= PORT_D_XELPD) {
4358                 drm_encoder_init(&dev_priv->drm, &encoder->base, &intel_ddi_funcs,
4359                                  DRM_MODE_ENCODER_TMDS,
4360                                  "DDI %c/PHY %c",
4361                                  port_name(port - PORT_D_XELPD + PORT_D),
4362                                  phy_name(phy));
4363         } else if (DISPLAY_VER(dev_priv) >= 12) {
4364                 enum tc_port tc_port = intel_port_to_tc(dev_priv, port);
4365
4366                 drm_encoder_init(&dev_priv->drm, &encoder->base, &intel_ddi_funcs,
4367                                  DRM_MODE_ENCODER_TMDS,
4368                                  "DDI %s%c/PHY %s%c",
4369                                  port >= PORT_TC1 ? "TC" : "",
4370                                  port >= PORT_TC1 ? port_tc_name(port) : port_name(port),
4371                                  tc_port != TC_PORT_NONE ? "TC" : "",
4372                                  tc_port != TC_PORT_NONE ? tc_port_name(tc_port) : phy_name(phy));
4373         } else if (DISPLAY_VER(dev_priv) >= 11) {
4374                 enum tc_port tc_port = intel_port_to_tc(dev_priv, port);
4375
4376                 drm_encoder_init(&dev_priv->drm, &encoder->base, &intel_ddi_funcs,
4377                                  DRM_MODE_ENCODER_TMDS,
4378                                  "DDI %c%s/PHY %s%c",
4379                                  port_name(port),
4380                                  port >= PORT_C ? " (TC)" : "",
4381                                  tc_port != TC_PORT_NONE ? "TC" : "",
4382                                  tc_port != TC_PORT_NONE ? tc_port_name(tc_port) : phy_name(phy));
4383         } else {
4384                 drm_encoder_init(&dev_priv->drm, &encoder->base, &intel_ddi_funcs,
4385                                  DRM_MODE_ENCODER_TMDS,
4386                                  "DDI %c/PHY %c", port_name(port),  phy_name(phy));
4387         }
4388
4389         mutex_init(&dig_port->hdcp_mutex);
4390         dig_port->num_hdcp_streams = 0;
4391
4392         encoder->hotplug = intel_ddi_hotplug;
4393         encoder->compute_output_type = intel_ddi_compute_output_type;
4394         encoder->compute_config = intel_ddi_compute_config;
4395         encoder->compute_config_late = intel_ddi_compute_config_late;
4396         encoder->enable = intel_enable_ddi;
4397         encoder->pre_pll_enable = intel_ddi_pre_pll_enable;
4398         encoder->pre_enable = intel_ddi_pre_enable;
4399         encoder->disable = intel_disable_ddi;
4400         encoder->post_pll_disable = intel_ddi_post_pll_disable;
4401         encoder->post_disable = intel_ddi_post_disable;
4402         encoder->update_pipe = intel_ddi_update_pipe;
4403         encoder->get_hw_state = intel_ddi_get_hw_state;
4404         encoder->sync_state = intel_ddi_sync_state;
4405         encoder->initial_fastset_check = intel_ddi_initial_fastset_check;
4406         encoder->suspend = intel_ddi_encoder_suspend;
4407         encoder->shutdown = intel_ddi_encoder_shutdown;
4408         encoder->get_power_domains = intel_ddi_get_power_domains;
4409
4410         encoder->type = INTEL_OUTPUT_DDI;
4411         encoder->power_domain = intel_display_power_ddi_lanes_domain(dev_priv, port);
4412         encoder->port = port;
4413         encoder->cloneable = 0;
4414         encoder->pipe_mask = ~0;
4415
4416         if (IS_DG2(dev_priv)) {
4417                 encoder->enable_clock = intel_mpllb_enable;
4418                 encoder->disable_clock = intel_mpllb_disable;
4419                 encoder->get_config = dg2_ddi_get_config;
4420         } else if (IS_ALDERLAKE_S(dev_priv)) {
4421                 encoder->enable_clock = adls_ddi_enable_clock;
4422                 encoder->disable_clock = adls_ddi_disable_clock;
4423                 encoder->is_clock_enabled = adls_ddi_is_clock_enabled;
4424                 encoder->get_config = adls_ddi_get_config;
4425         } else if (IS_ROCKETLAKE(dev_priv)) {
4426                 encoder->enable_clock = rkl_ddi_enable_clock;
4427                 encoder->disable_clock = rkl_ddi_disable_clock;
4428                 encoder->is_clock_enabled = rkl_ddi_is_clock_enabled;
4429                 encoder->get_config = rkl_ddi_get_config;
4430         } else if (IS_DG1(dev_priv)) {
4431                 encoder->enable_clock = dg1_ddi_enable_clock;
4432                 encoder->disable_clock = dg1_ddi_disable_clock;
4433                 encoder->is_clock_enabled = dg1_ddi_is_clock_enabled;
4434                 encoder->get_config = dg1_ddi_get_config;
4435         } else if (IS_JSL_EHL(dev_priv)) {
4436                 if (intel_ddi_is_tc(dev_priv, port)) {
4437                         encoder->enable_clock = jsl_ddi_tc_enable_clock;
4438                         encoder->disable_clock = jsl_ddi_tc_disable_clock;
4439                         encoder->is_clock_enabled = jsl_ddi_tc_is_clock_enabled;
4440                         encoder->port_pll_type = icl_ddi_tc_port_pll_type;
4441                         encoder->get_config = icl_ddi_combo_get_config;
4442                 } else {
4443                         encoder->enable_clock = icl_ddi_combo_enable_clock;
4444                         encoder->disable_clock = icl_ddi_combo_disable_clock;
4445                         encoder->is_clock_enabled = icl_ddi_combo_is_clock_enabled;
4446                         encoder->get_config = icl_ddi_combo_get_config;
4447                 }
4448         } else if (DISPLAY_VER(dev_priv) >= 11) {
4449                 if (intel_ddi_is_tc(dev_priv, port)) {
4450                         encoder->enable_clock = icl_ddi_tc_enable_clock;
4451                         encoder->disable_clock = icl_ddi_tc_disable_clock;
4452                         encoder->is_clock_enabled = icl_ddi_tc_is_clock_enabled;
4453                         encoder->port_pll_type = icl_ddi_tc_port_pll_type;
4454                         encoder->get_config = icl_ddi_tc_get_config;
4455                 } else {
4456                         encoder->enable_clock = icl_ddi_combo_enable_clock;
4457                         encoder->disable_clock = icl_ddi_combo_disable_clock;
4458                         encoder->is_clock_enabled = icl_ddi_combo_is_clock_enabled;
4459                         encoder->get_config = icl_ddi_combo_get_config;
4460                 }
4461         } else if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) {
4462                 /* BXT/GLK have fixed PLL->port mapping */
4463                 encoder->get_config = bxt_ddi_get_config;
4464         } else if (DISPLAY_VER(dev_priv) == 9) {
4465                 encoder->enable_clock = skl_ddi_enable_clock;
4466                 encoder->disable_clock = skl_ddi_disable_clock;
4467                 encoder->is_clock_enabled = skl_ddi_is_clock_enabled;
4468                 encoder->get_config = skl_ddi_get_config;
4469         } else if (IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv)) {
4470                 encoder->enable_clock = hsw_ddi_enable_clock;
4471                 encoder->disable_clock = hsw_ddi_disable_clock;
4472                 encoder->is_clock_enabled = hsw_ddi_is_clock_enabled;
4473                 encoder->get_config = hsw_ddi_get_config;
4474         }
4475
4476         if (IS_DG2(dev_priv)) {
4477                 encoder->set_signal_levels = intel_snps_phy_set_signal_levels;
4478         } else if (DISPLAY_VER(dev_priv) >= 12) {
4479                 if (intel_phy_is_combo(dev_priv, phy))
4480                         encoder->set_signal_levels = icl_combo_phy_set_signal_levels;
4481                 else
4482                         encoder->set_signal_levels = tgl_dkl_phy_set_signal_levels;
4483         } else if (DISPLAY_VER(dev_priv) >= 11) {
4484                 if (intel_phy_is_combo(dev_priv, phy))
4485                         encoder->set_signal_levels = icl_combo_phy_set_signal_levels;
4486                 else
4487                         encoder->set_signal_levels = icl_mg_phy_set_signal_levels;
4488         } else if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) {
4489                 encoder->set_signal_levels = bxt_ddi_phy_set_signal_levels;
4490         } else {
4491                 encoder->set_signal_levels = hsw_set_signal_levels;
4492         }
4493
4494         intel_ddi_buf_trans_init(encoder);
4495
4496         if (DISPLAY_VER(dev_priv) >= 13)
4497                 encoder->hpd_pin = xelpd_hpd_pin(dev_priv, port);
4498         else if (IS_DG1(dev_priv))
4499                 encoder->hpd_pin = dg1_hpd_pin(dev_priv, port);
4500         else if (IS_ROCKETLAKE(dev_priv))
4501                 encoder->hpd_pin = rkl_hpd_pin(dev_priv, port);
4502         else if (DISPLAY_VER(dev_priv) >= 12)
4503                 encoder->hpd_pin = tgl_hpd_pin(dev_priv, port);
4504         else if (IS_JSL_EHL(dev_priv))
4505                 encoder->hpd_pin = ehl_hpd_pin(dev_priv, port);
4506         else if (DISPLAY_VER(dev_priv) == 11)
4507                 encoder->hpd_pin = icl_hpd_pin(dev_priv, port);
4508         else if (DISPLAY_VER(dev_priv) == 9 && !IS_BROXTON(dev_priv))
4509                 encoder->hpd_pin = skl_hpd_pin(dev_priv, port);
4510         else
4511                 encoder->hpd_pin = intel_hpd_pin_default(dev_priv, port);
4512
4513         if (DISPLAY_VER(dev_priv) >= 11)
4514                 dig_port->saved_port_bits =
4515                         intel_de_read(dev_priv, DDI_BUF_CTL(port))
4516                         & DDI_BUF_PORT_REVERSAL;
4517         else
4518                 dig_port->saved_port_bits =
4519                         intel_de_read(dev_priv, DDI_BUF_CTL(port))
4520                         & (DDI_BUF_PORT_REVERSAL | DDI_A_4_LANES);
4521
4522         if (intel_bios_encoder_lane_reversal(devdata))
4523                 dig_port->saved_port_bits |= DDI_BUF_PORT_REVERSAL;
4524
4525         dig_port->dp.output_reg = INVALID_MMIO_REG;
4526         dig_port->max_lanes = intel_ddi_max_lanes(dig_port);
4527         dig_port->aux_ch = intel_dp_aux_ch(encoder);
4528
4529         if (intel_phy_is_tc(dev_priv, phy)) {
4530                 bool is_legacy =
4531                         !intel_bios_encoder_supports_typec_usb(devdata) &&
4532                         !intel_bios_encoder_supports_tbt(devdata);
4533
4534                 if (!is_legacy && init_hdmi) {
4535                         is_legacy = !init_dp;
4536
4537                         drm_dbg_kms(&dev_priv->drm,
4538                                     "VBT says port %c is non-legacy TC and has HDMI (with DP: %s), assume it's %s\n",
4539                                     port_name(port),
4540                                     str_yes_no(init_dp),
4541                                     is_legacy ? "legacy" : "non-legacy");
4542                 }
4543
4544                 if (intel_tc_port_init(dig_port, is_legacy) < 0)
4545                         goto err;
4546         }
4547
4548         drm_WARN_ON(&dev_priv->drm, port > PORT_I);
4549         dig_port->ddi_io_power_domain = intel_display_power_ddi_io_domain(dev_priv, port);
4550
4551         if (DISPLAY_VER(dev_priv) >= 11) {
4552                 if (intel_phy_is_tc(dev_priv, phy))
4553                         dig_port->connected = intel_tc_port_connected;
4554                 else
4555                         dig_port->connected = lpt_digital_port_connected;
4556         } else if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) {
4557                 dig_port->connected = bdw_digital_port_connected;
4558         } else if (DISPLAY_VER(dev_priv) == 9) {
4559                 dig_port->connected = lpt_digital_port_connected;
4560         } else if (IS_BROADWELL(dev_priv)) {
4561                 if (port == PORT_A)
4562                         dig_port->connected = bdw_digital_port_connected;
4563                 else
4564                         dig_port->connected = lpt_digital_port_connected;
4565         } else if (IS_HASWELL(dev_priv)) {
4566                 if (port == PORT_A)
4567                         dig_port->connected = hsw_digital_port_connected;
4568                 else
4569                         dig_port->connected = lpt_digital_port_connected;
4570         }
4571
4572         intel_infoframe_init(dig_port);
4573
4574         if (init_dp) {
4575                 if (!intel_ddi_init_dp_connector(dig_port))
4576                         goto err;
4577
4578                 dig_port->hpd_pulse = intel_dp_hpd_pulse;
4579
4580                 if (dig_port->dp.mso_link_count)
4581                         encoder->pipe_mask = intel_ddi_splitter_pipe_mask(dev_priv);
4582         }
4583
4584         /*
4585          * In theory we don't need the encoder->type check,
4586          * but leave it just in case we have some really bad VBTs...
4587          */
4588         if (encoder->type != INTEL_OUTPUT_EDP && init_hdmi) {
4589                 if (!intel_ddi_init_hdmi_connector(dig_port))
4590                         goto err;
4591         }
4592
4593         return;
4594
4595 err:
4596         drm_encoder_cleanup(&encoder->base);
4597         kfree(dig_port);
4598 }