drivers/gpu/drm/i915/display/intel_atomic_plane.c

   1 /*
   2  * Copyright © 2014 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  21  * DEALINGS IN THE SOFTWARE.
  22  */
  23
  24 /**
  25  * DOC: atomic plane helpers
  26  *
  27  * The functions here are used by the atomic plane helper functions to
  28  * implement legacy plane updates (i.e., drm_plane->update_plane() and
  29  * drm_plane->disable_plane()).  This allows plane updates to use the
  30  * atomic state infrastructure and perform plane updates as separate
  31  * prepare/check/commit/cleanup steps.
  32  */
  33
  34 #include <drm/drm_atomic_helper.h>
  35 #include <drm/drm_blend.h>
  36 #include <drm/drm_fourcc.h>
  37
  38 #include "i915_config.h"
  39 #include "intel_atomic_plane.h"
  40 #include "intel_cdclk.h"
  41 #include "intel_display_rps.h"
  42 #include "intel_display_trace.h"
  43 #include "intel_display_types.h"
  44 #include "intel_fb.h"
  45 #include "intel_fb_pin.h"
  46 #include "skl_scaler.h"
  47 #include "skl_watermark.h"
  48
  49 static void intel_plane_state_reset(struct intel_plane_state *plane_state,
  50                                     struct intel_plane *plane)
  51 {
  52         memset(plane_state, 0, sizeof(*plane_state));
  53
  54         __drm_atomic_helper_plane_state_reset(&plane_state->uapi, &plane->base);
  55
  56         plane_state->scaler_id = -1;
  57 }
  58
  59 struct intel_plane *intel_plane_alloc(void)
  60 {
  61         struct intel_plane_state *plane_state;
  62         struct intel_plane *plane;
  63
  64         plane = kzalloc(sizeof(*plane), GFP_KERNEL);
  65         if (!plane)
  66                 return ERR_PTR(-ENOMEM);
  67
  68         plane_state = kzalloc(sizeof(*plane_state), GFP_KERNEL);
  69         if (!plane_state) {
  70                 kfree(plane);
  71                 return ERR_PTR(-ENOMEM);
  72         }
  73
  74         intel_plane_state_reset(plane_state, plane);
  75
  76         plane->base.state = &plane_state->uapi;
  77
  78         return plane;
  79 }
  80
  81 void intel_plane_free(struct intel_plane *plane)
  82 {
  83         intel_plane_destroy_state(&plane->base, plane->base.state);
  84         kfree(plane);
  85 }
  86
  87 /**
  88  * intel_plane_duplicate_state - duplicate plane state
  89  * @plane: drm plane
  90  *
  91  * Allocates and returns a copy of the plane state (both common and
  92  * Intel-specific) for the specified plane.
  93  *
  94  * Returns: The newly allocated plane state, or NULL on failure.
  95  */
  96 struct drm_plane_state *
  97 intel_plane_duplicate_state(struct drm_plane *plane)
  98 {
  99         struct intel_plane_state *intel_state;
 100
 101         intel_state = to_intel_plane_state(plane->state);
 102         intel_state = kmemdup(intel_state, sizeof(*intel_state), GFP_KERNEL);
 103
 104         if (!intel_state)
 105                 return NULL;
 106
 107         __drm_atomic_helper_plane_duplicate_state(plane, &intel_state->uapi);
 108
 109         intel_state->ggtt_vma = NULL;
 110         intel_state->dpt_vma = NULL;
 111         intel_state->flags = 0;
 112
 113         /* add reference to fb */
 114         if (intel_state->hw.fb)
 115                 drm_framebuffer_get(intel_state->hw.fb);
 116
 117         return &intel_state->uapi;
 118 }
 119
 120 /**
 121  * intel_plane_destroy_state - destroy plane state
 122  * @plane: drm plane
 123  * @state: state object to destroy
 124  *
 125  * Destroys the plane state (both common and Intel-specific) for the
 126  * specified plane.
 127  */
 128 void
 129 intel_plane_destroy_state(struct drm_plane *plane,
 130                           struct drm_plane_state *state)
 131 {
 132         struct intel_plane_state *plane_state = to_intel_plane_state(state);
 133
 134         drm_WARN_ON(plane->dev, plane_state->ggtt_vma);
 135         drm_WARN_ON(plane->dev, plane_state->dpt_vma);
 136
 137         __drm_atomic_helper_plane_destroy_state(&plane_state->uapi);
 138         if (plane_state->hw.fb)
 139                 drm_framebuffer_put(plane_state->hw.fb);
 140         kfree(plane_state);
 141 }
 142
 143 unsigned int intel_adjusted_rate(const struct drm_rect *src,
 144                                  const struct drm_rect *dst,
 145                                  unsigned int rate)
 146 {
 147         unsigned int src_w, src_h, dst_w, dst_h;
 148
 149         src_w = drm_rect_width(src) >> 16;
 150         src_h = drm_rect_height(src) >> 16;
 151         dst_w = drm_rect_width(dst);
 152         dst_h = drm_rect_height(dst);
 153
 154         /* Downscaling limits the maximum pixel rate */
 155         dst_w = min(src_w, dst_w);
 156         dst_h = min(src_h, dst_h);
 157
 158         return DIV_ROUND_UP_ULL(mul_u32_u32(rate, src_w * src_h),
 159                                 dst_w * dst_h);
 160 }
 161
 162 unsigned int intel_plane_pixel_rate(const struct intel_crtc_state *crtc_state,
 163                                     const struct intel_plane_state *plane_state)
 164 {
 165         /*
 166          * Note we don't check for plane visibility here as
 167          * we want to use this when calculating the cursor
 168          * watermarks even if the cursor is fully offscreen.
 169          * That depends on the src/dst rectangles being
 170          * correctly populated whenever the watermark code
 171          * considers the cursor to be visible, whether or not
 172          * it is actually visible.
 173          *
 174          * See: intel_wm_plane_visible() and intel_check_cursor()
 175          */
 176
 177         return intel_adjusted_rate(&plane_state->uapi.src,
 178                                    &plane_state->uapi.dst,
 179                                    crtc_state->pixel_rate);
 180 }
 181
 182 unsigned int intel_plane_data_rate(const struct intel_crtc_state *crtc_state,
 183                                    const struct intel_plane_state *plane_state,
 184                                    int color_plane)
 185 {
 186         const struct drm_framebuffer *fb = plane_state->hw.fb;
 187
 188         if (!plane_state->uapi.visible)
 189                 return 0;
 190
 191         return intel_plane_pixel_rate(crtc_state, plane_state) *
 192                 fb->format->cpp[color_plane];
 193 }
 194
 195 static bool
 196 use_min_ddb(const struct intel_crtc_state *crtc_state,
 197             struct intel_plane *plane)
 198 {
 199         struct drm_i915_private *i915 = to_i915(plane->base.dev);
 200
 201         return DISPLAY_VER(i915) >= 13 &&
 202                crtc_state->uapi.async_flip &&
 203                plane->async_flip;
 204 }
 205
 206 static unsigned int
 207 intel_plane_relative_data_rate(const struct intel_crtc_state *crtc_state,
 208                                const struct intel_plane_state *plane_state,
 209                                int color_plane)
 210 {
 211         struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);
 212         const struct drm_framebuffer *fb = plane_state->hw.fb;
 213         int width, height;
 214
 215         if (plane->id == PLANE_CURSOR)
 216                 return 0;
 217
 218         if (!plane_state->uapi.visible)
 219                 return 0;
 220
 221         /*
 222          * We calculate extra ddb based on ratio plane rate/total data rate
 223          * in case, in some cases we should not allocate extra ddb for the plane,
 224          * so do not count its data rate, if this is the case.
 225          */
 226         if (use_min_ddb(crtc_state, plane))
 227                 return 0;
 228
 229         /*
 230          * Src coordinates are already rotated by 270 degrees for
 231          * the 90/270 degree plane rotation cases (to match the
 232          * GTT mapping), hence no need to account for rotation here.
 233          */
 234         width = drm_rect_width(&plane_state->uapi.src) >> 16;
 235         height = drm_rect_height(&plane_state->uapi.src) >> 16;
 236
 237         /* UV plane does 1/2 pixel sub-sampling */
 238         if (color_plane == 1) {
 239                 width /= 2;
 240                 height /= 2;
 241         }
 242
 243         return width * height * fb->format->cpp[color_plane];
 244 }
 245
 246 int intel_plane_calc_min_cdclk(struct intel_atomic_state *state,
 247                                struct intel_plane *plane,
 248                                bool *need_cdclk_calc)
 249 {
 250         struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
 251         const struct intel_plane_state *plane_state =
 252                 intel_atomic_get_new_plane_state(state, plane);
 253         struct intel_crtc *crtc = to_intel_crtc(plane_state->hw.crtc);
 254         const struct intel_cdclk_state *cdclk_state;
 255         const struct intel_crtc_state *old_crtc_state;
 256         struct intel_crtc_state *new_crtc_state;
 257
 258         if (!plane_state->uapi.visible || !plane->min_cdclk)
 259                 return 0;
 260
 261         old_crtc_state = intel_atomic_get_old_crtc_state(state, crtc);
 262         new_crtc_state = intel_atomic_get_new_crtc_state(state, crtc);
 263
 264         new_crtc_state->min_cdclk[plane->id] =
 265                 plane->min_cdclk(new_crtc_state, plane_state);
 266
 267         /*
 268          * No need to check against the cdclk state if
 269          * the min cdclk for the plane doesn't increase.
 270          *
 271          * Ie. we only ever increase the cdclk due to plane
 272          * requirements. This can reduce back and forth
 273          * display blinking due to constant cdclk changes.
 274          */
 275         if (new_crtc_state->min_cdclk[plane->id] <=
 276             old_crtc_state->min_cdclk[plane->id])
 277                 return 0;
 278
 279         cdclk_state = intel_atomic_get_cdclk_state(state);
 280         if (IS_ERR(cdclk_state))
 281                 return PTR_ERR(cdclk_state);
 282
 283         /*
 284          * No need to recalculate the cdclk state if
 285          * the min cdclk for the pipe doesn't increase.
 286          *
 287          * Ie. we only ever increase the cdclk due to plane
 288          * requirements. This can reduce back and forth
 289          * display blinking due to constant cdclk changes.
 290          */
 291         if (new_crtc_state->min_cdclk[plane->id] <=
 292             cdclk_state->min_cdclk[crtc->pipe])
 293                 return 0;
 294
 295         drm_dbg_kms(&dev_priv->drm,
 296                     "[PLANE:%d:%s] min cdclk (%d kHz) > [CRTC:%d:%s] min cdclk (%d kHz)\n",
 297                     plane->base.base.id, plane->base.name,
 298                     new_crtc_state->min_cdclk[plane->id],
 299                     crtc->base.base.id, crtc->base.name,
 300                     cdclk_state->min_cdclk[crtc->pipe]);
 301         *need_cdclk_calc = true;
 302
 303         return 0;
 304 }
 305
 306 static void intel_plane_clear_hw_state(struct intel_plane_state *plane_state)
 307 {
 308         if (plane_state->hw.fb)
 309                 drm_framebuffer_put(plane_state->hw.fb);
 310
 311         memset(&plane_state->hw, 0, sizeof(plane_state->hw));
 312 }
 313
 314 void intel_plane_copy_uapi_to_hw_state(struct intel_plane_state *plane_state,
 315                                        const struct intel_plane_state *from_plane_state,
 316                                        struct intel_crtc *crtc)
 317 {
 318         intel_plane_clear_hw_state(plane_state);
 319
 320         /*
 321          * For the bigjoiner slave uapi.crtc will point at
 322          * the master crtc. So we explicitly assign the right
 323          * slave crtc to hw.crtc. uapi.crtc!=NULL simply indicates
 324          * the plane is logically enabled on the uapi level.
 325          */
 326         plane_state->hw.crtc = from_plane_state->uapi.crtc ? &crtc->base : NULL;
 327
 328         plane_state->hw.fb = from_plane_state->uapi.fb;
 329         if (plane_state->hw.fb)
 330                 drm_framebuffer_get(plane_state->hw.fb);
 331
 332         plane_state->hw.alpha = from_plane_state->uapi.alpha;
 333         plane_state->hw.pixel_blend_mode =
 334                 from_plane_state->uapi.pixel_blend_mode;
 335         plane_state->hw.rotation = from_plane_state->uapi.rotation;
 336         plane_state->hw.color_encoding = from_plane_state->uapi.color_encoding;
 337         plane_state->hw.color_range = from_plane_state->uapi.color_range;
 338         plane_state->hw.scaling_filter = from_plane_state->uapi.scaling_filter;
 339
 340         plane_state->uapi.src = drm_plane_state_src(&from_plane_state->uapi);
 341         plane_state->uapi.dst = drm_plane_state_dest(&from_plane_state->uapi);
 342 }
 343
 344 void intel_plane_copy_hw_state(struct intel_plane_state *plane_state,
 345                                const struct intel_plane_state *from_plane_state)
 346 {
 347         intel_plane_clear_hw_state(plane_state);
 348
 349         memcpy(&plane_state->hw, &from_plane_state->hw,
 350                sizeof(plane_state->hw));
 351
 352         if (plane_state->hw.fb)
 353                 drm_framebuffer_get(plane_state->hw.fb);
 354 }
 355
 356 void intel_plane_set_invisible(struct intel_crtc_state *crtc_state,
 357                                struct intel_plane_state *plane_state)
 358 {
 359         struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);
 360
 361         crtc_state->active_planes &= ~BIT(plane->id);
 362         crtc_state->scaled_planes &= ~BIT(plane->id);
 363         crtc_state->nv12_planes &= ~BIT(plane->id);
 364         crtc_state->c8_planes &= ~BIT(plane->id);
 365         crtc_state->async_flip_planes &= ~BIT(plane->id);
 366         crtc_state->data_rate[plane->id] = 0;
 367         crtc_state->data_rate_y[plane->id] = 0;
 368         crtc_state->rel_data_rate[plane->id] = 0;
 369         crtc_state->rel_data_rate_y[plane->id] = 0;
 370         crtc_state->min_cdclk[plane->id] = 0;
 371
 372         plane_state->uapi.visible = false;
 373 }
 374
 375 /* FIXME nuke when all wm code is atomic */
 376 static bool intel_wm_need_update(const struct intel_plane_state *cur,
 377                                  struct intel_plane_state *new)
 378 {
 379         /* Update watermarks on tiling or size changes. */
 380         if (new->uapi.visible != cur->uapi.visible)
 381                 return true;
 382
 383         if (!cur->hw.fb || !new->hw.fb)
 384                 return false;
 385
 386         if (cur->hw.fb->modifier != new->hw.fb->modifier ||
 387             cur->hw.rotation != new->hw.rotation ||
 388             drm_rect_width(&new->uapi.src) != drm_rect_width(&cur->uapi.src) ||
 389             drm_rect_height(&new->uapi.src) != drm_rect_height(&cur->uapi.src) ||
 390             drm_rect_width(&new->uapi.dst) != drm_rect_width(&cur->uapi.dst) ||
 391             drm_rect_height(&new->uapi.dst) != drm_rect_height(&cur->uapi.dst))
 392                 return true;
 393
 394         return false;
 395 }
 396
 397 static bool intel_plane_is_scaled(const struct intel_plane_state *plane_state)
 398 {
 399         int src_w = drm_rect_width(&plane_state->uapi.src) >> 16;
 400         int src_h = drm_rect_height(&plane_state->uapi.src) >> 16;
 401         int dst_w = drm_rect_width(&plane_state->uapi.dst);
 402         int dst_h = drm_rect_height(&plane_state->uapi.dst);
 403
 404         return src_w != dst_w || src_h != dst_h;
 405 }
 406
 407 static bool intel_plane_do_async_flip(struct intel_plane *plane,
 408                                       const struct intel_crtc_state *old_crtc_state,
 409                                       const struct intel_crtc_state *new_crtc_state)
 410 {
 411         struct drm_i915_private *i915 = to_i915(plane->base.dev);
 412
 413         if (!plane->async_flip)
 414                 return false;
 415
 416         if (!new_crtc_state->uapi.async_flip)
 417                 return false;
 418
 419         /*
 420          * In platforms after DISPLAY13, we might need to override
 421          * first async flip in order to change watermark levels
 422          * as part of optimization.
 423          * So for those, we are checking if this is a first async flip.
 424          * For platforms earlier than DISPLAY13 we always do async flip.
 425          */
 426         return DISPLAY_VER(i915) < 13 || old_crtc_state->uapi.async_flip;
 427 }
 428
 429 static bool i9xx_must_disable_cxsr(const struct intel_crtc_state *new_crtc_state,
 430                                    const struct intel_plane_state *old_plane_state,
 431                                    const struct intel_plane_state *new_plane_state)
 432 {
 433         struct intel_plane *plane = to_intel_plane(new_plane_state->uapi.plane);
 434         bool old_visible = old_plane_state->uapi.visible;
 435         bool new_visible = new_plane_state->uapi.visible;
 436         u32 old_ctl = old_plane_state->ctl;
 437         u32 new_ctl = new_plane_state->ctl;
 438         bool modeset, turn_on, turn_off;
 439
 440         if (plane->id == PLANE_CURSOR)
 441                 return false;
 442
 443         modeset = intel_crtc_needs_modeset(new_crtc_state);
 444         turn_off = old_visible && (!new_visible || modeset);
 445         turn_on = new_visible && (!old_visible || modeset);
 446
 447         /* Must disable CxSR around plane enable/disable */
 448         if (turn_on || turn_off)
 449                 return true;
 450
 451         if (!old_visible || !new_visible)
 452                 return false;
 453
 454         /*
 455          * Most plane control register updates are blocked while in CxSR.
 456          *
 457          * Tiling mode is one exception where the primary plane can
 458          * apparently handle it, whereas the sprites can not (the
 459          * sprite issue being only relevant on VLV/CHV where CxSR
 460          * is actually possible with a sprite enabled).
 461          */
 462         if (plane->id == PLANE_PRIMARY) {
 463                 old_ctl &= ~DISP_TILED;
 464                 new_ctl &= ~DISP_TILED;
 465         }
 466
 467         return old_ctl != new_ctl;
 468 }
 469
 470 static int intel_plane_atomic_calc_changes(const struct intel_crtc_state *old_crtc_state,
 471                                            struct intel_crtc_state *new_crtc_state,
 472                                            const struct intel_plane_state *old_plane_state,
 473                                            struct intel_plane_state *new_plane_state)
 474 {
 475         struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->uapi.crtc);
 476         struct intel_plane *plane = to_intel_plane(new_plane_state->uapi.plane);
 477         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 478         bool mode_changed = intel_crtc_needs_modeset(new_crtc_state);
 479         bool was_crtc_enabled = old_crtc_state->hw.active;
 480         bool is_crtc_enabled = new_crtc_state->hw.active;
 481         bool turn_off, turn_on, visible, was_visible;
 482         int ret;
 483
 484         if (DISPLAY_VER(dev_priv) >= 9 && plane->id != PLANE_CURSOR) {
 485                 ret = skl_update_scaler_plane(new_crtc_state, new_plane_state);
 486                 if (ret)
 487                         return ret;
 488         }
 489
 490         was_visible = old_plane_state->uapi.visible;
 491         visible = new_plane_state->uapi.visible;
 492
 493         if (!was_crtc_enabled && drm_WARN_ON(&dev_priv->drm, was_visible))
 494                 was_visible = false;
 495
 496         /*
 497          * Visibility is calculated as if the crtc was on, but
 498          * after scaler setup everything depends on it being off
 499          * when the crtc isn't active.
 500          *
 501          * FIXME this is wrong for watermarks. Watermarks should also
 502          * be computed as if the pipe would be active. Perhaps move
 503          * per-plane wm computation to the .check_plane() hook, and
 504          * only combine the results from all planes in the current place?
 505          */
 506         if (!is_crtc_enabled) {
 507                 intel_plane_set_invisible(new_crtc_state, new_plane_state);
 508                 visible = false;
 509         }
 510
 511         if (!was_visible && !visible)
 512                 return 0;
 513
 514         turn_off = was_visible && (!visible || mode_changed);
 515         turn_on = visible && (!was_visible || mode_changed);
 516
 517         drm_dbg_atomic(&dev_priv->drm,
 518                        "[CRTC:%d:%s] with [PLANE:%d:%s] visible %i -> %i, off %i, on %i, ms %i\n",
 519                        crtc->base.base.id, crtc->base.name,
 520                        plane->base.base.id, plane->base.name,
 521                        was_visible, visible,
 522                        turn_off, turn_on, mode_changed);
 523
 524         if (turn_on) {
 525                 if (DISPLAY_VER(dev_priv) < 5 && !IS_G4X(dev_priv))
 526                         new_crtc_state->update_wm_pre = true;
 527         } else if (turn_off) {
 528                 if (DISPLAY_VER(dev_priv) < 5 && !IS_G4X(dev_priv))
 529                         new_crtc_state->update_wm_post = true;
 530         } else if (intel_wm_need_update(old_plane_state, new_plane_state)) {
 531                 if (DISPLAY_VER(dev_priv) < 5 && !IS_G4X(dev_priv)) {
 532                         /* FIXME bollocks */
 533                         new_crtc_state->update_wm_pre = true;
 534                         new_crtc_state->update_wm_post = true;
 535                 }
 536         }
 537
 538         if (visible || was_visible)
 539                 new_crtc_state->fb_bits |= plane->frontbuffer_bit;
 540
 541         if (HAS_GMCH(dev_priv) &&
 542             i9xx_must_disable_cxsr(new_crtc_state, old_plane_state, new_plane_state))
 543                 new_crtc_state->disable_cxsr = true;
 544
 545         /*
 546          * ILK/SNB DVSACNTR/Sprite Enable
 547          * IVB SPR_CTL/Sprite Enable
 548          * "When in Self Refresh Big FIFO mode, a write to enable the
 549          *  plane will be internally buffered and delayed while Big FIFO
 550          *  mode is exiting."
 551          *
 552          * Which means that enabling the sprite can take an extra frame
 553          * when we start in big FIFO mode (LP1+). Thus we need to drop
 554          * down to LP0 and wait for vblank in order to make sure the
 555          * sprite gets enabled on the next vblank after the register write.
 556          * Doing otherwise would risk enabling the sprite one frame after
 557          * we've already signalled flip completion. We can resume LP1+
 558          * once the sprite has been enabled.
 559          *
 560          *
 561          * WaCxSRDisabledForSpriteScaling:ivb
 562          * IVB SPR_SCALE/Scaling Enable
 563          * "Low Power watermarks must be disabled for at least one
 564          *  frame before enabling sprite scaling, and kept disabled
 565          *  until sprite scaling is disabled."
 566          *
 567          * ILK/SNB DVSASCALE/Scaling Enable
 568          * "When in Self Refresh Big FIFO mode, scaling enable will be
 569          *  masked off while Big FIFO mode is exiting."
 570          *
 571          * Despite the w/a only being listed for IVB we assume that
 572          * the ILK/SNB note has similar ramifications, hence we apply
 573          * the w/a on all three platforms.
 574          *
 575          * With experimental results seems this is needed also for primary
 576          * plane, not only sprite plane.
 577          */
 578         if (plane->id != PLANE_CURSOR &&
 579             (IS_IRONLAKE(dev_priv) || IS_SANDYBRIDGE(dev_priv) ||
 580              IS_IVYBRIDGE(dev_priv)) &&
 581             (turn_on || (!intel_plane_is_scaled(old_plane_state) &&
 582                          intel_plane_is_scaled(new_plane_state))))
 583                 new_crtc_state->disable_lp_wm = true;
 584
 585         if (intel_plane_do_async_flip(plane, old_crtc_state, new_crtc_state)) {
 586                 new_crtc_state->do_async_flip = true;
 587                 new_crtc_state->async_flip_planes |= BIT(plane->id);
 588         }
 589
 590         return 0;
 591 }
 592
 593 int intel_plane_atomic_check_with_state(const struct intel_crtc_state *old_crtc_state,
 594                                         struct intel_crtc_state *new_crtc_state,
 595                                         const struct intel_plane_state *old_plane_state,
 596                                         struct intel_plane_state *new_plane_state)
 597 {
 598         struct intel_plane *plane = to_intel_plane(new_plane_state->uapi.plane);
 599         const struct drm_framebuffer *fb = new_plane_state->hw.fb;
 600         int ret;
 601
 602         intel_plane_set_invisible(new_crtc_state, new_plane_state);
 603         new_crtc_state->enabled_planes &= ~BIT(plane->id);
 604
 605         if (!new_plane_state->hw.crtc && !old_plane_state->hw.crtc)
 606                 return 0;
 607
 608         ret = plane->check_plane(new_crtc_state, new_plane_state);
 609         if (ret)
 610                 return ret;
 611
 612         if (fb)
 613                 new_crtc_state->enabled_planes |= BIT(plane->id);
 614
 615         /* FIXME pre-g4x don't work like this */
 616         if (new_plane_state->uapi.visible)
 617                 new_crtc_state->active_planes |= BIT(plane->id);
 618
 619         if (new_plane_state->uapi.visible &&
 620             intel_plane_is_scaled(new_plane_state))
 621                 new_crtc_state->scaled_planes |= BIT(plane->id);
 622
 623         if (new_plane_state->uapi.visible &&
 624             intel_format_info_is_yuv_semiplanar(fb->format, fb->modifier))
 625                 new_crtc_state->nv12_planes |= BIT(plane->id);
 626
 627         if (new_plane_state->uapi.visible &&
 628             fb->format->format == DRM_FORMAT_C8)
 629                 new_crtc_state->c8_planes |= BIT(plane->id);
 630
 631         if (new_plane_state->uapi.visible || old_plane_state->uapi.visible)
 632                 new_crtc_state->update_planes |= BIT(plane->id);
 633
 634         if (new_plane_state->uapi.visible &&
 635             intel_format_info_is_yuv_semiplanar(fb->format, fb->modifier)) {
 636                 new_crtc_state->data_rate_y[plane->id] =
 637                         intel_plane_data_rate(new_crtc_state, new_plane_state, 0);
 638                 new_crtc_state->data_rate[plane->id] =
 639                         intel_plane_data_rate(new_crtc_state, new_plane_state, 1);
 640
 641                 new_crtc_state->rel_data_rate_y[plane->id] =
 642                         intel_plane_relative_data_rate(new_crtc_state,
 643                                                        new_plane_state, 0);
 644                 new_crtc_state->rel_data_rate[plane->id] =
 645                         intel_plane_relative_data_rate(new_crtc_state,
 646                                                        new_plane_state, 1);
 647         } else if (new_plane_state->uapi.visible) {
 648                 new_crtc_state->data_rate[plane->id] =
 649                         intel_plane_data_rate(new_crtc_state, new_plane_state, 0);
 650
 651                 new_crtc_state->rel_data_rate[plane->id] =
 652                         intel_plane_relative_data_rate(new_crtc_state,
 653                                                        new_plane_state, 0);
 654         }
 655
 656         return intel_plane_atomic_calc_changes(old_crtc_state, new_crtc_state,
 657                                                old_plane_state, new_plane_state);
 658 }
 659
 660 static struct intel_plane *
 661 intel_crtc_get_plane(struct intel_crtc *crtc, enum plane_id plane_id)
 662 {
 663         struct drm_i915_private *i915 = to_i915(crtc->base.dev);
 664         struct intel_plane *plane;
 665
 666         for_each_intel_plane_on_crtc(&i915->drm, crtc, plane) {
 667                 if (plane->id == plane_id)
 668                         return plane;
 669         }
 670
 671         return NULL;
 672 }
 673
 674 int intel_plane_atomic_check(struct intel_atomic_state *state,
 675                              struct intel_plane *plane)
 676 {
 677         struct drm_i915_private *i915 = to_i915(state->base.dev);
 678         struct intel_plane_state *new_plane_state =
 679                 intel_atomic_get_new_plane_state(state, plane);
 680         const struct intel_plane_state *old_plane_state =
 681                 intel_atomic_get_old_plane_state(state, plane);
 682         const struct intel_plane_state *new_master_plane_state;
 683         struct intel_crtc *crtc = intel_crtc_for_pipe(i915, plane->pipe);
 684         const struct intel_crtc_state *old_crtc_state =
 685                 intel_atomic_get_old_crtc_state(state, crtc);
 686         struct intel_crtc_state *new_crtc_state =
 687                 intel_atomic_get_new_crtc_state(state, crtc);
 688
 689         if (new_crtc_state && intel_crtc_is_bigjoiner_slave(new_crtc_state)) {
 690                 struct intel_crtc *master_crtc =
 691                         intel_master_crtc(new_crtc_state);
 692                 struct intel_plane *master_plane =
 693                         intel_crtc_get_plane(master_crtc, plane->id);
 694
 695                 new_master_plane_state =
 696                         intel_atomic_get_new_plane_state(state, master_plane);
 697         } else {
 698                 new_master_plane_state = new_plane_state;
 699         }
 700
 701         intel_plane_copy_uapi_to_hw_state(new_plane_state,
 702                                           new_master_plane_state,
 703                                           crtc);
 704
 705         new_plane_state->uapi.visible = false;
 706         if (!new_crtc_state)
 707                 return 0;
 708
 709         return intel_plane_atomic_check_with_state(old_crtc_state,
 710                                                    new_crtc_state,
 711                                                    old_plane_state,
 712                                                    new_plane_state);
 713 }
 714
 715 static struct intel_plane *
 716 skl_next_plane_to_commit(struct intel_atomic_state *state,
 717                          struct intel_crtc *crtc,
 718                          struct skl_ddb_entry ddb[I915_MAX_PLANES],
 719                          struct skl_ddb_entry ddb_y[I915_MAX_PLANES],
 720                          unsigned int *update_mask)
 721 {
 722         struct intel_crtc_state *crtc_state =
 723                 intel_atomic_get_new_crtc_state(state, crtc);
 724         struct intel_plane_state *plane_state;
 725         struct intel_plane *plane;
 726         int i;
 727
 728         if (*update_mask == 0)
 729                 return NULL;
 730
 731         for_each_new_intel_plane_in_state(state, plane, plane_state, i) {
 732                 enum plane_id plane_id = plane->id;
 733
 734                 if (crtc->pipe != plane->pipe ||
 735                     !(*update_mask & BIT(plane_id)))
 736                         continue;
 737
 738                 if (skl_ddb_allocation_overlaps(&crtc_state->wm.skl.plane_ddb[plane_id],
 739                                                 ddb, I915_MAX_PLANES, plane_id) ||
 740                     skl_ddb_allocation_overlaps(&crtc_state->wm.skl.plane_ddb_y[plane_id],
 741                                                 ddb_y, I915_MAX_PLANES, plane_id))
 742                         continue;
 743
 744                 *update_mask &= ~BIT(plane_id);
 745                 ddb[plane_id] = crtc_state->wm.skl.plane_ddb[plane_id];
 746                 ddb_y[plane_id] = crtc_state->wm.skl.plane_ddb_y[plane_id];
 747
 748                 return plane;
 749         }
 750
 751         /* should never happen */
 752         drm_WARN_ON(state->base.dev, 1);
 753
 754         return NULL;
 755 }
 756
 757 void intel_plane_update_noarm(struct intel_plane *plane,
 758                               const struct intel_crtc_state *crtc_state,
 759                               const struct intel_plane_state *plane_state)
 760 {
 761         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
 762
 763         trace_intel_plane_update_noarm(plane, crtc);
 764
 765         if (plane->update_noarm)
 766                 plane->update_noarm(plane, crtc_state, plane_state);
 767 }
 768
 769 void intel_plane_update_arm(struct intel_plane *plane,
 770                             const struct intel_crtc_state *crtc_state,
 771                             const struct intel_plane_state *plane_state)
 772 {
 773         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
 774
 775         trace_intel_plane_update_arm(plane, crtc);
 776
 777         if (crtc_state->do_async_flip && plane->async_flip)
 778                 plane->async_flip(plane, crtc_state, plane_state, true);
 779         else
 780                 plane->update_arm(plane, crtc_state, plane_state);
 781 }
 782
 783 void intel_plane_disable_arm(struct intel_plane *plane,
 784                              const struct intel_crtc_state *crtc_state)
 785 {
 786         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
 787
 788         trace_intel_plane_disable_arm(plane, crtc);
 789         plane->disable_arm(plane, crtc_state);
 790 }
 791
 792 void intel_crtc_planes_update_noarm(struct intel_atomic_state *state,
 793                                     struct intel_crtc *crtc)
 794 {
 795         struct intel_crtc_state *new_crtc_state =
 796                 intel_atomic_get_new_crtc_state(state, crtc);
 797         u32 update_mask = new_crtc_state->update_planes;
 798         struct intel_plane_state *new_plane_state;
 799         struct intel_plane *plane;
 800         int i;
 801
 802         if (new_crtc_state->do_async_flip)
 803                 return;
 804
 805         /*
 806          * Since we only write non-arming registers here,
 807          * the order does not matter even for skl+.
 808          */
 809         for_each_new_intel_plane_in_state(state, plane, new_plane_state, i) {
 810                 if (crtc->pipe != plane->pipe ||
 811                     !(update_mask & BIT(plane->id)))
 812                         continue;
 813
 814                 /* TODO: for mailbox updates this should be skipped */
 815                 if (new_plane_state->uapi.visible ||
 816                     new_plane_state->planar_slave)
 817                         intel_plane_update_noarm(plane, new_crtc_state, new_plane_state);
 818         }
 819 }
 820
 821 static void skl_crtc_planes_update_arm(struct intel_atomic_state *state,
 822                                        struct intel_crtc *crtc)
 823 {
 824         struct intel_crtc_state *old_crtc_state =
 825                 intel_atomic_get_old_crtc_state(state, crtc);
 826         struct intel_crtc_state *new_crtc_state =
 827                 intel_atomic_get_new_crtc_state(state, crtc);
 828         struct skl_ddb_entry ddb[I915_MAX_PLANES];
 829         struct skl_ddb_entry ddb_y[I915_MAX_PLANES];
 830         u32 update_mask = new_crtc_state->update_planes;
 831         struct intel_plane *plane;
 832
 833         memcpy(ddb, old_crtc_state->wm.skl.plane_ddb,
 834                sizeof(old_crtc_state->wm.skl.plane_ddb));
 835         memcpy(ddb_y, old_crtc_state->wm.skl.plane_ddb_y,
 836                sizeof(old_crtc_state->wm.skl.plane_ddb_y));
 837
 838         while ((plane = skl_next_plane_to_commit(state, crtc, ddb, ddb_y, &update_mask))) {
 839                 struct intel_plane_state *new_plane_state =
 840                         intel_atomic_get_new_plane_state(state, plane);
 841
 842                 /*
 843                  * TODO: for mailbox updates intel_plane_update_noarm()
 844                  * would have to be called here as well.
 845                  */
 846                 if (new_plane_state->uapi.visible ||
 847                     new_plane_state->planar_slave)
 848                         intel_plane_update_arm(plane, new_crtc_state, new_plane_state);
 849                 else
 850                         intel_plane_disable_arm(plane, new_crtc_state);
 851         }
 852 }
 853
 854 static void i9xx_crtc_planes_update_arm(struct intel_atomic_state *state,
 855                                         struct intel_crtc *crtc)
 856 {
 857         struct intel_crtc_state *new_crtc_state =
 858                 intel_atomic_get_new_crtc_state(state, crtc);
 859         u32 update_mask = new_crtc_state->update_planes;
 860         struct intel_plane_state *new_plane_state;
 861         struct intel_plane *plane;
 862         int i;
 863
 864         for_each_new_intel_plane_in_state(state, plane, new_plane_state, i) {
 865                 if (crtc->pipe != plane->pipe ||
 866                     !(update_mask & BIT(plane->id)))
 867                         continue;
 868
 869                 /*
 870                  * TODO: for mailbox updates intel_plane_update_noarm()
 871                  * would have to be called here as well.
 872                  */
 873                 if (new_plane_state->uapi.visible)
 874                         intel_plane_update_arm(plane, new_crtc_state, new_plane_state);
 875                 else
 876                         intel_plane_disable_arm(plane, new_crtc_state);
 877         }
 878 }
 879
 880 void intel_crtc_planes_update_arm(struct intel_atomic_state *state,
 881                                   struct intel_crtc *crtc)
 882 {
 883         struct drm_i915_private *i915 = to_i915(state->base.dev);
 884
 885         if (DISPLAY_VER(i915) >= 9)
 886                 skl_crtc_planes_update_arm(state, crtc);
 887         else
 888                 i9xx_crtc_planes_update_arm(state, crtc);
 889 }
 890
 891 int intel_atomic_plane_check_clipping(struct intel_plane_state *plane_state,
 892                                       struct intel_crtc_state *crtc_state,
 893                                       int min_scale, int max_scale,
 894                                       bool can_position)
 895 {
 896         struct drm_i915_private *i915 = to_i915(plane_state->uapi.plane->dev);
 897         struct drm_framebuffer *fb = plane_state->hw.fb;
 898         struct drm_rect *src = &plane_state->uapi.src;
 899         struct drm_rect *dst = &plane_state->uapi.dst;
 900         const struct drm_rect *clip = &crtc_state->pipe_src;
 901         unsigned int rotation = plane_state->hw.rotation;
 902         int hscale, vscale;
 903
 904         if (!fb) {
 905                 plane_state->uapi.visible = false;
 906                 return 0;
 907         }
 908
 909         drm_rect_rotate(src, fb->width << 16, fb->height << 16, rotation);
 910
 911         /* Check scaling */
 912         hscale = drm_rect_calc_hscale(src, dst, min_scale, max_scale);
 913         vscale = drm_rect_calc_vscale(src, dst, min_scale, max_scale);
 914         if (hscale < 0 || vscale < 0) {
 915                 drm_dbg_kms(&i915->drm, "Invalid scaling of plane\n");
 916                 drm_rect_debug_print("src: ", src, true);
 917                 drm_rect_debug_print("dst: ", dst, false);
 918                 return -ERANGE;
 919         }
 920
 921         /*
 922          * FIXME: This might need further adjustment for seamless scaling
 923          * with phase information, for the 2p2 and 2p1 scenarios.
 924          */
 925         plane_state->uapi.visible = drm_rect_clip_scaled(src, dst, clip);
 926
 927         drm_rect_rotate_inv(src, fb->width << 16, fb->height << 16, rotation);
 928
 929         if (!can_position && plane_state->uapi.visible &&
 930             !drm_rect_equals(dst, clip)) {
 931                 drm_dbg_kms(&i915->drm, "Plane must cover entire CRTC\n");
 932                 drm_rect_debug_print("dst: ", dst, false);
 933                 drm_rect_debug_print("clip: ", clip, false);
 934                 return -EINVAL;
 935         }
 936
 937         /* final plane coordinates will be relative to the plane's pipe */
 938         drm_rect_translate(dst, -clip->x1, -clip->y1);
 939
 940         return 0;
 941 }
 942
 943 int intel_plane_check_src_coordinates(struct intel_plane_state *plane_state)
 944 {
 945         struct drm_i915_private *i915 = to_i915(plane_state->uapi.plane->dev);
 946         const struct drm_framebuffer *fb = plane_state->hw.fb;
 947         struct drm_rect *src = &plane_state->uapi.src;
 948         u32 src_x, src_y, src_w, src_h, hsub, vsub;
 949         bool rotated = drm_rotation_90_or_270(plane_state->hw.rotation);
 950
 951         /*
 952          * FIXME hsub/vsub vs. block size is a mess. Pre-tgl CCS
 953          * abuses hsub/vsub so we can't use them here. But as they
 954          * are limited to 32bpp RGB formats we don't actually need
 955          * to check anything.
 956          */
 957         if (fb->modifier == I915_FORMAT_MOD_Y_TILED_CCS ||
 958             fb->modifier == I915_FORMAT_MOD_Yf_TILED_CCS)
 959                 return 0;
 960
 961         /*
 962          * Hardware doesn't handle subpixel coordinates.
 963          * Adjust to (macro)pixel boundary, but be careful not to
 964          * increase the source viewport size, because that could
 965          * push the downscaling factor out of bounds.
 966          */
 967         src_x = src->x1 >> 16;
 968         src_w = drm_rect_width(src) >> 16;
 969         src_y = src->y1 >> 16;
 970         src_h = drm_rect_height(src) >> 16;
 971
 972         drm_rect_init(src, src_x << 16, src_y << 16,
 973                       src_w << 16, src_h << 16);
 974
 975         if (fb->format->format == DRM_FORMAT_RGB565 && rotated) {
 976                 hsub = 2;
 977                 vsub = 2;
 978         } else {
 979                 hsub = fb->format->hsub;
 980                 vsub = fb->format->vsub;
 981         }
 982
 983         if (rotated)
 984                 hsub = vsub = max(hsub, vsub);
 985
 986         if (src_x % hsub || src_w % hsub) {
 987                 drm_dbg_kms(&i915->drm, "src x/w (%u, %u) must be a multiple of %u (rotated: %s)\n",
 988                             src_x, src_w, hsub, str_yes_no(rotated));
 989                 return -EINVAL;
 990         }
 991
 992         if (src_y % vsub || src_h % vsub) {
 993                 drm_dbg_kms(&i915->drm, "src y/h (%u, %u) must be a multiple of %u (rotated: %s)\n",
 994                             src_y, src_h, vsub, str_yes_no(rotated));
 995                 return -EINVAL;
 996         }
 997
 998         return 0;
 999 }
1000
1001 /**
1002  * intel_prepare_plane_fb - Prepare fb for usage on plane
1003  * @_plane: drm plane to prepare for
1004  * @_new_plane_state: the plane state being prepared
1005  *
1006  * Prepares a framebuffer for usage on a display plane.  Generally this
1007  * involves pinning the underlying object and updating the frontbuffer tracking
1008  * bits.  Some older platforms need special physical address handling for
1009  * cursor planes.
1010  *
1011  * Returns 0 on success, negative error code on failure.
1012  */
1013 static int
1014 intel_prepare_plane_fb(struct drm_plane *_plane,
1015                        struct drm_plane_state *_new_plane_state)
1016 {
1017         struct i915_sched_attr attr = { .priority = I915_PRIORITY_DISPLAY };
1018         struct intel_plane *plane = to_intel_plane(_plane);
1019         struct intel_plane_state *new_plane_state =
1020                 to_intel_plane_state(_new_plane_state);
1021         struct intel_atomic_state *state =
1022                 to_intel_atomic_state(new_plane_state->uapi.state);
1023         struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
1024         const struct intel_plane_state *old_plane_state =
1025                 intel_atomic_get_old_plane_state(state, plane);
1026         struct drm_i915_gem_object *obj = intel_fb_obj(new_plane_state->hw.fb);
1027         struct drm_i915_gem_object *old_obj = intel_fb_obj(old_plane_state->hw.fb);
1028         int ret;
1029
1030         if (old_obj) {
1031                 const struct intel_crtc_state *new_crtc_state =
1032                         intel_atomic_get_new_crtc_state(state,
1033                                                         to_intel_crtc(old_plane_state->hw.crtc));
1034
1035                 /* Big Hammer, we also need to ensure that any pending
1036                  * MI_WAIT_FOR_EVENT inside a user batch buffer on the
1037                  * current scanout is retired before unpinning the old
1038                  * framebuffer. Note that we rely on userspace rendering
1039                  * into the buffer attached to the pipe they are waiting
1040                  * on. If not, userspace generates a GPU hang with IPEHR
1041                  * point to the MI_WAIT_FOR_EVENT.
1042                  *
1043                  * This should only fail upon a hung GPU, in which case we
1044                  * can safely continue.
1045                  */
1046                 if (new_crtc_state && intel_crtc_needs_modeset(new_crtc_state)) {
1047                         ret = i915_sw_fence_await_reservation(&state->commit_ready,
1048                                                               old_obj->base.resv,
1049                                                               false, 0,
1050                                                               GFP_KERNEL);
1051                         if (ret < 0)
1052                                 return ret;
1053                 }
1054         }
1055
1056         if (new_plane_state->uapi.fence) { /* explicit fencing */
1057                 i915_gem_fence_wait_priority(new_plane_state->uapi.fence,
1058                                              &attr);
1059                 ret = i915_sw_fence_await_dma_fence(&state->commit_ready,
1060                                                     new_plane_state->uapi.fence,
1061                                                     i915_fence_timeout(dev_priv),
1062                                                     GFP_KERNEL);
1063                 if (ret < 0)
1064                         return ret;
1065         }
1066
1067         if (!obj)
1068                 return 0;
1069
1070
1071         ret = intel_plane_pin_fb(new_plane_state);
1072         if (ret)
1073                 return ret;
1074
1075         i915_gem_object_wait_priority(obj, 0, &attr);
1076
1077         if (!new_plane_state->uapi.fence) { /* implicit fencing */
1078                 struct dma_resv_iter cursor;
1079                 struct dma_fence *fence;
1080
1081                 ret = i915_sw_fence_await_reservation(&state->commit_ready,
1082                                                       obj->base.resv, false,
1083                                                       i915_fence_timeout(dev_priv),
1084                                                       GFP_KERNEL);
1085                 if (ret < 0)
1086                         goto unpin_fb;
1087
1088                 dma_resv_iter_begin(&cursor, obj->base.resv,
1089                                     DMA_RESV_USAGE_WRITE);
1090                 dma_resv_for_each_fence_unlocked(&cursor, fence) {
1091                         intel_display_rps_boost_after_vblank(new_plane_state->hw.crtc,
1092                                                              fence);
1093                 }
1094                 dma_resv_iter_end(&cursor);
1095         } else {
1096                 intel_display_rps_boost_after_vblank(new_plane_state->hw.crtc,
1097                                                      new_plane_state->uapi.fence);
1098         }
1099
1100         /*
1101          * We declare pageflips to be interactive and so merit a small bias
1102          * towards upclocking to deliver the frame on time. By only changing
1103          * the RPS thresholds to sample more regularly and aim for higher
1104          * clocks we can hopefully deliver low power workloads (like kodi)
1105          * that are not quite steady state without resorting to forcing
1106          * maximum clocks following a vblank miss (see do_rps_boost()).
1107          */
1108         intel_display_rps_mark_interactive(dev_priv, state, true);
1109
1110         return 0;
1111
1112 unpin_fb:
1113         intel_plane_unpin_fb(new_plane_state);
1114
1115         return ret;
1116 }
1117
1118 /**
1119  * intel_cleanup_plane_fb - Cleans up an fb after plane use
1120  * @plane: drm plane to clean up for
1121  * @_old_plane_state: the state from the previous modeset
1122  *
1123  * Cleans up a framebuffer that has just been removed from a plane.
1124  */
1125 static void
1126 intel_cleanup_plane_fb(struct drm_plane *plane,
1127                        struct drm_plane_state *_old_plane_state)
1128 {
1129         struct intel_plane_state *old_plane_state =
1130                 to_intel_plane_state(_old_plane_state);
1131         struct intel_atomic_state *state =
1132                 to_intel_atomic_state(old_plane_state->uapi.state);
1133         struct drm_i915_private *dev_priv = to_i915(plane->dev);
1134         struct drm_i915_gem_object *obj = intel_fb_obj(old_plane_state->hw.fb);
1135
1136         if (!obj)
1137                 return;
1138
1139         intel_display_rps_mark_interactive(dev_priv, state, false);
1140
1141         /* Should only be called after a successful intel_prepare_plane_fb()! */
1142         intel_plane_unpin_fb(old_plane_state);
1143 }
1144
1145 static const struct drm_plane_helper_funcs intel_plane_helper_funcs = {
1146         .prepare_fb = intel_prepare_plane_fb,
1147         .cleanup_fb = intel_cleanup_plane_fb,
1148 };
1149
1150 void intel_plane_helper_add(struct intel_plane *plane)
1151 {
1152         drm_plane_helper_add(&plane->base, &intel_plane_helper_funcs);
1153 }