drivers/gpu/drm/meson/meson_vpp.c

   1 // SPDX-License-Identifier: GPL-2.0-or-later
   2 /*
   3  * Copyright (C) 2016 BayLibre, SAS
   4  * Author: Neil Armstrong <[email protected]>
   5  * Copyright (C) 2015 Amlogic, Inc. All rights reserved.
   6  * Copyright (C) 2014 Endless Mobile
   7  */
   8
   9 #include <linux/kernel.h>
  10 #include <linux/module.h>
  11 #include <drm/drmP.h>
  12 #include "meson_drv.h"
  13 #include "meson_vpp.h"
  14 #include "meson_registers.h"
  15
  16 /**
  17  * DOC: Video Post Processing
  18  *
  19  * VPP Handles all the Post Processing after the Scanout from the VIU
  20  * We handle the following post processings :
  21  *
  22  * - Postblend, Blends the OSD1 only
  23  *      We exclude OSD2, VS1, VS1 and Preblend output
  24  * - Vertical OSD Scaler for OSD1 only, we disable vertical scaler and
  25  *      use it only for interlace scanout
  26  * - Intermediate FIFO with default Amlogic values
  27  *
  28  * What is missing :
  29  *
  30  * - Preblend for video overlay pre-scaling
  31  * - OSD2 support for cursor framebuffer
  32  * - Video pre-scaling before postblend
  33  * - Full Vertical/Horizontal OSD scaling to support TV overscan
  34  * - HDR conversion
  35  */
  36
  37 void meson_vpp_setup_mux(struct meson_drm *priv, unsigned int mux)
  38 {
  39         writel(mux, priv->io_base + _REG(VPU_VIU_VENC_MUX_CTRL));
  40 }
  41
  42 static unsigned int vpp_filter_coefs_4point_bspline[] = {
  43         0x15561500, 0x14561600, 0x13561700, 0x12561800,
  44         0x11551a00, 0x11541b00, 0x10541c00, 0x0f541d00,
  45         0x0f531e00, 0x0e531f00, 0x0d522100, 0x0c522200,
  46         0x0b522300, 0x0b512400, 0x0a502600, 0x0a4f2700,
  47         0x094e2900, 0x084e2a00, 0x084d2b00, 0x074c2c01,
  48         0x074b2d01, 0x064a2f01, 0x06493001, 0x05483201,
  49         0x05473301, 0x05463401, 0x04453601, 0x04433702,
  50         0x04423802, 0x03413a02, 0x03403b02, 0x033f3c02,
  51         0x033d3d03
  52 };
  53
  54 static void meson_vpp_write_scaling_filter_coefs(struct meson_drm *priv,
  55                                                  const unsigned int *coefs,
  56                                                  bool is_horizontal)
  57 {
  58         int i;
  59
  60         writel_relaxed(is_horizontal ? BIT(8) : 0,
  61                         priv->io_base + _REG(VPP_OSD_SCALE_COEF_IDX));
  62         for (i = 0; i < 33; i++)
  63                 writel_relaxed(coefs[i],
  64                                 priv->io_base + _REG(VPP_OSD_SCALE_COEF));
  65 }
  66
  67 static const uint32_t vpp_filter_coefs_bicubic[] = {
  68         0x00800000, 0x007f0100, 0xff7f0200, 0xfe7f0300,
  69         0xfd7e0500, 0xfc7e0600, 0xfb7d0800, 0xfb7c0900,
  70         0xfa7b0b00, 0xfa7a0dff, 0xf9790fff, 0xf97711ff,
  71         0xf87613ff, 0xf87416fe, 0xf87218fe, 0xf8701afe,
  72         0xf76f1dfd, 0xf76d1ffd, 0xf76b21fd, 0xf76824fd,
  73         0xf76627fc, 0xf76429fc, 0xf7612cfc, 0xf75f2ffb,
  74         0xf75d31fb, 0xf75a34fb, 0xf75837fa, 0xf7553afa,
  75         0xf8523cfa, 0xf8503ff9, 0xf84d42f9, 0xf84a45f9,
  76         0xf84848f8
  77 };
  78
  79 static void meson_vpp_write_vd_scaling_filter_coefs(struct meson_drm *priv,
  80                                                     const unsigned int *coefs,
  81                                                     bool is_horizontal)
  82 {
  83         int i;
  84
  85         writel_relaxed(is_horizontal ? BIT(8) : 0,
  86                         priv->io_base + _REG(VPP_SCALE_COEF_IDX));
  87         for (i = 0; i < 33; i++)
  88                 writel_relaxed(coefs[i],
  89                                 priv->io_base + _REG(VPP_SCALE_COEF));
  90 }
  91
  92 void meson_vpp_init(struct meson_drm *priv)
  93 {
  94         /* set dummy data default YUV black */
  95         if (meson_vpu_is_compatible(priv, "amlogic,meson-gxl-vpu"))
  96                 writel_relaxed(0x108080, priv->io_base + _REG(VPP_DUMMY_DATA1));
  97         else if (meson_vpu_is_compatible(priv, "amlogic,meson-gxm-vpu")) {
  98                 writel_bits_relaxed(0xff << 16, 0xff << 16,
  99                                     priv->io_base + _REG(VIU_MISC_CTRL1));
 100                 writel_relaxed(0x20000, priv->io_base + _REG(VPP_DOLBY_CTRL));
 101                 writel_relaxed(0x1020080,
 102                                 priv->io_base + _REG(VPP_DUMMY_DATA1));
 103         } else if (meson_vpu_is_compatible(priv, "amlogic,meson-g12a-vpu"))
 104                 writel_relaxed(0xf, priv->io_base + _REG(DOLBY_PATH_CTRL));
 105
 106         /* Initialize vpu fifo control registers */
 107         if (meson_vpu_is_compatible(priv, "amlogic,meson-g12a-vpu"))
 108                 writel_relaxed(0xfff << 20 | 0x1000,
 109                                priv->io_base + _REG(VPP_OFIFO_SIZE));
 110         else
 111                 writel_relaxed(readl_relaxed(priv->io_base + _REG(VPP_OFIFO_SIZE)) |
 112                                 0x77f, priv->io_base + _REG(VPP_OFIFO_SIZE));
 113         writel_relaxed(0x08080808, priv->io_base + _REG(VPP_HOLD_LINES));
 114
 115         if (!meson_vpu_is_compatible(priv, "amlogic,meson-g12a-vpu")) {
 116                 /* Turn off preblend */
 117                 writel_bits_relaxed(VPP_PREBLEND_ENABLE, 0,
 118                                     priv->io_base + _REG(VPP_MISC));
 119
 120                 /* Turn off POSTBLEND */
 121                 writel_bits_relaxed(VPP_POSTBLEND_ENABLE, 0,
 122                                     priv->io_base + _REG(VPP_MISC));
 123
 124                 /* Force all planes off */
 125                 writel_bits_relaxed(VPP_OSD1_POSTBLEND | VPP_OSD2_POSTBLEND |
 126                                     VPP_VD1_POSTBLEND | VPP_VD2_POSTBLEND |
 127                                     VPP_VD1_PREBLEND | VPP_VD2_PREBLEND, 0,
 128                                     priv->io_base + _REG(VPP_MISC));
 129
 130                 /* Setup default VD settings */
 131                 writel_relaxed(4096,
 132                                 priv->io_base + _REG(VPP_PREBLEND_VD1_H_START_END));
 133                 writel_relaxed(4096,
 134                                 priv->io_base + _REG(VPP_BLEND_VD2_H_START_END));
 135         }
 136
 137         /* Disable Scalers */
 138         writel_relaxed(0, priv->io_base + _REG(VPP_OSD_SC_CTRL0));
 139         writel_relaxed(0, priv->io_base + _REG(VPP_OSD_VSC_CTRL0));
 140         writel_relaxed(0, priv->io_base + _REG(VPP_OSD_HSC_CTRL0));
 141         writel_relaxed(4 | (4 << 8) | BIT(15),
 142                        priv->io_base + _REG(VPP_SC_MISC));
 143
 144         writel_relaxed(1, priv->io_base + _REG(VPP_VADJ_CTRL));
 145
 146         /* Write in the proper filter coefficients. */
 147         meson_vpp_write_scaling_filter_coefs(priv,
 148                                 vpp_filter_coefs_4point_bspline, false);
 149         meson_vpp_write_scaling_filter_coefs(priv,
 150                                 vpp_filter_coefs_4point_bspline, true);
 151
 152         /* Write the VD proper filter coefficients. */
 153         meson_vpp_write_vd_scaling_filter_coefs(priv, vpp_filter_coefs_bicubic,
 154                                                 false);
 155         meson_vpp_write_vd_scaling_filter_coefs(priv, vpp_filter_coefs_bicubic,
 156                                                 true);
 157 }