drivers/gpu/drm/amd/amdgpu/gfx_v9_4_2.c

   1 /*
   2  * Copyright 2020 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23 #include "amdgpu.h"
  24 #include "soc15.h"
  25
  26 #include "gc/gc_9_4_2_offset.h"
  27 #include "gc/gc_9_4_2_sh_mask.h"
  28 #include "gfx_v9_0.h"
  29
  30 #include "gfx_v9_4_2.h"
  31 #include "amdgpu_ras.h"
  32 #include "amdgpu_gfx.h"
  33
  34 enum gfx_v9_4_2_utc_type {
  35         VML2_MEM,
  36         VML2_WALKER_MEM,
  37         UTCL2_MEM,
  38         ATC_L2_CACHE_2M,
  39         ATC_L2_CACHE_32K,
  40         ATC_L2_CACHE_4K
  41 };
  42
  43 struct gfx_v9_4_2_utc_block {
  44         enum gfx_v9_4_2_utc_type type;
  45         uint32_t num_banks;
  46         uint32_t num_ways;
  47         uint32_t num_mem_blocks;
  48         struct soc15_reg idx_reg;
  49         struct soc15_reg data_reg;
  50         uint32_t sec_count_mask;
  51         uint32_t sec_count_shift;
  52         uint32_t ded_count_mask;
  53         uint32_t ded_count_shift;
  54         uint32_t clear;
  55 };
  56
  57 static const struct soc15_reg_golden golden_settings_gc_9_4_2_alde_die_0[] = {
  58         SOC15_REG_GOLDEN_VALUE(GC, 0, regTCP_CHAN_STEER_0, 0x3fffffff, 0x141dc920),
  59         SOC15_REG_GOLDEN_VALUE(GC, 0, regTCP_CHAN_STEER_1, 0x3fffffff, 0x3b458b93),
  60         SOC15_REG_GOLDEN_VALUE(GC, 0, regTCP_CHAN_STEER_2, 0x3fffffff, 0x1a4f5583),
  61         SOC15_REG_GOLDEN_VALUE(GC, 0, regTCP_CHAN_STEER_3, 0x3fffffff, 0x317717f6),
  62         SOC15_REG_GOLDEN_VALUE(GC, 0, regTCP_CHAN_STEER_4, 0x3fffffff, 0x107cc1e6),
  63         SOC15_REG_GOLDEN_VALUE(GC, 0, regTCP_CHAN_STEER_5, 0x3ff, 0x351),
  64 };
  65
  66 static const struct soc15_reg_golden golden_settings_gc_9_4_2_alde_die_1[] = {
  67         SOC15_REG_GOLDEN_VALUE(GC, 0, regTCP_CHAN_STEER_0, 0x3fffffff, 0x2591aa38),
  68         SOC15_REG_GOLDEN_VALUE(GC, 0, regTCP_CHAN_STEER_1, 0x3fffffff, 0xac9e88b),
  69         SOC15_REG_GOLDEN_VALUE(GC, 0, regTCP_CHAN_STEER_2, 0x3fffffff, 0x2bc3369b),
  70         SOC15_REG_GOLDEN_VALUE(GC, 0, regTCP_CHAN_STEER_3, 0x3fffffff, 0xfb74ee),
  71         SOC15_REG_GOLDEN_VALUE(GC, 0, regTCP_CHAN_STEER_4, 0x3fffffff, 0x21f0a2fe),
  72         SOC15_REG_GOLDEN_VALUE(GC, 0, regTCP_CHAN_STEER_5, 0x3ff, 0x49),
  73 };
  74
  75 static const struct soc15_reg_golden golden_settings_gc_9_4_2_alde[] = {
  76         SOC15_REG_GOLDEN_VALUE(GC, 0, regGB_ADDR_CONFIG, 0xffff77ff, 0x2a114042),
  77         SOC15_REG_GOLDEN_VALUE(GC, 0, regTA_CNTL_AUX, 0xfffffeef, 0x10b0000),
  78         SOC15_REG_GOLDEN_VALUE(GC, 0, regTCP_UTCL1_CNTL1, 0xffffffff, 0x30800400),
  79         SOC15_REG_GOLDEN_VALUE(GC, 0, regTCI_CNTL_3, 0xff, 0x20),
  80 };
  81
  82 static void gfx_v9_4_2_query_sq_timeout_status(struct amdgpu_device *adev);
  83 static void gfx_v9_4_2_reset_sq_timeout_status(struct amdgpu_device *adev);
  84
  85 void gfx_v9_4_2_init_golden_registers(struct amdgpu_device *adev,
  86                                       uint32_t die_id)
  87 {
  88         soc15_program_register_sequence(adev,
  89                                         golden_settings_gc_9_4_2_alde,
  90                                         ARRAY_SIZE(golden_settings_gc_9_4_2_alde));
  91
  92         /* apply golden settings per die */
  93         switch (die_id) {
  94         case 0:
  95                 soc15_program_register_sequence(adev,
  96                                 golden_settings_gc_9_4_2_alde_die_0,
  97                                 ARRAY_SIZE(golden_settings_gc_9_4_2_alde_die_0));
  98                 break;
  99         case 1:
 100                 soc15_program_register_sequence(adev,
 101                                 golden_settings_gc_9_4_2_alde_die_1,
 102                                 ARRAY_SIZE(golden_settings_gc_9_4_2_alde_die_1));
 103                 break;
 104         default:
 105                 dev_warn(adev->dev,
 106                          "invalid die id %d, ignore channel fabricid remap settings\n",
 107                          die_id);
 108                 break;
 109         }
 110
 111         return;
 112 }
 113
 114 void gfx_v9_4_2_debug_trap_config_init(struct amdgpu_device *adev,
 115                                 uint32_t first_vmid,
 116                                 uint32_t last_vmid)
 117 {
 118         uint32_t data;
 119         int i;
 120
 121         mutex_lock(&adev->srbm_mutex);
 122
 123         for (i = first_vmid; i < last_vmid; i++) {
 124                 data = 0;
 125                 soc15_grbm_select(adev, 0, 0, 0, i);
 126                 data = REG_SET_FIELD(data, SPI_GDBG_PER_VMID_CNTL, TRAP_EN, 1);
 127                 data = REG_SET_FIELD(data, SPI_GDBG_PER_VMID_CNTL, EXCP_EN, 0);
 128                 data = REG_SET_FIELD(data, SPI_GDBG_PER_VMID_CNTL, EXCP_REPLACE,
 129                                         0);
 130                 WREG32(SOC15_REG_OFFSET(GC, 0, regSPI_GDBG_PER_VMID_CNTL), data);
 131         }
 132
 133         soc15_grbm_select(adev, 0, 0, 0, 0);
 134         mutex_unlock(&adev->srbm_mutex);
 135 }
 136
 137 void gfx_v9_4_2_set_power_brake_sequence(struct amdgpu_device *adev)
 138 {
 139         u32 tmp;
 140
 141         gfx_v9_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
 142
 143         tmp = 0;
 144         tmp = REG_SET_FIELD(tmp, GC_THROTTLE_CTRL, PATTERN_MODE, 1);
 145         WREG32_SOC15(GC, 0, regGC_THROTTLE_CTRL, tmp);
 146
 147         tmp = 0;
 148         tmp = REG_SET_FIELD(tmp, GC_THROTTLE_CTRL1, PWRBRK_STALL_EN, 1);
 149         WREG32_SOC15(GC, 0, regGC_THROTTLE_CTRL1, tmp);
 150
 151         WREG32_SOC15(GC, 0, regDIDT_IND_INDEX, ixDIDT_SQ_THROTTLE_CTRL);
 152         tmp = 0;
 153         tmp = REG_SET_FIELD(tmp, DIDT_SQ_THROTTLE_CTRL, PWRBRK_STALL_EN, 1);
 154         WREG32_SOC15(GC, 0, regDIDT_IND_DATA, tmp);
 155
 156         WREG32_SOC15(GC, 0, regGC_CAC_IND_INDEX, ixPWRBRK_STALL_PATTERN_CTRL);
 157         tmp = 0;
 158         tmp = REG_SET_FIELD(tmp, PWRBRK_STALL_PATTERN_CTRL, PWRBRK_END_STEP, 0x12);
 159         WREG32_SOC15(GC, 0, regGC_CAC_IND_DATA, tmp);
 160 }
 161
 162 static const struct soc15_reg_entry gfx_v9_4_2_edc_counter_regs[] = {
 163         /* CPF */
 164         { SOC15_REG_ENTRY(GC, 0, regCPF_EDC_ROQ_CNT), 0, 1, 1 },
 165         { SOC15_REG_ENTRY(GC, 0, regCPF_EDC_TAG_CNT), 0, 1, 1 },
 166         /* CPC */
 167         { SOC15_REG_ENTRY(GC, 0, regCPC_EDC_SCRATCH_CNT), 0, 1, 1 },
 168         { SOC15_REG_ENTRY(GC, 0, regCPC_EDC_UCODE_CNT), 0, 1, 1 },
 169         { SOC15_REG_ENTRY(GC, 0, regDC_EDC_STATE_CNT), 0, 1, 1 },
 170         { SOC15_REG_ENTRY(GC, 0, regDC_EDC_CSINVOC_CNT), 0, 1, 1 },
 171         { SOC15_REG_ENTRY(GC, 0, regDC_EDC_RESTORE_CNT), 0, 1, 1 },
 172         /* GDS */
 173         { SOC15_REG_ENTRY(GC, 0, regGDS_EDC_CNT), 0, 1, 1 },
 174         { SOC15_REG_ENTRY(GC, 0, regGDS_EDC_GRBM_CNT), 0, 1, 1 },
 175         { SOC15_REG_ENTRY(GC, 0, regGDS_EDC_OA_DED), 0, 1, 1 },
 176         { SOC15_REG_ENTRY(GC, 0, regGDS_EDC_OA_PHY_CNT), 0, 1, 1 },
 177         { SOC15_REG_ENTRY(GC, 0, regGDS_EDC_OA_PIPE_CNT), 0, 1, 1 },
 178         /* RLC */
 179         { SOC15_REG_ENTRY(GC, 0, regRLC_EDC_CNT), 0, 1, 1 },
 180         { SOC15_REG_ENTRY(GC, 0, regRLC_EDC_CNT2), 0, 1, 1 },
 181         /* SPI */
 182         { SOC15_REG_ENTRY(GC, 0, regSPI_EDC_CNT), 0, 8, 1 },
 183         /* SQC */
 184         { SOC15_REG_ENTRY(GC, 0, regSQC_EDC_CNT), 0, 8, 7 },
 185         { SOC15_REG_ENTRY(GC, 0, regSQC_EDC_CNT2), 0, 8, 7 },
 186         { SOC15_REG_ENTRY(GC, 0, regSQC_EDC_CNT3), 0, 8, 7 },
 187         { SOC15_REG_ENTRY(GC, 0, regSQC_EDC_PARITY_CNT3), 0, 8, 7 },
 188         /* SQ */
 189         { SOC15_REG_ENTRY(GC, 0, regSQ_EDC_CNT), 0, 8, 14 },
 190         /* TCP */
 191         { SOC15_REG_ENTRY(GC, 0, regTCP_EDC_CNT_NEW), 0, 8, 14 },
 192         /* TCI */
 193         { SOC15_REG_ENTRY(GC, 0, regTCI_EDC_CNT), 0, 1, 69 },
 194         /* TCC */
 195         { SOC15_REG_ENTRY(GC, 0, regTCC_EDC_CNT), 0, 1, 16 },
 196         { SOC15_REG_ENTRY(GC, 0, regTCC_EDC_CNT2), 0, 1, 16 },
 197         /* TCA */
 198         { SOC15_REG_ENTRY(GC, 0, regTCA_EDC_CNT), 0, 1, 2 },
 199         /* TCX */
 200         { SOC15_REG_ENTRY(GC, 0, regTCX_EDC_CNT), 0, 1, 2 },
 201         { SOC15_REG_ENTRY(GC, 0, regTCX_EDC_CNT2), 0, 1, 2 },
 202         /* TD */
 203         { SOC15_REG_ENTRY(GC, 0, regTD_EDC_CNT), 0, 8, 14 },
 204         /* TA */
 205         { SOC15_REG_ENTRY(GC, 0, regTA_EDC_CNT), 0, 8, 14 },
 206         /* GCEA */
 207         { SOC15_REG_ENTRY(GC, 0, regGCEA_EDC_CNT), 0, 1, 16 },
 208         { SOC15_REG_ENTRY(GC, 0, regGCEA_EDC_CNT2), 0, 1, 16 },
 209         { SOC15_REG_ENTRY(GC, 0, regGCEA_EDC_CNT3), 0, 1, 16 },
 210 };
 211
 212 static void gfx_v9_4_2_select_se_sh(struct amdgpu_device *adev, u32 se_num,
 213                                   u32 sh_num, u32 instance)
 214 {
 215         u32 data;
 216
 217         if (instance == 0xffffffff)
 218                 data = REG_SET_FIELD(0, GRBM_GFX_INDEX,
 219                                      INSTANCE_BROADCAST_WRITES, 1);
 220         else
 221                 data = REG_SET_FIELD(0, GRBM_GFX_INDEX, INSTANCE_INDEX,
 222                                      instance);
 223
 224         if (se_num == 0xffffffff)
 225                 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_BROADCAST_WRITES,
 226                                      1);
 227         else
 228                 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_INDEX, se_num);
 229
 230         if (sh_num == 0xffffffff)
 231                 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SH_BROADCAST_WRITES,
 232                                      1);
 233         else
 234                 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SH_INDEX, sh_num);
 235
 236         WREG32_SOC15_RLC_SHADOW_EX(reg, GC, 0, regGRBM_GFX_INDEX, data);
 237 }
 238
 239 static const struct soc15_ras_field_entry gfx_v9_4_2_ras_fields[] = {
 240         /* CPF */
 241         { "CPF_ROQ_ME2", SOC15_REG_ENTRY(GC, 0, regCPF_EDC_ROQ_CNT),
 242           SOC15_REG_FIELD(CPF_EDC_ROQ_CNT, SEC_COUNT_ME2),
 243           SOC15_REG_FIELD(CPF_EDC_ROQ_CNT, DED_COUNT_ME2) },
 244         { "CPF_ROQ_ME1", SOC15_REG_ENTRY(GC, 0, regCPF_EDC_ROQ_CNT),
 245           SOC15_REG_FIELD(CPF_EDC_ROQ_CNT, SEC_COUNT_ME1),
 246           SOC15_REG_FIELD(CPF_EDC_ROQ_CNT, DED_COUNT_ME1) },
 247         { "CPF_TCIU_TAG", SOC15_REG_ENTRY(GC, 0, regCPF_EDC_TAG_CNT),
 248           SOC15_REG_FIELD(CPF_EDC_TAG_CNT, SEC_COUNT),
 249           SOC15_REG_FIELD(CPF_EDC_TAG_CNT, DED_COUNT) },
 250
 251         /* CPC */
 252         { "CPC_SCRATCH", SOC15_REG_ENTRY(GC, 0, regCPC_EDC_SCRATCH_CNT),
 253           SOC15_REG_FIELD(CPC_EDC_SCRATCH_CNT, SEC_COUNT),
 254           SOC15_REG_FIELD(CPC_EDC_SCRATCH_CNT, DED_COUNT) },
 255         { "CPC_UCODE", SOC15_REG_ENTRY(GC, 0, regCPC_EDC_UCODE_CNT),
 256           SOC15_REG_FIELD(CPC_EDC_UCODE_CNT, SEC_COUNT),
 257           SOC15_REG_FIELD(CPC_EDC_UCODE_CNT, DED_COUNT) },
 258         { "CPC_DC_STATE_RAM_ME1", SOC15_REG_ENTRY(GC, 0, regDC_EDC_STATE_CNT),
 259           SOC15_REG_FIELD(DC_EDC_STATE_CNT, SEC_COUNT_ME1),
 260           SOC15_REG_FIELD(DC_EDC_STATE_CNT, DED_COUNT_ME1) },
 261         { "CPC_DC_CSINVOC_RAM_ME1",
 262           SOC15_REG_ENTRY(GC, 0, regDC_EDC_CSINVOC_CNT),
 263           SOC15_REG_FIELD(DC_EDC_CSINVOC_CNT, SEC_COUNT_ME1),
 264           SOC15_REG_FIELD(DC_EDC_CSINVOC_CNT, DED_COUNT_ME1) },
 265         { "CPC_DC_RESTORE_RAM_ME1",
 266           SOC15_REG_ENTRY(GC, 0, regDC_EDC_RESTORE_CNT),
 267           SOC15_REG_FIELD(DC_EDC_RESTORE_CNT, SEC_COUNT_ME1),
 268           SOC15_REG_FIELD(DC_EDC_RESTORE_CNT, DED_COUNT_ME1) },
 269         { "CPC_DC_CSINVOC_RAM1_ME1",
 270           SOC15_REG_ENTRY(GC, 0, regDC_EDC_CSINVOC_CNT),
 271           SOC15_REG_FIELD(DC_EDC_CSINVOC_CNT, SEC_COUNT1_ME1),
 272           SOC15_REG_FIELD(DC_EDC_CSINVOC_CNT, DED_COUNT1_ME1) },
 273         { "CPC_DC_RESTORE_RAM1_ME1",
 274           SOC15_REG_ENTRY(GC, 0, regDC_EDC_RESTORE_CNT),
 275           SOC15_REG_FIELD(DC_EDC_RESTORE_CNT, SEC_COUNT1_ME1),
 276           SOC15_REG_FIELD(DC_EDC_RESTORE_CNT, DED_COUNT1_ME1) },
 277
 278         /* GDS */
 279         { "GDS_GRBM", SOC15_REG_ENTRY(GC, 0, regGDS_EDC_GRBM_CNT),
 280           SOC15_REG_FIELD(GDS_EDC_GRBM_CNT, SEC),
 281           SOC15_REG_FIELD(GDS_EDC_GRBM_CNT, DED) },
 282         { "GDS_MEM", SOC15_REG_ENTRY(GC, 0, regGDS_EDC_CNT),
 283           SOC15_REG_FIELD(GDS_EDC_CNT, GDS_MEM_SEC),
 284           SOC15_REG_FIELD(GDS_EDC_CNT, GDS_MEM_DED) },
 285         { "GDS_PHY_CMD_RAM_MEM", SOC15_REG_ENTRY(GC, 0, regGDS_EDC_OA_PHY_CNT),
 286           SOC15_REG_FIELD(GDS_EDC_OA_PHY_CNT, PHY_CMD_RAM_MEM_SEC),
 287           SOC15_REG_FIELD(GDS_EDC_OA_PHY_CNT, PHY_CMD_RAM_MEM_DED) },
 288         { "GDS_PHY_DATA_RAM_MEM", SOC15_REG_ENTRY(GC, 0, regGDS_EDC_OA_PHY_CNT),
 289           SOC15_REG_FIELD(GDS_EDC_OA_PHY_CNT, PHY_DATA_RAM_MEM_SEC),
 290           SOC15_REG_FIELD(GDS_EDC_OA_PHY_CNT, PHY_DATA_RAM_MEM_DED) },
 291         { "GDS_ME0_CS_PIPE_MEM", SOC15_REG_ENTRY(GC, 0, regGDS_EDC_OA_PHY_CNT),
 292           SOC15_REG_FIELD(GDS_EDC_OA_PHY_CNT, ME0_CS_PIPE_MEM_SEC),
 293           SOC15_REG_FIELD(GDS_EDC_OA_PHY_CNT, ME0_CS_PIPE_MEM_DED) },
 294         { "GDS_ME1_PIPE0_PIPE_MEM",
 295           SOC15_REG_ENTRY(GC, 0, regGDS_EDC_OA_PIPE_CNT),
 296           SOC15_REG_FIELD(GDS_EDC_OA_PIPE_CNT, ME1_PIPE0_PIPE_MEM_SEC),
 297           SOC15_REG_FIELD(GDS_EDC_OA_PIPE_CNT, ME1_PIPE0_PIPE_MEM_DED) },
 298         { "GDS_ME1_PIPE1_PIPE_MEM",
 299           SOC15_REG_ENTRY(GC, 0, regGDS_EDC_OA_PIPE_CNT),
 300           SOC15_REG_FIELD(GDS_EDC_OA_PIPE_CNT, ME1_PIPE1_PIPE_MEM_SEC),
 301           SOC15_REG_FIELD(GDS_EDC_OA_PIPE_CNT, ME1_PIPE1_PIPE_MEM_DED) },
 302         { "GDS_ME1_PIPE2_PIPE_MEM",
 303           SOC15_REG_ENTRY(GC, 0, regGDS_EDC_OA_PIPE_CNT),
 304           SOC15_REG_FIELD(GDS_EDC_OA_PIPE_CNT, ME1_PIPE2_PIPE_MEM_SEC),
 305           SOC15_REG_FIELD(GDS_EDC_OA_PIPE_CNT, ME1_PIPE2_PIPE_MEM_DED) },
 306         { "GDS_ME1_PIPE3_PIPE_MEM",
 307           SOC15_REG_ENTRY(GC, 0, regGDS_EDC_OA_PIPE_CNT),
 308           SOC15_REG_FIELD(GDS_EDC_OA_PIPE_CNT, ME1_PIPE3_PIPE_MEM_SEC),
 309           SOC15_REG_FIELD(GDS_EDC_OA_PIPE_CNT, ME1_PIPE3_PIPE_MEM_DED) },
 310         { "GDS_ME0_GFXHP3D_PIX_DED",
 311           SOC15_REG_ENTRY(GC, 0, regGDS_EDC_OA_DED), 0, 0,
 312           SOC15_REG_FIELD(GDS_EDC_OA_DED, ME0_GFXHP3D_PIX_DED) },
 313         { "GDS_ME0_GFXHP3D_VTX_DED",
 314           SOC15_REG_ENTRY(GC, 0, regGDS_EDC_OA_DED), 0, 0,
 315           SOC15_REG_FIELD(GDS_EDC_OA_DED, ME0_GFXHP3D_VTX_DED) },
 316         { "GDS_ME0_CS_DED",
 317           SOC15_REG_ENTRY(GC, 0, regGDS_EDC_OA_DED), 0, 0,
 318           SOC15_REG_FIELD(GDS_EDC_OA_DED, ME0_CS_DED) },
 319         { "GDS_ME0_GFXHP3D_GS_DED",
 320           SOC15_REG_ENTRY(GC, 0, regGDS_EDC_OA_DED), 0, 0,
 321           SOC15_REG_FIELD(GDS_EDC_OA_DED, ME0_GFXHP3D_GS_DED) },
 322         { "GDS_ME1_PIPE0_DED",
 323           SOC15_REG_ENTRY(GC, 0, regGDS_EDC_OA_DED), 0, 0,
 324           SOC15_REG_FIELD(GDS_EDC_OA_DED, ME1_PIPE0_DED) },
 325         { "GDS_ME1_PIPE1_DED",
 326           SOC15_REG_ENTRY(GC, 0, regGDS_EDC_OA_DED), 0, 0,
 327           SOC15_REG_FIELD(GDS_EDC_OA_DED, ME1_PIPE1_DED) },
 328         { "GDS_ME1_PIPE2_DED",
 329           SOC15_REG_ENTRY(GC, 0, regGDS_EDC_OA_DED), 0, 0,
 330           SOC15_REG_FIELD(GDS_EDC_OA_DED, ME1_PIPE2_DED) },
 331         { "GDS_ME1_PIPE3_DED",
 332           SOC15_REG_ENTRY(GC, 0, regGDS_EDC_OA_DED), 0, 0,
 333           SOC15_REG_FIELD(GDS_EDC_OA_DED, ME1_PIPE3_DED) },
 334         { "GDS_ME2_PIPE0_DED",
 335           SOC15_REG_ENTRY(GC, 0, regGDS_EDC_OA_DED), 0, 0,
 336           SOC15_REG_FIELD(GDS_EDC_OA_DED, ME2_PIPE0_DED) },
 337         { "GDS_ME2_PIPE1_DED",
 338           SOC15_REG_ENTRY(GC, 0, regGDS_EDC_OA_DED), 0, 0,
 339           SOC15_REG_FIELD(GDS_EDC_OA_DED, ME2_PIPE1_DED) },
 340         { "GDS_ME2_PIPE2_DED",
 341           SOC15_REG_ENTRY(GC, 0, regGDS_EDC_OA_DED), 0, 0,
 342           SOC15_REG_FIELD(GDS_EDC_OA_DED, ME2_PIPE2_DED) },
 343         { "GDS_ME2_PIPE3_DED",
 344           SOC15_REG_ENTRY(GC, 0, regGDS_EDC_OA_DED), 0, 0,
 345           SOC15_REG_FIELD(GDS_EDC_OA_DED, ME2_PIPE3_DED) },
 346
 347         /* RLC */
 348         { "RLCG_INSTR_RAM", SOC15_REG_ENTRY(GC, 0, regRLC_EDC_CNT),
 349           SOC15_REG_FIELD(RLC_EDC_CNT, RLCG_INSTR_RAM_SEC_COUNT),
 350           SOC15_REG_FIELD(RLC_EDC_CNT, RLCG_INSTR_RAM_DED_COUNT) },
 351         { "RLCG_SCRATCH_RAM", SOC15_REG_ENTRY(GC, 0, regRLC_EDC_CNT),
 352           SOC15_REG_FIELD(RLC_EDC_CNT, RLCG_SCRATCH_RAM_SEC_COUNT),
 353           SOC15_REG_FIELD(RLC_EDC_CNT, RLCG_SCRATCH_RAM_DED_COUNT) },
 354         { "RLCV_INSTR_RAM", SOC15_REG_ENTRY(GC, 0, regRLC_EDC_CNT),
 355           SOC15_REG_FIELD(RLC_EDC_CNT, RLCV_INSTR_RAM_SEC_COUNT),
 356           SOC15_REG_FIELD(RLC_EDC_CNT, RLCV_INSTR_RAM_DED_COUNT) },
 357         { "RLCV_SCRATCH_RAM", SOC15_REG_ENTRY(GC, 0, regRLC_EDC_CNT),
 358           SOC15_REG_FIELD(RLC_EDC_CNT, RLCV_SCRATCH_RAM_SEC_COUNT),
 359           SOC15_REG_FIELD(RLC_EDC_CNT, RLCV_SCRATCH_RAM_DED_COUNT) },
 360         { "RLC_TCTAG_RAM", SOC15_REG_ENTRY(GC, 0, regRLC_EDC_CNT),
 361           SOC15_REG_FIELD(RLC_EDC_CNT, RLC_TCTAG_RAM_SEC_COUNT),
 362           SOC15_REG_FIELD(RLC_EDC_CNT, RLC_TCTAG_RAM_DED_COUNT) },
 363         { "RLC_SPM_SCRATCH_RAM", SOC15_REG_ENTRY(GC, 0, regRLC_EDC_CNT),
 364           SOC15_REG_FIELD(RLC_EDC_CNT, RLC_SPM_SCRATCH_RAM_SEC_COUNT),
 365           SOC15_REG_FIELD(RLC_EDC_CNT, RLC_SPM_SCRATCH_RAM_DED_COUNT) },
 366         { "RLC_SRM_DATA_RAM", SOC15_REG_ENTRY(GC, 0, regRLC_EDC_CNT),
 367           SOC15_REG_FIELD(RLC_EDC_CNT, RLC_SRM_DATA_RAM_SEC_COUNT),
 368           SOC15_REG_FIELD(RLC_EDC_CNT, RLC_SRM_DATA_RAM_DED_COUNT) },
 369         { "RLC_SRM_ADDR_RAM", SOC15_REG_ENTRY(GC, 0, regRLC_EDC_CNT),
 370           SOC15_REG_FIELD(RLC_EDC_CNT, RLC_SRM_ADDR_RAM_SEC_COUNT),
 371           SOC15_REG_FIELD(RLC_EDC_CNT, RLC_SRM_ADDR_RAM_DED_COUNT) },
 372         { "RLC_SPM_SE0_SCRATCH_RAM", SOC15_REG_ENTRY(GC, 0, regRLC_EDC_CNT2),
 373           SOC15_REG_FIELD(RLC_EDC_CNT2, RLC_SPM_SE0_SCRATCH_RAM_SEC_COUNT),
 374           SOC15_REG_FIELD(RLC_EDC_CNT2, RLC_SPM_SE0_SCRATCH_RAM_DED_COUNT) },
 375         { "RLC_SPM_SE1_SCRATCH_RAM", SOC15_REG_ENTRY(GC, 0, regRLC_EDC_CNT2),
 376           SOC15_REG_FIELD(RLC_EDC_CNT2, RLC_SPM_SE1_SCRATCH_RAM_SEC_COUNT),
 377           SOC15_REG_FIELD(RLC_EDC_CNT2, RLC_SPM_SE1_SCRATCH_RAM_DED_COUNT) },
 378         { "RLC_SPM_SE2_SCRATCH_RAM", SOC15_REG_ENTRY(GC, 0, regRLC_EDC_CNT2),
 379           SOC15_REG_FIELD(RLC_EDC_CNT2, RLC_SPM_SE2_SCRATCH_RAM_SEC_COUNT),
 380           SOC15_REG_FIELD(RLC_EDC_CNT2, RLC_SPM_SE2_SCRATCH_RAM_DED_COUNT) },
 381         { "RLC_SPM_SE3_SCRATCH_RAM", SOC15_REG_ENTRY(GC, 0, regRLC_EDC_CNT2),
 382           SOC15_REG_FIELD(RLC_EDC_CNT2, RLC_SPM_SE3_SCRATCH_RAM_SEC_COUNT),
 383           SOC15_REG_FIELD(RLC_EDC_CNT2, RLC_SPM_SE3_SCRATCH_RAM_DED_COUNT) },
 384         { "RLC_SPM_SE4_SCRATCH_RAM", SOC15_REG_ENTRY(GC, 0, regRLC_EDC_CNT2),
 385           SOC15_REG_FIELD(RLC_EDC_CNT2, RLC_SPM_SE4_SCRATCH_RAM_SEC_COUNT),
 386           SOC15_REG_FIELD(RLC_EDC_CNT2, RLC_SPM_SE4_SCRATCH_RAM_DED_COUNT) },
 387         { "RLC_SPM_SE5_SCRATCH_RAM", SOC15_REG_ENTRY(GC, 0, regRLC_EDC_CNT2),
 388           SOC15_REG_FIELD(RLC_EDC_CNT2, RLC_SPM_SE5_SCRATCH_RAM_SEC_COUNT),
 389           SOC15_REG_FIELD(RLC_EDC_CNT2, RLC_SPM_SE5_SCRATCH_RAM_DED_COUNT) },
 390         { "RLC_SPM_SE6_SCRATCH_RAM", SOC15_REG_ENTRY(GC, 0, regRLC_EDC_CNT2),
 391           SOC15_REG_FIELD(RLC_EDC_CNT2, RLC_SPM_SE6_SCRATCH_RAM_SEC_COUNT),
 392           SOC15_REG_FIELD(RLC_EDC_CNT2, RLC_SPM_SE6_SCRATCH_RAM_DED_COUNT) },
 393         { "RLC_SPM_SE7_SCRATCH_RAM", SOC15_REG_ENTRY(GC, 0, regRLC_EDC_CNT2),
 394           SOC15_REG_FIELD(RLC_EDC_CNT2, RLC_SPM_SE7_SCRATCH_RAM_SEC_COUNT),
 395           SOC15_REG_FIELD(RLC_EDC_CNT2, RLC_SPM_SE7_SCRATCH_RAM_DED_COUNT) },
 396
 397         /* SPI */
 398         { "SPI_SR_MEM", SOC15_REG_ENTRY(GC, 0, regSPI_EDC_CNT),
 399           SOC15_REG_FIELD(SPI_EDC_CNT, SPI_SR_MEM_SEC_COUNT),
 400           SOC15_REG_FIELD(SPI_EDC_CNT, SPI_SR_MEM_DED_COUNT) },
 401         { "SPI_GDS_EXPREQ", SOC15_REG_ENTRY(GC, 0, regSPI_EDC_CNT),
 402           SOC15_REG_FIELD(SPI_EDC_CNT, SPI_GDS_EXPREQ_SEC_COUNT),
 403           SOC15_REG_FIELD(SPI_EDC_CNT, SPI_GDS_EXPREQ_DED_COUNT) },
 404         { "SPI_WB_GRANT_30", SOC15_REG_ENTRY(GC, 0, regSPI_EDC_CNT),
 405           SOC15_REG_FIELD(SPI_EDC_CNT, SPI_WB_GRANT_30_SEC_COUNT),
 406           SOC15_REG_FIELD(SPI_EDC_CNT, SPI_WB_GRANT_30_DED_COUNT) },
 407         { "SPI_LIFE_CNT", SOC15_REG_ENTRY(GC, 0, regSPI_EDC_CNT),
 408           SOC15_REG_FIELD(SPI_EDC_CNT, SPI_LIFE_CNT_SEC_COUNT),
 409           SOC15_REG_FIELD(SPI_EDC_CNT, SPI_LIFE_CNT_DED_COUNT) },
 410
 411         /* SQC - regSQC_EDC_CNT */
 412         { "SQC_DATA_CU0_WRITE_DATA_BUF", SOC15_REG_ENTRY(GC, 0, regSQC_EDC_CNT),
 413           SOC15_REG_FIELD(SQC_EDC_CNT, DATA_CU0_WRITE_DATA_BUF_SEC_COUNT),
 414           SOC15_REG_FIELD(SQC_EDC_CNT, DATA_CU0_WRITE_DATA_BUF_DED_COUNT) },
 415         { "SQC_DATA_CU0_UTCL1_LFIFO", SOC15_REG_ENTRY(GC, 0, regSQC_EDC_CNT),
 416           SOC15_REG_FIELD(SQC_EDC_CNT, DATA_CU0_UTCL1_LFIFO_SEC_COUNT),
 417           SOC15_REG_FIELD(SQC_EDC_CNT, DATA_CU0_UTCL1_LFIFO_DED_COUNT) },
 418         { "SQC_DATA_CU1_WRITE_DATA_BUF", SOC15_REG_ENTRY(GC, 0, regSQC_EDC_CNT),
 419           SOC15_REG_FIELD(SQC_EDC_CNT, DATA_CU1_WRITE_DATA_BUF_SEC_COUNT),
 420           SOC15_REG_FIELD(SQC_EDC_CNT, DATA_CU1_WRITE_DATA_BUF_DED_COUNT) },
 421         { "SQC_DATA_CU1_UTCL1_LFIFO", SOC15_REG_ENTRY(GC, 0, regSQC_EDC_CNT),
 422           SOC15_REG_FIELD(SQC_EDC_CNT, DATA_CU1_UTCL1_LFIFO_SEC_COUNT),
 423           SOC15_REG_FIELD(SQC_EDC_CNT, DATA_CU1_UTCL1_LFIFO_DED_COUNT) },
 424         { "SQC_DATA_CU2_WRITE_DATA_BUF", SOC15_REG_ENTRY(GC, 0, regSQC_EDC_CNT),
 425           SOC15_REG_FIELD(SQC_EDC_CNT, DATA_CU2_WRITE_DATA_BUF_SEC_COUNT),
 426           SOC15_REG_FIELD(SQC_EDC_CNT, DATA_CU2_WRITE_DATA_BUF_DED_COUNT) },
 427         { "SQC_DATA_CU2_UTCL1_LFIFO", SOC15_REG_ENTRY(GC, 0, regSQC_EDC_CNT),
 428           SOC15_REG_FIELD(SQC_EDC_CNT, DATA_CU2_UTCL1_LFIFO_SEC_COUNT),
 429           SOC15_REG_FIELD(SQC_EDC_CNT, DATA_CU2_UTCL1_LFIFO_DED_COUNT) },
 430         { "SQC_DATA_CU3_WRITE_DATA_BUF", SOC15_REG_ENTRY(GC, 0, regSQC_EDC_CNT),
 431           SOC15_REG_FIELD(SQC_EDC_CNT, DATA_CU3_WRITE_DATA_BUF_SEC_COUNT),
 432           SOC15_REG_FIELD(SQC_EDC_CNT, DATA_CU3_WRITE_DATA_BUF_DED_COUNT) },
 433         { "SQC_DATA_CU3_UTCL1_LFIFO", SOC15_REG_ENTRY(GC, 0, regSQC_EDC_CNT),
 434           SOC15_REG_FIELD(SQC_EDC_CNT, DATA_CU3_UTCL1_LFIFO_SEC_COUNT),
 435           SOC15_REG_FIELD(SQC_EDC_CNT, DATA_CU3_UTCL1_LFIFO_DED_COUNT) },
 436
 437         /* SQC - regSQC_EDC_CNT2 */
 438         { "SQC_INST_BANKA_TAG_RAM", SOC15_REG_ENTRY(GC, 0, regSQC_EDC_CNT2),
 439           SOC15_REG_FIELD(SQC_EDC_CNT2, INST_BANKA_TAG_RAM_SEC_COUNT),
 440           SOC15_REG_FIELD(SQC_EDC_CNT2, INST_BANKA_TAG_RAM_DED_COUNT) },
 441         { "SQC_INST_BANKA_BANK_RAM", SOC15_REG_ENTRY(GC, 0, regSQC_EDC_CNT2),
 442           SOC15_REG_FIELD(SQC_EDC_CNT2, INST_BANKA_BANK_RAM_SEC_COUNT),
 443           SOC15_REG_FIELD(SQC_EDC_CNT2, INST_BANKA_BANK_RAM_DED_COUNT) },
 444         { "SQC_DATA_BANKA_TAG_RAM", SOC15_REG_ENTRY(GC, 0, regSQC_EDC_CNT2),
 445           SOC15_REG_FIELD(SQC_EDC_CNT2, DATA_BANKA_TAG_RAM_SEC_COUNT),
 446           SOC15_REG_FIELD(SQC_EDC_CNT2, DATA_BANKA_TAG_RAM_DED_COUNT) },
 447         { "SQC_DATA_BANKA_BANK_RAM", SOC15_REG_ENTRY(GC, 0, regSQC_EDC_CNT2),
 448           SOC15_REG_FIELD(SQC_EDC_CNT2, DATA_BANKA_BANK_RAM_SEC_COUNT),
 449           SOC15_REG_FIELD(SQC_EDC_CNT2, DATA_BANKA_BANK_RAM_DED_COUNT) },
 450         { "SQC_INST_UTCL1_LFIFO", SOC15_REG_ENTRY(GC, 0, regSQC_EDC_CNT2),
 451           SOC15_REG_FIELD(SQC_EDC_CNT2, INST_UTCL1_LFIFO_SEC_COUNT),
 452           SOC15_REG_FIELD(SQC_EDC_CNT2, INST_UTCL1_LFIFO_DED_COUNT) },
 453         { "SQC_DATA_BANKA_DIRTY_BIT_RAM", SOC15_REG_ENTRY(GC, 0, regSQC_EDC_CNT2),
 454           SOC15_REG_FIELD(SQC_EDC_CNT2, DATA_BANKA_DIRTY_BIT_RAM_SEC_COUNT),
 455           SOC15_REG_FIELD(SQC_EDC_CNT2, DATA_BANKA_DIRTY_BIT_RAM_DED_COUNT) },
 456
 457         /* SQC - regSQC_EDC_CNT3 */
 458         { "SQC_INST_BANKB_TAG_RAM", SOC15_REG_ENTRY(GC, 0, regSQC_EDC_CNT3),
 459           SOC15_REG_FIELD(SQC_EDC_CNT3, INST_BANKB_TAG_RAM_SEC_COUNT),
 460           SOC15_REG_FIELD(SQC_EDC_CNT3, INST_BANKB_TAG_RAM_DED_COUNT) },
 461         { "SQC_INST_BANKB_BANK_RAM", SOC15_REG_ENTRY(GC, 0, regSQC_EDC_CNT3),
 462           SOC15_REG_FIELD(SQC_EDC_CNT3, INST_BANKB_BANK_RAM_SEC_COUNT),
 463           SOC15_REG_FIELD(SQC_EDC_CNT3, INST_BANKB_BANK_RAM_DED_COUNT) },
 464         { "SQC_DATA_BANKB_TAG_RAM", SOC15_REG_ENTRY(GC, 0, regSQC_EDC_CNT3),
 465           SOC15_REG_FIELD(SQC_EDC_CNT3, DATA_BANKB_TAG_RAM_SEC_COUNT),
 466           SOC15_REG_FIELD(SQC_EDC_CNT3, DATA_BANKB_TAG_RAM_DED_COUNT) },
 467         { "SQC_DATA_BANKB_BANK_RAM", SOC15_REG_ENTRY(GC, 0, regSQC_EDC_CNT3),
 468           SOC15_REG_FIELD(SQC_EDC_CNT3, DATA_BANKB_BANK_RAM_SEC_COUNT),
 469           SOC15_REG_FIELD(SQC_EDC_CNT3, DATA_BANKB_BANK_RAM_DED_COUNT) },
 470         { "SQC_DATA_BANKB_DIRTY_BIT_RAM", SOC15_REG_ENTRY(GC, 0, regSQC_EDC_CNT3),
 471           SOC15_REG_FIELD(SQC_EDC_CNT3, DATA_BANKB_DIRTY_BIT_RAM_SEC_COUNT),
 472           SOC15_REG_FIELD(SQC_EDC_CNT3, DATA_BANKB_DIRTY_BIT_RAM_DED_COUNT) },
 473
 474         /* SQC - regSQC_EDC_PARITY_CNT3 */
 475         { "SQC_INST_BANKA_UTCL1_MISS_FIFO", SOC15_REG_ENTRY(GC, 0, regSQC_EDC_PARITY_CNT3),
 476           SOC15_REG_FIELD(SQC_EDC_PARITY_CNT3, INST_BANKA_UTCL1_MISS_FIFO_SEC_COUNT),
 477           SOC15_REG_FIELD(SQC_EDC_PARITY_CNT3, INST_BANKA_UTCL1_MISS_FIFO_DED_COUNT) },
 478         { "SQC_INST_BANKA_MISS_FIFO", SOC15_REG_ENTRY(GC, 0, regSQC_EDC_PARITY_CNT3),
 479           SOC15_REG_FIELD(SQC_EDC_PARITY_CNT3, INST_BANKA_MISS_FIFO_SEC_COUNT),
 480           SOC15_REG_FIELD(SQC_EDC_PARITY_CNT3, INST_BANKA_MISS_FIFO_DED_COUNT) },
 481         { "SQC_DATA_BANKA_HIT_FIFO", SOC15_REG_ENTRY(GC, 0, regSQC_EDC_PARITY_CNT3),
 482           SOC15_REG_FIELD(SQC_EDC_PARITY_CNT3, DATA_BANKA_HIT_FIFO_SEC_COUNT),
 483           SOC15_REG_FIELD(SQC_EDC_PARITY_CNT3, DATA_BANKA_HIT_FIFO_DED_COUNT) },
 484         { "SQC_DATA_BANKA_MISS_FIFO", SOC15_REG_ENTRY(GC, 0, regSQC_EDC_PARITY_CNT3),
 485           SOC15_REG_FIELD(SQC_EDC_PARITY_CNT3, DATA_BANKA_MISS_FIFO_SEC_COUNT),
 486           SOC15_REG_FIELD(SQC_EDC_PARITY_CNT3, DATA_BANKA_MISS_FIFO_DED_COUNT) },
 487         { "SQC_INST_BANKB_UTCL1_MISS_FIFO", SOC15_REG_ENTRY(GC, 0, regSQC_EDC_PARITY_CNT3),
 488           SOC15_REG_FIELD(SQC_EDC_PARITY_CNT3, INST_BANKB_UTCL1_MISS_FIFO_SEC_COUNT),
 489           SOC15_REG_FIELD(SQC_EDC_PARITY_CNT3, INST_BANKB_UTCL1_MISS_FIFO_DED_COUNT) },
 490         { "SQC_INST_BANKB_MISS_FIFO", SOC15_REG_ENTRY(GC, 0, regSQC_EDC_PARITY_CNT3),
 491           SOC15_REG_FIELD(SQC_EDC_PARITY_CNT3, INST_BANKB_MISS_FIFO_SEC_COUNT),
 492           SOC15_REG_FIELD(SQC_EDC_PARITY_CNT3, INST_BANKB_MISS_FIFO_DED_COUNT) },
 493         { "SQC_DATA_BANKB_HIT_FIFO", SOC15_REG_ENTRY(GC, 0, regSQC_EDC_PARITY_CNT3),
 494           SOC15_REG_FIELD(SQC_EDC_PARITY_CNT3, DATA_BANKB_HIT_FIFO_SEC_COUNT),
 495           SOC15_REG_FIELD(SQC_EDC_PARITY_CNT3, DATA_BANKB_HIT_FIFO_DED_COUNT) },
 496         { "SQC_DATA_BANKB_MISS_FIFO", SOC15_REG_ENTRY(GC, 0, regSQC_EDC_PARITY_CNT3),
 497           SOC15_REG_FIELD(SQC_EDC_PARITY_CNT3, DATA_BANKB_MISS_FIFO_SEC_COUNT),
 498           SOC15_REG_FIELD(SQC_EDC_PARITY_CNT3, DATA_BANKB_MISS_FIFO_DED_COUNT) },
 499
 500         /* SQ */
 501         { "SQ_LDS_D", SOC15_REG_ENTRY(GC, 0, regSQ_EDC_CNT),
 502           SOC15_REG_FIELD(SQ_EDC_CNT, LDS_D_SEC_COUNT),
 503           SOC15_REG_FIELD(SQ_EDC_CNT, LDS_D_DED_COUNT) },
 504         { "SQ_LDS_I", SOC15_REG_ENTRY(GC, 0, regSQ_EDC_CNT),
 505           SOC15_REG_FIELD(SQ_EDC_CNT, LDS_I_SEC_COUNT),
 506           SOC15_REG_FIELD(SQ_EDC_CNT, LDS_I_DED_COUNT) },
 507         { "SQ_SGPR", SOC15_REG_ENTRY(GC, 0, regSQ_EDC_CNT),
 508           SOC15_REG_FIELD(SQ_EDC_CNT, SGPR_SEC_COUNT),
 509           SOC15_REG_FIELD(SQ_EDC_CNT, SGPR_DED_COUNT) },
 510         { "SQ_VGPR0", SOC15_REG_ENTRY(GC, 0, regSQ_EDC_CNT),
 511           SOC15_REG_FIELD(SQ_EDC_CNT, VGPR0_SEC_COUNT),
 512           SOC15_REG_FIELD(SQ_EDC_CNT, VGPR0_DED_COUNT) },
 513         { "SQ_VGPR1", SOC15_REG_ENTRY(GC, 0, regSQ_EDC_CNT),
 514           SOC15_REG_FIELD(SQ_EDC_CNT, VGPR1_SEC_COUNT),
 515           SOC15_REG_FIELD(SQ_EDC_CNT, VGPR1_DED_COUNT) },
 516         { "SQ_VGPR2", SOC15_REG_ENTRY(GC, 0, regSQ_EDC_CNT),
 517           SOC15_REG_FIELD(SQ_EDC_CNT, VGPR2_SEC_COUNT),
 518           SOC15_REG_FIELD(SQ_EDC_CNT, VGPR2_DED_COUNT) },
 519         { "SQ_VGPR3", SOC15_REG_ENTRY(GC, 0, regSQ_EDC_CNT),
 520           SOC15_REG_FIELD(SQ_EDC_CNT, VGPR3_SEC_COUNT),
 521           SOC15_REG_FIELD(SQ_EDC_CNT, VGPR3_DED_COUNT) },
 522
 523         /* TCP */
 524         { "TCP_CACHE_RAM", SOC15_REG_ENTRY(GC, 0, regTCP_EDC_CNT_NEW),
 525           SOC15_REG_FIELD(TCP_EDC_CNT_NEW, CACHE_RAM_SEC_COUNT),
 526           SOC15_REG_FIELD(TCP_EDC_CNT_NEW, CACHE_RAM_DED_COUNT) },
 527         { "TCP_LFIFO_RAM", SOC15_REG_ENTRY(GC, 0, regTCP_EDC_CNT_NEW),
 528           SOC15_REG_FIELD(TCP_EDC_CNT_NEW, LFIFO_RAM_SEC_COUNT),
 529           SOC15_REG_FIELD(TCP_EDC_CNT_NEW, LFIFO_RAM_DED_COUNT) },
 530         { "TCP_CMD_FIFO", SOC15_REG_ENTRY(GC, 0, regTCP_EDC_CNT_NEW),
 531           SOC15_REG_FIELD(TCP_EDC_CNT_NEW, CMD_FIFO_SEC_COUNT),
 532           SOC15_REG_FIELD(TCP_EDC_CNT_NEW, CMD_FIFO_DED_COUNT) },
 533         { "TCP_VM_FIFO", SOC15_REG_ENTRY(GC, 0, regTCP_EDC_CNT_NEW),
 534           SOC15_REG_FIELD(TCP_EDC_CNT_NEW, VM_FIFO_SEC_COUNT),
 535           SOC15_REG_FIELD(TCP_EDC_CNT_NEW, VM_FIFO_DED_COUNT) },
 536         { "TCP_DB_RAM", SOC15_REG_ENTRY(GC, 0, regTCP_EDC_CNT_NEW),
 537           SOC15_REG_FIELD(TCP_EDC_CNT_NEW, DB_RAM_SEC_COUNT),
 538           SOC15_REG_FIELD(TCP_EDC_CNT_NEW, DB_RAM_DED_COUNT) },
 539         { "TCP_UTCL1_LFIFO0", SOC15_REG_ENTRY(GC, 0, regTCP_EDC_CNT_NEW),
 540           SOC15_REG_FIELD(TCP_EDC_CNT_NEW, UTCL1_LFIFO0_SEC_COUNT),
 541           SOC15_REG_FIELD(TCP_EDC_CNT_NEW, UTCL1_LFIFO0_DED_COUNT) },
 542         { "TCP_UTCL1_LFIFO1", SOC15_REG_ENTRY(GC, 0, regTCP_EDC_CNT_NEW),
 543           SOC15_REG_FIELD(TCP_EDC_CNT_NEW, UTCL1_LFIFO1_SEC_COUNT),
 544           SOC15_REG_FIELD(TCP_EDC_CNT_NEW, UTCL1_LFIFO1_DED_COUNT) },
 545
 546         /* TCI */
 547         { "TCI_WRITE_RAM", SOC15_REG_ENTRY(GC, 0, regTCI_EDC_CNT),
 548           SOC15_REG_FIELD(TCI_EDC_CNT, WRITE_RAM_SEC_COUNT),
 549           SOC15_REG_FIELD(TCI_EDC_CNT, WRITE_RAM_DED_COUNT) },
 550
 551         /* TCC */
 552         { "TCC_CACHE_DATA", SOC15_REG_ENTRY(GC, 0, regTCC_EDC_CNT),
 553           SOC15_REG_FIELD(TCC_EDC_CNT, CACHE_DATA_SEC_COUNT),
 554           SOC15_REG_FIELD(TCC_EDC_CNT, CACHE_DATA_DED_COUNT) },
 555         { "TCC_CACHE_DIRTY", SOC15_REG_ENTRY(GC, 0, regTCC_EDC_CNT),
 556           SOC15_REG_FIELD(TCC_EDC_CNT, CACHE_DIRTY_SEC_COUNT),
 557           SOC15_REG_FIELD(TCC_EDC_CNT, CACHE_DIRTY_DED_COUNT) },
 558         { "TCC_HIGH_RATE_TAG", SOC15_REG_ENTRY(GC, 0, regTCC_EDC_CNT),
 559           SOC15_REG_FIELD(TCC_EDC_CNT, HIGH_RATE_TAG_SEC_COUNT),
 560           SOC15_REG_FIELD(TCC_EDC_CNT, HIGH_RATE_TAG_DED_COUNT) },
 561         { "TCC_LOW_RATE_TAG", SOC15_REG_ENTRY(GC, 0, regTCC_EDC_CNT),
 562           SOC15_REG_FIELD(TCC_EDC_CNT, LOW_RATE_TAG_SEC_COUNT),
 563           SOC15_REG_FIELD(TCC_EDC_CNT, LOW_RATE_TAG_DED_COUNT) },
 564         { "TCC_SRC_FIFO", SOC15_REG_ENTRY(GC, 0, regTCC_EDC_CNT),
 565           SOC15_REG_FIELD(TCC_EDC_CNT, SRC_FIFO_SEC_COUNT),
 566           SOC15_REG_FIELD(TCC_EDC_CNT, SRC_FIFO_DED_COUNT) },
 567         { "TCC_LATENCY_FIFO", SOC15_REG_ENTRY(GC, 0, regTCC_EDC_CNT),
 568           SOC15_REG_FIELD(TCC_EDC_CNT, LATENCY_FIFO_SEC_COUNT),
 569           SOC15_REG_FIELD(TCC_EDC_CNT, LATENCY_FIFO_DED_COUNT) },
 570         { "TCC_LATENCY_FIFO_NEXT_RAM", SOC15_REG_ENTRY(GC, 0, regTCC_EDC_CNT),
 571           SOC15_REG_FIELD(TCC_EDC_CNT, LATENCY_FIFO_NEXT_RAM_SEC_COUNT),
 572           SOC15_REG_FIELD(TCC_EDC_CNT, LATENCY_FIFO_NEXT_RAM_DED_COUNT) },
 573         { "TCC_CACHE_TAG_PROBE_FIFO", SOC15_REG_ENTRY(GC, 0, regTCC_EDC_CNT2),
 574           SOC15_REG_FIELD(TCC_EDC_CNT2, CACHE_TAG_PROBE_FIFO_SEC_COUNT),
 575           SOC15_REG_FIELD(TCC_EDC_CNT2, CACHE_TAG_PROBE_FIFO_DED_COUNT) },
 576         { "TCC_UC_ATOMIC_FIFO", SOC15_REG_ENTRY(GC, 0, regTCC_EDC_CNT2),
 577           SOC15_REG_FIELD(TCC_EDC_CNT2, UC_ATOMIC_FIFO_SEC_COUNT),
 578           SOC15_REG_FIELD(TCC_EDC_CNT2, UC_ATOMIC_FIFO_DED_COUNT) },
 579         { "TCC_WRITE_CACHE_READ", SOC15_REG_ENTRY(GC, 0, regTCC_EDC_CNT2),
 580           SOC15_REG_FIELD(TCC_EDC_CNT2, WRITE_CACHE_READ_SEC_COUNT),
 581           SOC15_REG_FIELD(TCC_EDC_CNT2, WRITE_CACHE_READ_DED_COUNT) },
 582         { "TCC_RETURN_CONTROL", SOC15_REG_ENTRY(GC, 0, regTCC_EDC_CNT2),
 583           SOC15_REG_FIELD(TCC_EDC_CNT2, RETURN_CONTROL_SEC_COUNT),
 584           SOC15_REG_FIELD(TCC_EDC_CNT2, RETURN_CONTROL_DED_COUNT) },
 585         { "TCC_IN_USE_TRANSFER", SOC15_REG_ENTRY(GC, 0, regTCC_EDC_CNT2),
 586           SOC15_REG_FIELD(TCC_EDC_CNT2, IN_USE_TRANSFER_SEC_COUNT),
 587           SOC15_REG_FIELD(TCC_EDC_CNT2, IN_USE_TRANSFER_DED_COUNT) },
 588         { "TCC_IN_USE_DEC", SOC15_REG_ENTRY(GC, 0, regTCC_EDC_CNT2),
 589           SOC15_REG_FIELD(TCC_EDC_CNT2, IN_USE_DEC_SEC_COUNT),
 590           SOC15_REG_FIELD(TCC_EDC_CNT2, IN_USE_DEC_DED_COUNT) },
 591         { "TCC_WRITE_RETURN", SOC15_REG_ENTRY(GC, 0, regTCC_EDC_CNT2),
 592           SOC15_REG_FIELD(TCC_EDC_CNT2, WRITE_RETURN_SEC_COUNT),
 593           SOC15_REG_FIELD(TCC_EDC_CNT2, WRITE_RETURN_DED_COUNT) },
 594         { "TCC_RETURN_DATA", SOC15_REG_ENTRY(GC, 0, regTCC_EDC_CNT2),
 595           SOC15_REG_FIELD(TCC_EDC_CNT2, RETURN_DATA_SEC_COUNT),
 596           SOC15_REG_FIELD(TCC_EDC_CNT2, RETURN_DATA_DED_COUNT) },
 597
 598         /* TCA */
 599         { "TCA_HOLE_FIFO", SOC15_REG_ENTRY(GC, 0, regTCA_EDC_CNT),
 600           SOC15_REG_FIELD(TCA_EDC_CNT, HOLE_FIFO_SEC_COUNT),
 601           SOC15_REG_FIELD(TCA_EDC_CNT, HOLE_FIFO_DED_COUNT) },
 602         { "TCA_REQ_FIFO", SOC15_REG_ENTRY(GC, 0, regTCA_EDC_CNT),
 603           SOC15_REG_FIELD(TCA_EDC_CNT, REQ_FIFO_SEC_COUNT),
 604           SOC15_REG_FIELD(TCA_EDC_CNT, REQ_FIFO_DED_COUNT) },
 605
 606         /* TCX */
 607         { "TCX_GROUP0", SOC15_REG_ENTRY(GC, 0, regTCX_EDC_CNT),
 608           SOC15_REG_FIELD(TCX_EDC_CNT, GROUP0_SEC_COUNT),
 609           SOC15_REG_FIELD(TCX_EDC_CNT, GROUP0_DED_COUNT) },
 610         { "TCX_GROUP1", SOC15_REG_ENTRY(GC, 0, regTCX_EDC_CNT),
 611           SOC15_REG_FIELD(TCX_EDC_CNT, GROUP1_SEC_COUNT),
 612           SOC15_REG_FIELD(TCX_EDC_CNT, GROUP1_DED_COUNT) },
 613         { "TCX_GROUP2", SOC15_REG_ENTRY(GC, 0, regTCX_EDC_CNT),
 614           SOC15_REG_FIELD(TCX_EDC_CNT, GROUP2_SEC_COUNT),
 615           SOC15_REG_FIELD(TCX_EDC_CNT, GROUP2_DED_COUNT) },
 616         { "TCX_GROUP3", SOC15_REG_ENTRY(GC, 0, regTCX_EDC_CNT),
 617           SOC15_REG_FIELD(TCX_EDC_CNT, GROUP3_SEC_COUNT),
 618           SOC15_REG_FIELD(TCX_EDC_CNT, GROUP3_DED_COUNT) },
 619         { "TCX_GROUP4", SOC15_REG_ENTRY(GC, 0, regTCX_EDC_CNT),
 620           SOC15_REG_FIELD(TCX_EDC_CNT, GROUP4_SEC_COUNT),
 621           SOC15_REG_FIELD(TCX_EDC_CNT, GROUP4_DED_COUNT) },
 622         { "TCX_GROUP5", SOC15_REG_ENTRY(GC, 0, regTCX_EDC_CNT),
 623           SOC15_REG_FIELD(TCX_EDC_CNT, GROUP5_SED_COUNT), 0, 0 },
 624         { "TCX_GROUP6", SOC15_REG_ENTRY(GC, 0, regTCX_EDC_CNT),
 625           SOC15_REG_FIELD(TCX_EDC_CNT, GROUP6_SED_COUNT), 0, 0 },
 626         { "TCX_GROUP7", SOC15_REG_ENTRY(GC, 0, regTCX_EDC_CNT),
 627           SOC15_REG_FIELD(TCX_EDC_CNT, GROUP7_SED_COUNT), 0, 0 },
 628         { "TCX_GROUP8", SOC15_REG_ENTRY(GC, 0, regTCX_EDC_CNT),
 629           SOC15_REG_FIELD(TCX_EDC_CNT, GROUP8_SED_COUNT), 0, 0 },
 630         { "TCX_GROUP9", SOC15_REG_ENTRY(GC, 0, regTCX_EDC_CNT),
 631           SOC15_REG_FIELD(TCX_EDC_CNT, GROUP9_SED_COUNT), 0, 0 },
 632         { "TCX_GROUP10", SOC15_REG_ENTRY(GC, 0, regTCX_EDC_CNT),
 633           SOC15_REG_FIELD(TCX_EDC_CNT, GROUP10_SED_COUNT), 0, 0 },
 634         { "TCX_GROUP11", SOC15_REG_ENTRY(GC, 0, regTCX_EDC_CNT2),
 635           SOC15_REG_FIELD(TCX_EDC_CNT2, GROUP11_SED_COUNT), 0, 0 },
 636         { "TCX_GROUP12", SOC15_REG_ENTRY(GC, 0, regTCX_EDC_CNT2),
 637           SOC15_REG_FIELD(TCX_EDC_CNT2, GROUP12_SED_COUNT), 0, 0 },
 638         { "TCX_GROUP13", SOC15_REG_ENTRY(GC, 0, regTCX_EDC_CNT2),
 639           SOC15_REG_FIELD(TCX_EDC_CNT2, GROUP13_SED_COUNT), 0, 0 },
 640         { "TCX_GROUP14", SOC15_REG_ENTRY(GC, 0, regTCX_EDC_CNT2),
 641           SOC15_REG_FIELD(TCX_EDC_CNT2, GROUP14_SED_COUNT), 0, 0 },
 642
 643         /* TD */
 644         { "TD_SS_FIFO_LO", SOC15_REG_ENTRY(GC, 0, regTD_EDC_CNT),
 645           SOC15_REG_FIELD(TD_EDC_CNT, SS_FIFO_LO_SEC_COUNT),
 646           SOC15_REG_FIELD(TD_EDC_CNT, SS_FIFO_LO_DED_COUNT) },
 647         { "TD_SS_FIFO_HI", SOC15_REG_ENTRY(GC, 0, regTD_EDC_CNT),
 648           SOC15_REG_FIELD(TD_EDC_CNT, SS_FIFO_HI_SEC_COUNT),
 649           SOC15_REG_FIELD(TD_EDC_CNT, SS_FIFO_HI_DED_COUNT) },
 650         { "TD_CS_FIFO", SOC15_REG_ENTRY(GC, 0, regTD_EDC_CNT),
 651           SOC15_REG_FIELD(TD_EDC_CNT, CS_FIFO_SEC_COUNT),
 652           SOC15_REG_FIELD(TD_EDC_CNT, CS_FIFO_DED_COUNT) },
 653
 654         /* TA */
 655         { "TA_FS_DFIFO", SOC15_REG_ENTRY(GC, 0, regTA_EDC_CNT),
 656           SOC15_REG_FIELD(TA_EDC_CNT, TA_FS_DFIFO_SEC_COUNT),
 657           SOC15_REG_FIELD(TA_EDC_CNT, TA_FS_DFIFO_DED_COUNT) },
 658         { "TA_FS_AFIFO_LO", SOC15_REG_ENTRY(GC, 0, regTA_EDC_CNT),
 659           SOC15_REG_FIELD(TA_EDC_CNT, TA_FS_AFIFO_LO_SEC_COUNT),
 660           SOC15_REG_FIELD(TA_EDC_CNT, TA_FS_AFIFO_LO_DED_COUNT) },
 661         { "TA_FL_LFIFO", SOC15_REG_ENTRY(GC, 0, regTA_EDC_CNT),
 662           SOC15_REG_FIELD(TA_EDC_CNT, TA_FL_LFIFO_SEC_COUNT),
 663           SOC15_REG_FIELD(TA_EDC_CNT, TA_FL_LFIFO_DED_COUNT) },
 664         { "TA_FX_LFIFO", SOC15_REG_ENTRY(GC, 0, regTA_EDC_CNT),
 665           SOC15_REG_FIELD(TA_EDC_CNT, TA_FX_LFIFO_SEC_COUNT),
 666           SOC15_REG_FIELD(TA_EDC_CNT, TA_FX_LFIFO_DED_COUNT) },
 667         { "TA_FS_CFIFO", SOC15_REG_ENTRY(GC, 0, regTA_EDC_CNT),
 668           SOC15_REG_FIELD(TA_EDC_CNT, TA_FS_CFIFO_SEC_COUNT),
 669           SOC15_REG_FIELD(TA_EDC_CNT, TA_FS_CFIFO_DED_COUNT) },
 670         { "TA_FS_AFIFO_HI", SOC15_REG_ENTRY(GC, 0, regTA_EDC_CNT),
 671           SOC15_REG_FIELD(TA_EDC_CNT, TA_FS_AFIFO_HI_SEC_COUNT),
 672           SOC15_REG_FIELD(TA_EDC_CNT, TA_FS_AFIFO_HI_DED_COUNT) },
 673
 674         /* EA - regGCEA_EDC_CNT */
 675         { "EA_DRAMRD_CMDMEM", SOC15_REG_ENTRY(GC, 0, regGCEA_EDC_CNT),
 676           SOC15_REG_FIELD(GCEA_EDC_CNT, DRAMRD_CMDMEM_SEC_COUNT),
 677           SOC15_REG_FIELD(GCEA_EDC_CNT, DRAMRD_CMDMEM_DED_COUNT) },
 678         { "EA_DRAMWR_CMDMEM", SOC15_REG_ENTRY(GC, 0, regGCEA_EDC_CNT),
 679           SOC15_REG_FIELD(GCEA_EDC_CNT, DRAMWR_CMDMEM_SEC_COUNT),
 680           SOC15_REG_FIELD(GCEA_EDC_CNT, DRAMWR_CMDMEM_DED_COUNT) },
 681         { "EA_DRAMWR_DATAMEM", SOC15_REG_ENTRY(GC, 0, regGCEA_EDC_CNT),
 682           SOC15_REG_FIELD(GCEA_EDC_CNT, DRAMWR_DATAMEM_SEC_COUNT),
 683           SOC15_REG_FIELD(GCEA_EDC_CNT, DRAMWR_DATAMEM_DED_COUNT) },
 684         { "EA_RRET_TAGMEM", SOC15_REG_ENTRY(GC, 0, regGCEA_EDC_CNT),
 685           SOC15_REG_FIELD(GCEA_EDC_CNT, RRET_TAGMEM_SEC_COUNT),
 686           SOC15_REG_FIELD(GCEA_EDC_CNT, RRET_TAGMEM_DED_COUNT) },
 687         { "EA_WRET_TAGMEM", SOC15_REG_ENTRY(GC, 0, regGCEA_EDC_CNT),
 688           SOC15_REG_FIELD(GCEA_EDC_CNT, WRET_TAGMEM_SEC_COUNT),
 689           SOC15_REG_FIELD(GCEA_EDC_CNT, WRET_TAGMEM_DED_COUNT) },
 690         { "EA_IOWR_DATAMEM", SOC15_REG_ENTRY(GC, 0, regGCEA_EDC_CNT),
 691           SOC15_REG_FIELD(GCEA_EDC_CNT, IOWR_DATAMEM_SEC_COUNT),
 692           SOC15_REG_FIELD(GCEA_EDC_CNT, IOWR_DATAMEM_DED_COUNT) },
 693         { "EA_DRAMRD_PAGEMEM", SOC15_REG_ENTRY(GC, 0, regGCEA_EDC_CNT),
 694           SOC15_REG_FIELD(GCEA_EDC_CNT, DRAMRD_PAGEMEM_SED_COUNT), 0, 0 },
 695         { "EA_DRAMWR_PAGEMEM", SOC15_REG_ENTRY(GC, 0, regGCEA_EDC_CNT),
 696           SOC15_REG_FIELD(GCEA_EDC_CNT, DRAMWR_PAGEMEM_SED_COUNT), 0, 0 },
 697         { "EA_IORD_CMDMEM", SOC15_REG_ENTRY(GC, 0, regGCEA_EDC_CNT),
 698           SOC15_REG_FIELD(GCEA_EDC_CNT, IORD_CMDMEM_SED_COUNT), 0, 0 },
 699         { "EA_IOWR_CMDMEM", SOC15_REG_ENTRY(GC, 0, regGCEA_EDC_CNT),
 700           SOC15_REG_FIELD(GCEA_EDC_CNT, IOWR_CMDMEM_SED_COUNT), 0, 0 },
 701
 702         /* EA - regGCEA_EDC_CNT2 */
 703         { "EA_GMIRD_CMDMEM", SOC15_REG_ENTRY(GC, 0, regGCEA_EDC_CNT2),
 704           SOC15_REG_FIELD(GCEA_EDC_CNT2, GMIRD_CMDMEM_SEC_COUNT),
 705           SOC15_REG_FIELD(GCEA_EDC_CNT2, GMIRD_CMDMEM_DED_COUNT) },
 706         { "EA_GMIWR_CMDMEM", SOC15_REG_ENTRY(GC, 0, regGCEA_EDC_CNT2),
 707           SOC15_REG_FIELD(GCEA_EDC_CNT2, GMIWR_CMDMEM_SEC_COUNT),
 708           SOC15_REG_FIELD(GCEA_EDC_CNT2, GMIWR_CMDMEM_DED_COUNT) },
 709         { "EA_GMIWR_DATAMEM", SOC15_REG_ENTRY(GC, 0, regGCEA_EDC_CNT2),
 710           SOC15_REG_FIELD(GCEA_EDC_CNT2, GMIWR_DATAMEM_SEC_COUNT),
 711           SOC15_REG_FIELD(GCEA_EDC_CNT2, GMIWR_DATAMEM_DED_COUNT) },
 712         { "EA_GMIRD_PAGEMEM", SOC15_REG_ENTRY(GC, 0, regGCEA_EDC_CNT2),
 713           SOC15_REG_FIELD(GCEA_EDC_CNT2, GMIRD_PAGEMEM_SED_COUNT), 0, 0 },
 714         { "EA_GMIWR_PAGEMEM", SOC15_REG_ENTRY(GC, 0, regGCEA_EDC_CNT2),
 715           SOC15_REG_FIELD(GCEA_EDC_CNT2, GMIWR_PAGEMEM_SED_COUNT), 0, 0 },
 716         { "EA_MAM_D0MEM", SOC15_REG_ENTRY(GC, 0, regGCEA_EDC_CNT2),
 717           SOC15_REG_FIELD(GCEA_EDC_CNT2, MAM_D0MEM_SED_COUNT),
 718           SOC15_REG_FIELD(GCEA_EDC_CNT2, MAM_D0MEM_DED_COUNT) },
 719         { "EA_MAM_D1MEM", SOC15_REG_ENTRY(GC, 0, regGCEA_EDC_CNT2),
 720           SOC15_REG_FIELD(GCEA_EDC_CNT2, MAM_D1MEM_SED_COUNT),
 721           SOC15_REG_FIELD(GCEA_EDC_CNT2, MAM_D1MEM_DED_COUNT) },
 722         { "EA_MAM_D2MEM", SOC15_REG_ENTRY(GC, 0, regGCEA_EDC_CNT2),
 723           SOC15_REG_FIELD(GCEA_EDC_CNT2, MAM_D2MEM_SED_COUNT),
 724           SOC15_REG_FIELD(GCEA_EDC_CNT2, MAM_D2MEM_DED_COUNT) },
 725         { "EA_MAM_D3MEM", SOC15_REG_ENTRY(GC, 0, regGCEA_EDC_CNT2),
 726           SOC15_REG_FIELD(GCEA_EDC_CNT2, MAM_D3MEM_SED_COUNT),
 727           SOC15_REG_FIELD(GCEA_EDC_CNT2, MAM_D3MEM_DED_COUNT) },
 728
 729         /* EA - regGCEA_EDC_CNT3 */
 730         { "EA_DRAMRD_PAGEMEM", SOC15_REG_ENTRY(GC, 0, regGCEA_EDC_CNT3), 0, 0,
 731           SOC15_REG_FIELD(GCEA_EDC_CNT3, DRAMRD_PAGEMEM_DED_COUNT) },
 732         { "EA_DRAMWR_PAGEMEM", SOC15_REG_ENTRY(GC, 0, regGCEA_EDC_CNT3), 0, 0,
 733           SOC15_REG_FIELD(GCEA_EDC_CNT3, DRAMWR_PAGEMEM_DED_COUNT) },
 734         { "EA_IORD_CMDMEM", SOC15_REG_ENTRY(GC, 0, regGCEA_EDC_CNT3), 0, 0,
 735           SOC15_REG_FIELD(GCEA_EDC_CNT3, IORD_CMDMEM_DED_COUNT) },
 736         { "EA_IOWR_CMDMEM", SOC15_REG_ENTRY(GC, 0, regGCEA_EDC_CNT3), 0, 0,
 737           SOC15_REG_FIELD(GCEA_EDC_CNT3, IOWR_CMDMEM_DED_COUNT) },
 738         { "EA_GMIRD_PAGEMEM", SOC15_REG_ENTRY(GC, 0, regGCEA_EDC_CNT3), 0, 0,
 739           SOC15_REG_FIELD(GCEA_EDC_CNT3, GMIRD_PAGEMEM_DED_COUNT) },
 740         { "EA_GMIWR_PAGEMEM", SOC15_REG_ENTRY(GC, 0, regGCEA_EDC_CNT3), 0, 0,
 741           SOC15_REG_FIELD(GCEA_EDC_CNT3, GMIWR_PAGEMEM_DED_COUNT) },
 742         { "EA_MAM_A0MEM", SOC15_REG_ENTRY(GC, 0, regGCEA_EDC_CNT3),
 743           SOC15_REG_FIELD(GCEA_EDC_CNT3, MAM_A0MEM_SEC_COUNT),
 744           SOC15_REG_FIELD(GCEA_EDC_CNT3, MAM_A0MEM_DED_COUNT) },
 745         { "EA_MAM_A1MEM", SOC15_REG_ENTRY(GC, 0, regGCEA_EDC_CNT3),
 746           SOC15_REG_FIELD(GCEA_EDC_CNT3, MAM_A1MEM_SEC_COUNT),
 747           SOC15_REG_FIELD(GCEA_EDC_CNT3, MAM_A1MEM_DED_COUNT) },
 748         { "EA_MAM_A2MEM", SOC15_REG_ENTRY(GC, 0, regGCEA_EDC_CNT3),
 749           SOC15_REG_FIELD(GCEA_EDC_CNT3, MAM_A2MEM_SEC_COUNT),
 750           SOC15_REG_FIELD(GCEA_EDC_CNT3, MAM_A2MEM_DED_COUNT) },
 751         { "EA_MAM_A3MEM", SOC15_REG_ENTRY(GC, 0, regGCEA_EDC_CNT3),
 752           SOC15_REG_FIELD(GCEA_EDC_CNT3, MAM_A3MEM_SEC_COUNT),
 753           SOC15_REG_FIELD(GCEA_EDC_CNT3, MAM_A3MEM_DED_COUNT) },
 754         { "EA_MAM_AFMEM", SOC15_REG_ENTRY(GC, 0, regGCEA_EDC_CNT3),
 755           SOC15_REG_FIELD(GCEA_EDC_CNT3, MAM_AFMEM_SEC_COUNT),
 756           SOC15_REG_FIELD(GCEA_EDC_CNT3, MAM_AFMEM_DED_COUNT) },
 757 };
 758
 759 static const char * const vml2_walker_mems[] = {
 760         "UTC_VML2_CACHE_PDE0_MEM0",
 761         "UTC_VML2_CACHE_PDE0_MEM1",
 762         "UTC_VML2_CACHE_PDE1_MEM0",
 763         "UTC_VML2_CACHE_PDE1_MEM1",
 764         "UTC_VML2_CACHE_PDE2_MEM0",
 765         "UTC_VML2_CACHE_PDE2_MEM1",
 766         "UTC_VML2_RDIF_ARADDRS",
 767         "UTC_VML2_RDIF_LOG_FIFO",
 768         "UTC_VML2_QUEUE_REQ",
 769         "UTC_VML2_QUEUE_RET",
 770 };
 771
 772 static struct gfx_v9_4_2_utc_block gfx_v9_4_2_utc_blocks[] = {
 773         { VML2_MEM, 8, 2, 2,
 774           { SOC15_REG_ENTRY(GC, 0, regVML2_MEM_ECC_INDEX) },
 775           { SOC15_REG_ENTRY(GC, 0, regVML2_MEM_ECC_CNTL) },
 776           SOC15_REG_FIELD(VML2_MEM_ECC_CNTL, SEC_COUNT),
 777           SOC15_REG_FIELD(VML2_MEM_ECC_CNTL, DED_COUNT),
 778           REG_SET_FIELD(0, VML2_MEM_ECC_CNTL, WRITE_COUNTERS, 1) },
 779         { VML2_WALKER_MEM, ARRAY_SIZE(vml2_walker_mems), 1, 1,
 780           { SOC15_REG_ENTRY(GC, 0, regVML2_WALKER_MEM_ECC_INDEX) },
 781           { SOC15_REG_ENTRY(GC, 0, regVML2_WALKER_MEM_ECC_CNTL) },
 782           SOC15_REG_FIELD(VML2_WALKER_MEM_ECC_CNTL, SEC_COUNT),
 783           SOC15_REG_FIELD(VML2_WALKER_MEM_ECC_CNTL, DED_COUNT),
 784           REG_SET_FIELD(0, VML2_WALKER_MEM_ECC_CNTL, WRITE_COUNTERS, 1) },
 785         { UTCL2_MEM, 18, 1, 2,
 786           { SOC15_REG_ENTRY(GC, 0, regUTCL2_MEM_ECC_INDEX) },
 787           { SOC15_REG_ENTRY(GC, 0, regUTCL2_MEM_ECC_CNTL) },
 788           SOC15_REG_FIELD(UTCL2_MEM_ECC_CNTL, SEC_COUNT),
 789           SOC15_REG_FIELD(UTCL2_MEM_ECC_CNTL, DED_COUNT),
 790           REG_SET_FIELD(0, UTCL2_MEM_ECC_CNTL, WRITE_COUNTERS, 1) },
 791         { ATC_L2_CACHE_2M, 8, 2, 1,
 792           { SOC15_REG_ENTRY(GC, 0, regATC_L2_CACHE_2M_DSM_INDEX) },
 793           { SOC15_REG_ENTRY(GC, 0, regATC_L2_CACHE_2M_DSM_CNTL) },
 794           SOC15_REG_FIELD(ATC_L2_CACHE_2M_DSM_CNTL, SEC_COUNT),
 795           SOC15_REG_FIELD(ATC_L2_CACHE_2M_DSM_CNTL, DED_COUNT),
 796           REG_SET_FIELD(0, ATC_L2_CACHE_2M_DSM_CNTL, WRITE_COUNTERS, 1) },
 797         { ATC_L2_CACHE_32K, 8, 2, 2,
 798           { SOC15_REG_ENTRY(GC, 0, regATC_L2_CACHE_32K_DSM_INDEX) },
 799           { SOC15_REG_ENTRY(GC, 0, regATC_L2_CACHE_32K_DSM_CNTL) },
 800           SOC15_REG_FIELD(ATC_L2_CACHE_32K_DSM_CNTL, SEC_COUNT),
 801           SOC15_REG_FIELD(ATC_L2_CACHE_32K_DSM_CNTL, DED_COUNT),
 802           REG_SET_FIELD(0, ATC_L2_CACHE_32K_DSM_CNTL, WRITE_COUNTERS, 1) },
 803         { ATC_L2_CACHE_4K, 8, 2, 8,
 804           { SOC15_REG_ENTRY(GC, 0, regATC_L2_CACHE_4K_DSM_INDEX) },
 805           { SOC15_REG_ENTRY(GC, 0, regATC_L2_CACHE_4K_DSM_CNTL) },
 806           SOC15_REG_FIELD(ATC_L2_CACHE_4K_DSM_CNTL, SEC_COUNT),
 807           SOC15_REG_FIELD(ATC_L2_CACHE_4K_DSM_CNTL, DED_COUNT),
 808           REG_SET_FIELD(0, ATC_L2_CACHE_4K_DSM_CNTL, WRITE_COUNTERS, 1) },
 809 };
 810
 811 static const struct soc15_reg_entry gfx_v9_4_2_rdrsp_status_regs =
 812         { SOC15_REG_ENTRY(GC, 0, regGCEA_ERR_STATUS), 0, 1, 16 };
 813
 814 static int gfx_v9_4_2_get_reg_error_count(struct amdgpu_device *adev,
 815                                           const struct soc15_reg_entry *reg,
 816                                           uint32_t se_id, uint32_t inst_id,
 817                                           uint32_t value, uint32_t *sec_count,
 818                                           uint32_t *ded_count)
 819 {
 820         uint32_t i;
 821         uint32_t sec_cnt, ded_cnt;
 822
 823         for (i = 0; i < ARRAY_SIZE(gfx_v9_4_2_ras_fields); i++) {
 824                 if (gfx_v9_4_2_ras_fields[i].reg_offset != reg->reg_offset ||
 825                     gfx_v9_4_2_ras_fields[i].seg != reg->seg ||
 826                     gfx_v9_4_2_ras_fields[i].inst != reg->inst)
 827                         continue;
 828
 829                 sec_cnt = SOC15_RAS_REG_FIELD_VAL(
 830                         value, gfx_v9_4_2_ras_fields[i], sec);
 831                 if (sec_cnt) {
 832                         dev_info(adev->dev,
 833                                  "GFX SubBlock %s, Instance[%d][%d], SEC %d\n",
 834                                  gfx_v9_4_2_ras_fields[i].name, se_id, inst_id,
 835                                  sec_cnt);
 836                         *sec_count += sec_cnt;
 837                 }
 838
 839                 ded_cnt = SOC15_RAS_REG_FIELD_VAL(
 840                         value, gfx_v9_4_2_ras_fields[i], ded);
 841                 if (ded_cnt) {
 842                         dev_info(adev->dev,
 843                                  "GFX SubBlock %s, Instance[%d][%d], DED %d\n",
 844                                  gfx_v9_4_2_ras_fields[i].name, se_id, inst_id,
 845                                  ded_cnt);
 846                         *ded_count += ded_cnt;
 847                 }
 848         }
 849
 850         return 0;
 851 }
 852
 853 static int gfx_v9_4_2_query_sram_edc_count(struct amdgpu_device *adev,
 854                                 uint32_t *sec_count, uint32_t *ded_count)
 855 {
 856         uint32_t i, j, k, data;
 857         uint32_t sec_cnt = 0, ded_cnt = 0;
 858
 859         if (sec_count && ded_count) {
 860                 *sec_count = 0;
 861                 *ded_count = 0;
 862         }
 863
 864         mutex_lock(&adev->grbm_idx_mutex);
 865
 866         for (i = 0; i < ARRAY_SIZE(gfx_v9_4_2_edc_counter_regs); i++) {
 867                 for (j = 0; j < gfx_v9_4_2_edc_counter_regs[i].se_num; j++) {
 868                         for (k = 0; k < gfx_v9_4_2_edc_counter_regs[i].instance;
 869                              k++) {
 870                                 gfx_v9_4_2_select_se_sh(adev, j, 0, k);
 871
 872                                 /* if sec/ded_count is null, just clear counter */
 873                                 if (!sec_count || !ded_count) {
 874                                         WREG32(SOC15_REG_ENTRY_OFFSET(
 875                                                 gfx_v9_4_2_edc_counter_regs[i]), 0);
 876                                         continue;
 877                                 }
 878
 879                                 data = RREG32(SOC15_REG_ENTRY_OFFSET(
 880                                         gfx_v9_4_2_edc_counter_regs[i]));
 881
 882                                 if (!data)
 883                                         continue;
 884
 885                                 gfx_v9_4_2_get_reg_error_count(adev,
 886                                         &gfx_v9_4_2_edc_counter_regs[i],
 887                                         j, k, data, &sec_cnt, &ded_cnt);
 888
 889                                 /* clear counter after read */
 890                                 WREG32(SOC15_REG_ENTRY_OFFSET(
 891                                         gfx_v9_4_2_edc_counter_regs[i]), 0);
 892                         }
 893                 }
 894         }
 895
 896         if (sec_count && ded_count) {
 897                 *sec_count += sec_cnt;
 898                 *ded_count += ded_cnt;
 899         }
 900
 901         gfx_v9_4_2_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
 902         mutex_unlock(&adev->grbm_idx_mutex);
 903
 904         return 0;
 905 }
 906
 907 static void gfx_v9_4_2_log_utc_edc_count(struct amdgpu_device *adev,
 908                                          struct gfx_v9_4_2_utc_block *blk,
 909                                          uint32_t instance, uint32_t sec_cnt,
 910                                          uint32_t ded_cnt)
 911 {
 912         uint32_t bank, way, mem;
 913         static const char *vml2_way_str[] = { "BIGK", "4K" };
 914         static const char *utcl2_rounter_str[] = { "VMC", "APT" };
 915
 916         mem = instance % blk->num_mem_blocks;
 917         way = (instance / blk->num_mem_blocks) % blk->num_ways;
 918         bank = instance / (blk->num_mem_blocks * blk->num_ways);
 919
 920         switch (blk->type) {
 921         case VML2_MEM:
 922                 dev_info(
 923                         adev->dev,
 924                         "GFX SubBlock UTC_VML2_BANK_CACHE_%d_%s_MEM%d, SED %d, DED %d\n",
 925                         bank, vml2_way_str[way], mem, sec_cnt, ded_cnt);
 926                 break;
 927         case VML2_WALKER_MEM:
 928                 dev_info(adev->dev, "GFX SubBlock %s, SED %d, DED %d\n",
 929                          vml2_walker_mems[bank], sec_cnt, ded_cnt);
 930                 break;
 931         case UTCL2_MEM:
 932                 dev_info(
 933                         adev->dev,
 934                         "GFX SubBlock UTCL2_ROUTER_IFIF%d_GROUP0_%s, SED %d, DED %d\n",
 935                         bank, utcl2_rounter_str[mem], sec_cnt, ded_cnt);
 936                 break;
 937         case ATC_L2_CACHE_2M:
 938                 dev_info(
 939                         adev->dev,
 940                         "GFX SubBlock UTC_ATCL2_CACHE_2M_BANK%d_WAY%d_MEM, SED %d, DED %d\n",
 941                         bank, way, sec_cnt, ded_cnt);
 942                 break;
 943         case ATC_L2_CACHE_32K:
 944                 dev_info(
 945                         adev->dev,
 946                         "GFX SubBlock UTC_ATCL2_CACHE_32K_BANK%d_WAY%d_MEM%d, SED %d, DED %d\n",
 947                         bank, way, mem, sec_cnt, ded_cnt);
 948                 break;
 949         case ATC_L2_CACHE_4K:
 950                 dev_info(
 951                         adev->dev,
 952                         "GFX SubBlock UTC_ATCL2_CACHE_4K_BANK%d_WAY%d_MEM%d, SED %d, DED %d\n",
 953                         bank, way, mem, sec_cnt, ded_cnt);
 954                 break;
 955         }
 956 }
 957
 958 static int gfx_v9_4_2_query_utc_edc_count(struct amdgpu_device *adev,
 959                                           uint32_t *sec_count,
 960                                           uint32_t *ded_count)
 961 {
 962         uint32_t i, j, data;
 963         uint32_t sec_cnt, ded_cnt;
 964         uint32_t num_instances;
 965         struct gfx_v9_4_2_utc_block *blk;
 966
 967         if (sec_count && ded_count) {
 968                 *sec_count = 0;
 969                 *ded_count = 0;
 970         }
 971
 972         for (i = 0; i < ARRAY_SIZE(gfx_v9_4_2_utc_blocks); i++) {
 973                 blk = &gfx_v9_4_2_utc_blocks[i];
 974                 num_instances =
 975                         blk->num_banks * blk->num_ways * blk->num_mem_blocks;
 976                 for (j = 0; j < num_instances; j++) {
 977                         WREG32(SOC15_REG_ENTRY_OFFSET(blk->idx_reg), j);
 978
 979                         /* if sec/ded_count is NULL, just clear counter */
 980                         if (!sec_count || !ded_count) {
 981                                 WREG32(SOC15_REG_ENTRY_OFFSET(blk->data_reg),
 982                                        blk->clear);
 983                                 continue;
 984                         }
 985
 986                         data = RREG32(SOC15_REG_ENTRY_OFFSET(blk->data_reg));
 987                         if (!data)
 988                                 continue;
 989
 990                         sec_cnt = SOC15_RAS_REG_FIELD_VAL(data, *blk, sec);
 991                         *sec_count += sec_cnt;
 992                         ded_cnt = SOC15_RAS_REG_FIELD_VAL(data, *blk, ded);
 993                         *ded_count += ded_cnt;
 994
 995                         /* clear counter after read */
 996                         WREG32(SOC15_REG_ENTRY_OFFSET(blk->data_reg),
 997                                blk->clear);
 998
 999                         /* print the edc count */
1000                         gfx_v9_4_2_log_utc_edc_count(adev, blk, j, sec_cnt,
1001                                                      ded_cnt);
1002                 }
1003         }
1004
1005         return 0;
1006 }
1007
1008 int gfx_v9_4_2_query_ras_error_count(struct amdgpu_device *adev,
1009                                    void *ras_error_status)
1010 {
1011         struct ras_err_data *err_data = (struct ras_err_data *)ras_error_status;
1012         uint32_t sec_count = 0, ded_count = 0;
1013
1014         if (!amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__GFX))
1015                 return -EINVAL;
1016
1017         err_data->ue_count = 0;
1018         err_data->ce_count = 0;
1019
1020         gfx_v9_4_2_query_sram_edc_count(adev, &sec_count, &ded_count);
1021         err_data->ce_count += sec_count;
1022         err_data->ue_count += ded_count;
1023
1024         gfx_v9_4_2_query_utc_edc_count(adev, &sec_count, &ded_count);
1025         err_data->ce_count += sec_count;
1026         err_data->ue_count += ded_count;
1027
1028         return 0;
1029 }
1030
1031 static void gfx_v9_4_2_reset_utc_err_status(struct amdgpu_device *adev)
1032 {
1033         WREG32_SOC15(GC, 0, regUTCL2_MEM_ECC_STATUS, 0x3);
1034         WREG32_SOC15(GC, 0, regVML2_MEM_ECC_STATUS, 0x3);
1035         WREG32_SOC15(GC, 0, regVML2_WALKER_MEM_ECC_STATUS, 0x3);
1036 }
1037
1038 static void gfx_v9_4_2_reset_ea_err_status(struct amdgpu_device *adev)
1039 {
1040         uint32_t i, j;
1041
1042         mutex_lock(&adev->grbm_idx_mutex);
1043         for (i = 0; i < gfx_v9_4_2_rdrsp_status_regs.se_num; i++) {
1044                 for (j = 0; j < gfx_v9_4_2_rdrsp_status_regs.instance;
1045                      j++) {
1046                         gfx_v9_4_2_select_se_sh(adev, i, 0, j);
1047                         WREG32(SOC15_REG_ENTRY_OFFSET(gfx_v9_4_2_rdrsp_status_regs), 0x10);
1048                 }
1049         }
1050         gfx_v9_4_2_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
1051         mutex_unlock(&adev->grbm_idx_mutex);
1052 }
1053
1054 void gfx_v9_4_2_reset_ras_error_count(struct amdgpu_device *adev)
1055 {
1056         if (!amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__GFX))
1057                 return;
1058
1059         gfx_v9_4_2_query_sram_edc_count(adev, NULL, NULL);
1060         gfx_v9_4_2_query_utc_edc_count(adev, NULL, NULL);
1061 }
1062
1063 int gfx_v9_4_2_ras_error_inject(struct amdgpu_device *adev, void *inject_if)
1064 {
1065         struct ras_inject_if *info = (struct ras_inject_if *)inject_if;
1066         int ret;
1067         struct ta_ras_trigger_error_input block_info = { 0 };
1068
1069         if (!amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__GFX))
1070                 return -EINVAL;
1071
1072         block_info.block_id = amdgpu_ras_block_to_ta(info->head.block);
1073         block_info.sub_block_index = info->head.sub_block_index;
1074         block_info.inject_error_type = amdgpu_ras_error_to_ta(info->head.type);
1075         block_info.address = info->address;
1076         block_info.value = info->value;
1077
1078         mutex_lock(&adev->grbm_idx_mutex);
1079         ret = psp_ras_trigger_error(&adev->psp, &block_info);
1080         mutex_unlock(&adev->grbm_idx_mutex);
1081
1082         return ret;
1083 }
1084
1085 static void gfx_v9_4_2_query_ea_err_status(struct amdgpu_device *adev)
1086 {
1087         uint32_t i, j;
1088         uint32_t reg_value;
1089
1090         mutex_lock(&adev->grbm_idx_mutex);
1091
1092         for (i = 0; i < gfx_v9_4_2_rdrsp_status_regs.se_num; i++) {
1093                 for (j = 0; j < gfx_v9_4_2_rdrsp_status_regs.instance;
1094                      j++) {
1095                         gfx_v9_4_2_select_se_sh(adev, i, 0, j);
1096                         reg_value = RREG32(SOC15_REG_ENTRY_OFFSET(
1097                                 gfx_v9_4_2_rdrsp_status_regs));
1098                         if (reg_value)
1099                                 dev_warn(adev->dev, "GCEA err detected at instance: %d, status: 0x%x!\n",
1100                                                 j, reg_value);
1101                         /* clear after read */
1102                         WREG32(SOC15_REG_ENTRY_OFFSET(gfx_v9_4_2_rdrsp_status_regs), 0x10);
1103                 }
1104         }
1105
1106         gfx_v9_4_2_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
1107         mutex_unlock(&adev->grbm_idx_mutex);
1108 }
1109
1110 static void gfx_v9_4_2_query_utc_err_status(struct amdgpu_device *adev)
1111 {
1112         uint32_t data;
1113
1114         data = RREG32_SOC15(GC, 0, regUTCL2_MEM_ECC_STATUS);
1115         if (!data) {
1116                 dev_warn(adev->dev, "GFX UTCL2 Mem Ecc Status: 0x%x!\n", data);
1117                 WREG32_SOC15(GC, 0, regUTCL2_MEM_ECC_STATUS, 0x3);
1118         }
1119
1120         data = RREG32_SOC15(GC, 0, regVML2_MEM_ECC_STATUS);
1121         if (!data) {
1122                 dev_warn(adev->dev, "GFX VML2 Mem Ecc Status: 0x%x!\n", data);
1123                 WREG32_SOC15(GC, 0, regVML2_MEM_ECC_STATUS, 0x3);
1124         }
1125
1126         data = RREG32_SOC15(GC, 0, regVML2_WALKER_MEM_ECC_STATUS);
1127         if (!data) {
1128                 dev_warn(adev->dev, "GFX VML2 Walker Mem Ecc Status: 0x%x!\n", data);
1129                 WREG32_SOC15(GC, 0, regVML2_WALKER_MEM_ECC_STATUS, 0x3);
1130         }
1131 }
1132
1133 void gfx_v9_4_2_query_ras_error_status(struct amdgpu_device *adev)
1134 {
1135         if (!amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__GFX))
1136                 return;
1137
1138         gfx_v9_4_2_query_ea_err_status(adev);
1139         gfx_v9_4_2_query_utc_err_status(adev);
1140         gfx_v9_4_2_query_sq_timeout_status(adev);
1141 }
1142
1143 void gfx_v9_4_2_reset_ras_error_status(struct amdgpu_device *adev)
1144 {
1145         if (!amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__GFX))
1146                 return;
1147
1148         gfx_v9_4_2_reset_utc_err_status(adev);
1149         gfx_v9_4_2_reset_ea_err_status(adev);
1150         gfx_v9_4_2_reset_sq_timeout_status(adev);
1151 }
1152
1153 void gfx_v9_4_2_enable_watchdog_timer(struct amdgpu_device *adev)
1154 {
1155         uint32_t i;
1156         uint32_t data;
1157
1158         data = REG_SET_FIELD(0, SQ_TIMEOUT_CONFIG, TIMEOUT_FATAL_DISABLE,
1159                              amdgpu_watchdog_timer.timeout_fatal_disable ? 1 :
1160                                                                            0);
1161
1162         if (amdgpu_watchdog_timer.timeout_fatal_disable &&
1163             (amdgpu_watchdog_timer.period < 1 ||
1164              amdgpu_watchdog_timer.period > 0x23)) {
1165                 dev_warn(adev->dev, "Watchdog period range is 1 to 0x23\n");
1166                 amdgpu_watchdog_timer.period = 0x23;
1167         }
1168         data = REG_SET_FIELD(data, SQ_TIMEOUT_CONFIG, PERIOD_SEL,
1169                              amdgpu_watchdog_timer.period);
1170
1171         mutex_lock(&adev->grbm_idx_mutex);
1172         for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {
1173                 gfx_v9_4_2_select_se_sh(adev, i, 0xffffffff, 0xffffffff);
1174                 WREG32_SOC15(GC, 0, regSQ_TIMEOUT_CONFIG, data);
1175         }
1176         gfx_v9_4_2_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
1177         mutex_unlock(&adev->grbm_idx_mutex);
1178 }
1179
1180 static uint32_t wave_read_ind(struct amdgpu_device *adev, uint32_t simd, uint32_t wave, uint32_t address)
1181 {
1182         WREG32_SOC15_RLC_EX(reg, GC, 0, regSQ_IND_INDEX,
1183                 (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) |
1184                 (simd << SQ_IND_INDEX__SIMD_ID__SHIFT) |
1185                 (address << SQ_IND_INDEX__INDEX__SHIFT) |
1186                 (SQ_IND_INDEX__FORCE_READ_MASK));
1187         return RREG32_SOC15(GC, 0, regSQ_IND_DATA);
1188 }
1189
1190 static void gfx_v9_4_2_log_cu_timeout_status(struct amdgpu_device *adev,
1191                                         uint32_t status)
1192 {
1193         struct amdgpu_cu_info *cu_info = &adev->gfx.cu_info;
1194         uint32_t i, simd, wave;
1195         uint32_t wave_status;
1196         uint32_t wave_pc_lo, wave_pc_hi;
1197         uint32_t wave_exec_lo, wave_exec_hi;
1198         uint32_t wave_inst_dw0, wave_inst_dw1;
1199         uint32_t wave_ib_sts;
1200
1201         for (i = 0; i < 32; i++) {
1202                 if (!((i << 1) & status))
1203                         continue;
1204
1205                 simd = i / cu_info->max_waves_per_simd;
1206                 wave = i % cu_info->max_waves_per_simd;
1207
1208                 wave_status = wave_read_ind(adev, simd, wave, ixSQ_WAVE_STATUS);
1209                 wave_pc_lo = wave_read_ind(adev, simd, wave, ixSQ_WAVE_PC_LO);
1210                 wave_pc_hi = wave_read_ind(adev, simd, wave, ixSQ_WAVE_PC_HI);
1211                 wave_exec_lo =
1212                         wave_read_ind(adev, simd, wave, ixSQ_WAVE_EXEC_LO);
1213                 wave_exec_hi =
1214                         wave_read_ind(adev, simd, wave, ixSQ_WAVE_EXEC_HI);
1215                 wave_inst_dw0 =
1216                         wave_read_ind(adev, simd, wave, ixSQ_WAVE_INST_DW0);
1217                 wave_inst_dw1 =
1218                         wave_read_ind(adev, simd, wave, ixSQ_WAVE_INST_DW1);
1219                 wave_ib_sts = wave_read_ind(adev, simd, wave, ixSQ_WAVE_IB_STS);
1220
1221                 dev_info(
1222                         adev->dev,
1223                         "\t SIMD %d, Wave %d: status 0x%x, pc 0x%llx, exec 0x%llx, inst 0x%llx, ib_sts 0x%x\n",
1224                         simd, wave, wave_status,
1225                         ((uint64_t)wave_pc_hi << 32 | wave_pc_lo),
1226                         ((uint64_t)wave_exec_hi << 32 | wave_exec_lo),
1227                         ((uint64_t)wave_inst_dw1 << 32 | wave_inst_dw0),
1228                         wave_ib_sts);
1229         }
1230 }
1231
1232 static void gfx_v9_4_2_query_sq_timeout_status(struct amdgpu_device *adev)
1233 {
1234         uint32_t se_idx, sh_idx, cu_idx;
1235         uint32_t status;
1236
1237         mutex_lock(&adev->grbm_idx_mutex);
1238         for (se_idx = 0; se_idx < adev->gfx.config.max_shader_engines;
1239              se_idx++) {
1240                 for (sh_idx = 0; sh_idx < adev->gfx.config.max_sh_per_se;
1241                      sh_idx++) {
1242                         for (cu_idx = 0;
1243                              cu_idx < adev->gfx.config.max_cu_per_sh;
1244                              cu_idx++) {
1245                                 gfx_v9_4_2_select_se_sh(adev, se_idx, sh_idx,
1246                                                         cu_idx);
1247                                 status = RREG32_SOC15(GC, 0,
1248                                                       regSQ_TIMEOUT_STATUS);
1249                                 if (status != 0) {
1250                                         dev_info(
1251                                                 adev->dev,
1252                                                 "GFX Watchdog Timeout: SE %d, SH %d, CU %d\n",
1253                                                 se_idx, sh_idx, cu_idx);
1254                                         gfx_v9_4_2_log_cu_timeout_status(
1255                                                 adev, status);
1256                                 }
1257                                 /* clear old status */
1258                                 WREG32_SOC15(GC, 0, regSQ_TIMEOUT_STATUS, 0);
1259                         }
1260                 }
1261         }
1262         gfx_v9_4_2_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
1263         mutex_unlock(&adev->grbm_idx_mutex);
1264 }
1265
1266 static void gfx_v9_4_2_reset_sq_timeout_status(struct amdgpu_device *adev)
1267 {
1268         uint32_t se_idx, sh_idx, cu_idx;
1269
1270         mutex_lock(&adev->grbm_idx_mutex);
1271         for (se_idx = 0; se_idx < adev->gfx.config.max_shader_engines;
1272              se_idx++) {
1273                 for (sh_idx = 0; sh_idx < adev->gfx.config.max_sh_per_se;
1274                      sh_idx++) {
1275                         for (cu_idx = 0;
1276                              cu_idx < adev->gfx.config.max_cu_per_sh;
1277                              cu_idx++) {
1278                                 gfx_v9_4_2_select_se_sh(adev, se_idx, sh_idx,
1279                                                         cu_idx);
1280                                 WREG32_SOC15(GC, 0, regSQ_TIMEOUT_STATUS, 0);
1281                         }
1282                 }
1283         }
1284         gfx_v9_4_2_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
1285         mutex_unlock(&adev->grbm_idx_mutex);
1286 }