drivers/gpu/drm/amd/amdgpu/amdgpu_jpeg.c

   1 /*
   2  * Copyright 2019 Advanced Micro Devices, Inc.
   3  * All Rights Reserved.
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the
   7  * "Software"), to deal in the Software without restriction, including
   8  * without limitation the rights to use, copy, modify, merge, publish,
   9  * distribute, sub license, and/or sell copies of the Software, and to
  10  * permit persons to whom the Software is furnished to do so, subject to
  11  * the following conditions:
  12  *
  13  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  14  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  15  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  16  * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
  17  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  18  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  19  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  20  *
  21  * The above copyright notice and this permission notice (including the
  22  * next paragraph) shall be included in all copies or substantial portions
  23  * of the Software.
  24  *
  25  */
  26
  27 #include "amdgpu.h"
  28 #include "amdgpu_jpeg.h"
  29 #include "amdgpu_pm.h"
  30 #include "soc15d.h"
  31 #include "soc15_common.h"
  32
  33 #define JPEG_IDLE_TIMEOUT       msecs_to_jiffies(1000)
  34
  35 static void amdgpu_jpeg_idle_work_handler(struct work_struct *work);
  36
  37 int amdgpu_jpeg_sw_init(struct amdgpu_device *adev)
  38 {
  39         INIT_DELAYED_WORK(&adev->jpeg.idle_work, amdgpu_jpeg_idle_work_handler);
  40         mutex_init(&adev->jpeg.jpeg_pg_lock);
  41         atomic_set(&adev->jpeg.total_submission_cnt, 0);
  42
  43         return 0;
  44 }
  45
  46 int amdgpu_jpeg_sw_fini(struct amdgpu_device *adev)
  47 {
  48         int i, j;
  49
  50         for (i = 0; i < adev->jpeg.num_jpeg_inst; ++i) {
  51                 if (adev->jpeg.harvest_config & (1 << i))
  52                         continue;
  53
  54                 for (j = 0; j < adev->jpeg.num_jpeg_rings; ++j)
  55                         amdgpu_ring_fini(&adev->jpeg.inst[i].ring_dec[j]);
  56         }
  57
  58         mutex_destroy(&adev->jpeg.jpeg_pg_lock);
  59
  60         return 0;
  61 }
  62
  63 int amdgpu_jpeg_suspend(struct amdgpu_device *adev)
  64 {
  65         cancel_delayed_work_sync(&adev->jpeg.idle_work);
  66
  67         return 0;
  68 }
  69
  70 int amdgpu_jpeg_resume(struct amdgpu_device *adev)
  71 {
  72         return 0;
  73 }
  74
  75 static void amdgpu_jpeg_idle_work_handler(struct work_struct *work)
  76 {
  77         struct amdgpu_device *adev =
  78                 container_of(work, struct amdgpu_device, jpeg.idle_work.work);
  79         unsigned int fences = 0;
  80         unsigned int i, j;
  81
  82         for (i = 0; i < adev->jpeg.num_jpeg_inst; ++i) {
  83                 if (adev->jpeg.harvest_config & (1 << i))
  84                         continue;
  85
  86                 for (j = 0; j < adev->jpeg.num_jpeg_rings; ++j)
  87                         fences += amdgpu_fence_count_emitted(&adev->jpeg.inst[i].ring_dec[j]);
  88         }
  89
  90         if (!fences && !atomic_read(&adev->jpeg.total_submission_cnt))
  91                 amdgpu_device_ip_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_JPEG,
  92                                                        AMD_PG_STATE_GATE);
  93         else
  94                 schedule_delayed_work(&adev->jpeg.idle_work, JPEG_IDLE_TIMEOUT);
  95 }
  96
  97 void amdgpu_jpeg_ring_begin_use(struct amdgpu_ring *ring)
  98 {
  99         struct amdgpu_device *adev = ring->adev;
 100
 101         atomic_inc(&adev->jpeg.total_submission_cnt);
 102         cancel_delayed_work_sync(&adev->jpeg.idle_work);
 103
 104         mutex_lock(&adev->jpeg.jpeg_pg_lock);
 105         amdgpu_device_ip_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_JPEG,
 106                                                        AMD_PG_STATE_UNGATE);
 107         mutex_unlock(&adev->jpeg.jpeg_pg_lock);
 108 }
 109
 110 void amdgpu_jpeg_ring_end_use(struct amdgpu_ring *ring)
 111 {
 112         atomic_dec(&ring->adev->jpeg.total_submission_cnt);
 113         schedule_delayed_work(&ring->adev->jpeg.idle_work, JPEG_IDLE_TIMEOUT);
 114 }
 115
 116 int amdgpu_jpeg_dec_ring_test_ring(struct amdgpu_ring *ring)
 117 {
 118         struct amdgpu_device *adev = ring->adev;
 119         uint32_t tmp = 0;
 120         unsigned i;
 121         int r;
 122
 123         /* JPEG in SRIOV does not support direct register read/write */
 124         if (amdgpu_sriov_vf(adev))
 125                 return 0;
 126
 127         WREG32(adev->jpeg.inst[ring->me].external.jpeg_pitch[ring->pipe], 0xCAFEDEAD);
 128         r = amdgpu_ring_alloc(ring, 3);
 129         if (r)
 130                 return r;
 131
 132         amdgpu_ring_write(ring, PACKET0(adev->jpeg.internal.jpeg_pitch[ring->pipe], 0));
 133         amdgpu_ring_write(ring, 0xDEADBEEF);
 134         amdgpu_ring_commit(ring);
 135
 136         for (i = 0; i < adev->usec_timeout; i++) {
 137                 tmp = RREG32(adev->jpeg.inst[ring->me].external.jpeg_pitch[ring->pipe]);
 138                 if (tmp == 0xDEADBEEF)
 139                         break;
 140                 udelay(1);
 141         }
 142
 143         if (i >= adev->usec_timeout)
 144                 r = -ETIMEDOUT;
 145
 146         return r;
 147 }
 148
 149 static int amdgpu_jpeg_dec_set_reg(struct amdgpu_ring *ring, uint32_t handle,
 150                 struct dma_fence **fence)
 151 {
 152         struct amdgpu_device *adev = ring->adev;
 153         struct amdgpu_job *job;
 154         struct amdgpu_ib *ib;
 155         struct dma_fence *f = NULL;
 156         const unsigned ib_size_dw = 16;
 157         int i, r;
 158
 159         r = amdgpu_job_alloc_with_ib(ring->adev, NULL, NULL, ib_size_dw * 4,
 160                                      AMDGPU_IB_POOL_DIRECT, &job);
 161         if (r)
 162                 return r;
 163
 164         ib = &job->ibs[0];
 165
 166         ib->ptr[0] = PACKETJ(adev->jpeg.internal.jpeg_pitch[ring->pipe], 0, 0, PACKETJ_TYPE0);
 167         ib->ptr[1] = 0xDEADBEEF;
 168         for (i = 2; i < 16; i += 2) {
 169                 ib->ptr[i] = PACKETJ(0, 0, 0, PACKETJ_TYPE6);
 170                 ib->ptr[i+1] = 0;
 171         }
 172         ib->length_dw = 16;
 173
 174         r = amdgpu_job_submit_direct(job, ring, &f);
 175         if (r)
 176                 goto err;
 177
 178         if (fence)
 179                 *fence = dma_fence_get(f);
 180         dma_fence_put(f);
 181
 182         return 0;
 183
 184 err:
 185         amdgpu_job_free(job);
 186         return r;
 187 }
 188
 189 int amdgpu_jpeg_dec_ring_test_ib(struct amdgpu_ring *ring, long timeout)
 190 {
 191         struct amdgpu_device *adev = ring->adev;
 192         uint32_t tmp = 0;
 193         unsigned i;
 194         struct dma_fence *fence = NULL;
 195         long r = 0;
 196
 197         r = amdgpu_jpeg_dec_set_reg(ring, 1, &fence);
 198         if (r)
 199                 goto error;
 200
 201         r = dma_fence_wait_timeout(fence, false, timeout);
 202         if (r == 0) {
 203                 r = -ETIMEDOUT;
 204                 goto error;
 205         } else if (r < 0) {
 206                 goto error;
 207         } else {
 208                 r = 0;
 209         }
 210         if (!amdgpu_sriov_vf(adev)) {
 211                 for (i = 0; i < adev->usec_timeout; i++) {
 212                         tmp = RREG32(adev->jpeg.inst[ring->me].external.jpeg_pitch[ring->pipe]);
 213                         if (tmp == 0xDEADBEEF)
 214                                 break;
 215                         udelay(1);
 216                 }
 217
 218                 if (i >= adev->usec_timeout)
 219                         r = -ETIMEDOUT;
 220         }
 221
 222         dma_fence_put(fence);
 223 error:
 224         return r;
 225 }
 226
 227 int amdgpu_jpeg_process_poison_irq(struct amdgpu_device *adev,
 228                                 struct amdgpu_irq_src *source,
 229                                 struct amdgpu_iv_entry *entry)
 230 {
 231         struct ras_common_if *ras_if = adev->jpeg.ras_if;
 232         struct ras_dispatch_if ih_data = {
 233                 .entry = entry,
 234         };
 235
 236         if (!ras_if)
 237                 return 0;
 238
 239         ih_data.head = *ras_if;
 240         amdgpu_ras_interrupt_dispatch(adev, &ih_data);
 241
 242         return 0;
 243 }
 244
 245 int amdgpu_jpeg_ras_sw_init(struct amdgpu_device *adev)
 246 {
 247         int err;
 248         struct amdgpu_jpeg_ras *ras;
 249
 250         if (!adev->jpeg.ras)
 251                 return 0;
 252
 253         ras = adev->jpeg.ras;
 254         err = amdgpu_ras_register_ras_block(adev, &ras->ras_block);
 255         if (err) {
 256                 dev_err(adev->dev, "Failed to register jpeg ras block!\n");
 257                 return err;
 258         }
 259
 260         strcpy(ras->ras_block.ras_comm.name, "jpeg");
 261         ras->ras_block.ras_comm.block = AMDGPU_RAS_BLOCK__JPEG;
 262         ras->ras_block.ras_comm.type = AMDGPU_RAS_ERROR__POISON;
 263         adev->jpeg.ras_if = &ras->ras_block.ras_comm;
 264
 265         if (!ras->ras_block.ras_late_init)
 266                 ras->ras_block.ras_late_init = amdgpu_ras_block_late_init;
 267
 268         return 0;
 269 }