drivers/gpu/drm/omapdrm/omap_drv.c

   1 /*
   2  * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
   3  * Author: Rob Clark <[email protected]>
   4  *
   5  * This program is free software; you can redistribute it and/or modify it
   6  * under the terms of the GNU General Public License version 2 as published by
   7  * the Free Software Foundation.
   8  *
   9  * This program is distributed in the hope that it will be useful, but WITHOUT
  10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  12  * more details.
  13  *
  14  * You should have received a copy of the GNU General Public License along with
  15  * this program.  If not, see <http://www.gnu.org/licenses/>.
  16  */
  17
  18 #include <linux/of.h>
  19 #include <linux/sort.h>
  20 #include <linux/sys_soc.h>
  21
  22 #include <drm/drm_atomic.h>
  23 #include <drm/drm_atomic_helper.h>
  24 #include <drm/drm_fb_helper.h>
  25 #include <drm/drm_probe_helper.h>
  26 #include <drm/drm_panel.h>
  27
  28 #include "omap_dmm_tiler.h"
  29 #include "omap_drv.h"
  30
  31 #define DRIVER_NAME             MODULE_NAME
  32 #define DRIVER_DESC             "OMAP DRM"
  33 #define DRIVER_DATE             "20110917"
  34 #define DRIVER_MAJOR            1
  35 #define DRIVER_MINOR            0
  36 #define DRIVER_PATCHLEVEL       0
  37
  38 /*
  39  * mode config funcs
  40  */
  41
  42 /* Notes about mapping DSS and DRM entities:
  43  *    CRTC:        overlay
  44  *    encoder:     manager.. with some extension to allow one primary CRTC
  45  *                 and zero or more video CRTC's to be mapped to one encoder?
  46  *    connector:   dssdev.. manager can be attached/detached from different
  47  *                 devices
  48  */
  49
  50 static void omap_atomic_wait_for_completion(struct drm_device *dev,
  51                                             struct drm_atomic_state *old_state)
  52 {
  53         struct drm_crtc_state *new_crtc_state;
  54         struct drm_crtc *crtc;
  55         unsigned int i;
  56         int ret;
  57
  58         for_each_new_crtc_in_state(old_state, crtc, new_crtc_state, i) {
  59                 if (!new_crtc_state->active)
  60                         continue;
  61
  62                 ret = omap_crtc_wait_pending(crtc);
  63
  64                 if (!ret)
  65                         dev_warn(dev->dev,
  66                                  "atomic complete timeout (pipe %u)!\n", i);
  67         }
  68 }
  69
  70 static void omap_atomic_commit_tail(struct drm_atomic_state *old_state)
  71 {
  72         struct drm_device *dev = old_state->dev;
  73         struct omap_drm_private *priv = dev->dev_private;
  74
  75         priv->dispc_ops->runtime_get(priv->dispc);
  76
  77         /* Apply the atomic update. */
  78         drm_atomic_helper_commit_modeset_disables(dev, old_state);
  79
  80         if (priv->omaprev != 0x3430) {
  81                 /* With the current dss dispc implementation we have to enable
  82                  * the new modeset before we can commit planes. The dispc ovl
  83                  * configuration relies on the video mode configuration been
  84                  * written into the HW when the ovl configuration is
  85                  * calculated.
  86                  *
  87                  * This approach is not ideal because after a mode change the
  88                  * plane update is executed only after the first vblank
  89                  * interrupt. The dispc implementation should be fixed so that
  90                  * it is able use uncommitted drm state information.
  91                  */
  92                 drm_atomic_helper_commit_modeset_enables(dev, old_state);
  93                 omap_atomic_wait_for_completion(dev, old_state);
  94
  95                 drm_atomic_helper_commit_planes(dev, old_state, 0);
  96
  97                 drm_atomic_helper_commit_hw_done(old_state);
  98         } else {
  99                 /*
 100                  * OMAP3 DSS seems to have issues with the work-around above,
 101                  * resulting in endless sync losts if a crtc is enabled without
 102                  * a plane. For now, skip the WA for OMAP3.
 103                  */
 104                 drm_atomic_helper_commit_planes(dev, old_state, 0);
 105
 106                 drm_atomic_helper_commit_modeset_enables(dev, old_state);
 107
 108                 drm_atomic_helper_commit_hw_done(old_state);
 109         }
 110
 111         /*
 112          * Wait for completion of the page flips to ensure that old buffers
 113          * can't be touched by the hardware anymore before cleaning up planes.
 114          */
 115         omap_atomic_wait_for_completion(dev, old_state);
 116
 117         drm_atomic_helper_cleanup_planes(dev, old_state);
 118
 119         priv->dispc_ops->runtime_put(priv->dispc);
 120 }
 121
 122 static const struct drm_mode_config_helper_funcs omap_mode_config_helper_funcs = {
 123         .atomic_commit_tail = omap_atomic_commit_tail,
 124 };
 125
 126 static const struct drm_mode_config_funcs omap_mode_config_funcs = {
 127         .fb_create = omap_framebuffer_create,
 128         .output_poll_changed = drm_fb_helper_output_poll_changed,
 129         .atomic_check = drm_atomic_helper_check,
 130         .atomic_commit = drm_atomic_helper_commit,
 131 };
 132
 133 static void omap_disconnect_pipelines(struct drm_device *ddev)
 134 {
 135         struct omap_drm_private *priv = ddev->dev_private;
 136         unsigned int i;
 137
 138         for (i = 0; i < priv->num_pipes; i++) {
 139                 struct omap_drm_pipeline *pipe = &priv->pipes[i];
 140
 141                 if (pipe->output->panel)
 142                         drm_panel_detach(pipe->output->panel);
 143
 144                 omapdss_device_disconnect(NULL, pipe->output);
 145
 146                 omapdss_device_put(pipe->output);
 147                 pipe->output = NULL;
 148         }
 149
 150         memset(&priv->channels, 0, sizeof(priv->channels));
 151
 152         priv->num_pipes = 0;
 153 }
 154
 155 static int omap_connect_pipelines(struct drm_device *ddev)
 156 {
 157         struct omap_drm_private *priv = ddev->dev_private;
 158         struct omap_dss_device *output = NULL;
 159         int r;
 160
 161         for_each_dss_output(output) {
 162                 r = omapdss_device_connect(priv->dss, NULL, output);
 163                 if (r == -EPROBE_DEFER) {
 164                         omapdss_device_put(output);
 165                         return r;
 166                 } else if (r) {
 167                         dev_warn(output->dev, "could not connect output %s\n",
 168                                  output->name);
 169                 } else {
 170                         struct omap_drm_pipeline *pipe;
 171
 172                         pipe = &priv->pipes[priv->num_pipes++];
 173                         pipe->output = omapdss_device_get(output);
 174
 175                         if (priv->num_pipes == ARRAY_SIZE(priv->pipes)) {
 176                                 /* To balance the 'for_each_dss_output' loop */
 177                                 omapdss_device_put(output);
 178                                 break;
 179                         }
 180                 }
 181         }
 182
 183         return 0;
 184 }
 185
 186 static int omap_compare_pipelines(const void *a, const void *b)
 187 {
 188         const struct omap_drm_pipeline *pipe1 = a;
 189         const struct omap_drm_pipeline *pipe2 = b;
 190
 191         if (pipe1->alias_id > pipe2->alias_id)
 192                 return 1;
 193         else if (pipe1->alias_id < pipe2->alias_id)
 194                 return -1;
 195         return 0;
 196 }
 197
 198 static int omap_modeset_init_properties(struct drm_device *dev)
 199 {
 200         struct omap_drm_private *priv = dev->dev_private;
 201         unsigned int num_planes = priv->dispc_ops->get_num_ovls(priv->dispc);
 202
 203         priv->zorder_prop = drm_property_create_range(dev, 0, "zorder", 0,
 204                                                       num_planes - 1);
 205         if (!priv->zorder_prop)
 206                 return -ENOMEM;
 207
 208         return 0;
 209 }
 210
 211 static int omap_display_id(struct omap_dss_device *output)
 212 {
 213         struct device_node *node = NULL;
 214
 215         if (output->next) {
 216                 struct omap_dss_device *display;
 217
 218                 display = omapdss_display_get(output);
 219                 node = display->dev->of_node;
 220                 omapdss_device_put(display);
 221         } else if (output->bridge) {
 222                 struct drm_bridge *bridge = output->bridge;
 223
 224                 while (bridge->next)
 225                         bridge = bridge->next;
 226
 227                 node = bridge->of_node;
 228         } else if (output->panel) {
 229                 node = output->panel->dev->of_node;
 230         }
 231
 232         return node ? of_alias_get_id(node, "display") : -ENODEV;
 233 }
 234
 235 static int omap_modeset_init(struct drm_device *dev)
 236 {
 237         struct omap_drm_private *priv = dev->dev_private;
 238         int num_ovls = priv->dispc_ops->get_num_ovls(priv->dispc);
 239         int num_mgrs = priv->dispc_ops->get_num_mgrs(priv->dispc);
 240         unsigned int i;
 241         int ret;
 242         u32 plane_crtc_mask;
 243
 244         if (!omapdss_stack_is_ready())
 245                 return -EPROBE_DEFER;
 246
 247         drm_mode_config_init(dev);
 248
 249         ret = omap_modeset_init_properties(dev);
 250         if (ret < 0)
 251                 return ret;
 252
 253         /*
 254          * This function creates exactly one connector, encoder, crtc,
 255          * and primary plane per each connected dss-device. Each
 256          * connector->encoder->crtc chain is expected to be separate
 257          * and each crtc is connect to a single dss-channel. If the
 258          * configuration does not match the expectations or exceeds
 259          * the available resources, the configuration is rejected.
 260          */
 261         ret = omap_connect_pipelines(dev);
 262         if (ret < 0)
 263                 return ret;
 264
 265         if (priv->num_pipes > num_mgrs || priv->num_pipes > num_ovls) {
 266                 dev_err(dev->dev, "%s(): Too many connected displays\n",
 267                         __func__);
 268                 return -EINVAL;
 269         }
 270
 271         /* Create all planes first. They can all be put to any CRTC. */
 272         plane_crtc_mask = (1 << priv->num_pipes) - 1;
 273
 274         for (i = 0; i < num_ovls; i++) {
 275                 enum drm_plane_type type = i < priv->num_pipes
 276                                          ? DRM_PLANE_TYPE_PRIMARY
 277                                          : DRM_PLANE_TYPE_OVERLAY;
 278                 struct drm_plane *plane;
 279
 280                 if (WARN_ON(priv->num_planes >= ARRAY_SIZE(priv->planes)))
 281                         return -EINVAL;
 282
 283                 plane = omap_plane_init(dev, i, type, plane_crtc_mask);
 284                 if (IS_ERR(plane))
 285                         return PTR_ERR(plane);
 286
 287                 priv->planes[priv->num_planes++] = plane;
 288         }
 289
 290         /*
 291          * Create the encoders, attach the bridges and get the pipeline alias
 292          * IDs.
 293          */
 294         for (i = 0; i < priv->num_pipes; i++) {
 295                 struct omap_drm_pipeline *pipe = &priv->pipes[i];
 296                 int id;
 297
 298                 pipe->encoder = omap_encoder_init(dev, pipe->output);
 299                 if (!pipe->encoder)
 300                         return -ENOMEM;
 301
 302                 if (pipe->output->bridge) {
 303                         ret = drm_bridge_attach(pipe->encoder,
 304                                                 pipe->output->bridge, NULL);
 305                         if (ret < 0)
 306                                 return ret;
 307                 }
 308
 309                 id = omap_display_id(pipe->output);
 310                 pipe->alias_id = id >= 0 ? id : i;
 311         }
 312
 313         /* Sort the pipelines by DT aliases. */
 314         sort(priv->pipes, priv->num_pipes, sizeof(priv->pipes[0]),
 315              omap_compare_pipelines, NULL);
 316
 317         /*
 318          * Populate the pipeline lookup table by DISPC channel. Only one display
 319          * is allowed per channel.
 320          */
 321         for (i = 0; i < priv->num_pipes; ++i) {
 322                 struct omap_drm_pipeline *pipe = &priv->pipes[i];
 323                 enum omap_channel channel = pipe->output->dispc_channel;
 324
 325                 if (WARN_ON(priv->channels[channel] != NULL))
 326                         return -EINVAL;
 327
 328                 priv->channels[channel] = pipe;
 329         }
 330
 331         /* Create the connectors and CRTCs. */
 332         for (i = 0; i < priv->num_pipes; i++) {
 333                 struct omap_drm_pipeline *pipe = &priv->pipes[i];
 334                 struct drm_encoder *encoder = pipe->encoder;
 335                 struct drm_crtc *crtc;
 336
 337                 if (!pipe->output->bridge) {
 338                         pipe->connector = omap_connector_init(dev, pipe->output,
 339                                                               encoder);
 340                         if (!pipe->connector)
 341                                 return -ENOMEM;
 342
 343                         drm_connector_attach_encoder(pipe->connector, encoder);
 344
 345                         if (pipe->output->panel) {
 346                                 ret = drm_panel_attach(pipe->output->panel,
 347                                                        pipe->connector);
 348                                 if (ret < 0)
 349                                         return ret;
 350                         }
 351                 }
 352
 353                 crtc = omap_crtc_init(dev, pipe, priv->planes[i]);
 354                 if (IS_ERR(crtc))
 355                         return PTR_ERR(crtc);
 356
 357                 encoder->possible_crtcs = 1 << i;
 358                 pipe->crtc = crtc;
 359         }
 360
 361         DBG("registered %u planes, %u crtcs/encoders/connectors\n",
 362             priv->num_planes, priv->num_pipes);
 363
 364         dev->mode_config.min_width = 8;
 365         dev->mode_config.min_height = 2;
 366
 367         /*
 368          * Note: these values are used for multiple independent things:
 369          * connector mode filtering, buffer sizes, crtc sizes...
 370          * Use big enough values here to cover all use cases, and do more
 371          * specific checking in the respective code paths.
 372          */
 373         dev->mode_config.max_width = 8192;
 374         dev->mode_config.max_height = 8192;
 375
 376         /* We want the zpos to be normalized */
 377         dev->mode_config.normalize_zpos = true;
 378
 379         dev->mode_config.funcs = &omap_mode_config_funcs;
 380         dev->mode_config.helper_private = &omap_mode_config_helper_funcs;
 381
 382         drm_mode_config_reset(dev);
 383
 384         omap_drm_irq_install(dev);
 385
 386         return 0;
 387 }
 388
 389 /*
 390  * Enable the HPD in external components if supported
 391  */
 392 static void omap_modeset_enable_external_hpd(struct drm_device *ddev)
 393 {
 394         struct omap_drm_private *priv = ddev->dev_private;
 395         unsigned int i;
 396
 397         for (i = 0; i < priv->num_pipes; i++) {
 398                 if (priv->pipes[i].connector)
 399                         omap_connector_enable_hpd(priv->pipes[i].connector);
 400         }
 401 }
 402
 403 /*
 404  * Disable the HPD in external components if supported
 405  */
 406 static void omap_modeset_disable_external_hpd(struct drm_device *ddev)
 407 {
 408         struct omap_drm_private *priv = ddev->dev_private;
 409         unsigned int i;
 410
 411         for (i = 0; i < priv->num_pipes; i++) {
 412                 if (priv->pipes[i].connector)
 413                         omap_connector_disable_hpd(priv->pipes[i].connector);
 414         }
 415 }
 416
 417 /*
 418  * drm ioctl funcs
 419  */
 420
 421
 422 static int ioctl_get_param(struct drm_device *dev, void *data,
 423                 struct drm_file *file_priv)
 424 {
 425         struct omap_drm_private *priv = dev->dev_private;
 426         struct drm_omap_param *args = data;
 427
 428         DBG("%p: param=%llu", dev, args->param);
 429
 430         switch (args->param) {
 431         case OMAP_PARAM_CHIPSET_ID:
 432                 args->value = priv->omaprev;
 433                 break;
 434         default:
 435                 DBG("unknown parameter %lld", args->param);
 436                 return -EINVAL;
 437         }
 438
 439         return 0;
 440 }
 441
 442 static int ioctl_set_param(struct drm_device *dev, void *data,
 443                 struct drm_file *file_priv)
 444 {
 445         struct drm_omap_param *args = data;
 446
 447         switch (args->param) {
 448         default:
 449                 DBG("unknown parameter %lld", args->param);
 450                 return -EINVAL;
 451         }
 452
 453         return 0;
 454 }
 455
 456 #define OMAP_BO_USER_MASK       0x00ffffff      /* flags settable by userspace */
 457
 458 static int ioctl_gem_new(struct drm_device *dev, void *data,
 459                 struct drm_file *file_priv)
 460 {
 461         struct drm_omap_gem_new *args = data;
 462         u32 flags = args->flags & OMAP_BO_USER_MASK;
 463
 464         VERB("%p:%p: size=0x%08x, flags=%08x", dev, file_priv,
 465              args->size.bytes, flags);
 466
 467         return omap_gem_new_handle(dev, file_priv, args->size, flags,
 468                                    &args->handle);
 469 }
 470
 471 static int ioctl_gem_info(struct drm_device *dev, void *data,
 472                 struct drm_file *file_priv)
 473 {
 474         struct drm_omap_gem_info *args = data;
 475         struct drm_gem_object *obj;
 476         int ret = 0;
 477
 478         VERB("%p:%p: handle=%d", dev, file_priv, args->handle);
 479
 480         obj = drm_gem_object_lookup(file_priv, args->handle);
 481         if (!obj)
 482                 return -ENOENT;
 483
 484         args->size = omap_gem_mmap_size(obj);
 485         args->offset = omap_gem_mmap_offset(obj);
 486
 487         drm_gem_object_put_unlocked(obj);
 488
 489         return ret;
 490 }
 491
 492 static const struct drm_ioctl_desc ioctls[DRM_COMMAND_END - DRM_COMMAND_BASE] = {
 493         DRM_IOCTL_DEF_DRV(OMAP_GET_PARAM, ioctl_get_param,
 494                           DRM_AUTH | DRM_RENDER_ALLOW),
 495         DRM_IOCTL_DEF_DRV(OMAP_SET_PARAM, ioctl_set_param,
 496                           DRM_AUTH | DRM_MASTER | DRM_ROOT_ONLY),
 497         DRM_IOCTL_DEF_DRV(OMAP_GEM_NEW, ioctl_gem_new,
 498                           DRM_AUTH | DRM_RENDER_ALLOW),
 499         /* Deprecated, to be removed. */
 500         DRM_IOCTL_DEF_DRV(OMAP_GEM_CPU_PREP, drm_noop,
 501                           DRM_AUTH | DRM_RENDER_ALLOW),
 502         /* Deprecated, to be removed. */
 503         DRM_IOCTL_DEF_DRV(OMAP_GEM_CPU_FINI, drm_noop,
 504                           DRM_AUTH | DRM_RENDER_ALLOW),
 505         DRM_IOCTL_DEF_DRV(OMAP_GEM_INFO, ioctl_gem_info,
 506                           DRM_AUTH | DRM_RENDER_ALLOW),
 507 };
 508
 509 /*
 510  * drm driver funcs
 511  */
 512
 513 static int dev_open(struct drm_device *dev, struct drm_file *file)
 514 {
 515         file->driver_priv = NULL;
 516
 517         DBG("open: dev=%p, file=%p", dev, file);
 518
 519         return 0;
 520 }
 521
 522 static const struct vm_operations_struct omap_gem_vm_ops = {
 523         .fault = omap_gem_fault,
 524         .open = drm_gem_vm_open,
 525         .close = drm_gem_vm_close,
 526 };
 527
 528 static const struct file_operations omapdriver_fops = {
 529         .owner = THIS_MODULE,
 530         .open = drm_open,
 531         .unlocked_ioctl = drm_ioctl,
 532         .compat_ioctl = drm_compat_ioctl,
 533         .release = drm_release,
 534         .mmap = omap_gem_mmap,
 535         .poll = drm_poll,
 536         .read = drm_read,
 537         .llseek = noop_llseek,
 538 };
 539
 540 static struct drm_driver omap_drm_driver = {
 541         .driver_features = DRIVER_MODESET | DRIVER_GEM  | DRIVER_PRIME |
 542                 DRIVER_ATOMIC | DRIVER_RENDER,
 543         .open = dev_open,
 544         .lastclose = drm_fb_helper_lastclose,
 545 #ifdef CONFIG_DEBUG_FS
 546         .debugfs_init = omap_debugfs_init,
 547 #endif
 548         .prime_handle_to_fd = drm_gem_prime_handle_to_fd,
 549         .prime_fd_to_handle = drm_gem_prime_fd_to_handle,
 550         .gem_prime_export = omap_gem_prime_export,
 551         .gem_prime_import = omap_gem_prime_import,
 552         .gem_free_object_unlocked = omap_gem_free_object,
 553         .gem_vm_ops = &omap_gem_vm_ops,
 554         .dumb_create = omap_gem_dumb_create,
 555         .dumb_map_offset = omap_gem_dumb_map_offset,
 556         .ioctls = ioctls,
 557         .num_ioctls = DRM_OMAP_NUM_IOCTLS,
 558         .fops = &omapdriver_fops,
 559         .name = DRIVER_NAME,
 560         .desc = DRIVER_DESC,
 561         .date = DRIVER_DATE,
 562         .major = DRIVER_MAJOR,
 563         .minor = DRIVER_MINOR,
 564         .patchlevel = DRIVER_PATCHLEVEL,
 565 };
 566
 567 static const struct soc_device_attribute omapdrm_soc_devices[] = {
 568         { .family = "OMAP3", .data = (void *)0x3430 },
 569         { .family = "OMAP4", .data = (void *)0x4430 },
 570         { .family = "OMAP5", .data = (void *)0x5430 },
 571         { .family = "DRA7",  .data = (void *)0x0752 },
 572         { /* sentinel */ }
 573 };
 574
 575 static int omapdrm_init(struct omap_drm_private *priv, struct device *dev)
 576 {
 577         const struct soc_device_attribute *soc;
 578         struct drm_device *ddev;
 579         unsigned int i;
 580         int ret;
 581
 582         DBG("%s", dev_name(dev));
 583
 584         /* Allocate and initialize the DRM device. */
 585         ddev = drm_dev_alloc(&omap_drm_driver, dev);
 586         if (IS_ERR(ddev))
 587                 return PTR_ERR(ddev);
 588
 589         priv->ddev = ddev;
 590         ddev->dev_private = priv;
 591
 592         priv->dev = dev;
 593         priv->dss = omapdss_get_dss();
 594         priv->dispc = dispc_get_dispc(priv->dss);
 595         priv->dispc_ops = dispc_get_ops(priv->dss);
 596
 597         omap_crtc_pre_init(priv);
 598
 599         soc = soc_device_match(omapdrm_soc_devices);
 600         priv->omaprev = soc ? (unsigned int)soc->data : 0;
 601         priv->wq = alloc_ordered_workqueue("omapdrm", 0);
 602
 603         mutex_init(&priv->list_lock);
 604         INIT_LIST_HEAD(&priv->obj_list);
 605
 606         /* Get memory bandwidth limits */
 607         if (priv->dispc_ops->get_memory_bandwidth_limit)
 608                 priv->max_bandwidth =
 609                         priv->dispc_ops->get_memory_bandwidth_limit(priv->dispc);
 610
 611         omap_gem_init(ddev);
 612
 613         ret = omap_modeset_init(ddev);
 614         if (ret) {
 615                 dev_err(priv->dev, "omap_modeset_init failed: ret=%d\n", ret);
 616                 goto err_gem_deinit;
 617         }
 618
 619         /* Initialize vblank handling, start with all CRTCs disabled. */
 620         ret = drm_vblank_init(ddev, priv->num_pipes);
 621         if (ret) {
 622                 dev_err(priv->dev, "could not init vblank\n");
 623                 goto err_cleanup_modeset;
 624         }
 625
 626         for (i = 0; i < priv->num_pipes; i++)
 627                 drm_crtc_vblank_off(priv->pipes[i].crtc);
 628
 629         omap_fbdev_init(ddev);
 630
 631         drm_kms_helper_poll_init(ddev);
 632         omap_modeset_enable_external_hpd(ddev);
 633
 634         /*
 635          * Register the DRM device with the core and the connectors with
 636          * sysfs.
 637          */
 638         ret = drm_dev_register(ddev, 0);
 639         if (ret)
 640                 goto err_cleanup_helpers;
 641
 642         return 0;
 643
 644 err_cleanup_helpers:
 645         omap_modeset_disable_external_hpd(ddev);
 646         drm_kms_helper_poll_fini(ddev);
 647
 648         omap_fbdev_fini(ddev);
 649 err_cleanup_modeset:
 650         drm_mode_config_cleanup(ddev);
 651         omap_drm_irq_uninstall(ddev);
 652 err_gem_deinit:
 653         omap_gem_deinit(ddev);
 654         destroy_workqueue(priv->wq);
 655         omap_disconnect_pipelines(ddev);
 656         omap_crtc_pre_uninit(priv);
 657         drm_dev_put(ddev);
 658         return ret;
 659 }
 660
 661 static void omapdrm_cleanup(struct omap_drm_private *priv)
 662 {
 663         struct drm_device *ddev = priv->ddev;
 664
 665         DBG("");
 666
 667         drm_dev_unregister(ddev);
 668
 669         omap_modeset_disable_external_hpd(ddev);
 670         drm_kms_helper_poll_fini(ddev);
 671
 672         omap_fbdev_fini(ddev);
 673
 674         drm_atomic_helper_shutdown(ddev);
 675
 676         drm_mode_config_cleanup(ddev);
 677
 678         omap_drm_irq_uninstall(ddev);
 679         omap_gem_deinit(ddev);
 680
 681         destroy_workqueue(priv->wq);
 682
 683         omap_disconnect_pipelines(ddev);
 684         omap_crtc_pre_uninit(priv);
 685
 686         drm_dev_put(ddev);
 687 }
 688
 689 static int pdev_probe(struct platform_device *pdev)
 690 {
 691         struct omap_drm_private *priv;
 692         int ret;
 693
 694         if (omapdss_is_initialized() == false)
 695                 return -EPROBE_DEFER;
 696
 697         ret = dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(32));
 698         if (ret) {
 699                 dev_err(&pdev->dev, "Failed to set the DMA mask\n");
 700                 return ret;
 701         }
 702
 703         /* Allocate and initialize the driver private structure. */
 704         priv = kzalloc(sizeof(*priv), GFP_KERNEL);
 705         if (!priv)
 706                 return -ENOMEM;
 707
 708         platform_set_drvdata(pdev, priv);
 709
 710         ret = omapdrm_init(priv, &pdev->dev);
 711         if (ret < 0)
 712                 kfree(priv);
 713
 714         return ret;
 715 }
 716
 717 static int pdev_remove(struct platform_device *pdev)
 718 {
 719         struct omap_drm_private *priv = platform_get_drvdata(pdev);
 720
 721         omapdrm_cleanup(priv);
 722         kfree(priv);
 723
 724         return 0;
 725 }
 726
 727 #ifdef CONFIG_PM_SLEEP
 728 static int omap_drm_suspend(struct device *dev)
 729 {
 730         struct omap_drm_private *priv = dev_get_drvdata(dev);
 731         struct drm_device *drm_dev = priv->ddev;
 732
 733         return drm_mode_config_helper_suspend(drm_dev);
 734 }
 735
 736 static int omap_drm_resume(struct device *dev)
 737 {
 738         struct omap_drm_private *priv = dev_get_drvdata(dev);
 739         struct drm_device *drm_dev = priv->ddev;
 740
 741         drm_mode_config_helper_resume(drm_dev);
 742
 743         return omap_gem_resume(drm_dev);
 744 }
 745 #endif
 746
 747 static SIMPLE_DEV_PM_OPS(omapdrm_pm_ops, omap_drm_suspend, omap_drm_resume);
 748
 749 static struct platform_driver pdev = {
 750         .driver = {
 751                 .name = "omapdrm",
 752                 .pm = &omapdrm_pm_ops,
 753         },
 754         .probe = pdev_probe,
 755         .remove = pdev_remove,
 756 };
 757
 758 static struct platform_driver * const drivers[] = {
 759         &omap_dmm_driver,
 760         &pdev,
 761 };
 762
 763 static int __init omap_drm_init(void)
 764 {
 765         DBG("init");
 766
 767         return platform_register_drivers(drivers, ARRAY_SIZE(drivers));
 768 }
 769
 770 static void __exit omap_drm_fini(void)
 771 {
 772         DBG("fini");
 773
 774         platform_unregister_drivers(drivers, ARRAY_SIZE(drivers));
 775 }
 776
 777 /* need late_initcall() so we load after dss_driver's are loaded */
 778 late_initcall(omap_drm_init);
 779 module_exit(omap_drm_fini);
 780
 781 MODULE_AUTHOR("Rob Clark <[email protected]>");
 782 MODULE_DESCRIPTION("OMAP DRM Display Driver");
 783 MODULE_ALIAS("platform:" DRIVER_NAME);
 784 MODULE_LICENSE("GPL v2");