drivers/gpu/drm/i915/intel_overlay.c

   1 /*
   2  * Copyright © 2009
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  20  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  21  * SOFTWARE.
  22  *
  23  * Authors:
  24  *    Daniel Vetter <[email protected]>
  25  *
  26  * Derived from Xorg ddx, xf86-video-intel, src/i830_video.c
  27  */
  28
  29 #include <drm/drm_fourcc.h>
  30 #include <drm/i915_drm.h>
  31
  32 #include "i915_drv.h"
  33 #include "i915_reg.h"
  34 #include "intel_drv.h"
  35 #include "intel_frontbuffer.h"
  36 #include "intel_overlay.h"
  37
  38 /* Limits for overlay size. According to intel doc, the real limits are:
  39  * Y width: 4095, UV width (planar): 2047, Y height: 2047,
  40  * UV width (planar): * 1023. But the xorg thinks 2048 for height and width. Use
  41  * the mininum of both.  */
  42 #define IMAGE_MAX_WIDTH         2048
  43 #define IMAGE_MAX_HEIGHT        2046 /* 2 * 1023 */
  44 /* on 830 and 845 these large limits result in the card hanging */
  45 #define IMAGE_MAX_WIDTH_LEGACY  1024
  46 #define IMAGE_MAX_HEIGHT_LEGACY 1088
  47
  48 /* overlay register definitions */
  49 /* OCMD register */
  50 #define OCMD_TILED_SURFACE      (0x1<<19)
  51 #define OCMD_MIRROR_MASK        (0x3<<17)
  52 #define OCMD_MIRROR_MODE        (0x3<<17)
  53 #define OCMD_MIRROR_HORIZONTAL  (0x1<<17)
  54 #define OCMD_MIRROR_VERTICAL    (0x2<<17)
  55 #define OCMD_MIRROR_BOTH        (0x3<<17)
  56 #define OCMD_BYTEORDER_MASK     (0x3<<14) /* zero for YUYV or FOURCC YUY2 */
  57 #define OCMD_UV_SWAP            (0x1<<14) /* YVYU */
  58 #define OCMD_Y_SWAP             (0x2<<14) /* UYVY or FOURCC UYVY */
  59 #define OCMD_Y_AND_UV_SWAP      (0x3<<14) /* VYUY */
  60 #define OCMD_SOURCE_FORMAT_MASK (0xf<<10)
  61 #define OCMD_RGB_888            (0x1<<10) /* not in i965 Intel docs */
  62 #define OCMD_RGB_555            (0x2<<10) /* not in i965 Intel docs */
  63 #define OCMD_RGB_565            (0x3<<10) /* not in i965 Intel docs */
  64 #define OCMD_YUV_422_PACKED     (0x8<<10)
  65 #define OCMD_YUV_411_PACKED     (0x9<<10) /* not in i965 Intel docs */
  66 #define OCMD_YUV_420_PLANAR     (0xc<<10)
  67 #define OCMD_YUV_422_PLANAR     (0xd<<10)
  68 #define OCMD_YUV_410_PLANAR     (0xe<<10) /* also 411 */
  69 #define OCMD_TVSYNCFLIP_PARITY  (0x1<<9)
  70 #define OCMD_TVSYNCFLIP_ENABLE  (0x1<<7)
  71 #define OCMD_BUF_TYPE_MASK      (0x1<<5)
  72 #define OCMD_BUF_TYPE_FRAME     (0x0<<5)
  73 #define OCMD_BUF_TYPE_FIELD     (0x1<<5)
  74 #define OCMD_TEST_MODE          (0x1<<4)
  75 #define OCMD_BUFFER_SELECT      (0x3<<2)
  76 #define OCMD_BUFFER0            (0x0<<2)
  77 #define OCMD_BUFFER1            (0x1<<2)
  78 #define OCMD_FIELD_SELECT       (0x1<<2)
  79 #define OCMD_FIELD0             (0x0<<1)
  80 #define OCMD_FIELD1             (0x1<<1)
  81 #define OCMD_ENABLE             (0x1<<0)
  82
  83 /* OCONFIG register */
  84 #define OCONF_PIPE_MASK         (0x1<<18)
  85 #define OCONF_PIPE_A            (0x0<<18)
  86 #define OCONF_PIPE_B            (0x1<<18)
  87 #define OCONF_GAMMA2_ENABLE     (0x1<<16)
  88 #define OCONF_CSC_MODE_BT601    (0x0<<5)
  89 #define OCONF_CSC_MODE_BT709    (0x1<<5)
  90 #define OCONF_CSC_BYPASS        (0x1<<4)
  91 #define OCONF_CC_OUT_8BIT       (0x1<<3)
  92 #define OCONF_TEST_MODE         (0x1<<2)
  93 #define OCONF_THREE_LINE_BUFFER (0x1<<0)
  94 #define OCONF_TWO_LINE_BUFFER   (0x0<<0)
  95
  96 /* DCLRKM (dst-key) register */
  97 #define DST_KEY_ENABLE          (0x1<<31)
  98 #define CLK_RGB24_MASK          0x0
  99 #define CLK_RGB16_MASK          0x070307
 100 #define CLK_RGB15_MASK          0x070707
 101 #define CLK_RGB8I_MASK          0xffffff
 102
 103 #define RGB16_TO_COLORKEY(c) \
 104         (((c & 0xF800) << 8) | ((c & 0x07E0) << 5) | ((c & 0x001F) << 3))
 105 #define RGB15_TO_COLORKEY(c) \
 106         (((c & 0x7c00) << 9) | ((c & 0x03E0) << 6) | ((c & 0x001F) << 3))
 107
 108 /* overlay flip addr flag */
 109 #define OFC_UPDATE              0x1
 110
 111 /* polyphase filter coefficients */
 112 #define N_HORIZ_Y_TAPS          5
 113 #define N_VERT_Y_TAPS           3
 114 #define N_HORIZ_UV_TAPS         3
 115 #define N_VERT_UV_TAPS          3
 116 #define N_PHASES                17
 117 #define MAX_TAPS                5
 118
 119 /* memory bufferd overlay registers */
 120 struct overlay_registers {
 121         u32 OBUF_0Y;
 122         u32 OBUF_1Y;
 123         u32 OBUF_0U;
 124         u32 OBUF_0V;
 125         u32 OBUF_1U;
 126         u32 OBUF_1V;
 127         u32 OSTRIDE;
 128         u32 YRGB_VPH;
 129         u32 UV_VPH;
 130         u32 HORZ_PH;
 131         u32 INIT_PHS;
 132         u32 DWINPOS;
 133         u32 DWINSZ;
 134         u32 SWIDTH;
 135         u32 SWIDTHSW;
 136         u32 SHEIGHT;
 137         u32 YRGBSCALE;
 138         u32 UVSCALE;
 139         u32 OCLRC0;
 140         u32 OCLRC1;
 141         u32 DCLRKV;
 142         u32 DCLRKM;
 143         u32 SCLRKVH;
 144         u32 SCLRKVL;
 145         u32 SCLRKEN;
 146         u32 OCONFIG;
 147         u32 OCMD;
 148         u32 RESERVED1; /* 0x6C */
 149         u32 OSTART_0Y;
 150         u32 OSTART_1Y;
 151         u32 OSTART_0U;
 152         u32 OSTART_0V;
 153         u32 OSTART_1U;
 154         u32 OSTART_1V;
 155         u32 OTILEOFF_0Y;
 156         u32 OTILEOFF_1Y;
 157         u32 OTILEOFF_0U;
 158         u32 OTILEOFF_0V;
 159         u32 OTILEOFF_1U;
 160         u32 OTILEOFF_1V;
 161         u32 FASTHSCALE; /* 0xA0 */
 162         u32 UVSCALEV; /* 0xA4 */
 163         u32 RESERVEDC[(0x200 - 0xA8) / 4]; /* 0xA8 - 0x1FC */
 164         u16 Y_VCOEFS[N_VERT_Y_TAPS * N_PHASES]; /* 0x200 */
 165         u16 RESERVEDD[0x100 / 2 - N_VERT_Y_TAPS * N_PHASES];
 166         u16 Y_HCOEFS[N_HORIZ_Y_TAPS * N_PHASES]; /* 0x300 */
 167         u16 RESERVEDE[0x200 / 2 - N_HORIZ_Y_TAPS * N_PHASES];
 168         u16 UV_VCOEFS[N_VERT_UV_TAPS * N_PHASES]; /* 0x500 */
 169         u16 RESERVEDF[0x100 / 2 - N_VERT_UV_TAPS * N_PHASES];
 170         u16 UV_HCOEFS[N_HORIZ_UV_TAPS * N_PHASES]; /* 0x600 */
 171         u16 RESERVEDG[0x100 / 2 - N_HORIZ_UV_TAPS * N_PHASES];
 172 };
 173
 174 struct intel_overlay {
 175         struct drm_i915_private *i915;
 176         struct intel_crtc *crtc;
 177         struct i915_vma *vma;
 178         struct i915_vma *old_vma;
 179         bool active;
 180         bool pfit_active;
 181         u32 pfit_vscale_ratio; /* shifted-point number, (1<<12) == 1.0 */
 182         u32 color_key:24;
 183         u32 color_key_enabled:1;
 184         u32 brightness, contrast, saturation;
 185         u32 old_xscale, old_yscale;
 186         /* register access */
 187         struct drm_i915_gem_object *reg_bo;
 188         struct overlay_registers __iomem *regs;
 189         u32 flip_addr;
 190         /* flip handling */
 191         struct i915_active_request last_flip;
 192 };
 193
 194 static void i830_overlay_clock_gating(struct drm_i915_private *dev_priv,
 195                                       bool enable)
 196 {
 197         struct pci_dev *pdev = dev_priv->drm.pdev;
 198         u8 val;
 199
 200         /* WA_OVERLAY_CLKGATE:alm */
 201         if (enable)
 202                 I915_WRITE(DSPCLK_GATE_D, 0);
 203         else
 204                 I915_WRITE(DSPCLK_GATE_D, OVRUNIT_CLOCK_GATE_DISABLE);
 205
 206         /* WA_DISABLE_L2CACHE_CLOCK_GATING:alm */
 207         pci_bus_read_config_byte(pdev->bus,
 208                                  PCI_DEVFN(0, 0), I830_CLOCK_GATE, &val);
 209         if (enable)
 210                 val &= ~I830_L2_CACHE_CLOCK_GATE_DISABLE;
 211         else
 212                 val |= I830_L2_CACHE_CLOCK_GATE_DISABLE;
 213         pci_bus_write_config_byte(pdev->bus,
 214                                   PCI_DEVFN(0, 0), I830_CLOCK_GATE, val);
 215 }
 216
 217 static void intel_overlay_submit_request(struct intel_overlay *overlay,
 218                                          struct i915_request *rq,
 219                                          i915_active_retire_fn retire)
 220 {
 221         GEM_BUG_ON(i915_active_request_peek(&overlay->last_flip,
 222                                             &overlay->i915->drm.struct_mutex));
 223         i915_active_request_set_retire_fn(&overlay->last_flip, retire,
 224                                           &overlay->i915->drm.struct_mutex);
 225         __i915_active_request_set(&overlay->last_flip, rq);
 226         i915_request_add(rq);
 227 }
 228
 229 static int intel_overlay_do_wait_request(struct intel_overlay *overlay,
 230                                          struct i915_request *rq,
 231                                          i915_active_retire_fn retire)
 232 {
 233         intel_overlay_submit_request(overlay, rq, retire);
 234         return i915_active_request_retire(&overlay->last_flip,
 235                                           &overlay->i915->drm.struct_mutex);
 236 }
 237
 238 static struct i915_request *alloc_request(struct intel_overlay *overlay)
 239 {
 240         struct intel_engine_cs *engine = overlay->i915->engine[RCS0];
 241
 242         return i915_request_create(engine->kernel_context);
 243 }
 244
 245 /* overlay needs to be disable in OCMD reg */
 246 static int intel_overlay_on(struct intel_overlay *overlay)
 247 {
 248         struct drm_i915_private *dev_priv = overlay->i915;
 249         struct i915_request *rq;
 250         u32 *cs;
 251
 252         WARN_ON(overlay->active);
 253
 254         rq = alloc_request(overlay);
 255         if (IS_ERR(rq))
 256                 return PTR_ERR(rq);
 257
 258         cs = intel_ring_begin(rq, 4);
 259         if (IS_ERR(cs)) {
 260                 i915_request_add(rq);
 261                 return PTR_ERR(cs);
 262         }
 263
 264         overlay->active = true;
 265
 266         if (IS_I830(dev_priv))
 267                 i830_overlay_clock_gating(dev_priv, false);
 268
 269         *cs++ = MI_OVERLAY_FLIP | MI_OVERLAY_ON;
 270         *cs++ = overlay->flip_addr | OFC_UPDATE;
 271         *cs++ = MI_WAIT_FOR_EVENT | MI_WAIT_FOR_OVERLAY_FLIP;
 272         *cs++ = MI_NOOP;
 273         intel_ring_advance(rq, cs);
 274
 275         return intel_overlay_do_wait_request(overlay, rq, NULL);
 276 }
 277
 278 static void intel_overlay_flip_prepare(struct intel_overlay *overlay,
 279                                        struct i915_vma *vma)
 280 {
 281         enum pipe pipe = overlay->crtc->pipe;
 282
 283         WARN_ON(overlay->old_vma);
 284
 285         i915_gem_track_fb(overlay->vma ? overlay->vma->obj : NULL,
 286                           vma ? vma->obj : NULL,
 287                           INTEL_FRONTBUFFER_OVERLAY(pipe));
 288
 289         intel_frontbuffer_flip_prepare(overlay->i915,
 290                                        INTEL_FRONTBUFFER_OVERLAY(pipe));
 291
 292         overlay->old_vma = overlay->vma;
 293         if (vma)
 294                 overlay->vma = i915_vma_get(vma);
 295         else
 296                 overlay->vma = NULL;
 297 }
 298
 299 /* overlay needs to be enabled in OCMD reg */
 300 static int intel_overlay_continue(struct intel_overlay *overlay,
 301                                   struct i915_vma *vma,
 302                                   bool load_polyphase_filter)
 303 {
 304         struct drm_i915_private *dev_priv = overlay->i915;
 305         struct i915_request *rq;
 306         u32 flip_addr = overlay->flip_addr;
 307         u32 tmp, *cs;
 308
 309         WARN_ON(!overlay->active);
 310
 311         if (load_polyphase_filter)
 312                 flip_addr |= OFC_UPDATE;
 313
 314         /* check for underruns */
 315         tmp = I915_READ(DOVSTA);
 316         if (tmp & (1 << 17))
 317                 DRM_DEBUG("overlay underrun, DOVSTA: %x\n", tmp);
 318
 319         rq = alloc_request(overlay);
 320         if (IS_ERR(rq))
 321                 return PTR_ERR(rq);
 322
 323         cs = intel_ring_begin(rq, 2);
 324         if (IS_ERR(cs)) {
 325                 i915_request_add(rq);
 326                 return PTR_ERR(cs);
 327         }
 328
 329         *cs++ = MI_OVERLAY_FLIP | MI_OVERLAY_CONTINUE;
 330         *cs++ = flip_addr;
 331         intel_ring_advance(rq, cs);
 332
 333         intel_overlay_flip_prepare(overlay, vma);
 334
 335         intel_overlay_submit_request(overlay, rq, NULL);
 336
 337         return 0;
 338 }
 339
 340 static void intel_overlay_release_old_vma(struct intel_overlay *overlay)
 341 {
 342         struct i915_vma *vma;
 343
 344         vma = fetch_and_zero(&overlay->old_vma);
 345         if (WARN_ON(!vma))
 346                 return;
 347
 348         intel_frontbuffer_flip_complete(overlay->i915,
 349                                         INTEL_FRONTBUFFER_OVERLAY(overlay->crtc->pipe));
 350
 351         i915_gem_object_unpin_from_display_plane(vma);
 352         i915_vma_put(vma);
 353 }
 354
 355 static void
 356 intel_overlay_release_old_vid_tail(struct i915_active_request *active,
 357                                    struct i915_request *rq)
 358 {
 359         struct intel_overlay *overlay =
 360                 container_of(active, typeof(*overlay), last_flip);
 361
 362         intel_overlay_release_old_vma(overlay);
 363 }
 364
 365 static void intel_overlay_off_tail(struct i915_active_request *active,
 366                                    struct i915_request *rq)
 367 {
 368         struct intel_overlay *overlay =
 369                 container_of(active, typeof(*overlay), last_flip);
 370         struct drm_i915_private *dev_priv = overlay->i915;
 371
 372         intel_overlay_release_old_vma(overlay);
 373
 374         overlay->crtc->overlay = NULL;
 375         overlay->crtc = NULL;
 376         overlay->active = false;
 377
 378         if (IS_I830(dev_priv))
 379                 i830_overlay_clock_gating(dev_priv, true);
 380 }
 381
 382 /* overlay needs to be disabled in OCMD reg */
 383 static int intel_overlay_off(struct intel_overlay *overlay)
 384 {
 385         struct i915_request *rq;
 386         u32 *cs, flip_addr = overlay->flip_addr;
 387
 388         WARN_ON(!overlay->active);
 389
 390         /* According to intel docs the overlay hw may hang (when switching
 391          * off) without loading the filter coeffs. It is however unclear whether
 392          * this applies to the disabling of the overlay or to the switching off
 393          * of the hw. Do it in both cases */
 394         flip_addr |= OFC_UPDATE;
 395
 396         rq = alloc_request(overlay);
 397         if (IS_ERR(rq))
 398                 return PTR_ERR(rq);
 399
 400         cs = intel_ring_begin(rq, 6);
 401         if (IS_ERR(cs)) {
 402                 i915_request_add(rq);
 403                 return PTR_ERR(cs);
 404         }
 405
 406         /* wait for overlay to go idle */
 407         *cs++ = MI_OVERLAY_FLIP | MI_OVERLAY_CONTINUE;
 408         *cs++ = flip_addr;
 409         *cs++ = MI_WAIT_FOR_EVENT | MI_WAIT_FOR_OVERLAY_FLIP;
 410
 411         /* turn overlay off */
 412         *cs++ = MI_OVERLAY_FLIP | MI_OVERLAY_OFF;
 413         *cs++ = flip_addr;
 414         *cs++ = MI_WAIT_FOR_EVENT | MI_WAIT_FOR_OVERLAY_FLIP;
 415
 416         intel_ring_advance(rq, cs);
 417
 418         intel_overlay_flip_prepare(overlay, NULL);
 419
 420         return intel_overlay_do_wait_request(overlay, rq,
 421                                              intel_overlay_off_tail);
 422 }
 423
 424 /* recover from an interruption due to a signal
 425  * We have to be careful not to repeat work forever an make forward progess. */
 426 static int intel_overlay_recover_from_interrupt(struct intel_overlay *overlay)
 427 {
 428         return i915_active_request_retire(&overlay->last_flip,
 429                                           &overlay->i915->drm.struct_mutex);
 430 }
 431
 432 /* Wait for pending overlay flip and release old frame.
 433  * Needs to be called before the overlay register are changed
 434  * via intel_overlay_(un)map_regs
 435  */
 436 static int intel_overlay_release_old_vid(struct intel_overlay *overlay)
 437 {
 438         struct drm_i915_private *dev_priv = overlay->i915;
 439         u32 *cs;
 440         int ret;
 441
 442         lockdep_assert_held(&dev_priv->drm.struct_mutex);
 443
 444         /* Only wait if there is actually an old frame to release to
 445          * guarantee forward progress.
 446          */
 447         if (!overlay->old_vma)
 448                 return 0;
 449
 450         if (I915_READ(GEN2_ISR) & I915_OVERLAY_PLANE_FLIP_PENDING_INTERRUPT) {
 451                 /* synchronous slowpath */
 452                 struct i915_request *rq;
 453
 454                 rq = alloc_request(overlay);
 455                 if (IS_ERR(rq))
 456                         return PTR_ERR(rq);
 457
 458                 cs = intel_ring_begin(rq, 2);
 459                 if (IS_ERR(cs)) {
 460                         i915_request_add(rq);
 461                         return PTR_ERR(cs);
 462                 }
 463
 464                 *cs++ = MI_WAIT_FOR_EVENT | MI_WAIT_FOR_OVERLAY_FLIP;
 465                 *cs++ = MI_NOOP;
 466                 intel_ring_advance(rq, cs);
 467
 468                 ret = intel_overlay_do_wait_request(overlay, rq,
 469                                                     intel_overlay_release_old_vid_tail);
 470                 if (ret)
 471                         return ret;
 472         } else
 473                 intel_overlay_release_old_vid_tail(&overlay->last_flip, NULL);
 474
 475         return 0;
 476 }
 477
 478 void intel_overlay_reset(struct drm_i915_private *dev_priv)
 479 {
 480         struct intel_overlay *overlay = dev_priv->overlay;
 481
 482         if (!overlay)
 483                 return;
 484
 485         overlay->old_xscale = 0;
 486         overlay->old_yscale = 0;
 487         overlay->crtc = NULL;
 488         overlay->active = false;
 489 }
 490
 491 static int packed_depth_bytes(u32 format)
 492 {
 493         switch (format & I915_OVERLAY_DEPTH_MASK) {
 494         case I915_OVERLAY_YUV422:
 495                 return 4;
 496         case I915_OVERLAY_YUV411:
 497                 /* return 6; not implemented */
 498         default:
 499                 return -EINVAL;
 500         }
 501 }
 502
 503 static int packed_width_bytes(u32 format, short width)
 504 {
 505         switch (format & I915_OVERLAY_DEPTH_MASK) {
 506         case I915_OVERLAY_YUV422:
 507                 return width << 1;
 508         default:
 509                 return -EINVAL;
 510         }
 511 }
 512
 513 static int uv_hsubsampling(u32 format)
 514 {
 515         switch (format & I915_OVERLAY_DEPTH_MASK) {
 516         case I915_OVERLAY_YUV422:
 517         case I915_OVERLAY_YUV420:
 518                 return 2;
 519         case I915_OVERLAY_YUV411:
 520         case I915_OVERLAY_YUV410:
 521                 return 4;
 522         default:
 523                 return -EINVAL;
 524         }
 525 }
 526
 527 static int uv_vsubsampling(u32 format)
 528 {
 529         switch (format & I915_OVERLAY_DEPTH_MASK) {
 530         case I915_OVERLAY_YUV420:
 531         case I915_OVERLAY_YUV410:
 532                 return 2;
 533         case I915_OVERLAY_YUV422:
 534         case I915_OVERLAY_YUV411:
 535                 return 1;
 536         default:
 537                 return -EINVAL;
 538         }
 539 }
 540
 541 static u32 calc_swidthsw(struct drm_i915_private *dev_priv, u32 offset, u32 width)
 542 {
 543         u32 sw;
 544
 545         if (IS_GEN(dev_priv, 2))
 546                 sw = ALIGN((offset & 31) + width, 32);
 547         else
 548                 sw = ALIGN((offset & 63) + width, 64);
 549
 550         if (sw == 0)
 551                 return 0;
 552
 553         return (sw - 32) >> 3;
 554 }
 555
 556 static const u16 y_static_hcoeffs[N_PHASES][N_HORIZ_Y_TAPS] = {
 557         [ 0] = { 0x3000, 0xb4a0, 0x1930, 0x1920, 0xb4a0, },
 558         [ 1] = { 0x3000, 0xb500, 0x19d0, 0x1880, 0xb440, },
 559         [ 2] = { 0x3000, 0xb540, 0x1a88, 0x2f80, 0xb3e0, },
 560         [ 3] = { 0x3000, 0xb580, 0x1b30, 0x2e20, 0xb380, },
 561         [ 4] = { 0x3000, 0xb5c0, 0x1bd8, 0x2cc0, 0xb320, },
 562         [ 5] = { 0x3020, 0xb5e0, 0x1c60, 0x2b80, 0xb2c0, },
 563         [ 6] = { 0x3020, 0xb5e0, 0x1cf8, 0x2a20, 0xb260, },
 564         [ 7] = { 0x3020, 0xb5e0, 0x1d80, 0x28e0, 0xb200, },
 565         [ 8] = { 0x3020, 0xb5c0, 0x1e08, 0x3f40, 0xb1c0, },
 566         [ 9] = { 0x3020, 0xb580, 0x1e78, 0x3ce0, 0xb160, },
 567         [10] = { 0x3040, 0xb520, 0x1ed8, 0x3aa0, 0xb120, },
 568         [11] = { 0x3040, 0xb4a0, 0x1f30, 0x3880, 0xb0e0, },
 569         [12] = { 0x3040, 0xb400, 0x1f78, 0x3680, 0xb0a0, },
 570         [13] = { 0x3020, 0xb340, 0x1fb8, 0x34a0, 0xb060, },
 571         [14] = { 0x3020, 0xb240, 0x1fe0, 0x32e0, 0xb040, },
 572         [15] = { 0x3020, 0xb140, 0x1ff8, 0x3160, 0xb020, },
 573         [16] = { 0xb000, 0x3000, 0x0800, 0x3000, 0xb000, },
 574 };
 575
 576 static const u16 uv_static_hcoeffs[N_PHASES][N_HORIZ_UV_TAPS] = {
 577         [ 0] = { 0x3000, 0x1800, 0x1800, },
 578         [ 1] = { 0xb000, 0x18d0, 0x2e60, },
 579         [ 2] = { 0xb000, 0x1990, 0x2ce0, },
 580         [ 3] = { 0xb020, 0x1a68, 0x2b40, },
 581         [ 4] = { 0xb040, 0x1b20, 0x29e0, },
 582         [ 5] = { 0xb060, 0x1bd8, 0x2880, },
 583         [ 6] = { 0xb080, 0x1c88, 0x3e60, },
 584         [ 7] = { 0xb0a0, 0x1d28, 0x3c00, },
 585         [ 8] = { 0xb0c0, 0x1db8, 0x39e0, },
 586         [ 9] = { 0xb0e0, 0x1e40, 0x37e0, },
 587         [10] = { 0xb100, 0x1eb8, 0x3620, },
 588         [11] = { 0xb100, 0x1f18, 0x34a0, },
 589         [12] = { 0xb100, 0x1f68, 0x3360, },
 590         [13] = { 0xb0e0, 0x1fa8, 0x3240, },
 591         [14] = { 0xb0c0, 0x1fe0, 0x3140, },
 592         [15] = { 0xb060, 0x1ff0, 0x30a0, },
 593         [16] = { 0x3000, 0x0800, 0x3000, },
 594 };
 595
 596 static void update_polyphase_filter(struct overlay_registers __iomem *regs)
 597 {
 598         memcpy_toio(regs->Y_HCOEFS, y_static_hcoeffs, sizeof(y_static_hcoeffs));
 599         memcpy_toio(regs->UV_HCOEFS, uv_static_hcoeffs,
 600                     sizeof(uv_static_hcoeffs));
 601 }
 602
 603 static bool update_scaling_factors(struct intel_overlay *overlay,
 604                                    struct overlay_registers __iomem *regs,
 605                                    struct drm_intel_overlay_put_image *params)
 606 {
 607         /* fixed point with a 12 bit shift */
 608         u32 xscale, yscale, xscale_UV, yscale_UV;
 609 #define FP_SHIFT 12
 610 #define FRACT_MASK 0xfff
 611         bool scale_changed = false;
 612         int uv_hscale = uv_hsubsampling(params->flags);
 613         int uv_vscale = uv_vsubsampling(params->flags);
 614
 615         if (params->dst_width > 1)
 616                 xscale = ((params->src_scan_width - 1) << FP_SHIFT) /
 617                         params->dst_width;
 618         else
 619                 xscale = 1 << FP_SHIFT;
 620
 621         if (params->dst_height > 1)
 622                 yscale = ((params->src_scan_height - 1) << FP_SHIFT) /
 623                         params->dst_height;
 624         else
 625                 yscale = 1 << FP_SHIFT;
 626
 627         /*if (params->format & I915_OVERLAY_YUV_PLANAR) {*/
 628         xscale_UV = xscale/uv_hscale;
 629         yscale_UV = yscale/uv_vscale;
 630         /* make the Y scale to UV scale ratio an exact multiply */
 631         xscale = xscale_UV * uv_hscale;
 632         yscale = yscale_UV * uv_vscale;
 633         /*} else {
 634           xscale_UV = 0;
 635           yscale_UV = 0;
 636           }*/
 637
 638         if (xscale != overlay->old_xscale || yscale != overlay->old_yscale)
 639                 scale_changed = true;
 640         overlay->old_xscale = xscale;
 641         overlay->old_yscale = yscale;
 642
 643         iowrite32(((yscale & FRACT_MASK) << 20) |
 644                   ((xscale >> FP_SHIFT)  << 16) |
 645                   ((xscale & FRACT_MASK) << 3),
 646                  &regs->YRGBSCALE);
 647
 648         iowrite32(((yscale_UV & FRACT_MASK) << 20) |
 649                   ((xscale_UV >> FP_SHIFT)  << 16) |
 650                   ((xscale_UV & FRACT_MASK) << 3),
 651                  &regs->UVSCALE);
 652
 653         iowrite32((((yscale    >> FP_SHIFT) << 16) |
 654                    ((yscale_UV >> FP_SHIFT) << 0)),
 655                  &regs->UVSCALEV);
 656
 657         if (scale_changed)
 658                 update_polyphase_filter(regs);
 659
 660         return scale_changed;
 661 }
 662
 663 static void update_colorkey(struct intel_overlay *overlay,
 664                             struct overlay_registers __iomem *regs)
 665 {
 666         const struct intel_plane_state *state =
 667                 to_intel_plane_state(overlay->crtc->base.primary->state);
 668         u32 key = overlay->color_key;
 669         u32 format = 0;
 670         u32 flags = 0;
 671
 672         if (overlay->color_key_enabled)
 673                 flags |= DST_KEY_ENABLE;
 674
 675         if (state->base.visible)
 676                 format = state->base.fb->format->format;
 677
 678         switch (format) {
 679         case DRM_FORMAT_C8:
 680                 key = 0;
 681                 flags |= CLK_RGB8I_MASK;
 682                 break;
 683         case DRM_FORMAT_XRGB1555:
 684                 key = RGB15_TO_COLORKEY(key);
 685                 flags |= CLK_RGB15_MASK;
 686                 break;
 687         case DRM_FORMAT_RGB565:
 688                 key = RGB16_TO_COLORKEY(key);
 689                 flags |= CLK_RGB16_MASK;
 690                 break;
 691         default:
 692                 flags |= CLK_RGB24_MASK;
 693                 break;
 694         }
 695
 696         iowrite32(key, &regs->DCLRKV);
 697         iowrite32(flags, &regs->DCLRKM);
 698 }
 699
 700 static u32 overlay_cmd_reg(struct drm_intel_overlay_put_image *params)
 701 {
 702         u32 cmd = OCMD_ENABLE | OCMD_BUF_TYPE_FRAME | OCMD_BUFFER0;
 703
 704         if (params->flags & I915_OVERLAY_YUV_PLANAR) {
 705                 switch (params->flags & I915_OVERLAY_DEPTH_MASK) {
 706                 case I915_OVERLAY_YUV422:
 707                         cmd |= OCMD_YUV_422_PLANAR;
 708                         break;
 709                 case I915_OVERLAY_YUV420:
 710                         cmd |= OCMD_YUV_420_PLANAR;
 711                         break;
 712                 case I915_OVERLAY_YUV411:
 713                 case I915_OVERLAY_YUV410:
 714                         cmd |= OCMD_YUV_410_PLANAR;
 715                         break;
 716                 }
 717         } else { /* YUV packed */
 718                 switch (params->flags & I915_OVERLAY_DEPTH_MASK) {
 719                 case I915_OVERLAY_YUV422:
 720                         cmd |= OCMD_YUV_422_PACKED;
 721                         break;
 722                 case I915_OVERLAY_YUV411:
 723                         cmd |= OCMD_YUV_411_PACKED;
 724                         break;
 725                 }
 726
 727                 switch (params->flags & I915_OVERLAY_SWAP_MASK) {
 728                 case I915_OVERLAY_NO_SWAP:
 729                         break;
 730                 case I915_OVERLAY_UV_SWAP:
 731                         cmd |= OCMD_UV_SWAP;
 732                         break;
 733                 case I915_OVERLAY_Y_SWAP:
 734                         cmd |= OCMD_Y_SWAP;
 735                         break;
 736                 case I915_OVERLAY_Y_AND_UV_SWAP:
 737                         cmd |= OCMD_Y_AND_UV_SWAP;
 738                         break;
 739                 }
 740         }
 741
 742         return cmd;
 743 }
 744
 745 static int intel_overlay_do_put_image(struct intel_overlay *overlay,
 746                                       struct drm_i915_gem_object *new_bo,
 747                                       struct drm_intel_overlay_put_image *params)
 748 {
 749         struct overlay_registers __iomem *regs = overlay->regs;
 750         struct drm_i915_private *dev_priv = overlay->i915;
 751         u32 swidth, swidthsw, sheight, ostride;
 752         enum pipe pipe = overlay->crtc->pipe;
 753         bool scale_changed = false;
 754         struct i915_vma *vma;
 755         int ret, tmp_width;
 756
 757         lockdep_assert_held(&dev_priv->drm.struct_mutex);
 758         WARN_ON(!drm_modeset_is_locked(&dev_priv->drm.mode_config.connection_mutex));
 759
 760         ret = intel_overlay_release_old_vid(overlay);
 761         if (ret != 0)
 762                 return ret;
 763
 764         atomic_inc(&dev_priv->gpu_error.pending_fb_pin);
 765
 766         vma = i915_gem_object_pin_to_display_plane(new_bo,
 767                                                    0, NULL, PIN_MAPPABLE);
 768         if (IS_ERR(vma)) {
 769                 ret = PTR_ERR(vma);
 770                 goto out_pin_section;
 771         }
 772         intel_fb_obj_flush(new_bo, ORIGIN_DIRTYFB);
 773
 774         ret = i915_vma_put_fence(vma);
 775         if (ret)
 776                 goto out_unpin;
 777
 778         if (!overlay->active) {
 779                 u32 oconfig;
 780
 781                 oconfig = OCONF_CC_OUT_8BIT;
 782                 if (IS_GEN(dev_priv, 4))
 783                         oconfig |= OCONF_CSC_MODE_BT709;
 784                 oconfig |= pipe == 0 ?
 785                         OCONF_PIPE_A : OCONF_PIPE_B;
 786                 iowrite32(oconfig, &regs->OCONFIG);
 787
 788                 ret = intel_overlay_on(overlay);
 789                 if (ret != 0)
 790                         goto out_unpin;
 791         }
 792
 793         iowrite32(params->dst_y << 16 | params->dst_x, &regs->DWINPOS);
 794         iowrite32(params->dst_height << 16 | params->dst_width, &regs->DWINSZ);
 795
 796         if (params->flags & I915_OVERLAY_YUV_PACKED)
 797                 tmp_width = packed_width_bytes(params->flags,
 798                                                params->src_width);
 799         else
 800                 tmp_width = params->src_width;
 801
 802         swidth = params->src_width;
 803         swidthsw = calc_swidthsw(dev_priv, params->offset_Y, tmp_width);
 804         sheight = params->src_height;
 805         iowrite32(i915_ggtt_offset(vma) + params->offset_Y, &regs->OBUF_0Y);
 806         ostride = params->stride_Y;
 807
 808         if (params->flags & I915_OVERLAY_YUV_PLANAR) {
 809                 int uv_hscale = uv_hsubsampling(params->flags);
 810                 int uv_vscale = uv_vsubsampling(params->flags);
 811                 u32 tmp_U, tmp_V;
 812
 813                 swidth |= (params->src_width / uv_hscale) << 16;
 814                 sheight |= (params->src_height / uv_vscale) << 16;
 815
 816                 tmp_U = calc_swidthsw(dev_priv, params->offset_U,
 817                                       params->src_width / uv_hscale);
 818                 tmp_V = calc_swidthsw(dev_priv, params->offset_V,
 819                                       params->src_width / uv_hscale);
 820                 swidthsw |= max(tmp_U, tmp_V) << 16;
 821
 822                 iowrite32(i915_ggtt_offset(vma) + params->offset_U,
 823                           &regs->OBUF_0U);
 824                 iowrite32(i915_ggtt_offset(vma) + params->offset_V,
 825                           &regs->OBUF_0V);
 826
 827                 ostride |= params->stride_UV << 16;
 828         }
 829
 830         iowrite32(swidth, &regs->SWIDTH);
 831         iowrite32(swidthsw, &regs->SWIDTHSW);
 832         iowrite32(sheight, &regs->SHEIGHT);
 833         iowrite32(ostride, &regs->OSTRIDE);
 834
 835         scale_changed = update_scaling_factors(overlay, regs, params);
 836
 837         update_colorkey(overlay, regs);
 838
 839         iowrite32(overlay_cmd_reg(params), &regs->OCMD);
 840
 841         ret = intel_overlay_continue(overlay, vma, scale_changed);
 842         if (ret)
 843                 goto out_unpin;
 844
 845         return 0;
 846
 847 out_unpin:
 848         i915_gem_object_unpin_from_display_plane(vma);
 849 out_pin_section:
 850         atomic_dec(&dev_priv->gpu_error.pending_fb_pin);
 851
 852         return ret;
 853 }
 854
 855 int intel_overlay_switch_off(struct intel_overlay *overlay)
 856 {
 857         struct drm_i915_private *dev_priv = overlay->i915;
 858         int ret;
 859
 860         lockdep_assert_held(&dev_priv->drm.struct_mutex);
 861         WARN_ON(!drm_modeset_is_locked(&dev_priv->drm.mode_config.connection_mutex));
 862
 863         ret = intel_overlay_recover_from_interrupt(overlay);
 864         if (ret != 0)
 865                 return ret;
 866
 867         if (!overlay->active)
 868                 return 0;
 869
 870         ret = intel_overlay_release_old_vid(overlay);
 871         if (ret != 0)
 872                 return ret;
 873
 874         iowrite32(0, &overlay->regs->OCMD);
 875
 876         return intel_overlay_off(overlay);
 877 }
 878
 879 static int check_overlay_possible_on_crtc(struct intel_overlay *overlay,
 880                                           struct intel_crtc *crtc)
 881 {
 882         if (!crtc->active)
 883                 return -EINVAL;
 884
 885         /* can't use the overlay with double wide pipe */
 886         if (crtc->config->double_wide)
 887                 return -EINVAL;
 888
 889         return 0;
 890 }
 891
 892 static void update_pfit_vscale_ratio(struct intel_overlay *overlay)
 893 {
 894         struct drm_i915_private *dev_priv = overlay->i915;
 895         u32 pfit_control = I915_READ(PFIT_CONTROL);
 896         u32 ratio;
 897
 898         /* XXX: This is not the same logic as in the xorg driver, but more in
 899          * line with the intel documentation for the i965
 900          */
 901         if (INTEL_GEN(dev_priv) >= 4) {
 902                 /* on i965 use the PGM reg to read out the autoscaler values */
 903                 ratio = I915_READ(PFIT_PGM_RATIOS) >> PFIT_VERT_SCALE_SHIFT_965;
 904         } else {
 905                 if (pfit_control & VERT_AUTO_SCALE)
 906                         ratio = I915_READ(PFIT_AUTO_RATIOS);
 907                 else
 908                         ratio = I915_READ(PFIT_PGM_RATIOS);
 909                 ratio >>= PFIT_VERT_SCALE_SHIFT;
 910         }
 911
 912         overlay->pfit_vscale_ratio = ratio;
 913 }
 914
 915 static int check_overlay_dst(struct intel_overlay *overlay,
 916                              struct drm_intel_overlay_put_image *rec)
 917 {
 918         const struct intel_crtc_state *pipe_config =
 919                 overlay->crtc->config;
 920
 921         if (rec->dst_x < pipe_config->pipe_src_w &&
 922             rec->dst_x + rec->dst_width <= pipe_config->pipe_src_w &&
 923             rec->dst_y < pipe_config->pipe_src_h &&
 924             rec->dst_y + rec->dst_height <= pipe_config->pipe_src_h)
 925                 return 0;
 926         else
 927                 return -EINVAL;
 928 }
 929
 930 static int check_overlay_scaling(struct drm_intel_overlay_put_image *rec)
 931 {
 932         u32 tmp;
 933
 934         /* downscaling limit is 8.0 */
 935         tmp = ((rec->src_scan_height << 16) / rec->dst_height) >> 16;
 936         if (tmp > 7)
 937                 return -EINVAL;
 938
 939         tmp = ((rec->src_scan_width << 16) / rec->dst_width) >> 16;
 940         if (tmp > 7)
 941                 return -EINVAL;
 942
 943         return 0;
 944 }
 945
 946 static int check_overlay_src(struct drm_i915_private *dev_priv,
 947                              struct drm_intel_overlay_put_image *rec,
 948                              struct drm_i915_gem_object *new_bo)
 949 {
 950         int uv_hscale = uv_hsubsampling(rec->flags);
 951         int uv_vscale = uv_vsubsampling(rec->flags);
 952         u32 stride_mask;
 953         int depth;
 954         u32 tmp;
 955
 956         /* check src dimensions */
 957         if (IS_I845G(dev_priv) || IS_I830(dev_priv)) {
 958                 if (rec->src_height > IMAGE_MAX_HEIGHT_LEGACY ||
 959                     rec->src_width  > IMAGE_MAX_WIDTH_LEGACY)
 960                         return -EINVAL;
 961         } else {
 962                 if (rec->src_height > IMAGE_MAX_HEIGHT ||
 963                     rec->src_width  > IMAGE_MAX_WIDTH)
 964                         return -EINVAL;
 965         }
 966
 967         /* better safe than sorry, use 4 as the maximal subsampling ratio */
 968         if (rec->src_height < N_VERT_Y_TAPS*4 ||
 969             rec->src_width  < N_HORIZ_Y_TAPS*4)
 970                 return -EINVAL;
 971
 972         /* check alignment constraints */
 973         switch (rec->flags & I915_OVERLAY_TYPE_MASK) {
 974         case I915_OVERLAY_RGB:
 975                 /* not implemented */
 976                 return -EINVAL;
 977
 978         case I915_OVERLAY_YUV_PACKED:
 979                 if (uv_vscale != 1)
 980                         return -EINVAL;
 981
 982                 depth = packed_depth_bytes(rec->flags);
 983                 if (depth < 0)
 984                         return depth;
 985
 986                 /* ignore UV planes */
 987                 rec->stride_UV = 0;
 988                 rec->offset_U = 0;
 989                 rec->offset_V = 0;
 990                 /* check pixel alignment */
 991                 if (rec->offset_Y % depth)
 992                         return -EINVAL;
 993                 break;
 994
 995         case I915_OVERLAY_YUV_PLANAR:
 996                 if (uv_vscale < 0 || uv_hscale < 0)
 997                         return -EINVAL;
 998                 /* no offset restrictions for planar formats */
 999                 break;
1000
1001         default:
1002                 return -EINVAL;
1003         }
1004
1005         if (rec->src_width % uv_hscale)
1006                 return -EINVAL;
1007
1008         /* stride checking */
1009         if (IS_I830(dev_priv) || IS_I845G(dev_priv))
1010                 stride_mask = 255;
1011         else
1012                 stride_mask = 63;
1013
1014         if (rec->stride_Y & stride_mask || rec->stride_UV & stride_mask)
1015                 return -EINVAL;
1016         if (IS_GEN(dev_priv, 4) && rec->stride_Y < 512)
1017                 return -EINVAL;
1018
1019         tmp = (rec->flags & I915_OVERLAY_TYPE_MASK) == I915_OVERLAY_YUV_PLANAR ?
1020                 4096 : 8192;
1021         if (rec->stride_Y > tmp || rec->stride_UV > 2*1024)
1022                 return -EINVAL;
1023
1024         /* check buffer dimensions */
1025         switch (rec->flags & I915_OVERLAY_TYPE_MASK) {
1026         case I915_OVERLAY_RGB:
1027         case I915_OVERLAY_YUV_PACKED:
1028                 /* always 4 Y values per depth pixels */
1029                 if (packed_width_bytes(rec->flags, rec->src_width) > rec->stride_Y)
1030                         return -EINVAL;
1031
1032                 tmp = rec->stride_Y*rec->src_height;
1033                 if (rec->offset_Y + tmp > new_bo->base.size)
1034                         return -EINVAL;
1035                 break;
1036
1037         case I915_OVERLAY_YUV_PLANAR:
1038                 if (rec->src_width > rec->stride_Y)
1039                         return -EINVAL;
1040                 if (rec->src_width/uv_hscale > rec->stride_UV)
1041                         return -EINVAL;
1042
1043                 tmp = rec->stride_Y * rec->src_height;
1044                 if (rec->offset_Y + tmp > new_bo->base.size)
1045                         return -EINVAL;
1046
1047                 tmp = rec->stride_UV * (rec->src_height / uv_vscale);
1048                 if (rec->offset_U + tmp > new_bo->base.size ||
1049                     rec->offset_V + tmp > new_bo->base.size)
1050                         return -EINVAL;
1051                 break;
1052         }
1053
1054         return 0;
1055 }
1056
1057 int intel_overlay_put_image_ioctl(struct drm_device *dev, void *data,
1058                                   struct drm_file *file_priv)
1059 {
1060         struct drm_intel_overlay_put_image *params = data;
1061         struct drm_i915_private *dev_priv = to_i915(dev);
1062         struct intel_overlay *overlay;
1063         struct drm_crtc *drmmode_crtc;
1064         struct intel_crtc *crtc;
1065         struct drm_i915_gem_object *new_bo;
1066         int ret;
1067
1068         overlay = dev_priv->overlay;
1069         if (!overlay) {
1070                 DRM_DEBUG("userspace bug: no overlay\n");
1071                 return -ENODEV;
1072         }
1073
1074         if (!(params->flags & I915_OVERLAY_ENABLE)) {
1075                 drm_modeset_lock_all(dev);
1076                 mutex_lock(&dev->struct_mutex);
1077
1078                 ret = intel_overlay_switch_off(overlay);
1079
1080                 mutex_unlock(&dev->struct_mutex);
1081                 drm_modeset_unlock_all(dev);
1082
1083                 return ret;
1084         }
1085
1086         drmmode_crtc = drm_crtc_find(dev, file_priv, params->crtc_id);
1087         if (!drmmode_crtc)
1088                 return -ENOENT;
1089         crtc = to_intel_crtc(drmmode_crtc);
1090
1091         new_bo = i915_gem_object_lookup(file_priv, params->bo_handle);
1092         if (!new_bo)
1093                 return -ENOENT;
1094
1095         drm_modeset_lock_all(dev);
1096         mutex_lock(&dev->struct_mutex);
1097
1098         if (i915_gem_object_is_tiled(new_bo)) {
1099                 DRM_DEBUG_KMS("buffer used for overlay image can not be tiled\n");
1100                 ret = -EINVAL;
1101                 goto out_unlock;
1102         }
1103
1104         ret = intel_overlay_recover_from_interrupt(overlay);
1105         if (ret != 0)
1106                 goto out_unlock;
1107
1108         if (overlay->crtc != crtc) {
1109                 ret = intel_overlay_switch_off(overlay);
1110                 if (ret != 0)
1111                         goto out_unlock;
1112
1113                 ret = check_overlay_possible_on_crtc(overlay, crtc);
1114                 if (ret != 0)
1115                         goto out_unlock;
1116
1117                 overlay->crtc = crtc;
1118                 crtc->overlay = overlay;
1119
1120                 /* line too wide, i.e. one-line-mode */
1121                 if (crtc->config->pipe_src_w > 1024 &&
1122                     crtc->config->gmch_pfit.control & PFIT_ENABLE) {
1123                         overlay->pfit_active = true;
1124                         update_pfit_vscale_ratio(overlay);
1125                 } else
1126                         overlay->pfit_active = false;
1127         }
1128
1129         ret = check_overlay_dst(overlay, params);
1130         if (ret != 0)
1131                 goto out_unlock;
1132
1133         if (overlay->pfit_active) {
1134                 params->dst_y = (((u32)params->dst_y << 12) /
1135                                  overlay->pfit_vscale_ratio);
1136                 /* shifting right rounds downwards, so add 1 */
1137                 params->dst_height = (((u32)params->dst_height << 12) /
1138                                  overlay->pfit_vscale_ratio) + 1;
1139         }
1140
1141         if (params->src_scan_height > params->src_height ||
1142             params->src_scan_width > params->src_width) {
1143                 ret = -EINVAL;
1144                 goto out_unlock;
1145         }
1146
1147         ret = check_overlay_src(dev_priv, params, new_bo);
1148         if (ret != 0)
1149                 goto out_unlock;
1150
1151         /* Check scaling after src size to prevent a divide-by-zero. */
1152         ret = check_overlay_scaling(params);
1153         if (ret != 0)
1154                 goto out_unlock;
1155
1156         ret = intel_overlay_do_put_image(overlay, new_bo, params);
1157         if (ret != 0)
1158                 goto out_unlock;
1159
1160         mutex_unlock(&dev->struct_mutex);
1161         drm_modeset_unlock_all(dev);
1162         i915_gem_object_put(new_bo);
1163
1164         return 0;
1165
1166 out_unlock:
1167         mutex_unlock(&dev->struct_mutex);
1168         drm_modeset_unlock_all(dev);
1169         i915_gem_object_put(new_bo);
1170
1171         return ret;
1172 }
1173
1174 static void update_reg_attrs(struct intel_overlay *overlay,
1175                              struct overlay_registers __iomem *regs)
1176 {
1177         iowrite32((overlay->contrast << 18) | (overlay->brightness & 0xff),
1178                   &regs->OCLRC0);
1179         iowrite32(overlay->saturation, &regs->OCLRC1);
1180 }
1181
1182 static bool check_gamma_bounds(u32 gamma1, u32 gamma2)
1183 {
1184         int i;
1185
1186         if (gamma1 & 0xff000000 || gamma2 & 0xff000000)
1187                 return false;
1188
1189         for (i = 0; i < 3; i++) {
1190                 if (((gamma1 >> i*8) & 0xff) >= ((gamma2 >> i*8) & 0xff))
1191                         return false;
1192         }
1193
1194         return true;
1195 }
1196
1197 static bool check_gamma5_errata(u32 gamma5)
1198 {
1199         int i;
1200
1201         for (i = 0; i < 3; i++) {
1202                 if (((gamma5 >> i*8) & 0xff) == 0x80)
1203                         return false;
1204         }
1205
1206         return true;
1207 }
1208
1209 static int check_gamma(struct drm_intel_overlay_attrs *attrs)
1210 {
1211         if (!check_gamma_bounds(0, attrs->gamma0) ||
1212             !check_gamma_bounds(attrs->gamma0, attrs->gamma1) ||
1213             !check_gamma_bounds(attrs->gamma1, attrs->gamma2) ||
1214             !check_gamma_bounds(attrs->gamma2, attrs->gamma3) ||
1215             !check_gamma_bounds(attrs->gamma3, attrs->gamma4) ||
1216             !check_gamma_bounds(attrs->gamma4, attrs->gamma5) ||
1217             !check_gamma_bounds(attrs->gamma5, 0x00ffffff))
1218                 return -EINVAL;
1219
1220         if (!check_gamma5_errata(attrs->gamma5))
1221                 return -EINVAL;
1222
1223         return 0;
1224 }
1225
1226 int intel_overlay_attrs_ioctl(struct drm_device *dev, void *data,
1227                               struct drm_file *file_priv)
1228 {
1229         struct drm_intel_overlay_attrs *attrs = data;
1230         struct drm_i915_private *dev_priv = to_i915(dev);
1231         struct intel_overlay *overlay;
1232         int ret;
1233
1234         overlay = dev_priv->overlay;
1235         if (!overlay) {
1236                 DRM_DEBUG("userspace bug: no overlay\n");
1237                 return -ENODEV;
1238         }
1239
1240         drm_modeset_lock_all(dev);
1241         mutex_lock(&dev->struct_mutex);
1242
1243         ret = -EINVAL;
1244         if (!(attrs->flags & I915_OVERLAY_UPDATE_ATTRS)) {
1245                 attrs->color_key  = overlay->color_key;
1246                 attrs->brightness = overlay->brightness;
1247                 attrs->contrast   = overlay->contrast;
1248                 attrs->saturation = overlay->saturation;
1249
1250                 if (!IS_GEN(dev_priv, 2)) {
1251                         attrs->gamma0 = I915_READ(OGAMC0);
1252                         attrs->gamma1 = I915_READ(OGAMC1);
1253                         attrs->gamma2 = I915_READ(OGAMC2);
1254                         attrs->gamma3 = I915_READ(OGAMC3);
1255                         attrs->gamma4 = I915_READ(OGAMC4);
1256                         attrs->gamma5 = I915_READ(OGAMC5);
1257                 }
1258         } else {
1259                 if (attrs->brightness < -128 || attrs->brightness > 127)
1260                         goto out_unlock;
1261                 if (attrs->contrast > 255)
1262                         goto out_unlock;
1263                 if (attrs->saturation > 1023)
1264                         goto out_unlock;
1265
1266                 overlay->color_key  = attrs->color_key;
1267                 overlay->brightness = attrs->brightness;
1268                 overlay->contrast   = attrs->contrast;
1269                 overlay->saturation = attrs->saturation;
1270
1271                 update_reg_attrs(overlay, overlay->regs);
1272
1273                 if (attrs->flags & I915_OVERLAY_UPDATE_GAMMA) {
1274                         if (IS_GEN(dev_priv, 2))
1275                                 goto out_unlock;
1276
1277                         if (overlay->active) {
1278                                 ret = -EBUSY;
1279                                 goto out_unlock;
1280                         }
1281
1282                         ret = check_gamma(attrs);
1283                         if (ret)
1284                                 goto out_unlock;
1285
1286                         I915_WRITE(OGAMC0, attrs->gamma0);
1287                         I915_WRITE(OGAMC1, attrs->gamma1);
1288                         I915_WRITE(OGAMC2, attrs->gamma2);
1289                         I915_WRITE(OGAMC3, attrs->gamma3);
1290                         I915_WRITE(OGAMC4, attrs->gamma4);
1291                         I915_WRITE(OGAMC5, attrs->gamma5);
1292                 }
1293         }
1294         overlay->color_key_enabled = (attrs->flags & I915_OVERLAY_DISABLE_DEST_COLORKEY) == 0;
1295
1296         ret = 0;
1297 out_unlock:
1298         mutex_unlock(&dev->struct_mutex);
1299         drm_modeset_unlock_all(dev);
1300
1301         return ret;
1302 }
1303
1304 static int get_registers(struct intel_overlay *overlay, bool use_phys)
1305 {
1306         struct drm_i915_gem_object *obj;
1307         struct i915_vma *vma;
1308         int err;
1309
1310         obj = i915_gem_object_create_stolen(overlay->i915, PAGE_SIZE);
1311         if (obj == NULL)
1312                 obj = i915_gem_object_create_internal(overlay->i915, PAGE_SIZE);
1313         if (IS_ERR(obj))
1314                 return PTR_ERR(obj);
1315
1316         vma = i915_gem_object_ggtt_pin(obj, NULL, 0, 0, PIN_MAPPABLE);
1317         if (IS_ERR(vma)) {
1318                 err = PTR_ERR(vma);
1319                 goto err_put_bo;
1320         }
1321
1322         if (use_phys)
1323                 overlay->flip_addr = sg_dma_address(obj->mm.pages->sgl);
1324         else
1325                 overlay->flip_addr = i915_ggtt_offset(vma);
1326         overlay->regs = i915_vma_pin_iomap(vma);
1327         i915_vma_unpin(vma);
1328
1329         if (IS_ERR(overlay->regs)) {
1330                 err = PTR_ERR(overlay->regs);
1331                 goto err_put_bo;
1332         }
1333
1334         overlay->reg_bo = obj;
1335         return 0;
1336
1337 err_put_bo:
1338         i915_gem_object_put(obj);
1339         return err;
1340 }
1341
1342 void intel_overlay_setup(struct drm_i915_private *dev_priv)
1343 {
1344         struct intel_overlay *overlay;
1345         int ret;
1346
1347         if (!HAS_OVERLAY(dev_priv))
1348                 return;
1349
1350         overlay = kzalloc(sizeof(*overlay), GFP_KERNEL);
1351         if (!overlay)
1352                 return;
1353
1354         overlay->i915 = dev_priv;
1355
1356         overlay->color_key = 0x0101fe;
1357         overlay->color_key_enabled = true;
1358         overlay->brightness = -19;
1359         overlay->contrast = 75;
1360         overlay->saturation = 146;
1361
1362         INIT_ACTIVE_REQUEST(&overlay->last_flip);
1363
1364         mutex_lock(&dev_priv->drm.struct_mutex);
1365
1366         ret = get_registers(overlay, OVERLAY_NEEDS_PHYSICAL(dev_priv));
1367         if (ret)
1368                 goto out_free;
1369
1370         ret = i915_gem_object_set_to_gtt_domain(overlay->reg_bo, true);
1371         if (ret)
1372                 goto out_reg_bo;
1373
1374         mutex_unlock(&dev_priv->drm.struct_mutex);
1375
1376         memset_io(overlay->regs, 0, sizeof(struct overlay_registers));
1377         update_polyphase_filter(overlay->regs);
1378         update_reg_attrs(overlay, overlay->regs);
1379
1380         dev_priv->overlay = overlay;
1381         DRM_INFO("Initialized overlay support.\n");
1382         return;
1383
1384 out_reg_bo:
1385         i915_gem_object_put(overlay->reg_bo);
1386 out_free:
1387         mutex_unlock(&dev_priv->drm.struct_mutex);
1388         kfree(overlay);
1389 }
1390
1391 void intel_overlay_cleanup(struct drm_i915_private *dev_priv)
1392 {
1393         struct intel_overlay *overlay;
1394
1395         overlay = fetch_and_zero(&dev_priv->overlay);
1396         if (!overlay)
1397                 return;
1398
1399         /*
1400          * The bo's should be free'd by the generic code already.
1401          * Furthermore modesetting teardown happens beforehand so the
1402          * hardware should be off already.
1403          */
1404         WARN_ON(overlay->active);
1405
1406         i915_gem_object_put(overlay->reg_bo);
1407
1408         kfree(overlay);
1409 }
1410
1411 #if IS_ENABLED(CONFIG_DRM_I915_CAPTURE_ERROR)
1412
1413 struct intel_overlay_error_state {
1414         struct overlay_registers regs;
1415         unsigned long base;
1416         u32 dovsta;
1417         u32 isr;
1418 };
1419
1420 struct intel_overlay_error_state *
1421 intel_overlay_capture_error_state(struct drm_i915_private *dev_priv)
1422 {
1423         struct intel_overlay *overlay = dev_priv->overlay;
1424         struct intel_overlay_error_state *error;
1425
1426         if (!overlay || !overlay->active)
1427                 return NULL;
1428
1429         error = kmalloc(sizeof(*error), GFP_ATOMIC);
1430         if (error == NULL)
1431                 return NULL;
1432
1433         error->dovsta = I915_READ(DOVSTA);
1434         error->isr = I915_READ(GEN2_ISR);
1435         error->base = overlay->flip_addr;
1436
1437         memcpy_fromio(&error->regs, overlay->regs, sizeof(error->regs));
1438
1439         return error;
1440 }
1441
1442 void
1443 intel_overlay_print_error_state(struct drm_i915_error_state_buf *m,
1444                                 struct intel_overlay_error_state *error)
1445 {
1446         i915_error_printf(m, "Overlay, status: 0x%08x, interrupt: 0x%08x\n",
1447                           error->dovsta, error->isr);
1448         i915_error_printf(m, "  Register file at 0x%08lx:\n",
1449                           error->base);
1450
1451 #define P(x) i915_error_printf(m, "    " #x ":  0x%08x\n", error->regs.x)
1452         P(OBUF_0Y);
1453         P(OBUF_1Y);
1454         P(OBUF_0U);
1455         P(OBUF_0V);
1456         P(OBUF_1U);
1457         P(OBUF_1V);
1458         P(OSTRIDE);
1459         P(YRGB_VPH);
1460         P(UV_VPH);
1461         P(HORZ_PH);
1462         P(INIT_PHS);
1463         P(DWINPOS);
1464         P(DWINSZ);
1465         P(SWIDTH);
1466         P(SWIDTHSW);
1467         P(SHEIGHT);
1468         P(YRGBSCALE);
1469         P(UVSCALE);
1470         P(OCLRC0);
1471         P(OCLRC1);
1472         P(DCLRKV);
1473         P(DCLRKM);
1474         P(SCLRKVH);
1475         P(SCLRKVL);
1476         P(SCLRKEN);
1477         P(OCONFIG);
1478         P(OCMD);
1479         P(OSTART_0Y);
1480         P(OSTART_1Y);
1481         P(OSTART_0U);
1482         P(OSTART_0V);
1483         P(OSTART_1U);
1484         P(OSTART_1V);
1485         P(OTILEOFF_0Y);
1486         P(OTILEOFF_1Y);
1487         P(OTILEOFF_0U);
1488         P(OTILEOFF_0V);
1489         P(OTILEOFF_1U);
1490         P(OTILEOFF_1V);
1491         P(FASTHSCALE);
1492         P(UVSCALEV);
1493 #undef P
1494 }
1495
1496 #endif