drivers/gpu/drm/i915/intel_fbc.c

   1 /*
   2  * Copyright © 2014 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  21  * DEALINGS IN THE SOFTWARE.
  22  */
  23
  24 /**
  25  * DOC: Frame Buffer Compression (FBC)
  26  *
  27  * FBC tries to save memory bandwidth (and so power consumption) by
  28  * compressing the amount of memory used by the display. It is total
  29  * transparent to user space and completely handled in the kernel.
  30  *
  31  * The benefits of FBC are mostly visible with solid backgrounds and
  32  * variation-less patterns. It comes from keeping the memory footprint small
  33  * and having fewer memory pages opened and accessed for refreshing the display.
  34  *
  35  * i915 is responsible to reserve stolen memory for FBC and configure its
  36  * offset on proper registers. The hardware takes care of all
  37  * compress/decompress. However there are many known cases where we have to
  38  * forcibly disable it to allow proper screen updates.
  39  */
  40
  41 #include <drm/drm_fourcc.h>
  42
  43 #include "i915_drv.h"
  44 #include "intel_drv.h"
  45 #include "intel_fbc.h"
  46 #include "intel_frontbuffer.h"
  47
  48 static inline bool fbc_supported(struct drm_i915_private *dev_priv)
  49 {
  50         return HAS_FBC(dev_priv);
  51 }
  52
  53 static inline bool no_fbc_on_multiple_pipes(struct drm_i915_private *dev_priv)
  54 {
  55         return INTEL_GEN(dev_priv) <= 3;
  56 }
  57
  58 /*
  59  * In some platforms where the CRTC's x:0/y:0 coordinates doesn't match the
  60  * frontbuffer's x:0/y:0 coordinates we lie to the hardware about the plane's
  61  * origin so the x and y offsets can actually fit the registers. As a
  62  * consequence, the fence doesn't really start exactly at the display plane
  63  * address we program because it starts at the real start of the buffer, so we
  64  * have to take this into consideration here.
  65  */
  66 static unsigned int get_crtc_fence_y_offset(struct intel_fbc *fbc)
  67 {
  68         return fbc->state_cache.plane.y - fbc->state_cache.plane.adjusted_y;
  69 }
  70
  71 /*
  72  * For SKL+, the plane source size used by the hardware is based on the value we
  73  * write to the PLANE_SIZE register. For BDW-, the hardware looks at the value
  74  * we wrote to PIPESRC.
  75  */
  76 static void intel_fbc_get_plane_source_size(struct intel_fbc_state_cache *cache,
  77                                             int *width, int *height)
  78 {
  79         if (width)
  80                 *width = cache->plane.src_w;
  81         if (height)
  82                 *height = cache->plane.src_h;
  83 }
  84
  85 static int intel_fbc_calculate_cfb_size(struct drm_i915_private *dev_priv,
  86                                         struct intel_fbc_state_cache *cache)
  87 {
  88         int lines;
  89
  90         intel_fbc_get_plane_source_size(cache, NULL, &lines);
  91         if (IS_GEN(dev_priv, 7))
  92                 lines = min(lines, 2048);
  93         else if (INTEL_GEN(dev_priv) >= 8)
  94                 lines = min(lines, 2560);
  95
  96         /* Hardware needs the full buffer stride, not just the active area. */
  97         return lines * cache->fb.stride;
  98 }
  99
 100 static void i8xx_fbc_deactivate(struct drm_i915_private *dev_priv)
 101 {
 102         u32 fbc_ctl;
 103
 104         /* Disable compression */
 105         fbc_ctl = I915_READ(FBC_CONTROL);
 106         if ((fbc_ctl & FBC_CTL_EN) == 0)
 107                 return;
 108
 109         fbc_ctl &= ~FBC_CTL_EN;
 110         I915_WRITE(FBC_CONTROL, fbc_ctl);
 111
 112         /* Wait for compressing bit to clear */
 113         if (intel_wait_for_register(&dev_priv->uncore,
 114                                     FBC_STATUS, FBC_STAT_COMPRESSING, 0,
 115                                     10)) {
 116                 DRM_DEBUG_KMS("FBC idle timed out\n");
 117                 return;
 118         }
 119 }
 120
 121 static void i8xx_fbc_activate(struct drm_i915_private *dev_priv)
 122 {
 123         struct intel_fbc_reg_params *params = &dev_priv->fbc.params;
 124         int cfb_pitch;
 125         int i;
 126         u32 fbc_ctl;
 127
 128         /* Note: fbc.threshold == 1 for i8xx */
 129         cfb_pitch = params->cfb_size / FBC_LL_SIZE;
 130         if (params->fb.stride < cfb_pitch)
 131                 cfb_pitch = params->fb.stride;
 132
 133         /* FBC_CTL wants 32B or 64B units */
 134         if (IS_GEN(dev_priv, 2))
 135                 cfb_pitch = (cfb_pitch / 32) - 1;
 136         else
 137                 cfb_pitch = (cfb_pitch / 64) - 1;
 138
 139         /* Clear old tags */
 140         for (i = 0; i < (FBC_LL_SIZE / 32) + 1; i++)
 141                 I915_WRITE(FBC_TAG(i), 0);
 142
 143         if (IS_GEN(dev_priv, 4)) {
 144                 u32 fbc_ctl2;
 145
 146                 /* Set it up... */
 147                 fbc_ctl2 = FBC_CTL_FENCE_DBL | FBC_CTL_IDLE_IMM | FBC_CTL_CPU_FENCE;
 148                 fbc_ctl2 |= FBC_CTL_PLANE(params->crtc.i9xx_plane);
 149                 I915_WRITE(FBC_CONTROL2, fbc_ctl2);
 150                 I915_WRITE(FBC_FENCE_OFF, params->crtc.fence_y_offset);
 151         }
 152
 153         /* enable it... */
 154         fbc_ctl = I915_READ(FBC_CONTROL);
 155         fbc_ctl &= 0x3fff << FBC_CTL_INTERVAL_SHIFT;
 156         fbc_ctl |= FBC_CTL_EN | FBC_CTL_PERIODIC;
 157         if (IS_I945GM(dev_priv))
 158                 fbc_ctl |= FBC_CTL_C3_IDLE; /* 945 needs special SR handling */
 159         fbc_ctl |= (cfb_pitch & 0xff) << FBC_CTL_STRIDE_SHIFT;
 160         fbc_ctl |= params->vma->fence->id;
 161         I915_WRITE(FBC_CONTROL, fbc_ctl);
 162 }
 163
 164 static bool i8xx_fbc_is_active(struct drm_i915_private *dev_priv)
 165 {
 166         return I915_READ(FBC_CONTROL) & FBC_CTL_EN;
 167 }
 168
 169 static void g4x_fbc_activate(struct drm_i915_private *dev_priv)
 170 {
 171         struct intel_fbc_reg_params *params = &dev_priv->fbc.params;
 172         u32 dpfc_ctl;
 173
 174         dpfc_ctl = DPFC_CTL_PLANE(params->crtc.i9xx_plane) | DPFC_SR_EN;
 175         if (params->fb.format->cpp[0] == 2)
 176                 dpfc_ctl |= DPFC_CTL_LIMIT_2X;
 177         else
 178                 dpfc_ctl |= DPFC_CTL_LIMIT_1X;
 179
 180         if (params->flags & PLANE_HAS_FENCE) {
 181                 dpfc_ctl |= DPFC_CTL_FENCE_EN | params->vma->fence->id;
 182                 I915_WRITE(DPFC_FENCE_YOFF, params->crtc.fence_y_offset);
 183         } else {
 184                 I915_WRITE(DPFC_FENCE_YOFF, 0);
 185         }
 186
 187         /* enable it... */
 188         I915_WRITE(DPFC_CONTROL, dpfc_ctl | DPFC_CTL_EN);
 189 }
 190
 191 static void g4x_fbc_deactivate(struct drm_i915_private *dev_priv)
 192 {
 193         u32 dpfc_ctl;
 194
 195         /* Disable compression */
 196         dpfc_ctl = I915_READ(DPFC_CONTROL);
 197         if (dpfc_ctl & DPFC_CTL_EN) {
 198                 dpfc_ctl &= ~DPFC_CTL_EN;
 199                 I915_WRITE(DPFC_CONTROL, dpfc_ctl);
 200         }
 201 }
 202
 203 static bool g4x_fbc_is_active(struct drm_i915_private *dev_priv)
 204 {
 205         return I915_READ(DPFC_CONTROL) & DPFC_CTL_EN;
 206 }
 207
 208 /* This function forces a CFB recompression through the nuke operation. */
 209 static void intel_fbc_recompress(struct drm_i915_private *dev_priv)
 210 {
 211         I915_WRITE(MSG_FBC_REND_STATE, FBC_REND_NUKE);
 212         POSTING_READ(MSG_FBC_REND_STATE);
 213 }
 214
 215 static void ilk_fbc_activate(struct drm_i915_private *dev_priv)
 216 {
 217         struct intel_fbc_reg_params *params = &dev_priv->fbc.params;
 218         u32 dpfc_ctl;
 219         int threshold = dev_priv->fbc.threshold;
 220
 221         dpfc_ctl = DPFC_CTL_PLANE(params->crtc.i9xx_plane);
 222         if (params->fb.format->cpp[0] == 2)
 223                 threshold++;
 224
 225         switch (threshold) {
 226         case 4:
 227         case 3:
 228                 dpfc_ctl |= DPFC_CTL_LIMIT_4X;
 229                 break;
 230         case 2:
 231                 dpfc_ctl |= DPFC_CTL_LIMIT_2X;
 232                 break;
 233         case 1:
 234                 dpfc_ctl |= DPFC_CTL_LIMIT_1X;
 235                 break;
 236         }
 237
 238         if (params->flags & PLANE_HAS_FENCE) {
 239                 dpfc_ctl |= DPFC_CTL_FENCE_EN;
 240                 if (IS_GEN(dev_priv, 5))
 241                         dpfc_ctl |= params->vma->fence->id;
 242                 if (IS_GEN(dev_priv, 6)) {
 243                         I915_WRITE(SNB_DPFC_CTL_SA,
 244                                    SNB_CPU_FENCE_ENABLE |
 245                                    params->vma->fence->id);
 246                         I915_WRITE(DPFC_CPU_FENCE_OFFSET,
 247                                    params->crtc.fence_y_offset);
 248                 }
 249         } else {
 250                 if (IS_GEN(dev_priv, 6)) {
 251                         I915_WRITE(SNB_DPFC_CTL_SA, 0);
 252                         I915_WRITE(DPFC_CPU_FENCE_OFFSET, 0);
 253                 }
 254         }
 255
 256         I915_WRITE(ILK_DPFC_FENCE_YOFF, params->crtc.fence_y_offset);
 257         I915_WRITE(ILK_FBC_RT_BASE,
 258                    i915_ggtt_offset(params->vma) | ILK_FBC_RT_VALID);
 259         /* enable it... */
 260         I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl | DPFC_CTL_EN);
 261
 262         intel_fbc_recompress(dev_priv);
 263 }
 264
 265 static void ilk_fbc_deactivate(struct drm_i915_private *dev_priv)
 266 {
 267         u32 dpfc_ctl;
 268
 269         /* Disable compression */
 270         dpfc_ctl = I915_READ(ILK_DPFC_CONTROL);
 271         if (dpfc_ctl & DPFC_CTL_EN) {
 272                 dpfc_ctl &= ~DPFC_CTL_EN;
 273                 I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl);
 274         }
 275 }
 276
 277 static bool ilk_fbc_is_active(struct drm_i915_private *dev_priv)
 278 {
 279         return I915_READ(ILK_DPFC_CONTROL) & DPFC_CTL_EN;
 280 }
 281
 282 static void gen7_fbc_activate(struct drm_i915_private *dev_priv)
 283 {
 284         struct intel_fbc_reg_params *params = &dev_priv->fbc.params;
 285         u32 dpfc_ctl;
 286         int threshold = dev_priv->fbc.threshold;
 287
 288         /* Display WA #0529: skl, kbl, bxt. */
 289         if (IS_GEN(dev_priv, 9) && !IS_GEMINILAKE(dev_priv)) {
 290                 u32 val = I915_READ(CHICKEN_MISC_4);
 291
 292                 val &= ~(FBC_STRIDE_OVERRIDE | FBC_STRIDE_MASK);
 293
 294                 if (i915_gem_object_get_tiling(params->vma->obj) !=
 295                     I915_TILING_X)
 296                         val |= FBC_STRIDE_OVERRIDE | params->gen9_wa_cfb_stride;
 297
 298                 I915_WRITE(CHICKEN_MISC_4, val);
 299         }
 300
 301         dpfc_ctl = 0;
 302         if (IS_IVYBRIDGE(dev_priv))
 303                 dpfc_ctl |= IVB_DPFC_CTL_PLANE(params->crtc.i9xx_plane);
 304
 305         if (params->fb.format->cpp[0] == 2)
 306                 threshold++;
 307
 308         switch (threshold) {
 309         case 4:
 310         case 3:
 311                 dpfc_ctl |= DPFC_CTL_LIMIT_4X;
 312                 break;
 313         case 2:
 314                 dpfc_ctl |= DPFC_CTL_LIMIT_2X;
 315                 break;
 316         case 1:
 317                 dpfc_ctl |= DPFC_CTL_LIMIT_1X;
 318                 break;
 319         }
 320
 321         if (params->flags & PLANE_HAS_FENCE) {
 322                 dpfc_ctl |= IVB_DPFC_CTL_FENCE_EN;
 323                 I915_WRITE(SNB_DPFC_CTL_SA,
 324                            SNB_CPU_FENCE_ENABLE |
 325                            params->vma->fence->id);
 326                 I915_WRITE(DPFC_CPU_FENCE_OFFSET, params->crtc.fence_y_offset);
 327         } else {
 328                 I915_WRITE(SNB_DPFC_CTL_SA,0);
 329                 I915_WRITE(DPFC_CPU_FENCE_OFFSET, 0);
 330         }
 331
 332         if (dev_priv->fbc.false_color)
 333                 dpfc_ctl |= FBC_CTL_FALSE_COLOR;
 334
 335         if (IS_IVYBRIDGE(dev_priv)) {
 336                 /* WaFbcAsynchFlipDisableFbcQueue:ivb */
 337                 I915_WRITE(ILK_DISPLAY_CHICKEN1,
 338                            I915_READ(ILK_DISPLAY_CHICKEN1) |
 339                            ILK_FBCQ_DIS);
 340         } else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
 341                 /* WaFbcAsynchFlipDisableFbcQueue:hsw,bdw */
 342                 I915_WRITE(CHICKEN_PIPESL_1(params->crtc.pipe),
 343                            I915_READ(CHICKEN_PIPESL_1(params->crtc.pipe)) |
 344                            HSW_FBCQ_DIS);
 345         }
 346
 347         I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl | DPFC_CTL_EN);
 348
 349         intel_fbc_recompress(dev_priv);
 350 }
 351
 352 static bool intel_fbc_hw_is_active(struct drm_i915_private *dev_priv)
 353 {
 354         if (INTEL_GEN(dev_priv) >= 5)
 355                 return ilk_fbc_is_active(dev_priv);
 356         else if (IS_GM45(dev_priv))
 357                 return g4x_fbc_is_active(dev_priv);
 358         else
 359                 return i8xx_fbc_is_active(dev_priv);
 360 }
 361
 362 static void intel_fbc_hw_activate(struct drm_i915_private *dev_priv)
 363 {
 364         struct intel_fbc *fbc = &dev_priv->fbc;
 365
 366         fbc->active = true;
 367
 368         if (INTEL_GEN(dev_priv) >= 7)
 369                 gen7_fbc_activate(dev_priv);
 370         else if (INTEL_GEN(dev_priv) >= 5)
 371                 ilk_fbc_activate(dev_priv);
 372         else if (IS_GM45(dev_priv))
 373                 g4x_fbc_activate(dev_priv);
 374         else
 375                 i8xx_fbc_activate(dev_priv);
 376 }
 377
 378 static void intel_fbc_hw_deactivate(struct drm_i915_private *dev_priv)
 379 {
 380         struct intel_fbc *fbc = &dev_priv->fbc;
 381
 382         fbc->active = false;
 383
 384         if (INTEL_GEN(dev_priv) >= 5)
 385                 ilk_fbc_deactivate(dev_priv);
 386         else if (IS_GM45(dev_priv))
 387                 g4x_fbc_deactivate(dev_priv);
 388         else
 389                 i8xx_fbc_deactivate(dev_priv);
 390 }
 391
 392 /**
 393  * intel_fbc_is_active - Is FBC active?
 394  * @dev_priv: i915 device instance
 395  *
 396  * This function is used to verify the current state of FBC.
 397  *
 398  * FIXME: This should be tracked in the plane config eventually
 399  * instead of queried at runtime for most callers.
 400  */
 401 bool intel_fbc_is_active(struct drm_i915_private *dev_priv)
 402 {
 403         return dev_priv->fbc.active;
 404 }
 405
 406 static void intel_fbc_deactivate(struct drm_i915_private *dev_priv,
 407                                  const char *reason)
 408 {
 409         struct intel_fbc *fbc = &dev_priv->fbc;
 410
 411         WARN_ON(!mutex_is_locked(&fbc->lock));
 412
 413         if (fbc->active)
 414                 intel_fbc_hw_deactivate(dev_priv);
 415
 416         fbc->no_fbc_reason = reason;
 417 }
 418
 419 static bool multiple_pipes_ok(struct intel_crtc *crtc,
 420                               struct intel_plane_state *plane_state)
 421 {
 422         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 423         struct intel_fbc *fbc = &dev_priv->fbc;
 424         enum pipe pipe = crtc->pipe;
 425
 426         /* Don't even bother tracking anything we don't need. */
 427         if (!no_fbc_on_multiple_pipes(dev_priv))
 428                 return true;
 429
 430         if (plane_state->base.visible)
 431                 fbc->visible_pipes_mask |= (1 << pipe);
 432         else
 433                 fbc->visible_pipes_mask &= ~(1 << pipe);
 434
 435         return (fbc->visible_pipes_mask & ~(1 << pipe)) != 0;
 436 }
 437
 438 static int find_compression_threshold(struct drm_i915_private *dev_priv,
 439                                       struct drm_mm_node *node,
 440                                       int size,
 441                                       int fb_cpp)
 442 {
 443         int compression_threshold = 1;
 444         int ret;
 445         u64 end;
 446
 447         /* The FBC hardware for BDW/SKL doesn't have access to the stolen
 448          * reserved range size, so it always assumes the maximum (8mb) is used.
 449          * If we enable FBC using a CFB on that memory range we'll get FIFO
 450          * underruns, even if that range is not reserved by the BIOS. */
 451         if (IS_BROADWELL(dev_priv) || IS_GEN9_BC(dev_priv))
 452                 end = resource_size(&dev_priv->dsm) - 8 * 1024 * 1024;
 453         else
 454                 end = U64_MAX;
 455
 456         /* HACK: This code depends on what we will do in *_enable_fbc. If that
 457          * code changes, this code needs to change as well.
 458          *
 459          * The enable_fbc code will attempt to use one of our 2 compression
 460          * thresholds, therefore, in that case, we only have 1 resort.
 461          */
 462
 463         /* Try to over-allocate to reduce reallocations and fragmentation. */
 464         ret = i915_gem_stolen_insert_node_in_range(dev_priv, node, size <<= 1,
 465                                                    4096, 0, end);
 466         if (ret == 0)
 467                 return compression_threshold;
 468
 469 again:
 470         /* HW's ability to limit the CFB is 1:4 */
 471         if (compression_threshold > 4 ||
 472             (fb_cpp == 2 && compression_threshold == 2))
 473                 return 0;
 474
 475         ret = i915_gem_stolen_insert_node_in_range(dev_priv, node, size >>= 1,
 476                                                    4096, 0, end);
 477         if (ret && INTEL_GEN(dev_priv) <= 4) {
 478                 return 0;
 479         } else if (ret) {
 480                 compression_threshold <<= 1;
 481                 goto again;
 482         } else {
 483                 return compression_threshold;
 484         }
 485 }
 486
 487 static int intel_fbc_alloc_cfb(struct intel_crtc *crtc)
 488 {
 489         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 490         struct intel_fbc *fbc = &dev_priv->fbc;
 491         struct drm_mm_node *uninitialized_var(compressed_llb);
 492         int size, fb_cpp, ret;
 493
 494         WARN_ON(drm_mm_node_allocated(&fbc->compressed_fb));
 495
 496         size = intel_fbc_calculate_cfb_size(dev_priv, &fbc->state_cache);
 497         fb_cpp = fbc->state_cache.fb.format->cpp[0];
 498
 499         ret = find_compression_threshold(dev_priv, &fbc->compressed_fb,
 500                                          size, fb_cpp);
 501         if (!ret)
 502                 goto err_llb;
 503         else if (ret > 1) {
 504                 DRM_INFO("Reducing the compressed framebuffer size. This may lead to less power savings than a non-reduced-size. Try to increase stolen memory size if available in BIOS.\n");
 505
 506         }
 507
 508         fbc->threshold = ret;
 509
 510         if (INTEL_GEN(dev_priv) >= 5)
 511                 I915_WRITE(ILK_DPFC_CB_BASE, fbc->compressed_fb.start);
 512         else if (IS_GM45(dev_priv)) {
 513                 I915_WRITE(DPFC_CB_BASE, fbc->compressed_fb.start);
 514         } else {
 515                 compressed_llb = kzalloc(sizeof(*compressed_llb), GFP_KERNEL);
 516                 if (!compressed_llb)
 517                         goto err_fb;
 518
 519                 ret = i915_gem_stolen_insert_node(dev_priv, compressed_llb,
 520                                                   4096, 4096);
 521                 if (ret)
 522                         goto err_fb;
 523
 524                 fbc->compressed_llb = compressed_llb;
 525
 526                 GEM_BUG_ON(range_overflows_t(u64, dev_priv->dsm.start,
 527                                              fbc->compressed_fb.start,
 528                                              U32_MAX));
 529                 GEM_BUG_ON(range_overflows_t(u64, dev_priv->dsm.start,
 530                                              fbc->compressed_llb->start,
 531                                              U32_MAX));
 532                 I915_WRITE(FBC_CFB_BASE,
 533                            dev_priv->dsm.start + fbc->compressed_fb.start);
 534                 I915_WRITE(FBC_LL_BASE,
 535                            dev_priv->dsm.start + compressed_llb->start);
 536         }
 537
 538         DRM_DEBUG_KMS("reserved %llu bytes of contiguous stolen space for FBC, threshold: %d\n",
 539                       fbc->compressed_fb.size, fbc->threshold);
 540
 541         return 0;
 542
 543 err_fb:
 544         kfree(compressed_llb);
 545         i915_gem_stolen_remove_node(dev_priv, &fbc->compressed_fb);
 546 err_llb:
 547         if (drm_mm_initialized(&dev_priv->mm.stolen))
 548                 pr_info_once("drm: not enough stolen space for compressed buffer (need %d more bytes), disabling. Hint: you may be able to increase stolen memory size in the BIOS to avoid this.\n", size);
 549         return -ENOSPC;
 550 }
 551
 552 static void __intel_fbc_cleanup_cfb(struct drm_i915_private *dev_priv)
 553 {
 554         struct intel_fbc *fbc = &dev_priv->fbc;
 555
 556         if (drm_mm_node_allocated(&fbc->compressed_fb))
 557                 i915_gem_stolen_remove_node(dev_priv, &fbc->compressed_fb);
 558
 559         if (fbc->compressed_llb) {
 560                 i915_gem_stolen_remove_node(dev_priv, fbc->compressed_llb);
 561                 kfree(fbc->compressed_llb);
 562         }
 563 }
 564
 565 void intel_fbc_cleanup_cfb(struct drm_i915_private *dev_priv)
 566 {
 567         struct intel_fbc *fbc = &dev_priv->fbc;
 568
 569         if (!fbc_supported(dev_priv))
 570                 return;
 571
 572         mutex_lock(&fbc->lock);
 573         __intel_fbc_cleanup_cfb(dev_priv);
 574         mutex_unlock(&fbc->lock);
 575 }
 576
 577 static bool stride_is_valid(struct drm_i915_private *dev_priv,
 578                             unsigned int stride)
 579 {
 580         /* This should have been caught earlier. */
 581         if (WARN_ON_ONCE((stride & (64 - 1)) != 0))
 582                 return false;
 583
 584         /* Below are the additional FBC restrictions. */
 585         if (stride < 512)
 586                 return false;
 587
 588         if (IS_GEN(dev_priv, 2) || IS_GEN(dev_priv, 3))
 589                 return stride == 4096 || stride == 8192;
 590
 591         if (IS_GEN(dev_priv, 4) && !IS_G4X(dev_priv) && stride < 2048)
 592                 return false;
 593
 594         if (stride > 16384)
 595                 return false;
 596
 597         return true;
 598 }
 599
 600 static bool pixel_format_is_valid(struct drm_i915_private *dev_priv,
 601                                   u32 pixel_format)
 602 {
 603         switch (pixel_format) {
 604         case DRM_FORMAT_XRGB8888:
 605         case DRM_FORMAT_XBGR8888:
 606                 return true;
 607         case DRM_FORMAT_XRGB1555:
 608         case DRM_FORMAT_RGB565:
 609                 /* 16bpp not supported on gen2 */
 610                 if (IS_GEN(dev_priv, 2))
 611                         return false;
 612                 /* WaFbcOnly1to1Ratio:ctg */
 613                 if (IS_G4X(dev_priv))
 614                         return false;
 615                 return true;
 616         default:
 617                 return false;
 618         }
 619 }
 620
 621 /*
 622  * For some reason, the hardware tracking starts looking at whatever we
 623  * programmed as the display plane base address register. It does not look at
 624  * the X and Y offset registers. That's why we look at the crtc->adjusted{x,y}
 625  * variables instead of just looking at the pipe/plane size.
 626  */
 627 static bool intel_fbc_hw_tracking_covers_screen(struct intel_crtc *crtc)
 628 {
 629         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 630         struct intel_fbc *fbc = &dev_priv->fbc;
 631         unsigned int effective_w, effective_h, max_w, max_h;
 632
 633         if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv)) {
 634                 max_w = 5120;
 635                 max_h = 4096;
 636         } else if (INTEL_GEN(dev_priv) >= 8 || IS_HASWELL(dev_priv)) {
 637                 max_w = 4096;
 638                 max_h = 4096;
 639         } else if (IS_G4X(dev_priv) || INTEL_GEN(dev_priv) >= 5) {
 640                 max_w = 4096;
 641                 max_h = 2048;
 642         } else {
 643                 max_w = 2048;
 644                 max_h = 1536;
 645         }
 646
 647         intel_fbc_get_plane_source_size(&fbc->state_cache, &effective_w,
 648                                         &effective_h);
 649         effective_w += fbc->state_cache.plane.adjusted_x;
 650         effective_h += fbc->state_cache.plane.adjusted_y;
 651
 652         return effective_w <= max_w && effective_h <= max_h;
 653 }
 654
 655 static void intel_fbc_update_state_cache(struct intel_crtc *crtc,
 656                                          struct intel_crtc_state *crtc_state,
 657                                          struct intel_plane_state *plane_state)
 658 {
 659         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 660         struct intel_fbc *fbc = &dev_priv->fbc;
 661         struct intel_fbc_state_cache *cache = &fbc->state_cache;
 662         struct drm_framebuffer *fb = plane_state->base.fb;
 663
 664         cache->vma = NULL;
 665         cache->flags = 0;
 666
 667         cache->crtc.mode_flags = crtc_state->base.adjusted_mode.flags;
 668         if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
 669                 cache->crtc.hsw_bdw_pixel_rate = crtc_state->pixel_rate;
 670
 671         cache->plane.rotation = plane_state->base.rotation;
 672         /*
 673          * Src coordinates are already rotated by 270 degrees for
 674          * the 90/270 degree plane rotation cases (to match the
 675          * GTT mapping), hence no need to account for rotation here.
 676          */
 677         cache->plane.src_w = drm_rect_width(&plane_state->base.src) >> 16;
 678         cache->plane.src_h = drm_rect_height(&plane_state->base.src) >> 16;
 679         cache->plane.visible = plane_state->base.visible;
 680         cache->plane.adjusted_x = plane_state->color_plane[0].x;
 681         cache->plane.adjusted_y = plane_state->color_plane[0].y;
 682         cache->plane.y = plane_state->base.src.y1 >> 16;
 683
 684         cache->plane.pixel_blend_mode = plane_state->base.pixel_blend_mode;
 685
 686         if (!cache->plane.visible)
 687                 return;
 688
 689         cache->fb.format = fb->format;
 690         cache->fb.stride = fb->pitches[0];
 691
 692         cache->vma = plane_state->vma;
 693         cache->flags = plane_state->flags;
 694         if (WARN_ON(cache->flags & PLANE_HAS_FENCE && !cache->vma->fence))
 695                 cache->flags &= ~PLANE_HAS_FENCE;
 696 }
 697
 698 static bool intel_fbc_can_activate(struct intel_crtc *crtc)
 699 {
 700         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 701         struct intel_fbc *fbc = &dev_priv->fbc;
 702         struct intel_fbc_state_cache *cache = &fbc->state_cache;
 703
 704         /* We don't need to use a state cache here since this information is
 705          * global for all CRTC.
 706          */
 707         if (fbc->underrun_detected) {
 708                 fbc->no_fbc_reason = "underrun detected";
 709                 return false;
 710         }
 711
 712         if (!cache->vma) {
 713                 fbc->no_fbc_reason = "primary plane not visible";
 714                 return false;
 715         }
 716
 717         if (cache->crtc.mode_flags & DRM_MODE_FLAG_INTERLACE) {
 718                 fbc->no_fbc_reason = "incompatible mode";
 719                 return false;
 720         }
 721
 722         if (!intel_fbc_hw_tracking_covers_screen(crtc)) {
 723                 fbc->no_fbc_reason = "mode too large for compression";
 724                 return false;
 725         }
 726
 727         /* The use of a CPU fence is mandatory in order to detect writes
 728          * by the CPU to the scanout and trigger updates to the FBC.
 729          *
 730          * Note that is possible for a tiled surface to be unmappable (and
 731          * so have no fence associated with it) due to aperture constaints
 732          * at the time of pinning.
 733          *
 734          * FIXME with 90/270 degree rotation we should use the fence on
 735          * the normal GTT view (the rotated view doesn't even have a
 736          * fence). Would need changes to the FBC fence Y offset as well.
 737          * For now this will effecively disable FBC with 90/270 degree
 738          * rotation.
 739          */
 740         if (!(cache->flags & PLANE_HAS_FENCE)) {
 741                 fbc->no_fbc_reason = "framebuffer not tiled or fenced";
 742                 return false;
 743         }
 744         if (INTEL_GEN(dev_priv) <= 4 && !IS_G4X(dev_priv) &&
 745             cache->plane.rotation != DRM_MODE_ROTATE_0) {
 746                 fbc->no_fbc_reason = "rotation unsupported";
 747                 return false;
 748         }
 749
 750         if (!stride_is_valid(dev_priv, cache->fb.stride)) {
 751                 fbc->no_fbc_reason = "framebuffer stride not supported";
 752                 return false;
 753         }
 754
 755         if (!pixel_format_is_valid(dev_priv, cache->fb.format->format)) {
 756                 fbc->no_fbc_reason = "pixel format is invalid";
 757                 return false;
 758         }
 759
 760         if (cache->plane.pixel_blend_mode != DRM_MODE_BLEND_PIXEL_NONE &&
 761             cache->fb.format->has_alpha) {
 762                 fbc->no_fbc_reason = "per-pixel alpha blending is incompatible with FBC";
 763                 return false;
 764         }
 765
 766         /* WaFbcExceedCdClockThreshold:hsw,bdw */
 767         if ((IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) &&
 768             cache->crtc.hsw_bdw_pixel_rate >= dev_priv->cdclk.hw.cdclk * 95 / 100) {
 769                 fbc->no_fbc_reason = "pixel rate is too big";
 770                 return false;
 771         }
 772
 773         /* It is possible for the required CFB size change without a
 774          * crtc->disable + crtc->enable since it is possible to change the
 775          * stride without triggering a full modeset. Since we try to
 776          * over-allocate the CFB, there's a chance we may keep FBC enabled even
 777          * if this happens, but if we exceed the current CFB size we'll have to
 778          * disable FBC. Notice that it would be possible to disable FBC, wait
 779          * for a frame, free the stolen node, then try to reenable FBC in case
 780          * we didn't get any invalidate/deactivate calls, but this would require
 781          * a lot of tracking just for a specific case. If we conclude it's an
 782          * important case, we can implement it later. */
 783         if (intel_fbc_calculate_cfb_size(dev_priv, &fbc->state_cache) >
 784             fbc->compressed_fb.size * fbc->threshold) {
 785                 fbc->no_fbc_reason = "CFB requirements changed";
 786                 return false;
 787         }
 788
 789         /*
 790          * Work around a problem on GEN9+ HW, where enabling FBC on a plane
 791          * having a Y offset that isn't divisible by 4 causes FIFO underrun
 792          * and screen flicker.
 793          */
 794         if (IS_GEN_RANGE(dev_priv, 9, 10) &&
 795             (fbc->state_cache.plane.adjusted_y & 3)) {
 796                 fbc->no_fbc_reason = "plane Y offset is misaligned";
 797                 return false;
 798         }
 799
 800         return true;
 801 }
 802
 803 static bool intel_fbc_can_enable(struct drm_i915_private *dev_priv)
 804 {
 805         struct intel_fbc *fbc = &dev_priv->fbc;
 806
 807         if (intel_vgpu_active(dev_priv)) {
 808                 fbc->no_fbc_reason = "VGPU is active";
 809                 return false;
 810         }
 811
 812         if (!i915_modparams.enable_fbc) {
 813                 fbc->no_fbc_reason = "disabled per module param or by default";
 814                 return false;
 815         }
 816
 817         if (fbc->underrun_detected) {
 818                 fbc->no_fbc_reason = "underrun detected";
 819                 return false;
 820         }
 821
 822         return true;
 823 }
 824
 825 static void intel_fbc_get_reg_params(struct intel_crtc *crtc,
 826                                      struct intel_fbc_reg_params *params)
 827 {
 828         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 829         struct intel_fbc *fbc = &dev_priv->fbc;
 830         struct intel_fbc_state_cache *cache = &fbc->state_cache;
 831
 832         /* Since all our fields are integer types, use memset here so the
 833          * comparison function can rely on memcmp because the padding will be
 834          * zero. */
 835         memset(params, 0, sizeof(*params));
 836
 837         params->vma = cache->vma;
 838         params->flags = cache->flags;
 839
 840         params->crtc.pipe = crtc->pipe;
 841         params->crtc.i9xx_plane = to_intel_plane(crtc->base.primary)->i9xx_plane;
 842         params->crtc.fence_y_offset = get_crtc_fence_y_offset(fbc);
 843
 844         params->fb.format = cache->fb.format;
 845         params->fb.stride = cache->fb.stride;
 846
 847         params->cfb_size = intel_fbc_calculate_cfb_size(dev_priv, cache);
 848
 849         if (IS_GEN(dev_priv, 9) && !IS_GEMINILAKE(dev_priv))
 850                 params->gen9_wa_cfb_stride = DIV_ROUND_UP(cache->plane.src_w,
 851                                                 32 * fbc->threshold) * 8;
 852 }
 853
 854 void intel_fbc_pre_update(struct intel_crtc *crtc,
 855                           struct intel_crtc_state *crtc_state,
 856                           struct intel_plane_state *plane_state)
 857 {
 858         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 859         struct intel_fbc *fbc = &dev_priv->fbc;
 860         const char *reason = "update pending";
 861
 862         if (!fbc_supported(dev_priv))
 863                 return;
 864
 865         mutex_lock(&fbc->lock);
 866
 867         if (!multiple_pipes_ok(crtc, plane_state)) {
 868                 reason = "more than one pipe active";
 869                 goto deactivate;
 870         }
 871
 872         if (!fbc->enabled || fbc->crtc != crtc)
 873                 goto unlock;
 874
 875         intel_fbc_update_state_cache(crtc, crtc_state, plane_state);
 876         fbc->flip_pending = true;
 877
 878 deactivate:
 879         intel_fbc_deactivate(dev_priv, reason);
 880 unlock:
 881         mutex_unlock(&fbc->lock);
 882 }
 883
 884 /**
 885  * __intel_fbc_disable - disable FBC
 886  * @dev_priv: i915 device instance
 887  *
 888  * This is the low level function that actually disables FBC. Callers should
 889  * grab the FBC lock.
 890  */
 891 static void __intel_fbc_disable(struct drm_i915_private *dev_priv)
 892 {
 893         struct intel_fbc *fbc = &dev_priv->fbc;
 894         struct intel_crtc *crtc = fbc->crtc;
 895
 896         WARN_ON(!mutex_is_locked(&fbc->lock));
 897         WARN_ON(!fbc->enabled);
 898         WARN_ON(fbc->active);
 899
 900         DRM_DEBUG_KMS("Disabling FBC on pipe %c\n", pipe_name(crtc->pipe));
 901
 902         __intel_fbc_cleanup_cfb(dev_priv);
 903
 904         fbc->enabled = false;
 905         fbc->crtc = NULL;
 906 }
 907
 908 static void __intel_fbc_post_update(struct intel_crtc *crtc)
 909 {
 910         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 911         struct intel_fbc *fbc = &dev_priv->fbc;
 912
 913         WARN_ON(!mutex_is_locked(&fbc->lock));
 914
 915         if (!fbc->enabled || fbc->crtc != crtc)
 916                 return;
 917
 918         fbc->flip_pending = false;
 919         WARN_ON(fbc->active);
 920
 921         if (!i915_modparams.enable_fbc) {
 922                 intel_fbc_deactivate(dev_priv, "disabled at runtime per module param");
 923                 __intel_fbc_disable(dev_priv);
 924
 925                 return;
 926         }
 927
 928         intel_fbc_get_reg_params(crtc, &fbc->params);
 929
 930         if (!intel_fbc_can_activate(crtc))
 931                 return;
 932
 933         if (!fbc->busy_bits) {
 934                 intel_fbc_deactivate(dev_priv, "FBC enabled (active or scheduled)");
 935                 intel_fbc_hw_activate(dev_priv);
 936         } else
 937                 intel_fbc_deactivate(dev_priv, "frontbuffer write");
 938 }
 939
 940 void intel_fbc_post_update(struct intel_crtc *crtc)
 941 {
 942         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 943         struct intel_fbc *fbc = &dev_priv->fbc;
 944
 945         if (!fbc_supported(dev_priv))
 946                 return;
 947
 948         mutex_lock(&fbc->lock);
 949         __intel_fbc_post_update(crtc);
 950         mutex_unlock(&fbc->lock);
 951 }
 952
 953 static unsigned int intel_fbc_get_frontbuffer_bit(struct intel_fbc *fbc)
 954 {
 955         if (fbc->enabled)
 956                 return to_intel_plane(fbc->crtc->base.primary)->frontbuffer_bit;
 957         else
 958                 return fbc->possible_framebuffer_bits;
 959 }
 960
 961 void intel_fbc_invalidate(struct drm_i915_private *dev_priv,
 962                           unsigned int frontbuffer_bits,
 963                           enum fb_op_origin origin)
 964 {
 965         struct intel_fbc *fbc = &dev_priv->fbc;
 966
 967         if (!fbc_supported(dev_priv))
 968                 return;
 969
 970         if (origin == ORIGIN_GTT || origin == ORIGIN_FLIP)
 971                 return;
 972
 973         mutex_lock(&fbc->lock);
 974
 975         fbc->busy_bits |= intel_fbc_get_frontbuffer_bit(fbc) & frontbuffer_bits;
 976
 977         if (fbc->enabled && fbc->busy_bits)
 978                 intel_fbc_deactivate(dev_priv, "frontbuffer write");
 979
 980         mutex_unlock(&fbc->lock);
 981 }
 982
 983 void intel_fbc_flush(struct drm_i915_private *dev_priv,
 984                      unsigned int frontbuffer_bits, enum fb_op_origin origin)
 985 {
 986         struct intel_fbc *fbc = &dev_priv->fbc;
 987
 988         if (!fbc_supported(dev_priv))
 989                 return;
 990
 991         mutex_lock(&fbc->lock);
 992
 993         fbc->busy_bits &= ~frontbuffer_bits;
 994
 995         if (origin == ORIGIN_GTT || origin == ORIGIN_FLIP)
 996                 goto out;
 997
 998         if (!fbc->busy_bits && fbc->enabled &&
 999             (frontbuffer_bits & intel_fbc_get_frontbuffer_bit(fbc))) {
1000                 if (fbc->active)
1001                         intel_fbc_recompress(dev_priv);
1002                 else if (!fbc->flip_pending)
1003                         __intel_fbc_post_update(fbc->crtc);
1004         }
1005
1006 out:
1007         mutex_unlock(&fbc->lock);
1008 }
1009
1010 /**
1011  * intel_fbc_choose_crtc - select a CRTC to enable FBC on
1012  * @dev_priv: i915 device instance
1013  * @state: the atomic state structure
1014  *
1015  * This function looks at the proposed state for CRTCs and planes, then chooses
1016  * which pipe is going to have FBC by setting intel_crtc_state->enable_fbc to
1017  * true.
1018  *
1019  * Later, intel_fbc_enable is going to look for state->enable_fbc and then maybe
1020  * enable FBC for the chosen CRTC. If it does, it will set dev_priv->fbc.crtc.
1021  */
1022 void intel_fbc_choose_crtc(struct drm_i915_private *dev_priv,
1023                            struct intel_atomic_state *state)
1024 {
1025         struct intel_fbc *fbc = &dev_priv->fbc;
1026         struct intel_plane *plane;
1027         struct intel_plane_state *plane_state;
1028         bool crtc_chosen = false;
1029         int i;
1030
1031         mutex_lock(&fbc->lock);
1032
1033         /* Does this atomic commit involve the CRTC currently tied to FBC? */
1034         if (fbc->crtc &&
1035             !intel_atomic_get_new_crtc_state(state, fbc->crtc))
1036                 goto out;
1037
1038         if (!intel_fbc_can_enable(dev_priv))
1039                 goto out;
1040
1041         /* Simply choose the first CRTC that is compatible and has a visible
1042          * plane. We could go for fancier schemes such as checking the plane
1043          * size, but this would just affect the few platforms that don't tie FBC
1044          * to pipe or plane A. */
1045         for_each_new_intel_plane_in_state(state, plane, plane_state, i) {
1046                 struct intel_crtc_state *crtc_state;
1047                 struct intel_crtc *crtc = to_intel_crtc(plane_state->base.crtc);
1048
1049                 if (!plane->has_fbc)
1050                         continue;
1051
1052                 if (!plane_state->base.visible)
1053                         continue;
1054
1055                 crtc_state = intel_atomic_get_new_crtc_state(state, crtc);
1056
1057                 crtc_state->enable_fbc = true;
1058                 crtc_chosen = true;
1059                 break;
1060         }
1061
1062         if (!crtc_chosen)
1063                 fbc->no_fbc_reason = "no suitable CRTC for FBC";
1064
1065 out:
1066         mutex_unlock(&fbc->lock);
1067 }
1068
1069 /**
1070  * intel_fbc_enable: tries to enable FBC on the CRTC
1071  * @crtc: the CRTC
1072  * @crtc_state: corresponding &drm_crtc_state for @crtc
1073  * @plane_state: corresponding &drm_plane_state for the primary plane of @crtc
1074  *
1075  * This function checks if the given CRTC was chosen for FBC, then enables it if
1076  * possible. Notice that it doesn't activate FBC. It is valid to call
1077  * intel_fbc_enable multiple times for the same pipe without an
1078  * intel_fbc_disable in the middle, as long as it is deactivated.
1079  */
1080 void intel_fbc_enable(struct intel_crtc *crtc,
1081                       struct intel_crtc_state *crtc_state,
1082                       struct intel_plane_state *plane_state)
1083 {
1084         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1085         struct intel_fbc *fbc = &dev_priv->fbc;
1086
1087         if (!fbc_supported(dev_priv))
1088                 return;
1089
1090         mutex_lock(&fbc->lock);
1091
1092         if (fbc->enabled) {
1093                 WARN_ON(fbc->crtc == NULL);
1094                 if (fbc->crtc == crtc) {
1095                         WARN_ON(!crtc_state->enable_fbc);
1096                         WARN_ON(fbc->active);
1097                 }
1098                 goto out;
1099         }
1100
1101         if (!crtc_state->enable_fbc)
1102                 goto out;
1103
1104         WARN_ON(fbc->active);
1105         WARN_ON(fbc->crtc != NULL);
1106
1107         intel_fbc_update_state_cache(crtc, crtc_state, plane_state);
1108         if (intel_fbc_alloc_cfb(crtc)) {
1109                 fbc->no_fbc_reason = "not enough stolen memory";
1110                 goto out;
1111         }
1112
1113         DRM_DEBUG_KMS("Enabling FBC on pipe %c\n", pipe_name(crtc->pipe));
1114         fbc->no_fbc_reason = "FBC enabled but not active yet\n";
1115
1116         fbc->enabled = true;
1117         fbc->crtc = crtc;
1118 out:
1119         mutex_unlock(&fbc->lock);
1120 }
1121
1122 /**
1123  * intel_fbc_disable - disable FBC if it's associated with crtc
1124  * @crtc: the CRTC
1125  *
1126  * This function disables FBC if it's associated with the provided CRTC.
1127  */
1128 void intel_fbc_disable(struct intel_crtc *crtc)
1129 {
1130         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1131         struct intel_fbc *fbc = &dev_priv->fbc;
1132
1133         if (!fbc_supported(dev_priv))
1134                 return;
1135
1136         mutex_lock(&fbc->lock);
1137         if (fbc->crtc == crtc)
1138                 __intel_fbc_disable(dev_priv);
1139         mutex_unlock(&fbc->lock);
1140 }
1141
1142 /**
1143  * intel_fbc_global_disable - globally disable FBC
1144  * @dev_priv: i915 device instance
1145  *
1146  * This function disables FBC regardless of which CRTC is associated with it.
1147  */
1148 void intel_fbc_global_disable(struct drm_i915_private *dev_priv)
1149 {
1150         struct intel_fbc *fbc = &dev_priv->fbc;
1151
1152         if (!fbc_supported(dev_priv))
1153                 return;
1154
1155         mutex_lock(&fbc->lock);
1156         if (fbc->enabled) {
1157                 WARN_ON(fbc->crtc->active);
1158                 __intel_fbc_disable(dev_priv);
1159         }
1160         mutex_unlock(&fbc->lock);
1161 }
1162
1163 static void intel_fbc_underrun_work_fn(struct work_struct *work)
1164 {
1165         struct drm_i915_private *dev_priv =
1166                 container_of(work, struct drm_i915_private, fbc.underrun_work);
1167         struct intel_fbc *fbc = &dev_priv->fbc;
1168
1169         mutex_lock(&fbc->lock);
1170
1171         /* Maybe we were scheduled twice. */
1172         if (fbc->underrun_detected || !fbc->enabled)
1173                 goto out;
1174
1175         DRM_DEBUG_KMS("Disabling FBC due to FIFO underrun.\n");
1176         fbc->underrun_detected = true;
1177
1178         intel_fbc_deactivate(dev_priv, "FIFO underrun");
1179 out:
1180         mutex_unlock(&fbc->lock);
1181 }
1182
1183 /*
1184  * intel_fbc_reset_underrun - reset FBC fifo underrun status.
1185  * @dev_priv: i915 device instance
1186  *
1187  * See intel_fbc_handle_fifo_underrun_irq(). For automated testing we
1188  * want to re-enable FBC after an underrun to increase test coverage.
1189  */
1190 int intel_fbc_reset_underrun(struct drm_i915_private *dev_priv)
1191 {
1192         int ret;
1193
1194         cancel_work_sync(&dev_priv->fbc.underrun_work);
1195
1196         ret = mutex_lock_interruptible(&dev_priv->fbc.lock);
1197         if (ret)
1198                 return ret;
1199
1200         if (dev_priv->fbc.underrun_detected) {
1201                 DRM_DEBUG_KMS("Re-allowing FBC after fifo underrun\n");
1202                 dev_priv->fbc.no_fbc_reason = "FIFO underrun cleared";
1203         }
1204
1205         dev_priv->fbc.underrun_detected = false;
1206         mutex_unlock(&dev_priv->fbc.lock);
1207
1208         return 0;
1209 }
1210
1211 /**
1212  * intel_fbc_handle_fifo_underrun_irq - disable FBC when we get a FIFO underrun
1213  * @dev_priv: i915 device instance
1214  *
1215  * Without FBC, most underruns are harmless and don't really cause too many
1216  * problems, except for an annoying message on dmesg. With FBC, underruns can
1217  * become black screens or even worse, especially when paired with bad
1218  * watermarks. So in order for us to be on the safe side, completely disable FBC
1219  * in case we ever detect a FIFO underrun on any pipe. An underrun on any pipe
1220  * already suggests that watermarks may be bad, so try to be as safe as
1221  * possible.
1222  *
1223  * This function is called from the IRQ handler.
1224  */
1225 void intel_fbc_handle_fifo_underrun_irq(struct drm_i915_private *dev_priv)
1226 {
1227         struct intel_fbc *fbc = &dev_priv->fbc;
1228
1229         if (!fbc_supported(dev_priv))
1230                 return;
1231
1232         /* There's no guarantee that underrun_detected won't be set to true
1233          * right after this check and before the work is scheduled, but that's
1234          * not a problem since we'll check it again under the work function
1235          * while FBC is locked. This check here is just to prevent us from
1236          * unnecessarily scheduling the work, and it relies on the fact that we
1237          * never switch underrun_detect back to false after it's true. */
1238         if (READ_ONCE(fbc->underrun_detected))
1239                 return;
1240
1241         schedule_work(&fbc->underrun_work);
1242 }
1243
1244 /**
1245  * intel_fbc_init_pipe_state - initialize FBC's CRTC visibility tracking
1246  * @dev_priv: i915 device instance
1247  *
1248  * The FBC code needs to track CRTC visibility since the older platforms can't
1249  * have FBC enabled while multiple pipes are used. This function does the
1250  * initial setup at driver load to make sure FBC is matching the real hardware.
1251  */
1252 void intel_fbc_init_pipe_state(struct drm_i915_private *dev_priv)
1253 {
1254         struct intel_crtc *crtc;
1255
1256         /* Don't even bother tracking anything if we don't need. */
1257         if (!no_fbc_on_multiple_pipes(dev_priv))
1258                 return;
1259
1260         for_each_intel_crtc(&dev_priv->drm, crtc)
1261                 if (intel_crtc_active(crtc) &&
1262                     crtc->base.primary->state->visible)
1263                         dev_priv->fbc.visible_pipes_mask |= (1 << crtc->pipe);
1264 }
1265
1266 /*
1267  * The DDX driver changes its behavior depending on the value it reads from
1268  * i915.enable_fbc, so sanitize it by translating the default value into either
1269  * 0 or 1 in order to allow it to know what's going on.
1270  *
1271  * Notice that this is done at driver initialization and we still allow user
1272  * space to change the value during runtime without sanitizing it again. IGT
1273  * relies on being able to change i915.enable_fbc at runtime.
1274  */
1275 static int intel_sanitize_fbc_option(struct drm_i915_private *dev_priv)
1276 {
1277         if (i915_modparams.enable_fbc >= 0)
1278                 return !!i915_modparams.enable_fbc;
1279
1280         if (!HAS_FBC(dev_priv))
1281                 return 0;
1282
1283         /* https://bugs.freedesktop.org/show_bug.cgi?id=108085 */
1284         if (IS_GEMINILAKE(dev_priv))
1285                 return 0;
1286
1287         if (IS_BROADWELL(dev_priv) || INTEL_GEN(dev_priv) >= 9)
1288                 return 1;
1289
1290         return 0;
1291 }
1292
1293 static bool need_fbc_vtd_wa(struct drm_i915_private *dev_priv)
1294 {
1295         /* WaFbcTurnOffFbcWhenHyperVisorIsUsed:skl,bxt */
1296         if (intel_vtd_active() &&
1297             (IS_SKYLAKE(dev_priv) || IS_BROXTON(dev_priv))) {
1298                 DRM_INFO("Disabling framebuffer compression (FBC) to prevent screen flicker with VT-d enabled\n");
1299                 return true;
1300         }
1301
1302         return false;
1303 }
1304
1305 /**
1306  * intel_fbc_init - Initialize FBC
1307  * @dev_priv: the i915 device
1308  *
1309  * This function might be called during PM init process.
1310  */
1311 void intel_fbc_init(struct drm_i915_private *dev_priv)
1312 {
1313         struct intel_fbc *fbc = &dev_priv->fbc;
1314
1315         INIT_WORK(&fbc->underrun_work, intel_fbc_underrun_work_fn);
1316         mutex_init(&fbc->lock);
1317         fbc->enabled = false;
1318         fbc->active = false;
1319
1320         if (need_fbc_vtd_wa(dev_priv))
1321                 mkwrite_device_info(dev_priv)->display.has_fbc = false;
1322
1323         i915_modparams.enable_fbc = intel_sanitize_fbc_option(dev_priv);
1324         DRM_DEBUG_KMS("Sanitized enable_fbc value: %d\n",
1325                       i915_modparams.enable_fbc);
1326
1327         if (!HAS_FBC(dev_priv)) {
1328                 fbc->no_fbc_reason = "unsupported by this chipset";
1329                 return;
1330         }
1331
1332         /* This value was pulled out of someone's hat */
1333         if (INTEL_GEN(dev_priv) <= 4 && !IS_GM45(dev_priv))
1334                 I915_WRITE(FBC_CONTROL, 500 << FBC_CTL_INTERVAL_SHIFT);
1335
1336         /* We still don't have any sort of hardware state readout for FBC, so
1337          * deactivate it in case the BIOS activated it to make sure software
1338          * matches the hardware state. */
1339         if (intel_fbc_hw_is_active(dev_priv))
1340                 intel_fbc_hw_deactivate(dev_priv);
1341 }