drivers/gpu/drm/radeon/radeon_object.c

   1 /*
   2  * Copyright 2009 Jerome Glisse.
   3  * All Rights Reserved.
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the
   7  * "Software"), to deal in the Software without restriction, including
   8  * without limitation the rights to use, copy, modify, merge, publish,
   9  * distribute, sub license, and/or sell copies of the Software, and to
  10  * permit persons to whom the Software is furnished to do so, subject to
  11  * the following conditions:
  12  *
  13  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  14  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  15  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  16  * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
  17  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  18  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  19  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  20  *
  21  * The above copyright notice and this permission notice (including the
  22  * next paragraph) shall be included in all copies or substantial portions
  23  * of the Software.
  24  *
  25  */
  26 /*
  27  * Authors:
  28  *    Jerome Glisse <[email protected]>
  29  *    Thomas Hellstrom <thomas-at-tungstengraphics-dot-com>
  30  *    Dave Airlie
  31  */
  32
  33 #include <linux/io.h>
  34 #include <linux/list.h>
  35 #include <linux/slab.h>
  36
  37 #include <drm/drm_cache.h>
  38 #include <drm/drm_prime.h>
  39 #include <drm/radeon_drm.h>
  40
  41 #include "radeon.h"
  42 #include "radeon_trace.h"
  43 #include "radeon_ttm.h"
  44
  45 static void radeon_bo_clear_surface_reg(struct radeon_bo *bo);
  46
  47 /*
  48  * To exclude mutual BO access we rely on bo_reserve exclusion, as all
  49  * function are calling it.
  50  */
  51
  52 static void radeon_update_memory_usage(struct radeon_bo *bo,
  53                                        unsigned mem_type, int sign)
  54 {
  55         struct radeon_device *rdev = bo->rdev;
  56         u64 size = (u64)bo->tbo.num_pages << PAGE_SHIFT;
  57
  58         switch (mem_type) {
  59         case TTM_PL_TT:
  60                 if (sign > 0)
  61                         atomic64_add(size, &rdev->gtt_usage);
  62                 else
  63                         atomic64_sub(size, &rdev->gtt_usage);
  64                 break;
  65         case TTM_PL_VRAM:
  66                 if (sign > 0)
  67                         atomic64_add(size, &rdev->vram_usage);
  68                 else
  69                         atomic64_sub(size, &rdev->vram_usage);
  70                 break;
  71         }
  72 }
  73
  74 static void radeon_ttm_bo_destroy(struct ttm_buffer_object *tbo)
  75 {
  76         struct radeon_bo *bo;
  77
  78         bo = container_of(tbo, struct radeon_bo, tbo);
  79
  80         radeon_update_memory_usage(bo, bo->tbo.mem.mem_type, -1);
  81
  82         mutex_lock(&bo->rdev->gem.mutex);
  83         list_del_init(&bo->list);
  84         mutex_unlock(&bo->rdev->gem.mutex);
  85         radeon_bo_clear_surface_reg(bo);
  86         WARN_ON_ONCE(!list_empty(&bo->va));
  87         if (bo->tbo.base.import_attach)
  88                 drm_prime_gem_destroy(&bo->tbo.base, bo->tbo.sg);
  89         drm_gem_object_release(&bo->tbo.base);
  90         kfree(bo);
  91 }
  92
  93 bool radeon_ttm_bo_is_radeon_bo(struct ttm_buffer_object *bo)
  94 {
  95         if (bo->destroy == &radeon_ttm_bo_destroy)
  96                 return true;
  97         return false;
  98 }
  99
 100 void radeon_ttm_placement_from_domain(struct radeon_bo *rbo, u32 domain)
 101 {
 102         u32 c = 0, i;
 103
 104         rbo->placement.placement = rbo->placements;
 105         rbo->placement.busy_placement = rbo->placements;
 106         if (domain & RADEON_GEM_DOMAIN_VRAM) {
 107                 /* Try placing BOs which don't need CPU access outside of the
 108                  * CPU accessible part of VRAM
 109                  */
 110                 if ((rbo->flags & RADEON_GEM_NO_CPU_ACCESS) &&
 111                     rbo->rdev->mc.visible_vram_size < rbo->rdev->mc.real_vram_size) {
 112                         rbo->placements[c].fpfn =
 113                                 rbo->rdev->mc.visible_vram_size >> PAGE_SHIFT;
 114                         rbo->placements[c].mem_type = TTM_PL_VRAM;
 115                         rbo->placements[c++].flags = 0;
 116                 }
 117
 118                 rbo->placements[c].fpfn = 0;
 119                 rbo->placements[c].mem_type = TTM_PL_VRAM;
 120                 rbo->placements[c++].flags = 0;
 121         }
 122
 123         if (domain & RADEON_GEM_DOMAIN_GTT) {
 124                 rbo->placements[c].fpfn = 0;
 125                 rbo->placements[c].mem_type = TTM_PL_TT;
 126                 rbo->placements[c++].flags = 0;
 127         }
 128
 129         if (domain & RADEON_GEM_DOMAIN_CPU) {
 130                 rbo->placements[c].fpfn = 0;
 131                 rbo->placements[c].mem_type = TTM_PL_SYSTEM;
 132                 rbo->placements[c++].flags = 0;
 133         }
 134         if (!c) {
 135                 rbo->placements[c].fpfn = 0;
 136                 rbo->placements[c].mem_type = TTM_PL_SYSTEM;
 137                 rbo->placements[c++].flags = 0;
 138         }
 139
 140         rbo->placement.num_placement = c;
 141         rbo->placement.num_busy_placement = c;
 142
 143         for (i = 0; i < c; ++i) {
 144                 if ((rbo->flags & RADEON_GEM_CPU_ACCESS) &&
 145                     (rbo->placements[i].mem_type == TTM_PL_VRAM) &&
 146                     !rbo->placements[i].fpfn)
 147                         rbo->placements[i].lpfn =
 148                                 rbo->rdev->mc.visible_vram_size >> PAGE_SHIFT;
 149                 else
 150                         rbo->placements[i].lpfn = 0;
 151         }
 152 }
 153
 154 int radeon_bo_create(struct radeon_device *rdev,
 155                      unsigned long size, int byte_align, bool kernel,
 156                      u32 domain, u32 flags, struct sg_table *sg,
 157                      struct dma_resv *resv,
 158                      struct radeon_bo **bo_ptr)
 159 {
 160         struct radeon_bo *bo;
 161         enum ttm_bo_type type;
 162         unsigned long page_align = roundup(byte_align, PAGE_SIZE) >> PAGE_SHIFT;
 163         size_t acc_size;
 164         int r;
 165
 166         size = ALIGN(size, PAGE_SIZE);
 167
 168         if (kernel) {
 169                 type = ttm_bo_type_kernel;
 170         } else if (sg) {
 171                 type = ttm_bo_type_sg;
 172         } else {
 173                 type = ttm_bo_type_device;
 174         }
 175         *bo_ptr = NULL;
 176
 177         acc_size = ttm_bo_dma_acc_size(&rdev->mman.bdev, size,
 178                                        sizeof(struct radeon_bo));
 179
 180         bo = kzalloc(sizeof(struct radeon_bo), GFP_KERNEL);
 181         if (bo == NULL)
 182                 return -ENOMEM;
 183         drm_gem_private_object_init(rdev->ddev, &bo->tbo.base, size);
 184         bo->rdev = rdev;
 185         bo->surface_reg = -1;
 186         INIT_LIST_HEAD(&bo->list);
 187         INIT_LIST_HEAD(&bo->va);
 188         bo->initial_domain = domain & (RADEON_GEM_DOMAIN_VRAM |
 189                                        RADEON_GEM_DOMAIN_GTT |
 190                                        RADEON_GEM_DOMAIN_CPU);
 191
 192         bo->flags = flags;
 193         /* PCI GART is always snooped */
 194         if (!(rdev->flags & RADEON_IS_PCIE))
 195                 bo->flags &= ~(RADEON_GEM_GTT_WC | RADEON_GEM_GTT_UC);
 196
 197         /* Write-combined CPU mappings of GTT cause GPU hangs with RV6xx
 198          * See https://bugs.freedesktop.org/show_bug.cgi?id=91268
 199          */
 200         if (rdev->family >= CHIP_RV610 && rdev->family <= CHIP_RV635)
 201                 bo->flags &= ~(RADEON_GEM_GTT_WC | RADEON_GEM_GTT_UC);
 202
 203 #ifdef CONFIG_X86_32
 204         /* XXX: Write-combined CPU mappings of GTT seem broken on 32-bit
 205          * See https://bugs.freedesktop.org/show_bug.cgi?id=84627
 206          */
 207         bo->flags &= ~(RADEON_GEM_GTT_WC | RADEON_GEM_GTT_UC);
 208 #elif defined(CONFIG_X86) && !defined(CONFIG_X86_PAT)
 209         /* Don't try to enable write-combining when it can't work, or things
 210          * may be slow
 211          * See https://bugs.freedesktop.org/show_bug.cgi?id=88758
 212          */
 213 #ifndef CONFIG_COMPILE_TEST
 214 #warning Please enable CONFIG_MTRR and CONFIG_X86_PAT for better performance \
 215          thanks to write-combining
 216 #endif
 217
 218         if (bo->flags & RADEON_GEM_GTT_WC)
 219                 DRM_INFO_ONCE("Please enable CONFIG_MTRR and CONFIG_X86_PAT for "
 220                               "better performance thanks to write-combining\n");
 221         bo->flags &= ~(RADEON_GEM_GTT_WC | RADEON_GEM_GTT_UC);
 222 #else
 223         /* For architectures that don't support WC memory,
 224          * mask out the WC flag from the BO
 225          */
 226         if (!drm_arch_can_wc_memory())
 227                 bo->flags &= ~RADEON_GEM_GTT_WC;
 228 #endif
 229
 230         radeon_ttm_placement_from_domain(bo, domain);
 231         /* Kernel allocation are uninterruptible */
 232         down_read(&rdev->pm.mclk_lock);
 233         r = ttm_bo_init(&rdev->mman.bdev, &bo->tbo, size, type,
 234                         &bo->placement, page_align, !kernel, acc_size,
 235                         sg, resv, &radeon_ttm_bo_destroy);
 236         up_read(&rdev->pm.mclk_lock);
 237         if (unlikely(r != 0)) {
 238                 return r;
 239         }
 240         *bo_ptr = bo;
 241
 242         trace_radeon_bo_create(bo);
 243
 244         return 0;
 245 }
 246
 247 int radeon_bo_kmap(struct radeon_bo *bo, void **ptr)
 248 {
 249         bool is_iomem;
 250         int r;
 251
 252         if (bo->kptr) {
 253                 if (ptr) {
 254                         *ptr = bo->kptr;
 255                 }
 256                 return 0;
 257         }
 258         r = ttm_bo_kmap(&bo->tbo, 0, bo->tbo.num_pages, &bo->kmap);
 259         if (r) {
 260                 return r;
 261         }
 262         bo->kptr = ttm_kmap_obj_virtual(&bo->kmap, &is_iomem);
 263         if (ptr) {
 264                 *ptr = bo->kptr;
 265         }
 266         radeon_bo_check_tiling(bo, 0, 0);
 267         return 0;
 268 }
 269
 270 void radeon_bo_kunmap(struct radeon_bo *bo)
 271 {
 272         if (bo->kptr == NULL)
 273                 return;
 274         bo->kptr = NULL;
 275         radeon_bo_check_tiling(bo, 0, 0);
 276         ttm_bo_kunmap(&bo->kmap);
 277 }
 278
 279 struct radeon_bo *radeon_bo_ref(struct radeon_bo *bo)
 280 {
 281         if (bo == NULL)
 282                 return NULL;
 283
 284         ttm_bo_get(&bo->tbo);
 285         return bo;
 286 }
 287
 288 void radeon_bo_unref(struct radeon_bo **bo)
 289 {
 290         struct ttm_buffer_object *tbo;
 291
 292         if ((*bo) == NULL)
 293                 return;
 294         tbo = &((*bo)->tbo);
 295         ttm_bo_put(tbo);
 296         *bo = NULL;
 297 }
 298
 299 int radeon_bo_pin_restricted(struct radeon_bo *bo, u32 domain, u64 max_offset,
 300                              u64 *gpu_addr)
 301 {
 302         struct ttm_operation_ctx ctx = { false, false };
 303         int r, i;
 304
 305         if (radeon_ttm_tt_has_userptr(bo->rdev, bo->tbo.ttm))
 306                 return -EPERM;
 307
 308         if (bo->tbo.pin_count) {
 309                 ttm_bo_pin(&bo->tbo);
 310                 if (gpu_addr)
 311                         *gpu_addr = radeon_bo_gpu_offset(bo);
 312
 313                 if (max_offset != 0) {
 314                         u64 domain_start;
 315
 316                         if (domain == RADEON_GEM_DOMAIN_VRAM)
 317                                 domain_start = bo->rdev->mc.vram_start;
 318                         else
 319                                 domain_start = bo->rdev->mc.gtt_start;
 320                         WARN_ON_ONCE(max_offset <
 321                                      (radeon_bo_gpu_offset(bo) - domain_start));
 322                 }
 323
 324                 return 0;
 325         }
 326         if (bo->prime_shared_count && domain == RADEON_GEM_DOMAIN_VRAM) {
 327                 /* A BO shared as a dma-buf cannot be sensibly migrated to VRAM */
 328                 return -EINVAL;
 329         }
 330
 331         radeon_ttm_placement_from_domain(bo, domain);
 332         for (i = 0; i < bo->placement.num_placement; i++) {
 333                 /* force to pin into visible video ram */
 334                 if ((bo->placements[i].mem_type == TTM_PL_VRAM) &&
 335                     !(bo->flags & RADEON_GEM_NO_CPU_ACCESS) &&
 336                     (!max_offset || max_offset > bo->rdev->mc.visible_vram_size))
 337                         bo->placements[i].lpfn =
 338                                 bo->rdev->mc.visible_vram_size >> PAGE_SHIFT;
 339                 else
 340                         bo->placements[i].lpfn = max_offset >> PAGE_SHIFT;
 341         }
 342
 343         r = ttm_bo_validate(&bo->tbo, &bo->placement, &ctx);
 344         if (likely(r == 0)) {
 345                 ttm_bo_pin(&bo->tbo);
 346                 if (gpu_addr != NULL)
 347                         *gpu_addr = radeon_bo_gpu_offset(bo);
 348                 if (domain == RADEON_GEM_DOMAIN_VRAM)
 349                         bo->rdev->vram_pin_size += radeon_bo_size(bo);
 350                 else
 351                         bo->rdev->gart_pin_size += radeon_bo_size(bo);
 352         } else {
 353                 dev_err(bo->rdev->dev, "%p pin failed\n", bo);
 354         }
 355         return r;
 356 }
 357
 358 int radeon_bo_pin(struct radeon_bo *bo, u32 domain, u64 *gpu_addr)
 359 {
 360         return radeon_bo_pin_restricted(bo, domain, 0, gpu_addr);
 361 }
 362
 363 void radeon_bo_unpin(struct radeon_bo *bo)
 364 {
 365         ttm_bo_unpin(&bo->tbo);
 366         if (!bo->tbo.pin_count) {
 367                 if (bo->tbo.mem.mem_type == TTM_PL_VRAM)
 368                         bo->rdev->vram_pin_size -= radeon_bo_size(bo);
 369                 else
 370                         bo->rdev->gart_pin_size -= radeon_bo_size(bo);
 371         }
 372 }
 373
 374 int radeon_bo_evict_vram(struct radeon_device *rdev)
 375 {
 376         struct ttm_bo_device *bdev = &rdev->mman.bdev;
 377         struct ttm_resource_manager *man;
 378
 379         /* late 2.6.33 fix IGP hibernate - we need pm ops to do this correct */
 380 #ifndef CONFIG_HIBERNATION
 381         if (rdev->flags & RADEON_IS_IGP) {
 382                 if (rdev->mc.igp_sideport_enabled == false)
 383                         /* Useless to evict on IGP chips */
 384                         return 0;
 385         }
 386 #endif
 387         man = ttm_manager_type(bdev, TTM_PL_VRAM);
 388         return ttm_resource_manager_evict_all(bdev, man);
 389 }
 390
 391 void radeon_bo_force_delete(struct radeon_device *rdev)
 392 {
 393         struct radeon_bo *bo, *n;
 394
 395         if (list_empty(&rdev->gem.objects)) {
 396                 return;
 397         }
 398         dev_err(rdev->dev, "Userspace still has active objects !\n");
 399         list_for_each_entry_safe(bo, n, &rdev->gem.objects, list) {
 400                 dev_err(rdev->dev, "%p %p %lu %lu force free\n",
 401                         &bo->tbo.base, bo, (unsigned long)bo->tbo.base.size,
 402                         *((unsigned long *)&bo->tbo.base.refcount));
 403                 mutex_lock(&bo->rdev->gem.mutex);
 404                 list_del_init(&bo->list);
 405                 mutex_unlock(&bo->rdev->gem.mutex);
 406                 /* this should unref the ttm bo */
 407                 drm_gem_object_put(&bo->tbo.base);
 408         }
 409 }
 410
 411 int radeon_bo_init(struct radeon_device *rdev)
 412 {
 413         /* reserve PAT memory space to WC for VRAM */
 414         arch_io_reserve_memtype_wc(rdev->mc.aper_base,
 415                                    rdev->mc.aper_size);
 416
 417         /* Add an MTRR for the VRAM */
 418         if (!rdev->fastfb_working) {
 419                 rdev->mc.vram_mtrr = arch_phys_wc_add(rdev->mc.aper_base,
 420                                                       rdev->mc.aper_size);
 421         }
 422         DRM_INFO("Detected VRAM RAM=%lluM, BAR=%lluM\n",
 423                 rdev->mc.mc_vram_size >> 20,
 424                 (unsigned long long)rdev->mc.aper_size >> 20);
 425         DRM_INFO("RAM width %dbits %cDR\n",
 426                         rdev->mc.vram_width, rdev->mc.vram_is_ddr ? 'D' : 'S');
 427         return radeon_ttm_init(rdev);
 428 }
 429
 430 void radeon_bo_fini(struct radeon_device *rdev)
 431 {
 432         radeon_ttm_fini(rdev);
 433         arch_phys_wc_del(rdev->mc.vram_mtrr);
 434         arch_io_free_memtype_wc(rdev->mc.aper_base, rdev->mc.aper_size);
 435 }
 436
 437 /* Returns how many bytes TTM can move per IB.
 438  */
 439 static u64 radeon_bo_get_threshold_for_moves(struct radeon_device *rdev)
 440 {
 441         u64 real_vram_size = rdev->mc.real_vram_size;
 442         u64 vram_usage = atomic64_read(&rdev->vram_usage);
 443
 444         /* This function is based on the current VRAM usage.
 445          *
 446          * - If all of VRAM is free, allow relocating the number of bytes that
 447          *   is equal to 1/4 of the size of VRAM for this IB.
 448
 449          * - If more than one half of VRAM is occupied, only allow relocating
 450          *   1 MB of data for this IB.
 451          *
 452          * - From 0 to one half of used VRAM, the threshold decreases
 453          *   linearly.
 454          *         __________________
 455          * 1/4 of -|\               |
 456          * VRAM    | \              |
 457          *         |  \             |
 458          *         |   \            |
 459          *         |    \           |
 460          *         |     \          |
 461          *         |      \         |
 462          *         |       \________|1 MB
 463          *         |----------------|
 464          *    VRAM 0 %             100 %
 465          *         used            used
 466          *
 467          * Note: It's a threshold, not a limit. The threshold must be crossed
 468          * for buffer relocations to stop, so any buffer of an arbitrary size
 469          * can be moved as long as the threshold isn't crossed before
 470          * the relocation takes place. We don't want to disable buffer
 471          * relocations completely.
 472          *
 473          * The idea is that buffers should be placed in VRAM at creation time
 474          * and TTM should only do a minimum number of relocations during
 475          * command submission. In practice, you need to submit at least
 476          * a dozen IBs to move all buffers to VRAM if they are in GTT.
 477          *
 478          * Also, things can get pretty crazy under memory pressure and actual
 479          * VRAM usage can change a lot, so playing safe even at 50% does
 480          * consistently increase performance.
 481          */
 482
 483         u64 half_vram = real_vram_size >> 1;
 484         u64 half_free_vram = vram_usage >= half_vram ? 0 : half_vram - vram_usage;
 485         u64 bytes_moved_threshold = half_free_vram >> 1;
 486         return max(bytes_moved_threshold, 1024*1024ull);
 487 }
 488
 489 int radeon_bo_list_validate(struct radeon_device *rdev,
 490                             struct ww_acquire_ctx *ticket,
 491                             struct list_head *head, int ring)
 492 {
 493         struct ttm_operation_ctx ctx = { true, false };
 494         struct radeon_bo_list *lobj;
 495         struct list_head duplicates;
 496         int r;
 497         u64 bytes_moved = 0, initial_bytes_moved;
 498         u64 bytes_moved_threshold = radeon_bo_get_threshold_for_moves(rdev);
 499
 500         INIT_LIST_HEAD(&duplicates);
 501         r = ttm_eu_reserve_buffers(ticket, head, true, &duplicates);
 502         if (unlikely(r != 0)) {
 503                 return r;
 504         }
 505
 506         list_for_each_entry(lobj, head, tv.head) {
 507                 struct radeon_bo *bo = lobj->robj;
 508                 if (!bo->tbo.pin_count) {
 509                         u32 domain = lobj->preferred_domains;
 510                         u32 allowed = lobj->allowed_domains;
 511                         u32 current_domain =
 512                                 radeon_mem_type_to_domain(bo->tbo.mem.mem_type);
 513
 514                         /* Check if this buffer will be moved and don't move it
 515                          * if we have moved too many buffers for this IB already.
 516                          *
 517                          * Note that this allows moving at least one buffer of
 518                          * any size, because it doesn't take the current "bo"
 519                          * into account. We don't want to disallow buffer moves
 520                          * completely.
 521                          */
 522                         if ((allowed & current_domain) != 0 &&
 523                             (domain & current_domain) == 0 && /* will be moved */
 524                             bytes_moved > bytes_moved_threshold) {
 525                                 /* don't move it */
 526                                 domain = current_domain;
 527                         }
 528
 529                 retry:
 530                         radeon_ttm_placement_from_domain(bo, domain);
 531                         if (ring == R600_RING_TYPE_UVD_INDEX)
 532                                 radeon_uvd_force_into_uvd_segment(bo, allowed);
 533
 534                         initial_bytes_moved = atomic64_read(&rdev->num_bytes_moved);
 535                         r = ttm_bo_validate(&bo->tbo, &bo->placement, &ctx);
 536                         bytes_moved += atomic64_read(&rdev->num_bytes_moved) -
 537                                        initial_bytes_moved;
 538
 539                         if (unlikely(r)) {
 540                                 if (r != -ERESTARTSYS &&
 541                                     domain != lobj->allowed_domains) {
 542                                         domain = lobj->allowed_domains;
 543                                         goto retry;
 544                                 }
 545                                 ttm_eu_backoff_reservation(ticket, head);
 546                                 return r;
 547                         }
 548                 }
 549                 lobj->gpu_offset = radeon_bo_gpu_offset(bo);
 550                 lobj->tiling_flags = bo->tiling_flags;
 551         }
 552
 553         list_for_each_entry(lobj, &duplicates, tv.head) {
 554                 lobj->gpu_offset = radeon_bo_gpu_offset(lobj->robj);
 555                 lobj->tiling_flags = lobj->robj->tiling_flags;
 556         }
 557
 558         return 0;
 559 }
 560
 561 int radeon_bo_get_surface_reg(struct radeon_bo *bo)
 562 {
 563         struct radeon_device *rdev = bo->rdev;
 564         struct radeon_surface_reg *reg;
 565         struct radeon_bo *old_object;
 566         int steal;
 567         int i;
 568
 569         dma_resv_assert_held(bo->tbo.base.resv);
 570
 571         if (!bo->tiling_flags)
 572                 return 0;
 573
 574         if (bo->surface_reg >= 0) {
 575                 reg = &rdev->surface_regs[bo->surface_reg];
 576                 i = bo->surface_reg;
 577                 goto out;
 578         }
 579
 580         steal = -1;
 581         for (i = 0; i < RADEON_GEM_MAX_SURFACES; i++) {
 582
 583                 reg = &rdev->surface_regs[i];
 584                 if (!reg->bo)
 585                         break;
 586
 587                 old_object = reg->bo;
 588                 if (old_object->tbo.pin_count == 0)
 589                         steal = i;
 590         }
 591
 592         /* if we are all out */
 593         if (i == RADEON_GEM_MAX_SURFACES) {
 594                 if (steal == -1)
 595                         return -ENOMEM;
 596                 /* find someone with a surface reg and nuke their BO */
 597                 reg = &rdev->surface_regs[steal];
 598                 old_object = reg->bo;
 599                 /* blow away the mapping */
 600                 DRM_DEBUG("stealing surface reg %d from %p\n", steal, old_object);
 601                 ttm_bo_unmap_virtual(&old_object->tbo);
 602                 old_object->surface_reg = -1;
 603                 i = steal;
 604         }
 605
 606         bo->surface_reg = i;
 607         reg->bo = bo;
 608
 609 out:
 610         radeon_set_surface_reg(rdev, i, bo->tiling_flags, bo->pitch,
 611                                bo->tbo.mem.start << PAGE_SHIFT,
 612                                bo->tbo.num_pages << PAGE_SHIFT);
 613         return 0;
 614 }
 615
 616 static void radeon_bo_clear_surface_reg(struct radeon_bo *bo)
 617 {
 618         struct radeon_device *rdev = bo->rdev;
 619         struct radeon_surface_reg *reg;
 620
 621         if (bo->surface_reg == -1)
 622                 return;
 623
 624         reg = &rdev->surface_regs[bo->surface_reg];
 625         radeon_clear_surface_reg(rdev, bo->surface_reg);
 626
 627         reg->bo = NULL;
 628         bo->surface_reg = -1;
 629 }
 630
 631 int radeon_bo_set_tiling_flags(struct radeon_bo *bo,
 632                                 uint32_t tiling_flags, uint32_t pitch)
 633 {
 634         struct radeon_device *rdev = bo->rdev;
 635         int r;
 636
 637         if (rdev->family >= CHIP_CEDAR) {
 638                 unsigned bankw, bankh, mtaspect, tilesplit, stilesplit;
 639
 640                 bankw = (tiling_flags >> RADEON_TILING_EG_BANKW_SHIFT) & RADEON_TILING_EG_BANKW_MASK;
 641                 bankh = (tiling_flags >> RADEON_TILING_EG_BANKH_SHIFT) & RADEON_TILING_EG_BANKH_MASK;
 642                 mtaspect = (tiling_flags >> RADEON_TILING_EG_MACRO_TILE_ASPECT_SHIFT) & RADEON_TILING_EG_MACRO_TILE_ASPECT_MASK;
 643                 tilesplit = (tiling_flags >> RADEON_TILING_EG_TILE_SPLIT_SHIFT) & RADEON_TILING_EG_TILE_SPLIT_MASK;
 644                 stilesplit = (tiling_flags >> RADEON_TILING_EG_STENCIL_TILE_SPLIT_SHIFT) & RADEON_TILING_EG_STENCIL_TILE_SPLIT_MASK;
 645                 switch (bankw) {
 646                 case 0:
 647                 case 1:
 648                 case 2:
 649                 case 4:
 650                 case 8:
 651                         break;
 652                 default:
 653                         return -EINVAL;
 654                 }
 655                 switch (bankh) {
 656                 case 0:
 657                 case 1:
 658                 case 2:
 659                 case 4:
 660                 case 8:
 661                         break;
 662                 default:
 663                         return -EINVAL;
 664                 }
 665                 switch (mtaspect) {
 666                 case 0:
 667                 case 1:
 668                 case 2:
 669                 case 4:
 670                 case 8:
 671                         break;
 672                 default:
 673                         return -EINVAL;
 674                 }
 675                 if (tilesplit > 6) {
 676                         return -EINVAL;
 677                 }
 678                 if (stilesplit > 6) {
 679                         return -EINVAL;
 680                 }
 681         }
 682         r = radeon_bo_reserve(bo, false);
 683         if (unlikely(r != 0))
 684                 return r;
 685         bo->tiling_flags = tiling_flags;
 686         bo->pitch = pitch;
 687         radeon_bo_unreserve(bo);
 688         return 0;
 689 }
 690
 691 void radeon_bo_get_tiling_flags(struct radeon_bo *bo,
 692                                 uint32_t *tiling_flags,
 693                                 uint32_t *pitch)
 694 {
 695         dma_resv_assert_held(bo->tbo.base.resv);
 696
 697         if (tiling_flags)
 698                 *tiling_flags = bo->tiling_flags;
 699         if (pitch)
 700                 *pitch = bo->pitch;
 701 }
 702
 703 int radeon_bo_check_tiling(struct radeon_bo *bo, bool has_moved,
 704                                 bool force_drop)
 705 {
 706         if (!force_drop)
 707                 dma_resv_assert_held(bo->tbo.base.resv);
 708
 709         if (!(bo->tiling_flags & RADEON_TILING_SURFACE))
 710                 return 0;
 711
 712         if (force_drop) {
 713                 radeon_bo_clear_surface_reg(bo);
 714                 return 0;
 715         }
 716
 717         if (bo->tbo.mem.mem_type != TTM_PL_VRAM) {
 718                 if (!has_moved)
 719                         return 0;
 720
 721                 if (bo->surface_reg >= 0)
 722                         radeon_bo_clear_surface_reg(bo);
 723                 return 0;
 724         }
 725
 726         if ((bo->surface_reg >= 0) && !has_moved)
 727                 return 0;
 728
 729         return radeon_bo_get_surface_reg(bo);
 730 }
 731
 732 void radeon_bo_move_notify(struct ttm_buffer_object *bo,
 733                            bool evict,
 734                            struct ttm_resource *new_mem)
 735 {
 736         struct radeon_bo *rbo;
 737
 738         if (!radeon_ttm_bo_is_radeon_bo(bo))
 739                 return;
 740
 741         rbo = container_of(bo, struct radeon_bo, tbo);
 742         radeon_bo_check_tiling(rbo, 0, 1);
 743         radeon_vm_bo_invalidate(rbo->rdev, rbo);
 744
 745         /* update statistics */
 746         if (!new_mem)
 747                 return;
 748
 749         radeon_update_memory_usage(rbo, bo->mem.mem_type, -1);
 750         radeon_update_memory_usage(rbo, new_mem->mem_type, 1);
 751 }
 752
 753 vm_fault_t radeon_bo_fault_reserve_notify(struct ttm_buffer_object *bo)
 754 {
 755         struct ttm_operation_ctx ctx = { false, false };
 756         struct radeon_device *rdev;
 757         struct radeon_bo *rbo;
 758         unsigned long offset, size, lpfn;
 759         int i, r;
 760
 761         if (!radeon_ttm_bo_is_radeon_bo(bo))
 762                 return 0;
 763         rbo = container_of(bo, struct radeon_bo, tbo);
 764         radeon_bo_check_tiling(rbo, 0, 0);
 765         rdev = rbo->rdev;
 766         if (bo->mem.mem_type != TTM_PL_VRAM)
 767                 return 0;
 768
 769         size = bo->mem.num_pages << PAGE_SHIFT;
 770         offset = bo->mem.start << PAGE_SHIFT;
 771         if ((offset + size) <= rdev->mc.visible_vram_size)
 772                 return 0;
 773
 774         /* Can't move a pinned BO to visible VRAM */
 775         if (rbo->tbo.pin_count > 0)
 776                 return VM_FAULT_SIGBUS;
 777
 778         /* hurrah the memory is not visible ! */
 779         radeon_ttm_placement_from_domain(rbo, RADEON_GEM_DOMAIN_VRAM);
 780         lpfn =  rdev->mc.visible_vram_size >> PAGE_SHIFT;
 781         for (i = 0; i < rbo->placement.num_placement; i++) {
 782                 /* Force into visible VRAM */
 783                 if ((rbo->placements[i].mem_type == TTM_PL_VRAM) &&
 784                     (!rbo->placements[i].lpfn || rbo->placements[i].lpfn > lpfn))
 785                         rbo->placements[i].lpfn = lpfn;
 786         }
 787         r = ttm_bo_validate(bo, &rbo->placement, &ctx);
 788         if (unlikely(r == -ENOMEM)) {
 789                 radeon_ttm_placement_from_domain(rbo, RADEON_GEM_DOMAIN_GTT);
 790                 r = ttm_bo_validate(bo, &rbo->placement, &ctx);
 791         } else if (likely(!r)) {
 792                 offset = bo->mem.start << PAGE_SHIFT;
 793                 /* this should never happen */
 794                 if ((offset + size) > rdev->mc.visible_vram_size)
 795                         return VM_FAULT_SIGBUS;
 796         }
 797
 798         if (unlikely(r == -EBUSY || r == -ERESTARTSYS))
 799                 return VM_FAULT_NOPAGE;
 800         else if (unlikely(r))
 801                 return VM_FAULT_SIGBUS;
 802
 803         ttm_bo_move_to_lru_tail_unlocked(bo);
 804         return 0;
 805 }
 806
 807 /**
 808  * radeon_bo_fence - add fence to buffer object
 809  *
 810  * @bo: buffer object in question
 811  * @fence: fence to add
 812  * @shared: true if fence should be added shared
 813  *
 814  */
 815 void radeon_bo_fence(struct radeon_bo *bo, struct radeon_fence *fence,
 816                      bool shared)
 817 {
 818         struct dma_resv *resv = bo->tbo.base.resv;
 819
 820         if (shared)
 821                 dma_resv_add_shared_fence(resv, &fence->base);
 822         else
 823                 dma_resv_add_excl_fence(resv, &fence->base);
 824 }