drivers/cxl/acpi.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /* Copyright(c) 2021 Intel Corporation. All rights reserved. */
   3 #include <linux/platform_device.h>
   4 #include <linux/module.h>
   5 #include <linux/device.h>
   6 #include <linux/kernel.h>
   7 #include <linux/acpi.h>
   8 #include <linux/pci.h>
   9 #include <linux/node.h>
  10 #include <asm/div64.h>
  11 #include "cxlpci.h"
  12 #include "cxl.h"
  13
  14 #define CXL_RCRB_SIZE   SZ_8K
  15
  16 struct cxl_cxims_data {
  17         int nr_maps;
  18         u64 xormaps[] __counted_by(nr_maps);
  19 };
  20
  21 static const guid_t acpi_cxl_qtg_id_guid =
  22         GUID_INIT(0xF365F9A6, 0xA7DE, 0x4071,
  23                   0xA6, 0x6A, 0xB4, 0x0C, 0x0B, 0x4F, 0x8E, 0x52);
  24
  25 /*
  26  * Find a targets entry (n) in the host bridge interleave list.
  27  * CXL Specification 3.0 Table 9-22
  28  */
  29 static int cxl_xor_calc_n(u64 hpa, struct cxl_cxims_data *cximsd, int iw,
  30                           int ig)
  31 {
  32         int i = 0, n = 0;
  33         u8 eiw;
  34
  35         /* IW: 2,4,6,8,12,16 begin building 'n' using xormaps */
  36         if (iw != 3) {
  37                 for (i = 0; i < cximsd->nr_maps; i++)
  38                         n |= (hweight64(hpa & cximsd->xormaps[i]) & 1) << i;
  39         }
  40         /* IW: 3,6,12 add a modulo calculation to 'n' */
  41         if (!is_power_of_2(iw)) {
  42                 if (ways_to_eiw(iw, &eiw))
  43                         return -1;
  44                 hpa &= GENMASK_ULL(51, eiw + ig);
  45                 n |= do_div(hpa, 3) << i;
  46         }
  47         return n;
  48 }
  49
  50 static struct cxl_dport *cxl_hb_xor(struct cxl_root_decoder *cxlrd, int pos)
  51 {
  52         struct cxl_cxims_data *cximsd = cxlrd->platform_data;
  53         struct cxl_switch_decoder *cxlsd = &cxlrd->cxlsd;
  54         struct cxl_decoder *cxld = &cxlsd->cxld;
  55         int ig = cxld->interleave_granularity;
  56         int iw = cxld->interleave_ways;
  57         int n = 0;
  58         u64 hpa;
  59
  60         if (dev_WARN_ONCE(&cxld->dev,
  61                           cxld->interleave_ways != cxlsd->nr_targets,
  62                           "misconfigured root decoder\n"))
  63                 return NULL;
  64
  65         hpa = cxlrd->res->start + pos * ig;
  66
  67         /* Entry (n) is 0 for no interleave (iw == 1) */
  68         if (iw != 1)
  69                 n = cxl_xor_calc_n(hpa, cximsd, iw, ig);
  70
  71         if (n < 0)
  72                 return NULL;
  73
  74         return cxlrd->cxlsd.target[n];
  75 }
  76
  77 struct cxl_cxims_context {
  78         struct device *dev;
  79         struct cxl_root_decoder *cxlrd;
  80 };
  81
  82 static int cxl_parse_cxims(union acpi_subtable_headers *header, void *arg,
  83                            const unsigned long end)
  84 {
  85         struct acpi_cedt_cxims *cxims = (struct acpi_cedt_cxims *)header;
  86         struct cxl_cxims_context *ctx = arg;
  87         struct cxl_root_decoder *cxlrd = ctx->cxlrd;
  88         struct cxl_decoder *cxld = &cxlrd->cxlsd.cxld;
  89         struct device *dev = ctx->dev;
  90         struct cxl_cxims_data *cximsd;
  91         unsigned int hbig, nr_maps;
  92         int rc;
  93
  94         rc = eig_to_granularity(cxims->hbig, &hbig);
  95         if (rc)
  96                 return rc;
  97
  98         /* Does this CXIMS entry apply to the given CXL Window? */
  99         if (hbig != cxld->interleave_granularity)
 100                 return 0;
 101
 102         /* IW 1,3 do not use xormaps and skip this parsing entirely */
 103         if (is_power_of_2(cxld->interleave_ways))
 104                 /* 2, 4, 8, 16 way */
 105                 nr_maps = ilog2(cxld->interleave_ways);
 106         else
 107                 /* 6, 12 way */
 108                 nr_maps = ilog2(cxld->interleave_ways / 3);
 109
 110         if (cxims->nr_xormaps < nr_maps) {
 111                 dev_dbg(dev, "CXIMS nr_xormaps[%d] expected[%d]\n",
 112                         cxims->nr_xormaps, nr_maps);
 113                 return -ENXIO;
 114         }
 115
 116         cximsd = devm_kzalloc(dev, struct_size(cximsd, xormaps, nr_maps),
 117                               GFP_KERNEL);
 118         if (!cximsd)
 119                 return -ENOMEM;
 120         cximsd->nr_maps = nr_maps;
 121         memcpy(cximsd->xormaps, cxims->xormap_list,
 122                nr_maps * sizeof(*cximsd->xormaps));
 123         cxlrd->platform_data = cximsd;
 124
 125         return 0;
 126 }
 127
 128 static unsigned long cfmws_to_decoder_flags(int restrictions)
 129 {
 130         unsigned long flags = CXL_DECODER_F_ENABLE;
 131
 132         if (restrictions & ACPI_CEDT_CFMWS_RESTRICT_TYPE2)
 133                 flags |= CXL_DECODER_F_TYPE2;
 134         if (restrictions & ACPI_CEDT_CFMWS_RESTRICT_TYPE3)
 135                 flags |= CXL_DECODER_F_TYPE3;
 136         if (restrictions & ACPI_CEDT_CFMWS_RESTRICT_VOLATILE)
 137                 flags |= CXL_DECODER_F_RAM;
 138         if (restrictions & ACPI_CEDT_CFMWS_RESTRICT_PMEM)
 139                 flags |= CXL_DECODER_F_PMEM;
 140         if (restrictions & ACPI_CEDT_CFMWS_RESTRICT_FIXED)
 141                 flags |= CXL_DECODER_F_LOCK;
 142
 143         return flags;
 144 }
 145
 146 static int cxl_acpi_cfmws_verify(struct device *dev,
 147                                  struct acpi_cedt_cfmws *cfmws)
 148 {
 149         int rc, expected_len;
 150         unsigned int ways;
 151
 152         if (cfmws->interleave_arithmetic != ACPI_CEDT_CFMWS_ARITHMETIC_MODULO &&
 153             cfmws->interleave_arithmetic != ACPI_CEDT_CFMWS_ARITHMETIC_XOR) {
 154                 dev_err(dev, "CFMWS Unknown Interleave Arithmetic: %d\n",
 155                         cfmws->interleave_arithmetic);
 156                 return -EINVAL;
 157         }
 158
 159         if (!IS_ALIGNED(cfmws->base_hpa, SZ_256M)) {
 160                 dev_err(dev, "CFMWS Base HPA not 256MB aligned\n");
 161                 return -EINVAL;
 162         }
 163
 164         if (!IS_ALIGNED(cfmws->window_size, SZ_256M)) {
 165                 dev_err(dev, "CFMWS Window Size not 256MB aligned\n");
 166                 return -EINVAL;
 167         }
 168
 169         rc = eiw_to_ways(cfmws->interleave_ways, &ways);
 170         if (rc) {
 171                 dev_err(dev, "CFMWS Interleave Ways (%d) invalid\n",
 172                         cfmws->interleave_ways);
 173                 return -EINVAL;
 174         }
 175
 176         expected_len = struct_size(cfmws, interleave_targets, ways);
 177
 178         if (cfmws->header.length < expected_len) {
 179                 dev_err(dev, "CFMWS length %d less than expected %d\n",
 180                         cfmws->header.length, expected_len);
 181                 return -EINVAL;
 182         }
 183
 184         if (cfmws->header.length > expected_len)
 185                 dev_dbg(dev, "CFMWS length %d greater than expected %d\n",
 186                         cfmws->header.length, expected_len);
 187
 188         return 0;
 189 }
 190
 191 /*
 192  * Note, @dev must be the first member, see 'struct cxl_chbs_context'
 193  * and mock_acpi_table_parse_cedt()
 194  */
 195 struct cxl_cfmws_context {
 196         struct device *dev;
 197         struct cxl_port *root_port;
 198         struct resource *cxl_res;
 199         int id;
 200 };
 201
 202 /**
 203  * cxl_acpi_evaluate_qtg_dsm - Retrieve QTG ids via ACPI _DSM
 204  * @handle: ACPI handle
 205  * @coord: performance access coordinates
 206  * @entries: number of QTG IDs to return
 207  * @qos_class: int array provided by caller to return QTG IDs
 208  *
 209  * Return: number of QTG IDs returned, or -errno for errors
 210  *
 211  * Issue QTG _DSM with accompanied bandwidth and latency data in order to get
 212  * the QTG IDs that are suitable for the performance point in order of most
 213  * suitable to least suitable. Write back array of QTG IDs and return the
 214  * actual number of QTG IDs written back.
 215  */
 216 static int
 217 cxl_acpi_evaluate_qtg_dsm(acpi_handle handle, struct access_coordinate *coord,
 218                           int entries, int *qos_class)
 219 {
 220         union acpi_object *out_obj, *out_buf, *obj;
 221         union acpi_object in_array[4] = {
 222                 [0].integer = { ACPI_TYPE_INTEGER, coord->read_latency },
 223                 [1].integer = { ACPI_TYPE_INTEGER, coord->write_latency },
 224                 [2].integer = { ACPI_TYPE_INTEGER, coord->read_bandwidth },
 225                 [3].integer = { ACPI_TYPE_INTEGER, coord->write_bandwidth },
 226         };
 227         union acpi_object in_obj = {
 228                 .package = {
 229                         .type = ACPI_TYPE_PACKAGE,
 230                         .count = 4,
 231                         .elements = in_array,
 232                 },
 233         };
 234         int count, pkg_entries, i;
 235         u16 max_qtg;
 236         int rc;
 237
 238         if (!entries)
 239                 return -EINVAL;
 240
 241         out_obj = acpi_evaluate_dsm(handle, &acpi_cxl_qtg_id_guid, 1, 1, &in_obj);
 242         if (!out_obj)
 243                 return -ENXIO;
 244
 245         if (out_obj->type != ACPI_TYPE_PACKAGE) {
 246                 rc = -ENXIO;
 247                 goto out;
 248         }
 249
 250         /* Check Max QTG ID */
 251         obj = &out_obj->package.elements[0];
 252         if (obj->type != ACPI_TYPE_INTEGER) {
 253                 rc = -ENXIO;
 254                 goto out;
 255         }
 256
 257         max_qtg = obj->integer.value;
 258
 259         /* It's legal to have 0 QTG entries */
 260         pkg_entries = out_obj->package.count;
 261         if (pkg_entries <= 1) {
 262                 rc = 0;
 263                 goto out;
 264         }
 265
 266         /* Retrieve QTG IDs package */
 267         obj = &out_obj->package.elements[1];
 268         if (obj->type != ACPI_TYPE_PACKAGE) {
 269                 rc = -ENXIO;
 270                 goto out;
 271         }
 272
 273         pkg_entries = obj->package.count;
 274         count = min(entries, pkg_entries);
 275         for (i = 0; i < count; i++) {
 276                 u16 qtg_id;
 277
 278                 out_buf = &obj->package.elements[i];
 279                 if (out_buf->type != ACPI_TYPE_INTEGER) {
 280                         rc = -ENXIO;
 281                         goto out;
 282                 }
 283
 284                 qtg_id = out_buf->integer.value;
 285                 if (qtg_id > max_qtg)
 286                         pr_warn("QTG ID %u greater than MAX %u\n",
 287                                 qtg_id, max_qtg);
 288
 289                 qos_class[i] = qtg_id;
 290         }
 291         rc = count;
 292
 293 out:
 294         ACPI_FREE(out_obj);
 295         return rc;
 296 }
 297
 298 static int cxl_acpi_qos_class(struct cxl_root *cxl_root,
 299                               struct access_coordinate *coord, int entries,
 300                               int *qos_class)
 301 {
 302         struct device *dev = cxl_root->port.uport_dev;
 303         acpi_handle handle;
 304
 305         if (!dev_is_platform(dev))
 306                 return -ENODEV;
 307
 308         handle = ACPI_HANDLE(dev);
 309         if (!handle)
 310                 return -ENODEV;
 311
 312         return cxl_acpi_evaluate_qtg_dsm(handle, coord, entries, qos_class);
 313 }
 314
 315 static const struct cxl_root_ops acpi_root_ops = {
 316         .qos_class = cxl_acpi_qos_class,
 317 };
 318
 319 static void del_cxl_resource(struct resource *res)
 320 {
 321         if (!res)
 322                 return;
 323         kfree(res->name);
 324         kfree(res);
 325 }
 326
 327 static struct resource *alloc_cxl_resource(resource_size_t base,
 328                                            resource_size_t n, int id)
 329 {
 330         struct resource *res __free(kfree) = kzalloc(sizeof(*res), GFP_KERNEL);
 331
 332         if (!res)
 333                 return NULL;
 334
 335         res->start = base;
 336         res->end = base + n - 1;
 337         res->flags = IORESOURCE_MEM;
 338         res->name = kasprintf(GFP_KERNEL, "CXL Window %d", id);
 339         if (!res->name)
 340                 return NULL;
 341
 342         return no_free_ptr(res);
 343 }
 344
 345 static int add_or_reset_cxl_resource(struct resource *parent, struct resource *res)
 346 {
 347         int rc = insert_resource(parent, res);
 348
 349         if (rc)
 350                 del_cxl_resource(res);
 351         return rc;
 352 }
 353
 354 DEFINE_FREE(put_cxlrd, struct cxl_root_decoder *,
 355             if (!IS_ERR_OR_NULL(_T)) put_device(&_T->cxlsd.cxld.dev))
 356 DEFINE_FREE(del_cxl_resource, struct resource *, if (_T) del_cxl_resource(_T))
 357 static int __cxl_parse_cfmws(struct acpi_cedt_cfmws *cfmws,
 358                              struct cxl_cfmws_context *ctx)
 359 {
 360         int target_map[CXL_DECODER_MAX_INTERLEAVE];
 361         struct cxl_port *root_port = ctx->root_port;
 362         struct cxl_cxims_context cxims_ctx;
 363         struct device *dev = ctx->dev;
 364         cxl_calc_hb_fn cxl_calc_hb;
 365         struct cxl_decoder *cxld;
 366         unsigned int ways, i, ig;
 367         int rc;
 368
 369         rc = cxl_acpi_cfmws_verify(dev, cfmws);
 370         if (rc)
 371                 return rc;
 372
 373         rc = eiw_to_ways(cfmws->interleave_ways, &ways);
 374         if (rc)
 375                 return rc;
 376         rc = eig_to_granularity(cfmws->granularity, &ig);
 377         if (rc)
 378                 return rc;
 379         for (i = 0; i < ways; i++)
 380                 target_map[i] = cfmws->interleave_targets[i];
 381
 382         struct resource *res __free(del_cxl_resource) = alloc_cxl_resource(
 383                 cfmws->base_hpa, cfmws->window_size, ctx->id++);
 384         if (!res)
 385                 return -ENOMEM;
 386
 387         /* add to the local resource tracking to establish a sort order */
 388         rc = add_or_reset_cxl_resource(ctx->cxl_res, no_free_ptr(res));
 389         if (rc)
 390                 return rc;
 391
 392         if (cfmws->interleave_arithmetic == ACPI_CEDT_CFMWS_ARITHMETIC_MODULO)
 393                 cxl_calc_hb = cxl_hb_modulo;
 394         else
 395                 cxl_calc_hb = cxl_hb_xor;
 396
 397         struct cxl_root_decoder *cxlrd __free(put_cxlrd) =
 398                 cxl_root_decoder_alloc(root_port, ways, cxl_calc_hb);
 399         if (IS_ERR(cxlrd))
 400                 return PTR_ERR(cxlrd);
 401
 402         cxld = &cxlrd->cxlsd.cxld;
 403         cxld->flags = cfmws_to_decoder_flags(cfmws->restrictions);
 404         cxld->target_type = CXL_DECODER_HOSTONLYMEM;
 405         cxld->hpa_range = (struct range) {
 406                 .start = cfmws->base_hpa,
 407                 .end = cfmws->base_hpa + cfmws->window_size - 1,
 408         };
 409         cxld->interleave_ways = ways;
 410         /*
 411          * Minimize the x1 granularity to advertise support for any
 412          * valid region granularity
 413          */
 414         if (ways == 1)
 415                 ig = CXL_DECODER_MIN_GRANULARITY;
 416         cxld->interleave_granularity = ig;
 417
 418         if (cfmws->interleave_arithmetic == ACPI_CEDT_CFMWS_ARITHMETIC_XOR) {
 419                 if (ways != 1 && ways != 3) {
 420                         cxims_ctx = (struct cxl_cxims_context) {
 421                                 .dev = dev,
 422                                 .cxlrd = cxlrd,
 423                         };
 424                         rc = acpi_table_parse_cedt(ACPI_CEDT_TYPE_CXIMS,
 425                                                    cxl_parse_cxims, &cxims_ctx);
 426                         if (rc < 0)
 427                                 return rc;
 428                         if (!cxlrd->platform_data) {
 429                                 dev_err(dev, "No CXIMS for HBIG %u\n", ig);
 430                                 return -EINVAL;
 431                         }
 432                 }
 433         }
 434
 435         cxlrd->qos_class = cfmws->qtg_id;
 436
 437         rc = cxl_decoder_add(cxld, target_map);
 438         if (rc)
 439                 return rc;
 440         return cxl_root_decoder_autoremove(dev, no_free_ptr(cxlrd));
 441 }
 442
 443 static int cxl_parse_cfmws(union acpi_subtable_headers *header, void *arg,
 444                            const unsigned long end)
 445 {
 446         struct acpi_cedt_cfmws *cfmws = (struct acpi_cedt_cfmws *)header;
 447         struct cxl_cfmws_context *ctx = arg;
 448         struct device *dev = ctx->dev;
 449         int rc;
 450
 451         rc = __cxl_parse_cfmws(cfmws, ctx);
 452         if (rc)
 453                 dev_err(dev,
 454                         "Failed to add decode range: [%#llx - %#llx] (%d)\n",
 455                         cfmws->base_hpa,
 456                         cfmws->base_hpa + cfmws->window_size - 1, rc);
 457         else
 458                 dev_dbg(dev, "decode range: node: %d range [%#llx - %#llx]\n",
 459                         phys_to_target_node(cfmws->base_hpa), cfmws->base_hpa,
 460                         cfmws->base_hpa + cfmws->window_size - 1);
 461
 462         /* never fail cxl_acpi load for a single window failure */
 463         return 0;
 464 }
 465
 466 __mock struct acpi_device *to_cxl_host_bridge(struct device *host,
 467                                               struct device *dev)
 468 {
 469         struct acpi_device *adev = to_acpi_device(dev);
 470
 471         if (!acpi_pci_find_root(adev->handle))
 472                 return NULL;
 473
 474         if (strcmp(acpi_device_hid(adev), "ACPI0016") == 0)
 475                 return adev;
 476         return NULL;
 477 }
 478
 479 /* Note, @dev is used by mock_acpi_table_parse_cedt() */
 480 struct cxl_chbs_context {
 481         struct device *dev;
 482         unsigned long long uid;
 483         resource_size_t base;
 484         u32 cxl_version;
 485 };
 486
 487 static int cxl_get_chbs_iter(union acpi_subtable_headers *header, void *arg,
 488                              const unsigned long end)
 489 {
 490         struct cxl_chbs_context *ctx = arg;
 491         struct acpi_cedt_chbs *chbs;
 492
 493         if (ctx->base != CXL_RESOURCE_NONE)
 494                 return 0;
 495
 496         chbs = (struct acpi_cedt_chbs *) header;
 497
 498         if (ctx->uid != chbs->uid)
 499                 return 0;
 500
 501         ctx->cxl_version = chbs->cxl_version;
 502         if (!chbs->base)
 503                 return 0;
 504
 505         if (chbs->cxl_version == ACPI_CEDT_CHBS_VERSION_CXL11 &&
 506             chbs->length != CXL_RCRB_SIZE)
 507                 return 0;
 508
 509         ctx->base = chbs->base;
 510
 511         return 0;
 512 }
 513
 514 static int cxl_get_chbs(struct device *dev, struct acpi_device *hb,
 515                         struct cxl_chbs_context *ctx)
 516 {
 517         unsigned long long uid;
 518         int rc;
 519
 520         rc = acpi_evaluate_integer(hb->handle, METHOD_NAME__UID, NULL, &uid);
 521         if (rc != AE_OK) {
 522                 dev_err(dev, "unable to retrieve _UID\n");
 523                 return -ENOENT;
 524         }
 525
 526         dev_dbg(dev, "UID found: %lld\n", uid);
 527         *ctx = (struct cxl_chbs_context) {
 528                 .dev = dev,
 529                 .uid = uid,
 530                 .base = CXL_RESOURCE_NONE,
 531                 .cxl_version = UINT_MAX,
 532         };
 533
 534         acpi_table_parse_cedt(ACPI_CEDT_TYPE_CHBS, cxl_get_chbs_iter, ctx);
 535
 536         return 0;
 537 }
 538
 539 static int get_genport_coordinates(struct device *dev, struct cxl_dport *dport)
 540 {
 541         struct acpi_device *hb = to_cxl_host_bridge(NULL, dev);
 542         u32 uid;
 543
 544         if (kstrtou32(acpi_device_uid(hb), 0, &uid))
 545                 return -EINVAL;
 546
 547         return acpi_get_genport_coordinates(uid, dport->coord);
 548 }
 549
 550 static int add_host_bridge_dport(struct device *match, void *arg)
 551 {
 552         int ret;
 553         acpi_status rc;
 554         struct device *bridge;
 555         struct cxl_dport *dport;
 556         struct cxl_chbs_context ctx;
 557         struct acpi_pci_root *pci_root;
 558         struct cxl_port *root_port = arg;
 559         struct device *host = root_port->dev.parent;
 560         struct acpi_device *hb = to_cxl_host_bridge(host, match);
 561
 562         if (!hb)
 563                 return 0;
 564
 565         rc = cxl_get_chbs(match, hb, &ctx);
 566         if (rc)
 567                 return rc;
 568
 569         if (ctx.cxl_version == UINT_MAX) {
 570                 dev_warn(match, "No CHBS found for Host Bridge (UID %lld)\n",
 571                          ctx.uid);
 572                 return 0;
 573         }
 574
 575         if (ctx.base == CXL_RESOURCE_NONE) {
 576                 dev_warn(match, "CHBS invalid for Host Bridge (UID %lld)\n",
 577                          ctx.uid);
 578                 return 0;
 579         }
 580
 581         pci_root = acpi_pci_find_root(hb->handle);
 582         bridge = pci_root->bus->bridge;
 583
 584         /*
 585          * In RCH mode, bind the component regs base to the dport. In
 586          * VH mode it will be bound to the CXL host bridge's port
 587          * object later in add_host_bridge_uport().
 588          */
 589         if (ctx.cxl_version == ACPI_CEDT_CHBS_VERSION_CXL11) {
 590                 dev_dbg(match, "RCRB found for UID %lld: %pa\n", ctx.uid,
 591                         &ctx.base);
 592                 dport = devm_cxl_add_rch_dport(root_port, bridge, ctx.uid,
 593                                                ctx.base);
 594         } else {
 595                 dport = devm_cxl_add_dport(root_port, bridge, ctx.uid,
 596                                            CXL_RESOURCE_NONE);
 597         }
 598
 599         if (IS_ERR(dport))
 600                 return PTR_ERR(dport);
 601
 602         ret = get_genport_coordinates(match, dport);
 603         if (ret)
 604                 dev_dbg(match, "Failed to get generic port perf coordinates.\n");
 605
 606         return 0;
 607 }
 608
 609 /*
 610  * A host bridge is a dport to a CFMWS decode and it is a uport to the
 611  * dport (PCIe Root Ports) in the host bridge.
 612  */
 613 static int add_host_bridge_uport(struct device *match, void *arg)
 614 {
 615         struct cxl_port *root_port = arg;
 616         struct device *host = root_port->dev.parent;
 617         struct acpi_device *hb = to_cxl_host_bridge(host, match);
 618         struct acpi_pci_root *pci_root;
 619         struct cxl_dport *dport;
 620         struct cxl_port *port;
 621         struct device *bridge;
 622         struct cxl_chbs_context ctx;
 623         resource_size_t component_reg_phys;
 624         int rc;
 625
 626         if (!hb)
 627                 return 0;
 628
 629         pci_root = acpi_pci_find_root(hb->handle);
 630         bridge = pci_root->bus->bridge;
 631         dport = cxl_find_dport_by_dev(root_port, bridge);
 632         if (!dport) {
 633                 dev_dbg(host, "host bridge expected and not found\n");
 634                 return 0;
 635         }
 636
 637         if (dport->rch) {
 638                 dev_info(bridge, "host supports CXL (restricted)\n");
 639                 return 0;
 640         }
 641
 642         rc = cxl_get_chbs(match, hb, &ctx);
 643         if (rc)
 644                 return rc;
 645
 646         if (ctx.cxl_version == ACPI_CEDT_CHBS_VERSION_CXL11) {
 647                 dev_warn(bridge,
 648                          "CXL CHBS version mismatch, skip port registration\n");
 649                 return 0;
 650         }
 651
 652         component_reg_phys = ctx.base;
 653         if (component_reg_phys != CXL_RESOURCE_NONE)
 654                 dev_dbg(match, "CHBCR found for UID %lld: %pa\n",
 655                         ctx.uid, &component_reg_phys);
 656
 657         rc = devm_cxl_register_pci_bus(host, bridge, pci_root->bus);
 658         if (rc)
 659                 return rc;
 660
 661         port = devm_cxl_add_port(host, bridge, component_reg_phys, dport);
 662         if (IS_ERR(port))
 663                 return PTR_ERR(port);
 664
 665         dev_info(bridge, "host supports CXL\n");
 666
 667         return 0;
 668 }
 669
 670 static int add_root_nvdimm_bridge(struct device *match, void *data)
 671 {
 672         struct cxl_decoder *cxld;
 673         struct cxl_port *root_port = data;
 674         struct cxl_nvdimm_bridge *cxl_nvb;
 675         struct device *host = root_port->dev.parent;
 676
 677         if (!is_root_decoder(match))
 678                 return 0;
 679
 680         cxld = to_cxl_decoder(match);
 681         if (!(cxld->flags & CXL_DECODER_F_PMEM))
 682                 return 0;
 683
 684         cxl_nvb = devm_cxl_add_nvdimm_bridge(host, root_port);
 685         if (IS_ERR(cxl_nvb)) {
 686                 dev_dbg(host, "failed to register pmem\n");
 687                 return PTR_ERR(cxl_nvb);
 688         }
 689         dev_dbg(host, "%s: add: %s\n", dev_name(&root_port->dev),
 690                 dev_name(&cxl_nvb->dev));
 691         return 1;
 692 }
 693
 694 static struct lock_class_key cxl_root_key;
 695
 696 static void cxl_acpi_lock_reset_class(void *dev)
 697 {
 698         device_lock_reset_class(dev);
 699 }
 700
 701 static void cxl_set_public_resource(struct resource *priv, struct resource *pub)
 702 {
 703         priv->desc = (unsigned long) pub;
 704 }
 705
 706 static struct resource *cxl_get_public_resource(struct resource *priv)
 707 {
 708         return (struct resource *) priv->desc;
 709 }
 710
 711 static void remove_cxl_resources(void *data)
 712 {
 713         struct resource *res, *next, *cxl = data;
 714
 715         for (res = cxl->child; res; res = next) {
 716                 struct resource *victim = cxl_get_public_resource(res);
 717
 718                 next = res->sibling;
 719                 remove_resource(res);
 720
 721                 if (victim) {
 722                         remove_resource(victim);
 723                         kfree(victim);
 724                 }
 725
 726                 del_cxl_resource(res);
 727         }
 728 }
 729
 730 /**
 731  * add_cxl_resources() - reflect CXL fixed memory windows in iomem_resource
 732  * @cxl_res: A standalone resource tree where each CXL window is a sibling
 733  *
 734  * Walk each CXL window in @cxl_res and add it to iomem_resource potentially
 735  * expanding its boundaries to ensure that any conflicting resources become
 736  * children. If a window is expanded it may then conflict with a another window
 737  * entry and require the window to be truncated or trimmed. Consider this
 738  * situation:
 739  *
 740  * |-- "CXL Window 0" --||----- "CXL Window 1" -----|
 741  * |--------------- "System RAM" -------------|
 742  *
 743  * ...where platform firmware has established as System RAM resource across 2
 744  * windows, but has left some portion of window 1 for dynamic CXL region
 745  * provisioning. In this case "Window 0" will span the entirety of the "System
 746  * RAM" span, and "CXL Window 1" is truncated to the remaining tail past the end
 747  * of that "System RAM" resource.
 748  */
 749 static int add_cxl_resources(struct resource *cxl_res)
 750 {
 751         struct resource *res, *new, *next;
 752
 753         for (res = cxl_res->child; res; res = next) {
 754                 new = kzalloc(sizeof(*new), GFP_KERNEL);
 755                 if (!new)
 756                         return -ENOMEM;
 757                 new->name = res->name;
 758                 new->start = res->start;
 759                 new->end = res->end;
 760                 new->flags = IORESOURCE_MEM;
 761                 new->desc = IORES_DESC_CXL;
 762
 763                 /*
 764                  * Record the public resource in the private cxl_res tree for
 765                  * later removal.
 766                  */
 767                 cxl_set_public_resource(res, new);
 768
 769                 insert_resource_expand_to_fit(&iomem_resource, new);
 770
 771                 next = res->sibling;
 772                 while (next && resource_overlaps(new, next)) {
 773                         if (resource_contains(new, next)) {
 774                                 struct resource *_next = next->sibling;
 775
 776                                 remove_resource(next);
 777                                 del_cxl_resource(next);
 778                                 next = _next;
 779                         } else
 780                                 next->start = new->end + 1;
 781                 }
 782         }
 783         return 0;
 784 }
 785
 786 static int pair_cxl_resource(struct device *dev, void *data)
 787 {
 788         struct resource *cxl_res = data;
 789         struct resource *p;
 790
 791         if (!is_root_decoder(dev))
 792                 return 0;
 793
 794         for (p = cxl_res->child; p; p = p->sibling) {
 795                 struct cxl_root_decoder *cxlrd = to_cxl_root_decoder(dev);
 796                 struct cxl_decoder *cxld = &cxlrd->cxlsd.cxld;
 797                 struct resource res = {
 798                         .start = cxld->hpa_range.start,
 799                         .end = cxld->hpa_range.end,
 800                         .flags = IORESOURCE_MEM,
 801                 };
 802
 803                 if (resource_contains(p, &res)) {
 804                         cxlrd->res = cxl_get_public_resource(p);
 805                         break;
 806                 }
 807         }
 808
 809         return 0;
 810 }
 811
 812 static int cxl_acpi_probe(struct platform_device *pdev)
 813 {
 814         int rc;
 815         struct resource *cxl_res;
 816         struct cxl_root *cxl_root;
 817         struct cxl_port *root_port;
 818         struct device *host = &pdev->dev;
 819         struct acpi_device *adev = ACPI_COMPANION(host);
 820         struct cxl_cfmws_context ctx;
 821
 822         device_lock_set_class(&pdev->dev, &cxl_root_key);
 823         rc = devm_add_action_or_reset(&pdev->dev, cxl_acpi_lock_reset_class,
 824                                       &pdev->dev);
 825         if (rc)
 826                 return rc;
 827
 828         cxl_res = devm_kzalloc(host, sizeof(*cxl_res), GFP_KERNEL);
 829         if (!cxl_res)
 830                 return -ENOMEM;
 831         cxl_res->name = "CXL mem";
 832         cxl_res->start = 0;
 833         cxl_res->end = -1;
 834         cxl_res->flags = IORESOURCE_MEM;
 835
 836         cxl_root = devm_cxl_add_root(host, &acpi_root_ops);
 837         if (IS_ERR(cxl_root))
 838                 return PTR_ERR(cxl_root);
 839         root_port = &cxl_root->port;
 840
 841         rc = bus_for_each_dev(adev->dev.bus, NULL, root_port,
 842                               add_host_bridge_dport);
 843         if (rc < 0)
 844                 return rc;
 845
 846         rc = devm_add_action_or_reset(host, remove_cxl_resources, cxl_res);
 847         if (rc)
 848                 return rc;
 849
 850         ctx = (struct cxl_cfmws_context) {
 851                 .dev = host,
 852                 .root_port = root_port,
 853                 .cxl_res = cxl_res,
 854         };
 855         rc = acpi_table_parse_cedt(ACPI_CEDT_TYPE_CFMWS, cxl_parse_cfmws, &ctx);
 856         if (rc < 0)
 857                 return -ENXIO;
 858
 859         rc = add_cxl_resources(cxl_res);
 860         if (rc)
 861                 return rc;
 862
 863         /*
 864          * Populate the root decoders with their related iomem resource,
 865          * if present
 866          */
 867         device_for_each_child(&root_port->dev, cxl_res, pair_cxl_resource);
 868
 869         /*
 870          * Root level scanned with host-bridge as dports, now scan host-bridges
 871          * for their role as CXL uports to their CXL-capable PCIe Root Ports.
 872          */
 873         rc = bus_for_each_dev(adev->dev.bus, NULL, root_port,
 874                               add_host_bridge_uport);
 875         if (rc < 0)
 876                 return rc;
 877
 878         if (IS_ENABLED(CONFIG_CXL_PMEM))
 879                 rc = device_for_each_child(&root_port->dev, root_port,
 880                                            add_root_nvdimm_bridge);
 881         if (rc < 0)
 882                 return rc;
 883
 884         /* In case PCI is scanned before ACPI re-trigger memdev attach */
 885         cxl_bus_rescan();
 886         return 0;
 887 }
 888
 889 static const struct acpi_device_id cxl_acpi_ids[] = {
 890         { "ACPI0017" },
 891         { },
 892 };
 893 MODULE_DEVICE_TABLE(acpi, cxl_acpi_ids);
 894
 895 static const struct platform_device_id cxl_test_ids[] = {
 896         { "cxl_acpi" },
 897         { },
 898 };
 899 MODULE_DEVICE_TABLE(platform, cxl_test_ids);
 900
 901 static struct platform_driver cxl_acpi_driver = {
 902         .probe = cxl_acpi_probe,
 903         .driver = {
 904                 .name = KBUILD_MODNAME,
 905                 .acpi_match_table = cxl_acpi_ids,
 906         },
 907         .id_table = cxl_test_ids,
 908 };
 909
 910 static int __init cxl_acpi_init(void)
 911 {
 912         return platform_driver_register(&cxl_acpi_driver);
 913 }
 914
 915 static void __exit cxl_acpi_exit(void)
 916 {
 917         platform_driver_unregister(&cxl_acpi_driver);
 918         cxl_bus_drain();
 919 }
 920
 921 /* load before dax_hmem sees 'Soft Reserved' CXL ranges */
 922 subsys_initcall(cxl_acpi_init);
 923 module_exit(cxl_acpi_exit);
 924 MODULE_LICENSE("GPL v2");
 925 MODULE_IMPORT_NS(CXL);
 926 MODULE_IMPORT_NS(ACPI);