drivers/clk/stm32/clk-stm32mp25.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * Copyright (C) STMicroelectronics 2023 - All Rights Reserved
   4  * Author: Gabriel Fernandez <[email protected]> for STMicroelectronics.
   5  */
   6
   7 #include <linux/clk-provider.h>
   8 #include <linux/platform_device.h>
   9
  10 #include "clk-stm32-core.h"
  11 #include "reset-stm32.h"
  12 #include "stm32mp25_rcc.h"
  13
  14 #include <dt-bindings/clock/st,stm32mp25-rcc.h>
  15 #include <dt-bindings/reset/st,stm32mp25-rcc.h>
  16
  17 enum {
  18         HSE,
  19         HSI,
  20         MSI,
  21         LSE,
  22         LSI,
  23         HSE_DIV2,
  24         ICN_HS_MCU,
  25         ICN_LS_MCU,
  26         ICN_SDMMC,
  27         ICN_DDR,
  28         ICN_DISPLAY,
  29         ICN_HSL,
  30         ICN_NIC,
  31         ICN_VID,
  32         FLEXGEN_07,
  33         FLEXGEN_08,
  34         FLEXGEN_09,
  35         FLEXGEN_10,
  36         FLEXGEN_11,
  37         FLEXGEN_12,
  38         FLEXGEN_13,
  39         FLEXGEN_14,
  40         FLEXGEN_15,
  41         FLEXGEN_16,
  42         FLEXGEN_17,
  43         FLEXGEN_18,
  44         FLEXGEN_19,
  45         FLEXGEN_20,
  46         FLEXGEN_21,
  47         FLEXGEN_22,
  48         FLEXGEN_23,
  49         FLEXGEN_24,
  50         FLEXGEN_25,
  51         FLEXGEN_26,
  52         FLEXGEN_27,
  53         FLEXGEN_28,
  54         FLEXGEN_29,
  55         FLEXGEN_30,
  56         FLEXGEN_31,
  57         FLEXGEN_32,
  58         FLEXGEN_33,
  59         FLEXGEN_34,
  60         FLEXGEN_35,
  61         FLEXGEN_36,
  62         FLEXGEN_37,
  63         FLEXGEN_38,
  64         FLEXGEN_39,
  65         FLEXGEN_40,
  66         FLEXGEN_41,
  67         FLEXGEN_42,
  68         FLEXGEN_43,
  69         FLEXGEN_44,
  70         FLEXGEN_45,
  71         FLEXGEN_46,
  72         FLEXGEN_47,
  73         FLEXGEN_48,
  74         FLEXGEN_49,
  75         FLEXGEN_50,
  76         FLEXGEN_51,
  77         FLEXGEN_52,
  78         FLEXGEN_53,
  79         FLEXGEN_54,
  80         FLEXGEN_55,
  81         FLEXGEN_56,
  82         FLEXGEN_57,
  83         FLEXGEN_58,
  84         FLEXGEN_59,
  85         FLEXGEN_60,
  86         FLEXGEN_61,
  87         FLEXGEN_62,
  88         FLEXGEN_63,
  89         ICN_APB1,
  90         ICN_APB2,
  91         ICN_APB3,
  92         ICN_APB4,
  93         ICN_APBDBG,
  94         TIMG1,
  95         TIMG2,
  96         PLL3,
  97         DSI_TXBYTE,
  98 };
  99
 100 static const struct clk_parent_data adc12_src[] = {
 101         { .index = FLEXGEN_46 },
 102         { .index = ICN_LS_MCU },
 103 };
 104
 105 static const struct clk_parent_data adc3_src[] = {
 106         { .index = FLEXGEN_47 },
 107         { .index = ICN_LS_MCU },
 108         { .index = FLEXGEN_46 },
 109 };
 110
 111 static const struct clk_parent_data usb2phy1_src[] = {
 112         { .index = FLEXGEN_57 },
 113         { .index = HSE_DIV2 },
 114 };
 115
 116 static const struct clk_parent_data usb2phy2_src[] = {
 117         { .index = FLEXGEN_58 },
 118         { .index = HSE_DIV2 },
 119 };
 120
 121 static const struct clk_parent_data usb3pciphy_src[] = {
 122         { .index = FLEXGEN_34 },
 123         { .index = HSE_DIV2 },
 124 };
 125
 126 static struct clk_stm32_gate ck_ker_ltdc;
 127
 128 static const struct clk_parent_data dsiblane_src[] = {
 129         { .index = DSI_TXBYTE },
 130         { .hw = &ck_ker_ltdc.hw },
 131 };
 132
 133 static const struct clk_parent_data dsiphy_src[] = {
 134         { .index = FLEXGEN_28 },
 135         { .index = HSE },
 136 };
 137
 138 static const struct clk_parent_data lvdsphy_src[] = {
 139         { .index = FLEXGEN_32 },
 140         { .index = HSE },
 141 };
 142
 143 static const struct clk_parent_data dts_src[] = {
 144         { .index = HSI },
 145         { .index = HSE },
 146         { .index = MSI },
 147 };
 148
 149 static const struct clk_parent_data mco1_src[] = {
 150         { .index = FLEXGEN_61 },
 151 };
 152
 153 static const struct clk_parent_data mco2_src[] = {
 154         { .index = FLEXGEN_62 },
 155 };
 156
 157 enum enum_mux_cfg {
 158         MUX_ADC12,
 159         MUX_ADC3,
 160         MUX_DSIBLANE,
 161         MUX_DSIPHY,
 162         MUX_DTS,
 163         MUX_LVDSPHY,
 164         MUX_MCO1,
 165         MUX_MCO2,
 166         MUX_USB2PHY1,
 167         MUX_USB2PHY2,
 168         MUX_USB3PCIEPHY,
 169         MUX_NB
 170 };
 171
 172 #define MUX_CFG(id, _offset, _shift, _witdh)    \
 173         [id] = {                                \
 174                 .offset         = (_offset),    \
 175                 .shift          = (_shift),     \
 176                 .width          = (_witdh),     \
 177         }
 178
 179 static const struct stm32_mux_cfg stm32mp25_muxes[MUX_NB] = {
 180         MUX_CFG(MUX_ADC12,              RCC_ADC12CFGR,          12,     1),
 181         MUX_CFG(MUX_ADC3,               RCC_ADC3CFGR,           12,     2),
 182         MUX_CFG(MUX_DSIBLANE,           RCC_DSICFGR,            12,     1),
 183         MUX_CFG(MUX_DSIPHY,             RCC_DSICFGR,            15,     1),
 184         MUX_CFG(MUX_DTS,                RCC_DTSCFGR,            12,     2),
 185         MUX_CFG(MUX_LVDSPHY,            RCC_LVDSCFGR,           15,     1),
 186         MUX_CFG(MUX_MCO1,               RCC_MCO1CFGR,           0,      1),
 187         MUX_CFG(MUX_MCO2,               RCC_MCO2CFGR,           0,      1),
 188         MUX_CFG(MUX_USB2PHY1,           RCC_USB2PHY1CFGR,       15,     1),
 189         MUX_CFG(MUX_USB2PHY2,           RCC_USB2PHY2CFGR,       15,     1),
 190         MUX_CFG(MUX_USB3PCIEPHY,        RCC_USB3PCIEPHYCFGR,    15,     1),
 191 };
 192
 193 enum enum_gate_cfg {
 194         GATE_ADC12,
 195         GATE_ADC3,
 196         GATE_ADF1,
 197         GATE_CCI,
 198         GATE_CRC,
 199         GATE_CRYP1,
 200         GATE_CRYP2,
 201         GATE_CSI,
 202         GATE_DCMIPP,
 203         GATE_DSI,
 204         GATE_DTS,
 205         GATE_ETH1,
 206         GATE_ETH1MAC,
 207         GATE_ETH1RX,
 208         GATE_ETH1STP,
 209         GATE_ETH1TX,
 210         GATE_ETH2,
 211         GATE_ETH2MAC,
 212         GATE_ETH2RX,
 213         GATE_ETH2STP,
 214         GATE_ETH2TX,
 215         GATE_ETHSW,
 216         GATE_ETHSWACMCFG,
 217         GATE_ETHSWACMMSG,
 218         GATE_ETHSWMAC,
 219         GATE_ETHSWREF,
 220         GATE_FDCAN,
 221         GATE_GPU,
 222         GATE_HASH,
 223         GATE_HDP,
 224         GATE_I2C1,
 225         GATE_I2C2,
 226         GATE_I2C3,
 227         GATE_I2C4,
 228         GATE_I2C5,
 229         GATE_I2C6,
 230         GATE_I2C7,
 231         GATE_I2C8,
 232         GATE_I3C1,
 233         GATE_I3C2,
 234         GATE_I3C3,
 235         GATE_I3C4,
 236         GATE_IS2M,
 237         GATE_IWDG1,
 238         GATE_IWDG2,
 239         GATE_IWDG3,
 240         GATE_IWDG4,
 241         GATE_IWDG5,
 242         GATE_LPTIM1,
 243         GATE_LPTIM2,
 244         GATE_LPTIM3,
 245         GATE_LPTIM4,
 246         GATE_LPTIM5,
 247         GATE_LPUART1,
 248         GATE_LTDC,
 249         GATE_LVDS,
 250         GATE_MCO1,
 251         GATE_MCO2,
 252         GATE_MDF1,
 253         GATE_OSPIIOM,
 254         GATE_PCIE,
 255         GATE_PKA,
 256         GATE_RNG,
 257         GATE_SAES,
 258         GATE_SAI1,
 259         GATE_SAI2,
 260         GATE_SAI3,
 261         GATE_SAI4,
 262         GATE_SDMMC1,
 263         GATE_SDMMC2,
 264         GATE_SDMMC3,
 265         GATE_SERC,
 266         GATE_SPDIFRX,
 267         GATE_SPI1,
 268         GATE_SPI2,
 269         GATE_SPI3,
 270         GATE_SPI4,
 271         GATE_SPI5,
 272         GATE_SPI6,
 273         GATE_SPI7,
 274         GATE_SPI8,
 275         GATE_TIM1,
 276         GATE_TIM10,
 277         GATE_TIM11,
 278         GATE_TIM12,
 279         GATE_TIM13,
 280         GATE_TIM14,
 281         GATE_TIM15,
 282         GATE_TIM16,
 283         GATE_TIM17,
 284         GATE_TIM2,
 285         GATE_TIM20,
 286         GATE_TIM3,
 287         GATE_TIM4,
 288         GATE_TIM5,
 289         GATE_TIM6,
 290         GATE_TIM7,
 291         GATE_TIM8,
 292         GATE_UART4,
 293         GATE_UART5,
 294         GATE_UART7,
 295         GATE_UART8,
 296         GATE_UART9,
 297         GATE_USART1,
 298         GATE_USART2,
 299         GATE_USART3,
 300         GATE_USART6,
 301         GATE_USBH,
 302         GATE_USB2PHY1,
 303         GATE_USB2PHY2,
 304         GATE_USB3DR,
 305         GATE_USB3PCIEPHY,
 306         GATE_USBTC,
 307         GATE_VDEC,
 308         GATE_VENC,
 309         GATE_VREF,
 310         GATE_WWDG1,
 311         GATE_WWDG2,
 312         GATE_NB
 313 };
 314
 315 #define GATE_CFG(id, _offset, _bit_idx, _offset_clr)    \
 316         [id] = {                                        \
 317                 .offset         = (_offset),            \
 318                 .bit_idx        = (_bit_idx),           \
 319                 .set_clr        = (_offset_clr),        \
 320         }
 321
 322 static const struct stm32_gate_cfg stm32mp25_gates[GATE_NB] = {
 323         GATE_CFG(GATE_ADC12,            RCC_ADC12CFGR,          1,      0),
 324         GATE_CFG(GATE_ADC3,             RCC_ADC3CFGR,           1,      0),
 325         GATE_CFG(GATE_ADF1,             RCC_ADF1CFGR,           1,      0),
 326         GATE_CFG(GATE_CCI,              RCC_CCICFGR,            1,      0),
 327         GATE_CFG(GATE_CRC,              RCC_CRCCFGR,            1,      0),
 328         GATE_CFG(GATE_CRYP1,            RCC_CRYP1CFGR,          1,      0),
 329         GATE_CFG(GATE_CRYP2,            RCC_CRYP2CFGR,          1,      0),
 330         GATE_CFG(GATE_CSI,              RCC_CSICFGR,            1,      0),
 331         GATE_CFG(GATE_DCMIPP,           RCC_DCMIPPCFGR,         1,      0),
 332         GATE_CFG(GATE_DSI,              RCC_DSICFGR,            1,      0),
 333         GATE_CFG(GATE_DTS,              RCC_DTSCFGR,            1,      0),
 334         GATE_CFG(GATE_ETH1,             RCC_ETH1CFGR,           5,      0),
 335         GATE_CFG(GATE_ETH1MAC,          RCC_ETH1CFGR,           1,      0),
 336         GATE_CFG(GATE_ETH1RX,           RCC_ETH1CFGR,           10,     0),
 337         GATE_CFG(GATE_ETH1STP,          RCC_ETH1CFGR,           4,      0),
 338         GATE_CFG(GATE_ETH1TX,           RCC_ETH1CFGR,           8,      0),
 339         GATE_CFG(GATE_ETH2,             RCC_ETH2CFGR,           5,      0),
 340         GATE_CFG(GATE_ETH2MAC,          RCC_ETH2CFGR,           1,      0),
 341         GATE_CFG(GATE_ETH2RX,           RCC_ETH2CFGR,           10,     0),
 342         GATE_CFG(GATE_ETH2STP,          RCC_ETH2CFGR,           4,      0),
 343         GATE_CFG(GATE_ETH2TX,           RCC_ETH2CFGR,           8,      0),
 344         GATE_CFG(GATE_ETHSW,            RCC_ETHSWCFGR,          5,      0),
 345         GATE_CFG(GATE_ETHSWACMCFG,      RCC_ETHSWACMCFGR,       1,      0),
 346         GATE_CFG(GATE_ETHSWACMMSG,      RCC_ETHSWACMMSGCFGR,    1,      0),
 347         GATE_CFG(GATE_ETHSWMAC,         RCC_ETHSWCFGR,          1,      0),
 348         GATE_CFG(GATE_ETHSWREF,         RCC_ETHSWCFGR,          21,     0),
 349         GATE_CFG(GATE_FDCAN,            RCC_FDCANCFGR,          1,      0),
 350         GATE_CFG(GATE_GPU,              RCC_GPUCFGR,            1,      0),
 351         GATE_CFG(GATE_HASH,             RCC_HASHCFGR,           1,      0),
 352         GATE_CFG(GATE_HDP,              RCC_HDPCFGR,            1,      0),
 353         GATE_CFG(GATE_I2C1,             RCC_I2C1CFGR,           1,      0),
 354         GATE_CFG(GATE_I2C2,             RCC_I2C2CFGR,           1,      0),
 355         GATE_CFG(GATE_I2C3,             RCC_I2C3CFGR,           1,      0),
 356         GATE_CFG(GATE_I2C4,             RCC_I2C4CFGR,           1,      0),
 357         GATE_CFG(GATE_I2C5,             RCC_I2C5CFGR,           1,      0),
 358         GATE_CFG(GATE_I2C6,             RCC_I2C6CFGR,           1,      0),
 359         GATE_CFG(GATE_I2C7,             RCC_I2C7CFGR,           1,      0),
 360         GATE_CFG(GATE_I2C8,             RCC_I2C8CFGR,           1,      0),
 361         GATE_CFG(GATE_I3C1,             RCC_I3C1CFGR,           1,      0),
 362         GATE_CFG(GATE_I3C2,             RCC_I3C2CFGR,           1,      0),
 363         GATE_CFG(GATE_I3C3,             RCC_I3C3CFGR,           1,      0),
 364         GATE_CFG(GATE_I3C4,             RCC_I3C4CFGR,           1,      0),
 365         GATE_CFG(GATE_IS2M,             RCC_IS2MCFGR,           1,      0),
 366         GATE_CFG(GATE_IWDG1,            RCC_IWDG1CFGR,          1,      0),
 367         GATE_CFG(GATE_IWDG2,            RCC_IWDG2CFGR,          1,      0),
 368         GATE_CFG(GATE_IWDG3,            RCC_IWDG3CFGR,          1,      0),
 369         GATE_CFG(GATE_IWDG4,            RCC_IWDG4CFGR,          1,      0),
 370         GATE_CFG(GATE_IWDG5,            RCC_IWDG5CFGR,          1,      0),
 371         GATE_CFG(GATE_LPTIM1,           RCC_LPTIM1CFGR,         1,      0),
 372         GATE_CFG(GATE_LPTIM2,           RCC_LPTIM2CFGR,         1,      0),
 373         GATE_CFG(GATE_LPTIM3,           RCC_LPTIM3CFGR,         1,      0),
 374         GATE_CFG(GATE_LPTIM4,           RCC_LPTIM4CFGR,         1,      0),
 375         GATE_CFG(GATE_LPTIM5,           RCC_LPTIM5CFGR,         1,      0),
 376         GATE_CFG(GATE_LPUART1,          RCC_LPUART1CFGR,        1,      0),
 377         GATE_CFG(GATE_LTDC,             RCC_LTDCCFGR,           1,      0),
 378         GATE_CFG(GATE_LVDS,             RCC_LVDSCFGR,           1,      0),
 379         GATE_CFG(GATE_MCO1,             RCC_MCO1CFGR,           8,      0),
 380         GATE_CFG(GATE_MCO2,             RCC_MCO2CFGR,           8,      0),
 381         GATE_CFG(GATE_MDF1,             RCC_MDF1CFGR,           1,      0),
 382         GATE_CFG(GATE_OSPIIOM,          RCC_OSPIIOMCFGR,        1,      0),
 383         GATE_CFG(GATE_PCIE,             RCC_PCIECFGR,           1,      0),
 384         GATE_CFG(GATE_PKA,              RCC_PKACFGR,            1,      0),
 385         GATE_CFG(GATE_RNG,              RCC_RNGCFGR,            1,      0),
 386         GATE_CFG(GATE_SAES,             RCC_SAESCFGR,           1,      0),
 387         GATE_CFG(GATE_SAI1,             RCC_SAI1CFGR,           1,      0),
 388         GATE_CFG(GATE_SAI2,             RCC_SAI2CFGR,           1,      0),
 389         GATE_CFG(GATE_SAI3,             RCC_SAI3CFGR,           1,      0),
 390         GATE_CFG(GATE_SAI4,             RCC_SAI4CFGR,           1,      0),
 391         GATE_CFG(GATE_SDMMC1,           RCC_SDMMC1CFGR,         1,      0),
 392         GATE_CFG(GATE_SDMMC2,           RCC_SDMMC2CFGR,         1,      0),
 393         GATE_CFG(GATE_SDMMC3,           RCC_SDMMC3CFGR,         1,      0),
 394         GATE_CFG(GATE_SERC,             RCC_SERCCFGR,           1,      0),
 395         GATE_CFG(GATE_SPDIFRX,          RCC_SPDIFRXCFGR,        1,      0),
 396         GATE_CFG(GATE_SPI1,             RCC_SPI1CFGR,           1,      0),
 397         GATE_CFG(GATE_SPI2,             RCC_SPI2CFGR,           1,      0),
 398         GATE_CFG(GATE_SPI3,             RCC_SPI3CFGR,           1,      0),
 399         GATE_CFG(GATE_SPI4,             RCC_SPI4CFGR,           1,      0),
 400         GATE_CFG(GATE_SPI5,             RCC_SPI5CFGR,           1,      0),
 401         GATE_CFG(GATE_SPI6,             RCC_SPI6CFGR,           1,      0),
 402         GATE_CFG(GATE_SPI7,             RCC_SPI7CFGR,           1,      0),
 403         GATE_CFG(GATE_SPI8,             RCC_SPI8CFGR,           1,      0),
 404         GATE_CFG(GATE_TIM1,             RCC_TIM1CFGR,           1,      0),
 405         GATE_CFG(GATE_TIM10,            RCC_TIM10CFGR,          1,      0),
 406         GATE_CFG(GATE_TIM11,            RCC_TIM11CFGR,          1,      0),
 407         GATE_CFG(GATE_TIM12,            RCC_TIM12CFGR,          1,      0),
 408         GATE_CFG(GATE_TIM13,            RCC_TIM13CFGR,          1,      0),
 409         GATE_CFG(GATE_TIM14,            RCC_TIM14CFGR,          1,      0),
 410         GATE_CFG(GATE_TIM15,            RCC_TIM15CFGR,          1,      0),
 411         GATE_CFG(GATE_TIM16,            RCC_TIM16CFGR,          1,      0),
 412         GATE_CFG(GATE_TIM17,            RCC_TIM17CFGR,          1,      0),
 413         GATE_CFG(GATE_TIM2,             RCC_TIM2CFGR,           1,      0),
 414         GATE_CFG(GATE_TIM20,            RCC_TIM20CFGR,          1,      0),
 415         GATE_CFG(GATE_TIM3,             RCC_TIM3CFGR,           1,      0),
 416         GATE_CFG(GATE_TIM4,             RCC_TIM4CFGR,           1,      0),
 417         GATE_CFG(GATE_TIM5,             RCC_TIM5CFGR,           1,      0),
 418         GATE_CFG(GATE_TIM6,             RCC_TIM6CFGR,           1,      0),
 419         GATE_CFG(GATE_TIM7,             RCC_TIM7CFGR,           1,      0),
 420         GATE_CFG(GATE_TIM8,             RCC_TIM8CFGR,           1,      0),
 421         GATE_CFG(GATE_UART4,            RCC_UART4CFGR,          1,      0),
 422         GATE_CFG(GATE_UART5,            RCC_UART5CFGR,          1,      0),
 423         GATE_CFG(GATE_UART7,            RCC_UART7CFGR,          1,      0),
 424         GATE_CFG(GATE_UART8,            RCC_UART8CFGR,          1,      0),
 425         GATE_CFG(GATE_UART9,            RCC_UART9CFGR,          1,      0),
 426         GATE_CFG(GATE_USART1,           RCC_USART1CFGR,         1,      0),
 427         GATE_CFG(GATE_USART2,           RCC_USART2CFGR,         1,      0),
 428         GATE_CFG(GATE_USART3,           RCC_USART3CFGR,         1,      0),
 429         GATE_CFG(GATE_USART6,           RCC_USART6CFGR,         1,      0),
 430         GATE_CFG(GATE_USBH,             RCC_USBHCFGR,           1,      0),
 431         GATE_CFG(GATE_USB2PHY1,         RCC_USB2PHY1CFGR,       1,      0),
 432         GATE_CFG(GATE_USB2PHY2,         RCC_USB2PHY2CFGR,       1,      0),
 433         GATE_CFG(GATE_USB3DR,           RCC_USB3DRCFGR,         1,      0),
 434         GATE_CFG(GATE_USB3PCIEPHY,      RCC_USB3PCIEPHYCFGR,    1,      0),
 435         GATE_CFG(GATE_USBTC,            RCC_USBTCCFGR,          1,      0),
 436         GATE_CFG(GATE_VDEC,             RCC_VDECCFGR,           1,      0),
 437         GATE_CFG(GATE_VENC,             RCC_VENCCFGR,           1,      0),
 438         GATE_CFG(GATE_VREF,             RCC_VREFCFGR,           1,      0),
 439         GATE_CFG(GATE_WWDG1,            RCC_WWDG1CFGR,          1,      0),
 440         GATE_CFG(GATE_WWDG2,            RCC_WWDG2CFGR,          1,      0),
 441 };
 442
 443 #define CLK_HW_INIT_INDEX(_name, _parent, _ops, _flags)         \
 444         (&(struct clk_init_data) {                                      \
 445                 .flags          = _flags,                               \
 446                 .name           = _name,                                \
 447                 .parent_data    = (const struct clk_parent_data[]) {    \
 448                                         { .index = _parent },           \
 449                                   },                                    \
 450                 .num_parents    = 1,                                    \
 451                 .ops            = _ops,                                 \
 452         })
 453
 454 /* ADC */
 455 static struct clk_stm32_gate ck_icn_p_adc12 = {
 456         .gate_id = GATE_ADC12,
 457         .hw.init = CLK_HW_INIT_INDEX("ck_icn_p_adc12", ICN_LS_MCU, &clk_stm32_gate_ops, 0),
 458 };
 459
 460 static struct clk_stm32_composite ck_ker_adc12 = {
 461         .gate_id = GATE_ADC12,
 462         .mux_id = MUX_ADC12,
 463         .div_id = NO_STM32_DIV,
 464         .hw.init = CLK_HW_INIT_PARENTS_DATA("ck_ker_adc12", adc12_src, &clk_stm32_composite_ops, 0),
 465 };
 466
 467 static struct clk_stm32_gate ck_icn_p_adc3 = {
 468         .gate_id = GATE_ADC3,
 469         .hw.init = CLK_HW_INIT_INDEX("ck_icn_p_adc3", ICN_LS_MCU, &clk_stm32_gate_ops, 0),
 470 };
 471
 472 static struct clk_stm32_composite ck_ker_adc3 = {
 473         .gate_id = GATE_ADC3,
 474         .mux_id = MUX_ADC3,
 475         .div_id = NO_STM32_DIV,
 476         .hw.init = CLK_HW_INIT_PARENTS_DATA("ck_ker_adc3", adc3_src, &clk_stm32_composite_ops, 0),
 477 };
 478
 479 /* ADF */
 480 static struct clk_stm32_gate ck_icn_p_adf1 = {
 481         .gate_id = GATE_ADF1,
 482         .hw.init = CLK_HW_INIT_INDEX("ck_icn_p_adf1", ICN_LS_MCU, &clk_stm32_gate_ops, 0),
 483 };
 484
 485 static struct clk_stm32_gate ck_ker_adf1 = {
 486         .gate_id = GATE_ADF1,
 487         .hw.init = CLK_HW_INIT_INDEX("ck_ker_adf1", FLEXGEN_42, &clk_stm32_gate_ops, 0),
 488 };
 489
 490 /* DCMI */
 491 static struct clk_stm32_gate ck_icn_p_cci = {
 492         .gate_id = GATE_CCI,
 493         .hw.init = CLK_HW_INIT_INDEX("ck_icn_p_cci", ICN_LS_MCU, &clk_stm32_gate_ops, 0),
 494 };
 495
 496 /* CSI-HOST */
 497 static struct clk_stm32_gate ck_icn_p_csi = {
 498         .gate_id = GATE_CSI,
 499         .hw.init = CLK_HW_INIT_INDEX("ck_icn_p_csi", ICN_APB4, &clk_stm32_gate_ops, 0),
 500 };
 501
 502 static struct clk_stm32_gate ck_ker_csi = {
 503         .gate_id = GATE_CSI,
 504         .hw.init = CLK_HW_INIT_INDEX("ck_ker_csi", FLEXGEN_29, &clk_stm32_gate_ops, 0),
 505 };
 506
 507 static struct clk_stm32_gate ck_ker_csitxesc = {
 508         .gate_id = GATE_CSI,
 509         .hw.init = CLK_HW_INIT_INDEX("ck_ker_csitxesc", FLEXGEN_30, &clk_stm32_gate_ops, 0),
 510 };
 511
 512 /* CSI-PHY */
 513 static struct clk_stm32_gate ck_ker_csiphy = {
 514         .gate_id = GATE_CSI,
 515         .hw.init = CLK_HW_INIT_INDEX("ck_ker_csiphy", FLEXGEN_31, &clk_stm32_gate_ops, 0),
 516 };
 517
 518 /* DCMIPP */
 519 static struct clk_stm32_gate ck_icn_p_dcmipp = {
 520         .gate_id = GATE_DCMIPP,
 521         .hw.init = CLK_HW_INIT_INDEX("ck_icn_p_dcmipp", ICN_APB4, &clk_stm32_gate_ops, 0),
 522 };
 523
 524 /* CRC */
 525 static struct clk_stm32_gate ck_icn_p_crc = {
 526         .gate_id = GATE_CRC,
 527         .hw.init = CLK_HW_INIT_INDEX("ck_icn_p_crc", ICN_LS_MCU, &clk_stm32_gate_ops, 0),
 528 };
 529
 530 /* CRYP */
 531 static struct clk_stm32_gate ck_icn_p_cryp1 = {
 532         .gate_id = GATE_CRYP1,
 533         .hw.init = CLK_HW_INIT_INDEX("ck_icn_p_cryp1", ICN_LS_MCU, &clk_stm32_gate_ops, 0),
 534 };
 535
 536 static struct clk_stm32_gate ck_icn_p_cryp2 = {
 537         .gate_id = GATE_CRYP2,
 538         .hw.init = CLK_HW_INIT_INDEX("ck_icn_p_cryp2", ICN_LS_MCU, &clk_stm32_gate_ops, 0),
 539 };
 540
 541 /* DBG & TRACE*/
 542 /* Trace and debug clocks are managed by SCMI */
 543
 544 /* LTDC */
 545 static struct clk_stm32_gate ck_icn_p_ltdc = {
 546         .gate_id = GATE_LTDC,
 547         .hw.init = CLK_HW_INIT_INDEX("ck_icn_p_ltdc", ICN_APB4, &clk_stm32_gate_ops, 0),
 548 };
 549
 550 static struct clk_stm32_gate ck_ker_ltdc = {
 551         .gate_id = GATE_LTDC,
 552         .hw.init = CLK_HW_INIT_INDEX("ck_ker_ltdc", FLEXGEN_27, &clk_stm32_gate_ops,
 553                                      CLK_SET_RATE_PARENT),
 554 };
 555
 556 /* DSI */
 557 static struct clk_stm32_gate ck_icn_p_dsi = {
 558         .gate_id = GATE_DSI,
 559         .hw.init = CLK_HW_INIT_INDEX("ck_icn_p_dsi", ICN_APB4, &clk_stm32_gate_ops, 0),
 560 };
 561
 562 static struct clk_stm32_composite clk_lanebyte = {
 563         .gate_id = GATE_DSI,
 564         .mux_id = MUX_DSIBLANE,
 565         .div_id = NO_STM32_DIV,
 566         .hw.init = CLK_HW_INIT_PARENTS_DATA("clk_lanebyte", dsiblane_src,
 567                                             &clk_stm32_composite_ops, 0),
 568 };
 569
 570 /* LVDS */
 571 static struct clk_stm32_gate ck_icn_p_lvds = {
 572         .gate_id = GATE_LVDS,
 573         .hw.init = CLK_HW_INIT_INDEX("ck_icn_p_lvds", ICN_APB4, &clk_stm32_gate_ops, 0),
 574 };
 575
 576 /* DSI PHY */
 577 static struct clk_stm32_composite clk_phy_dsi = {
 578         .gate_id = GATE_DSI,
 579         .mux_id = MUX_DSIPHY,
 580         .div_id = NO_STM32_DIV,
 581         .hw.init = CLK_HW_INIT_PARENTS_DATA("clk_phy_dsi", dsiphy_src,
 582                                             &clk_stm32_composite_ops, 0),
 583 };
 584
 585 /* LVDS PHY */
 586 static struct clk_stm32_composite ck_ker_lvdsphy = {
 587         .gate_id = GATE_LVDS,
 588         .mux_id = MUX_LVDSPHY,
 589         .div_id = NO_STM32_DIV,
 590         .hw.init = CLK_HW_INIT_PARENTS_DATA("ck_ker_lvdsphy", lvdsphy_src,
 591                                             &clk_stm32_composite_ops, 0),
 592 };
 593
 594 /* DTS */
 595 static struct clk_stm32_composite ck_ker_dts = {
 596         .gate_id = GATE_DTS,
 597         .mux_id = MUX_DTS,
 598         .div_id = NO_STM32_DIV,
 599         .hw.init = CLK_HW_INIT_PARENTS_DATA("ck_ker_dts", dts_src,
 600                                             &clk_stm32_composite_ops, 0),
 601 };
 602
 603 /* ETHERNET */
 604 static struct clk_stm32_gate ck_icn_p_eth1 = {
 605         .gate_id = GATE_ETH1,
 606         .hw.init = CLK_HW_INIT_INDEX("ck_icn_p_eth1", ICN_LS_MCU, &clk_stm32_gate_ops, 0),
 607 };
 608
 609 static struct clk_stm32_gate ck_ker_eth1stp = {
 610         .gate_id = GATE_ETH1STP,
 611         .hw.init = CLK_HW_INIT_INDEX("ck_ker_eth1stp", ICN_LS_MCU, &clk_stm32_gate_ops, 0),
 612 };
 613
 614 static struct clk_stm32_gate ck_ker_eth1 = {
 615         .gate_id = GATE_ETH1,
 616         .hw.init = CLK_HW_INIT_INDEX("ck_ker_eth1", FLEXGEN_54, &clk_stm32_gate_ops, 0),
 617 };
 618
 619 static struct clk_stm32_gate ck_ker_eth1ptp = {
 620         .gate_id = GATE_ETH1,
 621         .hw.init = CLK_HW_INIT_INDEX("ck_ker_eth1ptp", FLEXGEN_56, &clk_stm32_gate_ops, 0),
 622 };
 623
 624 static struct clk_stm32_gate ck_ker_eth1mac = {
 625         .gate_id = GATE_ETH1MAC,
 626         .hw.init = CLK_HW_INIT_INDEX("ck_ker_eth1mac", ICN_LS_MCU, &clk_stm32_gate_ops, 0),
 627 };
 628
 629 static struct clk_stm32_gate ck_ker_eth1tx = {
 630         .gate_id = GATE_ETH1TX,
 631         .hw.init = CLK_HW_INIT_INDEX("ck_ker_eth1tx", ICN_LS_MCU, &clk_stm32_gate_ops, 0),
 632 };
 633
 634 static struct clk_stm32_gate ck_ker_eth1rx = {
 635         .gate_id = GATE_ETH1RX,
 636         .hw.init = CLK_HW_INIT_INDEX("ck_ker_eth1rx", ICN_LS_MCU, &clk_stm32_gate_ops, 0),
 637 };
 638
 639 static struct clk_stm32_gate ck_icn_p_eth2 = {
 640         .gate_id = GATE_ETH2,
 641         .hw.init = CLK_HW_INIT_INDEX("ck_icn_p_eth2", ICN_LS_MCU, &clk_stm32_gate_ops, 0),
 642 };
 643
 644 static struct clk_stm32_gate ck_ker_eth2stp = {
 645         .gate_id = GATE_ETH2STP,
 646         .hw.init = CLK_HW_INIT_INDEX("ck_ker_eth2stp", ICN_LS_MCU, &clk_stm32_gate_ops, 0),
 647 };
 648
 649 static struct clk_stm32_gate ck_ker_eth2 = {
 650         .gate_id = GATE_ETH2,
 651         .hw.init = CLK_HW_INIT_INDEX("ck_ker_eth2", FLEXGEN_55, &clk_stm32_gate_ops, 0),
 652 };
 653
 654 static struct clk_stm32_gate ck_ker_eth2ptp = {
 655         .gate_id = GATE_ETH2,
 656         .hw.init = CLK_HW_INIT_INDEX("ck_ker_eth2ptp", FLEXGEN_56, &clk_stm32_gate_ops, 0),
 657 };
 658
 659 static struct clk_stm32_gate ck_ker_eth2mac = {
 660         .gate_id = GATE_ETH2MAC,
 661         .hw.init = CLK_HW_INIT_INDEX("ck_ker_eth2mac", ICN_LS_MCU, &clk_stm32_gate_ops, 0),
 662 };
 663
 664 static struct clk_stm32_gate ck_ker_eth2tx = {
 665         .gate_id = GATE_ETH2TX,
 666         .hw.init = CLK_HW_INIT_INDEX("ck_ker_eth2tx", ICN_LS_MCU, &clk_stm32_gate_ops, 0),
 667 };
 668
 669 static struct clk_stm32_gate ck_ker_eth2rx = {
 670         .gate_id = GATE_ETH2RX,
 671         .hw.init = CLK_HW_INIT_INDEX("ck_ker_eth2rx", ICN_LS_MCU, &clk_stm32_gate_ops, 0),
 672 };
 673
 674 static struct clk_stm32_gate ck_icn_p_ethsw = {
 675         .gate_id = GATE_ETHSWMAC,
 676         .hw.init = CLK_HW_INIT_INDEX("ck_icn_p_ethsw", ICN_LS_MCU, &clk_stm32_gate_ops, 0),
 677 };
 678
 679 static struct clk_stm32_gate ck_ker_ethsw = {
 680         .gate_id = GATE_ETHSW,
 681         .hw.init = CLK_HW_INIT_INDEX("ck_ker_ethsw", FLEXGEN_54, &clk_stm32_gate_ops, 0),
 682 };
 683
 684 static struct clk_stm32_gate ck_ker_ethswref = {
 685         .gate_id = GATE_ETHSWREF,
 686         .hw.init = CLK_HW_INIT_INDEX("ck_ker_ethswref", FLEXGEN_60, &clk_stm32_gate_ops, 0),
 687 };
 688
 689 static struct clk_stm32_gate ck_icn_p_ethsw_acm_cfg = {
 690         .gate_id = GATE_ETHSWACMCFG,
 691         .hw.init = CLK_HW_INIT_INDEX("ck_icn_p_ethsw_acm_cfg", ICN_LS_MCU,
 692                                      &clk_stm32_gate_ops, 0),
 693 };
 694
 695 static struct clk_stm32_gate ck_icn_p_ethsw_acm_msg = {
 696         .gate_id = GATE_ETHSWACMMSG,
 697         .hw.init = CLK_HW_INIT_INDEX("ck_icn_p_ethsw_acm_msg", ICN_LS_MCU,
 698                                      &clk_stm32_gate_ops, 0),
 699 };
 700
 701 /* FDCAN */
 702 static struct clk_stm32_gate ck_icn_p_fdcan = {
 703         .gate_id = GATE_FDCAN,
 704         .hw.init = CLK_HW_INIT_INDEX("ck_icn_p_fdcan", ICN_APB2, &clk_stm32_gate_ops, 0),
 705 };
 706
 707 static struct clk_stm32_gate ck_ker_fdcan = {
 708         .gate_id = GATE_FDCAN,
 709         .hw.init = CLK_HW_INIT_INDEX("ck_ker_fdcan", FLEXGEN_26, &clk_stm32_gate_ops, 0),
 710 };
 711
 712 /* GPU */
 713 static struct clk_stm32_gate ck_icn_m_gpu = {
 714         .gate_id = GATE_GPU,
 715         .hw.init = CLK_HW_INIT_INDEX("ck_icn_m_gpu", FLEXGEN_59, &clk_stm32_gate_ops, 0),
 716 };
 717
 718 static struct clk_stm32_gate ck_ker_gpu = {
 719         .gate_id = GATE_GPU,
 720         .hw.init = CLK_HW_INIT_INDEX("ck_ker_gpu", PLL3, &clk_stm32_gate_ops, 0),
 721 };
 722
 723 /* HASH */
 724 static struct clk_stm32_gate ck_icn_p_hash = {
 725         .gate_id = GATE_HASH,
 726         .hw.init = CLK_HW_INIT_INDEX("ck_icn_p_hash", ICN_LS_MCU, &clk_stm32_gate_ops, 0),
 727 };
 728
 729 /* HDP */
 730 static struct clk_stm32_gate ck_icn_p_hdp = {
 731         .gate_id = GATE_HDP,
 732         .hw.init = CLK_HW_INIT_INDEX("ck_icn_p_hdp", ICN_APB3, &clk_stm32_gate_ops, 0),
 733 };
 734
 735 /* I2C */
 736 static struct clk_stm32_gate ck_icn_p_i2c8 = {
 737         .gate_id = GATE_I2C8,
 738         .hw.init = CLK_HW_INIT_INDEX("ck_icn_p_i2c8", ICN_LS_MCU, &clk_stm32_gate_ops, 0),
 739 };
 740
 741 static struct clk_stm32_gate ck_icn_p_i2c1 = {
 742         .gate_id = GATE_I2C1,
 743         .hw.init = CLK_HW_INIT_INDEX("ck_icn_p_i2c1", ICN_APB1, &clk_stm32_gate_ops, 0),
 744 };
 745
 746 static struct clk_stm32_gate ck_icn_p_i2c2 = {
 747         .gate_id = GATE_I2C2,
 748         .hw.init = CLK_HW_INIT_INDEX("ck_icn_p_i2c2", ICN_APB1, &clk_stm32_gate_ops, 0),
 749 };
 750
 751 static struct clk_stm32_gate ck_icn_p_i2c3 = {
 752         .gate_id = GATE_I2C3,
 753         .hw.init = CLK_HW_INIT_INDEX("ck_icn_p_i2c3", ICN_APB1, &clk_stm32_gate_ops, 0),
 754 };
 755
 756 static struct clk_stm32_gate ck_icn_p_i2c4 = {
 757         .gate_id = GATE_I2C4,
 758         .hw.init = CLK_HW_INIT_INDEX("ck_icn_p_i2c4", ICN_APB1, &clk_stm32_gate_ops, 0),
 759 };
 760
 761 static struct clk_stm32_gate ck_icn_p_i2c5 = {
 762         .gate_id = GATE_I2C5,
 763         .hw.init = CLK_HW_INIT_INDEX("ck_icn_p_i2c5", ICN_APB1, &clk_stm32_gate_ops, 0),
 764 };
 765
 766 static struct clk_stm32_gate ck_icn_p_i2c6 = {
 767         .gate_id = GATE_I2C6,
 768         .hw.init = CLK_HW_INIT_INDEX("ck_icn_p_i2c6", ICN_APB1, &clk_stm32_gate_ops, 0),
 769 };
 770
 771 static struct clk_stm32_gate ck_icn_p_i2c7 = {
 772         .gate_id = GATE_I2C7,
 773         .hw.init = CLK_HW_INIT_INDEX("ck_icn_p_i2c7", ICN_APB1, &clk_stm32_gate_ops, 0),
 774 };
 775
 776 static struct clk_stm32_gate ck_ker_i2c1 = {
 777         .gate_id = GATE_I2C1,
 778         .hw.init = CLK_HW_INIT_INDEX("ck_ker_i2c1", FLEXGEN_12, &clk_stm32_gate_ops, 0),
 779 };
 780
 781 static struct clk_stm32_gate ck_ker_i2c2 = {
 782         .gate_id = GATE_I2C2,
 783         .hw.init = CLK_HW_INIT_INDEX("ck_ker_i2c2", FLEXGEN_12, &clk_stm32_gate_ops, 0),
 784 };
 785
 786 static struct clk_stm32_gate ck_ker_i2c3 = {
 787         .gate_id = GATE_I2C3,
 788         .hw.init = CLK_HW_INIT_INDEX("ck_ker_i2c3", FLEXGEN_13, &clk_stm32_gate_ops, 0),
 789 };
 790
 791 static struct clk_stm32_gate ck_ker_i2c5 = {
 792         .gate_id = GATE_I2C5,
 793         .hw.init = CLK_HW_INIT_INDEX("ck_ker_i2c5", FLEXGEN_13, &clk_stm32_gate_ops, 0),
 794 };
 795
 796 static struct clk_stm32_gate ck_ker_i2c4 = {
 797         .gate_id = GATE_I2C4,
 798         .hw.init = CLK_HW_INIT_INDEX("ck_ker_i2c4", FLEXGEN_14, &clk_stm32_gate_ops, 0),
 799 };
 800
 801 static struct clk_stm32_gate ck_ker_i2c6 = {
 802         .gate_id = GATE_I2C6,
 803         .hw.init = CLK_HW_INIT_INDEX("ck_ker_i2c6", FLEXGEN_14, &clk_stm32_gate_ops, 0),
 804 };
 805
 806 static struct clk_stm32_gate ck_ker_i2c7 = {
 807         .gate_id = GATE_I2C7,
 808         .hw.init = CLK_HW_INIT_INDEX("ck_ker_i2c7", FLEXGEN_15, &clk_stm32_gate_ops, 0),
 809 };
 810
 811 static struct clk_stm32_gate ck_ker_i2c8 = {
 812         .gate_id = GATE_I2C8,
 813         .hw.init = CLK_HW_INIT_INDEX("ck_ker_i2c8", FLEXGEN_38, &clk_stm32_gate_ops, 0),
 814 };
 815
 816 /* I3C */
 817 static struct clk_stm32_gate ck_icn_p_i3c1 = {
 818         .gate_id = GATE_I3C1,
 819         .hw.init = CLK_HW_INIT_INDEX("ck_icn_p_i3c1", ICN_APB1, &clk_stm32_gate_ops, 0),
 820 };
 821
 822 static struct clk_stm32_gate ck_icn_p_i3c2 = {
 823         .gate_id = GATE_I3C2,
 824         .hw.init = CLK_HW_INIT_INDEX("ck_icn_p_i3c2", ICN_APB1, &clk_stm32_gate_ops, 0),
 825 };
 826
 827 static struct clk_stm32_gate ck_icn_p_i3c3 = {
 828         .gate_id = GATE_I3C3,
 829         .hw.init = CLK_HW_INIT_INDEX("ck_icn_p_i3c3", ICN_APB1, &clk_stm32_gate_ops, 0),
 830 };
 831
 832 static struct clk_stm32_gate ck_icn_p_i3c4 = {
 833         .gate_id = GATE_I3C4,
 834         .hw.init = CLK_HW_INIT_INDEX("ck_icn_p_i3c4", ICN_LS_MCU, &clk_stm32_gate_ops, 0),
 835 };
 836
 837 static struct clk_stm32_gate ck_ker_i3c1 = {
 838         .gate_id = GATE_I3C1,
 839         .hw.init = CLK_HW_INIT_INDEX("ck_ker_i3c1", FLEXGEN_12, &clk_stm32_gate_ops, 0),
 840 };
 841
 842 static struct clk_stm32_gate ck_ker_i3c2 = {
 843         .gate_id = GATE_I3C2,
 844         .hw.init = CLK_HW_INIT_INDEX("ck_ker_i3c2", FLEXGEN_12, &clk_stm32_gate_ops, 0),
 845 };
 846
 847 static struct clk_stm32_gate ck_ker_i3c3 = {
 848         .gate_id = GATE_I3C3,
 849         .hw.init = CLK_HW_INIT_INDEX("ck_ker_i3c3", FLEXGEN_13, &clk_stm32_gate_ops, 0),
 850 };
 851
 852 static struct clk_stm32_gate ck_ker_i3c4 = {
 853         .gate_id = GATE_I3C4,
 854         .hw.init = CLK_HW_INIT_INDEX("ck_ker_i3c4", FLEXGEN_36, &clk_stm32_gate_ops, 0),
 855 };
 856
 857 /* I2S */
 858 static struct clk_stm32_gate ck_icn_p_is2m = {
 859         .gate_id = GATE_IS2M,
 860         .hw.init = CLK_HW_INIT_INDEX("ck_icn_p_is2m", ICN_APB3, &clk_stm32_gate_ops, 0),
 861 };
 862
 863 /* IWDG */
 864 static struct clk_stm32_gate ck_icn_p_iwdg2 = {
 865         .gate_id = GATE_IWDG2,
 866         .hw.init = CLK_HW_INIT_INDEX("ck_icn_p_iwdg2", ICN_APB3, &clk_stm32_gate_ops, 0),
 867 };
 868
 869 static struct clk_stm32_gate ck_icn_p_iwdg3 = {
 870         .gate_id = GATE_IWDG3,
 871         .hw.init = CLK_HW_INIT_INDEX("ck_icn_p_iwdg3", ICN_APB3, &clk_stm32_gate_ops, 0),
 872 };
 873
 874 static struct clk_stm32_gate ck_icn_p_iwdg4 = {
 875         .gate_id = GATE_IWDG4,
 876         .hw.init = CLK_HW_INIT_INDEX("ck_icn_p_iwdg4", ICN_APB3, &clk_stm32_gate_ops, 0),
 877 };
 878
 879 static struct clk_stm32_gate ck_icn_p_iwdg5 = {
 880         .gate_id = GATE_IWDG5,
 881         .hw.init = CLK_HW_INIT_INDEX("ck_icn_p_iwdg5", ICN_LS_MCU, &clk_stm32_gate_ops, 0),
 882 };
 883
 884 /* LPTIM */
 885 static struct clk_stm32_gate ck_icn_p_lptim1 = {
 886         .gate_id = GATE_LPTIM1,
 887         .hw.init = CLK_HW_INIT_INDEX("ck_icn_p_lptim1", ICN_APB1, &clk_stm32_gate_ops, 0),
 888 };
 889
 890 static struct clk_stm32_gate ck_icn_p_lptim2 = {
 891         .gate_id = GATE_LPTIM2,
 892         .hw.init = CLK_HW_INIT_INDEX("ck_icn_p_lptim2", ICN_APB1, &clk_stm32_gate_ops, 0),
 893 };
 894
 895 static struct clk_stm32_gate ck_icn_p_lptim3 = {
 896         .gate_id = GATE_LPTIM3,
 897         .hw.init = CLK_HW_INIT_INDEX("ck_icn_p_lptim3", ICN_LS_MCU, &clk_stm32_gate_ops, 0),
 898 };
 899
 900 static struct clk_stm32_gate ck_icn_p_lptim4 = {
 901         .gate_id = GATE_LPTIM4,
 902         .hw.init = CLK_HW_INIT_INDEX("ck_icn_p_lptim4", ICN_LS_MCU, &clk_stm32_gate_ops, 0),
 903 };
 904
 905 static struct clk_stm32_gate ck_icn_p_lptim5 = {
 906         .gate_id = GATE_LPTIM5,
 907         .hw.init = CLK_HW_INIT_INDEX("ck_icn_p_lptim5", ICN_LS_MCU, &clk_stm32_gate_ops, 0),
 908 };
 909
 910 static struct clk_stm32_gate ck_ker_lptim1 = {
 911         .gate_id = GATE_LPTIM1,
 912         .hw.init = CLK_HW_INIT_INDEX("ck_ker_lptim1", FLEXGEN_07, &clk_stm32_gate_ops, 0),
 913 };
 914
 915 static struct clk_stm32_gate ck_ker_lptim2 = {
 916         .gate_id = GATE_LPTIM2,
 917         .hw.init = CLK_HW_INIT_INDEX("ck_ker_lptim2", FLEXGEN_07, &clk_stm32_gate_ops, 0),
 918 };
 919
 920 static struct clk_stm32_gate ck_ker_lptim3 = {
 921         .gate_id = GATE_LPTIM3,
 922         .hw.init = CLK_HW_INIT_INDEX("ck_ker_lptim3", FLEXGEN_40, &clk_stm32_gate_ops, 0),
 923 };
 924
 925 static struct clk_stm32_gate ck_ker_lptim4 = {
 926         .gate_id = GATE_LPTIM4,
 927         .hw.init = CLK_HW_INIT_INDEX("ck_ker_lptim4", FLEXGEN_41, &clk_stm32_gate_ops, 0),
 928 };
 929
 930 static struct clk_stm32_gate ck_ker_lptim5 = {
 931         .gate_id = GATE_LPTIM5,
 932         .hw.init = CLK_HW_INIT_INDEX("ck_ker_lptim5", FLEXGEN_41, &clk_stm32_gate_ops, 0),
 933 };
 934
 935 /* LPUART */
 936 static struct clk_stm32_gate ck_icn_p_lpuart1 = {
 937         .gate_id = GATE_LPUART1,
 938         .hw.init = CLK_HW_INIT_INDEX("ck_icn_p_lpuart1", ICN_LS_MCU, &clk_stm32_gate_ops, 0),
 939 };
 940
 941 static struct clk_stm32_gate ck_ker_lpuart1 = {
 942         .gate_id = GATE_LPUART1,
 943         .hw.init = CLK_HW_INIT_INDEX("ck_ker_lpuart1", FLEXGEN_39, &clk_stm32_gate_ops, 0),
 944 };
 945
 946 /* MCO1 & MCO2 */
 947 static struct clk_stm32_composite ck_mco1 = {
 948         .gate_id = GATE_MCO1,
 949         .mux_id = MUX_MCO1,
 950         .div_id = NO_STM32_DIV,
 951         .hw.init = CLK_HW_INIT_PARENTS_DATA("ck_mco1", mco1_src, &clk_stm32_composite_ops, 0),
 952 };
 953
 954 static struct clk_stm32_composite ck_mco2 = {
 955         .gate_id = GATE_MCO2,
 956         .mux_id = MUX_MCO2,
 957         .div_id = NO_STM32_DIV,
 958         .hw.init = CLK_HW_INIT_PARENTS_DATA("ck_mco2", mco2_src, &clk_stm32_composite_ops, 0),
 959 };
 960
 961 /* MDF */
 962 static struct clk_stm32_gate ck_icn_p_mdf1 = {
 963         .gate_id = GATE_MDF1,
 964         .hw.init = CLK_HW_INIT_INDEX("ck_icn_p_mdf1", ICN_LS_MCU, &clk_stm32_gate_ops, 0),
 965 };
 966
 967 static struct clk_stm32_gate ck_ker_mdf1 = {
 968         .gate_id = GATE_MDF1,
 969         .hw.init = CLK_HW_INIT_INDEX("ck_ker_mdf1", FLEXGEN_23, &clk_stm32_gate_ops, 0),
 970 };
 971
 972 /* OSPI */
 973 static struct clk_stm32_gate ck_icn_p_ospiiom = {
 974         .gate_id = GATE_OSPIIOM,
 975         .hw.init = CLK_HW_INIT_INDEX("ck_icn_p_ospiiom", ICN_LS_MCU, &clk_stm32_gate_ops, 0),
 976 };
 977
 978 /* PCIE */
 979 static struct clk_stm32_gate ck_icn_p_pcie = {
 980         .gate_id = GATE_PCIE,
 981         .hw.init = CLK_HW_INIT_INDEX("ck_icn_p_pcie", ICN_LS_MCU, &clk_stm32_gate_ops, 0),
 982 };
 983
 984 /* SAI */
 985 static struct clk_stm32_gate ck_icn_p_sai1 = {
 986         .gate_id = GATE_SAI1,
 987         .hw.init = CLK_HW_INIT_INDEX("ck_icn_p_sai1", ICN_APB2, &clk_stm32_gate_ops, 0),
 988 };
 989
 990 static struct clk_stm32_gate ck_icn_p_sai2 = {
 991         .gate_id = GATE_SAI2,
 992         .hw.init = CLK_HW_INIT_INDEX("ck_icn_p_sai2", ICN_APB2, &clk_stm32_gate_ops, 0),
 993 };
 994
 995 static struct clk_stm32_gate ck_icn_p_sai3 = {
 996         .gate_id = GATE_SAI3,
 997         .hw.init = CLK_HW_INIT_INDEX("ck_icn_p_sai3", ICN_APB2, &clk_stm32_gate_ops, 0),
 998 };
 999
1000 static struct clk_stm32_gate ck_icn_p_sai4 = {
1001         .gate_id = GATE_SAI4,
1002         .hw.init = CLK_HW_INIT_INDEX("ck_icn_p_sai4", ICN_APB2, &clk_stm32_gate_ops, 0),
1003 };
1004
1005 static struct clk_stm32_gate ck_ker_sai1 = {
1006         .gate_id = GATE_SAI1,
1007         .hw.init = CLK_HW_INIT_INDEX("ck_ker_sai1", FLEXGEN_23, &clk_stm32_gate_ops,
1008                                      CLK_SET_RATE_PARENT),
1009 };
1010
1011 static struct clk_stm32_gate ck_ker_sai2 = {
1012         .gate_id = GATE_SAI2,
1013         .hw.init = CLK_HW_INIT_INDEX("ck_ker_sai2", FLEXGEN_24, &clk_stm32_gate_ops,
1014                                      CLK_SET_RATE_PARENT),
1015 };
1016
1017 static struct clk_stm32_gate ck_ker_sai3 = {
1018         .gate_id = GATE_SAI3,
1019         .hw.init = CLK_HW_INIT_INDEX("ck_ker_sai3", FLEXGEN_25, &clk_stm32_gate_ops,
1020                                      CLK_SET_RATE_PARENT),
1021 };
1022
1023 static struct clk_stm32_gate ck_ker_sai4 = {
1024         .gate_id = GATE_SAI4,
1025         .hw.init = CLK_HW_INIT_INDEX("ck_ker_sai4", FLEXGEN_25, &clk_stm32_gate_ops,
1026                                      CLK_SET_RATE_PARENT),
1027 };
1028
1029 /* SDMMC */
1030 static struct clk_stm32_gate ck_icn_m_sdmmc1 = {
1031         .gate_id = GATE_SDMMC1,
1032         .hw.init = CLK_HW_INIT_INDEX("ck_icn_m_sdmmc1", ICN_SDMMC, &clk_stm32_gate_ops, 0),
1033 };
1034
1035 static struct clk_stm32_gate ck_icn_m_sdmmc2 = {
1036         .gate_id = GATE_SDMMC2,
1037         .hw.init = CLK_HW_INIT_INDEX("ck_icn_m_sdmmc2", ICN_SDMMC, &clk_stm32_gate_ops, 0),
1038 };
1039
1040 static struct clk_stm32_gate ck_icn_m_sdmmc3 = {
1041         .gate_id = GATE_SDMMC3,
1042         .hw.init = CLK_HW_INIT_INDEX("ck_icn_m_sdmmc3", ICN_SDMMC, &clk_stm32_gate_ops, 0),
1043 };
1044
1045 static struct clk_stm32_gate ck_ker_sdmmc1 = {
1046         .gate_id = GATE_SDMMC1,
1047         .hw.init = CLK_HW_INIT_INDEX("ck_ker_sdmmc1", FLEXGEN_51, &clk_stm32_gate_ops, 0),
1048 };
1049
1050 static struct clk_stm32_gate ck_ker_sdmmc2 = {
1051         .gate_id = GATE_SDMMC2,
1052         .hw.init = CLK_HW_INIT_INDEX("ck_ker_sdmmc2", FLEXGEN_52, &clk_stm32_gate_ops, 0),
1053 };
1054
1055 static struct clk_stm32_gate ck_ker_sdmmc3 = {
1056         .gate_id = GATE_SDMMC3,
1057         .hw.init = CLK_HW_INIT_INDEX("ck_ker_sdmmc3", FLEXGEN_53, &clk_stm32_gate_ops, 0),
1058 };
1059
1060 /* SPDIF */
1061 static struct clk_stm32_gate ck_icn_p_spdifrx = {
1062         .gate_id = GATE_SPDIFRX,
1063         .hw.init = CLK_HW_INIT_INDEX("ck_icn_p_spdifrx", ICN_APB1, &clk_stm32_gate_ops, 0),
1064 };
1065
1066 static struct clk_stm32_gate ck_ker_spdifrx = {
1067         .gate_id = GATE_SPDIFRX,
1068         .hw.init = CLK_HW_INIT_INDEX("ck_ker_spdifrx", FLEXGEN_11, &clk_stm32_gate_ops, 0),
1069 };
1070
1071 /* SPI */
1072 static struct clk_stm32_gate ck_icn_p_spi1 = {
1073         .gate_id = GATE_SPI1,
1074         .hw.init = CLK_HW_INIT_INDEX("ck_icn_p_spi1", ICN_APB2, &clk_stm32_gate_ops, 0),
1075 };
1076
1077 static struct clk_stm32_gate ck_icn_p_spi2 = {
1078         .gate_id = GATE_SPI2,
1079         .hw.init = CLK_HW_INIT_INDEX("ck_icn_p_spi2", ICN_APB1, &clk_stm32_gate_ops, 0),
1080 };
1081
1082 static struct clk_stm32_gate ck_icn_p_spi3 = {
1083         .gate_id = GATE_SPI3,
1084         .hw.init = CLK_HW_INIT_INDEX("ck_icn_p_spi3", ICN_APB1, &clk_stm32_gate_ops, 0),
1085 };
1086
1087 static struct clk_stm32_gate ck_icn_p_spi4 = {
1088         .gate_id = GATE_SPI4,
1089         .hw.init = CLK_HW_INIT_INDEX("ck_icn_p_spi4", ICN_APB2, &clk_stm32_gate_ops, 0),
1090 };
1091
1092 static struct clk_stm32_gate ck_icn_p_spi5 = {
1093         .gate_id = GATE_SPI5,
1094         .hw.init = CLK_HW_INIT_INDEX("ck_icn_p_spi5", ICN_APB2, &clk_stm32_gate_ops, 0),
1095 };
1096
1097 static struct clk_stm32_gate ck_icn_p_spi6 = {
1098         .gate_id = GATE_SPI6,
1099         .hw.init = CLK_HW_INIT_INDEX("ck_icn_p_spi6", ICN_APB2, &clk_stm32_gate_ops, 0),
1100 };
1101
1102 static struct clk_stm32_gate ck_icn_p_spi7 = {
1103         .gate_id = GATE_SPI7,
1104         .hw.init = CLK_HW_INIT_INDEX("ck_icn_p_spi7", ICN_APB2, &clk_stm32_gate_ops, 0),
1105 };
1106
1107 static struct clk_stm32_gate ck_icn_p_spi8 = {
1108         .gate_id = GATE_SPI8,
1109         .hw.init = CLK_HW_INIT_INDEX("ck_icn_p_spi8", ICN_LS_MCU, &clk_stm32_gate_ops, 0),
1110 };
1111
1112 static struct clk_stm32_gate ck_ker_spi1 = {
1113         .gate_id = GATE_SPI1,
1114         .hw.init = CLK_HW_INIT_INDEX("ck_ker_spi1", FLEXGEN_16, &clk_stm32_gate_ops,
1115                                      CLK_SET_RATE_PARENT),
1116 };
1117
1118 static struct clk_stm32_gate ck_ker_spi2 = {
1119         .gate_id = GATE_SPI2,
1120         .hw.init = CLK_HW_INIT_INDEX("ck_ker_spi2", FLEXGEN_10, &clk_stm32_gate_ops,
1121                                      CLK_SET_RATE_PARENT),
1122 };
1123
1124 static struct clk_stm32_gate ck_ker_spi3 = {
1125         .gate_id = GATE_SPI3,
1126         .hw.init = CLK_HW_INIT_INDEX("ck_ker_spi3", FLEXGEN_10, &clk_stm32_gate_ops,
1127                                      CLK_SET_RATE_PARENT),
1128 };
1129
1130 static struct clk_stm32_gate ck_ker_spi4 = {
1131         .gate_id = GATE_SPI4,
1132         .hw.init = CLK_HW_INIT_INDEX("ck_ker_spi4", FLEXGEN_17, &clk_stm32_gate_ops, 0),
1133 };
1134
1135 static struct clk_stm32_gate ck_ker_spi5 = {
1136         .gate_id = GATE_SPI5,
1137         .hw.init = CLK_HW_INIT_INDEX("ck_ker_spi5", FLEXGEN_17, &clk_stm32_gate_ops, 0),
1138 };
1139
1140 static struct clk_stm32_gate ck_ker_spi6 = {
1141         .gate_id = GATE_SPI6,
1142         .hw.init = CLK_HW_INIT_INDEX("ck_ker_spi6", FLEXGEN_18, &clk_stm32_gate_ops, 0),
1143 };
1144
1145 static struct clk_stm32_gate ck_ker_spi7 = {
1146         .gate_id = GATE_SPI7,
1147         .hw.init = CLK_HW_INIT_INDEX("ck_ker_spi7", FLEXGEN_18, &clk_stm32_gate_ops, 0),
1148 };
1149
1150 static struct clk_stm32_gate ck_ker_spi8 = {
1151         .gate_id = GATE_SPI8,
1152         .hw.init = CLK_HW_INIT_INDEX("ck_ker_spi8", FLEXGEN_37, &clk_stm32_gate_ops, 0),
1153 };
1154
1155 /* Timers */
1156 static struct clk_stm32_gate ck_icn_p_tim2 = {
1157         .gate_id = GATE_TIM2,
1158         .hw.init = CLK_HW_INIT_INDEX("ck_icn_p_tim2", ICN_APB1, &clk_stm32_gate_ops, 0),
1159 };
1160
1161 static struct clk_stm32_gate ck_icn_p_tim3 = {
1162         .gate_id = GATE_TIM3,
1163         .hw.init = CLK_HW_INIT_INDEX("ck_icn_p_tim3", ICN_APB1, &clk_stm32_gate_ops, 0),
1164 };
1165
1166 static struct clk_stm32_gate ck_icn_p_tim4 = {
1167         .gate_id = GATE_TIM4,
1168         .hw.init = CLK_HW_INIT_INDEX("ck_icn_p_tim4", ICN_APB1, &clk_stm32_gate_ops, 0),
1169 };
1170
1171 static struct clk_stm32_gate ck_icn_p_tim5 = {
1172         .gate_id = GATE_TIM5,
1173         .hw.init = CLK_HW_INIT_INDEX("ck_icn_p_tim5", ICN_APB1, &clk_stm32_gate_ops, 0),
1174 };
1175
1176 static struct clk_stm32_gate ck_icn_p_tim6 = {
1177         .gate_id = GATE_TIM6,
1178         .hw.init = CLK_HW_INIT_INDEX("ck_icn_p_tim6", ICN_APB1, &clk_stm32_gate_ops, 0),
1179 };
1180
1181 static struct clk_stm32_gate ck_icn_p_tim7 = {
1182         .gate_id = GATE_TIM7,
1183         .hw.init = CLK_HW_INIT_INDEX("ck_icn_p_tim7", ICN_APB1, &clk_stm32_gate_ops, 0),
1184 };
1185
1186 static struct clk_stm32_gate ck_icn_p_tim10 = {
1187         .gate_id = GATE_TIM10,
1188         .hw.init = CLK_HW_INIT_INDEX("ck_icn_p_tim10", ICN_APB1, &clk_stm32_gate_ops, 0),
1189 };
1190
1191 static struct clk_stm32_gate ck_icn_p_tim11 = {
1192         .gate_id = GATE_TIM11,
1193         .hw.init = CLK_HW_INIT_INDEX("ck_icn_p_tim11", ICN_APB1, &clk_stm32_gate_ops, 0),
1194 };
1195
1196 static struct clk_stm32_gate ck_icn_p_tim12 = {
1197         .gate_id = GATE_TIM12,
1198         .hw.init = CLK_HW_INIT_INDEX("ck_icn_p_tim12", ICN_APB1, &clk_stm32_gate_ops, 0),
1199 };
1200
1201 static struct clk_stm32_gate ck_icn_p_tim13 = {
1202         .gate_id = GATE_TIM13,
1203         .hw.init = CLK_HW_INIT_INDEX("ck_icn_p_tim13", ICN_APB1, &clk_stm32_gate_ops, 0),
1204 };
1205
1206 static struct clk_stm32_gate ck_icn_p_tim14 = {
1207         .gate_id = GATE_TIM14,
1208         .hw.init = CLK_HW_INIT_INDEX("ck_icn_p_tim14", ICN_APB1, &clk_stm32_gate_ops, 0),
1209 };
1210
1211 static struct clk_stm32_gate ck_icn_p_tim1 = {
1212         .gate_id = GATE_TIM1,
1213         .hw.init = CLK_HW_INIT_INDEX("ck_icn_p_tim1", ICN_APB2, &clk_stm32_gate_ops, 0),
1214 };
1215
1216 static struct clk_stm32_gate ck_icn_p_tim8 = {
1217         .gate_id = GATE_TIM8,
1218         .hw.init = CLK_HW_INIT_INDEX("ck_icn_p_tim8", ICN_APB2, &clk_stm32_gate_ops, 0),
1219 };
1220
1221 static struct clk_stm32_gate ck_icn_p_tim15 = {
1222         .gate_id = GATE_TIM15,
1223         .hw.init = CLK_HW_INIT_INDEX("ck_icn_p_tim15", ICN_APB2, &clk_stm32_gate_ops, 0),
1224 };
1225
1226 static struct clk_stm32_gate ck_icn_p_tim16 = {
1227         .gate_id = GATE_TIM16,
1228         .hw.init = CLK_HW_INIT_INDEX("ck_icn_p_tim16", ICN_APB2, &clk_stm32_gate_ops, 0),
1229 };
1230
1231 static struct clk_stm32_gate ck_icn_p_tim17 = {
1232         .gate_id = GATE_TIM17,
1233         .hw.init = CLK_HW_INIT_INDEX("ck_icn_p_tim17", ICN_APB2, &clk_stm32_gate_ops, 0),
1234 };
1235
1236 static struct clk_stm32_gate ck_icn_p_tim20 = {
1237         .gate_id = GATE_TIM20,
1238         .hw.init = CLK_HW_INIT_INDEX("ck_icn_p_tim20", ICN_APB2, &clk_stm32_gate_ops, 0),
1239 };
1240
1241 static struct clk_stm32_gate ck_ker_tim2 = {
1242         .gate_id = GATE_TIM2,
1243         .hw.init = CLK_HW_INIT_INDEX("ck_ker_tim2", TIMG1, &clk_stm32_gate_ops, 0),
1244 };
1245
1246 static struct clk_stm32_gate ck_ker_tim3 = {
1247         .gate_id = GATE_TIM3,
1248         .hw.init = CLK_HW_INIT_INDEX("ck_ker_tim3", TIMG1, &clk_stm32_gate_ops, 0),
1249 };
1250
1251 static struct clk_stm32_gate ck_ker_tim4 = {
1252         .gate_id = GATE_TIM4,
1253         .hw.init = CLK_HW_INIT_INDEX("ck_ker_tim4", TIMG1, &clk_stm32_gate_ops, 0),
1254 };
1255
1256 static struct clk_stm32_gate ck_ker_tim5 = {
1257         .gate_id = GATE_TIM5,
1258         .hw.init = CLK_HW_INIT_INDEX("ck_ker_tim5", TIMG1, &clk_stm32_gate_ops, 0),
1259 };
1260
1261 static struct clk_stm32_gate ck_ker_tim6 = {
1262         .gate_id = GATE_TIM6,
1263         .hw.init = CLK_HW_INIT_INDEX("ck_ker_tim6", TIMG1, &clk_stm32_gate_ops, 0),
1264 };
1265
1266 static struct clk_stm32_gate ck_ker_tim7 = {
1267         .gate_id = GATE_TIM7,
1268         .hw.init = CLK_HW_INIT_INDEX("ck_ker_tim7", TIMG1, &clk_stm32_gate_ops, 0),
1269 };
1270
1271 static struct clk_stm32_gate ck_ker_tim10 = {
1272         .gate_id = GATE_TIM10,
1273         .hw.init = CLK_HW_INIT_INDEX("ck_ker_tim10", TIMG1, &clk_stm32_gate_ops, 0),
1274 };
1275
1276 static struct clk_stm32_gate ck_ker_tim11 = {
1277         .gate_id = GATE_TIM11,
1278         .hw.init = CLK_HW_INIT_INDEX("ck_ker_tim11", TIMG1, &clk_stm32_gate_ops, 0),
1279 };
1280
1281 static struct clk_stm32_gate ck_ker_tim12 = {
1282         .gate_id = GATE_TIM12,
1283         .hw.init = CLK_HW_INIT_INDEX("ck_ker_tim12", TIMG1, &clk_stm32_gate_ops, 0),
1284 };
1285
1286 static struct clk_stm32_gate ck_ker_tim13 = {
1287         .gate_id = GATE_TIM13,
1288         .hw.init = CLK_HW_INIT_INDEX("ck_ker_tim13", TIMG1, &clk_stm32_gate_ops, 0),
1289 };
1290
1291 static struct clk_stm32_gate ck_ker_tim14 = {
1292         .gate_id = GATE_TIM14,
1293         .hw.init = CLK_HW_INIT_INDEX("ck_ker_tim14", TIMG1, &clk_stm32_gate_ops, 0),
1294 };
1295
1296 static struct clk_stm32_gate ck_ker_tim1 = {
1297         .gate_id = GATE_TIM1,
1298         .hw.init = CLK_HW_INIT_INDEX("ck_ker_tim1", TIMG2, &clk_stm32_gate_ops, 0),
1299 };
1300
1301 static struct clk_stm32_gate ck_ker_tim8 = {
1302         .gate_id = GATE_TIM8,
1303         .hw.init = CLK_HW_INIT_INDEX("ck_ker_tim8", TIMG2, &clk_stm32_gate_ops, 0),
1304 };
1305
1306 static struct clk_stm32_gate ck_ker_tim15 = {
1307         .gate_id = GATE_TIM15,
1308         .hw.init = CLK_HW_INIT_INDEX("ck_ker_tim15", TIMG2, &clk_stm32_gate_ops, 0),
1309 };
1310
1311 static struct clk_stm32_gate ck_ker_tim16 = {
1312         .gate_id = GATE_TIM16,
1313         .hw.init = CLK_HW_INIT_INDEX("ck_ker_tim16", TIMG2, &clk_stm32_gate_ops, 0),
1314 };
1315
1316 static struct clk_stm32_gate ck_ker_tim17 = {
1317         .gate_id = GATE_TIM17,
1318         .hw.init = CLK_HW_INIT_INDEX("ck_ker_tim17", TIMG2, &clk_stm32_gate_ops, 0),
1319 };
1320
1321 static struct clk_stm32_gate ck_ker_tim20 = {
1322         .gate_id = GATE_TIM20,
1323         .hw.init = CLK_HW_INIT_INDEX("ck_ker_tim20", TIMG2, &clk_stm32_gate_ops, 0),
1324 };
1325
1326 /* UART/USART */
1327 static struct clk_stm32_gate ck_icn_p_usart2 = {
1328         .gate_id = GATE_USART2,
1329         .hw.init = CLK_HW_INIT_INDEX("ck_icn_p_usart2", ICN_APB1, &clk_stm32_gate_ops, 0),
1330 };
1331
1332 static struct clk_stm32_gate ck_icn_p_usart3 = {
1333         .gate_id = GATE_USART3,
1334         .hw.init = CLK_HW_INIT_INDEX("ck_icn_p_usart3", ICN_APB1, &clk_stm32_gate_ops, 0),
1335 };
1336
1337 static struct clk_stm32_gate ck_icn_p_uart4 = {
1338         .gate_id = GATE_UART4,
1339         .hw.init = CLK_HW_INIT_INDEX("ck_icn_p_uart4", ICN_APB1, &clk_stm32_gate_ops, 0),
1340 };
1341
1342 static struct clk_stm32_gate ck_icn_p_uart5 = {
1343         .gate_id = GATE_UART5,
1344         .hw.init = CLK_HW_INIT_INDEX("ck_icn_p_uart5", ICN_APB1, &clk_stm32_gate_ops, 0),
1345 };
1346
1347 static struct clk_stm32_gate ck_icn_p_usart1 = {
1348         .gate_id = GATE_USART1,
1349         .hw.init = CLK_HW_INIT_INDEX("ck_icn_p_usart1", ICN_APB2, &clk_stm32_gate_ops, 0),
1350 };
1351
1352 static struct clk_stm32_gate ck_icn_p_usart6 = {
1353         .gate_id = GATE_USART6,
1354         .hw.init = CLK_HW_INIT_INDEX("ck_icn_p_usart6", ICN_APB2, &clk_stm32_gate_ops, 0),
1355 };
1356
1357 static struct clk_stm32_gate ck_icn_p_uart7 = {
1358         .gate_id = GATE_UART7,
1359         .hw.init = CLK_HW_INIT_INDEX("ck_icn_p_uart7", ICN_APB2, &clk_stm32_gate_ops, 0),
1360 };
1361
1362 static struct clk_stm32_gate ck_icn_p_uart8 = {
1363         .gate_id = GATE_UART8,
1364         .hw.init = CLK_HW_INIT_INDEX("ck_icn_p_uart8", ICN_APB2, &clk_stm32_gate_ops, 0),
1365 };
1366
1367 static struct clk_stm32_gate ck_icn_p_uart9 = {
1368         .gate_id = GATE_UART9,
1369         .hw.init = CLK_HW_INIT_INDEX("ck_icn_p_uart9", ICN_APB2, &clk_stm32_gate_ops, 0),
1370 };
1371
1372 static struct clk_stm32_gate ck_ker_usart2 = {
1373         .gate_id = GATE_USART2,
1374         .hw.init = CLK_HW_INIT_INDEX("ck_ker_usart2", FLEXGEN_08, &clk_stm32_gate_ops, 0),
1375 };
1376
1377 static struct clk_stm32_gate ck_ker_uart4 = {
1378         .gate_id = GATE_UART4,
1379         .hw.init = CLK_HW_INIT_INDEX("ck_ker_uart4", FLEXGEN_08, &clk_stm32_gate_ops, 0),
1380 };
1381
1382 static struct clk_stm32_gate ck_ker_usart3 = {
1383         .gate_id = GATE_USART3,
1384         .hw.init = CLK_HW_INIT_INDEX("ck_ker_usart3", FLEXGEN_09, &clk_stm32_gate_ops, 0),
1385 };
1386
1387 static struct clk_stm32_gate ck_ker_uart5 = {
1388         .gate_id = GATE_UART5,
1389         .hw.init = CLK_HW_INIT_INDEX("ck_ker_uart5", FLEXGEN_09, &clk_stm32_gate_ops, 0),
1390 };
1391
1392 static struct clk_stm32_gate ck_ker_usart1 = {
1393         .gate_id = GATE_USART1,
1394         .hw.init = CLK_HW_INIT_INDEX("ck_ker_usart1", FLEXGEN_19, &clk_stm32_gate_ops, 0),
1395 };
1396
1397 static struct clk_stm32_gate ck_ker_usart6 = {
1398         .gate_id = GATE_USART6,
1399         .hw.init = CLK_HW_INIT_INDEX("ck_ker_usart6", FLEXGEN_20, &clk_stm32_gate_ops, 0),
1400 };
1401
1402 static struct clk_stm32_gate ck_ker_uart7 = {
1403         .gate_id = GATE_UART7,
1404         .hw.init = CLK_HW_INIT_INDEX("ck_ker_uart7", FLEXGEN_21, &clk_stm32_gate_ops, 0),
1405 };
1406
1407 static struct clk_stm32_gate ck_ker_uart8 = {
1408         .gate_id = GATE_UART8,
1409         .hw.init = CLK_HW_INIT_INDEX("ck_ker_uart8", FLEXGEN_21, &clk_stm32_gate_ops, 0),
1410 };
1411
1412 static struct clk_stm32_gate ck_ker_uart9 = {
1413         .gate_id = GATE_UART9,
1414         .hw.init = CLK_HW_INIT_INDEX("ck_ker_uart9", FLEXGEN_22, &clk_stm32_gate_ops, 0),
1415 };
1416
1417 /* USB2PHY1 */
1418 static struct clk_stm32_composite ck_ker_usb2phy1 = {
1419         .gate_id = GATE_USB2PHY1,
1420         .mux_id = MUX_USB2PHY1,
1421         .div_id = NO_STM32_DIV,
1422         .hw.init = CLK_HW_INIT_PARENTS_DATA("ck_ker_usb2phy1", usb2phy1_src,
1423                                             &clk_stm32_composite_ops, 0),
1424 };
1425
1426 /* USB2H */
1427 static struct clk_stm32_gate ck_icn_m_usb2ehci = {
1428         .gate_id = GATE_USBH,
1429         .hw.init = CLK_HW_INIT_INDEX("ck_icn_m_usb2ehci", ICN_HSL, &clk_stm32_gate_ops, 0),
1430 };
1431
1432 static struct clk_stm32_gate ck_icn_m_usb2ohci = {
1433         .gate_id = GATE_USBH,
1434         .hw.init = CLK_HW_INIT_INDEX("ck_icn_m_usb2ohci", ICN_HSL, &clk_stm32_gate_ops, 0),
1435 };
1436
1437 /* USB2PHY2 */
1438 static struct clk_stm32_composite ck_ker_usb2phy2_en = {
1439         .gate_id = GATE_USB2PHY2,
1440         .mux_id = MUX_USB2PHY2,
1441         .div_id = NO_STM32_DIV,
1442         .hw.init = CLK_HW_INIT_PARENTS_DATA("ck_ker_usb2phy2_en", usb2phy2_src,
1443                                             &clk_stm32_composite_ops, 0),
1444 };
1445
1446 /* USB3 PCIe COMBOPHY */
1447 static struct clk_stm32_gate ck_icn_p_usb3pciephy = {
1448         .gate_id = GATE_USB3PCIEPHY,
1449         .hw.init = CLK_HW_INIT_INDEX("ck_icn_p_usb3pciephy", ICN_APB4, &clk_stm32_gate_ops, 0),
1450 };
1451
1452 static struct clk_stm32_composite ck_ker_usb3pciephy = {
1453         .gate_id = GATE_USB3PCIEPHY,
1454         .mux_id = MUX_USB3PCIEPHY,
1455         .div_id = NO_STM32_DIV,
1456         .hw.init = CLK_HW_INIT_PARENTS_DATA("ck_ker_usb3pciephy", usb3pciphy_src,
1457                                             &clk_stm32_composite_ops, 0),
1458 };
1459
1460 /* USB3 DRD */
1461 static struct clk_stm32_gate ck_icn_m_usb3dr = {
1462         .gate_id = GATE_USB3DR,
1463         .hw.init = CLK_HW_INIT_INDEX("ck_icn_m_usb3dr", ICN_HSL, &clk_stm32_gate_ops, 0),
1464 };
1465
1466 static struct clk_stm32_gate ck_ker_usb2phy2 = {
1467         .gate_id = GATE_USB3DR,
1468         .hw.init = CLK_HW_INIT_INDEX("ck_ker_usb2phy2", FLEXGEN_58, &clk_stm32_gate_ops, 0),
1469 };
1470
1471 /* USBTC */
1472 static struct clk_stm32_gate ck_icn_p_usbtc = {
1473         .gate_id = GATE_USBTC,
1474         .hw.init = CLK_HW_INIT_INDEX("ck_icn_p_usbtc", ICN_APB4, &clk_stm32_gate_ops, 0),
1475 };
1476
1477 static struct clk_stm32_gate ck_ker_usbtc = {
1478         .gate_id = GATE_USBTC,
1479         .hw.init = CLK_HW_INIT_INDEX("ck_ker_usbtc", FLEXGEN_35, &clk_stm32_gate_ops, 0),
1480 };
1481
1482 /* VDEC / VENC */
1483 static struct clk_stm32_gate ck_icn_p_vdec = {
1484         .gate_id = GATE_VDEC,
1485         .hw.init = CLK_HW_INIT_INDEX("ck_icn_p_vdec", ICN_APB4, &clk_stm32_gate_ops, 0),
1486 };
1487
1488 static struct clk_stm32_gate ck_icn_p_venc = {
1489         .gate_id = GATE_VENC,
1490         .hw.init = CLK_HW_INIT_INDEX("ck_icn_p_venc", ICN_APB4, &clk_stm32_gate_ops, 0),
1491 };
1492
1493 /* VREF */
1494 static struct clk_stm32_gate ck_icn_p_vref = {
1495         .gate_id = GATE_VREF,
1496         .hw.init = CLK_HW_INIT_INDEX("ck_icn_p_vref", ICN_APB3, &clk_stm32_gate_ops, 0),
1497 };
1498
1499 /* WWDG */
1500 static struct clk_stm32_gate ck_icn_p_wwdg1 = {
1501         .gate_id = GATE_WWDG1,
1502         .hw.init = CLK_HW_INIT_INDEX("ck_icn_p_wwdg1", ICN_APB3, &clk_stm32_gate_ops, 0),
1503 };
1504
1505 static struct clk_stm32_gate ck_icn_p_wwdg2 = {
1506         .gate_id = GATE_WWDG2,
1507         .hw.init = CLK_HW_INIT_INDEX("ck_icn_p_wwdg2", ICN_LS_MCU, &clk_stm32_gate_ops, 0),
1508 };
1509
1510 #define SECF_NONE -1
1511
1512 static const struct clock_config stm32mp25_clock_cfg[] = {
1513         STM32_GATE_CFG(CK_BUS_ETH1,             ck_icn_p_eth1,          SECF_NONE),
1514         STM32_GATE_CFG(CK_BUS_ETH2,             ck_icn_p_eth2,          SECF_NONE),
1515         STM32_GATE_CFG(CK_BUS_PCIE,             ck_icn_p_pcie,          SECF_NONE),
1516         STM32_GATE_CFG(CK_BUS_ETHSW,            ck_icn_p_ethsw,         SECF_NONE),
1517         STM32_GATE_CFG(CK_BUS_ADC12,            ck_icn_p_adc12,         SECF_NONE),
1518         STM32_GATE_CFG(CK_BUS_ADC3,             ck_icn_p_adc3,          SECF_NONE),
1519         STM32_GATE_CFG(CK_BUS_CCI,              ck_icn_p_cci,           SECF_NONE),
1520         STM32_GATE_CFG(CK_BUS_CRC,              ck_icn_p_crc,           SECF_NONE),
1521         STM32_GATE_CFG(CK_BUS_MDF1,             ck_icn_p_mdf1,          SECF_NONE),
1522         STM32_GATE_CFG(CK_BUS_OSPIIOM,          ck_icn_p_ospiiom,       SECF_NONE),
1523         STM32_GATE_CFG(CK_BUS_HASH,             ck_icn_p_hash,          SECF_NONE),
1524         STM32_GATE_CFG(CK_BUS_CRYP1,            ck_icn_p_cryp1,         SECF_NONE),
1525         STM32_GATE_CFG(CK_BUS_CRYP2,            ck_icn_p_cryp2,         SECF_NONE),
1526         STM32_GATE_CFG(CK_BUS_ADF1,             ck_icn_p_adf1,          SECF_NONE),
1527         STM32_GATE_CFG(CK_BUS_SPI8,             ck_icn_p_spi8,          SECF_NONE),
1528         STM32_GATE_CFG(CK_BUS_LPUART1,          ck_icn_p_lpuart1,       SECF_NONE),
1529         STM32_GATE_CFG(CK_BUS_I2C8,             ck_icn_p_i2c8,          SECF_NONE),
1530         STM32_GATE_CFG(CK_BUS_LPTIM3,           ck_icn_p_lptim3,        SECF_NONE),
1531         STM32_GATE_CFG(CK_BUS_LPTIM4,           ck_icn_p_lptim4,        SECF_NONE),
1532         STM32_GATE_CFG(CK_BUS_LPTIM5,           ck_icn_p_lptim5,        SECF_NONE),
1533         STM32_GATE_CFG(CK_BUS_IWDG5,            ck_icn_p_iwdg5,         SECF_NONE),
1534         STM32_GATE_CFG(CK_BUS_WWDG2,            ck_icn_p_wwdg2,         SECF_NONE),
1535         STM32_GATE_CFG(CK_BUS_I3C4,             ck_icn_p_i3c4,          SECF_NONE),
1536         STM32_GATE_CFG(CK_BUS_SDMMC1,           ck_icn_m_sdmmc1,        SECF_NONE),
1537         STM32_GATE_CFG(CK_BUS_SDMMC2,           ck_icn_m_sdmmc2,        SECF_NONE),
1538         STM32_GATE_CFG(CK_BUS_SDMMC3,           ck_icn_m_sdmmc3,        SECF_NONE),
1539         STM32_GATE_CFG(CK_BUS_USB2OHCI,         ck_icn_m_usb2ohci,      SECF_NONE),
1540         STM32_GATE_CFG(CK_BUS_USB2EHCI,         ck_icn_m_usb2ehci,      SECF_NONE),
1541         STM32_GATE_CFG(CK_BUS_USB3DR,           ck_icn_m_usb3dr,        SECF_NONE),
1542         STM32_GATE_CFG(CK_BUS_TIM2,             ck_icn_p_tim2,          SECF_NONE),
1543         STM32_GATE_CFG(CK_BUS_TIM3,             ck_icn_p_tim3,          SECF_NONE),
1544         STM32_GATE_CFG(CK_BUS_TIM4,             ck_icn_p_tim4,          SECF_NONE),
1545         STM32_GATE_CFG(CK_BUS_TIM5,             ck_icn_p_tim5,          SECF_NONE),
1546         STM32_GATE_CFG(CK_BUS_TIM6,             ck_icn_p_tim6,          SECF_NONE),
1547         STM32_GATE_CFG(CK_BUS_TIM7,             ck_icn_p_tim7,          SECF_NONE),
1548         STM32_GATE_CFG(CK_BUS_TIM10,            ck_icn_p_tim10,         SECF_NONE),
1549         STM32_GATE_CFG(CK_BUS_TIM11,            ck_icn_p_tim11,         SECF_NONE),
1550         STM32_GATE_CFG(CK_BUS_TIM12,            ck_icn_p_tim12,         SECF_NONE),
1551         STM32_GATE_CFG(CK_BUS_TIM13,            ck_icn_p_tim13,         SECF_NONE),
1552         STM32_GATE_CFG(CK_BUS_TIM14,            ck_icn_p_tim14,         SECF_NONE),
1553         STM32_GATE_CFG(CK_BUS_LPTIM1,           ck_icn_p_lptim1,        SECF_NONE),
1554         STM32_GATE_CFG(CK_BUS_LPTIM2,           ck_icn_p_lptim2,        SECF_NONE),
1555         STM32_GATE_CFG(CK_BUS_SPI2,             ck_icn_p_spi2,          SECF_NONE),
1556         STM32_GATE_CFG(CK_BUS_SPI3,             ck_icn_p_spi3,          SECF_NONE),
1557         STM32_GATE_CFG(CK_BUS_SPDIFRX,          ck_icn_p_spdifrx,       SECF_NONE),
1558         STM32_GATE_CFG(CK_BUS_USART2,           ck_icn_p_usart2,        SECF_NONE),
1559         STM32_GATE_CFG(CK_BUS_USART3,           ck_icn_p_usart3,        SECF_NONE),
1560         STM32_GATE_CFG(CK_BUS_UART4,            ck_icn_p_uart4,         SECF_NONE),
1561         STM32_GATE_CFG(CK_BUS_UART5,            ck_icn_p_uart5,         SECF_NONE),
1562         STM32_GATE_CFG(CK_BUS_I2C1,             ck_icn_p_i2c1,          SECF_NONE),
1563         STM32_GATE_CFG(CK_BUS_I2C2,             ck_icn_p_i2c2,          SECF_NONE),
1564         STM32_GATE_CFG(CK_BUS_I2C3,             ck_icn_p_i2c3,          SECF_NONE),
1565         STM32_GATE_CFG(CK_BUS_I2C4,             ck_icn_p_i2c4,          SECF_NONE),
1566         STM32_GATE_CFG(CK_BUS_I2C5,             ck_icn_p_i2c5,          SECF_NONE),
1567         STM32_GATE_CFG(CK_BUS_I2C6,             ck_icn_p_i2c6,          SECF_NONE),
1568         STM32_GATE_CFG(CK_BUS_I2C7,             ck_icn_p_i2c7,          SECF_NONE),
1569         STM32_GATE_CFG(CK_BUS_I3C1,             ck_icn_p_i3c1,          SECF_NONE),
1570         STM32_GATE_CFG(CK_BUS_I3C2,             ck_icn_p_i3c2,          SECF_NONE),
1571         STM32_GATE_CFG(CK_BUS_I3C3,             ck_icn_p_i3c3,          SECF_NONE),
1572         STM32_GATE_CFG(CK_BUS_TIM1,             ck_icn_p_tim1,          SECF_NONE),
1573         STM32_GATE_CFG(CK_BUS_TIM8,             ck_icn_p_tim8,          SECF_NONE),
1574         STM32_GATE_CFG(CK_BUS_TIM15,            ck_icn_p_tim15,         SECF_NONE),
1575         STM32_GATE_CFG(CK_BUS_TIM16,            ck_icn_p_tim16,         SECF_NONE),
1576         STM32_GATE_CFG(CK_BUS_TIM17,            ck_icn_p_tim17,         SECF_NONE),
1577         STM32_GATE_CFG(CK_BUS_TIM20,            ck_icn_p_tim20,         SECF_NONE),
1578         STM32_GATE_CFG(CK_BUS_SAI1,             ck_icn_p_sai1,          SECF_NONE),
1579         STM32_GATE_CFG(CK_BUS_SAI2,             ck_icn_p_sai2,          SECF_NONE),
1580         STM32_GATE_CFG(CK_BUS_SAI3,             ck_icn_p_sai3,          SECF_NONE),
1581         STM32_GATE_CFG(CK_BUS_SAI4,             ck_icn_p_sai4,          SECF_NONE),
1582         STM32_GATE_CFG(CK_BUS_USART1,           ck_icn_p_usart1,        SECF_NONE),
1583         STM32_GATE_CFG(CK_BUS_USART6,           ck_icn_p_usart6,        SECF_NONE),
1584         STM32_GATE_CFG(CK_BUS_UART7,            ck_icn_p_uart7,         SECF_NONE),
1585         STM32_GATE_CFG(CK_BUS_UART8,            ck_icn_p_uart8,         SECF_NONE),
1586         STM32_GATE_CFG(CK_BUS_UART9,            ck_icn_p_uart9,         SECF_NONE),
1587         STM32_GATE_CFG(CK_BUS_FDCAN,            ck_icn_p_fdcan,         SECF_NONE),
1588         STM32_GATE_CFG(CK_BUS_SPI1,             ck_icn_p_spi1,          SECF_NONE),
1589         STM32_GATE_CFG(CK_BUS_SPI4,             ck_icn_p_spi4,          SECF_NONE),
1590         STM32_GATE_CFG(CK_BUS_SPI5,             ck_icn_p_spi5,          SECF_NONE),
1591         STM32_GATE_CFG(CK_BUS_SPI6,             ck_icn_p_spi6,          SECF_NONE),
1592         STM32_GATE_CFG(CK_BUS_SPI7,             ck_icn_p_spi7,          SECF_NONE),
1593         STM32_GATE_CFG(CK_BUS_IWDG2,            ck_icn_p_iwdg2,         SECF_NONE),
1594         STM32_GATE_CFG(CK_BUS_IWDG3,            ck_icn_p_iwdg3,         SECF_NONE),
1595         STM32_GATE_CFG(CK_BUS_IWDG4,            ck_icn_p_iwdg4,         SECF_NONE),
1596         STM32_GATE_CFG(CK_BUS_WWDG1,            ck_icn_p_wwdg1,         SECF_NONE),
1597         STM32_GATE_CFG(CK_BUS_VREF,             ck_icn_p_vref,          SECF_NONE),
1598         STM32_GATE_CFG(CK_BUS_HDP,              ck_icn_p_hdp,           SECF_NONE),
1599         STM32_GATE_CFG(CK_BUS_IS2M,             ck_icn_p_is2m,          SECF_NONE),
1600         STM32_GATE_CFG(CK_BUS_DSI,              ck_icn_p_dsi,           SECF_NONE),
1601         STM32_GATE_CFG(CK_BUS_LTDC,             ck_icn_p_ltdc,          SECF_NONE),
1602         STM32_GATE_CFG(CK_BUS_CSI,              ck_icn_p_csi,           SECF_NONE),
1603         STM32_GATE_CFG(CK_BUS_DCMIPP,           ck_icn_p_dcmipp,        SECF_NONE),
1604         STM32_GATE_CFG(CK_BUS_LVDS,             ck_icn_p_lvds,          SECF_NONE),
1605         STM32_GATE_CFG(CK_BUS_USBTC,            ck_icn_p_usbtc,         SECF_NONE),
1606         STM32_GATE_CFG(CK_BUS_USB3PCIEPHY,      ck_icn_p_usb3pciephy,   SECF_NONE),
1607         STM32_GATE_CFG(CK_BUS_VDEC,             ck_icn_p_vdec,          SECF_NONE),
1608         STM32_GATE_CFG(CK_BUS_VENC,             ck_icn_p_venc,          SECF_NONE),
1609         STM32_GATE_CFG(CK_KER_TIM2,             ck_ker_tim2,            SECF_NONE),
1610         STM32_GATE_CFG(CK_KER_TIM3,             ck_ker_tim3,            SECF_NONE),
1611         STM32_GATE_CFG(CK_KER_TIM4,             ck_ker_tim4,            SECF_NONE),
1612         STM32_GATE_CFG(CK_KER_TIM5,             ck_ker_tim5,            SECF_NONE),
1613         STM32_GATE_CFG(CK_KER_TIM6,             ck_ker_tim6,            SECF_NONE),
1614         STM32_GATE_CFG(CK_KER_TIM7,             ck_ker_tim7,            SECF_NONE),
1615         STM32_GATE_CFG(CK_KER_TIM10,            ck_ker_tim10,           SECF_NONE),
1616         STM32_GATE_CFG(CK_KER_TIM11,            ck_ker_tim11,           SECF_NONE),
1617         STM32_GATE_CFG(CK_KER_TIM12,            ck_ker_tim12,           SECF_NONE),
1618         STM32_GATE_CFG(CK_KER_TIM13,            ck_ker_tim13,           SECF_NONE),
1619         STM32_GATE_CFG(CK_KER_TIM14,            ck_ker_tim14,           SECF_NONE),
1620         STM32_GATE_CFG(CK_KER_TIM1,             ck_ker_tim1,            SECF_NONE),
1621         STM32_GATE_CFG(CK_KER_TIM8,             ck_ker_tim8,            SECF_NONE),
1622         STM32_GATE_CFG(CK_KER_TIM15,            ck_ker_tim15,           SECF_NONE),
1623         STM32_GATE_CFG(CK_KER_TIM16,            ck_ker_tim16,           SECF_NONE),
1624         STM32_GATE_CFG(CK_KER_TIM17,            ck_ker_tim17,           SECF_NONE),
1625         STM32_GATE_CFG(CK_KER_TIM20,            ck_ker_tim20,           SECF_NONE),
1626         STM32_GATE_CFG(CK_KER_LPTIM1,           ck_ker_lptim1,          SECF_NONE),
1627         STM32_GATE_CFG(CK_KER_LPTIM2,           ck_ker_lptim2,          SECF_NONE),
1628         STM32_GATE_CFG(CK_KER_USART2,           ck_ker_usart2,          SECF_NONE),
1629         STM32_GATE_CFG(CK_KER_UART4,            ck_ker_uart4,           SECF_NONE),
1630         STM32_GATE_CFG(CK_KER_USART3,           ck_ker_usart3,          SECF_NONE),
1631         STM32_GATE_CFG(CK_KER_UART5,            ck_ker_uart5,           SECF_NONE),
1632         STM32_GATE_CFG(CK_KER_SPI2,             ck_ker_spi2,            SECF_NONE),
1633         STM32_GATE_CFG(CK_KER_SPI3,             ck_ker_spi3,            SECF_NONE),
1634         STM32_GATE_CFG(CK_KER_SPDIFRX,          ck_ker_spdifrx,         SECF_NONE),
1635         STM32_GATE_CFG(CK_KER_I2C1,             ck_ker_i2c1,            SECF_NONE),
1636         STM32_GATE_CFG(CK_KER_I2C2,             ck_ker_i2c2,            SECF_NONE),
1637         STM32_GATE_CFG(CK_KER_I3C1,             ck_ker_i3c1,            SECF_NONE),
1638         STM32_GATE_CFG(CK_KER_I3C2,             ck_ker_i3c2,            SECF_NONE),
1639         STM32_GATE_CFG(CK_KER_I2C3,             ck_ker_i2c3,            SECF_NONE),
1640         STM32_GATE_CFG(CK_KER_I2C5,             ck_ker_i2c5,            SECF_NONE),
1641         STM32_GATE_CFG(CK_KER_I3C3,             ck_ker_i3c3,            SECF_NONE),
1642         STM32_GATE_CFG(CK_KER_I2C4,             ck_ker_i2c4,            SECF_NONE),
1643         STM32_GATE_CFG(CK_KER_I2C6,             ck_ker_i2c6,            SECF_NONE),
1644         STM32_GATE_CFG(CK_KER_I2C7,             ck_ker_i2c7,            SECF_NONE),
1645         STM32_GATE_CFG(CK_KER_SPI1,             ck_ker_spi1,            SECF_NONE),
1646         STM32_GATE_CFG(CK_KER_SPI4,             ck_ker_spi4,            SECF_NONE),
1647         STM32_GATE_CFG(CK_KER_SPI5,             ck_ker_spi5,            SECF_NONE),
1648         STM32_GATE_CFG(CK_KER_SPI6,             ck_ker_spi6,            SECF_NONE),
1649         STM32_GATE_CFG(CK_KER_SPI7,             ck_ker_spi7,            SECF_NONE),
1650         STM32_GATE_CFG(CK_KER_USART1,           ck_ker_usart1,          SECF_NONE),
1651         STM32_GATE_CFG(CK_KER_USART6,           ck_ker_usart6,          SECF_NONE),
1652         STM32_GATE_CFG(CK_KER_UART7,            ck_ker_uart7,           SECF_NONE),
1653         STM32_GATE_CFG(CK_KER_UART8,            ck_ker_uart8,           SECF_NONE),
1654         STM32_GATE_CFG(CK_KER_UART9,            ck_ker_uart9,           SECF_NONE),
1655         STM32_GATE_CFG(CK_KER_MDF1,             ck_ker_mdf1,            SECF_NONE),
1656         STM32_GATE_CFG(CK_KER_SAI1,             ck_ker_sai1,            SECF_NONE),
1657         STM32_GATE_CFG(CK_KER_SAI2,             ck_ker_sai2,            SECF_NONE),
1658         STM32_GATE_CFG(CK_KER_SAI3,             ck_ker_sai3,            SECF_NONE),
1659         STM32_GATE_CFG(CK_KER_SAI4,             ck_ker_sai4,            SECF_NONE),
1660         STM32_GATE_CFG(CK_KER_FDCAN,            ck_ker_fdcan,           SECF_NONE),
1661         STM32_GATE_CFG(CK_KER_CSI,              ck_ker_csi,             SECF_NONE),
1662         STM32_GATE_CFG(CK_KER_CSITXESC,         ck_ker_csitxesc,        SECF_NONE),
1663         STM32_GATE_CFG(CK_KER_CSIPHY,           ck_ker_csiphy,          SECF_NONE),
1664         STM32_GATE_CFG(CK_KER_USBTC,            ck_ker_usbtc,           SECF_NONE),
1665         STM32_GATE_CFG(CK_KER_I3C4,             ck_ker_i3c4,            SECF_NONE),
1666         STM32_GATE_CFG(CK_KER_SPI8,             ck_ker_spi8,            SECF_NONE),
1667         STM32_GATE_CFG(CK_KER_I2C8,             ck_ker_i2c8,            SECF_NONE),
1668         STM32_GATE_CFG(CK_KER_LPUART1,          ck_ker_lpuart1,         SECF_NONE),
1669         STM32_GATE_CFG(CK_KER_LPTIM3,           ck_ker_lptim3,          SECF_NONE),
1670         STM32_GATE_CFG(CK_KER_LPTIM4,           ck_ker_lptim4,          SECF_NONE),
1671         STM32_GATE_CFG(CK_KER_LPTIM5,           ck_ker_lptim5,          SECF_NONE),
1672         STM32_GATE_CFG(CK_KER_ADF1,             ck_ker_adf1,            SECF_NONE),
1673         STM32_GATE_CFG(CK_KER_SDMMC1,           ck_ker_sdmmc1,          SECF_NONE),
1674         STM32_GATE_CFG(CK_KER_SDMMC2,           ck_ker_sdmmc2,          SECF_NONE),
1675         STM32_GATE_CFG(CK_KER_SDMMC3,           ck_ker_sdmmc3,          SECF_NONE),
1676         STM32_GATE_CFG(CK_KER_ETH1,             ck_ker_eth1,            SECF_NONE),
1677         STM32_GATE_CFG(CK_ETH1_STP,             ck_ker_eth1stp,         SECF_NONE),
1678         STM32_GATE_CFG(CK_KER_ETHSW,            ck_ker_ethsw,           SECF_NONE),
1679         STM32_GATE_CFG(CK_KER_ETH2,             ck_ker_eth2,            SECF_NONE),
1680         STM32_GATE_CFG(CK_ETH2_STP,             ck_ker_eth2stp,         SECF_NONE),
1681         STM32_GATE_CFG(CK_KER_ETH1PTP,          ck_ker_eth1ptp,         SECF_NONE),
1682         STM32_GATE_CFG(CK_KER_ETH2PTP,          ck_ker_eth2ptp,         SECF_NONE),
1683         STM32_GATE_CFG(CK_BUS_GPU,              ck_icn_m_gpu,           SECF_NONE),
1684         STM32_GATE_CFG(CK_KER_GPU,              ck_ker_gpu,             SECF_NONE),
1685         STM32_GATE_CFG(CK_KER_ETHSWREF,         ck_ker_ethswref,        SECF_NONE),
1686         STM32_GATE_CFG(CK_BUS_ETHSWACMCFG,      ck_icn_p_ethsw_acm_cfg, SECF_NONE),
1687         STM32_GATE_CFG(CK_BUS_ETHSWACMMSG, ck_icn_p_ethsw_acm_msg,      SECF_NONE),
1688         STM32_GATE_CFG(CK_ETH1_MAC,             ck_ker_eth1mac,         SECF_NONE),
1689         STM32_GATE_CFG(CK_ETH1_TX,              ck_ker_eth1tx,          SECF_NONE),
1690         STM32_GATE_CFG(CK_ETH1_RX,              ck_ker_eth1rx,          SECF_NONE),
1691         STM32_GATE_CFG(CK_ETH2_MAC,             ck_ker_eth2mac,         SECF_NONE),
1692         STM32_GATE_CFG(CK_ETH2_TX,              ck_ker_eth2tx,          SECF_NONE),
1693         STM32_GATE_CFG(CK_ETH2_RX,              ck_ker_eth2rx,          SECF_NONE),
1694         STM32_COMPOSITE_CFG(CK_MCO1,            ck_mco1,                SECF_NONE),
1695         STM32_COMPOSITE_CFG(CK_MCO2,            ck_mco2,                SECF_NONE),
1696         STM32_COMPOSITE_CFG(CK_KER_ADC12,       ck_ker_adc12,           SECF_NONE),
1697         STM32_COMPOSITE_CFG(CK_KER_ADC3,        ck_ker_adc3,            SECF_NONE),
1698         STM32_COMPOSITE_CFG(CK_KER_USB2PHY1,    ck_ker_usb2phy1,        SECF_NONE),
1699         STM32_GATE_CFG(CK_KER_USB2PHY2,         ck_ker_usb2phy2,        SECF_NONE),
1700         STM32_COMPOSITE_CFG(CK_KER_USB2PHY2EN,  ck_ker_usb2phy2_en,     SECF_NONE),
1701         STM32_COMPOSITE_CFG(CK_KER_USB3PCIEPHY, ck_ker_usb3pciephy,     SECF_NONE),
1702         STM32_COMPOSITE_CFG(CK_KER_DSIBLANE,    clk_lanebyte,           SECF_NONE),
1703         STM32_COMPOSITE_CFG(CK_KER_DSIPHY,      clk_phy_dsi,            SECF_NONE),
1704         STM32_COMPOSITE_CFG(CK_KER_LVDSPHY,     ck_ker_lvdsphy,         SECF_NONE),
1705         STM32_COMPOSITE_CFG(CK_KER_DTS,         ck_ker_dts,             SECF_NONE),
1706         STM32_GATE_CFG(CK_KER_LTDC,             ck_ker_ltdc,            SECF_NONE),
1707 };
1708
1709 #define RESET_MP25(id, _offset, _bit_idx, _set_clr)     \
1710         [id] = &(struct stm32_reset_cfg){               \
1711                 .offset         = (_offset),            \
1712                 .bit_idx        = (_bit_idx),           \
1713                 .set_clr        = (_set_clr),           \
1714         }
1715
1716 static const struct stm32_reset_cfg *stm32mp25_reset_cfg[STM32MP25_LAST_RESET] = {
1717         RESET_MP25(TIM1_R,              RCC_TIM1CFGR,           0,      0),
1718         RESET_MP25(TIM2_R,              RCC_TIM2CFGR,           0,      0),
1719         RESET_MP25(TIM3_R,              RCC_TIM3CFGR,           0,      0),
1720         RESET_MP25(TIM4_R,              RCC_TIM4CFGR,           0,      0),
1721         RESET_MP25(TIM5_R,              RCC_TIM5CFGR,           0,      0),
1722         RESET_MP25(TIM6_R,              RCC_TIM6CFGR,           0,      0),
1723         RESET_MP25(TIM7_R,              RCC_TIM7CFGR,           0,      0),
1724         RESET_MP25(TIM8_R,              RCC_TIM8CFGR,           0,      0),
1725         RESET_MP25(TIM10_R,             RCC_TIM10CFGR,          0,      0),
1726         RESET_MP25(TIM11_R,             RCC_TIM11CFGR,          0,      0),
1727         RESET_MP25(TIM12_R,             RCC_TIM12CFGR,          0,      0),
1728         RESET_MP25(TIM13_R,             RCC_TIM13CFGR,          0,      0),
1729         RESET_MP25(TIM14_R,             RCC_TIM14CFGR,          0,      0),
1730         RESET_MP25(TIM15_R,             RCC_TIM15CFGR,          0,      0),
1731         RESET_MP25(TIM16_R,             RCC_TIM16CFGR,          0,      0),
1732         RESET_MP25(TIM17_R,             RCC_TIM17CFGR,          0,      0),
1733         RESET_MP25(TIM20_R,             RCC_TIM20CFGR,          0,      0),
1734         RESET_MP25(LPTIM1_R,            RCC_LPTIM1CFGR,         0,      0),
1735         RESET_MP25(LPTIM2_R,            RCC_LPTIM2CFGR,         0,      0),
1736         RESET_MP25(LPTIM3_R,            RCC_LPTIM3CFGR,         0,      0),
1737         RESET_MP25(LPTIM4_R,            RCC_LPTIM4CFGR,         0,      0),
1738         RESET_MP25(LPTIM5_R,            RCC_LPTIM5CFGR,         0,      0),
1739         RESET_MP25(SPI1_R,              RCC_SPI1CFGR,           0,      0),
1740         RESET_MP25(SPI2_R,              RCC_SPI2CFGR,           0,      0),
1741         RESET_MP25(SPI3_R,              RCC_SPI3CFGR,           0,      0),
1742         RESET_MP25(SPI4_R,              RCC_SPI4CFGR,           0,      0),
1743         RESET_MP25(SPI5_R,              RCC_SPI5CFGR,           0,      0),
1744         RESET_MP25(SPI6_R,              RCC_SPI6CFGR,           0,      0),
1745         RESET_MP25(SPI7_R,              RCC_SPI7CFGR,           0,      0),
1746         RESET_MP25(SPI8_R,              RCC_SPI8CFGR,           0,      0),
1747         RESET_MP25(SPDIFRX_R,           RCC_SPDIFRXCFGR,        0,      0),
1748         RESET_MP25(USART1_R,            RCC_USART1CFGR,         0,      0),
1749         RESET_MP25(USART2_R,            RCC_USART2CFGR,         0,      0),
1750         RESET_MP25(USART3_R,            RCC_USART3CFGR,         0,      0),
1751         RESET_MP25(UART4_R,             RCC_UART4CFGR,          0,      0),
1752         RESET_MP25(UART5_R,             RCC_UART5CFGR,          0,      0),
1753         RESET_MP25(USART6_R,            RCC_USART6CFGR,         0,      0),
1754         RESET_MP25(UART7_R,             RCC_UART7CFGR,          0,      0),
1755         RESET_MP25(UART8_R,             RCC_UART8CFGR,          0,      0),
1756         RESET_MP25(UART9_R,             RCC_UART9CFGR,          0,      0),
1757         RESET_MP25(LPUART1_R,           RCC_LPUART1CFGR,        0,      0),
1758         RESET_MP25(IS2M_R,              RCC_IS2MCFGR,           0,      0),
1759         RESET_MP25(I2C1_R,              RCC_I2C1CFGR,           0,      0),
1760         RESET_MP25(I2C2_R,              RCC_I2C2CFGR,           0,      0),
1761         RESET_MP25(I2C3_R,              RCC_I2C3CFGR,           0,      0),
1762         RESET_MP25(I2C4_R,              RCC_I2C4CFGR,           0,      0),
1763         RESET_MP25(I2C5_R,              RCC_I2C5CFGR,           0,      0),
1764         RESET_MP25(I2C6_R,              RCC_I2C6CFGR,           0,      0),
1765         RESET_MP25(I2C7_R,              RCC_I2C7CFGR,           0,      0),
1766         RESET_MP25(I2C8_R,              RCC_I2C8CFGR,           0,      0),
1767         RESET_MP25(SAI1_R,              RCC_SAI1CFGR,           0,      0),
1768         RESET_MP25(SAI2_R,              RCC_SAI2CFGR,           0,      0),
1769         RESET_MP25(SAI3_R,              RCC_SAI3CFGR,           0,      0),
1770         RESET_MP25(SAI4_R,              RCC_SAI4CFGR,           0,      0),
1771         RESET_MP25(MDF1_R,              RCC_MDF1CFGR,           0,      0),
1772         RESET_MP25(MDF2_R,              RCC_ADF1CFGR,           0,      0),
1773         RESET_MP25(FDCAN_R,             RCC_FDCANCFGR,          0,      0),
1774         RESET_MP25(HDP_R,               RCC_HDPCFGR,            0,      0),
1775         RESET_MP25(ADC12_R,             RCC_ADC12CFGR,          0,      0),
1776         RESET_MP25(ADC3_R,              RCC_ADC3CFGR,           0,      0),
1777         RESET_MP25(ETH1_R,              RCC_ETH1CFGR,           0,      0),
1778         RESET_MP25(ETH2_R,              RCC_ETH2CFGR,           0,      0),
1779         RESET_MP25(USBH_R,              RCC_USBHCFGR,           0,      0),
1780         RESET_MP25(USB2PHY1_R,          RCC_USB2PHY1CFGR,       0,      0),
1781         RESET_MP25(USB2PHY2_R,          RCC_USB2PHY2CFGR,       0,      0),
1782         RESET_MP25(USB3DR_R,            RCC_USB3DRCFGR,         0,      0),
1783         RESET_MP25(USB3PCIEPHY_R,       RCC_USB3PCIEPHYCFGR,    0,      0),
1784         RESET_MP25(USBTC_R,             RCC_USBTCCFGR,          0,      0),
1785         RESET_MP25(ETHSW_R,             RCC_ETHSWCFGR,          0,      0),
1786         RESET_MP25(SDMMC1_R,            RCC_SDMMC1CFGR,         0,      0),
1787         RESET_MP25(SDMMC1DLL_R,         RCC_SDMMC1CFGR,         16,     0),
1788         RESET_MP25(SDMMC2_R,            RCC_SDMMC2CFGR,         0,      0),
1789         RESET_MP25(SDMMC2DLL_R,         RCC_SDMMC2CFGR,         16,     0),
1790         RESET_MP25(SDMMC3_R,            RCC_SDMMC3CFGR,         0,      0),
1791         RESET_MP25(SDMMC3DLL_R,         RCC_SDMMC3CFGR,         16,     0),
1792         RESET_MP25(GPU_R,               RCC_GPUCFGR,            0,      0),
1793         RESET_MP25(LTDC_R,              RCC_LTDCCFGR,           0,      0),
1794         RESET_MP25(DSI_R,               RCC_DSICFGR,            0,      0),
1795         RESET_MP25(LVDS_R,              RCC_LVDSCFGR,           0,      0),
1796         RESET_MP25(CSI_R,               RCC_CSICFGR,            0,      0),
1797         RESET_MP25(DCMIPP_R,            RCC_DCMIPPCFGR,         0,      0),
1798         RESET_MP25(CCI_R,               RCC_CCICFGR,            0,      0),
1799         RESET_MP25(VDEC_R,              RCC_VDECCFGR,           0,      0),
1800         RESET_MP25(VENC_R,              RCC_VENCCFGR,           0,      0),
1801         RESET_MP25(WWDG1_R,             RCC_WWDG1CFGR,          0,      0),
1802         RESET_MP25(WWDG2_R,             RCC_WWDG2CFGR,          0,      0),
1803         RESET_MP25(VREF_R,              RCC_VREFCFGR,           0,      0),
1804         RESET_MP25(DTS_R,               RCC_DTSCFGR,            0,      0),
1805         RESET_MP25(CRC_R,               RCC_CRCCFGR,            0,      0),
1806         RESET_MP25(SERC_R,              RCC_SERCCFGR,           0,      0),
1807         RESET_MP25(OSPIIOM_R,           RCC_OSPIIOMCFGR,        0,      0),
1808         RESET_MP25(I3C1_R,              RCC_I3C1CFGR,           0,      0),
1809         RESET_MP25(I3C2_R,              RCC_I3C2CFGR,           0,      0),
1810         RESET_MP25(I3C3_R,              RCC_I3C3CFGR,           0,      0),
1811         RESET_MP25(I3C4_R,              RCC_I3C4CFGR,           0,      0),
1812         RESET_MP25(IWDG2_KER_R,         RCC_IWDGC1CFGSETR,      18,     1),
1813         RESET_MP25(IWDG4_KER_R,         RCC_IWDGC2CFGSETR,      18,     1),
1814         RESET_MP25(RNG_R,               RCC_RNGCFGR,            0,      0),
1815         RESET_MP25(PKA_R,               RCC_PKACFGR,            0,      0),
1816         RESET_MP25(SAES_R,              RCC_SAESCFGR,           0,      0),
1817         RESET_MP25(HASH_R,              RCC_HASHCFGR,           0,      0),
1818         RESET_MP25(CRYP1_R,             RCC_CRYP1CFGR,          0,      0),
1819         RESET_MP25(CRYP2_R,             RCC_CRYP2CFGR,          0,      0),
1820         RESET_MP25(PCIE_R,              RCC_PCIECFGR,           0,      0),
1821 };
1822
1823 static u16 stm32mp25_cpt_gate[GATE_NB];
1824
1825 static struct clk_stm32_clock_data stm32mp25_clock_data = {
1826         .gate_cpt       = stm32mp25_cpt_gate,
1827         .gates          = stm32mp25_gates,
1828         .muxes          = stm32mp25_muxes,
1829 };
1830
1831 static struct clk_stm32_reset_data stm32mp25_reset_data = {
1832         .reset_lines    = stm32mp25_reset_cfg,
1833         .nr_lines       = ARRAY_SIZE(stm32mp25_reset_cfg),
1834 };
1835
1836 static const struct stm32_rcc_match_data stm32mp25_data = {
1837         .tab_clocks     = stm32mp25_clock_cfg,
1838         .num_clocks     = ARRAY_SIZE(stm32mp25_clock_cfg),
1839         .maxbinding     = STM32MP25_LAST_CLK,
1840         .clock_data     = &stm32mp25_clock_data,
1841         .reset_data     = &stm32mp25_reset_data,
1842 };
1843
1844 static const struct of_device_id stm32mp25_match_data[] = {
1845         { .compatible = "st,stm32mp25-rcc", .data = &stm32mp25_data, },
1846         { }
1847 };
1848 MODULE_DEVICE_TABLE(of, stm32mp25_match_data);
1849
1850 static int stm32mp25_rcc_clocks_probe(struct platform_device *pdev)
1851 {
1852         struct device *dev = &pdev->dev;
1853         void __iomem *base;
1854
1855         base = devm_platform_ioremap_resource(pdev, 0);
1856         if (IS_ERR(base))
1857                 return PTR_ERR(base);
1858
1859         return stm32_rcc_init(dev, stm32mp25_match_data, base);
1860 }
1861
1862 static struct platform_driver stm32mp25_rcc_clocks_driver = {
1863         .driver = {
1864                 .name = "stm32mp25_rcc",
1865                 .of_match_table = stm32mp25_match_data,
1866         },
1867         .probe = stm32mp25_rcc_clocks_probe,
1868 };
1869
1870 static int __init stm32mp25_clocks_init(void)
1871 {
1872         return platform_driver_register(&stm32mp25_rcc_clocks_driver);
1873 }
1874
1875 core_initcall(stm32mp25_clocks_init);