drivers/gpu/drm/i915/intel_sprite.c

   1 /*
   2  * Copyright © 2011 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  20  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  21  * SOFTWARE.
  22  *
  23  * Authors:
  24  *   Jesse Barnes <[email protected]>
  25  *
  26  * New plane/sprite handling.
  27  *
  28  * The older chips had a separate interface for programming plane related
  29  * registers; newer ones are much simpler and we can use the new DRM plane
  30  * support.
  31  */
  32 #include <drm/drmP.h>
  33 #include <drm/drm_crtc.h>
  34 #include <drm/drm_fourcc.h>
  35 #include <drm/drm_rect.h>
  36 #include <drm/drm_atomic.h>
  37 #include <drm/drm_plane_helper.h>
  38 #include "intel_drv.h"
  39 #include "intel_frontbuffer.h"
  40 #include <drm/i915_drm.h>
  41 #include "i915_drv.h"
  42
  43 static bool
  44 format_is_yuv(uint32_t format)
  45 {
  46         switch (format) {
  47         case DRM_FORMAT_YUYV:
  48         case DRM_FORMAT_UYVY:
  49         case DRM_FORMAT_VYUY:
  50         case DRM_FORMAT_YVYU:
  51                 return true;
  52         default:
  53                 return false;
  54         }
  55 }
  56
  57 int intel_usecs_to_scanlines(const struct drm_display_mode *adjusted_mode,
  58                              int usecs)
  59 {
  60         /* paranoia */
  61         if (!adjusted_mode->crtc_htotal)
  62                 return 1;
  63
  64         return DIV_ROUND_UP(usecs * adjusted_mode->crtc_clock,
  65                             1000 * adjusted_mode->crtc_htotal);
  66 }
  67
  68 #define VBLANK_EVASION_TIME_US 100
  69
  70 /**
  71  * intel_pipe_update_start() - start update of a set of display registers
  72  * @crtc: the crtc of which the registers are going to be updated
  73  * @start_vbl_count: vblank counter return pointer used for error checking
  74  *
  75  * Mark the start of an update to pipe registers that should be updated
  76  * atomically regarding vblank. If the next vblank will happens within
  77  * the next 100 us, this function waits until the vblank passes.
  78  *
  79  * After a successful call to this function, interrupts will be disabled
  80  * until a subsequent call to intel_pipe_update_end(). That is done to
  81  * avoid random delays. The value written to @start_vbl_count should be
  82  * supplied to intel_pipe_update_end() for error checking.
  83  */
  84 void intel_pipe_update_start(struct intel_crtc *crtc)
  85 {
  86         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
  87         const struct drm_display_mode *adjusted_mode = &crtc->config->base.adjusted_mode;
  88         long timeout = msecs_to_jiffies_timeout(1);
  89         int scanline, min, max, vblank_start;
  90         wait_queue_head_t *wq = drm_crtc_vblank_waitqueue(&crtc->base);
  91         bool need_vlv_dsi_wa = (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) &&
  92                 intel_crtc_has_type(crtc->config, INTEL_OUTPUT_DSI);
  93         DEFINE_WAIT(wait);
  94
  95         vblank_start = adjusted_mode->crtc_vblank_start;
  96         if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
  97                 vblank_start = DIV_ROUND_UP(vblank_start, 2);
  98
  99         /* FIXME needs to be calibrated sensibly */
 100         min = vblank_start - intel_usecs_to_scanlines(adjusted_mode,
 101                                                       VBLANK_EVASION_TIME_US);
 102         max = vblank_start - 1;
 103
 104         local_irq_disable();
 105
 106         if (min <= 0 || max <= 0)
 107                 return;
 108
 109         if (WARN_ON(drm_crtc_vblank_get(&crtc->base)))
 110                 return;
 111
 112         crtc->debug.min_vbl = min;
 113         crtc->debug.max_vbl = max;
 114         trace_i915_pipe_update_start(crtc);
 115
 116         for (;;) {
 117                 /*
 118                  * prepare_to_wait() has a memory barrier, which guarantees
 119                  * other CPUs can see the task state update by the time we
 120                  * read the scanline.
 121                  */
 122                 prepare_to_wait(wq, &wait, TASK_UNINTERRUPTIBLE);
 123
 124                 scanline = intel_get_crtc_scanline(crtc);
 125                 if (scanline < min || scanline > max)
 126                         break;
 127
 128                 if (timeout <= 0) {
 129                         DRM_ERROR("Potential atomic update failure on pipe %c\n",
 130                                   pipe_name(crtc->pipe));
 131                         break;
 132                 }
 133
 134                 local_irq_enable();
 135
 136                 timeout = schedule_timeout(timeout);
 137
 138                 local_irq_disable();
 139         }
 140
 141         finish_wait(wq, &wait);
 142
 143         drm_crtc_vblank_put(&crtc->base);
 144
 145         /*
 146          * On VLV/CHV DSI the scanline counter would appear to
 147          * increment approx. 1/3 of a scanline before start of vblank.
 148          * The registers still get latched at start of vblank however.
 149          * This means we must not write any registers on the first
 150          * line of vblank (since not the whole line is actually in
 151          * vblank). And unfortunately we can't use the interrupt to
 152          * wait here since it will fire too soon. We could use the
 153          * frame start interrupt instead since it will fire after the
 154          * critical scanline, but that would require more changes
 155          * in the interrupt code. So for now we'll just do the nasty
 156          * thing and poll for the bad scanline to pass us by.
 157          *
 158          * FIXME figure out if BXT+ DSI suffers from this as well
 159          */
 160         while (need_vlv_dsi_wa && scanline == vblank_start)
 161                 scanline = intel_get_crtc_scanline(crtc);
 162
 163         crtc->debug.scanline_start = scanline;
 164         crtc->debug.start_vbl_time = ktime_get();
 165         crtc->debug.start_vbl_count = intel_crtc_get_vblank_counter(crtc);
 166
 167         trace_i915_pipe_update_vblank_evaded(crtc);
 168 }
 169
 170 /**
 171  * intel_pipe_update_end() - end update of a set of display registers
 172  * @crtc: the crtc of which the registers were updated
 173  * @start_vbl_count: start vblank counter (used for error checking)
 174  *
 175  * Mark the end of an update started with intel_pipe_update_start(). This
 176  * re-enables interrupts and verifies the update was actually completed
 177  * before a vblank using the value of @start_vbl_count.
 178  */
 179 void intel_pipe_update_end(struct intel_crtc *crtc)
 180 {
 181         enum pipe pipe = crtc->pipe;
 182         int scanline_end = intel_get_crtc_scanline(crtc);
 183         u32 end_vbl_count = intel_crtc_get_vblank_counter(crtc);
 184         ktime_t end_vbl_time = ktime_get();
 185         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 186
 187         trace_i915_pipe_update_end(crtc, end_vbl_count, scanline_end);
 188
 189         /* We're still in the vblank-evade critical section, this can't race.
 190          * Would be slightly nice to just grab the vblank count and arm the
 191          * event outside of the critical section - the spinlock might spin for a
 192          * while ... */
 193         if (crtc->base.state->event) {
 194                 WARN_ON(drm_crtc_vblank_get(&crtc->base) != 0);
 195
 196                 spin_lock(&crtc->base.dev->event_lock);
 197                 drm_crtc_arm_vblank_event(&crtc->base, crtc->base.state->event);
 198                 spin_unlock(&crtc->base.dev->event_lock);
 199
 200                 crtc->base.state->event = NULL;
 201         }
 202
 203         local_irq_enable();
 204
 205         if (intel_vgpu_active(dev_priv))
 206                 return;
 207
 208         if (crtc->debug.start_vbl_count &&
 209             crtc->debug.start_vbl_count != end_vbl_count) {
 210                 DRM_ERROR("Atomic update failure on pipe %c (start=%u end=%u) time %lld us, min %d, max %d, scanline start %d, end %d\n",
 211                           pipe_name(pipe), crtc->debug.start_vbl_count,
 212                           end_vbl_count,
 213                           ktime_us_delta(end_vbl_time, crtc->debug.start_vbl_time),
 214                           crtc->debug.min_vbl, crtc->debug.max_vbl,
 215                           crtc->debug.scanline_start, scanline_end);
 216         }
 217 #ifdef CONFIG_DRM_I915_DEBUG_VBLANK_EVADE
 218         else if (ktime_us_delta(end_vbl_time, crtc->debug.start_vbl_time) >
 219                  VBLANK_EVASION_TIME_US)
 220                 DRM_WARN("Atomic update on pipe (%c) took %lld us, max time under evasion is %u us\n",
 221                          pipe_name(pipe),
 222                          ktime_us_delta(end_vbl_time, crtc->debug.start_vbl_time),
 223                          VBLANK_EVASION_TIME_US);
 224 #endif
 225 }
 226
 227 static void
 228 skl_update_plane(struct intel_plane *plane,
 229                  const struct intel_crtc_state *crtc_state,
 230                  const struct intel_plane_state *plane_state)
 231 {
 232         struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
 233         const struct drm_framebuffer *fb = plane_state->base.fb;
 234         enum plane_id plane_id = plane->id;
 235         enum pipe pipe = plane->pipe;
 236         u32 plane_ctl = plane_state->ctl;
 237         const struct drm_intel_sprite_colorkey *key = &plane_state->ckey;
 238         u32 surf_addr = plane_state->main.offset;
 239         unsigned int rotation = plane_state->base.rotation;
 240         u32 stride = skl_plane_stride(fb, 0, rotation);
 241         int crtc_x = plane_state->base.dst.x1;
 242         int crtc_y = plane_state->base.dst.y1;
 243         uint32_t crtc_w = drm_rect_width(&plane_state->base.dst);
 244         uint32_t crtc_h = drm_rect_height(&plane_state->base.dst);
 245         uint32_t x = plane_state->main.x;
 246         uint32_t y = plane_state->main.y;
 247         uint32_t src_w = drm_rect_width(&plane_state->base.src) >> 16;
 248         uint32_t src_h = drm_rect_height(&plane_state->base.src) >> 16;
 249         unsigned long irqflags;
 250
 251         /* Sizes are 0 based */
 252         src_w--;
 253         src_h--;
 254         crtc_w--;
 255         crtc_h--;
 256
 257         spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
 258
 259         if (IS_GEMINILAKE(dev_priv) || IS_CANNONLAKE(dev_priv)) {
 260                 I915_WRITE_FW(PLANE_COLOR_CTL(pipe, plane_id),
 261                               PLANE_COLOR_PIPE_GAMMA_ENABLE |
 262                               PLANE_COLOR_PIPE_CSC_ENABLE |
 263                               PLANE_COLOR_PLANE_GAMMA_DISABLE);
 264         }
 265
 266         if (key->flags) {
 267                 I915_WRITE_FW(PLANE_KEYVAL(pipe, plane_id), key->min_value);
 268                 I915_WRITE_FW(PLANE_KEYMAX(pipe, plane_id), key->max_value);
 269                 I915_WRITE_FW(PLANE_KEYMSK(pipe, plane_id), key->channel_mask);
 270         }
 271
 272         I915_WRITE_FW(PLANE_OFFSET(pipe, plane_id), (y << 16) | x);
 273         I915_WRITE_FW(PLANE_STRIDE(pipe, plane_id), stride);
 274         I915_WRITE_FW(PLANE_SIZE(pipe, plane_id), (src_h << 16) | src_w);
 275
 276         /* program plane scaler */
 277         if (plane_state->scaler_id >= 0) {
 278                 int scaler_id = plane_state->scaler_id;
 279                 const struct intel_scaler *scaler;
 280
 281                 scaler = &crtc_state->scaler_state.scalers[scaler_id];
 282
 283                 I915_WRITE_FW(SKL_PS_CTRL(pipe, scaler_id),
 284                               PS_SCALER_EN | PS_PLANE_SEL(plane_id) | scaler->mode);
 285                 I915_WRITE_FW(SKL_PS_PWR_GATE(pipe, scaler_id), 0);
 286                 I915_WRITE_FW(SKL_PS_WIN_POS(pipe, scaler_id), (crtc_x << 16) | crtc_y);
 287                 I915_WRITE_FW(SKL_PS_WIN_SZ(pipe, scaler_id),
 288                               ((crtc_w + 1) << 16)|(crtc_h + 1));
 289
 290                 I915_WRITE_FW(PLANE_POS(pipe, plane_id), 0);
 291         } else {
 292                 I915_WRITE_FW(PLANE_POS(pipe, plane_id), (crtc_y << 16) | crtc_x);
 293         }
 294
 295         I915_WRITE_FW(PLANE_CTL(pipe, plane_id), plane_ctl);
 296         I915_WRITE_FW(PLANE_SURF(pipe, plane_id),
 297                       intel_plane_ggtt_offset(plane_state) + surf_addr);
 298         POSTING_READ_FW(PLANE_SURF(pipe, plane_id));
 299
 300         spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
 301 }
 302
 303 static void
 304 skl_disable_plane(struct intel_plane *plane, struct intel_crtc *crtc)
 305 {
 306         struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
 307         enum plane_id plane_id = plane->id;
 308         enum pipe pipe = plane->pipe;
 309         unsigned long irqflags;
 310
 311         spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
 312
 313         I915_WRITE_FW(PLANE_CTL(pipe, plane_id), 0);
 314
 315         I915_WRITE_FW(PLANE_SURF(pipe, plane_id), 0);
 316         POSTING_READ_FW(PLANE_SURF(pipe, plane_id));
 317
 318         spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
 319 }
 320
 321 static void
 322 chv_update_csc(struct intel_plane *plane, uint32_t format)
 323 {
 324         struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
 325         enum plane_id plane_id = plane->id;
 326
 327         /* Seems RGB data bypasses the CSC always */
 328         if (!format_is_yuv(format))
 329                 return;
 330
 331         /*
 332          * BT.601 limited range YCbCr -> full range RGB
 333          *
 334          * |r|   | 6537 4769     0|   |cr  |
 335          * |g| = |-3330 4769 -1605| x |y-64|
 336          * |b|   |    0 4769  8263|   |cb  |
 337          *
 338          * Cb and Cr apparently come in as signed already, so no
 339          * need for any offset. For Y we need to remove the offset.
 340          */
 341         I915_WRITE_FW(SPCSCYGOFF(plane_id), SPCSC_OOFF(0) | SPCSC_IOFF(-64));
 342         I915_WRITE_FW(SPCSCCBOFF(plane_id), SPCSC_OOFF(0) | SPCSC_IOFF(0));
 343         I915_WRITE_FW(SPCSCCROFF(plane_id), SPCSC_OOFF(0) | SPCSC_IOFF(0));
 344
 345         I915_WRITE_FW(SPCSCC01(plane_id), SPCSC_C1(4769) | SPCSC_C0(6537));
 346         I915_WRITE_FW(SPCSCC23(plane_id), SPCSC_C1(-3330) | SPCSC_C0(0));
 347         I915_WRITE_FW(SPCSCC45(plane_id), SPCSC_C1(-1605) | SPCSC_C0(4769));
 348         I915_WRITE_FW(SPCSCC67(plane_id), SPCSC_C1(4769) | SPCSC_C0(0));
 349         I915_WRITE_FW(SPCSCC8(plane_id), SPCSC_C0(8263));
 350
 351         I915_WRITE_FW(SPCSCYGICLAMP(plane_id), SPCSC_IMAX(940) | SPCSC_IMIN(64));
 352         I915_WRITE_FW(SPCSCCBICLAMP(plane_id), SPCSC_IMAX(448) | SPCSC_IMIN(-448));
 353         I915_WRITE_FW(SPCSCCRICLAMP(plane_id), SPCSC_IMAX(448) | SPCSC_IMIN(-448));
 354
 355         I915_WRITE_FW(SPCSCYGOCLAMP(plane_id), SPCSC_OMAX(1023) | SPCSC_OMIN(0));
 356         I915_WRITE_FW(SPCSCCBOCLAMP(plane_id), SPCSC_OMAX(1023) | SPCSC_OMIN(0));
 357         I915_WRITE_FW(SPCSCCROCLAMP(plane_id), SPCSC_OMAX(1023) | SPCSC_OMIN(0));
 358 }
 359
 360 static u32 vlv_sprite_ctl(const struct intel_crtc_state *crtc_state,
 361                           const struct intel_plane_state *plane_state)
 362 {
 363         const struct drm_framebuffer *fb = plane_state->base.fb;
 364         unsigned int rotation = plane_state->base.rotation;
 365         const struct drm_intel_sprite_colorkey *key = &plane_state->ckey;
 366         u32 sprctl;
 367
 368         sprctl = SP_ENABLE | SP_GAMMA_ENABLE;
 369
 370         switch (fb->format->format) {
 371         case DRM_FORMAT_YUYV:
 372                 sprctl |= SP_FORMAT_YUV422 | SP_YUV_ORDER_YUYV;
 373                 break;
 374         case DRM_FORMAT_YVYU:
 375                 sprctl |= SP_FORMAT_YUV422 | SP_YUV_ORDER_YVYU;
 376                 break;
 377         case DRM_FORMAT_UYVY:
 378                 sprctl |= SP_FORMAT_YUV422 | SP_YUV_ORDER_UYVY;
 379                 break;
 380         case DRM_FORMAT_VYUY:
 381                 sprctl |= SP_FORMAT_YUV422 | SP_YUV_ORDER_VYUY;
 382                 break;
 383         case DRM_FORMAT_RGB565:
 384                 sprctl |= SP_FORMAT_BGR565;
 385                 break;
 386         case DRM_FORMAT_XRGB8888:
 387                 sprctl |= SP_FORMAT_BGRX8888;
 388                 break;
 389         case DRM_FORMAT_ARGB8888:
 390                 sprctl |= SP_FORMAT_BGRA8888;
 391                 break;
 392         case DRM_FORMAT_XBGR2101010:
 393                 sprctl |= SP_FORMAT_RGBX1010102;
 394                 break;
 395         case DRM_FORMAT_ABGR2101010:
 396                 sprctl |= SP_FORMAT_RGBA1010102;
 397                 break;
 398         case DRM_FORMAT_XBGR8888:
 399                 sprctl |= SP_FORMAT_RGBX8888;
 400                 break;
 401         case DRM_FORMAT_ABGR8888:
 402                 sprctl |= SP_FORMAT_RGBA8888;
 403                 break;
 404         default:
 405                 MISSING_CASE(fb->format->format);
 406                 return 0;
 407         }
 408
 409         if (fb->modifier == I915_FORMAT_MOD_X_TILED)
 410                 sprctl |= SP_TILED;
 411
 412         if (rotation & DRM_MODE_ROTATE_180)
 413                 sprctl |= SP_ROTATE_180;
 414
 415         if (rotation & DRM_MODE_REFLECT_X)
 416                 sprctl |= SP_MIRROR;
 417
 418         if (key->flags & I915_SET_COLORKEY_SOURCE)
 419                 sprctl |= SP_SOURCE_KEY;
 420
 421         return sprctl;
 422 }
 423
 424 static void
 425 vlv_update_plane(struct intel_plane *plane,
 426                  const struct intel_crtc_state *crtc_state,
 427                  const struct intel_plane_state *plane_state)
 428 {
 429         struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
 430         const struct drm_framebuffer *fb = plane_state->base.fb;
 431         enum pipe pipe = plane->pipe;
 432         enum plane_id plane_id = plane->id;
 433         u32 sprctl = plane_state->ctl;
 434         u32 sprsurf_offset = plane_state->main.offset;
 435         u32 linear_offset;
 436         const struct drm_intel_sprite_colorkey *key = &plane_state->ckey;
 437         int crtc_x = plane_state->base.dst.x1;
 438         int crtc_y = plane_state->base.dst.y1;
 439         uint32_t crtc_w = drm_rect_width(&plane_state->base.dst);
 440         uint32_t crtc_h = drm_rect_height(&plane_state->base.dst);
 441         uint32_t x = plane_state->main.x;
 442         uint32_t y = plane_state->main.y;
 443         unsigned long irqflags;
 444
 445         /* Sizes are 0 based */
 446         crtc_w--;
 447         crtc_h--;
 448
 449         linear_offset = intel_fb_xy_to_linear(x, y, plane_state, 0);
 450
 451         spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
 452
 453         if (IS_CHERRYVIEW(dev_priv) && pipe == PIPE_B)
 454                 chv_update_csc(plane, fb->format->format);
 455
 456         if (key->flags) {
 457                 I915_WRITE_FW(SPKEYMINVAL(pipe, plane_id), key->min_value);
 458                 I915_WRITE_FW(SPKEYMAXVAL(pipe, plane_id), key->max_value);
 459                 I915_WRITE_FW(SPKEYMSK(pipe, plane_id), key->channel_mask);
 460         }
 461         I915_WRITE_FW(SPSTRIDE(pipe, plane_id), fb->pitches[0]);
 462         I915_WRITE_FW(SPPOS(pipe, plane_id), (crtc_y << 16) | crtc_x);
 463
 464         if (fb->modifier == I915_FORMAT_MOD_X_TILED)
 465                 I915_WRITE_FW(SPTILEOFF(pipe, plane_id), (y << 16) | x);
 466         else
 467                 I915_WRITE_FW(SPLINOFF(pipe, plane_id), linear_offset);
 468
 469         I915_WRITE_FW(SPCONSTALPHA(pipe, plane_id), 0);
 470
 471         I915_WRITE_FW(SPSIZE(pipe, plane_id), (crtc_h << 16) | crtc_w);
 472         I915_WRITE_FW(SPCNTR(pipe, plane_id), sprctl);
 473         I915_WRITE_FW(SPSURF(pipe, plane_id),
 474                       intel_plane_ggtt_offset(plane_state) + sprsurf_offset);
 475         POSTING_READ_FW(SPSURF(pipe, plane_id));
 476
 477         spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
 478 }
 479
 480 static void
 481 vlv_disable_plane(struct intel_plane *plane, struct intel_crtc *crtc)
 482 {
 483         struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
 484         enum pipe pipe = plane->pipe;
 485         enum plane_id plane_id = plane->id;
 486         unsigned long irqflags;
 487
 488         spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
 489
 490         I915_WRITE_FW(SPCNTR(pipe, plane_id), 0);
 491
 492         I915_WRITE_FW(SPSURF(pipe, plane_id), 0);
 493         POSTING_READ_FW(SPSURF(pipe, plane_id));
 494
 495         spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
 496 }
 497
 498 static u32 ivb_sprite_ctl(const struct intel_crtc_state *crtc_state,
 499                           const struct intel_plane_state *plane_state)
 500 {
 501         struct drm_i915_private *dev_priv =
 502                 to_i915(plane_state->base.plane->dev);
 503         const struct drm_framebuffer *fb = plane_state->base.fb;
 504         unsigned int rotation = plane_state->base.rotation;
 505         const struct drm_intel_sprite_colorkey *key = &plane_state->ckey;
 506         u32 sprctl;
 507
 508         sprctl = SPRITE_ENABLE | SPRITE_GAMMA_ENABLE;
 509
 510         if (IS_IVYBRIDGE(dev_priv))
 511                 sprctl |= SPRITE_TRICKLE_FEED_DISABLE;
 512
 513         if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
 514                 sprctl |= SPRITE_PIPE_CSC_ENABLE;
 515
 516         switch (fb->format->format) {
 517         case DRM_FORMAT_XBGR8888:
 518                 sprctl |= SPRITE_FORMAT_RGBX888 | SPRITE_RGB_ORDER_RGBX;
 519                 break;
 520         case DRM_FORMAT_XRGB8888:
 521                 sprctl |= SPRITE_FORMAT_RGBX888;
 522                 break;
 523         case DRM_FORMAT_YUYV:
 524                 sprctl |= SPRITE_FORMAT_YUV422 | SPRITE_YUV_ORDER_YUYV;
 525                 break;
 526         case DRM_FORMAT_YVYU:
 527                 sprctl |= SPRITE_FORMAT_YUV422 | SPRITE_YUV_ORDER_YVYU;
 528                 break;
 529         case DRM_FORMAT_UYVY:
 530                 sprctl |= SPRITE_FORMAT_YUV422 | SPRITE_YUV_ORDER_UYVY;
 531                 break;
 532         case DRM_FORMAT_VYUY:
 533                 sprctl |= SPRITE_FORMAT_YUV422 | SPRITE_YUV_ORDER_VYUY;
 534                 break;
 535         default:
 536                 MISSING_CASE(fb->format->format);
 537                 return 0;
 538         }
 539
 540         if (fb->modifier == I915_FORMAT_MOD_X_TILED)
 541                 sprctl |= SPRITE_TILED;
 542
 543         if (rotation & DRM_MODE_ROTATE_180)
 544                 sprctl |= SPRITE_ROTATE_180;
 545
 546         if (key->flags & I915_SET_COLORKEY_DESTINATION)
 547                 sprctl |= SPRITE_DEST_KEY;
 548         else if (key->flags & I915_SET_COLORKEY_SOURCE)
 549                 sprctl |= SPRITE_SOURCE_KEY;
 550
 551         return sprctl;
 552 }
 553
 554 static void
 555 ivb_update_plane(struct intel_plane *plane,
 556                  const struct intel_crtc_state *crtc_state,
 557                  const struct intel_plane_state *plane_state)
 558 {
 559         struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
 560         const struct drm_framebuffer *fb = plane_state->base.fb;
 561         enum pipe pipe = plane->pipe;
 562         u32 sprctl = plane_state->ctl, sprscale = 0;
 563         u32 sprsurf_offset = plane_state->main.offset;
 564         u32 linear_offset;
 565         const struct drm_intel_sprite_colorkey *key = &plane_state->ckey;
 566         int crtc_x = plane_state->base.dst.x1;
 567         int crtc_y = plane_state->base.dst.y1;
 568         uint32_t crtc_w = drm_rect_width(&plane_state->base.dst);
 569         uint32_t crtc_h = drm_rect_height(&plane_state->base.dst);
 570         uint32_t x = plane_state->main.x;
 571         uint32_t y = plane_state->main.y;
 572         uint32_t src_w = drm_rect_width(&plane_state->base.src) >> 16;
 573         uint32_t src_h = drm_rect_height(&plane_state->base.src) >> 16;
 574         unsigned long irqflags;
 575
 576         /* Sizes are 0 based */
 577         src_w--;
 578         src_h--;
 579         crtc_w--;
 580         crtc_h--;
 581
 582         if (crtc_w != src_w || crtc_h != src_h)
 583                 sprscale = SPRITE_SCALE_ENABLE | (src_w << 16) | src_h;
 584
 585         linear_offset = intel_fb_xy_to_linear(x, y, plane_state, 0);
 586
 587         spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
 588
 589         if (key->flags) {
 590                 I915_WRITE_FW(SPRKEYVAL(pipe), key->min_value);
 591                 I915_WRITE_FW(SPRKEYMAX(pipe), key->max_value);
 592                 I915_WRITE_FW(SPRKEYMSK(pipe), key->channel_mask);
 593         }
 594
 595         I915_WRITE_FW(SPRSTRIDE(pipe), fb->pitches[0]);
 596         I915_WRITE_FW(SPRPOS(pipe), (crtc_y << 16) | crtc_x);
 597
 598         /* HSW consolidates SPRTILEOFF and SPRLINOFF into a single SPROFFSET
 599          * register */
 600         if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
 601                 I915_WRITE_FW(SPROFFSET(pipe), (y << 16) | x);
 602         else if (fb->modifier == I915_FORMAT_MOD_X_TILED)
 603                 I915_WRITE_FW(SPRTILEOFF(pipe), (y << 16) | x);
 604         else
 605                 I915_WRITE_FW(SPRLINOFF(pipe), linear_offset);
 606
 607         I915_WRITE_FW(SPRSIZE(pipe), (crtc_h << 16) | crtc_w);
 608         if (plane->can_scale)
 609                 I915_WRITE_FW(SPRSCALE(pipe), sprscale);
 610         I915_WRITE_FW(SPRCTL(pipe), sprctl);
 611         I915_WRITE_FW(SPRSURF(pipe),
 612                       intel_plane_ggtt_offset(plane_state) + sprsurf_offset);
 613         POSTING_READ_FW(SPRSURF(pipe));
 614
 615         spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
 616 }
 617
 618 static void
 619 ivb_disable_plane(struct intel_plane *plane, struct intel_crtc *crtc)
 620 {
 621         struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
 622         enum pipe pipe = plane->pipe;
 623         unsigned long irqflags;
 624
 625         spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
 626
 627         I915_WRITE_FW(SPRCTL(pipe), 0);
 628         /* Can't leave the scaler enabled... */
 629         if (plane->can_scale)
 630                 I915_WRITE_FW(SPRSCALE(pipe), 0);
 631
 632         I915_WRITE_FW(SPRSURF(pipe), 0);
 633         POSTING_READ_FW(SPRSURF(pipe));
 634
 635         spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
 636 }
 637
 638 static u32 g4x_sprite_ctl(const struct intel_crtc_state *crtc_state,
 639                           const struct intel_plane_state *plane_state)
 640 {
 641         struct drm_i915_private *dev_priv =
 642                 to_i915(plane_state->base.plane->dev);
 643         const struct drm_framebuffer *fb = plane_state->base.fb;
 644         unsigned int rotation = plane_state->base.rotation;
 645         const struct drm_intel_sprite_colorkey *key = &plane_state->ckey;
 646         u32 dvscntr;
 647
 648         dvscntr = DVS_ENABLE | DVS_GAMMA_ENABLE;
 649
 650         if (IS_GEN6(dev_priv))
 651                 dvscntr |= DVS_TRICKLE_FEED_DISABLE;
 652
 653         switch (fb->format->format) {
 654         case DRM_FORMAT_XBGR8888:
 655                 dvscntr |= DVS_FORMAT_RGBX888 | DVS_RGB_ORDER_XBGR;
 656                 break;
 657         case DRM_FORMAT_XRGB8888:
 658                 dvscntr |= DVS_FORMAT_RGBX888;
 659                 break;
 660         case DRM_FORMAT_YUYV:
 661                 dvscntr |= DVS_FORMAT_YUV422 | DVS_YUV_ORDER_YUYV;
 662                 break;
 663         case DRM_FORMAT_YVYU:
 664                 dvscntr |= DVS_FORMAT_YUV422 | DVS_YUV_ORDER_YVYU;
 665                 break;
 666         case DRM_FORMAT_UYVY:
 667                 dvscntr |= DVS_FORMAT_YUV422 | DVS_YUV_ORDER_UYVY;
 668                 break;
 669         case DRM_FORMAT_VYUY:
 670                 dvscntr |= DVS_FORMAT_YUV422 | DVS_YUV_ORDER_VYUY;
 671                 break;
 672         default:
 673                 MISSING_CASE(fb->format->format);
 674                 return 0;
 675         }
 676
 677         if (fb->modifier == I915_FORMAT_MOD_X_TILED)
 678                 dvscntr |= DVS_TILED;
 679
 680         if (rotation & DRM_MODE_ROTATE_180)
 681                 dvscntr |= DVS_ROTATE_180;
 682
 683         if (key->flags & I915_SET_COLORKEY_DESTINATION)
 684                 dvscntr |= DVS_DEST_KEY;
 685         else if (key->flags & I915_SET_COLORKEY_SOURCE)
 686                 dvscntr |= DVS_SOURCE_KEY;
 687
 688         return dvscntr;
 689 }
 690
 691 static void
 692 g4x_update_plane(struct intel_plane *plane,
 693                  const struct intel_crtc_state *crtc_state,
 694                  const struct intel_plane_state *plane_state)
 695 {
 696         struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
 697         const struct drm_framebuffer *fb = plane_state->base.fb;
 698         enum pipe pipe = plane->pipe;
 699         u32 dvscntr = plane_state->ctl, dvsscale = 0;
 700         u32 dvssurf_offset = plane_state->main.offset;
 701         u32 linear_offset;
 702         const struct drm_intel_sprite_colorkey *key = &plane_state->ckey;
 703         int crtc_x = plane_state->base.dst.x1;
 704         int crtc_y = plane_state->base.dst.y1;
 705         uint32_t crtc_w = drm_rect_width(&plane_state->base.dst);
 706         uint32_t crtc_h = drm_rect_height(&plane_state->base.dst);
 707         uint32_t x = plane_state->main.x;
 708         uint32_t y = plane_state->main.y;
 709         uint32_t src_w = drm_rect_width(&plane_state->base.src) >> 16;
 710         uint32_t src_h = drm_rect_height(&plane_state->base.src) >> 16;
 711         unsigned long irqflags;
 712
 713         /* Sizes are 0 based */
 714         src_w--;
 715         src_h--;
 716         crtc_w--;
 717         crtc_h--;
 718
 719         if (crtc_w != src_w || crtc_h != src_h)
 720                 dvsscale = DVS_SCALE_ENABLE | (src_w << 16) | src_h;
 721
 722         linear_offset = intel_fb_xy_to_linear(x, y, plane_state, 0);
 723
 724         spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
 725
 726         if (key->flags) {
 727                 I915_WRITE_FW(DVSKEYVAL(pipe), key->min_value);
 728                 I915_WRITE_FW(DVSKEYMAX(pipe), key->max_value);
 729                 I915_WRITE_FW(DVSKEYMSK(pipe), key->channel_mask);
 730         }
 731
 732         I915_WRITE_FW(DVSSTRIDE(pipe), fb->pitches[0]);
 733         I915_WRITE_FW(DVSPOS(pipe), (crtc_y << 16) | crtc_x);
 734
 735         if (fb->modifier == I915_FORMAT_MOD_X_TILED)
 736                 I915_WRITE_FW(DVSTILEOFF(pipe), (y << 16) | x);
 737         else
 738                 I915_WRITE_FW(DVSLINOFF(pipe), linear_offset);
 739
 740         I915_WRITE_FW(DVSSIZE(pipe), (crtc_h << 16) | crtc_w);
 741         I915_WRITE_FW(DVSSCALE(pipe), dvsscale);
 742         I915_WRITE_FW(DVSCNTR(pipe), dvscntr);
 743         I915_WRITE_FW(DVSSURF(pipe),
 744                       intel_plane_ggtt_offset(plane_state) + dvssurf_offset);
 745         POSTING_READ_FW(DVSSURF(pipe));
 746
 747         spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
 748 }
 749
 750 static void
 751 g4x_disable_plane(struct intel_plane *plane, struct intel_crtc *crtc)
 752 {
 753         struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
 754         enum pipe pipe = plane->pipe;
 755         unsigned long irqflags;
 756
 757         spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
 758
 759         I915_WRITE_FW(DVSCNTR(pipe), 0);
 760         /* Disable the scaler */
 761         I915_WRITE_FW(DVSSCALE(pipe), 0);
 762
 763         I915_WRITE_FW(DVSSURF(pipe), 0);
 764         POSTING_READ_FW(DVSSURF(pipe));
 765
 766         spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
 767 }
 768
 769 static int
 770 intel_check_sprite_plane(struct intel_plane *plane,
 771                          struct intel_crtc_state *crtc_state,
 772                          struct intel_plane_state *state)
 773 {
 774         struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
 775         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
 776         struct drm_framebuffer *fb = state->base.fb;
 777         int crtc_x, crtc_y;
 778         unsigned int crtc_w, crtc_h;
 779         uint32_t src_x, src_y, src_w, src_h;
 780         struct drm_rect *src = &state->base.src;
 781         struct drm_rect *dst = &state->base.dst;
 782         const struct drm_rect *clip = &state->clip;
 783         int hscale, vscale;
 784         int max_scale, min_scale;
 785         bool can_scale;
 786         int ret;
 787
 788         *src = drm_plane_state_src(&state->base);
 789         *dst = drm_plane_state_dest(&state->base);
 790
 791         if (!fb) {
 792                 state->base.visible = false;
 793                 return 0;
 794         }
 795
 796         /* Don't modify another pipe's plane */
 797         if (plane->pipe != crtc->pipe) {
 798                 DRM_DEBUG_KMS("Wrong plane <-> crtc mapping\n");
 799                 return -EINVAL;
 800         }
 801
 802         /* FIXME check all gen limits */
 803         if (fb->width < 3 || fb->height < 3 || fb->pitches[0] > 16384) {
 804                 DRM_DEBUG_KMS("Unsuitable framebuffer for plane\n");
 805                 return -EINVAL;
 806         }
 807
 808         /* setup can_scale, min_scale, max_scale */
 809         if (INTEL_GEN(dev_priv) >= 9) {
 810                 /* use scaler when colorkey is not required */
 811                 if (state->ckey.flags == I915_SET_COLORKEY_NONE) {
 812                         can_scale = 1;
 813                         min_scale = 1;
 814                         max_scale = skl_max_scale(crtc, crtc_state);
 815                 } else {
 816                         can_scale = 0;
 817                         min_scale = DRM_PLANE_HELPER_NO_SCALING;
 818                         max_scale = DRM_PLANE_HELPER_NO_SCALING;
 819                 }
 820         } else {
 821                 can_scale = plane->can_scale;
 822                 max_scale = plane->max_downscale << 16;
 823                 min_scale = plane->can_scale ? 1 : (1 << 16);
 824         }
 825
 826         /*
 827          * FIXME the following code does a bunch of fuzzy adjustments to the
 828          * coordinates and sizes. We probably need some way to decide whether
 829          * more strict checking should be done instead.
 830          */
 831         drm_rect_rotate(src, fb->width << 16, fb->height << 16,
 832                         state->base.rotation);
 833
 834         hscale = drm_rect_calc_hscale_relaxed(src, dst, min_scale, max_scale);
 835         BUG_ON(hscale < 0);
 836
 837         vscale = drm_rect_calc_vscale_relaxed(src, dst, min_scale, max_scale);
 838         BUG_ON(vscale < 0);
 839
 840         state->base.visible = drm_rect_clip_scaled(src, dst, clip, hscale, vscale);
 841
 842         crtc_x = dst->x1;
 843         crtc_y = dst->y1;
 844         crtc_w = drm_rect_width(dst);
 845         crtc_h = drm_rect_height(dst);
 846
 847         if (state->base.visible) {
 848                 /* check again in case clipping clamped the results */
 849                 hscale = drm_rect_calc_hscale(src, dst, min_scale, max_scale);
 850                 if (hscale < 0) {
 851                         DRM_DEBUG_KMS("Horizontal scaling factor out of limits\n");
 852                         drm_rect_debug_print("src: ", src, true);
 853                         drm_rect_debug_print("dst: ", dst, false);
 854
 855                         return hscale;
 856                 }
 857
 858                 vscale = drm_rect_calc_vscale(src, dst, min_scale, max_scale);
 859                 if (vscale < 0) {
 860                         DRM_DEBUG_KMS("Vertical scaling factor out of limits\n");
 861                         drm_rect_debug_print("src: ", src, true);
 862                         drm_rect_debug_print("dst: ", dst, false);
 863
 864                         return vscale;
 865                 }
 866
 867                 /* Make the source viewport size an exact multiple of the scaling factors. */
 868                 drm_rect_adjust_size(src,
 869                                      drm_rect_width(dst) * hscale - drm_rect_width(src),
 870                                      drm_rect_height(dst) * vscale - drm_rect_height(src));
 871
 872                 drm_rect_rotate_inv(src, fb->width << 16, fb->height << 16,
 873                                     state->base.rotation);
 874
 875                 /* sanity check to make sure the src viewport wasn't enlarged */
 876                 WARN_ON(src->x1 < (int) state->base.src_x ||
 877                         src->y1 < (int) state->base.src_y ||
 878                         src->x2 > (int) state->base.src_x + state->base.src_w ||
 879                         src->y2 > (int) state->base.src_y + state->base.src_h);
 880
 881                 /*
 882                  * Hardware doesn't handle subpixel coordinates.
 883                  * Adjust to (macro)pixel boundary, but be careful not to
 884                  * increase the source viewport size, because that could
 885                  * push the downscaling factor out of bounds.
 886                  */
 887                 src_x = src->x1 >> 16;
 888                 src_w = drm_rect_width(src) >> 16;
 889                 src_y = src->y1 >> 16;
 890                 src_h = drm_rect_height(src) >> 16;
 891
 892                 if (format_is_yuv(fb->format->format)) {
 893                         src_x &= ~1;
 894                         src_w &= ~1;
 895
 896                         /*
 897                          * Must keep src and dst the
 898                          * same if we can't scale.
 899                          */
 900                         if (!can_scale)
 901                                 crtc_w &= ~1;
 902
 903                         if (crtc_w == 0)
 904                                 state->base.visible = false;
 905                 }
 906         }
 907
 908         /* Check size restrictions when scaling */
 909         if (state->base.visible && (src_w != crtc_w || src_h != crtc_h)) {
 910                 unsigned int width_bytes;
 911                 int cpp = fb->format->cpp[0];
 912
 913                 WARN_ON(!can_scale);
 914
 915                 /* FIXME interlacing min height is 6 */
 916
 917                 if (crtc_w < 3 || crtc_h < 3)
 918                         state->base.visible = false;
 919
 920                 if (src_w < 3 || src_h < 3)
 921                         state->base.visible = false;
 922
 923                 width_bytes = ((src_x * cpp) & 63) + src_w * cpp;
 924
 925                 if (INTEL_GEN(dev_priv) < 9 && (src_w > 2048 || src_h > 2048 ||
 926                     width_bytes > 4096 || fb->pitches[0] > 4096)) {
 927                         DRM_DEBUG_KMS("Source dimensions exceed hardware limits\n");
 928                         return -EINVAL;
 929                 }
 930         }
 931
 932         if (state->base.visible) {
 933                 src->x1 = src_x << 16;
 934                 src->x2 = (src_x + src_w) << 16;
 935                 src->y1 = src_y << 16;
 936                 src->y2 = (src_y + src_h) << 16;
 937         }
 938
 939         dst->x1 = crtc_x;
 940         dst->x2 = crtc_x + crtc_w;
 941         dst->y1 = crtc_y;
 942         dst->y2 = crtc_y + crtc_h;
 943
 944         if (INTEL_GEN(dev_priv) >= 9) {
 945                 ret = skl_check_plane_surface(state);
 946                 if (ret)
 947                         return ret;
 948
 949                 state->ctl = skl_plane_ctl(crtc_state, state);
 950         } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
 951                 ret = i9xx_check_plane_surface(state);
 952                 if (ret)
 953                         return ret;
 954
 955                 state->ctl = vlv_sprite_ctl(crtc_state, state);
 956         } else if (INTEL_GEN(dev_priv) >= 7) {
 957                 ret = i9xx_check_plane_surface(state);
 958                 if (ret)
 959                         return ret;
 960
 961                 state->ctl = ivb_sprite_ctl(crtc_state, state);
 962         } else {
 963                 ret = i9xx_check_plane_surface(state);
 964                 if (ret)
 965                         return ret;
 966
 967                 state->ctl = g4x_sprite_ctl(crtc_state, state);
 968         }
 969
 970         return 0;
 971 }
 972
 973 int intel_sprite_set_colorkey(struct drm_device *dev, void *data,
 974                               struct drm_file *file_priv)
 975 {
 976         struct drm_i915_private *dev_priv = to_i915(dev);
 977         struct drm_intel_sprite_colorkey *set = data;
 978         struct drm_plane *plane;
 979         struct drm_plane_state *plane_state;
 980         struct drm_atomic_state *state;
 981         struct drm_modeset_acquire_ctx ctx;
 982         int ret = 0;
 983
 984         /* Make sure we don't try to enable both src & dest simultaneously */
 985         if ((set->flags & (I915_SET_COLORKEY_DESTINATION | I915_SET_COLORKEY_SOURCE)) == (I915_SET_COLORKEY_DESTINATION | I915_SET_COLORKEY_SOURCE))
 986                 return -EINVAL;
 987
 988         if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) &&
 989             set->flags & I915_SET_COLORKEY_DESTINATION)
 990                 return -EINVAL;
 991
 992         plane = drm_plane_find(dev, set->plane_id);
 993         if (!plane || plane->type != DRM_PLANE_TYPE_OVERLAY)
 994                 return -ENOENT;
 995
 996         drm_modeset_acquire_init(&ctx, 0);
 997
 998         state = drm_atomic_state_alloc(plane->dev);
 999         if (!state) {
1000                 ret = -ENOMEM;
1001                 goto out;
1002         }
1003         state->acquire_ctx = &ctx;
1004
1005         while (1) {
1006                 plane_state = drm_atomic_get_plane_state(state, plane);
1007                 ret = PTR_ERR_OR_ZERO(plane_state);
1008                 if (!ret) {
1009                         to_intel_plane_state(plane_state)->ckey = *set;
1010                         ret = drm_atomic_commit(state);
1011                 }
1012
1013                 if (ret != -EDEADLK)
1014                         break;
1015
1016                 drm_atomic_state_clear(state);
1017                 drm_modeset_backoff(&ctx);
1018         }
1019
1020         drm_atomic_state_put(state);
1021 out:
1022         drm_modeset_drop_locks(&ctx);
1023         drm_modeset_acquire_fini(&ctx);
1024         return ret;
1025 }
1026
1027 static const uint32_t g4x_plane_formats[] = {
1028         DRM_FORMAT_XRGB8888,
1029         DRM_FORMAT_YUYV,
1030         DRM_FORMAT_YVYU,
1031         DRM_FORMAT_UYVY,
1032         DRM_FORMAT_VYUY,
1033 };
1034
1035 static const uint32_t snb_plane_formats[] = {
1036         DRM_FORMAT_XBGR8888,
1037         DRM_FORMAT_XRGB8888,
1038         DRM_FORMAT_YUYV,
1039         DRM_FORMAT_YVYU,
1040         DRM_FORMAT_UYVY,
1041         DRM_FORMAT_VYUY,
1042 };
1043
1044 static const uint32_t vlv_plane_formats[] = {
1045         DRM_FORMAT_RGB565,
1046         DRM_FORMAT_ABGR8888,
1047         DRM_FORMAT_ARGB8888,
1048         DRM_FORMAT_XBGR8888,
1049         DRM_FORMAT_XRGB8888,
1050         DRM_FORMAT_XBGR2101010,
1051         DRM_FORMAT_ABGR2101010,
1052         DRM_FORMAT_YUYV,
1053         DRM_FORMAT_YVYU,
1054         DRM_FORMAT_UYVY,
1055         DRM_FORMAT_VYUY,
1056 };
1057
1058 static uint32_t skl_plane_formats[] = {
1059         DRM_FORMAT_RGB565,
1060         DRM_FORMAT_ABGR8888,
1061         DRM_FORMAT_ARGB8888,
1062         DRM_FORMAT_XBGR8888,
1063         DRM_FORMAT_XRGB8888,
1064         DRM_FORMAT_YUYV,
1065         DRM_FORMAT_YVYU,
1066         DRM_FORMAT_UYVY,
1067         DRM_FORMAT_VYUY,
1068 };
1069
1070 struct intel_plane *
1071 intel_sprite_plane_create(struct drm_i915_private *dev_priv,
1072                           enum pipe pipe, int plane)
1073 {
1074         struct intel_plane *intel_plane = NULL;
1075         struct intel_plane_state *state = NULL;
1076         unsigned long possible_crtcs;
1077         const uint32_t *plane_formats;
1078         unsigned int supported_rotations;
1079         int num_plane_formats;
1080         int ret;
1081
1082         intel_plane = kzalloc(sizeof(*intel_plane), GFP_KERNEL);
1083         if (!intel_plane) {
1084                 ret = -ENOMEM;
1085                 goto fail;
1086         }
1087
1088         state = intel_create_plane_state(&intel_plane->base);
1089         if (!state) {
1090                 ret = -ENOMEM;
1091                 goto fail;
1092         }
1093         intel_plane->base.state = &state->base;
1094
1095         if (INTEL_GEN(dev_priv) >= 9) {
1096                 intel_plane->can_scale = true;
1097                 state->scaler_id = -1;
1098
1099                 intel_plane->update_plane = skl_update_plane;
1100                 intel_plane->disable_plane = skl_disable_plane;
1101
1102                 plane_formats = skl_plane_formats;
1103                 num_plane_formats = ARRAY_SIZE(skl_plane_formats);
1104         } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
1105                 intel_plane->can_scale = false;
1106                 intel_plane->max_downscale = 1;
1107
1108                 intel_plane->update_plane = vlv_update_plane;
1109                 intel_plane->disable_plane = vlv_disable_plane;
1110
1111                 plane_formats = vlv_plane_formats;
1112                 num_plane_formats = ARRAY_SIZE(vlv_plane_formats);
1113         } else if (INTEL_GEN(dev_priv) >= 7) {
1114                 if (IS_IVYBRIDGE(dev_priv)) {
1115                         intel_plane->can_scale = true;
1116                         intel_plane->max_downscale = 2;
1117                 } else {
1118                         intel_plane->can_scale = false;
1119                         intel_plane->max_downscale = 1;
1120                 }
1121
1122                 intel_plane->update_plane = ivb_update_plane;
1123                 intel_plane->disable_plane = ivb_disable_plane;
1124
1125                 plane_formats = snb_plane_formats;
1126                 num_plane_formats = ARRAY_SIZE(snb_plane_formats);
1127         } else {
1128                 intel_plane->can_scale = true;
1129                 intel_plane->max_downscale = 16;
1130
1131                 intel_plane->update_plane = g4x_update_plane;
1132                 intel_plane->disable_plane = g4x_disable_plane;
1133
1134                 if (IS_GEN6(dev_priv)) {
1135                         plane_formats = snb_plane_formats;
1136                         num_plane_formats = ARRAY_SIZE(snb_plane_formats);
1137                 } else {
1138                         plane_formats = g4x_plane_formats;
1139                         num_plane_formats = ARRAY_SIZE(g4x_plane_formats);
1140                 }
1141         }
1142
1143         if (INTEL_GEN(dev_priv) >= 9) {
1144                 supported_rotations =
1145                         DRM_MODE_ROTATE_0 | DRM_MODE_ROTATE_90 |
1146                         DRM_MODE_ROTATE_180 | DRM_MODE_ROTATE_270;
1147         } else if (IS_CHERRYVIEW(dev_priv) && pipe == PIPE_B) {
1148                 supported_rotations =
1149                         DRM_MODE_ROTATE_0 | DRM_MODE_ROTATE_180 |
1150                         DRM_MODE_REFLECT_X;
1151         } else {
1152                 supported_rotations =
1153                         DRM_MODE_ROTATE_0 | DRM_MODE_ROTATE_180;
1154         }
1155
1156         intel_plane->pipe = pipe;
1157         intel_plane->plane = plane;
1158         intel_plane->id = PLANE_SPRITE0 + plane;
1159         intel_plane->frontbuffer_bit = INTEL_FRONTBUFFER_SPRITE(pipe, plane);
1160         intel_plane->check_plane = intel_check_sprite_plane;
1161
1162         possible_crtcs = (1 << pipe);
1163
1164         if (INTEL_GEN(dev_priv) >= 9)
1165                 ret = drm_universal_plane_init(&dev_priv->drm, &intel_plane->base,
1166                                                possible_crtcs, &intel_plane_funcs,
1167                                                plane_formats, num_plane_formats,
1168                                                NULL, DRM_PLANE_TYPE_OVERLAY,
1169                                                "plane %d%c", plane + 2, pipe_name(pipe));
1170         else
1171                 ret = drm_universal_plane_init(&dev_priv->drm, &intel_plane->base,
1172                                                possible_crtcs, &intel_plane_funcs,
1173                                                plane_formats, num_plane_formats,
1174                                                NULL, DRM_PLANE_TYPE_OVERLAY,
1175                                                "sprite %c", sprite_name(pipe, plane));
1176         if (ret)
1177                 goto fail;
1178
1179         drm_plane_create_rotation_property(&intel_plane->base,
1180                                            DRM_MODE_ROTATE_0,
1181                                            supported_rotations);
1182
1183         drm_plane_helper_add(&intel_plane->base, &intel_plane_helper_funcs);
1184
1185         return intel_plane;
1186
1187 fail:
1188         kfree(state);
1189         kfree(intel_plane);
1190
1191         return ERR_PTR(ret);
1192 }