drivers/spi/spi-imx.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 // Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved.
   3 // Copyright (C) 2008 Juergen Beisert
   4
   5 #include <linux/bits.h>
   6 #include <linux/clk.h>
   7 #include <linux/completion.h>
   8 #include <linux/delay.h>
   9 #include <linux/dmaengine.h>
  10 #include <linux/dma-mapping.h>
  11 #include <linux/err.h>
  12 #include <linux/interrupt.h>
  13 #include <linux/io.h>
  14 #include <linux/irq.h>
  15 #include <linux/kernel.h>
  16 #include <linux/module.h>
  17 #include <linux/pinctrl/consumer.h>
  18 #include <linux/platform_device.h>
  19 #include <linux/pm_runtime.h>
  20 #include <linux/slab.h>
  21 #include <linux/spi/spi.h>
  22 #include <linux/types.h>
  23 #include <linux/of.h>
  24 #include <linux/property.h>
  25
  26 #include <linux/dma/imx-dma.h>
  27
  28 #define DRIVER_NAME "spi_imx"
  29
  30 static bool use_dma = true;
  31 module_param(use_dma, bool, 0644);
  32 MODULE_PARM_DESC(use_dma, "Enable usage of DMA when available (default)");
  33
  34 /* define polling limits */
  35 static unsigned int polling_limit_us = 30;
  36 module_param(polling_limit_us, uint, 0664);
  37 MODULE_PARM_DESC(polling_limit_us,
  38                  "time in us to run a transfer in polling mode\n");
  39
  40 #define MXC_RPM_TIMEOUT         2000 /* 2000ms */
  41
  42 #define MXC_CSPIRXDATA          0x00
  43 #define MXC_CSPITXDATA          0x04
  44 #define MXC_CSPICTRL            0x08
  45 #define MXC_CSPIINT             0x0c
  46 #define MXC_RESET               0x1c
  47
  48 /* generic defines to abstract from the different register layouts */
  49 #define MXC_INT_RR      (1 << 0) /* Receive data ready interrupt */
  50 #define MXC_INT_TE      (1 << 1) /* Transmit FIFO empty interrupt */
  51 #define MXC_INT_RDR     BIT(4) /* Receive date threshold interrupt */
  52
  53 /* The maximum bytes that a sdma BD can transfer. */
  54 #define MAX_SDMA_BD_BYTES (1 << 15)
  55 #define MX51_ECSPI_CTRL_MAX_BURST       512
  56 /* The maximum bytes that IMX53_ECSPI can transfer in target mode.*/
  57 #define MX53_MAX_TRANSFER_BYTES         512
  58
  59 enum spi_imx_devtype {
  60         IMX1_CSPI,
  61         IMX21_CSPI,
  62         IMX27_CSPI,
  63         IMX31_CSPI,
  64         IMX35_CSPI,     /* CSPI on all i.mx except above */
  65         IMX51_ECSPI,    /* ECSPI on i.mx51 */
  66         IMX53_ECSPI,    /* ECSPI on i.mx53 and later */
  67 };
  68
  69 struct spi_imx_data;
  70
  71 struct spi_imx_devtype_data {
  72         void (*intctrl)(struct spi_imx_data *spi_imx, int enable);
  73         int (*prepare_message)(struct spi_imx_data *spi_imx, struct spi_message *msg);
  74         int (*prepare_transfer)(struct spi_imx_data *spi_imx, struct spi_device *spi);
  75         void (*trigger)(struct spi_imx_data *spi_imx);
  76         int (*rx_available)(struct spi_imx_data *spi_imx);
  77         void (*reset)(struct spi_imx_data *spi_imx);
  78         void (*setup_wml)(struct spi_imx_data *spi_imx);
  79         void (*disable)(struct spi_imx_data *spi_imx);
  80         bool has_dmamode;
  81         bool has_targetmode;
  82         unsigned int fifo_size;
  83         bool dynamic_burst;
  84         /*
  85          * ERR009165 fixed or not:
  86          * https://www.nxp.com/docs/en/errata/IMX6DQCE.pdf
  87          */
  88         bool tx_glitch_fixed;
  89         enum spi_imx_devtype devtype;
  90 };
  91
  92 struct spi_imx_data {
  93         struct spi_controller *controller;
  94         struct device *dev;
  95
  96         struct completion xfer_done;
  97         void __iomem *base;
  98         unsigned long base_phys;
  99
 100         struct clk *clk_per;
 101         struct clk *clk_ipg;
 102         unsigned long spi_clk;
 103         unsigned int spi_bus_clk;
 104
 105         unsigned int bits_per_word;
 106         unsigned int spi_drctl;
 107
 108         unsigned int count, remainder;
 109         void (*tx)(struct spi_imx_data *spi_imx);
 110         void (*rx)(struct spi_imx_data *spi_imx);
 111         void *rx_buf;
 112         const void *tx_buf;
 113         unsigned int txfifo; /* number of words pushed in tx FIFO */
 114         unsigned int dynamic_burst;
 115         bool rx_only;
 116
 117         /* Target mode */
 118         bool target_mode;
 119         bool target_aborted;
 120         unsigned int target_burst;
 121
 122         /* DMA */
 123         bool usedma;
 124         u32 wml;
 125         struct completion dma_rx_completion;
 126         struct completion dma_tx_completion;
 127
 128         const struct spi_imx_devtype_data *devtype_data;
 129 };
 130
 131 static inline int is_imx27_cspi(struct spi_imx_data *d)
 132 {
 133         return d->devtype_data->devtype == IMX27_CSPI;
 134 }
 135
 136 static inline int is_imx35_cspi(struct spi_imx_data *d)
 137 {
 138         return d->devtype_data->devtype == IMX35_CSPI;
 139 }
 140
 141 static inline int is_imx51_ecspi(struct spi_imx_data *d)
 142 {
 143         return d->devtype_data->devtype == IMX51_ECSPI;
 144 }
 145
 146 static inline int is_imx53_ecspi(struct spi_imx_data *d)
 147 {
 148         return d->devtype_data->devtype == IMX53_ECSPI;
 149 }
 150
 151 #define MXC_SPI_BUF_RX(type)                                            \
 152 static void spi_imx_buf_rx_##type(struct spi_imx_data *spi_imx)         \
 153 {                                                                       \
 154         unsigned int val = readl(spi_imx->base + MXC_CSPIRXDATA);       \
 155                                                                         \
 156         if (spi_imx->rx_buf) {                                          \
 157                 *(type *)spi_imx->rx_buf = val;                         \
 158                 spi_imx->rx_buf += sizeof(type);                        \
 159         }                                                               \
 160                                                                         \
 161         spi_imx->remainder -= sizeof(type);                             \
 162 }
 163
 164 #define MXC_SPI_BUF_TX(type)                                            \
 165 static void spi_imx_buf_tx_##type(struct spi_imx_data *spi_imx)         \
 166 {                                                                       \
 167         type val = 0;                                                   \
 168                                                                         \
 169         if (spi_imx->tx_buf) {                                          \
 170                 val = *(type *)spi_imx->tx_buf;                         \
 171                 spi_imx->tx_buf += sizeof(type);                        \
 172         }                                                               \
 173                                                                         \
 174         spi_imx->count -= sizeof(type);                                 \
 175                                                                         \
 176         writel(val, spi_imx->base + MXC_CSPITXDATA);                    \
 177 }
 178
 179 MXC_SPI_BUF_RX(u8)
 180 MXC_SPI_BUF_TX(u8)
 181 MXC_SPI_BUF_RX(u16)
 182 MXC_SPI_BUF_TX(u16)
 183 MXC_SPI_BUF_RX(u32)
 184 MXC_SPI_BUF_TX(u32)
 185
 186 /* First entry is reserved, second entry is valid only if SDHC_SPIEN is set
 187  * (which is currently not the case in this driver)
 188  */
 189 static int mxc_clkdivs[] = {0, 3, 4, 6, 8, 12, 16, 24, 32, 48, 64, 96, 128, 192,
 190         256, 384, 512, 768, 1024};
 191
 192 /* MX21, MX27 */
 193 static unsigned int spi_imx_clkdiv_1(unsigned int fin,
 194                 unsigned int fspi, unsigned int max, unsigned int *fres)
 195 {
 196         int i;
 197
 198         for (i = 2; i < max; i++)
 199                 if (fspi * mxc_clkdivs[i] >= fin)
 200                         break;
 201
 202         *fres = fin / mxc_clkdivs[i];
 203         return i;
 204 }
 205
 206 /* MX1, MX31, MX35, MX51 CSPI */
 207 static unsigned int spi_imx_clkdiv_2(unsigned int fin,
 208                 unsigned int fspi, unsigned int *fres)
 209 {
 210         int i, div = 4;
 211
 212         for (i = 0; i < 7; i++) {
 213                 if (fspi * div >= fin)
 214                         goto out;
 215                 div <<= 1;
 216         }
 217
 218 out:
 219         *fres = fin / div;
 220         return i;
 221 }
 222
 223 static int spi_imx_bytes_per_word(const int bits_per_word)
 224 {
 225         if (bits_per_word <= 8)
 226                 return 1;
 227         else if (bits_per_word <= 16)
 228                 return 2;
 229         else
 230                 return 4;
 231 }
 232
 233 static bool spi_imx_can_dma(struct spi_controller *controller, struct spi_device *spi,
 234                          struct spi_transfer *transfer)
 235 {
 236         struct spi_imx_data *spi_imx = spi_controller_get_devdata(controller);
 237
 238         if (!use_dma || controller->fallback)
 239                 return false;
 240
 241         if (!controller->dma_rx)
 242                 return false;
 243
 244         if (spi_imx->target_mode)
 245                 return false;
 246
 247         if (transfer->len < spi_imx->devtype_data->fifo_size)
 248                 return false;
 249
 250         spi_imx->dynamic_burst = 0;
 251
 252         return true;
 253 }
 254
 255 /*
 256  * Note the number of natively supported chip selects for MX51 is 4. Some
 257  * devices may have less actual SS pins but the register map supports 4. When
 258  * using gpio chip selects the cs values passed into the macros below can go
 259  * outside the range 0 - 3. We therefore need to limit the cs value to avoid
 260  * corrupting bits outside the allocated locations.
 261  *
 262  * The simplest way to do this is to just mask the cs bits to 2 bits. This
 263  * still allows all 4 native chip selects to work as well as gpio chip selects
 264  * (which can use any of the 4 chip select configurations).
 265  */
 266
 267 #define MX51_ECSPI_CTRL         0x08
 268 #define MX51_ECSPI_CTRL_ENABLE          (1 <<  0)
 269 #define MX51_ECSPI_CTRL_XCH             (1 <<  2)
 270 #define MX51_ECSPI_CTRL_SMC             (1 << 3)
 271 #define MX51_ECSPI_CTRL_MODE_MASK       (0xf << 4)
 272 #define MX51_ECSPI_CTRL_DRCTL(drctl)    ((drctl) << 16)
 273 #define MX51_ECSPI_CTRL_POSTDIV_OFFSET  8
 274 #define MX51_ECSPI_CTRL_PREDIV_OFFSET   12
 275 #define MX51_ECSPI_CTRL_CS(cs)          ((cs & 3) << 18)
 276 #define MX51_ECSPI_CTRL_BL_OFFSET       20
 277 #define MX51_ECSPI_CTRL_BL_MASK         (0xfff << 20)
 278
 279 #define MX51_ECSPI_CONFIG       0x0c
 280 #define MX51_ECSPI_CONFIG_SCLKPHA(cs)   (1 << ((cs & 3) +  0))
 281 #define MX51_ECSPI_CONFIG_SCLKPOL(cs)   (1 << ((cs & 3) +  4))
 282 #define MX51_ECSPI_CONFIG_SBBCTRL(cs)   (1 << ((cs & 3) +  8))
 283 #define MX51_ECSPI_CONFIG_SSBPOL(cs)    (1 << ((cs & 3) + 12))
 284 #define MX51_ECSPI_CONFIG_DATACTL(cs)   (1 << ((cs & 3) + 16))
 285 #define MX51_ECSPI_CONFIG_SCLKCTL(cs)   (1 << ((cs & 3) + 20))
 286
 287 #define MX51_ECSPI_INT          0x10
 288 #define MX51_ECSPI_INT_TEEN             (1 <<  0)
 289 #define MX51_ECSPI_INT_RREN             (1 <<  3)
 290 #define MX51_ECSPI_INT_RDREN            (1 <<  4)
 291
 292 #define MX51_ECSPI_DMA          0x14
 293 #define MX51_ECSPI_DMA_TX_WML(wml)      ((wml) & 0x3f)
 294 #define MX51_ECSPI_DMA_RX_WML(wml)      (((wml) & 0x3f) << 16)
 295 #define MX51_ECSPI_DMA_RXT_WML(wml)     (((wml) & 0x3f) << 24)
 296
 297 #define MX51_ECSPI_DMA_TEDEN            (1 << 7)
 298 #define MX51_ECSPI_DMA_RXDEN            (1 << 23)
 299 #define MX51_ECSPI_DMA_RXTDEN           (1 << 31)
 300
 301 #define MX51_ECSPI_STAT         0x18
 302 #define MX51_ECSPI_STAT_RR              (1 <<  3)
 303
 304 #define MX51_ECSPI_TESTREG      0x20
 305 #define MX51_ECSPI_TESTREG_LBC  BIT(31)
 306
 307 static void spi_imx_buf_rx_swap_u32(struct spi_imx_data *spi_imx)
 308 {
 309         unsigned int val = readl(spi_imx->base + MXC_CSPIRXDATA);
 310
 311         if (spi_imx->rx_buf) {
 312 #ifdef __LITTLE_ENDIAN
 313                 unsigned int bytes_per_word;
 314
 315                 bytes_per_word = spi_imx_bytes_per_word(spi_imx->bits_per_word);
 316                 if (bytes_per_word == 1)
 317                         swab32s(&val);
 318                 else if (bytes_per_word == 2)
 319                         swahw32s(&val);
 320 #endif
 321                 *(u32 *)spi_imx->rx_buf = val;
 322                 spi_imx->rx_buf += sizeof(u32);
 323         }
 324
 325         spi_imx->remainder -= sizeof(u32);
 326 }
 327
 328 static void spi_imx_buf_rx_swap(struct spi_imx_data *spi_imx)
 329 {
 330         int unaligned;
 331         u32 val;
 332
 333         unaligned = spi_imx->remainder % 4;
 334
 335         if (!unaligned) {
 336                 spi_imx_buf_rx_swap_u32(spi_imx);
 337                 return;
 338         }
 339
 340         if (spi_imx_bytes_per_word(spi_imx->bits_per_word) == 2) {
 341                 spi_imx_buf_rx_u16(spi_imx);
 342                 return;
 343         }
 344
 345         val = readl(spi_imx->base + MXC_CSPIRXDATA);
 346
 347         while (unaligned--) {
 348                 if (spi_imx->rx_buf) {
 349                         *(u8 *)spi_imx->rx_buf = (val >> (8 * unaligned)) & 0xff;
 350                         spi_imx->rx_buf++;
 351                 }
 352                 spi_imx->remainder--;
 353         }
 354 }
 355
 356 static void spi_imx_buf_tx_swap_u32(struct spi_imx_data *spi_imx)
 357 {
 358         u32 val = 0;
 359 #ifdef __LITTLE_ENDIAN
 360         unsigned int bytes_per_word;
 361 #endif
 362
 363         if (spi_imx->tx_buf) {
 364                 val = *(u32 *)spi_imx->tx_buf;
 365                 spi_imx->tx_buf += sizeof(u32);
 366         }
 367
 368         spi_imx->count -= sizeof(u32);
 369 #ifdef __LITTLE_ENDIAN
 370         bytes_per_word = spi_imx_bytes_per_word(spi_imx->bits_per_word);
 371
 372         if (bytes_per_word == 1)
 373                 swab32s(&val);
 374         else if (bytes_per_word == 2)
 375                 swahw32s(&val);
 376 #endif
 377         writel(val, spi_imx->base + MXC_CSPITXDATA);
 378 }
 379
 380 static void spi_imx_buf_tx_swap(struct spi_imx_data *spi_imx)
 381 {
 382         int unaligned;
 383         u32 val = 0;
 384
 385         unaligned = spi_imx->count % 4;
 386
 387         if (!unaligned) {
 388                 spi_imx_buf_tx_swap_u32(spi_imx);
 389                 return;
 390         }
 391
 392         if (spi_imx_bytes_per_word(spi_imx->bits_per_word) == 2) {
 393                 spi_imx_buf_tx_u16(spi_imx);
 394                 return;
 395         }
 396
 397         while (unaligned--) {
 398                 if (spi_imx->tx_buf) {
 399                         val |= *(u8 *)spi_imx->tx_buf << (8 * unaligned);
 400                         spi_imx->tx_buf++;
 401                 }
 402                 spi_imx->count--;
 403         }
 404
 405         writel(val, spi_imx->base + MXC_CSPITXDATA);
 406 }
 407
 408 static void mx53_ecspi_rx_target(struct spi_imx_data *spi_imx)
 409 {
 410         u32 val = be32_to_cpu(readl(spi_imx->base + MXC_CSPIRXDATA));
 411
 412         if (spi_imx->rx_buf) {
 413                 int n_bytes = spi_imx->target_burst % sizeof(val);
 414
 415                 if (!n_bytes)
 416                         n_bytes = sizeof(val);
 417
 418                 memcpy(spi_imx->rx_buf,
 419                        ((u8 *)&val) + sizeof(val) - n_bytes, n_bytes);
 420
 421                 spi_imx->rx_buf += n_bytes;
 422                 spi_imx->target_burst -= n_bytes;
 423         }
 424
 425         spi_imx->remainder -= sizeof(u32);
 426 }
 427
 428 static void mx53_ecspi_tx_target(struct spi_imx_data *spi_imx)
 429 {
 430         u32 val = 0;
 431         int n_bytes = spi_imx->count % sizeof(val);
 432
 433         if (!n_bytes)
 434                 n_bytes = sizeof(val);
 435
 436         if (spi_imx->tx_buf) {
 437                 memcpy(((u8 *)&val) + sizeof(val) - n_bytes,
 438                        spi_imx->tx_buf, n_bytes);
 439                 val = cpu_to_be32(val);
 440                 spi_imx->tx_buf += n_bytes;
 441         }
 442
 443         spi_imx->count -= n_bytes;
 444
 445         writel(val, spi_imx->base + MXC_CSPITXDATA);
 446 }
 447
 448 /* MX51 eCSPI */
 449 static unsigned int mx51_ecspi_clkdiv(struct spi_imx_data *spi_imx,
 450                                       unsigned int fspi, unsigned int *fres)
 451 {
 452         /*
 453          * there are two 4-bit dividers, the pre-divider divides by
 454          * $pre, the post-divider by 2^$post
 455          */
 456         unsigned int pre, post;
 457         unsigned int fin = spi_imx->spi_clk;
 458
 459         fspi = min(fspi, fin);
 460
 461         post = fls(fin) - fls(fspi);
 462         if (fin > fspi << post)
 463                 post++;
 464
 465         /* now we have: (fin <= fspi << post) with post being minimal */
 466
 467         post = max(4U, post) - 4;
 468         if (unlikely(post > 0xf)) {
 469                 dev_err(spi_imx->dev, "cannot set clock freq: %u (base freq: %u)\n",
 470                                 fspi, fin);
 471                 return 0xff;
 472         }
 473
 474         pre = DIV_ROUND_UP(fin, fspi << post) - 1;
 475
 476         dev_dbg(spi_imx->dev, "%s: fin: %u, fspi: %u, post: %u, pre: %u\n",
 477                         __func__, fin, fspi, post, pre);
 478
 479         /* Resulting frequency for the SCLK line. */
 480         *fres = (fin / (pre + 1)) >> post;
 481
 482         return (pre << MX51_ECSPI_CTRL_PREDIV_OFFSET) |
 483                 (post << MX51_ECSPI_CTRL_POSTDIV_OFFSET);
 484 }
 485
 486 static void mx51_ecspi_intctrl(struct spi_imx_data *spi_imx, int enable)
 487 {
 488         unsigned int val = 0;
 489
 490         if (enable & MXC_INT_TE)
 491                 val |= MX51_ECSPI_INT_TEEN;
 492
 493         if (enable & MXC_INT_RR)
 494                 val |= MX51_ECSPI_INT_RREN;
 495
 496         if (enable & MXC_INT_RDR)
 497                 val |= MX51_ECSPI_INT_RDREN;
 498
 499         writel(val, spi_imx->base + MX51_ECSPI_INT);
 500 }
 501
 502 static void mx51_ecspi_trigger(struct spi_imx_data *spi_imx)
 503 {
 504         u32 reg;
 505
 506         reg = readl(spi_imx->base + MX51_ECSPI_CTRL);
 507         reg |= MX51_ECSPI_CTRL_XCH;
 508         writel(reg, spi_imx->base + MX51_ECSPI_CTRL);
 509 }
 510
 511 static void mx51_ecspi_disable(struct spi_imx_data *spi_imx)
 512 {
 513         u32 ctrl;
 514
 515         ctrl = readl(spi_imx->base + MX51_ECSPI_CTRL);
 516         ctrl &= ~MX51_ECSPI_CTRL_ENABLE;
 517         writel(ctrl, spi_imx->base + MX51_ECSPI_CTRL);
 518 }
 519
 520 static int mx51_ecspi_channel(const struct spi_device *spi)
 521 {
 522         if (!spi_get_csgpiod(spi, 0))
 523                 return spi_get_chipselect(spi, 0);
 524         return spi->controller->unused_native_cs;
 525 }
 526
 527 static int mx51_ecspi_prepare_message(struct spi_imx_data *spi_imx,
 528                                       struct spi_message *msg)
 529 {
 530         struct spi_device *spi = msg->spi;
 531         struct spi_transfer *xfer;
 532         u32 ctrl = MX51_ECSPI_CTRL_ENABLE;
 533         u32 min_speed_hz = ~0U;
 534         u32 testreg, delay;
 535         u32 cfg = readl(spi_imx->base + MX51_ECSPI_CONFIG);
 536         u32 current_cfg = cfg;
 537         int channel = mx51_ecspi_channel(spi);
 538
 539         /* set Host or Target mode */
 540         if (spi_imx->target_mode)
 541                 ctrl &= ~MX51_ECSPI_CTRL_MODE_MASK;
 542         else
 543                 ctrl |= MX51_ECSPI_CTRL_MODE_MASK;
 544
 545         /*
 546          * Enable SPI_RDY handling (falling edge/level triggered).
 547          */
 548         if (spi->mode & SPI_READY)
 549                 ctrl |= MX51_ECSPI_CTRL_DRCTL(spi_imx->spi_drctl);
 550
 551         /* set chip select to use */
 552         ctrl |= MX51_ECSPI_CTRL_CS(channel);
 553
 554         /*
 555          * The ctrl register must be written first, with the EN bit set other
 556          * registers must not be written to.
 557          */
 558         writel(ctrl, spi_imx->base + MX51_ECSPI_CTRL);
 559
 560         testreg = readl(spi_imx->base + MX51_ECSPI_TESTREG);
 561         if (spi->mode & SPI_LOOP)
 562                 testreg |= MX51_ECSPI_TESTREG_LBC;
 563         else
 564                 testreg &= ~MX51_ECSPI_TESTREG_LBC;
 565         writel(testreg, spi_imx->base + MX51_ECSPI_TESTREG);
 566
 567         /*
 568          * eCSPI burst completion by Chip Select signal in Target mode
 569          * is not functional for imx53 Soc, config SPI burst completed when
 570          * BURST_LENGTH + 1 bits are received
 571          */
 572         if (spi_imx->target_mode && is_imx53_ecspi(spi_imx))
 573                 cfg &= ~MX51_ECSPI_CONFIG_SBBCTRL(channel);
 574         else
 575                 cfg |= MX51_ECSPI_CONFIG_SBBCTRL(channel);
 576
 577         if (spi->mode & SPI_CPOL) {
 578                 cfg |= MX51_ECSPI_CONFIG_SCLKPOL(channel);
 579                 cfg |= MX51_ECSPI_CONFIG_SCLKCTL(channel);
 580         } else {
 581                 cfg &= ~MX51_ECSPI_CONFIG_SCLKPOL(channel);
 582                 cfg &= ~MX51_ECSPI_CONFIG_SCLKCTL(channel);
 583         }
 584
 585         if (spi->mode & SPI_MOSI_IDLE_LOW)
 586                 cfg |= MX51_ECSPI_CONFIG_DATACTL(channel);
 587         else
 588                 cfg &= ~MX51_ECSPI_CONFIG_DATACTL(channel);
 589
 590         if (spi->mode & SPI_CS_HIGH)
 591                 cfg |= MX51_ECSPI_CONFIG_SSBPOL(channel);
 592         else
 593                 cfg &= ~MX51_ECSPI_CONFIG_SSBPOL(channel);
 594
 595         if (cfg == current_cfg)
 596                 return 0;
 597
 598         writel(cfg, spi_imx->base + MX51_ECSPI_CONFIG);
 599
 600         /*
 601          * Wait until the changes in the configuration register CONFIGREG
 602          * propagate into the hardware. It takes exactly one tick of the
 603          * SCLK clock, but we will wait two SCLK clock just to be sure. The
 604          * effect of the delay it takes for the hardware to apply changes
 605          * is noticable if the SCLK clock run very slow. In such a case, if
 606          * the polarity of SCLK should be inverted, the GPIO ChipSelect might
 607          * be asserted before the SCLK polarity changes, which would disrupt
 608          * the SPI communication as the device on the other end would consider
 609          * the change of SCLK polarity as a clock tick already.
 610          *
 611          * Because spi_imx->spi_bus_clk is only set in prepare_message
 612          * callback, iterate over all the transfers in spi_message, find the
 613          * one with lowest bus frequency, and use that bus frequency for the
 614          * delay calculation. In case all transfers have speed_hz == 0, then
 615          * min_speed_hz is ~0 and the resulting delay is zero.
 616          */
 617         list_for_each_entry(xfer, &msg->transfers, transfer_list) {
 618                 if (!xfer->speed_hz)
 619                         continue;
 620                 min_speed_hz = min(xfer->speed_hz, min_speed_hz);
 621         }
 622
 623         delay = (2 * 1000000) / min_speed_hz;
 624         if (likely(delay < 10)) /* SCLK is faster than 200 kHz */
 625                 udelay(delay);
 626         else                    /* SCLK is _very_ slow */
 627                 usleep_range(delay, delay + 10);
 628
 629         return 0;
 630 }
 631
 632 static void mx51_configure_cpha(struct spi_imx_data *spi_imx,
 633                                 struct spi_device *spi)
 634 {
 635         bool cpha = (spi->mode & SPI_CPHA);
 636         bool flip_cpha = (spi->mode & SPI_RX_CPHA_FLIP) && spi_imx->rx_only;
 637         u32 cfg = readl(spi_imx->base + MX51_ECSPI_CONFIG);
 638         int channel = mx51_ecspi_channel(spi);
 639
 640         /* Flip cpha logical value iff flip_cpha */
 641         cpha ^= flip_cpha;
 642
 643         if (cpha)
 644                 cfg |= MX51_ECSPI_CONFIG_SCLKPHA(channel);
 645         else
 646                 cfg &= ~MX51_ECSPI_CONFIG_SCLKPHA(channel);
 647
 648         writel(cfg, spi_imx->base + MX51_ECSPI_CONFIG);
 649 }
 650
 651 static int mx51_ecspi_prepare_transfer(struct spi_imx_data *spi_imx,
 652                                        struct spi_device *spi)
 653 {
 654         u32 ctrl = readl(spi_imx->base + MX51_ECSPI_CTRL);
 655         u32 clk;
 656
 657         /* Clear BL field and set the right value */
 658         ctrl &= ~MX51_ECSPI_CTRL_BL_MASK;
 659         if (spi_imx->target_mode && is_imx53_ecspi(spi_imx))
 660                 ctrl |= (spi_imx->target_burst * 8 - 1)
 661                         << MX51_ECSPI_CTRL_BL_OFFSET;
 662         else {
 663                 ctrl |= (spi_imx->bits_per_word - 1)
 664                         << MX51_ECSPI_CTRL_BL_OFFSET;
 665         }
 666
 667         /* set clock speed */
 668         ctrl &= ~(0xf << MX51_ECSPI_CTRL_POSTDIV_OFFSET |
 669                   0xf << MX51_ECSPI_CTRL_PREDIV_OFFSET);
 670         ctrl |= mx51_ecspi_clkdiv(spi_imx, spi_imx->spi_bus_clk, &clk);
 671         spi_imx->spi_bus_clk = clk;
 672
 673         mx51_configure_cpha(spi_imx, spi);
 674
 675         /*
 676          * ERR009165: work in XHC mode instead of SMC as PIO on the chips
 677          * before i.mx6ul.
 678          */
 679         if (spi_imx->usedma && spi_imx->devtype_data->tx_glitch_fixed)
 680                 ctrl |= MX51_ECSPI_CTRL_SMC;
 681         else
 682                 ctrl &= ~MX51_ECSPI_CTRL_SMC;
 683
 684         writel(ctrl, spi_imx->base + MX51_ECSPI_CTRL);
 685
 686         return 0;
 687 }
 688
 689 static void mx51_setup_wml(struct spi_imx_data *spi_imx)
 690 {
 691         u32 tx_wml = 0;
 692
 693         if (spi_imx->devtype_data->tx_glitch_fixed)
 694                 tx_wml = spi_imx->wml;
 695         /*
 696          * Configure the DMA register: setup the watermark
 697          * and enable DMA request.
 698          */
 699         writel(MX51_ECSPI_DMA_RX_WML(spi_imx->wml - 1) |
 700                 MX51_ECSPI_DMA_TX_WML(tx_wml) |
 701                 MX51_ECSPI_DMA_RXT_WML(spi_imx->wml) |
 702                 MX51_ECSPI_DMA_TEDEN | MX51_ECSPI_DMA_RXDEN |
 703                 MX51_ECSPI_DMA_RXTDEN, spi_imx->base + MX51_ECSPI_DMA);
 704 }
 705
 706 static int mx51_ecspi_rx_available(struct spi_imx_data *spi_imx)
 707 {
 708         return readl(spi_imx->base + MX51_ECSPI_STAT) & MX51_ECSPI_STAT_RR;
 709 }
 710
 711 static void mx51_ecspi_reset(struct spi_imx_data *spi_imx)
 712 {
 713         /* drain receive buffer */
 714         while (mx51_ecspi_rx_available(spi_imx))
 715                 readl(spi_imx->base + MXC_CSPIRXDATA);
 716 }
 717
 718 #define MX31_INTREG_TEEN        (1 << 0)
 719 #define MX31_INTREG_RREN        (1 << 3)
 720
 721 #define MX31_CSPICTRL_ENABLE    (1 << 0)
 722 #define MX31_CSPICTRL_HOST      (1 << 1)
 723 #define MX31_CSPICTRL_XCH       (1 << 2)
 724 #define MX31_CSPICTRL_SMC       (1 << 3)
 725 #define MX31_CSPICTRL_POL       (1 << 4)
 726 #define MX31_CSPICTRL_PHA       (1 << 5)
 727 #define MX31_CSPICTRL_SSCTL     (1 << 6)
 728 #define MX31_CSPICTRL_SSPOL     (1 << 7)
 729 #define MX31_CSPICTRL_BC_SHIFT  8
 730 #define MX35_CSPICTRL_BL_SHIFT  20
 731 #define MX31_CSPICTRL_CS_SHIFT  24
 732 #define MX35_CSPICTRL_CS_SHIFT  12
 733 #define MX31_CSPICTRL_DR_SHIFT  16
 734
 735 #define MX31_CSPI_DMAREG        0x10
 736 #define MX31_DMAREG_RH_DEN      (1<<4)
 737 #define MX31_DMAREG_TH_DEN      (1<<1)
 738
 739 #define MX31_CSPISTATUS         0x14
 740 #define MX31_STATUS_RR          (1 << 3)
 741
 742 #define MX31_CSPI_TESTREG       0x1C
 743 #define MX31_TEST_LBC           (1 << 14)
 744
 745 /* These functions also work for the i.MX35, but be aware that
 746  * the i.MX35 has a slightly different register layout for bits
 747  * we do not use here.
 748  */
 749 static void mx31_intctrl(struct spi_imx_data *spi_imx, int enable)
 750 {
 751         unsigned int val = 0;
 752
 753         if (enable & MXC_INT_TE)
 754                 val |= MX31_INTREG_TEEN;
 755         if (enable & MXC_INT_RR)
 756                 val |= MX31_INTREG_RREN;
 757
 758         writel(val, spi_imx->base + MXC_CSPIINT);
 759 }
 760
 761 static void mx31_trigger(struct spi_imx_data *spi_imx)
 762 {
 763         unsigned int reg;
 764
 765         reg = readl(spi_imx->base + MXC_CSPICTRL);
 766         reg |= MX31_CSPICTRL_XCH;
 767         writel(reg, spi_imx->base + MXC_CSPICTRL);
 768 }
 769
 770 static int mx31_prepare_message(struct spi_imx_data *spi_imx,
 771                                 struct spi_message *msg)
 772 {
 773         return 0;
 774 }
 775
 776 static int mx31_prepare_transfer(struct spi_imx_data *spi_imx,
 777                                  struct spi_device *spi)
 778 {
 779         unsigned int reg = MX31_CSPICTRL_ENABLE | MX31_CSPICTRL_HOST;
 780         unsigned int clk;
 781
 782         reg |= spi_imx_clkdiv_2(spi_imx->spi_clk, spi_imx->spi_bus_clk, &clk) <<
 783                 MX31_CSPICTRL_DR_SHIFT;
 784         spi_imx->spi_bus_clk = clk;
 785
 786         if (is_imx35_cspi(spi_imx)) {
 787                 reg |= (spi_imx->bits_per_word - 1) << MX35_CSPICTRL_BL_SHIFT;
 788                 reg |= MX31_CSPICTRL_SSCTL;
 789         } else {
 790                 reg |= (spi_imx->bits_per_word - 1) << MX31_CSPICTRL_BC_SHIFT;
 791         }
 792
 793         if (spi->mode & SPI_CPHA)
 794                 reg |= MX31_CSPICTRL_PHA;
 795         if (spi->mode & SPI_CPOL)
 796                 reg |= MX31_CSPICTRL_POL;
 797         if (spi->mode & SPI_CS_HIGH)
 798                 reg |= MX31_CSPICTRL_SSPOL;
 799         if (!spi_get_csgpiod(spi, 0))
 800                 reg |= (spi_get_chipselect(spi, 0)) <<
 801                         (is_imx35_cspi(spi_imx) ? MX35_CSPICTRL_CS_SHIFT :
 802                                                   MX31_CSPICTRL_CS_SHIFT);
 803
 804         if (spi_imx->usedma)
 805                 reg |= MX31_CSPICTRL_SMC;
 806
 807         writel(reg, spi_imx->base + MXC_CSPICTRL);
 808
 809         reg = readl(spi_imx->base + MX31_CSPI_TESTREG);
 810         if (spi->mode & SPI_LOOP)
 811                 reg |= MX31_TEST_LBC;
 812         else
 813                 reg &= ~MX31_TEST_LBC;
 814         writel(reg, spi_imx->base + MX31_CSPI_TESTREG);
 815
 816         if (spi_imx->usedma) {
 817                 /*
 818                  * configure DMA requests when RXFIFO is half full and
 819                  * when TXFIFO is half empty
 820                  */
 821                 writel(MX31_DMAREG_RH_DEN | MX31_DMAREG_TH_DEN,
 822                         spi_imx->base + MX31_CSPI_DMAREG);
 823         }
 824
 825         return 0;
 826 }
 827
 828 static int mx31_rx_available(struct spi_imx_data *spi_imx)
 829 {
 830         return readl(spi_imx->base + MX31_CSPISTATUS) & MX31_STATUS_RR;
 831 }
 832
 833 static void mx31_reset(struct spi_imx_data *spi_imx)
 834 {
 835         /* drain receive buffer */
 836         while (readl(spi_imx->base + MX31_CSPISTATUS) & MX31_STATUS_RR)
 837                 readl(spi_imx->base + MXC_CSPIRXDATA);
 838 }
 839
 840 #define MX21_INTREG_RR          (1 << 4)
 841 #define MX21_INTREG_TEEN        (1 << 9)
 842 #define MX21_INTREG_RREN        (1 << 13)
 843
 844 #define MX21_CSPICTRL_POL       (1 << 5)
 845 #define MX21_CSPICTRL_PHA       (1 << 6)
 846 #define MX21_CSPICTRL_SSPOL     (1 << 8)
 847 #define MX21_CSPICTRL_XCH       (1 << 9)
 848 #define MX21_CSPICTRL_ENABLE    (1 << 10)
 849 #define MX21_CSPICTRL_HOST      (1 << 11)
 850 #define MX21_CSPICTRL_DR_SHIFT  14
 851 #define MX21_CSPICTRL_CS_SHIFT  19
 852
 853 static void mx21_intctrl(struct spi_imx_data *spi_imx, int enable)
 854 {
 855         unsigned int val = 0;
 856
 857         if (enable & MXC_INT_TE)
 858                 val |= MX21_INTREG_TEEN;
 859         if (enable & MXC_INT_RR)
 860                 val |= MX21_INTREG_RREN;
 861
 862         writel(val, spi_imx->base + MXC_CSPIINT);
 863 }
 864
 865 static void mx21_trigger(struct spi_imx_data *spi_imx)
 866 {
 867         unsigned int reg;
 868
 869         reg = readl(spi_imx->base + MXC_CSPICTRL);
 870         reg |= MX21_CSPICTRL_XCH;
 871         writel(reg, spi_imx->base + MXC_CSPICTRL);
 872 }
 873
 874 static int mx21_prepare_message(struct spi_imx_data *spi_imx,
 875                                 struct spi_message *msg)
 876 {
 877         return 0;
 878 }
 879
 880 static int mx21_prepare_transfer(struct spi_imx_data *spi_imx,
 881                                  struct spi_device *spi)
 882 {
 883         unsigned int reg = MX21_CSPICTRL_ENABLE | MX21_CSPICTRL_HOST;
 884         unsigned int max = is_imx27_cspi(spi_imx) ? 16 : 18;
 885         unsigned int clk;
 886
 887         reg |= spi_imx_clkdiv_1(spi_imx->spi_clk, spi_imx->spi_bus_clk, max, &clk)
 888                 << MX21_CSPICTRL_DR_SHIFT;
 889         spi_imx->spi_bus_clk = clk;
 890
 891         reg |= spi_imx->bits_per_word - 1;
 892
 893         if (spi->mode & SPI_CPHA)
 894                 reg |= MX21_CSPICTRL_PHA;
 895         if (spi->mode & SPI_CPOL)
 896                 reg |= MX21_CSPICTRL_POL;
 897         if (spi->mode & SPI_CS_HIGH)
 898                 reg |= MX21_CSPICTRL_SSPOL;
 899         if (!spi_get_csgpiod(spi, 0))
 900                 reg |= spi_get_chipselect(spi, 0) << MX21_CSPICTRL_CS_SHIFT;
 901
 902         writel(reg, spi_imx->base + MXC_CSPICTRL);
 903
 904         return 0;
 905 }
 906
 907 static int mx21_rx_available(struct spi_imx_data *spi_imx)
 908 {
 909         return readl(spi_imx->base + MXC_CSPIINT) & MX21_INTREG_RR;
 910 }
 911
 912 static void mx21_reset(struct spi_imx_data *spi_imx)
 913 {
 914         writel(1, spi_imx->base + MXC_RESET);
 915 }
 916
 917 #define MX1_INTREG_RR           (1 << 3)
 918 #define MX1_INTREG_TEEN         (1 << 8)
 919 #define MX1_INTREG_RREN         (1 << 11)
 920
 921 #define MX1_CSPICTRL_POL        (1 << 4)
 922 #define MX1_CSPICTRL_PHA        (1 << 5)
 923 #define MX1_CSPICTRL_XCH        (1 << 8)
 924 #define MX1_CSPICTRL_ENABLE     (1 << 9)
 925 #define MX1_CSPICTRL_HOST       (1 << 10)
 926 #define MX1_CSPICTRL_DR_SHIFT   13
 927
 928 static void mx1_intctrl(struct spi_imx_data *spi_imx, int enable)
 929 {
 930         unsigned int val = 0;
 931
 932         if (enable & MXC_INT_TE)
 933                 val |= MX1_INTREG_TEEN;
 934         if (enable & MXC_INT_RR)
 935                 val |= MX1_INTREG_RREN;
 936
 937         writel(val, spi_imx->base + MXC_CSPIINT);
 938 }
 939
 940 static void mx1_trigger(struct spi_imx_data *spi_imx)
 941 {
 942         unsigned int reg;
 943
 944         reg = readl(spi_imx->base + MXC_CSPICTRL);
 945         reg |= MX1_CSPICTRL_XCH;
 946         writel(reg, spi_imx->base + MXC_CSPICTRL);
 947 }
 948
 949 static int mx1_prepare_message(struct spi_imx_data *spi_imx,
 950                                struct spi_message *msg)
 951 {
 952         return 0;
 953 }
 954
 955 static int mx1_prepare_transfer(struct spi_imx_data *spi_imx,
 956                                 struct spi_device *spi)
 957 {
 958         unsigned int reg = MX1_CSPICTRL_ENABLE | MX1_CSPICTRL_HOST;
 959         unsigned int clk;
 960
 961         reg |= spi_imx_clkdiv_2(spi_imx->spi_clk, spi_imx->spi_bus_clk, &clk) <<
 962                 MX1_CSPICTRL_DR_SHIFT;
 963         spi_imx->spi_bus_clk = clk;
 964
 965         reg |= spi_imx->bits_per_word - 1;
 966
 967         if (spi->mode & SPI_CPHA)
 968                 reg |= MX1_CSPICTRL_PHA;
 969         if (spi->mode & SPI_CPOL)
 970                 reg |= MX1_CSPICTRL_POL;
 971
 972         writel(reg, spi_imx->base + MXC_CSPICTRL);
 973
 974         return 0;
 975 }
 976
 977 static int mx1_rx_available(struct spi_imx_data *spi_imx)
 978 {
 979         return readl(spi_imx->base + MXC_CSPIINT) & MX1_INTREG_RR;
 980 }
 981
 982 static void mx1_reset(struct spi_imx_data *spi_imx)
 983 {
 984         writel(1, spi_imx->base + MXC_RESET);
 985 }
 986
 987 static struct spi_imx_devtype_data imx1_cspi_devtype_data = {
 988         .intctrl = mx1_intctrl,
 989         .prepare_message = mx1_prepare_message,
 990         .prepare_transfer = mx1_prepare_transfer,
 991         .trigger = mx1_trigger,
 992         .rx_available = mx1_rx_available,
 993         .reset = mx1_reset,
 994         .fifo_size = 8,
 995         .has_dmamode = false,
 996         .dynamic_burst = false,
 997         .has_targetmode = false,
 998         .devtype = IMX1_CSPI,
 999 };
1000
1001 static struct spi_imx_devtype_data imx21_cspi_devtype_data = {
1002         .intctrl = mx21_intctrl,
1003         .prepare_message = mx21_prepare_message,
1004         .prepare_transfer = mx21_prepare_transfer,
1005         .trigger = mx21_trigger,
1006         .rx_available = mx21_rx_available,
1007         .reset = mx21_reset,
1008         .fifo_size = 8,
1009         .has_dmamode = false,
1010         .dynamic_burst = false,
1011         .has_targetmode = false,
1012         .devtype = IMX21_CSPI,
1013 };
1014
1015 static struct spi_imx_devtype_data imx27_cspi_devtype_data = {
1016         /* i.mx27 cspi shares the functions with i.mx21 one */
1017         .intctrl = mx21_intctrl,
1018         .prepare_message = mx21_prepare_message,
1019         .prepare_transfer = mx21_prepare_transfer,
1020         .trigger = mx21_trigger,
1021         .rx_available = mx21_rx_available,
1022         .reset = mx21_reset,
1023         .fifo_size = 8,
1024         .has_dmamode = false,
1025         .dynamic_burst = false,
1026         .has_targetmode = false,
1027         .devtype = IMX27_CSPI,
1028 };
1029
1030 static struct spi_imx_devtype_data imx31_cspi_devtype_data = {
1031         .intctrl = mx31_intctrl,
1032         .prepare_message = mx31_prepare_message,
1033         .prepare_transfer = mx31_prepare_transfer,
1034         .trigger = mx31_trigger,
1035         .rx_available = mx31_rx_available,
1036         .reset = mx31_reset,
1037         .fifo_size = 8,
1038         .has_dmamode = false,
1039         .dynamic_burst = false,
1040         .has_targetmode = false,
1041         .devtype = IMX31_CSPI,
1042 };
1043
1044 static struct spi_imx_devtype_data imx35_cspi_devtype_data = {
1045         /* i.mx35 and later cspi shares the functions with i.mx31 one */
1046         .intctrl = mx31_intctrl,
1047         .prepare_message = mx31_prepare_message,
1048         .prepare_transfer = mx31_prepare_transfer,
1049         .trigger = mx31_trigger,
1050         .rx_available = mx31_rx_available,
1051         .reset = mx31_reset,
1052         .fifo_size = 8,
1053         .has_dmamode = false,
1054         .dynamic_burst = false,
1055         .has_targetmode = false,
1056         .devtype = IMX35_CSPI,
1057 };
1058
1059 static struct spi_imx_devtype_data imx51_ecspi_devtype_data = {
1060         .intctrl = mx51_ecspi_intctrl,
1061         .prepare_message = mx51_ecspi_prepare_message,
1062         .prepare_transfer = mx51_ecspi_prepare_transfer,
1063         .trigger = mx51_ecspi_trigger,
1064         .rx_available = mx51_ecspi_rx_available,
1065         .reset = mx51_ecspi_reset,
1066         .setup_wml = mx51_setup_wml,
1067         .fifo_size = 64,
1068         .has_dmamode = true,
1069         .dynamic_burst = true,
1070         .has_targetmode = true,
1071         .disable = mx51_ecspi_disable,
1072         .devtype = IMX51_ECSPI,
1073 };
1074
1075 static struct spi_imx_devtype_data imx53_ecspi_devtype_data = {
1076         .intctrl = mx51_ecspi_intctrl,
1077         .prepare_message = mx51_ecspi_prepare_message,
1078         .prepare_transfer = mx51_ecspi_prepare_transfer,
1079         .trigger = mx51_ecspi_trigger,
1080         .rx_available = mx51_ecspi_rx_available,
1081         .reset = mx51_ecspi_reset,
1082         .fifo_size = 64,
1083         .has_dmamode = true,
1084         .has_targetmode = true,
1085         .disable = mx51_ecspi_disable,
1086         .devtype = IMX53_ECSPI,
1087 };
1088
1089 static struct spi_imx_devtype_data imx6ul_ecspi_devtype_data = {
1090         .intctrl = mx51_ecspi_intctrl,
1091         .prepare_message = mx51_ecspi_prepare_message,
1092         .prepare_transfer = mx51_ecspi_prepare_transfer,
1093         .trigger = mx51_ecspi_trigger,
1094         .rx_available = mx51_ecspi_rx_available,
1095         .reset = mx51_ecspi_reset,
1096         .setup_wml = mx51_setup_wml,
1097         .fifo_size = 64,
1098         .has_dmamode = true,
1099         .dynamic_burst = true,
1100         .has_targetmode = true,
1101         .tx_glitch_fixed = true,
1102         .disable = mx51_ecspi_disable,
1103         .devtype = IMX51_ECSPI,
1104 };
1105
1106 static const struct of_device_id spi_imx_dt_ids[] = {
1107         { .compatible = "fsl,imx1-cspi", .data = &imx1_cspi_devtype_data, },
1108         { .compatible = "fsl,imx21-cspi", .data = &imx21_cspi_devtype_data, },
1109         { .compatible = "fsl,imx27-cspi", .data = &imx27_cspi_devtype_data, },
1110         { .compatible = "fsl,imx31-cspi", .data = &imx31_cspi_devtype_data, },
1111         { .compatible = "fsl,imx35-cspi", .data = &imx35_cspi_devtype_data, },
1112         { .compatible = "fsl,imx51-ecspi", .data = &imx51_ecspi_devtype_data, },
1113         { .compatible = "fsl,imx53-ecspi", .data = &imx53_ecspi_devtype_data, },
1114         { .compatible = "fsl,imx6ul-ecspi", .data = &imx6ul_ecspi_devtype_data, },
1115         { /* sentinel */ }
1116 };
1117 MODULE_DEVICE_TABLE(of, spi_imx_dt_ids);
1118
1119 static void spi_imx_set_burst_len(struct spi_imx_data *spi_imx, int n_bits)
1120 {
1121         u32 ctrl;
1122
1123         ctrl = readl(spi_imx->base + MX51_ECSPI_CTRL);
1124         ctrl &= ~MX51_ECSPI_CTRL_BL_MASK;
1125         ctrl |= ((n_bits - 1) << MX51_ECSPI_CTRL_BL_OFFSET);
1126         writel(ctrl, spi_imx->base + MX51_ECSPI_CTRL);
1127 }
1128
1129 static void spi_imx_push(struct spi_imx_data *spi_imx)
1130 {
1131         unsigned int burst_len;
1132
1133         /*
1134          * Reload the FIFO when the remaining bytes to be transferred in the
1135          * current burst is 0. This only applies when bits_per_word is a
1136          * multiple of 8.
1137          */
1138         if (!spi_imx->remainder) {
1139                 if (spi_imx->dynamic_burst) {
1140
1141                         /* We need to deal unaligned data first */
1142                         burst_len = spi_imx->count % MX51_ECSPI_CTRL_MAX_BURST;
1143
1144                         if (!burst_len)
1145                                 burst_len = MX51_ECSPI_CTRL_MAX_BURST;
1146
1147                         spi_imx_set_burst_len(spi_imx, burst_len * 8);
1148
1149                         spi_imx->remainder = burst_len;
1150                 } else {
1151                         spi_imx->remainder = spi_imx_bytes_per_word(spi_imx->bits_per_word);
1152                 }
1153         }
1154
1155         while (spi_imx->txfifo < spi_imx->devtype_data->fifo_size) {
1156                 if (!spi_imx->count)
1157                         break;
1158                 if (spi_imx->dynamic_burst &&
1159                     spi_imx->txfifo >= DIV_ROUND_UP(spi_imx->remainder, 4))
1160                         break;
1161                 spi_imx->tx(spi_imx);
1162                 spi_imx->txfifo++;
1163         }
1164
1165         if (!spi_imx->target_mode)
1166                 spi_imx->devtype_data->trigger(spi_imx);
1167 }
1168
1169 static irqreturn_t spi_imx_isr(int irq, void *dev_id)
1170 {
1171         struct spi_imx_data *spi_imx = dev_id;
1172
1173         while (spi_imx->txfifo &&
1174                spi_imx->devtype_data->rx_available(spi_imx)) {
1175                 spi_imx->rx(spi_imx);
1176                 spi_imx->txfifo--;
1177         }
1178
1179         if (spi_imx->count) {
1180                 spi_imx_push(spi_imx);
1181                 return IRQ_HANDLED;
1182         }
1183
1184         if (spi_imx->txfifo) {
1185                 /* No data left to push, but still waiting for rx data,
1186                  * enable receive data available interrupt.
1187                  */
1188                 spi_imx->devtype_data->intctrl(
1189                                 spi_imx, MXC_INT_RR);
1190                 return IRQ_HANDLED;
1191         }
1192
1193         spi_imx->devtype_data->intctrl(spi_imx, 0);
1194         complete(&spi_imx->xfer_done);
1195
1196         return IRQ_HANDLED;
1197 }
1198
1199 static int spi_imx_dma_configure(struct spi_controller *controller)
1200 {
1201         int ret;
1202         enum dma_slave_buswidth buswidth;
1203         struct dma_slave_config rx = {}, tx = {};
1204         struct spi_imx_data *spi_imx = spi_controller_get_devdata(controller);
1205
1206         switch (spi_imx_bytes_per_word(spi_imx->bits_per_word)) {
1207         case 4:
1208                 buswidth = DMA_SLAVE_BUSWIDTH_4_BYTES;
1209                 break;
1210         case 2:
1211                 buswidth = DMA_SLAVE_BUSWIDTH_2_BYTES;
1212                 break;
1213         case 1:
1214                 buswidth = DMA_SLAVE_BUSWIDTH_1_BYTE;
1215                 break;
1216         default:
1217                 return -EINVAL;
1218         }
1219
1220         tx.direction = DMA_MEM_TO_DEV;
1221         tx.dst_addr = spi_imx->base_phys + MXC_CSPITXDATA;
1222         tx.dst_addr_width = buswidth;
1223         tx.dst_maxburst = spi_imx->wml;
1224         ret = dmaengine_slave_config(controller->dma_tx, &tx);
1225         if (ret) {
1226                 dev_err(spi_imx->dev, "TX dma configuration failed with %d\n", ret);
1227                 return ret;
1228         }
1229
1230         rx.direction = DMA_DEV_TO_MEM;
1231         rx.src_addr = spi_imx->base_phys + MXC_CSPIRXDATA;
1232         rx.src_addr_width = buswidth;
1233         rx.src_maxburst = spi_imx->wml;
1234         ret = dmaengine_slave_config(controller->dma_rx, &rx);
1235         if (ret) {
1236                 dev_err(spi_imx->dev, "RX dma configuration failed with %d\n", ret);
1237                 return ret;
1238         }
1239
1240         return 0;
1241 }
1242
1243 static int spi_imx_setupxfer(struct spi_device *spi,
1244                                  struct spi_transfer *t)
1245 {
1246         struct spi_imx_data *spi_imx = spi_controller_get_devdata(spi->controller);
1247
1248         if (!t)
1249                 return 0;
1250
1251         if (!t->speed_hz) {
1252                 if (!spi->max_speed_hz) {
1253                         dev_err(&spi->dev, "no speed_hz provided!\n");
1254                         return -EINVAL;
1255                 }
1256                 dev_dbg(&spi->dev, "using spi->max_speed_hz!\n");
1257                 spi_imx->spi_bus_clk = spi->max_speed_hz;
1258         } else
1259                 spi_imx->spi_bus_clk = t->speed_hz;
1260
1261         spi_imx->bits_per_word = t->bits_per_word;
1262         spi_imx->count = t->len;
1263
1264         /*
1265          * Initialize the functions for transfer. To transfer non byte-aligned
1266          * words, we have to use multiple word-size bursts, we can't use
1267          * dynamic_burst in that case.
1268          */
1269         if (spi_imx->devtype_data->dynamic_burst && !spi_imx->target_mode &&
1270             !(spi->mode & SPI_CS_WORD) &&
1271             (spi_imx->bits_per_word == 8 ||
1272             spi_imx->bits_per_word == 16 ||
1273             spi_imx->bits_per_word == 32)) {
1274
1275                 spi_imx->rx = spi_imx_buf_rx_swap;
1276                 spi_imx->tx = spi_imx_buf_tx_swap;
1277                 spi_imx->dynamic_burst = 1;
1278
1279         } else {
1280                 if (spi_imx->bits_per_word <= 8) {
1281                         spi_imx->rx = spi_imx_buf_rx_u8;
1282                         spi_imx->tx = spi_imx_buf_tx_u8;
1283                 } else if (spi_imx->bits_per_word <= 16) {
1284                         spi_imx->rx = spi_imx_buf_rx_u16;
1285                         spi_imx->tx = spi_imx_buf_tx_u16;
1286                 } else {
1287                         spi_imx->rx = spi_imx_buf_rx_u32;
1288                         spi_imx->tx = spi_imx_buf_tx_u32;
1289                 }
1290                 spi_imx->dynamic_burst = 0;
1291         }
1292
1293         if (spi_imx_can_dma(spi_imx->controller, spi, t))
1294                 spi_imx->usedma = true;
1295         else
1296                 spi_imx->usedma = false;
1297
1298         spi_imx->rx_only = ((t->tx_buf == NULL)
1299                         || (t->tx_buf == spi->controller->dummy_tx));
1300
1301         if (is_imx53_ecspi(spi_imx) && spi_imx->target_mode) {
1302                 spi_imx->rx = mx53_ecspi_rx_target;
1303                 spi_imx->tx = mx53_ecspi_tx_target;
1304                 spi_imx->target_burst = t->len;
1305         }
1306
1307         spi_imx->devtype_data->prepare_transfer(spi_imx, spi);
1308
1309         return 0;
1310 }
1311
1312 static void spi_imx_sdma_exit(struct spi_imx_data *spi_imx)
1313 {
1314         struct spi_controller *controller = spi_imx->controller;
1315
1316         if (controller->dma_rx) {
1317                 dma_release_channel(controller->dma_rx);
1318                 controller->dma_rx = NULL;
1319         }
1320
1321         if (controller->dma_tx) {
1322                 dma_release_channel(controller->dma_tx);
1323                 controller->dma_tx = NULL;
1324         }
1325 }
1326
1327 static int spi_imx_sdma_init(struct device *dev, struct spi_imx_data *spi_imx,
1328                              struct spi_controller *controller)
1329 {
1330         int ret;
1331
1332         spi_imx->wml = spi_imx->devtype_data->fifo_size / 2;
1333
1334         /* Prepare for TX DMA: */
1335         controller->dma_tx = dma_request_chan(dev, "tx");
1336         if (IS_ERR(controller->dma_tx)) {
1337                 ret = PTR_ERR(controller->dma_tx);
1338                 dev_err_probe(dev, ret, "can't get the TX DMA channel!\n");
1339                 controller->dma_tx = NULL;
1340                 goto err;
1341         }
1342
1343         /* Prepare for RX : */
1344         controller->dma_rx = dma_request_chan(dev, "rx");
1345         if (IS_ERR(controller->dma_rx)) {
1346                 ret = PTR_ERR(controller->dma_rx);
1347                 dev_err_probe(dev, ret, "can't get the RX DMA channel!\n");
1348                 controller->dma_rx = NULL;
1349                 goto err;
1350         }
1351
1352         init_completion(&spi_imx->dma_rx_completion);
1353         init_completion(&spi_imx->dma_tx_completion);
1354         controller->can_dma = spi_imx_can_dma;
1355         controller->max_dma_len = MAX_SDMA_BD_BYTES;
1356         spi_imx->controller->flags = SPI_CONTROLLER_MUST_RX |
1357                                          SPI_CONTROLLER_MUST_TX;
1358
1359         return 0;
1360 err:
1361         spi_imx_sdma_exit(spi_imx);
1362         return ret;
1363 }
1364
1365 static void spi_imx_dma_rx_callback(void *cookie)
1366 {
1367         struct spi_imx_data *spi_imx = (struct spi_imx_data *)cookie;
1368
1369         complete(&spi_imx->dma_rx_completion);
1370 }
1371
1372 static void spi_imx_dma_tx_callback(void *cookie)
1373 {
1374         struct spi_imx_data *spi_imx = (struct spi_imx_data *)cookie;
1375
1376         complete(&spi_imx->dma_tx_completion);
1377 }
1378
1379 static int spi_imx_calculate_timeout(struct spi_imx_data *spi_imx, int size)
1380 {
1381         unsigned long timeout = 0;
1382
1383         /* Time with actual data transfer and CS change delay related to HW */
1384         timeout = (8 + 4) * size / spi_imx->spi_bus_clk;
1385
1386         /* Add extra second for scheduler related activities */
1387         timeout += 1;
1388
1389         /* Double calculated timeout */
1390         return msecs_to_jiffies(2 * timeout * MSEC_PER_SEC);
1391 }
1392
1393 static int spi_imx_dma_transfer(struct spi_imx_data *spi_imx,
1394                                 struct spi_transfer *transfer)
1395 {
1396         struct dma_async_tx_descriptor *desc_tx, *desc_rx;
1397         unsigned long transfer_timeout;
1398         unsigned long time_left;
1399         struct spi_controller *controller = spi_imx->controller;
1400         struct sg_table *tx = &transfer->tx_sg, *rx = &transfer->rx_sg;
1401         struct scatterlist *last_sg = sg_last(rx->sgl, rx->nents);
1402         unsigned int bytes_per_word, i;
1403         int ret;
1404
1405         /* Get the right burst length from the last sg to ensure no tail data */
1406         bytes_per_word = spi_imx_bytes_per_word(transfer->bits_per_word);
1407         for (i = spi_imx->devtype_data->fifo_size / 2; i > 0; i--) {
1408                 if (!(sg_dma_len(last_sg) % (i * bytes_per_word)))
1409                         break;
1410         }
1411         /* Use 1 as wml in case no available burst length got */
1412         if (i == 0)
1413                 i = 1;
1414
1415         spi_imx->wml =  i;
1416
1417         ret = spi_imx_dma_configure(controller);
1418         if (ret)
1419                 goto dma_failure_no_start;
1420
1421         if (!spi_imx->devtype_data->setup_wml) {
1422                 dev_err(spi_imx->dev, "No setup_wml()?\n");
1423                 ret = -EINVAL;
1424                 goto dma_failure_no_start;
1425         }
1426         spi_imx->devtype_data->setup_wml(spi_imx);
1427
1428         /*
1429          * The TX DMA setup starts the transfer, so make sure RX is configured
1430          * before TX.
1431          */
1432         desc_rx = dmaengine_prep_slave_sg(controller->dma_rx,
1433                                 rx->sgl, rx->nents, DMA_DEV_TO_MEM,
1434                                 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
1435         if (!desc_rx) {
1436                 ret = -EINVAL;
1437                 goto dma_failure_no_start;
1438         }
1439
1440         desc_rx->callback = spi_imx_dma_rx_callback;
1441         desc_rx->callback_param = (void *)spi_imx;
1442         dmaengine_submit(desc_rx);
1443         reinit_completion(&spi_imx->dma_rx_completion);
1444         dma_async_issue_pending(controller->dma_rx);
1445
1446         desc_tx = dmaengine_prep_slave_sg(controller->dma_tx,
1447                                 tx->sgl, tx->nents, DMA_MEM_TO_DEV,
1448                                 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
1449         if (!desc_tx) {
1450                 dmaengine_terminate_all(controller->dma_tx);
1451                 dmaengine_terminate_all(controller->dma_rx);
1452                 return -EINVAL;
1453         }
1454
1455         desc_tx->callback = spi_imx_dma_tx_callback;
1456         desc_tx->callback_param = (void *)spi_imx;
1457         dmaengine_submit(desc_tx);
1458         reinit_completion(&spi_imx->dma_tx_completion);
1459         dma_async_issue_pending(controller->dma_tx);
1460
1461         transfer_timeout = spi_imx_calculate_timeout(spi_imx, transfer->len);
1462
1463         /* Wait SDMA to finish the data transfer.*/
1464         time_left = wait_for_completion_timeout(&spi_imx->dma_tx_completion,
1465                                                 transfer_timeout);
1466         if (!time_left) {
1467                 dev_err(spi_imx->dev, "I/O Error in DMA TX\n");
1468                 dmaengine_terminate_all(controller->dma_tx);
1469                 dmaengine_terminate_all(controller->dma_rx);
1470                 return -ETIMEDOUT;
1471         }
1472
1473         time_left = wait_for_completion_timeout(&spi_imx->dma_rx_completion,
1474                                                 transfer_timeout);
1475         if (!time_left) {
1476                 dev_err(&controller->dev, "I/O Error in DMA RX\n");
1477                 spi_imx->devtype_data->reset(spi_imx);
1478                 dmaengine_terminate_all(controller->dma_rx);
1479                 return -ETIMEDOUT;
1480         }
1481
1482         return 0;
1483 /* fallback to pio */
1484 dma_failure_no_start:
1485         transfer->error |= SPI_TRANS_FAIL_NO_START;
1486         return ret;
1487 }
1488
1489 static int spi_imx_pio_transfer(struct spi_device *spi,
1490                                 struct spi_transfer *transfer)
1491 {
1492         struct spi_imx_data *spi_imx = spi_controller_get_devdata(spi->controller);
1493         unsigned long transfer_timeout;
1494         unsigned long time_left;
1495
1496         spi_imx->tx_buf = transfer->tx_buf;
1497         spi_imx->rx_buf = transfer->rx_buf;
1498         spi_imx->count = transfer->len;
1499         spi_imx->txfifo = 0;
1500         spi_imx->remainder = 0;
1501
1502         reinit_completion(&spi_imx->xfer_done);
1503
1504         spi_imx_push(spi_imx);
1505
1506         spi_imx->devtype_data->intctrl(spi_imx, MXC_INT_TE);
1507
1508         transfer_timeout = spi_imx_calculate_timeout(spi_imx, transfer->len);
1509
1510         time_left = wait_for_completion_timeout(&spi_imx->xfer_done,
1511                                                 transfer_timeout);
1512         if (!time_left) {
1513                 dev_err(&spi->dev, "I/O Error in PIO\n");
1514                 spi_imx->devtype_data->reset(spi_imx);
1515                 return -ETIMEDOUT;
1516         }
1517
1518         return 0;
1519 }
1520
1521 static int spi_imx_poll_transfer(struct spi_device *spi,
1522                                  struct spi_transfer *transfer)
1523 {
1524         struct spi_imx_data *spi_imx = spi_controller_get_devdata(spi->controller);
1525         unsigned long timeout;
1526
1527         spi_imx->tx_buf = transfer->tx_buf;
1528         spi_imx->rx_buf = transfer->rx_buf;
1529         spi_imx->count = transfer->len;
1530         spi_imx->txfifo = 0;
1531         spi_imx->remainder = 0;
1532
1533         /* fill in the fifo before timeout calculations if we are
1534          * interrupted here, then the data is getting transferred by
1535          * the HW while we are interrupted
1536          */
1537         spi_imx_push(spi_imx);
1538
1539         timeout = spi_imx_calculate_timeout(spi_imx, transfer->len) + jiffies;
1540         while (spi_imx->txfifo) {
1541                 /* RX */
1542                 while (spi_imx->txfifo &&
1543                        spi_imx->devtype_data->rx_available(spi_imx)) {
1544                         spi_imx->rx(spi_imx);
1545                         spi_imx->txfifo--;
1546                 }
1547
1548                 /* TX */
1549                 if (spi_imx->count) {
1550                         spi_imx_push(spi_imx);
1551                         continue;
1552                 }
1553
1554                 if (spi_imx->txfifo &&
1555                     time_after(jiffies, timeout)) {
1556
1557                         dev_err_ratelimited(&spi->dev,
1558                                             "timeout period reached: jiffies: %lu- falling back to interrupt mode\n",
1559                                             jiffies - timeout);
1560
1561                         /* fall back to interrupt mode */
1562                         return spi_imx_pio_transfer(spi, transfer);
1563                 }
1564         }
1565
1566         return 0;
1567 }
1568
1569 static int spi_imx_pio_transfer_target(struct spi_device *spi,
1570                                        struct spi_transfer *transfer)
1571 {
1572         struct spi_imx_data *spi_imx = spi_controller_get_devdata(spi->controller);
1573         int ret = 0;
1574
1575         if (is_imx53_ecspi(spi_imx) &&
1576             transfer->len > MX53_MAX_TRANSFER_BYTES) {
1577                 dev_err(&spi->dev, "Transaction too big, max size is %d bytes\n",
1578                         MX53_MAX_TRANSFER_BYTES);
1579                 return -EMSGSIZE;
1580         }
1581
1582         spi_imx->tx_buf = transfer->tx_buf;
1583         spi_imx->rx_buf = transfer->rx_buf;
1584         spi_imx->count = transfer->len;
1585         spi_imx->txfifo = 0;
1586         spi_imx->remainder = 0;
1587
1588         reinit_completion(&spi_imx->xfer_done);
1589         spi_imx->target_aborted = false;
1590
1591         spi_imx_push(spi_imx);
1592
1593         spi_imx->devtype_data->intctrl(spi_imx, MXC_INT_TE | MXC_INT_RDR);
1594
1595         if (wait_for_completion_interruptible(&spi_imx->xfer_done) ||
1596             spi_imx->target_aborted) {
1597                 dev_dbg(&spi->dev, "interrupted\n");
1598                 ret = -EINTR;
1599         }
1600
1601         /* ecspi has a HW issue when works in Target mode,
1602          * after 64 words writtern to TXFIFO, even TXFIFO becomes empty,
1603          * ECSPI_TXDATA keeps shift out the last word data,
1604          * so we have to disable ECSPI when in target mode after the
1605          * transfer completes
1606          */
1607         if (spi_imx->devtype_data->disable)
1608                 spi_imx->devtype_data->disable(spi_imx);
1609
1610         return ret;
1611 }
1612
1613 static int spi_imx_transfer_one(struct spi_controller *controller,
1614                                 struct spi_device *spi,
1615                                 struct spi_transfer *transfer)
1616 {
1617         struct spi_imx_data *spi_imx = spi_controller_get_devdata(spi->controller);
1618         unsigned long hz_per_byte, byte_limit;
1619
1620         spi_imx_setupxfer(spi, transfer);
1621         transfer->effective_speed_hz = spi_imx->spi_bus_clk;
1622
1623         /* flush rxfifo before transfer */
1624         while (spi_imx->devtype_data->rx_available(spi_imx))
1625                 readl(spi_imx->base + MXC_CSPIRXDATA);
1626
1627         if (spi_imx->target_mode)
1628                 return spi_imx_pio_transfer_target(spi, transfer);
1629
1630         /*
1631          * If we decided in spi_imx_can_dma() that we want to do a DMA
1632          * transfer, the SPI transfer has already been mapped, so we
1633          * have to do the DMA transfer here.
1634          */
1635         if (spi_imx->usedma)
1636                 return spi_imx_dma_transfer(spi_imx, transfer);
1637         /*
1638          * Calculate the estimated time in us the transfer runs. Find
1639          * the number of Hz per byte per polling limit.
1640          */
1641         hz_per_byte = polling_limit_us ? ((8 + 4) * USEC_PER_SEC) / polling_limit_us : 0;
1642         byte_limit = hz_per_byte ? transfer->effective_speed_hz / hz_per_byte : 1;
1643
1644         /* run in polling mode for short transfers */
1645         if (transfer->len < byte_limit)
1646                 return spi_imx_poll_transfer(spi, transfer);
1647
1648         return spi_imx_pio_transfer(spi, transfer);
1649 }
1650
1651 static int spi_imx_setup(struct spi_device *spi)
1652 {
1653         dev_dbg(&spi->dev, "%s: mode %d, %u bpw, %d hz\n", __func__,
1654                  spi->mode, spi->bits_per_word, spi->max_speed_hz);
1655
1656         return 0;
1657 }
1658
1659 static int
1660 spi_imx_prepare_message(struct spi_controller *controller, struct spi_message *msg)
1661 {
1662         struct spi_imx_data *spi_imx = spi_controller_get_devdata(controller);
1663         int ret;
1664
1665         ret = pm_runtime_resume_and_get(spi_imx->dev);
1666         if (ret < 0) {
1667                 dev_err(spi_imx->dev, "failed to enable clock\n");
1668                 return ret;
1669         }
1670
1671         ret = spi_imx->devtype_data->prepare_message(spi_imx, msg);
1672         if (ret) {
1673                 pm_runtime_mark_last_busy(spi_imx->dev);
1674                 pm_runtime_put_autosuspend(spi_imx->dev);
1675         }
1676
1677         return ret;
1678 }
1679
1680 static int
1681 spi_imx_unprepare_message(struct spi_controller *controller, struct spi_message *msg)
1682 {
1683         struct spi_imx_data *spi_imx = spi_controller_get_devdata(controller);
1684
1685         pm_runtime_mark_last_busy(spi_imx->dev);
1686         pm_runtime_put_autosuspend(spi_imx->dev);
1687         return 0;
1688 }
1689
1690 static int spi_imx_target_abort(struct spi_controller *controller)
1691 {
1692         struct spi_imx_data *spi_imx = spi_controller_get_devdata(controller);
1693
1694         spi_imx->target_aborted = true;
1695         complete(&spi_imx->xfer_done);
1696
1697         return 0;
1698 }
1699
1700 static int spi_imx_probe(struct platform_device *pdev)
1701 {
1702         struct device_node *np = pdev->dev.of_node;
1703         struct spi_controller *controller;
1704         struct spi_imx_data *spi_imx;
1705         struct resource *res;
1706         int ret, irq, spi_drctl;
1707         const struct spi_imx_devtype_data *devtype_data =
1708                         of_device_get_match_data(&pdev->dev);
1709         bool target_mode;
1710         u32 val;
1711
1712         target_mode = devtype_data->has_targetmode &&
1713                       of_property_read_bool(np, "spi-slave");
1714         if (target_mode)
1715                 controller = spi_alloc_target(&pdev->dev,
1716                                               sizeof(struct spi_imx_data));
1717         else
1718                 controller = spi_alloc_host(&pdev->dev,
1719                                             sizeof(struct spi_imx_data));
1720         if (!controller)
1721                 return -ENOMEM;
1722
1723         ret = of_property_read_u32(np, "fsl,spi-rdy-drctl", &spi_drctl);
1724         if ((ret < 0) || (spi_drctl >= 0x3)) {
1725                 /* '11' is reserved */
1726                 spi_drctl = 0;
1727         }
1728
1729         platform_set_drvdata(pdev, controller);
1730
1731         controller->bits_per_word_mask = SPI_BPW_RANGE_MASK(1, 32);
1732         controller->bus_num = np ? -1 : pdev->id;
1733         controller->use_gpio_descriptors = true;
1734
1735         spi_imx = spi_controller_get_devdata(controller);
1736         spi_imx->controller = controller;
1737         spi_imx->dev = &pdev->dev;
1738         spi_imx->target_mode = target_mode;
1739
1740         spi_imx->devtype_data = devtype_data;
1741
1742         /*
1743          * Get number of chip selects from device properties. This can be
1744          * coming from device tree or boardfiles, if it is not defined,
1745          * a default value of 3 chip selects will be used, as all the legacy
1746          * board files have <= 3 chip selects.
1747          */
1748         if (!device_property_read_u32(&pdev->dev, "num-cs", &val))
1749                 controller->num_chipselect = val;
1750         else
1751                 controller->num_chipselect = 3;
1752
1753         controller->transfer_one = spi_imx_transfer_one;
1754         controller->setup = spi_imx_setup;
1755         controller->prepare_message = spi_imx_prepare_message;
1756         controller->unprepare_message = spi_imx_unprepare_message;
1757         controller->target_abort = spi_imx_target_abort;
1758         controller->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH | SPI_NO_CS |
1759                                 SPI_MOSI_IDLE_LOW;
1760
1761         if (is_imx35_cspi(spi_imx) || is_imx51_ecspi(spi_imx) ||
1762             is_imx53_ecspi(spi_imx))
1763                 controller->mode_bits |= SPI_LOOP | SPI_READY;
1764
1765         if (is_imx51_ecspi(spi_imx) || is_imx53_ecspi(spi_imx))
1766                 controller->mode_bits |= SPI_RX_CPHA_FLIP;
1767
1768         if (is_imx51_ecspi(spi_imx) &&
1769             device_property_read_u32(&pdev->dev, "cs-gpios", NULL))
1770                 /*
1771                  * When using HW-CS implementing SPI_CS_WORD can be done by just
1772                  * setting the burst length to the word size. This is
1773                  * considerably faster than manually controlling the CS.
1774                  */
1775                 controller->mode_bits |= SPI_CS_WORD;
1776
1777         if (is_imx51_ecspi(spi_imx) || is_imx53_ecspi(spi_imx)) {
1778                 controller->max_native_cs = 4;
1779                 controller->flags |= SPI_CONTROLLER_GPIO_SS;
1780         }
1781
1782         spi_imx->spi_drctl = spi_drctl;
1783
1784         init_completion(&spi_imx->xfer_done);
1785
1786         spi_imx->base = devm_platform_get_and_ioremap_resource(pdev, 0, &res);
1787         if (IS_ERR(spi_imx->base)) {
1788                 ret = PTR_ERR(spi_imx->base);
1789                 goto out_controller_put;
1790         }
1791         spi_imx->base_phys = res->start;
1792
1793         irq = platform_get_irq(pdev, 0);
1794         if (irq < 0) {
1795                 ret = irq;
1796                 goto out_controller_put;
1797         }
1798
1799         ret = devm_request_irq(&pdev->dev, irq, spi_imx_isr, 0,
1800                                dev_name(&pdev->dev), spi_imx);
1801         if (ret) {
1802                 dev_err(&pdev->dev, "can't get irq%d: %d\n", irq, ret);
1803                 goto out_controller_put;
1804         }
1805
1806         spi_imx->clk_ipg = devm_clk_get(&pdev->dev, "ipg");
1807         if (IS_ERR(spi_imx->clk_ipg)) {
1808                 ret = PTR_ERR(spi_imx->clk_ipg);
1809                 goto out_controller_put;
1810         }
1811
1812         spi_imx->clk_per = devm_clk_get(&pdev->dev, "per");
1813         if (IS_ERR(spi_imx->clk_per)) {
1814                 ret = PTR_ERR(spi_imx->clk_per);
1815                 goto out_controller_put;
1816         }
1817
1818         ret = clk_prepare_enable(spi_imx->clk_per);
1819         if (ret)
1820                 goto out_controller_put;
1821
1822         ret = clk_prepare_enable(spi_imx->clk_ipg);
1823         if (ret)
1824                 goto out_put_per;
1825
1826         pm_runtime_set_autosuspend_delay(spi_imx->dev, MXC_RPM_TIMEOUT);
1827         pm_runtime_use_autosuspend(spi_imx->dev);
1828         pm_runtime_get_noresume(spi_imx->dev);
1829         pm_runtime_set_active(spi_imx->dev);
1830         pm_runtime_enable(spi_imx->dev);
1831
1832         spi_imx->spi_clk = clk_get_rate(spi_imx->clk_per);
1833         /*
1834          * Only validated on i.mx35 and i.mx6 now, can remove the constraint
1835          * if validated on other chips.
1836          */
1837         if (spi_imx->devtype_data->has_dmamode) {
1838                 ret = spi_imx_sdma_init(&pdev->dev, spi_imx, controller);
1839                 if (ret == -EPROBE_DEFER)
1840                         goto out_runtime_pm_put;
1841
1842                 if (ret < 0)
1843                         dev_dbg(&pdev->dev, "dma setup error %d, use pio\n",
1844                                 ret);
1845         }
1846
1847         spi_imx->devtype_data->reset(spi_imx);
1848
1849         spi_imx->devtype_data->intctrl(spi_imx, 0);
1850
1851         controller->dev.of_node = pdev->dev.of_node;
1852         ret = spi_register_controller(controller);
1853         if (ret) {
1854                 dev_err_probe(&pdev->dev, ret, "register controller failed\n");
1855                 goto out_register_controller;
1856         }
1857
1858         pm_runtime_mark_last_busy(spi_imx->dev);
1859         pm_runtime_put_autosuspend(spi_imx->dev);
1860
1861         return ret;
1862
1863 out_register_controller:
1864         if (spi_imx->devtype_data->has_dmamode)
1865                 spi_imx_sdma_exit(spi_imx);
1866 out_runtime_pm_put:
1867         pm_runtime_dont_use_autosuspend(spi_imx->dev);
1868         pm_runtime_set_suspended(&pdev->dev);
1869         pm_runtime_disable(spi_imx->dev);
1870
1871         clk_disable_unprepare(spi_imx->clk_ipg);
1872 out_put_per:
1873         clk_disable_unprepare(spi_imx->clk_per);
1874 out_controller_put:
1875         spi_controller_put(controller);
1876
1877         return ret;
1878 }
1879
1880 static void spi_imx_remove(struct platform_device *pdev)
1881 {
1882         struct spi_controller *controller = platform_get_drvdata(pdev);
1883         struct spi_imx_data *spi_imx = spi_controller_get_devdata(controller);
1884         int ret;
1885
1886         spi_unregister_controller(controller);
1887
1888         ret = pm_runtime_get_sync(spi_imx->dev);
1889         if (ret >= 0)
1890                 writel(0, spi_imx->base + MXC_CSPICTRL);
1891         else
1892                 dev_warn(spi_imx->dev, "failed to enable clock, skip hw disable\n");
1893
1894         pm_runtime_dont_use_autosuspend(spi_imx->dev);
1895         pm_runtime_put_sync(spi_imx->dev);
1896         pm_runtime_disable(spi_imx->dev);
1897
1898         spi_imx_sdma_exit(spi_imx);
1899 }
1900
1901 static int spi_imx_runtime_resume(struct device *dev)
1902 {
1903         struct spi_controller *controller = dev_get_drvdata(dev);
1904         struct spi_imx_data *spi_imx;
1905         int ret;
1906
1907         spi_imx = spi_controller_get_devdata(controller);
1908
1909         ret = clk_prepare_enable(spi_imx->clk_per);
1910         if (ret)
1911                 return ret;
1912
1913         ret = clk_prepare_enable(spi_imx->clk_ipg);
1914         if (ret) {
1915                 clk_disable_unprepare(spi_imx->clk_per);
1916                 return ret;
1917         }
1918
1919         return 0;
1920 }
1921
1922 static int spi_imx_runtime_suspend(struct device *dev)
1923 {
1924         struct spi_controller *controller = dev_get_drvdata(dev);
1925         struct spi_imx_data *spi_imx;
1926
1927         spi_imx = spi_controller_get_devdata(controller);
1928
1929         clk_disable_unprepare(spi_imx->clk_per);
1930         clk_disable_unprepare(spi_imx->clk_ipg);
1931
1932         return 0;
1933 }
1934
1935 static int spi_imx_suspend(struct device *dev)
1936 {
1937         pinctrl_pm_select_sleep_state(dev);
1938         return 0;
1939 }
1940
1941 static int spi_imx_resume(struct device *dev)
1942 {
1943         pinctrl_pm_select_default_state(dev);
1944         return 0;
1945 }
1946
1947 static const struct dev_pm_ops imx_spi_pm = {
1948         RUNTIME_PM_OPS(spi_imx_runtime_suspend, spi_imx_runtime_resume, NULL)
1949         SYSTEM_SLEEP_PM_OPS(spi_imx_suspend, spi_imx_resume)
1950 };
1951
1952 static struct platform_driver spi_imx_driver = {
1953         .driver = {
1954                    .name = DRIVER_NAME,
1955                    .of_match_table = spi_imx_dt_ids,
1956                    .pm = pm_ptr(&imx_spi_pm),
1957         },
1958         .probe = spi_imx_probe,
1959         .remove_new = spi_imx_remove,
1960 };
1961 module_platform_driver(spi_imx_driver);
1962
1963 MODULE_DESCRIPTION("i.MX SPI Controller driver");
1964 MODULE_AUTHOR("Sascha Hauer, Pengutronix");
1965 MODULE_LICENSE("GPL");
1966 MODULE_ALIAS("platform:" DRIVER_NAME);