drivers/spi/spi-amd.c

   1 // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
   2 //
   3 // AMD SPI controller driver
   4 //
   5 // Copyright (c) 2020, Advanced Micro Devices, Inc.
   6 //
   7 // Author: Sanjay R Mehta <[email protected]>
   8
   9 #include <linux/acpi.h>
  10 #include <linux/init.h>
  11 #include <linux/module.h>
  12 #include <linux/platform_device.h>
  13 #include <linux/delay.h>
  14 #include <linux/spi/spi.h>
  15 #include <linux/iopoll.h>
  16 #include <linux/spi/spi-mem.h>
  17
  18 #define AMD_SPI_CTRL0_REG       0x00
  19 #define AMD_SPI_EXEC_CMD        BIT(16)
  20 #define AMD_SPI_FIFO_CLEAR      BIT(20)
  21 #define AMD_SPI_BUSY            BIT(31)
  22
  23 #define AMD_SPI_OPCODE_REG      0x45
  24 #define AMD_SPI_CMD_TRIGGER_REG 0x47
  25 #define AMD_SPI_TRIGGER_CMD     BIT(7)
  26
  27 #define AMD_SPI_OPCODE_MASK     0xFF
  28
  29 #define AMD_SPI_ALT_CS_REG      0x1D
  30 #define AMD_SPI_ALT_CS_MASK     0x3
  31
  32 #define AMD_SPI_FIFO_BASE       0x80
  33 #define AMD_SPI_TX_COUNT_REG    0x48
  34 #define AMD_SPI_RX_COUNT_REG    0x4B
  35 #define AMD_SPI_STATUS_REG      0x4C
  36
  37 #define AMD_SPI_FIFO_SIZE       70
  38 #define AMD_SPI_MEM_SIZE        200
  39 #define AMD_SPI_MAX_DATA        64
  40
  41 #define AMD_SPI_ENA_REG         0x20
  42 #define AMD_SPI_ALT_SPD_SHIFT   20
  43 #define AMD_SPI_ALT_SPD_MASK    GENMASK(23, AMD_SPI_ALT_SPD_SHIFT)
  44 #define AMD_SPI_SPI100_SHIFT    0
  45 #define AMD_SPI_SPI100_MASK     GENMASK(AMD_SPI_SPI100_SHIFT, AMD_SPI_SPI100_SHIFT)
  46 #define AMD_SPI_SPEED_REG       0x6C
  47 #define AMD_SPI_SPD7_SHIFT      8
  48 #define AMD_SPI_SPD7_MASK       GENMASK(13, AMD_SPI_SPD7_SHIFT)
  49
  50 #define AMD_SPI_MAX_HZ          100000000
  51 #define AMD_SPI_MIN_HZ          800000
  52
  53 /**
  54  * enum amd_spi_versions - SPI controller versions
  55  * @AMD_SPI_V1:         AMDI0061 hardware version
  56  * @AMD_SPI_V2:         AMDI0062 hardware version
  57  */
  58 enum amd_spi_versions {
  59         AMD_SPI_V1 = 1,
  60         AMD_SPI_V2,
  61 };
  62
  63 enum amd_spi_speed {
  64         F_66_66MHz,
  65         F_33_33MHz,
  66         F_22_22MHz,
  67         F_16_66MHz,
  68         F_100MHz,
  69         F_800KHz,
  70         SPI_SPD7 = 0x7,
  71         F_50MHz = 0x4,
  72         F_4MHz = 0x32,
  73         F_3_17MHz = 0x3F
  74 };
  75
  76 /**
  77  * struct amd_spi_freq - Matches device speed with values to write in regs
  78  * @speed_hz: Device frequency
  79  * @enable_val: Value to be written to "enable register"
  80  * @spd7_val: Some frequencies requires to have a value written at SPISPEED register
  81  */
  82 struct amd_spi_freq {
  83         u32 speed_hz;
  84         u32 enable_val;
  85         u32 spd7_val;
  86 };
  87
  88 /**
  89  * struct amd_spi - SPI driver instance
  90  * @io_remap_addr:      Start address of the SPI controller registers
  91  * @version:            SPI controller hardware version
  92  * @speed_hz:           Device frequency
  93  */
  94 struct amd_spi {
  95         void __iomem *io_remap_addr;
  96         enum amd_spi_versions version;
  97         unsigned int speed_hz;
  98 };
  99
 100 static inline u8 amd_spi_readreg8(struct amd_spi *amd_spi, int idx)
 101 {
 102         return ioread8((u8 __iomem *)amd_spi->io_remap_addr + idx);
 103 }
 104
 105 static inline void amd_spi_writereg8(struct amd_spi *amd_spi, int idx, u8 val)
 106 {
 107         iowrite8(val, ((u8 __iomem *)amd_spi->io_remap_addr + idx));
 108 }
 109
 110 static void amd_spi_setclear_reg8(struct amd_spi *amd_spi, int idx, u8 set, u8 clear)
 111 {
 112         u8 tmp = amd_spi_readreg8(amd_spi, idx);
 113
 114         tmp = (tmp & ~clear) | set;
 115         amd_spi_writereg8(amd_spi, idx, tmp);
 116 }
 117
 118 static inline u32 amd_spi_readreg32(struct amd_spi *amd_spi, int idx)
 119 {
 120         return ioread32((u8 __iomem *)amd_spi->io_remap_addr + idx);
 121 }
 122
 123 static inline void amd_spi_writereg32(struct amd_spi *amd_spi, int idx, u32 val)
 124 {
 125         iowrite32(val, ((u8 __iomem *)amd_spi->io_remap_addr + idx));
 126 }
 127
 128 static inline void amd_spi_setclear_reg32(struct amd_spi *amd_spi, int idx, u32 set, u32 clear)
 129 {
 130         u32 tmp = amd_spi_readreg32(amd_spi, idx);
 131
 132         tmp = (tmp & ~clear) | set;
 133         amd_spi_writereg32(amd_spi, idx, tmp);
 134 }
 135
 136 static void amd_spi_select_chip(struct amd_spi *amd_spi, u8 cs)
 137 {
 138         amd_spi_setclear_reg8(amd_spi, AMD_SPI_ALT_CS_REG, cs, AMD_SPI_ALT_CS_MASK);
 139 }
 140
 141 static inline void amd_spi_clear_chip(struct amd_spi *amd_spi, u8 chip_select)
 142 {
 143         amd_spi_writereg8(amd_spi, AMD_SPI_ALT_CS_REG, chip_select & ~AMD_SPI_ALT_CS_MASK);
 144 }
 145
 146 static void amd_spi_clear_fifo_ptr(struct amd_spi *amd_spi)
 147 {
 148         amd_spi_setclear_reg32(amd_spi, AMD_SPI_CTRL0_REG, AMD_SPI_FIFO_CLEAR, AMD_SPI_FIFO_CLEAR);
 149 }
 150
 151 static int amd_spi_set_opcode(struct amd_spi *amd_spi, u8 cmd_opcode)
 152 {
 153         switch (amd_spi->version) {
 154         case AMD_SPI_V1:
 155                 amd_spi_setclear_reg32(amd_spi, AMD_SPI_CTRL0_REG, cmd_opcode,
 156                                        AMD_SPI_OPCODE_MASK);
 157                 return 0;
 158         case AMD_SPI_V2:
 159                 amd_spi_writereg8(amd_spi, AMD_SPI_OPCODE_REG, cmd_opcode);
 160                 return 0;
 161         default:
 162                 return -ENODEV;
 163         }
 164 }
 165
 166 static inline void amd_spi_set_rx_count(struct amd_spi *amd_spi, u8 rx_count)
 167 {
 168         amd_spi_setclear_reg8(amd_spi, AMD_SPI_RX_COUNT_REG, rx_count, 0xff);
 169 }
 170
 171 static inline void amd_spi_set_tx_count(struct amd_spi *amd_spi, u8 tx_count)
 172 {
 173         amd_spi_setclear_reg8(amd_spi, AMD_SPI_TX_COUNT_REG, tx_count, 0xff);
 174 }
 175
 176 static int amd_spi_busy_wait(struct amd_spi *amd_spi)
 177 {
 178         u32 val;
 179         int reg;
 180
 181         switch (amd_spi->version) {
 182         case AMD_SPI_V1:
 183                 reg = AMD_SPI_CTRL0_REG;
 184                 break;
 185         case AMD_SPI_V2:
 186                 reg = AMD_SPI_STATUS_REG;
 187                 break;
 188         default:
 189                 return -ENODEV;
 190         }
 191
 192         return readl_poll_timeout(amd_spi->io_remap_addr + reg, val,
 193                                   !(val & AMD_SPI_BUSY), 20, 2000000);
 194 }
 195
 196 static int amd_spi_execute_opcode(struct amd_spi *amd_spi)
 197 {
 198         int ret;
 199
 200         ret = amd_spi_busy_wait(amd_spi);
 201         if (ret)
 202                 return ret;
 203
 204         switch (amd_spi->version) {
 205         case AMD_SPI_V1:
 206                 /* Set ExecuteOpCode bit in the CTRL0 register */
 207                 amd_spi_setclear_reg32(amd_spi, AMD_SPI_CTRL0_REG, AMD_SPI_EXEC_CMD,
 208                                        AMD_SPI_EXEC_CMD);
 209                 return 0;
 210         case AMD_SPI_V2:
 211                 /* Trigger the command execution */
 212                 amd_spi_setclear_reg8(amd_spi, AMD_SPI_CMD_TRIGGER_REG,
 213                                       AMD_SPI_TRIGGER_CMD, AMD_SPI_TRIGGER_CMD);
 214                 return 0;
 215         default:
 216                 return -ENODEV;
 217         }
 218 }
 219
 220 static int amd_spi_host_setup(struct spi_device *spi)
 221 {
 222         struct amd_spi *amd_spi = spi_controller_get_devdata(spi->controller);
 223
 224         amd_spi_clear_fifo_ptr(amd_spi);
 225
 226         return 0;
 227 }
 228
 229 static const struct amd_spi_freq amd_spi_freq[] = {
 230         { AMD_SPI_MAX_HZ,   F_100MHz,         0},
 231         {       66660000, F_66_66MHz,         0},
 232         {       50000000,   SPI_SPD7,   F_50MHz},
 233         {       33330000, F_33_33MHz,         0},
 234         {       22220000, F_22_22MHz,         0},
 235         {       16660000, F_16_66MHz,         0},
 236         {        4000000,   SPI_SPD7,    F_4MHz},
 237         {        3170000,   SPI_SPD7, F_3_17MHz},
 238         { AMD_SPI_MIN_HZ,   F_800KHz,         0},
 239 };
 240
 241 static int amd_set_spi_freq(struct amd_spi *amd_spi, u32 speed_hz)
 242 {
 243         unsigned int i, spd7_val, alt_spd;
 244
 245         if (speed_hz < AMD_SPI_MIN_HZ)
 246                 return -EINVAL;
 247
 248         for (i = 0; i < ARRAY_SIZE(amd_spi_freq); i++)
 249                 if (speed_hz >= amd_spi_freq[i].speed_hz)
 250                         break;
 251
 252         if (amd_spi->speed_hz == amd_spi_freq[i].speed_hz)
 253                 return 0;
 254
 255         amd_spi->speed_hz = amd_spi_freq[i].speed_hz;
 256
 257         alt_spd = (amd_spi_freq[i].enable_val << AMD_SPI_ALT_SPD_SHIFT)
 258                    & AMD_SPI_ALT_SPD_MASK;
 259         amd_spi_setclear_reg32(amd_spi, AMD_SPI_ENA_REG, alt_spd,
 260                                AMD_SPI_ALT_SPD_MASK);
 261
 262         if (amd_spi->speed_hz == AMD_SPI_MAX_HZ)
 263                 amd_spi_setclear_reg32(amd_spi, AMD_SPI_ENA_REG, 1,
 264                                        AMD_SPI_SPI100_MASK);
 265
 266         if (amd_spi_freq[i].spd7_val) {
 267                 spd7_val = (amd_spi_freq[i].spd7_val << AMD_SPI_SPD7_SHIFT)
 268                             & AMD_SPI_SPD7_MASK;
 269                 amd_spi_setclear_reg32(amd_spi, AMD_SPI_SPEED_REG, spd7_val,
 270                                        AMD_SPI_SPD7_MASK);
 271         }
 272
 273         return 0;
 274 }
 275
 276 static inline int amd_spi_fifo_xfer(struct amd_spi *amd_spi,
 277                                     struct spi_controller *host,
 278                                     struct spi_message *message)
 279 {
 280         struct spi_transfer *xfer = NULL;
 281         struct spi_device *spi = message->spi;
 282         u8 cmd_opcode = 0, fifo_pos = AMD_SPI_FIFO_BASE;
 283         u8 *buf = NULL;
 284         u32 i = 0;
 285         u32 tx_len = 0, rx_len = 0;
 286
 287         list_for_each_entry(xfer, &message->transfers,
 288                             transfer_list) {
 289                 if (xfer->speed_hz)
 290                         amd_set_spi_freq(amd_spi, xfer->speed_hz);
 291                 else
 292                         amd_set_spi_freq(amd_spi, spi->max_speed_hz);
 293
 294                 if (xfer->tx_buf) {
 295                         buf = (u8 *)xfer->tx_buf;
 296                         if (!tx_len) {
 297                                 cmd_opcode = *(u8 *)xfer->tx_buf;
 298                                 buf++;
 299                                 xfer->len--;
 300                         }
 301                         tx_len += xfer->len;
 302
 303                         /* Write data into the FIFO. */
 304                         for (i = 0; i < xfer->len; i++)
 305                                 amd_spi_writereg8(amd_spi, fifo_pos + i, buf[i]);
 306
 307                         fifo_pos += xfer->len;
 308                 }
 309
 310                 /* Store no. of bytes to be received from FIFO */
 311                 if (xfer->rx_buf)
 312                         rx_len += xfer->len;
 313         }
 314
 315         if (!buf) {
 316                 message->status = -EINVAL;
 317                 goto fin_msg;
 318         }
 319
 320         amd_spi_set_opcode(amd_spi, cmd_opcode);
 321         amd_spi_set_tx_count(amd_spi, tx_len);
 322         amd_spi_set_rx_count(amd_spi, rx_len);
 323
 324         /* Execute command */
 325         message->status = amd_spi_execute_opcode(amd_spi);
 326         if (message->status)
 327                 goto fin_msg;
 328
 329         if (rx_len) {
 330                 message->status = amd_spi_busy_wait(amd_spi);
 331                 if (message->status)
 332                         goto fin_msg;
 333
 334                 list_for_each_entry(xfer, &message->transfers, transfer_list)
 335                         if (xfer->rx_buf) {
 336                                 buf = (u8 *)xfer->rx_buf;
 337                                 /* Read data from FIFO to receive buffer */
 338                                 for (i = 0; i < xfer->len; i++)
 339                                         buf[i] = amd_spi_readreg8(amd_spi, fifo_pos + i);
 340                                 fifo_pos += xfer->len;
 341                         }
 342         }
 343
 344         /* Update statistics */
 345         message->actual_length = tx_len + rx_len + 1;
 346
 347 fin_msg:
 348         switch (amd_spi->version) {
 349         case AMD_SPI_V1:
 350                 break;
 351         case AMD_SPI_V2:
 352                 amd_spi_clear_chip(amd_spi, spi_get_chipselect(message->spi, 0));
 353                 break;
 354         default:
 355                 return -ENODEV;
 356         }
 357
 358         spi_finalize_current_message(host);
 359
 360         return message->status;
 361 }
 362
 363 static bool amd_spi_supports_op(struct spi_mem *mem,
 364                                 const struct spi_mem_op *op)
 365 {
 366         /* bus width is number of IO lines used to transmit */
 367         if (op->cmd.buswidth > 1 || op->addr.buswidth > 1 ||
 368             op->data.buswidth > 1 || op->data.nbytes > AMD_SPI_MAX_DATA)
 369                 return false;
 370
 371         return spi_mem_default_supports_op(mem, op);
 372 }
 373
 374 static int amd_spi_adjust_op_size(struct spi_mem *mem, struct spi_mem_op *op)
 375 {
 376         op->data.nbytes = clamp_val(op->data.nbytes, 0, AMD_SPI_MAX_DATA);
 377         return 0;
 378 }
 379
 380 static void amd_spi_set_addr(struct amd_spi *amd_spi,
 381                              const struct spi_mem_op *op)
 382 {
 383         u8 nbytes = op->addr.nbytes;
 384         u64 addr_val = op->addr.val;
 385         int base_addr, i;
 386
 387         base_addr = AMD_SPI_FIFO_BASE + nbytes;
 388
 389         for (i = 0; i < nbytes; i++) {
 390                 amd_spi_writereg8(amd_spi, base_addr - i - 1, addr_val &
 391                                   GENMASK(7, 0));
 392                 addr_val >>= 8;
 393         }
 394 }
 395
 396 static void amd_spi_mem_data_out(struct amd_spi *amd_spi,
 397                                  const struct spi_mem_op *op)
 398 {
 399         int base_addr = AMD_SPI_FIFO_BASE + op->addr.nbytes;
 400         u8 *buf = (u8 *)op->data.buf.out;
 401         u32 nbytes = op->data.nbytes;
 402         int i;
 403
 404         amd_spi_set_opcode(amd_spi, op->cmd.opcode);
 405         amd_spi_set_addr(amd_spi, op);
 406
 407         for (i = 0; i < nbytes; i++)
 408                 amd_spi_writereg8(amd_spi, (base_addr + i), buf[i]);
 409
 410         amd_spi_set_tx_count(amd_spi, op->addr.nbytes + op->data.nbytes);
 411         amd_spi_set_rx_count(amd_spi, 0);
 412         amd_spi_clear_fifo_ptr(amd_spi);
 413         amd_spi_execute_opcode(amd_spi);
 414 }
 415
 416 static void amd_spi_mem_data_in(struct amd_spi *amd_spi,
 417                                 const struct spi_mem_op *op)
 418 {
 419         int offset = (op->addr.nbytes == 0) ? 0 : 1;
 420         u8 *buf = (u8 *)op->data.buf.in;
 421         u32 nbytes = op->data.nbytes;
 422         int base_addr, i;
 423
 424         base_addr = AMD_SPI_FIFO_BASE + op->addr.nbytes + offset;
 425
 426         amd_spi_set_opcode(amd_spi, op->cmd.opcode);
 427         amd_spi_set_addr(amd_spi, op);
 428         amd_spi_set_tx_count(amd_spi, op->addr.nbytes);
 429         amd_spi_set_rx_count(amd_spi, op->data.nbytes + 1);
 430         amd_spi_clear_fifo_ptr(amd_spi);
 431         amd_spi_execute_opcode(amd_spi);
 432         amd_spi_busy_wait(amd_spi);
 433
 434         for (i = 0; i < nbytes; i++)
 435                 buf[i] = amd_spi_readreg8(amd_spi, base_addr + i);
 436 }
 437
 438 static int amd_spi_exec_mem_op(struct spi_mem *mem,
 439                                const struct spi_mem_op *op)
 440 {
 441         struct amd_spi *amd_spi;
 442         int ret;
 443
 444         amd_spi = spi_controller_get_devdata(mem->spi->controller);
 445
 446         ret = amd_set_spi_freq(amd_spi, mem->spi->max_speed_hz);
 447         if (ret)
 448                 return ret;
 449
 450         switch (op->data.dir) {
 451         case SPI_MEM_DATA_IN:
 452                 amd_spi_mem_data_in(amd_spi, op);
 453                 break;
 454         case SPI_MEM_DATA_OUT:
 455                 fallthrough;
 456         case SPI_MEM_NO_DATA:
 457                 amd_spi_mem_data_out(amd_spi, op);
 458                 break;
 459         default:
 460                 ret = -EOPNOTSUPP;
 461         }
 462
 463         return ret;
 464 }
 465
 466 static const struct spi_controller_mem_ops amd_spi_mem_ops = {
 467         .exec_op = amd_spi_exec_mem_op,
 468         .adjust_op_size = amd_spi_adjust_op_size,
 469         .supports_op = amd_spi_supports_op,
 470 };
 471
 472 static int amd_spi_host_transfer(struct spi_controller *host,
 473                                    struct spi_message *msg)
 474 {
 475         struct amd_spi *amd_spi = spi_controller_get_devdata(host);
 476         struct spi_device *spi = msg->spi;
 477
 478         amd_spi_select_chip(amd_spi, spi_get_chipselect(spi, 0));
 479
 480         /*
 481          * Extract spi_transfers from the spi message and
 482          * program the controller.
 483          */
 484         return amd_spi_fifo_xfer(amd_spi, host, msg);
 485 }
 486
 487 static size_t amd_spi_max_transfer_size(struct spi_device *spi)
 488 {
 489         return AMD_SPI_FIFO_SIZE;
 490 }
 491
 492 static int amd_spi_probe(struct platform_device *pdev)
 493 {
 494         struct device *dev = &pdev->dev;
 495         struct spi_controller *host;
 496         struct amd_spi *amd_spi;
 497         int err;
 498
 499         /* Allocate storage for host and driver private data */
 500         host = devm_spi_alloc_host(dev, sizeof(struct amd_spi));
 501         if (!host)
 502                 return dev_err_probe(dev, -ENOMEM, "Error allocating SPI host\n");
 503
 504         amd_spi = spi_controller_get_devdata(host);
 505         amd_spi->io_remap_addr = devm_platform_ioremap_resource(pdev, 0);
 506         if (IS_ERR(amd_spi->io_remap_addr))
 507                 return dev_err_probe(dev, PTR_ERR(amd_spi->io_remap_addr),
 508                                      "ioremap of SPI registers failed\n");
 509
 510         dev_dbg(dev, "io_remap_address: %p\n", amd_spi->io_remap_addr);
 511
 512         amd_spi->version = (uintptr_t) device_get_match_data(dev);
 513
 514         /* Initialize the spi_controller fields */
 515         host->bus_num = 0;
 516         host->num_chipselect = 4;
 517         host->mode_bits = 0;
 518         host->flags = SPI_CONTROLLER_HALF_DUPLEX;
 519         host->max_speed_hz = AMD_SPI_MAX_HZ;
 520         host->min_speed_hz = AMD_SPI_MIN_HZ;
 521         host->setup = amd_spi_host_setup;
 522         host->transfer_one_message = amd_spi_host_transfer;
 523         host->mem_ops = &amd_spi_mem_ops;
 524         host->max_transfer_size = amd_spi_max_transfer_size;
 525         host->max_message_size = amd_spi_max_transfer_size;
 526
 527         /* Register the controller with SPI framework */
 528         err = devm_spi_register_controller(dev, host);
 529         if (err)
 530                 return dev_err_probe(dev, err, "error registering SPI controller\n");
 531
 532         return 0;
 533 }
 534
 535 #ifdef CONFIG_ACPI
 536 static const struct acpi_device_id spi_acpi_match[] = {
 537         { "AMDI0061", AMD_SPI_V1 },
 538         { "AMDI0062", AMD_SPI_V2 },
 539         {},
 540 };
 541 MODULE_DEVICE_TABLE(acpi, spi_acpi_match);
 542 #endif
 543
 544 static struct platform_driver amd_spi_driver = {
 545         .driver = {
 546                 .name = "amd_spi",
 547                 .acpi_match_table = ACPI_PTR(spi_acpi_match),
 548         },
 549         .probe = amd_spi_probe,
 550 };
 551
 552 module_platform_driver(amd_spi_driver);
 553
 554 MODULE_LICENSE("Dual BSD/GPL");
 555 MODULE_AUTHOR("Sanjay Mehta <[email protected]>");
 556 MODULE_DESCRIPTION("AMD SPI Master Controller Driver");