drivers/hwtracing/coresight/coresight-stm.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Copyright (c) 2015-2016, The Linux Foundation. All rights reserved.
   4  *
   5  * Description: CoreSight System Trace Macrocell driver
   6  *
   7  * Initial implementation by Pratik Patel
   8  * (C) 2014-2015 Pratik Patel <[email protected]>
   9  *
  10  * Serious refactoring, code cleanup and upgrading to the Coresight upstream
  11  * framework by Mathieu Poirier
  12  * (C) 2015-2016 Mathieu Poirier <[email protected]>
  13  *
  14  * Guaranteed timing and support for various packet type coming from the
  15  * generic STM API by Chunyan Zhang
  16  * (C) 2015-2016 Chunyan Zhang <[email protected]>
  17  */
  18 #include <asm/local.h>
  19 #include <linux/acpi.h>
  20 #include <linux/amba/bus.h>
  21 #include <linux/bitmap.h>
  22 #include <linux/clk.h>
  23 #include <linux/coresight.h>
  24 #include <linux/coresight-stm.h>
  25 #include <linux/err.h>
  26 #include <linux/kernel.h>
  27 #include <linux/moduleparam.h>
  28 #include <linux/of_address.h>
  29 #include <linux/perf_event.h>
  30 #include <linux/pm_runtime.h>
  31 #include <linux/stm.h>
  32 #include <linux/platform_device.h>
  33
  34 #include "coresight-priv.h"
  35 #include "coresight-trace-id.h"
  36
  37 #define STMDMASTARTR                    0xc04
  38 #define STMDMASTOPR                     0xc08
  39 #define STMDMASTATR                     0xc0c
  40 #define STMDMACTLR                      0xc10
  41 #define STMDMAIDR                       0xcfc
  42 #define STMHEER                         0xd00
  43 #define STMHETER                        0xd20
  44 #define STMHEBSR                        0xd60
  45 #define STMHEMCR                        0xd64
  46 #define STMHEMASTR                      0xdf4
  47 #define STMHEFEAT1R                     0xdf8
  48 #define STMHEIDR                        0xdfc
  49 #define STMSPER                         0xe00
  50 #define STMSPTER                        0xe20
  51 #define STMPRIVMASKR                    0xe40
  52 #define STMSPSCR                        0xe60
  53 #define STMSPMSCR                       0xe64
  54 #define STMSPOVERRIDER                  0xe68
  55 #define STMSPMOVERRIDER                 0xe6c
  56 #define STMSPTRIGCSR                    0xe70
  57 #define STMTCSR                         0xe80
  58 #define STMTSSTIMR                      0xe84
  59 #define STMTSFREQR                      0xe8c
  60 #define STMSYNCR                        0xe90
  61 #define STMAUXCR                        0xe94
  62 #define STMSPFEAT1R                     0xea0
  63 #define STMSPFEAT2R                     0xea4
  64 #define STMSPFEAT3R                     0xea8
  65 #define STMITTRIGGER                    0xee8
  66 #define STMITATBDATA0                   0xeec
  67 #define STMITATBCTR2                    0xef0
  68 #define STMITATBID                      0xef4
  69 #define STMITATBCTR0                    0xef8
  70
  71 #define STM_32_CHANNEL                  32
  72 #define BYTES_PER_CHANNEL               256
  73 #define STM_TRACE_BUF_SIZE              4096
  74 #define STM_SW_MASTER_END               127
  75
  76 /* Register bit definition */
  77 #define STMTCSR_BUSY_BIT                23
  78 /* Reserve the first 10 channels for kernel usage */
  79 #define STM_CHANNEL_OFFSET              0
  80
  81 enum stm_pkt_type {
  82         STM_PKT_TYPE_DATA       = 0x98,
  83         STM_PKT_TYPE_FLAG       = 0xE8,
  84         STM_PKT_TYPE_TRIG       = 0xF8,
  85 };
  86
  87 #define stm_channel_addr(drvdata, ch)   (drvdata->chs.base +    \
  88                                         (ch * BYTES_PER_CHANNEL))
  89 #define stm_channel_off(type, opts)     (type & ~opts)
  90
  91 static int boot_nr_channel;
  92
  93 /*
  94  * Not really modular but using module_param is the easiest way to
  95  * remain consistent with existing use cases for now.
  96  */
  97 module_param_named(
  98         boot_nr_channel, boot_nr_channel, int, S_IRUGO
  99 );
 100
 101 /*
 102  * struct channel_space - central management entity for extended ports
 103  * @base:               memory mapped base address where channels start.
 104  * @phys:               physical base address of channel region.
 105  * @guaraneed:          is the channel delivery guaranteed.
 106  */
 107 struct channel_space {
 108         void __iomem            *base;
 109         phys_addr_t             phys;
 110         unsigned long           *guaranteed;
 111 };
 112
 113 DEFINE_CORESIGHT_DEVLIST(stm_devs, "stm");
 114
 115 /**
 116  * struct stm_drvdata - specifics associated to an STM component
 117  * @base:               memory mapped base address for this component.
 118  * @atclk:              optional clock for the core parts of the STM.
 119  * @pclk:               APB clock if present, otherwise NULL
 120  * @csdev:              component vitals needed by the framework.
 121  * @spinlock:           only one at a time pls.
 122  * @chs:                the channels accociated to this STM.
 123  * @stm:                structure associated to the generic STM interface.
 124  * @traceid:            value of the current ID for this component.
 125  * @write_bytes:        Maximus bytes this STM can write at a time.
 126  * @stmsper:            settings for register STMSPER.
 127  * @stmspscr:           settings for register STMSPSCR.
 128  * @numsp:              the total number of stimulus port support by this STM.
 129  * @stmheer:            settings for register STMHEER.
 130  * @stmheter:           settings for register STMHETER.
 131  * @stmhebsr:           settings for register STMHEBSR.
 132  */
 133 struct stm_drvdata {
 134         void __iomem            *base;
 135         struct clk              *atclk;
 136         struct clk              *pclk;
 137         struct coresight_device *csdev;
 138         spinlock_t              spinlock;
 139         struct channel_space    chs;
 140         struct stm_data         stm;
 141         u8                      traceid;
 142         u32                     write_bytes;
 143         u32                     stmsper;
 144         u32                     stmspscr;
 145         u32                     numsp;
 146         u32                     stmheer;
 147         u32                     stmheter;
 148         u32                     stmhebsr;
 149 };
 150
 151 static void stm_hwevent_enable_hw(struct stm_drvdata *drvdata)
 152 {
 153         CS_UNLOCK(drvdata->base);
 154
 155         writel_relaxed(drvdata->stmhebsr, drvdata->base + STMHEBSR);
 156         writel_relaxed(drvdata->stmheter, drvdata->base + STMHETER);
 157         writel_relaxed(drvdata->stmheer, drvdata->base + STMHEER);
 158         writel_relaxed(0x01 |   /* Enable HW event tracing */
 159                        0x04,    /* Error detection on event tracing */
 160                        drvdata->base + STMHEMCR);
 161
 162         CS_LOCK(drvdata->base);
 163 }
 164
 165 static void stm_port_enable_hw(struct stm_drvdata *drvdata)
 166 {
 167         CS_UNLOCK(drvdata->base);
 168         /* ATB trigger enable on direct writes to TRIG locations */
 169         writel_relaxed(0x10,
 170                        drvdata->base + STMSPTRIGCSR);
 171         writel_relaxed(drvdata->stmspscr, drvdata->base + STMSPSCR);
 172         writel_relaxed(drvdata->stmsper, drvdata->base + STMSPER);
 173
 174         CS_LOCK(drvdata->base);
 175 }
 176
 177 static void stm_enable_hw(struct stm_drvdata *drvdata)
 178 {
 179         if (drvdata->stmheer)
 180                 stm_hwevent_enable_hw(drvdata);
 181
 182         stm_port_enable_hw(drvdata);
 183
 184         CS_UNLOCK(drvdata->base);
 185
 186         /* 4096 byte between synchronisation packets */
 187         writel_relaxed(0xFFF, drvdata->base + STMSYNCR);
 188         writel_relaxed((drvdata->traceid << 16 | /* trace id */
 189                         0x02 |                   /* timestamp enable */
 190                         0x01),                   /* global STM enable */
 191                         drvdata->base + STMTCSR);
 192
 193         CS_LOCK(drvdata->base);
 194 }
 195
 196 static int stm_enable(struct coresight_device *csdev, struct perf_event *event,
 197                       enum cs_mode mode)
 198 {
 199         struct stm_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent);
 200
 201         if (mode != CS_MODE_SYSFS)
 202                 return -EINVAL;
 203
 204         if (!coresight_take_mode(csdev, mode)) {
 205                 /* Someone is already using the tracer */
 206                 return -EBUSY;
 207         }
 208
 209         pm_runtime_get_sync(csdev->dev.parent);
 210
 211         spin_lock(&drvdata->spinlock);
 212         stm_enable_hw(drvdata);
 213         spin_unlock(&drvdata->spinlock);
 214
 215         dev_dbg(&csdev->dev, "STM tracing enabled\n");
 216         return 0;
 217 }
 218
 219 static void stm_hwevent_disable_hw(struct stm_drvdata *drvdata)
 220 {
 221         CS_UNLOCK(drvdata->base);
 222
 223         writel_relaxed(0x0, drvdata->base + STMHEMCR);
 224         writel_relaxed(0x0, drvdata->base + STMHEER);
 225         writel_relaxed(0x0, drvdata->base + STMHETER);
 226
 227         CS_LOCK(drvdata->base);
 228 }
 229
 230 static void stm_port_disable_hw(struct stm_drvdata *drvdata)
 231 {
 232         CS_UNLOCK(drvdata->base);
 233
 234         writel_relaxed(0x0, drvdata->base + STMSPER);
 235         writel_relaxed(0x0, drvdata->base + STMSPTRIGCSR);
 236
 237         CS_LOCK(drvdata->base);
 238 }
 239
 240 static void stm_disable_hw(struct stm_drvdata *drvdata)
 241 {
 242         u32 val;
 243
 244         CS_UNLOCK(drvdata->base);
 245
 246         val = readl_relaxed(drvdata->base + STMTCSR);
 247         val &= ~0x1; /* clear global STM enable [0] */
 248         writel_relaxed(val, drvdata->base + STMTCSR);
 249
 250         CS_LOCK(drvdata->base);
 251
 252         stm_port_disable_hw(drvdata);
 253         if (drvdata->stmheer)
 254                 stm_hwevent_disable_hw(drvdata);
 255 }
 256
 257 static void stm_disable(struct coresight_device *csdev,
 258                         struct perf_event *event)
 259 {
 260         struct stm_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent);
 261         struct csdev_access *csa = &csdev->access;
 262
 263         /*
 264          * For as long as the tracer isn't disabled another entity can't
 265          * change its status.  As such we can read the status here without
 266          * fearing it will change under us.
 267          */
 268         if (coresight_get_mode(csdev) == CS_MODE_SYSFS) {
 269                 spin_lock(&drvdata->spinlock);
 270                 stm_disable_hw(drvdata);
 271                 spin_unlock(&drvdata->spinlock);
 272
 273                 /* Wait until the engine has completely stopped */
 274                 coresight_timeout(csa, STMTCSR, STMTCSR_BUSY_BIT, 0);
 275
 276                 pm_runtime_put(csdev->dev.parent);
 277
 278                 coresight_set_mode(csdev, CS_MODE_DISABLED);
 279                 dev_dbg(&csdev->dev, "STM tracing disabled\n");
 280         }
 281 }
 282
 283 static const struct coresight_ops_source stm_source_ops = {
 284         .enable         = stm_enable,
 285         .disable        = stm_disable,
 286 };
 287
 288 static const struct coresight_ops stm_cs_ops = {
 289         .source_ops     = &stm_source_ops,
 290 };
 291
 292 static inline bool stm_addr_unaligned(const void *addr, u8 write_bytes)
 293 {
 294         return ((unsigned long)addr & (write_bytes - 1));
 295 }
 296
 297 static void stm_send(void __iomem *addr, const void *data,
 298                      u32 size, u8 write_bytes)
 299 {
 300         u8 paload[8];
 301
 302         if (stm_addr_unaligned(data, write_bytes)) {
 303                 memcpy(paload, data, size);
 304                 data = paload;
 305         }
 306
 307         /* now we are 64bit/32bit aligned */
 308         switch (size) {
 309 #ifdef CONFIG_64BIT
 310         case 8:
 311                 writeq_relaxed(*(u64 *)data, addr);
 312                 break;
 313 #endif
 314         case 4:
 315                 writel_relaxed(*(u32 *)data, addr);
 316                 break;
 317         case 2:
 318                 writew_relaxed(*(u16 *)data, addr);
 319                 break;
 320         case 1:
 321                 writeb_relaxed(*(u8 *)data, addr);
 322                 break;
 323         default:
 324                 break;
 325         }
 326 }
 327
 328 static int stm_generic_link(struct stm_data *stm_data,
 329                             unsigned int master,  unsigned int channel)
 330 {
 331         struct stm_drvdata *drvdata = container_of(stm_data,
 332                                                    struct stm_drvdata, stm);
 333         if (!drvdata || !drvdata->csdev)
 334                 return -EINVAL;
 335
 336         return coresight_enable_sysfs(drvdata->csdev);
 337 }
 338
 339 static void stm_generic_unlink(struct stm_data *stm_data,
 340                                unsigned int master,  unsigned int channel)
 341 {
 342         struct stm_drvdata *drvdata = container_of(stm_data,
 343                                                    struct stm_drvdata, stm);
 344         if (!drvdata || !drvdata->csdev)
 345                 return;
 346
 347         coresight_disable_sysfs(drvdata->csdev);
 348 }
 349
 350 static phys_addr_t
 351 stm_mmio_addr(struct stm_data *stm_data, unsigned int master,
 352               unsigned int channel, unsigned int nr_chans)
 353 {
 354         struct stm_drvdata *drvdata = container_of(stm_data,
 355                                                    struct stm_drvdata, stm);
 356         phys_addr_t addr;
 357
 358         addr = drvdata->chs.phys + channel * BYTES_PER_CHANNEL;
 359
 360         if (offset_in_page(addr) ||
 361             offset_in_page(nr_chans * BYTES_PER_CHANNEL))
 362                 return 0;
 363
 364         return addr;
 365 }
 366
 367 static long stm_generic_set_options(struct stm_data *stm_data,
 368                                     unsigned int master,
 369                                     unsigned int channel,
 370                                     unsigned int nr_chans,
 371                                     unsigned long options)
 372 {
 373         struct stm_drvdata *drvdata = container_of(stm_data,
 374                                                    struct stm_drvdata, stm);
 375         if (!(drvdata && coresight_get_mode(drvdata->csdev)))
 376                 return -EINVAL;
 377
 378         if (channel >= drvdata->numsp)
 379                 return -EINVAL;
 380
 381         switch (options) {
 382         case STM_OPTION_GUARANTEED:
 383                 set_bit(channel, drvdata->chs.guaranteed);
 384                 break;
 385
 386         case STM_OPTION_INVARIANT:
 387                 clear_bit(channel, drvdata->chs.guaranteed);
 388                 break;
 389
 390         default:
 391                 return -EINVAL;
 392         }
 393
 394         return 0;
 395 }
 396
 397 static ssize_t notrace stm_generic_packet(struct stm_data *stm_data,
 398                                   unsigned int master,
 399                                   unsigned int channel,
 400                                   unsigned int packet,
 401                                   unsigned int flags,
 402                                   unsigned int size,
 403                                   const unsigned char *payload)
 404 {
 405         void __iomem *ch_addr;
 406         struct stm_drvdata *drvdata = container_of(stm_data,
 407                                                    struct stm_drvdata, stm);
 408         unsigned int stm_flags;
 409
 410         if (!(drvdata && coresight_get_mode(drvdata->csdev)))
 411                 return -EACCES;
 412
 413         if (channel >= drvdata->numsp)
 414                 return -EINVAL;
 415
 416         ch_addr = stm_channel_addr(drvdata, channel);
 417
 418         stm_flags = (flags & STP_PACKET_TIMESTAMPED) ?
 419                         STM_FLAG_TIMESTAMPED : 0;
 420         stm_flags |= test_bit(channel, drvdata->chs.guaranteed) ?
 421                            STM_FLAG_GUARANTEED : 0;
 422
 423         if (size > drvdata->write_bytes)
 424                 size = drvdata->write_bytes;
 425         else
 426                 size = rounddown_pow_of_two(size);
 427
 428         switch (packet) {
 429         case STP_PACKET_FLAG:
 430                 ch_addr += stm_channel_off(STM_PKT_TYPE_FLAG, stm_flags);
 431
 432                 /*
 433                  * The generic STM core sets a size of '0' on flag packets.
 434                  * As such send a flag packet of size '1' and tell the
 435                  * core we did so.
 436                  */
 437                 stm_send(ch_addr, payload, 1, drvdata->write_bytes);
 438                 size = 1;
 439                 break;
 440
 441         case STP_PACKET_DATA:
 442                 stm_flags |= (flags & STP_PACKET_MARKED) ? STM_FLAG_MARKED : 0;
 443                 ch_addr += stm_channel_off(STM_PKT_TYPE_DATA, stm_flags);
 444                 stm_send(ch_addr, payload, size,
 445                                 drvdata->write_bytes);
 446                 break;
 447
 448         default:
 449                 return -ENOTSUPP;
 450         }
 451
 452         return size;
 453 }
 454
 455 static ssize_t hwevent_enable_show(struct device *dev,
 456                                    struct device_attribute *attr, char *buf)
 457 {
 458         struct stm_drvdata *drvdata = dev_get_drvdata(dev->parent);
 459         unsigned long val = drvdata->stmheer;
 460
 461         return scnprintf(buf, PAGE_SIZE, "%#lx\n", val);
 462 }
 463
 464 static ssize_t hwevent_enable_store(struct device *dev,
 465                                     struct device_attribute *attr,
 466                                     const char *buf, size_t size)
 467 {
 468         struct stm_drvdata *drvdata = dev_get_drvdata(dev->parent);
 469         unsigned long val;
 470         int ret = 0;
 471
 472         ret = kstrtoul(buf, 16, &val);
 473         if (ret)
 474                 return -EINVAL;
 475
 476         drvdata->stmheer = val;
 477         /* HW event enable and trigger go hand in hand */
 478         drvdata->stmheter = val;
 479
 480         return size;
 481 }
 482 static DEVICE_ATTR_RW(hwevent_enable);
 483
 484 static ssize_t hwevent_select_show(struct device *dev,
 485                                    struct device_attribute *attr, char *buf)
 486 {
 487         struct stm_drvdata *drvdata = dev_get_drvdata(dev->parent);
 488         unsigned long val = drvdata->stmhebsr;
 489
 490         return scnprintf(buf, PAGE_SIZE, "%#lx\n", val);
 491 }
 492
 493 static ssize_t hwevent_select_store(struct device *dev,
 494                                     struct device_attribute *attr,
 495                                     const char *buf, size_t size)
 496 {
 497         struct stm_drvdata *drvdata = dev_get_drvdata(dev->parent);
 498         unsigned long val;
 499         int ret = 0;
 500
 501         ret = kstrtoul(buf, 16, &val);
 502         if (ret)
 503                 return -EINVAL;
 504
 505         drvdata->stmhebsr = val;
 506
 507         return size;
 508 }
 509 static DEVICE_ATTR_RW(hwevent_select);
 510
 511 static ssize_t port_select_show(struct device *dev,
 512                                 struct device_attribute *attr, char *buf)
 513 {
 514         struct stm_drvdata *drvdata = dev_get_drvdata(dev->parent);
 515         unsigned long val;
 516
 517         if (!coresight_get_mode(drvdata->csdev)) {
 518                 val = drvdata->stmspscr;
 519         } else {
 520                 spin_lock(&drvdata->spinlock);
 521                 val = readl_relaxed(drvdata->base + STMSPSCR);
 522                 spin_unlock(&drvdata->spinlock);
 523         }
 524
 525         return scnprintf(buf, PAGE_SIZE, "%#lx\n", val);
 526 }
 527
 528 static ssize_t port_select_store(struct device *dev,
 529                                  struct device_attribute *attr,
 530                                  const char *buf, size_t size)
 531 {
 532         struct stm_drvdata *drvdata = dev_get_drvdata(dev->parent);
 533         unsigned long val, stmsper;
 534         int ret = 0;
 535
 536         ret = kstrtoul(buf, 16, &val);
 537         if (ret)
 538                 return ret;
 539
 540         spin_lock(&drvdata->spinlock);
 541         drvdata->stmspscr = val;
 542
 543         if (coresight_get_mode(drvdata->csdev)) {
 544                 CS_UNLOCK(drvdata->base);
 545                 /* Process as per ARM's TRM recommendation */
 546                 stmsper = readl_relaxed(drvdata->base + STMSPER);
 547                 writel_relaxed(0x0, drvdata->base + STMSPER);
 548                 writel_relaxed(drvdata->stmspscr, drvdata->base + STMSPSCR);
 549                 writel_relaxed(stmsper, drvdata->base + STMSPER);
 550                 CS_LOCK(drvdata->base);
 551         }
 552         spin_unlock(&drvdata->spinlock);
 553
 554         return size;
 555 }
 556 static DEVICE_ATTR_RW(port_select);
 557
 558 static ssize_t port_enable_show(struct device *dev,
 559                                 struct device_attribute *attr, char *buf)
 560 {
 561         struct stm_drvdata *drvdata = dev_get_drvdata(dev->parent);
 562         unsigned long val;
 563
 564         if (!coresight_get_mode(drvdata->csdev)) {
 565                 val = drvdata->stmsper;
 566         } else {
 567                 spin_lock(&drvdata->spinlock);
 568                 val = readl_relaxed(drvdata->base + STMSPER);
 569                 spin_unlock(&drvdata->spinlock);
 570         }
 571
 572         return scnprintf(buf, PAGE_SIZE, "%#lx\n", val);
 573 }
 574
 575 static ssize_t port_enable_store(struct device *dev,
 576                                  struct device_attribute *attr,
 577                                  const char *buf, size_t size)
 578 {
 579         struct stm_drvdata *drvdata = dev_get_drvdata(dev->parent);
 580         unsigned long val;
 581         int ret = 0;
 582
 583         ret = kstrtoul(buf, 16, &val);
 584         if (ret)
 585                 return ret;
 586
 587         spin_lock(&drvdata->spinlock);
 588         drvdata->stmsper = val;
 589
 590         if (coresight_get_mode(drvdata->csdev)) {
 591                 CS_UNLOCK(drvdata->base);
 592                 writel_relaxed(drvdata->stmsper, drvdata->base + STMSPER);
 593                 CS_LOCK(drvdata->base);
 594         }
 595         spin_unlock(&drvdata->spinlock);
 596
 597         return size;
 598 }
 599 static DEVICE_ATTR_RW(port_enable);
 600
 601 static ssize_t traceid_show(struct device *dev,
 602                             struct device_attribute *attr, char *buf)
 603 {
 604         unsigned long val;
 605         struct stm_drvdata *drvdata = dev_get_drvdata(dev->parent);
 606
 607         val = drvdata->traceid;
 608         return sprintf(buf, "%#lx\n", val);
 609 }
 610 static DEVICE_ATTR_RO(traceid);
 611
 612 static struct attribute *coresight_stm_attrs[] = {
 613         &dev_attr_hwevent_enable.attr,
 614         &dev_attr_hwevent_select.attr,
 615         &dev_attr_port_enable.attr,
 616         &dev_attr_port_select.attr,
 617         &dev_attr_traceid.attr,
 618         NULL,
 619 };
 620
 621 static struct attribute *coresight_stm_mgmt_attrs[] = {
 622         coresight_simple_reg32(tcsr, STMTCSR),
 623         coresight_simple_reg32(tsfreqr, STMTSFREQR),
 624         coresight_simple_reg32(syncr, STMSYNCR),
 625         coresight_simple_reg32(sper, STMSPER),
 626         coresight_simple_reg32(spter, STMSPTER),
 627         coresight_simple_reg32(privmaskr, STMPRIVMASKR),
 628         coresight_simple_reg32(spscr, STMSPSCR),
 629         coresight_simple_reg32(spmscr, STMSPMSCR),
 630         coresight_simple_reg32(spfeat1r, STMSPFEAT1R),
 631         coresight_simple_reg32(spfeat2r, STMSPFEAT2R),
 632         coresight_simple_reg32(spfeat3r, STMSPFEAT3R),
 633         coresight_simple_reg32(devid, CORESIGHT_DEVID),
 634         NULL,
 635 };
 636
 637 static const struct attribute_group coresight_stm_group = {
 638         .attrs = coresight_stm_attrs,
 639 };
 640
 641 static const struct attribute_group coresight_stm_mgmt_group = {
 642         .attrs = coresight_stm_mgmt_attrs,
 643         .name = "mgmt",
 644 };
 645
 646 static const struct attribute_group *coresight_stm_groups[] = {
 647         &coresight_stm_group,
 648         &coresight_stm_mgmt_group,
 649         NULL,
 650 };
 651
 652 #ifdef CONFIG_OF
 653 static int of_stm_get_stimulus_area(struct device *dev, struct resource *res)
 654 {
 655         const char *name = NULL;
 656         int index = 0, found = 0;
 657         struct device_node *np = dev->of_node;
 658
 659         while (!of_property_read_string_index(np, "reg-names", index, &name)) {
 660                 if (strcmp("stm-stimulus-base", name)) {
 661                         index++;
 662                         continue;
 663                 }
 664
 665                 /* We have a match and @index is where it's at */
 666                 found = 1;
 667                 break;
 668         }
 669
 670         if (!found)
 671                 return -EINVAL;
 672
 673         return of_address_to_resource(np, index, res);
 674 }
 675 #else
 676 static inline int of_stm_get_stimulus_area(struct device *dev,
 677                                            struct resource *res)
 678 {
 679         return -ENOENT;
 680 }
 681 #endif
 682
 683 #ifdef CONFIG_ACPI
 684 static int acpi_stm_get_stimulus_area(struct device *dev, struct resource *res)
 685 {
 686         int rc;
 687         bool found_base = false;
 688         struct resource_entry *rent;
 689         LIST_HEAD(res_list);
 690
 691         struct acpi_device *adev = ACPI_COMPANION(dev);
 692
 693         rc = acpi_dev_get_resources(adev, &res_list, NULL, NULL);
 694         if (rc < 0)
 695                 return rc;
 696
 697         /*
 698          * The stimulus base for STM device must be listed as the second memory
 699          * resource, followed by the programming base address as described in
 700          * "Section 2.3 Resources" in ACPI for CoreSightTM 1.0 Platform Design
 701          * document (DEN0067).
 702          */
 703         rc = -ENOENT;
 704         list_for_each_entry(rent, &res_list, node) {
 705                 if (resource_type(rent->res) != IORESOURCE_MEM)
 706                         continue;
 707                 if (found_base) {
 708                         *res = *rent->res;
 709                         rc = 0;
 710                         break;
 711                 }
 712
 713                 found_base = true;
 714         }
 715
 716         acpi_dev_free_resource_list(&res_list);
 717         return rc;
 718 }
 719 #else
 720 static inline int acpi_stm_get_stimulus_area(struct device *dev,
 721                                              struct resource *res)
 722 {
 723         return -ENOENT;
 724 }
 725 #endif
 726
 727 static int stm_get_stimulus_area(struct device *dev, struct resource *res)
 728 {
 729         struct fwnode_handle *fwnode = dev_fwnode(dev);
 730
 731         if (is_of_node(fwnode))
 732                 return of_stm_get_stimulus_area(dev, res);
 733         else if (is_acpi_node(fwnode))
 734                 return acpi_stm_get_stimulus_area(dev, res);
 735         return -ENOENT;
 736 }
 737
 738 static u32 stm_fundamental_data_size(struct stm_drvdata *drvdata)
 739 {
 740         u32 stmspfeat2r;
 741
 742         if (!IS_ENABLED(CONFIG_64BIT))
 743                 return 4;
 744
 745         stmspfeat2r = readl_relaxed(drvdata->base + STMSPFEAT2R);
 746
 747         /*
 748          * bit[15:12] represents the fundamental data size
 749          * 0 - 32-bit data
 750          * 1 - 64-bit data
 751          */
 752         return BMVAL(stmspfeat2r, 12, 15) ? 8 : 4;
 753 }
 754
 755 static u32 stm_num_stimulus_port(struct stm_drvdata *drvdata)
 756 {
 757         u32 numsp;
 758
 759         numsp = readl_relaxed(drvdata->base + CORESIGHT_DEVID);
 760         /*
 761          * NUMPS in STMDEVID is 17 bit long and if equal to 0x0,
 762          * 32 stimulus ports are supported.
 763          */
 764         numsp &= 0x1ffff;
 765         if (!numsp)
 766                 numsp = STM_32_CHANNEL;
 767         return numsp;
 768 }
 769
 770 static void stm_init_default_data(struct stm_drvdata *drvdata)
 771 {
 772         /* Don't use port selection */
 773         drvdata->stmspscr = 0x0;
 774         /*
 775          * Enable all channel regardless of their number.  When port
 776          * selection isn't used (see above) STMSPER applies to all
 777          * 32 channel group available, hence setting all 32 bits to 1
 778          */
 779         drvdata->stmsper = ~0x0;
 780
 781         /* Set invariant transaction timing on all channels */
 782         bitmap_clear(drvdata->chs.guaranteed, 0, drvdata->numsp);
 783 }
 784
 785 static void stm_init_generic_data(struct stm_drvdata *drvdata,
 786                                   const char *name)
 787 {
 788         drvdata->stm.name = name;
 789
 790         /*
 791          * MasterIDs are assigned at HW design phase. As such the core is
 792          * using a single master for interaction with this device.
 793          */
 794         drvdata->stm.sw_start = 1;
 795         drvdata->stm.sw_end = 1;
 796         drvdata->stm.hw_override = true;
 797         drvdata->stm.sw_nchannels = drvdata->numsp;
 798         drvdata->stm.sw_mmiosz = BYTES_PER_CHANNEL;
 799         drvdata->stm.packet = stm_generic_packet;
 800         drvdata->stm.mmio_addr = stm_mmio_addr;
 801         drvdata->stm.link = stm_generic_link;
 802         drvdata->stm.unlink = stm_generic_unlink;
 803         drvdata->stm.set_options = stm_generic_set_options;
 804 }
 805
 806 static const struct amba_id stm_ids[];
 807
 808 static char *stm_csdev_name(struct coresight_device *csdev)
 809 {
 810         u32 stm_pid = coresight_get_pid(&csdev->access);
 811         void *uci_data = coresight_get_uci_data_from_amba(stm_ids, stm_pid);
 812
 813         return uci_data ? (char *)uci_data : "STM";
 814 }
 815
 816 static int __stm_probe(struct device *dev, struct resource *res)
 817 {
 818         int ret, trace_id;
 819         void __iomem *base;
 820         struct coresight_platform_data *pdata = NULL;
 821         struct stm_drvdata *drvdata;
 822         struct resource ch_res;
 823         struct coresight_desc desc = { 0 };
 824
 825         desc.name = coresight_alloc_device_name(&stm_devs, dev);
 826         if (!desc.name)
 827                 return -ENOMEM;
 828
 829         drvdata = devm_kzalloc(dev, sizeof(*drvdata), GFP_KERNEL);
 830         if (!drvdata)
 831                 return -ENOMEM;
 832
 833         drvdata->atclk = devm_clk_get(dev, "atclk"); /* optional */
 834         if (!IS_ERR(drvdata->atclk)) {
 835                 ret = clk_prepare_enable(drvdata->atclk);
 836                 if (ret)
 837                         return ret;
 838         }
 839
 840         drvdata->pclk = coresight_get_enable_apb_pclk(dev);
 841         if (IS_ERR(drvdata->pclk))
 842                 return -ENODEV;
 843         dev_set_drvdata(dev, drvdata);
 844
 845         base = devm_ioremap_resource(dev, res);
 846         if (IS_ERR(base))
 847                 return PTR_ERR(base);
 848         drvdata->base = base;
 849         desc.access = CSDEV_ACCESS_IOMEM(base);
 850
 851         ret = stm_get_stimulus_area(dev, &ch_res);
 852         if (ret)
 853                 return ret;
 854         drvdata->chs.phys = ch_res.start;
 855
 856         base = devm_ioremap_resource(dev, &ch_res);
 857         if (IS_ERR(base))
 858                 return PTR_ERR(base);
 859         drvdata->chs.base = base;
 860
 861         drvdata->write_bytes = stm_fundamental_data_size(drvdata);
 862
 863         if (boot_nr_channel)
 864                 drvdata->numsp = boot_nr_channel;
 865         else
 866                 drvdata->numsp = stm_num_stimulus_port(drvdata);
 867
 868         drvdata->chs.guaranteed = devm_bitmap_zalloc(dev, drvdata->numsp,
 869                                                      GFP_KERNEL);
 870         if (!drvdata->chs.guaranteed)
 871                 return -ENOMEM;
 872
 873         spin_lock_init(&drvdata->spinlock);
 874
 875         stm_init_default_data(drvdata);
 876         stm_init_generic_data(drvdata, desc.name);
 877
 878         if (stm_register_device(dev, &drvdata->stm, THIS_MODULE)) {
 879                 dev_info(dev,
 880                          "%s : stm_register_device failed, probing deferred\n",
 881                          desc.name);
 882                 return -EPROBE_DEFER;
 883         }
 884
 885         pdata = coresight_get_platform_data(dev);
 886         if (IS_ERR(pdata)) {
 887                 ret = PTR_ERR(pdata);
 888                 goto stm_unregister;
 889         }
 890         dev->platform_data = pdata;
 891
 892         desc.type = CORESIGHT_DEV_TYPE_SOURCE;
 893         desc.subtype.source_subtype = CORESIGHT_DEV_SUBTYPE_SOURCE_SOFTWARE;
 894         desc.ops = &stm_cs_ops;
 895         desc.pdata = pdata;
 896         desc.dev = dev;
 897         desc.groups = coresight_stm_groups;
 898         drvdata->csdev = coresight_register(&desc);
 899         if (IS_ERR(drvdata->csdev)) {
 900                 ret = PTR_ERR(drvdata->csdev);
 901                 goto stm_unregister;
 902         }
 903
 904         trace_id = coresight_trace_id_get_system_id();
 905         if (trace_id < 0) {
 906                 ret = trace_id;
 907                 goto cs_unregister;
 908         }
 909         drvdata->traceid = (u8)trace_id;
 910
 911         dev_info(&drvdata->csdev->dev, "%s initialized\n",
 912                  stm_csdev_name(drvdata->csdev));
 913         return 0;
 914
 915 cs_unregister:
 916         coresight_unregister(drvdata->csdev);
 917
 918 stm_unregister:
 919         stm_unregister_device(&drvdata->stm);
 920         return ret;
 921 }
 922
 923 static int stm_probe(struct amba_device *adev, const struct amba_id *id)
 924 {
 925         int ret;
 926
 927         ret = __stm_probe(&adev->dev, &adev->res);
 928         if (!ret)
 929                 pm_runtime_put(&adev->dev);
 930
 931         return ret;
 932 }
 933
 934 static void __stm_remove(struct device *dev)
 935 {
 936         struct stm_drvdata *drvdata = dev_get_drvdata(dev);
 937
 938         coresight_trace_id_put_system_id(drvdata->traceid);
 939         coresight_unregister(drvdata->csdev);
 940
 941         stm_unregister_device(&drvdata->stm);
 942 }
 943
 944 static void stm_remove(struct amba_device *adev)
 945 {
 946         __stm_remove(&adev->dev);
 947 }
 948
 949 #ifdef CONFIG_PM
 950 static int stm_runtime_suspend(struct device *dev)
 951 {
 952         struct stm_drvdata *drvdata = dev_get_drvdata(dev);
 953
 954         if (drvdata && !IS_ERR(drvdata->atclk))
 955                 clk_disable_unprepare(drvdata->atclk);
 956
 957         if (drvdata && !IS_ERR_OR_NULL(drvdata->pclk))
 958                 clk_disable_unprepare(drvdata->pclk);
 959         return 0;
 960 }
 961
 962 static int stm_runtime_resume(struct device *dev)
 963 {
 964         struct stm_drvdata *drvdata = dev_get_drvdata(dev);
 965
 966         if (drvdata && !IS_ERR(drvdata->atclk))
 967                 clk_prepare_enable(drvdata->atclk);
 968
 969         if (drvdata && !IS_ERR_OR_NULL(drvdata->pclk))
 970                 clk_prepare_enable(drvdata->pclk);
 971         return 0;
 972 }
 973 #endif
 974
 975 static const struct dev_pm_ops stm_dev_pm_ops = {
 976         SET_RUNTIME_PM_OPS(stm_runtime_suspend, stm_runtime_resume, NULL)
 977 };
 978
 979 static const struct amba_id stm_ids[] = {
 980         CS_AMBA_ID_DATA(0x000bb962, "STM32"),
 981         CS_AMBA_ID_DATA(0x000bb963, "STM500"),
 982         { 0, 0, NULL },
 983 };
 984
 985 MODULE_DEVICE_TABLE(amba, stm_ids);
 986
 987 static struct amba_driver stm_driver = {
 988         .drv = {
 989                 .name   = "coresight-stm",
 990                 .pm     = &stm_dev_pm_ops,
 991                 .suppress_bind_attrs = true,
 992         },
 993         .probe          = stm_probe,
 994         .remove         = stm_remove,
 995         .id_table       = stm_ids,
 996 };
 997
 998 static int stm_platform_probe(struct platform_device *pdev)
 999 {
1000         struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1001         int ret = 0;
1002
1003         pm_runtime_get_noresume(&pdev->dev);
1004         pm_runtime_set_active(&pdev->dev);
1005         pm_runtime_enable(&pdev->dev);
1006
1007         ret = __stm_probe(&pdev->dev, res);
1008         pm_runtime_put(&pdev->dev);
1009         if (ret)
1010                 pm_runtime_disable(&pdev->dev);
1011
1012         return ret;
1013 }
1014
1015 static void stm_platform_remove(struct platform_device *pdev)
1016 {
1017         struct stm_drvdata *drvdata = dev_get_drvdata(&pdev->dev);
1018
1019         if (WARN_ON(!drvdata))
1020                 return;
1021
1022         __stm_remove(&pdev->dev);
1023         pm_runtime_disable(&pdev->dev);
1024         if (!IS_ERR_OR_NULL(drvdata->pclk))
1025                 clk_put(drvdata->pclk);
1026 }
1027
1028 #ifdef CONFIG_ACPI
1029 static const struct acpi_device_id stm_acpi_ids[] = {
1030         {"ARMHC502", 0, 0, 0}, /* ARM CoreSight STM */
1031         {},
1032 };
1033 MODULE_DEVICE_TABLE(acpi, stm_acpi_ids);
1034 #endif
1035
1036 static struct platform_driver stm_platform_driver = {
1037         .probe  = stm_platform_probe,
1038         .remove_new = stm_platform_remove,
1039         .driver = {
1040                 .name                   = "coresight-stm-platform",
1041                 .acpi_match_table       = ACPI_PTR(stm_acpi_ids),
1042                 .suppress_bind_attrs    = true,
1043                 .pm                     = &stm_dev_pm_ops,
1044         },
1045 };
1046
1047 static int __init stm_init(void)
1048 {
1049         return coresight_init_driver("stm", &stm_driver, &stm_platform_driver);
1050 }
1051
1052 static void __exit stm_exit(void)
1053 {
1054         coresight_remove_driver(&stm_driver, &stm_platform_driver);
1055 }
1056 module_init(stm_init);
1057 module_exit(stm_exit);
1058
1059 MODULE_AUTHOR("Pratik Patel <[email protected]>");
1060 MODULE_DESCRIPTION("Arm CoreSight System Trace Macrocell driver");
1061 MODULE_LICENSE("GPL v2");