drivers/gpu/drm/radeon/radeon_i2c.c

   1 /*
   2  * Copyright 2007-8 Advanced Micro Devices, Inc.
   3  * Copyright 2008 Red Hat Inc.
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the "Software"),
   7  * to deal in the Software without restriction, including without limitation
   8  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   9  * and/or sell copies of the Software, and to permit persons to whom the
  10  * Software is furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice shall be included in
  13  * all copies or substantial portions of the Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  19  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  20  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  21  * OTHER DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors: Dave Airlie
  24  *          Alex Deucher
  25  */
  26
  27 #include <linux/export.h>
  28 #include <linux/pci.h>
  29
  30 #include <drm/drm_device.h>
  31 #include <drm/drm_edid.h>
  32 #include <drm/radeon_drm.h>
  33
  34 #include "radeon.h"
  35 #include "atom.h"
  36
  37 bool radeon_ddc_probe(struct radeon_connector *radeon_connector, bool use_aux)
  38 {
  39         u8 out = 0x0;
  40         u8 buf[8];
  41         int ret;
  42         struct i2c_msg msgs[] = {
  43                 {
  44                         .addr = DDC_ADDR,
  45                         .flags = 0,
  46                         .len = 1,
  47                         .buf = &out,
  48                 },
  49                 {
  50                         .addr = DDC_ADDR,
  51                         .flags = I2C_M_RD,
  52                         .len = 8,
  53                         .buf = buf,
  54                 }
  55         };
  56
  57         /* on hw with routers, select right port */
  58         if (radeon_connector->router.ddc_valid)
  59                 radeon_router_select_ddc_port(radeon_connector);
  60
  61         if (use_aux) {
  62                 ret = i2c_transfer(&radeon_connector->ddc_bus->aux.ddc, msgs, 2);
  63         } else {
  64                 ret = i2c_transfer(&radeon_connector->ddc_bus->adapter, msgs, 2);
  65         }
  66
  67         if (ret != 2)
  68                 /* Couldn't find an accessible DDC on this connector */
  69                 return false;
  70         /* Probe also for valid EDID header
  71          * EDID header starts with:
  72          * 0x00,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0x00.
  73          * Only the first 6 bytes must be valid as
  74          * drm_edid_block_valid() can fix the last 2 bytes */
  75         if (drm_edid_header_is_valid(buf) < 6) {
  76                 /* Couldn't find an accessible EDID on this
  77                  * connector */
  78                 return false;
  79         }
  80         return true;
  81 }
  82
  83 /* bit banging i2c */
  84
  85 static int pre_xfer(struct i2c_adapter *i2c_adap)
  86 {
  87         struct radeon_i2c_chan *i2c = i2c_get_adapdata(i2c_adap);
  88         struct radeon_device *rdev = i2c->dev->dev_private;
  89         struct radeon_i2c_bus_rec *rec = &i2c->rec;
  90         uint32_t temp;
  91
  92         mutex_lock(&i2c->mutex);
  93
  94         /* RV410 appears to have a bug where the hw i2c in reset
  95          * holds the i2c port in a bad state - switch hw i2c away before
  96          * doing DDC - do this for all r200s/r300s/r400s for safety sake
  97          */
  98         if (rec->hw_capable) {
  99                 if ((rdev->family >= CHIP_R200) && !ASIC_IS_AVIVO(rdev)) {
 100                         u32 reg;
 101
 102                         if (rdev->family >= CHIP_RV350)
 103                                 reg = RADEON_GPIO_MONID;
 104                         else if ((rdev->family == CHIP_R300) ||
 105                                  (rdev->family == CHIP_R350))
 106                                 reg = RADEON_GPIO_DVI_DDC;
 107                         else
 108                                 reg = RADEON_GPIO_CRT2_DDC;
 109
 110                         mutex_lock(&rdev->dc_hw_i2c_mutex);
 111                         if (rec->a_clk_reg == reg) {
 112                                 WREG32(RADEON_DVI_I2C_CNTL_0, (RADEON_I2C_SOFT_RST |
 113                                                                R200_DVI_I2C_PIN_SEL(R200_SEL_DDC1)));
 114                         } else {
 115                                 WREG32(RADEON_DVI_I2C_CNTL_0, (RADEON_I2C_SOFT_RST |
 116                                                                R200_DVI_I2C_PIN_SEL(R200_SEL_DDC3)));
 117                         }
 118                         mutex_unlock(&rdev->dc_hw_i2c_mutex);
 119                 }
 120         }
 121
 122         /* switch the pads to ddc mode */
 123         if (ASIC_IS_DCE3(rdev) && rec->hw_capable) {
 124                 temp = RREG32(rec->mask_clk_reg);
 125                 temp &= ~(1 << 16);
 126                 WREG32(rec->mask_clk_reg, temp);
 127         }
 128
 129         /* clear the output pin values */
 130         temp = RREG32(rec->a_clk_reg) & ~rec->a_clk_mask;
 131         WREG32(rec->a_clk_reg, temp);
 132
 133         temp = RREG32(rec->a_data_reg) & ~rec->a_data_mask;
 134         WREG32(rec->a_data_reg, temp);
 135
 136         /* set the pins to input */
 137         temp = RREG32(rec->en_clk_reg) & ~rec->en_clk_mask;
 138         WREG32(rec->en_clk_reg, temp);
 139
 140         temp = RREG32(rec->en_data_reg) & ~rec->en_data_mask;
 141         WREG32(rec->en_data_reg, temp);
 142
 143         /* mask the gpio pins for software use */
 144         temp = RREG32(rec->mask_clk_reg) | rec->mask_clk_mask;
 145         WREG32(rec->mask_clk_reg, temp);
 146         temp = RREG32(rec->mask_clk_reg);
 147
 148         temp = RREG32(rec->mask_data_reg) | rec->mask_data_mask;
 149         WREG32(rec->mask_data_reg, temp);
 150         temp = RREG32(rec->mask_data_reg);
 151
 152         return 0;
 153 }
 154
 155 static void post_xfer(struct i2c_adapter *i2c_adap)
 156 {
 157         struct radeon_i2c_chan *i2c = i2c_get_adapdata(i2c_adap);
 158         struct radeon_device *rdev = i2c->dev->dev_private;
 159         struct radeon_i2c_bus_rec *rec = &i2c->rec;
 160         uint32_t temp;
 161
 162         /* unmask the gpio pins for software use */
 163         temp = RREG32(rec->mask_clk_reg) & ~rec->mask_clk_mask;
 164         WREG32(rec->mask_clk_reg, temp);
 165         temp = RREG32(rec->mask_clk_reg);
 166
 167         temp = RREG32(rec->mask_data_reg) & ~rec->mask_data_mask;
 168         WREG32(rec->mask_data_reg, temp);
 169         temp = RREG32(rec->mask_data_reg);
 170
 171         mutex_unlock(&i2c->mutex);
 172 }
 173
 174 static int get_clock(void *i2c_priv)
 175 {
 176         struct radeon_i2c_chan *i2c = i2c_priv;
 177         struct radeon_device *rdev = i2c->dev->dev_private;
 178         struct radeon_i2c_bus_rec *rec = &i2c->rec;
 179         uint32_t val;
 180
 181         /* read the value off the pin */
 182         val = RREG32(rec->y_clk_reg);
 183         val &= rec->y_clk_mask;
 184
 185         return (val != 0);
 186 }
 187
 188
 189 static int get_data(void *i2c_priv)
 190 {
 191         struct radeon_i2c_chan *i2c = i2c_priv;
 192         struct radeon_device *rdev = i2c->dev->dev_private;
 193         struct radeon_i2c_bus_rec *rec = &i2c->rec;
 194         uint32_t val;
 195
 196         /* read the value off the pin */
 197         val = RREG32(rec->y_data_reg);
 198         val &= rec->y_data_mask;
 199
 200         return (val != 0);
 201 }
 202
 203 static void set_clock(void *i2c_priv, int clock)
 204 {
 205         struct radeon_i2c_chan *i2c = i2c_priv;
 206         struct radeon_device *rdev = i2c->dev->dev_private;
 207         struct radeon_i2c_bus_rec *rec = &i2c->rec;
 208         uint32_t val;
 209
 210         /* set pin direction */
 211         val = RREG32(rec->en_clk_reg) & ~rec->en_clk_mask;
 212         val |= clock ? 0 : rec->en_clk_mask;
 213         WREG32(rec->en_clk_reg, val);
 214 }
 215
 216 static void set_data(void *i2c_priv, int data)
 217 {
 218         struct radeon_i2c_chan *i2c = i2c_priv;
 219         struct radeon_device *rdev = i2c->dev->dev_private;
 220         struct radeon_i2c_bus_rec *rec = &i2c->rec;
 221         uint32_t val;
 222
 223         /* set pin direction */
 224         val = RREG32(rec->en_data_reg) & ~rec->en_data_mask;
 225         val |= data ? 0 : rec->en_data_mask;
 226         WREG32(rec->en_data_reg, val);
 227 }
 228
 229 /* hw i2c */
 230
 231 static u32 radeon_get_i2c_prescale(struct radeon_device *rdev)
 232 {
 233         u32 sclk = rdev->pm.current_sclk;
 234         u32 prescale = 0;
 235         u32 nm;
 236         u8 n, m, loop;
 237         int i2c_clock;
 238
 239         switch (rdev->family) {
 240         case CHIP_R100:
 241         case CHIP_RV100:
 242         case CHIP_RS100:
 243         case CHIP_RV200:
 244         case CHIP_RS200:
 245         case CHIP_R200:
 246         case CHIP_RV250:
 247         case CHIP_RS300:
 248         case CHIP_RV280:
 249         case CHIP_R300:
 250         case CHIP_R350:
 251         case CHIP_RV350:
 252                 i2c_clock = 60;
 253                 nm = (sclk * 10) / (i2c_clock * 4);
 254                 for (loop = 1; loop < 255; loop++) {
 255                         if ((nm / loop) < loop)
 256                                 break;
 257                 }
 258                 n = loop - 1;
 259                 m = loop - 2;
 260                 prescale = m | (n << 8);
 261                 break;
 262         case CHIP_RV380:
 263         case CHIP_RS400:
 264         case CHIP_RS480:
 265         case CHIP_R420:
 266         case CHIP_R423:
 267         case CHIP_RV410:
 268                 prescale = (((sclk * 10)/(4 * 128 * 100) + 1) << 8) + 128;
 269                 break;
 270         case CHIP_RS600:
 271         case CHIP_RS690:
 272         case CHIP_RS740:
 273                 /* todo */
 274                 break;
 275         case CHIP_RV515:
 276         case CHIP_R520:
 277         case CHIP_RV530:
 278         case CHIP_RV560:
 279         case CHIP_RV570:
 280         case CHIP_R580:
 281                 i2c_clock = 50;
 282                 if (rdev->family == CHIP_R520)
 283                         prescale = (127 << 8) + ((sclk * 10) / (4 * 127 * i2c_clock));
 284                 else
 285                         prescale = (((sclk * 10)/(4 * 128 * 100) + 1) << 8) + 128;
 286                 break;
 287         case CHIP_R600:
 288         case CHIP_RV610:
 289         case CHIP_RV630:
 290         case CHIP_RV670:
 291                 /* todo */
 292                 break;
 293         case CHIP_RV620:
 294         case CHIP_RV635:
 295         case CHIP_RS780:
 296         case CHIP_RS880:
 297         case CHIP_RV770:
 298         case CHIP_RV730:
 299         case CHIP_RV710:
 300         case CHIP_RV740:
 301                 /* todo */
 302                 break;
 303         case CHIP_CEDAR:
 304         case CHIP_REDWOOD:
 305         case CHIP_JUNIPER:
 306         case CHIP_CYPRESS:
 307         case CHIP_HEMLOCK:
 308                 /* todo */
 309                 break;
 310         default:
 311                 DRM_ERROR("i2c: unhandled radeon chip\n");
 312                 break;
 313         }
 314         return prescale;
 315 }
 316
 317
 318 /* hw i2c engine for r1xx-4xx hardware
 319  * hw can buffer up to 15 bytes
 320  */
 321 static int r100_hw_i2c_xfer(struct i2c_adapter *i2c_adap,
 322                             struct i2c_msg *msgs, int num)
 323 {
 324         struct radeon_i2c_chan *i2c = i2c_get_adapdata(i2c_adap);
 325         struct radeon_device *rdev = i2c->dev->dev_private;
 326         struct radeon_i2c_bus_rec *rec = &i2c->rec;
 327         struct i2c_msg *p;
 328         int i, j, k, ret = num;
 329         u32 prescale;
 330         u32 i2c_cntl_0, i2c_cntl_1, i2c_data;
 331         u32 tmp, reg;
 332
 333         mutex_lock(&rdev->dc_hw_i2c_mutex);
 334         /* take the pm lock since we need a constant sclk */
 335         mutex_lock(&rdev->pm.mutex);
 336
 337         prescale = radeon_get_i2c_prescale(rdev);
 338
 339         reg = ((prescale << RADEON_I2C_PRESCALE_SHIFT) |
 340                RADEON_I2C_DRIVE_EN |
 341                RADEON_I2C_START |
 342                RADEON_I2C_STOP |
 343                RADEON_I2C_GO);
 344
 345         if (rdev->is_atom_bios) {
 346                 tmp = RREG32(RADEON_BIOS_6_SCRATCH);
 347                 WREG32(RADEON_BIOS_6_SCRATCH, tmp | ATOM_S6_HW_I2C_BUSY_STATE);
 348         }
 349
 350         if (rec->mm_i2c) {
 351                 i2c_cntl_0 = RADEON_I2C_CNTL_0;
 352                 i2c_cntl_1 = RADEON_I2C_CNTL_1;
 353                 i2c_data = RADEON_I2C_DATA;
 354         } else {
 355                 i2c_cntl_0 = RADEON_DVI_I2C_CNTL_0;
 356                 i2c_cntl_1 = RADEON_DVI_I2C_CNTL_1;
 357                 i2c_data = RADEON_DVI_I2C_DATA;
 358
 359                 switch (rdev->family) {
 360                 case CHIP_R100:
 361                 case CHIP_RV100:
 362                 case CHIP_RS100:
 363                 case CHIP_RV200:
 364                 case CHIP_RS200:
 365                 case CHIP_RS300:
 366                         switch (rec->mask_clk_reg) {
 367                         case RADEON_GPIO_DVI_DDC:
 368                                 /* no gpio select bit */
 369                                 break;
 370                         default:
 371                                 DRM_ERROR("gpio not supported with hw i2c\n");
 372                                 ret = -EINVAL;
 373                                 goto done;
 374                         }
 375                         break;
 376                 case CHIP_R200:
 377                         /* only bit 4 on r200 */
 378                         switch (rec->mask_clk_reg) {
 379                         case RADEON_GPIO_DVI_DDC:
 380                                 reg |= R200_DVI_I2C_PIN_SEL(R200_SEL_DDC1);
 381                                 break;
 382                         case RADEON_GPIO_MONID:
 383                                 reg |= R200_DVI_I2C_PIN_SEL(R200_SEL_DDC3);
 384                                 break;
 385                         default:
 386                                 DRM_ERROR("gpio not supported with hw i2c\n");
 387                                 ret = -EINVAL;
 388                                 goto done;
 389                         }
 390                         break;
 391                 case CHIP_RV250:
 392                 case CHIP_RV280:
 393                         /* bits 3 and 4 */
 394                         switch (rec->mask_clk_reg) {
 395                         case RADEON_GPIO_DVI_DDC:
 396                                 reg |= R200_DVI_I2C_PIN_SEL(R200_SEL_DDC1);
 397                                 break;
 398                         case RADEON_GPIO_VGA_DDC:
 399                                 reg |= R200_DVI_I2C_PIN_SEL(R200_SEL_DDC2);
 400                                 break;
 401                         case RADEON_GPIO_CRT2_DDC:
 402                                 reg |= R200_DVI_I2C_PIN_SEL(R200_SEL_DDC3);
 403                                 break;
 404                         default:
 405                                 DRM_ERROR("gpio not supported with hw i2c\n");
 406                                 ret = -EINVAL;
 407                                 goto done;
 408                         }
 409                         break;
 410                 case CHIP_R300:
 411                 case CHIP_R350:
 412                         /* only bit 4 on r300/r350 */
 413                         switch (rec->mask_clk_reg) {
 414                         case RADEON_GPIO_VGA_DDC:
 415                                 reg |= R200_DVI_I2C_PIN_SEL(R200_SEL_DDC1);
 416                                 break;
 417                         case RADEON_GPIO_DVI_DDC:
 418                                 reg |= R200_DVI_I2C_PIN_SEL(R200_SEL_DDC3);
 419                                 break;
 420                         default:
 421                                 DRM_ERROR("gpio not supported with hw i2c\n");
 422                                 ret = -EINVAL;
 423                                 goto done;
 424                         }
 425                         break;
 426                 case CHIP_RV350:
 427                 case CHIP_RV380:
 428                 case CHIP_R420:
 429                 case CHIP_R423:
 430                 case CHIP_RV410:
 431                 case CHIP_RS400:
 432                 case CHIP_RS480:
 433                         /* bits 3 and 4 */
 434                         switch (rec->mask_clk_reg) {
 435                         case RADEON_GPIO_VGA_DDC:
 436                                 reg |= R200_DVI_I2C_PIN_SEL(R200_SEL_DDC1);
 437                                 break;
 438                         case RADEON_GPIO_DVI_DDC:
 439                                 reg |= R200_DVI_I2C_PIN_SEL(R200_SEL_DDC2);
 440                                 break;
 441                         case RADEON_GPIO_MONID:
 442                                 reg |= R200_DVI_I2C_PIN_SEL(R200_SEL_DDC3);
 443                                 break;
 444                         default:
 445                                 DRM_ERROR("gpio not supported with hw i2c\n");
 446                                 ret = -EINVAL;
 447                                 goto done;
 448                         }
 449                         break;
 450                 default:
 451                         DRM_ERROR("unsupported asic\n");
 452                         ret = -EINVAL;
 453                         goto done;
 454                         break;
 455                 }
 456         }
 457
 458         /* check for bus probe */
 459         p = &msgs[0];
 460         if ((num == 1) && (p->len == 0)) {
 461                 WREG32(i2c_cntl_0, (RADEON_I2C_DONE |
 462                                     RADEON_I2C_NACK |
 463                                     RADEON_I2C_HALT |
 464                                     RADEON_I2C_SOFT_RST));
 465                 WREG32(i2c_data, (p->addr << 1) & 0xff);
 466                 WREG32(i2c_data, 0);
 467                 WREG32(i2c_cntl_1, ((1 << RADEON_I2C_DATA_COUNT_SHIFT) |
 468                                     (1 << RADEON_I2C_ADDR_COUNT_SHIFT) |
 469                                     RADEON_I2C_EN |
 470                                     (48 << RADEON_I2C_TIME_LIMIT_SHIFT)));
 471                 WREG32(i2c_cntl_0, reg);
 472                 for (k = 0; k < 32; k++) {
 473                         udelay(10);
 474                         tmp = RREG32(i2c_cntl_0);
 475                         if (tmp & RADEON_I2C_GO)
 476                                 continue;
 477                         tmp = RREG32(i2c_cntl_0);
 478                         if (tmp & RADEON_I2C_DONE)
 479                                 break;
 480                         else {
 481                                 DRM_DEBUG("i2c write error 0x%08x\n", tmp);
 482                                 WREG32(i2c_cntl_0, tmp | RADEON_I2C_ABORT);
 483                                 ret = -EIO;
 484                                 goto done;
 485                         }
 486                 }
 487                 goto done;
 488         }
 489
 490         for (i = 0; i < num; i++) {
 491                 p = &msgs[i];
 492                 for (j = 0; j < p->len; j++) {
 493                         if (p->flags & I2C_M_RD) {
 494                                 WREG32(i2c_cntl_0, (RADEON_I2C_DONE |
 495                                                     RADEON_I2C_NACK |
 496                                                     RADEON_I2C_HALT |
 497                                                     RADEON_I2C_SOFT_RST));
 498                                 WREG32(i2c_data, ((p->addr << 1) & 0xff) | 0x1);
 499                                 WREG32(i2c_cntl_1, ((1 << RADEON_I2C_DATA_COUNT_SHIFT) |
 500                                                     (1 << RADEON_I2C_ADDR_COUNT_SHIFT) |
 501                                                     RADEON_I2C_EN |
 502                                                     (48 << RADEON_I2C_TIME_LIMIT_SHIFT)));
 503                                 WREG32(i2c_cntl_0, reg | RADEON_I2C_RECEIVE);
 504                                 for (k = 0; k < 32; k++) {
 505                                         udelay(10);
 506                                         tmp = RREG32(i2c_cntl_0);
 507                                         if (tmp & RADEON_I2C_GO)
 508                                                 continue;
 509                                         tmp = RREG32(i2c_cntl_0);
 510                                         if (tmp & RADEON_I2C_DONE)
 511                                                 break;
 512                                         else {
 513                                                 DRM_DEBUG("i2c read error 0x%08x\n", tmp);
 514                                                 WREG32(i2c_cntl_0, tmp | RADEON_I2C_ABORT);
 515                                                 ret = -EIO;
 516                                                 goto done;
 517                                         }
 518                                 }
 519                                 p->buf[j] = RREG32(i2c_data) & 0xff;
 520                         } else {
 521                                 WREG32(i2c_cntl_0, (RADEON_I2C_DONE |
 522                                                     RADEON_I2C_NACK |
 523                                                     RADEON_I2C_HALT |
 524                                                     RADEON_I2C_SOFT_RST));
 525                                 WREG32(i2c_data, (p->addr << 1) & 0xff);
 526                                 WREG32(i2c_data, p->buf[j]);
 527                                 WREG32(i2c_cntl_1, ((1 << RADEON_I2C_DATA_COUNT_SHIFT) |
 528                                                     (1 << RADEON_I2C_ADDR_COUNT_SHIFT) |
 529                                                     RADEON_I2C_EN |
 530                                                     (48 << RADEON_I2C_TIME_LIMIT_SHIFT)));
 531                                 WREG32(i2c_cntl_0, reg);
 532                                 for (k = 0; k < 32; k++) {
 533                                         udelay(10);
 534                                         tmp = RREG32(i2c_cntl_0);
 535                                         if (tmp & RADEON_I2C_GO)
 536                                                 continue;
 537                                         tmp = RREG32(i2c_cntl_0);
 538                                         if (tmp & RADEON_I2C_DONE)
 539                                                 break;
 540                                         else {
 541                                                 DRM_DEBUG("i2c write error 0x%08x\n", tmp);
 542                                                 WREG32(i2c_cntl_0, tmp | RADEON_I2C_ABORT);
 543                                                 ret = -EIO;
 544                                                 goto done;
 545                                         }
 546                                 }
 547                         }
 548                 }
 549         }
 550
 551 done:
 552         WREG32(i2c_cntl_0, 0);
 553         WREG32(i2c_cntl_1, 0);
 554         WREG32(i2c_cntl_0, (RADEON_I2C_DONE |
 555                             RADEON_I2C_NACK |
 556                             RADEON_I2C_HALT |
 557                             RADEON_I2C_SOFT_RST));
 558
 559         if (rdev->is_atom_bios) {
 560                 tmp = RREG32(RADEON_BIOS_6_SCRATCH);
 561                 tmp &= ~ATOM_S6_HW_I2C_BUSY_STATE;
 562                 WREG32(RADEON_BIOS_6_SCRATCH, tmp);
 563         }
 564
 565         mutex_unlock(&rdev->pm.mutex);
 566         mutex_unlock(&rdev->dc_hw_i2c_mutex);
 567
 568         return ret;
 569 }
 570
 571 /* hw i2c engine for r5xx hardware
 572  * hw can buffer up to 15 bytes
 573  */
 574 static int r500_hw_i2c_xfer(struct i2c_adapter *i2c_adap,
 575                             struct i2c_msg *msgs, int num)
 576 {
 577         struct radeon_i2c_chan *i2c = i2c_get_adapdata(i2c_adap);
 578         struct radeon_device *rdev = i2c->dev->dev_private;
 579         struct radeon_i2c_bus_rec *rec = &i2c->rec;
 580         struct i2c_msg *p;
 581         int i, j, remaining, current_count, buffer_offset, ret = num;
 582         u32 prescale;
 583         u32 tmp, reg;
 584         u32 saved1, saved2;
 585
 586         mutex_lock(&rdev->dc_hw_i2c_mutex);
 587         /* take the pm lock since we need a constant sclk */
 588         mutex_lock(&rdev->pm.mutex);
 589
 590         prescale = radeon_get_i2c_prescale(rdev);
 591
 592         /* clear gpio mask bits */
 593         tmp = RREG32(rec->mask_clk_reg);
 594         tmp &= ~rec->mask_clk_mask;
 595         WREG32(rec->mask_clk_reg, tmp);
 596         tmp = RREG32(rec->mask_clk_reg);
 597
 598         tmp = RREG32(rec->mask_data_reg);
 599         tmp &= ~rec->mask_data_mask;
 600         WREG32(rec->mask_data_reg, tmp);
 601         tmp = RREG32(rec->mask_data_reg);
 602
 603         /* clear pin values */
 604         tmp = RREG32(rec->a_clk_reg);
 605         tmp &= ~rec->a_clk_mask;
 606         WREG32(rec->a_clk_reg, tmp);
 607         tmp = RREG32(rec->a_clk_reg);
 608
 609         tmp = RREG32(rec->a_data_reg);
 610         tmp &= ~rec->a_data_mask;
 611         WREG32(rec->a_data_reg, tmp);
 612         tmp = RREG32(rec->a_data_reg);
 613
 614         /* set the pins to input */
 615         tmp = RREG32(rec->en_clk_reg);
 616         tmp &= ~rec->en_clk_mask;
 617         WREG32(rec->en_clk_reg, tmp);
 618         tmp = RREG32(rec->en_clk_reg);
 619
 620         tmp = RREG32(rec->en_data_reg);
 621         tmp &= ~rec->en_data_mask;
 622         WREG32(rec->en_data_reg, tmp);
 623         tmp = RREG32(rec->en_data_reg);
 624
 625         /* */
 626         tmp = RREG32(RADEON_BIOS_6_SCRATCH);
 627         WREG32(RADEON_BIOS_6_SCRATCH, tmp | ATOM_S6_HW_I2C_BUSY_STATE);
 628         saved1 = RREG32(AVIVO_DC_I2C_CONTROL1);
 629         saved2 = RREG32(0x494);
 630         WREG32(0x494, saved2 | 0x1);
 631
 632         WREG32(AVIVO_DC_I2C_ARBITRATION, AVIVO_DC_I2C_SW_WANTS_TO_USE_I2C);
 633         for (i = 0; i < 50; i++) {
 634                 udelay(1);
 635                 if (RREG32(AVIVO_DC_I2C_ARBITRATION) & AVIVO_DC_I2C_SW_CAN_USE_I2C)
 636                         break;
 637         }
 638         if (i == 50) {
 639                 DRM_ERROR("failed to get i2c bus\n");
 640                 ret = -EBUSY;
 641                 goto done;
 642         }
 643
 644         reg = AVIVO_DC_I2C_START | AVIVO_DC_I2C_STOP | AVIVO_DC_I2C_EN;
 645         switch (rec->mask_clk_reg) {
 646         case AVIVO_DC_GPIO_DDC1_MASK:
 647                 reg |= AVIVO_DC_I2C_PIN_SELECT(AVIVO_SEL_DDC1);
 648                 break;
 649         case AVIVO_DC_GPIO_DDC2_MASK:
 650                 reg |= AVIVO_DC_I2C_PIN_SELECT(AVIVO_SEL_DDC2);
 651                 break;
 652         case AVIVO_DC_GPIO_DDC3_MASK:
 653                 reg |= AVIVO_DC_I2C_PIN_SELECT(AVIVO_SEL_DDC3);
 654                 break;
 655         default:
 656                 DRM_ERROR("gpio not supported with hw i2c\n");
 657                 ret = -EINVAL;
 658                 goto done;
 659         }
 660
 661         /* check for bus probe */
 662         p = &msgs[0];
 663         if ((num == 1) && (p->len == 0)) {
 664                 WREG32(AVIVO_DC_I2C_STATUS1, (AVIVO_DC_I2C_DONE |
 665                                               AVIVO_DC_I2C_NACK |
 666                                               AVIVO_DC_I2C_HALT));
 667                 WREG32(AVIVO_DC_I2C_RESET, AVIVO_DC_I2C_SOFT_RESET);
 668                 udelay(1);
 669                 WREG32(AVIVO_DC_I2C_RESET, 0);
 670
 671                 WREG32(AVIVO_DC_I2C_DATA, (p->addr << 1) & 0xff);
 672                 WREG32(AVIVO_DC_I2C_DATA, 0);
 673
 674                 WREG32(AVIVO_DC_I2C_CONTROL3, AVIVO_DC_I2C_TIME_LIMIT(48));
 675                 WREG32(AVIVO_DC_I2C_CONTROL2, (AVIVO_DC_I2C_ADDR_COUNT(1) |
 676                                                AVIVO_DC_I2C_DATA_COUNT(1) |
 677                                                (prescale << 16)));
 678                 WREG32(AVIVO_DC_I2C_CONTROL1, reg);
 679                 WREG32(AVIVO_DC_I2C_STATUS1, AVIVO_DC_I2C_GO);
 680                 for (j = 0; j < 200; j++) {
 681                         udelay(50);
 682                         tmp = RREG32(AVIVO_DC_I2C_STATUS1);
 683                         if (tmp & AVIVO_DC_I2C_GO)
 684                                 continue;
 685                         tmp = RREG32(AVIVO_DC_I2C_STATUS1);
 686                         if (tmp & AVIVO_DC_I2C_DONE)
 687                                 break;
 688                         else {
 689                                 DRM_DEBUG("i2c write error 0x%08x\n", tmp);
 690                                 WREG32(AVIVO_DC_I2C_RESET, AVIVO_DC_I2C_ABORT);
 691                                 ret = -EIO;
 692                                 goto done;
 693                         }
 694                 }
 695                 goto done;
 696         }
 697
 698         for (i = 0; i < num; i++) {
 699                 p = &msgs[i];
 700                 remaining = p->len;
 701                 buffer_offset = 0;
 702                 if (p->flags & I2C_M_RD) {
 703                         while (remaining) {
 704                                 if (remaining > 15)
 705                                         current_count = 15;
 706                                 else
 707                                         current_count = remaining;
 708                                 WREG32(AVIVO_DC_I2C_STATUS1, (AVIVO_DC_I2C_DONE |
 709                                                               AVIVO_DC_I2C_NACK |
 710                                                               AVIVO_DC_I2C_HALT));
 711                                 WREG32(AVIVO_DC_I2C_RESET, AVIVO_DC_I2C_SOFT_RESET);
 712                                 udelay(1);
 713                                 WREG32(AVIVO_DC_I2C_RESET, 0);
 714
 715                                 WREG32(AVIVO_DC_I2C_DATA, ((p->addr << 1) & 0xff) | 0x1);
 716                                 WREG32(AVIVO_DC_I2C_CONTROL3, AVIVO_DC_I2C_TIME_LIMIT(48));
 717                                 WREG32(AVIVO_DC_I2C_CONTROL2, (AVIVO_DC_I2C_ADDR_COUNT(1) |
 718                                                                AVIVO_DC_I2C_DATA_COUNT(current_count) |
 719                                                                (prescale << 16)));
 720                                 WREG32(AVIVO_DC_I2C_CONTROL1, reg | AVIVO_DC_I2C_RECEIVE);
 721                                 WREG32(AVIVO_DC_I2C_STATUS1, AVIVO_DC_I2C_GO);
 722                                 for (j = 0; j < 200; j++) {
 723                                         udelay(50);
 724                                         tmp = RREG32(AVIVO_DC_I2C_STATUS1);
 725                                         if (tmp & AVIVO_DC_I2C_GO)
 726                                                 continue;
 727                                         tmp = RREG32(AVIVO_DC_I2C_STATUS1);
 728                                         if (tmp & AVIVO_DC_I2C_DONE)
 729                                                 break;
 730                                         else {
 731                                                 DRM_DEBUG("i2c read error 0x%08x\n", tmp);
 732                                                 WREG32(AVIVO_DC_I2C_RESET, AVIVO_DC_I2C_ABORT);
 733                                                 ret = -EIO;
 734                                                 goto done;
 735                                         }
 736                                 }
 737                                 for (j = 0; j < current_count; j++)
 738                                         p->buf[buffer_offset + j] = RREG32(AVIVO_DC_I2C_DATA) & 0xff;
 739                                 remaining -= current_count;
 740                                 buffer_offset += current_count;
 741                         }
 742                 } else {
 743                         while (remaining) {
 744                                 if (remaining > 15)
 745                                         current_count = 15;
 746                                 else
 747                                         current_count = remaining;
 748                                 WREG32(AVIVO_DC_I2C_STATUS1, (AVIVO_DC_I2C_DONE |
 749                                                               AVIVO_DC_I2C_NACK |
 750                                                               AVIVO_DC_I2C_HALT));
 751                                 WREG32(AVIVO_DC_I2C_RESET, AVIVO_DC_I2C_SOFT_RESET);
 752                                 udelay(1);
 753                                 WREG32(AVIVO_DC_I2C_RESET, 0);
 754
 755                                 WREG32(AVIVO_DC_I2C_DATA, (p->addr << 1) & 0xff);
 756                                 for (j = 0; j < current_count; j++)
 757                                         WREG32(AVIVO_DC_I2C_DATA, p->buf[buffer_offset + j]);
 758
 759                                 WREG32(AVIVO_DC_I2C_CONTROL3, AVIVO_DC_I2C_TIME_LIMIT(48));
 760                                 WREG32(AVIVO_DC_I2C_CONTROL2, (AVIVO_DC_I2C_ADDR_COUNT(1) |
 761                                                                AVIVO_DC_I2C_DATA_COUNT(current_count) |
 762                                                                (prescale << 16)));
 763                                 WREG32(AVIVO_DC_I2C_CONTROL1, reg);
 764                                 WREG32(AVIVO_DC_I2C_STATUS1, AVIVO_DC_I2C_GO);
 765                                 for (j = 0; j < 200; j++) {
 766                                         udelay(50);
 767                                         tmp = RREG32(AVIVO_DC_I2C_STATUS1);
 768                                         if (tmp & AVIVO_DC_I2C_GO)
 769                                                 continue;
 770                                         tmp = RREG32(AVIVO_DC_I2C_STATUS1);
 771                                         if (tmp & AVIVO_DC_I2C_DONE)
 772                                                 break;
 773                                         else {
 774                                                 DRM_DEBUG("i2c write error 0x%08x\n", tmp);
 775                                                 WREG32(AVIVO_DC_I2C_RESET, AVIVO_DC_I2C_ABORT);
 776                                                 ret = -EIO;
 777                                                 goto done;
 778                                         }
 779                                 }
 780                                 remaining -= current_count;
 781                                 buffer_offset += current_count;
 782                         }
 783                 }
 784         }
 785
 786 done:
 787         WREG32(AVIVO_DC_I2C_STATUS1, (AVIVO_DC_I2C_DONE |
 788                                       AVIVO_DC_I2C_NACK |
 789                                       AVIVO_DC_I2C_HALT));
 790         WREG32(AVIVO_DC_I2C_RESET, AVIVO_DC_I2C_SOFT_RESET);
 791         udelay(1);
 792         WREG32(AVIVO_DC_I2C_RESET, 0);
 793
 794         WREG32(AVIVO_DC_I2C_ARBITRATION, AVIVO_DC_I2C_SW_DONE_USING_I2C);
 795         WREG32(AVIVO_DC_I2C_CONTROL1, saved1);
 796         WREG32(0x494, saved2);
 797         tmp = RREG32(RADEON_BIOS_6_SCRATCH);
 798         tmp &= ~ATOM_S6_HW_I2C_BUSY_STATE;
 799         WREG32(RADEON_BIOS_6_SCRATCH, tmp);
 800
 801         mutex_unlock(&rdev->pm.mutex);
 802         mutex_unlock(&rdev->dc_hw_i2c_mutex);
 803
 804         return ret;
 805 }
 806
 807 static int radeon_hw_i2c_xfer(struct i2c_adapter *i2c_adap,
 808                               struct i2c_msg *msgs, int num)
 809 {
 810         struct radeon_i2c_chan *i2c = i2c_get_adapdata(i2c_adap);
 811         struct radeon_device *rdev = i2c->dev->dev_private;
 812         struct radeon_i2c_bus_rec *rec = &i2c->rec;
 813         int ret = 0;
 814
 815         mutex_lock(&i2c->mutex);
 816
 817         switch (rdev->family) {
 818         case CHIP_R100:
 819         case CHIP_RV100:
 820         case CHIP_RS100:
 821         case CHIP_RV200:
 822         case CHIP_RS200:
 823         case CHIP_R200:
 824         case CHIP_RV250:
 825         case CHIP_RS300:
 826         case CHIP_RV280:
 827         case CHIP_R300:
 828         case CHIP_R350:
 829         case CHIP_RV350:
 830         case CHIP_RV380:
 831         case CHIP_R420:
 832         case CHIP_R423:
 833         case CHIP_RV410:
 834         case CHIP_RS400:
 835         case CHIP_RS480:
 836                 ret = r100_hw_i2c_xfer(i2c_adap, msgs, num);
 837                 break;
 838         case CHIP_RS600:
 839         case CHIP_RS690:
 840         case CHIP_RS740:
 841                 /* XXX fill in hw i2c implementation */
 842                 break;
 843         case CHIP_RV515:
 844         case CHIP_R520:
 845         case CHIP_RV530:
 846         case CHIP_RV560:
 847         case CHIP_RV570:
 848         case CHIP_R580:
 849                 if (rec->mm_i2c)
 850                         ret = r100_hw_i2c_xfer(i2c_adap, msgs, num);
 851                 else
 852                         ret = r500_hw_i2c_xfer(i2c_adap, msgs, num);
 853                 break;
 854         case CHIP_R600:
 855         case CHIP_RV610:
 856         case CHIP_RV630:
 857         case CHIP_RV670:
 858                 /* XXX fill in hw i2c implementation */
 859                 break;
 860         case CHIP_RV620:
 861         case CHIP_RV635:
 862         case CHIP_RS780:
 863         case CHIP_RS880:
 864         case CHIP_RV770:
 865         case CHIP_RV730:
 866         case CHIP_RV710:
 867         case CHIP_RV740:
 868                 /* XXX fill in hw i2c implementation */
 869                 break;
 870         case CHIP_CEDAR:
 871         case CHIP_REDWOOD:
 872         case CHIP_JUNIPER:
 873         case CHIP_CYPRESS:
 874         case CHIP_HEMLOCK:
 875                 /* XXX fill in hw i2c implementation */
 876                 break;
 877         default:
 878                 DRM_ERROR("i2c: unhandled radeon chip\n");
 879                 ret = -EIO;
 880                 break;
 881         }
 882
 883         mutex_unlock(&i2c->mutex);
 884
 885         return ret;
 886 }
 887
 888 static u32 radeon_hw_i2c_func(struct i2c_adapter *adap)
 889 {
 890         return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
 891 }
 892
 893 static const struct i2c_algorithm radeon_i2c_algo = {
 894         .master_xfer = radeon_hw_i2c_xfer,
 895         .functionality = radeon_hw_i2c_func,
 896 };
 897
 898 static const struct i2c_algorithm radeon_atom_i2c_algo = {
 899         .master_xfer = radeon_atom_hw_i2c_xfer,
 900         .functionality = radeon_atom_hw_i2c_func,
 901 };
 902
 903 struct radeon_i2c_chan *radeon_i2c_create(struct drm_device *dev,
 904                                           struct radeon_i2c_bus_rec *rec,
 905                                           const char *name)
 906 {
 907         struct radeon_device *rdev = dev->dev_private;
 908         struct radeon_i2c_chan *i2c;
 909         int ret;
 910
 911         /* don't add the mm_i2c bus unless hw_i2c is enabled */
 912         if (rec->mm_i2c && (radeon_hw_i2c == 0))
 913                 return NULL;
 914
 915         i2c = kzalloc(sizeof(struct radeon_i2c_chan), GFP_KERNEL);
 916         if (i2c == NULL)
 917                 return NULL;
 918
 919         i2c->rec = *rec;
 920         i2c->adapter.owner = THIS_MODULE;
 921         i2c->adapter.dev.parent = dev->dev;
 922         i2c->dev = dev;
 923         i2c_set_adapdata(&i2c->adapter, i2c);
 924         mutex_init(&i2c->mutex);
 925         if (rec->mm_i2c ||
 926             (rec->hw_capable &&
 927              radeon_hw_i2c &&
 928              ((rdev->family <= CHIP_RS480) ||
 929               ((rdev->family >= CHIP_RV515) && (rdev->family <= CHIP_R580))))) {
 930                 /* set the radeon hw i2c adapter */
 931                 snprintf(i2c->adapter.name, sizeof(i2c->adapter.name),
 932                          "Radeon i2c hw bus %s", name);
 933                 i2c->adapter.algo = &radeon_i2c_algo;
 934                 ret = i2c_add_adapter(&i2c->adapter);
 935                 if (ret)
 936                         goto out_free;
 937         } else if (rec->hw_capable &&
 938                    radeon_hw_i2c &&
 939                    ASIC_IS_DCE3(rdev)) {
 940                 /* hw i2c using atom */
 941                 snprintf(i2c->adapter.name, sizeof(i2c->adapter.name),
 942                          "Radeon i2c hw bus %s", name);
 943                 i2c->adapter.algo = &radeon_atom_i2c_algo;
 944                 ret = i2c_add_adapter(&i2c->adapter);
 945                 if (ret)
 946                         goto out_free;
 947         } else {
 948                 /* set the radeon bit adapter */
 949                 snprintf(i2c->adapter.name, sizeof(i2c->adapter.name),
 950                          "Radeon i2c bit bus %s", name);
 951                 i2c->adapter.algo_data = &i2c->bit;
 952                 i2c->bit.pre_xfer = pre_xfer;
 953                 i2c->bit.post_xfer = post_xfer;
 954                 i2c->bit.setsda = set_data;
 955                 i2c->bit.setscl = set_clock;
 956                 i2c->bit.getsda = get_data;
 957                 i2c->bit.getscl = get_clock;
 958                 i2c->bit.udelay = 10;
 959                 i2c->bit.timeout = usecs_to_jiffies(2200);      /* from VESA */
 960                 i2c->bit.data = i2c;
 961                 ret = i2c_bit_add_bus(&i2c->adapter);
 962                 if (ret) {
 963                         DRM_ERROR("Failed to register bit i2c %s\n", name);
 964                         goto out_free;
 965                 }
 966         }
 967
 968         return i2c;
 969 out_free:
 970         kfree(i2c);
 971         return NULL;
 972
 973 }
 974
 975 void radeon_i2c_destroy(struct radeon_i2c_chan *i2c)
 976 {
 977         if (!i2c)
 978                 return;
 979         WARN_ON(i2c->has_aux);
 980         i2c_del_adapter(&i2c->adapter);
 981         kfree(i2c);
 982 }
 983
 984 /* Add the default buses */
 985 void radeon_i2c_init(struct radeon_device *rdev)
 986 {
 987         if (radeon_hw_i2c)
 988                 DRM_INFO("hw_i2c forced on, you may experience display detection problems!\n");
 989
 990         if (rdev->is_atom_bios)
 991                 radeon_atombios_i2c_init(rdev);
 992         else
 993                 radeon_combios_i2c_init(rdev);
 994 }
 995
 996 /* remove all the buses */
 997 void radeon_i2c_fini(struct radeon_device *rdev)
 998 {
 999         int i;
1000
1001         for (i = 0; i < RADEON_MAX_I2C_BUS; i++) {
1002                 if (rdev->i2c_bus[i]) {
1003                         radeon_i2c_destroy(rdev->i2c_bus[i]);
1004                         rdev->i2c_bus[i] = NULL;
1005                 }
1006         }
1007 }
1008
1009 /* Add additional buses */
1010 void radeon_i2c_add(struct radeon_device *rdev,
1011                     struct radeon_i2c_bus_rec *rec,
1012                     const char *name)
1013 {
1014         struct drm_device *dev = rdev->ddev;
1015         int i;
1016
1017         for (i = 0; i < RADEON_MAX_I2C_BUS; i++) {
1018                 if (!rdev->i2c_bus[i]) {
1019                         rdev->i2c_bus[i] = radeon_i2c_create(dev, rec, name);
1020                         return;
1021                 }
1022         }
1023 }
1024
1025 /* looks up bus based on id */
1026 struct radeon_i2c_chan *radeon_i2c_lookup(struct radeon_device *rdev,
1027                                           struct radeon_i2c_bus_rec *i2c_bus)
1028 {
1029         int i;
1030
1031         for (i = 0; i < RADEON_MAX_I2C_BUS; i++) {
1032                 if (rdev->i2c_bus[i] &&
1033                     (rdev->i2c_bus[i]->rec.i2c_id == i2c_bus->i2c_id)) {
1034                         return rdev->i2c_bus[i];
1035                 }
1036         }
1037         return NULL;
1038 }
1039
1040 void radeon_i2c_get_byte(struct radeon_i2c_chan *i2c_bus,
1041                          u8 slave_addr,
1042                          u8 addr,
1043                          u8 *val)
1044 {
1045         u8 out_buf[2];
1046         u8 in_buf[2];
1047         struct i2c_msg msgs[] = {
1048                 {
1049                         .addr = slave_addr,
1050                         .flags = 0,
1051                         .len = 1,
1052                         .buf = out_buf,
1053                 },
1054                 {
1055                         .addr = slave_addr,
1056                         .flags = I2C_M_RD,
1057                         .len = 1,
1058                         .buf = in_buf,
1059                 }
1060         };
1061
1062         out_buf[0] = addr;
1063         out_buf[1] = 0;
1064
1065         if (i2c_transfer(&i2c_bus->adapter, msgs, 2) == 2) {
1066                 *val = in_buf[0];
1067                 DRM_DEBUG("val = 0x%02x\n", *val);
1068         } else {
1069                 DRM_DEBUG("i2c 0x%02x 0x%02x read failed\n",
1070                           addr, *val);
1071         }
1072 }
1073
1074 void radeon_i2c_put_byte(struct radeon_i2c_chan *i2c_bus,
1075                          u8 slave_addr,
1076                          u8 addr,
1077                          u8 val)
1078 {
1079         uint8_t out_buf[2];
1080         struct i2c_msg msg = {
1081                 .addr = slave_addr,
1082                 .flags = 0,
1083                 .len = 2,
1084                 .buf = out_buf,
1085         };
1086
1087         out_buf[0] = addr;
1088         out_buf[1] = val;
1089
1090         if (i2c_transfer(&i2c_bus->adapter, &msg, 1) != 1)
1091                 DRM_DEBUG("i2c 0x%02x 0x%02x write failed\n",
1092                           addr, val);
1093 }
1094
1095 /* ddc router switching */
1096 void radeon_router_select_ddc_port(struct radeon_connector *radeon_connector)
1097 {
1098         u8 val;
1099
1100         if (!radeon_connector->router.ddc_valid)
1101                 return;
1102
1103         if (!radeon_connector->router_bus)
1104                 return;
1105
1106         radeon_i2c_get_byte(radeon_connector->router_bus,
1107                             radeon_connector->router.i2c_addr,
1108                             0x3, &val);
1109         val &= ~radeon_connector->router.ddc_mux_control_pin;
1110         radeon_i2c_put_byte(radeon_connector->router_bus,
1111                             radeon_connector->router.i2c_addr,
1112                             0x3, val);
1113         radeon_i2c_get_byte(radeon_connector->router_bus,
1114                             radeon_connector->router.i2c_addr,
1115                             0x1, &val);
1116         val &= ~radeon_connector->router.ddc_mux_control_pin;
1117         val |= radeon_connector->router.ddc_mux_state;
1118         radeon_i2c_put_byte(radeon_connector->router_bus,
1119                             radeon_connector->router.i2c_addr,
1120                             0x1, val);
1121 }
1122
1123 /* clock/data router switching */
1124 void radeon_router_select_cd_port(struct radeon_connector *radeon_connector)
1125 {
1126         u8 val;
1127
1128         if (!radeon_connector->router.cd_valid)
1129                 return;
1130
1131         if (!radeon_connector->router_bus)
1132                 return;
1133
1134         radeon_i2c_get_byte(radeon_connector->router_bus,
1135                             radeon_connector->router.i2c_addr,
1136                             0x3, &val);
1137         val &= ~radeon_connector->router.cd_mux_control_pin;
1138         radeon_i2c_put_byte(radeon_connector->router_bus,
1139                             radeon_connector->router.i2c_addr,
1140                             0x3, val);
1141         radeon_i2c_get_byte(radeon_connector->router_bus,
1142                             radeon_connector->router.i2c_addr,
1143                             0x1, &val);
1144         val &= ~radeon_connector->router.cd_mux_control_pin;
1145         val |= radeon_connector->router.cd_mux_state;
1146         radeon_i2c_put_byte(radeon_connector->router_bus,
1147                             radeon_connector->router.i2c_addr,
1148                             0x1, val);
1149 }
1150