drivers/gpu/drm/amd/amdgpu/mmhub_v4_1_0.c

   1 /*
   2  * Copyright 2023 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23
  24 #include "amdgpu.h"
  25 #include "mmhub_v4_1_0.h"
  26
  27 #include "mmhub/mmhub_4_1_0_offset.h"
  28 #include "mmhub/mmhub_4_1_0_sh_mask.h"
  29
  30 #include "soc15_common.h"
  31 #include "soc24_enum.h"
  32
  33 #define regMMVM_L2_CNTL3_DEFAULT                                0x80100007
  34 #define regMMVM_L2_CNTL4_DEFAULT                                0x000000c1
  35 #define regMMVM_L2_CNTL5_DEFAULT                                0x00003fe0
  36
  37 static const char *mmhub_client_ids_v4_1_0[][2] = {
  38         [0][0] = "VMC",
  39         [4][0] = "DCEDMC",
  40         [5][0] = "DCEVGA",
  41         [6][0] = "MP0",
  42         [7][0] = "MP1",
  43         [8][0] = "MPIO",
  44         [16][0] = "HDP",
  45         [17][0] = "LSDMA",
  46         [18][0] = "JPEG",
  47         [19][0] = "VCNU0",
  48         [21][0] = "VSCH",
  49         [22][0] = "VCNU1",
  50         [23][0] = "VCN1",
  51         [32+20][0] = "VCN0",
  52         [2][1] = "DBGUNBIO",
  53         [3][1] = "DCEDWB",
  54         [4][1] = "DCEDMC",
  55         [5][1] = "DCEVGA",
  56         [6][1] = "MP0",
  57         [7][1] = "MP1",
  58         [8][1] = "MPIO",
  59         [10][1] = "DBGU0",
  60         [11][1] = "DBGU1",
  61         [12][1] = "DBGU2",
  62         [13][1] = "DBGU3",
  63         [14][1] = "XDP",
  64         [15][1] = "OSSSYS",
  65         [16][1] = "HDP",
  66         [17][1] = "LSDMA",
  67         [18][1] = "JPEG",
  68         [19][1] = "VCNU0",
  69         [20][1] = "VCN0",
  70         [21][1] = "VSCH",
  71         [22][1] = "VCNU1",
  72         [23][1] = "VCN1",
  73 };
  74
  75 static uint32_t mmhub_v4_1_0_get_invalidate_req(unsigned int vmid,
  76                                                 uint32_t flush_type)
  77 {
  78         u32 req = 0;
  79
  80         /* invalidate using legacy mode on vmid*/
  81         req = REG_SET_FIELD(req, MMVM_INVALIDATE_ENG0_REQ,
  82                             PER_VMID_INVALIDATE_REQ, 1 << vmid);
  83         req = REG_SET_FIELD(req, MMVM_INVALIDATE_ENG0_REQ, FLUSH_TYPE, flush_type);
  84         req = REG_SET_FIELD(req, MMVM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PTES, 1);
  85         req = REG_SET_FIELD(req, MMVM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE0, 1);
  86         req = REG_SET_FIELD(req, MMVM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE1, 1);
  87         req = REG_SET_FIELD(req, MMVM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE2, 1);
  88         req = REG_SET_FIELD(req, MMVM_INVALIDATE_ENG0_REQ, INVALIDATE_L1_PTES, 1);
  89         req = REG_SET_FIELD(req, MMVM_INVALIDATE_ENG0_REQ,
  90                             CLEAR_PROTECTION_FAULT_STATUS_ADDR, 0);
  91
  92         return req;
  93 }
  94
  95 static void
  96 mmhub_v4_1_0_print_l2_protection_fault_status(struct amdgpu_device *adev,
  97                                               uint32_t status)
  98 {
  99         uint32_t cid, rw;
 100         const char *mmhub_cid = NULL;
 101
 102         cid = REG_GET_FIELD(status,
 103                             MMVM_L2_PROTECTION_FAULT_STATUS_LO32, CID);
 104         rw = REG_GET_FIELD(status,
 105                            MMVM_L2_PROTECTION_FAULT_STATUS_LO32, RW);
 106
 107         dev_err(adev->dev,
 108                 "MMVM_L2_PROTECTION_FAULT_STATUS_LO32:0x%08X\n",
 109                 status);
 110         switch (adev->ip_versions[MMHUB_HWIP][0]) {
 111         case IP_VERSION(4, 1, 0):
 112                 mmhub_cid = mmhub_client_ids_v4_1_0[cid][rw];
 113                 break;
 114         default:
 115                 mmhub_cid = NULL;
 116                 break;
 117         }
 118         dev_err(adev->dev, "\t Faulty UTCL2 client ID: %s (0x%x)\n",
 119                 mmhub_cid ? mmhub_cid : "unknown", cid);
 120         dev_err(adev->dev, "\t MORE_FAULTS: 0x%lx\n",
 121                 REG_GET_FIELD(status,
 122                 MMVM_L2_PROTECTION_FAULT_STATUS_LO32, MORE_FAULTS));
 123         dev_err(adev->dev, "\t WALKER_ERROR: 0x%lx\n",
 124                 REG_GET_FIELD(status,
 125                 MMVM_L2_PROTECTION_FAULT_STATUS_LO32, WALKER_ERROR));
 126         dev_err(adev->dev, "\t PERMISSION_FAULTS: 0x%lx\n",
 127                 REG_GET_FIELD(status,
 128                 MMVM_L2_PROTECTION_FAULT_STATUS_LO32, PERMISSION_FAULTS));
 129         dev_err(adev->dev, "\t MAPPING_ERROR: 0x%lx\n",
 130                 REG_GET_FIELD(status,
 131                 MMVM_L2_PROTECTION_FAULT_STATUS_LO32, MAPPING_ERROR));
 132         dev_err(adev->dev, "\t RW: 0x%x\n", rw);
 133 }
 134
 135 static void mmhub_v4_1_0_setup_vm_pt_regs(struct amdgpu_device *adev,
 136                                           uint32_t vmid, uint64_t page_table_base)
 137 {
 138         struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_MMHUB0(0)];
 139
 140         WREG32_SOC15_OFFSET(MMHUB, 0, regMMVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32,
 141                             hub->ctx_addr_distance * vmid,
 142                             lower_32_bits(page_table_base));
 143
 144         WREG32_SOC15_OFFSET(MMHUB, 0, regMMVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32,
 145                             hub->ctx_addr_distance * vmid,
 146                             upper_32_bits(page_table_base));
 147 }
 148
 149 static void mmhub_v4_1_0_init_gart_aperture_regs(struct amdgpu_device *adev)
 150 {
 151         uint64_t pt_base = amdgpu_gmc_pd_addr(adev->gart.bo);
 152
 153         mmhub_v4_1_0_setup_vm_pt_regs(adev, 0, pt_base);
 154
 155         WREG32_SOC15(MMHUB, 0, regMMVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32,
 156                      (u32)(adev->gmc.gart_start >> 12));
 157         WREG32_SOC15(MMHUB, 0, regMMVM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32,
 158                      (u32)(adev->gmc.gart_start >> 44));
 159
 160         WREG32_SOC15(MMHUB, 0, regMMVM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32,
 161                      (u32)(adev->gmc.gart_end >> 12));
 162         WREG32_SOC15(MMHUB, 0, regMMVM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32,
 163                      (u32)(adev->gmc.gart_end >> 44));
 164 }
 165
 166 static void mmhub_v4_1_0_init_system_aperture_regs(struct amdgpu_device *adev)
 167 {
 168         uint64_t value;
 169         uint32_t tmp;
 170
 171         /*
 172          * the new L1 policy will block SRIOV guest from writing
 173          * these regs, and they will be programed at host.
 174          * so skip programing these regs.
 175          */
 176         if (amdgpu_sriov_vf(adev))
 177                 return;
 178
 179         /* Program the AGP BAR */
 180         WREG32_SOC15(MMHUB, 0, regMMMC_VM_AGP_BASE, 0);
 181         WREG32_SOC15(MMHUB, 0, regMMMC_VM_AGP_BOT, adev->gmc.agp_start >> 24);
 182         WREG32_SOC15(MMHUB, 0, regMMMC_VM_AGP_TOP, adev->gmc.agp_end >> 24);
 183
 184         /* Program the system aperture low logical page number. */
 185         WREG32_SOC15(MMHUB, 0, regMMMC_VM_SYSTEM_APERTURE_LOW_ADDR,
 186                      min(adev->gmc.fb_start, adev->gmc.agp_start) >> 18);
 187         WREG32_SOC15(MMHUB, 0, regMMMC_VM_SYSTEM_APERTURE_HIGH_ADDR,
 188                      max(adev->gmc.fb_end, adev->gmc.agp_end) >> 18);
 189
 190         /* Set default page address. */
 191         value = adev->mem_scratch.gpu_addr - adev->gmc.vram_start +
 192                 adev->vm_manager.vram_base_offset;
 193         WREG32_SOC15(MMHUB, 0, regMMMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB,
 194                      (u32)(value >> 12));
 195         WREG32_SOC15(MMHUB, 0, regMMMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB,
 196                      (u32)(value >> 44));
 197
 198         /* Program "protection fault". */
 199         WREG32_SOC15(MMHUB, 0, regMMVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32,
 200                      (u32)(adev->dummy_page_addr >> 12));
 201         WREG32_SOC15(MMHUB, 0, regMMVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32,
 202                      (u32)((u64)adev->dummy_page_addr >> 44));
 203
 204         tmp = RREG32_SOC15(MMHUB, 0, regMMVM_L2_PROTECTION_FAULT_CNTL2);
 205         tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL2,
 206                             ACTIVE_PAGE_MIGRATION_PTE_READ_RETRY, 1);
 207         WREG32_SOC15(MMHUB, 0, regMMVM_L2_PROTECTION_FAULT_CNTL2, tmp);
 208 }
 209
 210 static void mmhub_v4_1_0_init_tlb_regs(struct amdgpu_device *adev)
 211 {
 212         uint32_t tmp;
 213
 214         /* Setup TLB control */
 215         tmp = RREG32_SOC15(MMHUB, 0, regMMMC_VM_MX_L1_TLB_CNTL);
 216
 217         tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 1);
 218         tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL, SYSTEM_ACCESS_MODE, 3);
 219         tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL,
 220                             ENABLE_ADVANCED_DRIVER_MODEL, 1);
 221         tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL,
 222                             SYSTEM_APERTURE_UNMAPPED_ACCESS, 0);
 223         tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL, ECO_BITS, 0);
 224         tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL,
 225                             MTYPE, MTYPE_UC); /* UC, uncached */
 226
 227         WREG32_SOC15(MMHUB, 0, regMMMC_VM_MX_L1_TLB_CNTL, tmp);
 228 }
 229
 230 static void mmhub_v4_1_0_init_cache_regs(struct amdgpu_device *adev)
 231 {
 232         uint32_t tmp;
 233
 234         /* These registers are not accessible to VF-SRIOV.
 235          * The PF will program them instead.
 236          */
 237         if (amdgpu_sriov_vf(adev))
 238                 return;
 239
 240         /* Setup L2 cache */
 241         tmp = RREG32_SOC15(MMHUB, 0, regMMVM_L2_CNTL);
 242         tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL, ENABLE_L2_CACHE, 1);
 243         tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING, 0);
 244         tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL,
 245                             ENABLE_DEFAULT_PAGE_OUT_TO_SYSTEM_MEMORY, 1);
 246         /* XXX for emulation, Refer to closed source code.*/
 247         tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL, L2_PDE0_CACHE_TAG_GENERATION_MODE,
 248                             0);
 249         tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL, PDE_FAULT_CLASSIFICATION, 0);
 250         tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL, CONTEXT1_IDENTITY_ACCESS_MODE, 1);
 251         tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL, IDENTITY_MODE_FRAGMENT_SIZE, 0);
 252         WREG32_SOC15(MMHUB, 0, regMMVM_L2_CNTL, tmp);
 253
 254         tmp = RREG32_SOC15(MMHUB, 0, regMMVM_L2_CNTL2);
 255         tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL2, INVALIDATE_ALL_L1_TLBS, 1);
 256         tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL2, INVALIDATE_L2_CACHE, 1);
 257         WREG32_SOC15(MMHUB, 0, regMMVM_L2_CNTL2, tmp);
 258
 259         tmp = regMMVM_L2_CNTL3_DEFAULT;
 260         if (adev->gmc.translate_further) {
 261                 tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL3, BANK_SELECT, 12);
 262                 tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL3,
 263                                     L2_CACHE_BIGK_FRAGMENT_SIZE, 9);
 264         } else {
 265                 tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL3, BANK_SELECT, 9);
 266                 tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL3,
 267                                     L2_CACHE_BIGK_FRAGMENT_SIZE, 6);
 268         }
 269         WREG32_SOC15(MMHUB, 0, regMMVM_L2_CNTL3, tmp);
 270
 271         tmp = regMMVM_L2_CNTL4_DEFAULT;
 272         tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL4, VMC_TAP_PDE_REQUEST_PHYSICAL, 0);
 273         tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL4, VMC_TAP_PTE_REQUEST_PHYSICAL, 0);
 274         WREG32_SOC15(MMHUB, 0, regMMVM_L2_CNTL4, tmp);
 275
 276         tmp = regMMVM_L2_CNTL5_DEFAULT;
 277         tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL5, L2_CACHE_SMALLK_FRAGMENT_SIZE, 0);
 278         WREG32_SOC15(MMHUB, 0, regMMVM_L2_CNTL5, tmp);
 279 }
 280
 281 static void mmhub_v4_1_0_enable_system_domain(struct amdgpu_device *adev)
 282 {
 283         uint32_t tmp;
 284
 285         tmp = RREG32_SOC15(MMHUB, 0, regMMVM_CONTEXT0_CNTL);
 286         tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT0_CNTL, ENABLE_CONTEXT, 1);
 287         tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT0_CNTL, PAGE_TABLE_DEPTH, 0);
 288         tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT0_CNTL,
 289                             RETRY_PERMISSION_OR_INVALID_PAGE_FAULT, 0);
 290         WREG32_SOC15(MMHUB, 0, regMMVM_CONTEXT0_CNTL, tmp);
 291 }
 292
 293 static void mmhub_v4_1_0_disable_identity_aperture(struct amdgpu_device *adev)
 294 {
 295         /* These registers are not accessible to VF-SRIOV.
 296          * The PF will program them instead.
 297          */
 298         if (amdgpu_sriov_vf(adev))
 299                 return;
 300
 301         WREG32_SOC15(MMHUB, 0,
 302                      regMMVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32,
 303                      0xFFFFFFFF);
 304         WREG32_SOC15(MMHUB, 0,
 305                      regMMVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32,
 306                      0x0000000F);
 307
 308         WREG32_SOC15(MMHUB, 0,
 309                      regMMVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_LO32, 0);
 310         WREG32_SOC15(MMHUB, 0,
 311                      regMMVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_HI32, 0);
 312
 313         WREG32_SOC15(MMHUB, 0, regMMVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_LO32,
 314                      0);
 315         WREG32_SOC15(MMHUB, 0, regMMVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_HI32,
 316                      0);
 317 }
 318
 319 static void mmhub_v4_1_0_setup_vmid_config(struct amdgpu_device *adev)
 320 {
 321         struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_MMHUB0(0)];
 322         int i;
 323         uint32_t tmp;
 324
 325         for (i = 0; i <= 14; i++) {
 326                 tmp = RREG32_SOC15_OFFSET(MMHUB, 0, regMMVM_CONTEXT1_CNTL, i);
 327                 tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL, ENABLE_CONTEXT, 1);
 328                 tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL, PAGE_TABLE_DEPTH,
 329                                     adev->vm_manager.num_level);
 330                 tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL,
 331                                     RANGE_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
 332                 tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL,
 333                                     DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT,
 334                                     1);
 335                 tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL,
 336                                     PDE0_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
 337                 tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL,
 338                                     VALID_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
 339                 tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL,
 340                                     READ_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
 341                 tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL,
 342                                     WRITE_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
 343                 tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL,
 344                                     EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
 345                 tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL,
 346                                     PAGE_TABLE_BLOCK_SIZE,
 347                                     adev->vm_manager.block_size - 9);
 348                 /* Send no-retry XNACK on fault to suppress VM fault storm. */
 349                 tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL,
 350                                     RETRY_PERMISSION_OR_INVALID_PAGE_FAULT,
 351                                     !amdgpu_noretry);
 352                 WREG32_SOC15_OFFSET(MMHUB, 0, regMMVM_CONTEXT1_CNTL,
 353                                     i * hub->ctx_distance, tmp);
 354                 WREG32_SOC15_OFFSET(MMHUB, 0, regMMVM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32,
 355                                     i * hub->ctx_addr_distance, 0);
 356                 WREG32_SOC15_OFFSET(MMHUB, 0, regMMVM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32,
 357                                     i * hub->ctx_addr_distance, 0);
 358                 WREG32_SOC15_OFFSET(MMHUB, 0, regMMVM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32,
 359                                     i * hub->ctx_addr_distance,
 360                                     lower_32_bits(adev->vm_manager.max_pfn - 1));
 361                 WREG32_SOC15_OFFSET(MMHUB, 0, regMMVM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32,
 362                                     i * hub->ctx_addr_distance,
 363                                     upper_32_bits(adev->vm_manager.max_pfn - 1));
 364         }
 365
 366         hub->vm_cntx_cntl = tmp;
 367 }
 368
 369 static void mmhub_v4_1_0_program_invalidation(struct amdgpu_device *adev)
 370 {
 371         struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_MMHUB0(0)];
 372         unsigned i;
 373
 374         for (i = 0; i < 18; ++i) {
 375                 WREG32_SOC15_OFFSET(MMHUB, 0, regMMVM_INVALIDATE_ENG0_ADDR_RANGE_LO32,
 376                                     i * hub->eng_addr_distance, 0xffffffff);
 377                 WREG32_SOC15_OFFSET(MMHUB, 0, regMMVM_INVALIDATE_ENG0_ADDR_RANGE_HI32,
 378                                     i * hub->eng_addr_distance, 0x1f);
 379         }
 380 }
 381
 382 static int mmhub_v4_1_0_gart_enable(struct amdgpu_device *adev)
 383 {
 384         /* GART Enable. */
 385         mmhub_v4_1_0_init_gart_aperture_regs(adev);
 386         mmhub_v4_1_0_init_system_aperture_regs(adev);
 387         mmhub_v4_1_0_init_tlb_regs(adev);
 388         mmhub_v4_1_0_init_cache_regs(adev);
 389
 390         mmhub_v4_1_0_enable_system_domain(adev);
 391         mmhub_v4_1_0_disable_identity_aperture(adev);
 392         mmhub_v4_1_0_setup_vmid_config(adev);
 393         mmhub_v4_1_0_program_invalidation(adev);
 394
 395         return 0;
 396 }
 397
 398 static void mmhub_v4_1_0_gart_disable(struct amdgpu_device *adev)
 399 {
 400         struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_MMHUB0(0)];
 401         u32 tmp;
 402         u32 i;
 403
 404         /* Disable all tables */
 405         for (i = 0; i < 16; i++)
 406                 WREG32_SOC15_OFFSET(MMHUB, 0, regMMVM_CONTEXT0_CNTL,
 407                                     i * hub->ctx_distance, 0);
 408
 409         /* Setup TLB control */
 410         tmp = RREG32_SOC15(MMHUB, 0, regMMMC_VM_MX_L1_TLB_CNTL);
 411         tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 0);
 412         tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL,
 413                             ENABLE_ADVANCED_DRIVER_MODEL, 0);
 414         WREG32_SOC15(MMHUB, 0, regMMMC_VM_MX_L1_TLB_CNTL, tmp);
 415
 416         /* Setup L2 cache */
 417         tmp = RREG32_SOC15(MMHUB, 0, regMMVM_L2_CNTL);
 418         tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL, ENABLE_L2_CACHE, 0);
 419         WREG32_SOC15(MMHUB, 0, regMMVM_L2_CNTL, tmp);
 420         WREG32_SOC15(MMHUB, 0, regMMVM_L2_CNTL3, 0);
 421 }
 422
 423 /**
 424  * mmhub_v4_1_0_set_fault_enable_default - update GART/VM fault handling
 425  *
 426  * @adev: amdgpu_device pointer
 427  * @value: true redirects VM faults to the default page
 428  */
 429 static void
 430 mmhub_v4_1_0_set_fault_enable_default(struct amdgpu_device *adev, bool value)
 431 {
 432         u32 tmp;
 433
 434         /* These registers are not accessible to VF-SRIOV.
 435          * The PF will program them instead.
 436          */
 437         if (amdgpu_sriov_vf(adev))
 438                 return;
 439
 440         tmp = RREG32_SOC15(MMHUB, 0, regMMVM_L2_PROTECTION_FAULT_CNTL);
 441         tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL,
 442                             RANGE_PROTECTION_FAULT_ENABLE_DEFAULT, value);
 443         tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL,
 444                             PDE0_PROTECTION_FAULT_ENABLE_DEFAULT, value);
 445         tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL,
 446                             PDE1_PROTECTION_FAULT_ENABLE_DEFAULT, value);
 447         tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL,
 448                             PDE2_PROTECTION_FAULT_ENABLE_DEFAULT, value);
 449         tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL,
 450                             TRANSLATE_FURTHER_PROTECTION_FAULT_ENABLE_DEFAULT,
 451                             value);
 452         tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL,
 453                             NACK_PROTECTION_FAULT_ENABLE_DEFAULT, value);
 454         tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL,
 455                             DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT, value);
 456         tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL,
 457                             VALID_PROTECTION_FAULT_ENABLE_DEFAULT, value);
 458         tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL,
 459                             READ_PROTECTION_FAULT_ENABLE_DEFAULT, value);
 460         tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL,
 461                             WRITE_PROTECTION_FAULT_ENABLE_DEFAULT, value);
 462         tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL,
 463                             EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT, value);
 464         if (!value) {
 465                 tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL,
 466                                 CRASH_ON_NO_RETRY_FAULT, 1);
 467                 tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL,
 468                                 CRASH_ON_RETRY_FAULT, 1);
 469         }
 470         WREG32_SOC15(MMHUB, 0, regMMVM_L2_PROTECTION_FAULT_CNTL, tmp);
 471 }
 472
 473 static const struct amdgpu_vmhub_funcs mmhub_v4_1_0_vmhub_funcs = {
 474         .print_l2_protection_fault_status = mmhub_v4_1_0_print_l2_protection_fault_status,
 475         .get_invalidate_req = mmhub_v4_1_0_get_invalidate_req,
 476 };
 477
 478 static void mmhub_v4_1_0_init(struct amdgpu_device *adev)
 479 {
 480         struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_MMHUB0(0)];
 481
 482         hub->ctx0_ptb_addr_lo32 =
 483                 SOC15_REG_OFFSET(MMHUB, 0,
 484                                  regMMVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32);
 485         hub->ctx0_ptb_addr_hi32 =
 486                 SOC15_REG_OFFSET(MMHUB, 0,
 487                                  regMMVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32);
 488         hub->vm_inv_eng0_sem =
 489                 SOC15_REG_OFFSET(MMHUB, 0, regMMVM_INVALIDATE_ENG0_SEM);
 490         hub->vm_inv_eng0_req =
 491                 SOC15_REG_OFFSET(MMHUB, 0, regMMVM_INVALIDATE_ENG0_REQ);
 492         hub->vm_inv_eng0_ack =
 493                 SOC15_REG_OFFSET(MMHUB, 0, regMMVM_INVALIDATE_ENG0_ACK);
 494         hub->vm_context0_cntl =
 495                 SOC15_REG_OFFSET(MMHUB, 0, regMMVM_CONTEXT0_CNTL);
 496         hub->vm_l2_pro_fault_status =
 497                 SOC15_REG_OFFSET(MMHUB, 0, regMMVM_L2_PROTECTION_FAULT_STATUS_LO32);
 498         hub->vm_l2_pro_fault_cntl =
 499                 SOC15_REG_OFFSET(MMHUB, 0, regMMVM_L2_PROTECTION_FAULT_CNTL);
 500
 501         hub->ctx_distance = regMMVM_CONTEXT1_CNTL - regMMVM_CONTEXT0_CNTL;
 502         hub->ctx_addr_distance = regMMVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32 -
 503                 regMMVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32;
 504         hub->eng_distance = regMMVM_INVALIDATE_ENG1_REQ -
 505                 regMMVM_INVALIDATE_ENG0_REQ;
 506         hub->eng_addr_distance = regMMVM_INVALIDATE_ENG1_ADDR_RANGE_LO32 -
 507                 regMMVM_INVALIDATE_ENG0_ADDR_RANGE_LO32;
 508
 509         hub->vm_cntx_cntl_vm_fault = MMVM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
 510                 MMVM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
 511                 MMVM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
 512                 MMVM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
 513                 MMVM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
 514                 MMVM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
 515                 MMVM_CONTEXT1_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK;
 516
 517         hub->vm_l2_bank_select_reserved_cid2 =
 518                 SOC15_REG_OFFSET(MMHUB, 0, regMMVM_L2_BANK_SELECT_RESERVED_CID2);
 519
 520         hub->vm_contexts_disable =
 521                 SOC15_REG_OFFSET(MMHUB, 0, regMMVM_CONTEXTS_DISABLE);
 522
 523         hub->vmhub_funcs = &mmhub_v4_1_0_vmhub_funcs;
 524 }
 525
 526 static u64 mmhub_v4_1_0_get_fb_location(struct amdgpu_device *adev)
 527 {
 528         u64 base;
 529
 530         base = RREG32_SOC15(MMHUB, 0, regMMMC_VM_FB_LOCATION_BASE);
 531
 532         base &= MMMC_VM_FB_LOCATION_BASE__FB_BASE_MASK;
 533         base <<= 24;
 534
 535         return base;
 536 }
 537
 538 static u64 mmhub_v4_1_0_get_mc_fb_offset(struct amdgpu_device *adev)
 539 {
 540         return (u64)RREG32_SOC15(MMHUB, 0, regMMMC_VM_FB_OFFSET) << 24;
 541 }
 542
 543 static void
 544 mmhub_v4_1_0_update_medium_grain_clock_gating(struct amdgpu_device *adev,
 545                                               bool enable)
 546 {
 547 #if 0
 548         uint32_t def, data;
 549 #endif
 550         uint32_t def1, data1, def2 = 0, data2 = 0;
 551 #if 0
 552         def  = data  = RREG32_SOC15(MMHUB, 0, regMM_ATC_L2_MISC_CG);
 553 #endif
 554         def1 = data1 = RREG32_SOC15(MMHUB, 0, regDAGB0_CNTL_MISC2);
 555         def2 = data2 = RREG32_SOC15(MMHUB, 0, regDAGB1_CNTL_MISC2);
 556
 557         if (enable) {
 558 #if 0
 559                 data |= MM_ATC_L2_MISC_CG__ENABLE_MASK;
 560 #endif
 561                 data1 &= ~(DAGB0_CNTL_MISC2__DISABLE_RDRET_TAP_CHAIN_FGCG_MASK |
 562                            DAGB0_CNTL_MISC2__DISABLE_WRRET_TAP_CHAIN_FGCG_MASK);
 563
 564                 data2 &= ~(DAGB1_CNTL_MISC2__DISABLE_RDRET_TAP_CHAIN_FGCG_MASK |
 565                            DAGB1_CNTL_MISC2__DISABLE_WRRET_TAP_CHAIN_FGCG_MASK);
 566         } else {
 567 #if 0
 568                 data &= ~MM_ATC_L2_MISC_CG__ENABLE_MASK;
 569 #endif
 570                 data1 |= (DAGB0_CNTL_MISC2__DISABLE_RDRET_TAP_CHAIN_FGCG_MASK |
 571                           DAGB0_CNTL_MISC2__DISABLE_WRRET_TAP_CHAIN_FGCG_MASK);
 572
 573                 data2 |= (DAGB1_CNTL_MISC2__DISABLE_RDRET_TAP_CHAIN_FGCG_MASK |
 574                           DAGB1_CNTL_MISC2__DISABLE_WRRET_TAP_CHAIN_FGCG_MASK);
 575         }
 576
 577 #if 0
 578         if (def != data)
 579                 WREG32_SOC15(MMHUB, 0, regMM_ATC_L2_MISC_CG, data);
 580 #endif
 581         if (def1 != data1)
 582                 WREG32_SOC15(MMHUB, 0, regDAGB0_CNTL_MISC2, data1);
 583
 584         if (def2 != data2)
 585                 WREG32_SOC15(MMHUB, 0, regDAGB1_CNTL_MISC2, data2);
 586 }
 587
 588 static void
 589 mmhub_v4_1_0_update_medium_grain_light_sleep(struct amdgpu_device *adev,
 590                                              bool enable)
 591 {
 592 #if 0
 593         uint32_t def, data;
 594
 595         def = data = RREG32_SOC15(MMHUB, 0, regMM_ATC_L2_MISC_CG);
 596
 597         if (enable)
 598                 data |= MM_ATC_L2_MISC_CG__MEM_LS_ENABLE_MASK;
 599         else
 600                 data &= ~MM_ATC_L2_MISC_CG__MEM_LS_ENABLE_MASK;
 601
 602         if (def != data)
 603                 WREG32_SOC15(MMHUB, 0, regMM_ATC_L2_MISC_CG, data);
 604 #endif
 605 }
 606
 607 static int mmhub_v4_1_0_set_clockgating(struct amdgpu_device *adev,
 608                                         enum amd_clockgating_state state)
 609 {
 610         if (amdgpu_sriov_vf(adev))
 611                 return 0;
 612
 613         if (adev->cg_flags & AMD_CG_SUPPORT_MC_MGCG)
 614                 mmhub_v4_1_0_update_medium_grain_clock_gating(adev,
 615                                 state == AMD_CG_STATE_GATE);
 616
 617         if (adev->cg_flags & AMD_CG_SUPPORT_MC_LS)
 618                 mmhub_v4_1_0_update_medium_grain_light_sleep(adev,
 619                                 state == AMD_CG_STATE_GATE);
 620
 621         return 0;
 622 }
 623
 624 static void mmhub_v4_1_0_get_clockgating(struct amdgpu_device *adev, u64 *flags)
 625 {
 626 #if 0
 627         int data;
 628
 629         if (amdgpu_sriov_vf(adev))
 630                 *flags = 0;
 631
 632         data = RREG32_SOC15(MMHUB, 0, regMM_ATC_L2_MISC_CG);
 633
 634         /* AMD_CG_SUPPORT_MC_MGCG */
 635         if (data & MM_ATC_L2_MISC_CG__ENABLE_MASK)
 636                 *flags |= AMD_CG_SUPPORT_MC_MGCG;
 637
 638         /* AMD_CG_SUPPORT_MC_LS */
 639         if (data & MM_ATC_L2_MISC_CG__MEM_LS_ENABLE_MASK)
 640                 *flags |= AMD_CG_SUPPORT_MC_LS;
 641 #endif
 642 }
 643
 644 const struct amdgpu_mmhub_funcs mmhub_v4_1_0_funcs = {
 645         .init = mmhub_v4_1_0_init,
 646         .get_fb_location = mmhub_v4_1_0_get_fb_location,
 647         .get_mc_fb_offset = mmhub_v4_1_0_get_mc_fb_offset,
 648         .gart_enable = mmhub_v4_1_0_gart_enable,
 649         .set_fault_enable_default = mmhub_v4_1_0_set_fault_enable_default,
 650         .gart_disable = mmhub_v4_1_0_gart_disable,
 651         .set_clockgating = mmhub_v4_1_0_set_clockgating,
 652         .get_clockgating = mmhub_v4_1_0_get_clockgating,
 653         .setup_vm_pt_regs = mmhub_v4_1_0_setup_vm_pt_regs,
 654 };