drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c

   1 /*
   2  * Copyright 2018 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  *
  23  */
  24 #include <linux/debugfs.h>
  25 #include <linux/list.h>
  26 #include <linux/module.h>
  27 #include <linux/uaccess.h>
  28 #include <linux/reboot.h>
  29 #include <linux/syscalls.h>
  30 #include <linux/pm_runtime.h>
  31
  32 #include "amdgpu.h"
  33 #include "amdgpu_ras.h"
  34 #include "amdgpu_atomfirmware.h"
  35 #include "amdgpu_xgmi.h"
  36 #include "ivsrcid/nbio/irqsrcs_nbif_7_4.h"
  37 #include "nbio_v4_3.h"
  38 #include "nbio_v7_9.h"
  39 #include "atom.h"
  40 #include "amdgpu_reset.h"
  41
  42 #ifdef CONFIG_X86_MCE_AMD
  43 #include <asm/mce.h>
  44
  45 static bool notifier_registered;
  46 #endif
  47 static const char *RAS_FS_NAME = "ras";
  48
  49 const char *ras_error_string[] = {
  50         "none",
  51         "parity",
  52         "single_correctable",
  53         "multi_uncorrectable",
  54         "poison",
  55 };
  56
  57 const char *ras_block_string[] = {
  58         "umc",
  59         "sdma",
  60         "gfx",
  61         "mmhub",
  62         "athub",
  63         "pcie_bif",
  64         "hdp",
  65         "xgmi_wafl",
  66         "df",
  67         "smn",
  68         "sem",
  69         "mp0",
  70         "mp1",
  71         "fuse",
  72         "mca",
  73         "vcn",
  74         "jpeg",
  75 };
  76
  77 const char *ras_mca_block_string[] = {
  78         "mca_mp0",
  79         "mca_mp1",
  80         "mca_mpio",
  81         "mca_iohc",
  82 };
  83
  84 struct amdgpu_ras_block_list {
  85         /* ras block link */
  86         struct list_head node;
  87
  88         struct amdgpu_ras_block_object *ras_obj;
  89 };
  90
  91 const char *get_ras_block_str(struct ras_common_if *ras_block)
  92 {
  93         if (!ras_block)
  94                 return "NULL";
  95
  96         if (ras_block->block >= AMDGPU_RAS_BLOCK_COUNT)
  97                 return "OUT OF RANGE";
  98
  99         if (ras_block->block == AMDGPU_RAS_BLOCK__MCA)
 100                 return ras_mca_block_string[ras_block->sub_block_index];
 101
 102         return ras_block_string[ras_block->block];
 103 }
 104
 105 #define ras_block_str(_BLOCK_) \
 106         (((_BLOCK_) < ARRAY_SIZE(ras_block_string)) ? ras_block_string[_BLOCK_] : "Out Of Range")
 107
 108 #define ras_err_str(i) (ras_error_string[ffs(i)])
 109
 110 #define RAS_DEFAULT_FLAGS (AMDGPU_RAS_FLAG_INIT_BY_VBIOS)
 111
 112 /* inject address is 52 bits */
 113 #define RAS_UMC_INJECT_ADDR_LIMIT       (0x1ULL << 52)
 114
 115 /* typical ECC bad page rate is 1 bad page per 100MB VRAM */
 116 #define RAS_BAD_PAGE_COVER              (100 * 1024 * 1024ULL)
 117
 118 enum amdgpu_ras_retire_page_reservation {
 119         AMDGPU_RAS_RETIRE_PAGE_RESERVED,
 120         AMDGPU_RAS_RETIRE_PAGE_PENDING,
 121         AMDGPU_RAS_RETIRE_PAGE_FAULT,
 122 };
 123
 124 atomic_t amdgpu_ras_in_intr = ATOMIC_INIT(0);
 125
 126 static bool amdgpu_ras_check_bad_page_unlock(struct amdgpu_ras *con,
 127                                 uint64_t addr);
 128 static bool amdgpu_ras_check_bad_page(struct amdgpu_device *adev,
 129                                 uint64_t addr);
 130 #ifdef CONFIG_X86_MCE_AMD
 131 static void amdgpu_register_bad_pages_mca_notifier(struct amdgpu_device *adev);
 132 struct mce_notifier_adev_list {
 133         struct amdgpu_device *devs[MAX_GPU_INSTANCE];
 134         int num_gpu;
 135 };
 136 static struct mce_notifier_adev_list mce_adev_list;
 137 #endif
 138
 139 void amdgpu_ras_set_error_query_ready(struct amdgpu_device *adev, bool ready)
 140 {
 141         if (adev && amdgpu_ras_get_context(adev))
 142                 amdgpu_ras_get_context(adev)->error_query_ready = ready;
 143 }
 144
 145 static bool amdgpu_ras_get_error_query_ready(struct amdgpu_device *adev)
 146 {
 147         if (adev && amdgpu_ras_get_context(adev))
 148                 return amdgpu_ras_get_context(adev)->error_query_ready;
 149
 150         return false;
 151 }
 152
 153 static int amdgpu_reserve_page_direct(struct amdgpu_device *adev, uint64_t address)
 154 {
 155         struct ras_err_data err_data;
 156         struct eeprom_table_record err_rec;
 157         int ret;
 158
 159         if ((address >= adev->gmc.mc_vram_size) ||
 160             (address >= RAS_UMC_INJECT_ADDR_LIMIT)) {
 161                 dev_warn(adev->dev,
 162                          "RAS WARN: input address 0x%llx is invalid.\n",
 163                          address);
 164                 return -EINVAL;
 165         }
 166
 167         if (amdgpu_ras_check_bad_page(adev, address)) {
 168                 dev_warn(adev->dev,
 169                          "RAS WARN: 0x%llx has already been marked as bad page!\n",
 170                          address);
 171                 return 0;
 172         }
 173
 174         ret = amdgpu_ras_error_data_init(&err_data);
 175         if (ret)
 176                 return ret;
 177
 178         memset(&err_rec, 0x0, sizeof(struct eeprom_table_record));
 179         err_data.err_addr = &err_rec;
 180         amdgpu_umc_fill_error_record(&err_data, address, address, 0, 0);
 181
 182         if (amdgpu_bad_page_threshold != 0) {
 183                 amdgpu_ras_add_bad_pages(adev, err_data.err_addr,
 184                                          err_data.err_addr_cnt);
 185                 amdgpu_ras_save_bad_pages(adev, NULL);
 186         }
 187
 188         amdgpu_ras_error_data_fini(&err_data);
 189
 190         dev_warn(adev->dev, "WARNING: THIS IS ONLY FOR TEST PURPOSES AND WILL CORRUPT RAS EEPROM\n");
 191         dev_warn(adev->dev, "Clear EEPROM:\n");
 192         dev_warn(adev->dev, "    echo 1 > /sys/kernel/debug/dri/0/ras/ras_eeprom_reset\n");
 193
 194         return 0;
 195 }
 196
 197 static ssize_t amdgpu_ras_debugfs_read(struct file *f, char __user *buf,
 198                                         size_t size, loff_t *pos)
 199 {
 200         struct ras_manager *obj = (struct ras_manager *)file_inode(f)->i_private;
 201         struct ras_query_if info = {
 202                 .head = obj->head,
 203         };
 204         ssize_t s;
 205         char val[128];
 206
 207         if (amdgpu_ras_query_error_status(obj->adev, &info))
 208                 return -EINVAL;
 209
 210         /* Hardware counter will be reset automatically after the query on Vega20 and Arcturus */
 211         if (amdgpu_ip_version(obj->adev, MP0_HWIP, 0) != IP_VERSION(11, 0, 2) &&
 212             amdgpu_ip_version(obj->adev, MP0_HWIP, 0) != IP_VERSION(11, 0, 4)) {
 213                 if (amdgpu_ras_reset_error_status(obj->adev, info.head.block))
 214                         dev_warn(obj->adev->dev, "Failed to reset error counter and error status");
 215         }
 216
 217         s = snprintf(val, sizeof(val), "%s: %lu\n%s: %lu\n",
 218                         "ue", info.ue_count,
 219                         "ce", info.ce_count);
 220         if (*pos >= s)
 221                 return 0;
 222
 223         s -= *pos;
 224         s = min_t(u64, s, size);
 225
 226
 227         if (copy_to_user(buf, &val[*pos], s))
 228                 return -EINVAL;
 229
 230         *pos += s;
 231
 232         return s;
 233 }
 234
 235 static const struct file_operations amdgpu_ras_debugfs_ops = {
 236         .owner = THIS_MODULE,
 237         .read = amdgpu_ras_debugfs_read,
 238         .write = NULL,
 239         .llseek = default_llseek
 240 };
 241
 242 static int amdgpu_ras_find_block_id_by_name(const char *name, int *block_id)
 243 {
 244         int i;
 245
 246         for (i = 0; i < ARRAY_SIZE(ras_block_string); i++) {
 247                 *block_id = i;
 248                 if (strcmp(name, ras_block_string[i]) == 0)
 249                         return 0;
 250         }
 251         return -EINVAL;
 252 }
 253
 254 static int amdgpu_ras_debugfs_ctrl_parse_data(struct file *f,
 255                 const char __user *buf, size_t size,
 256                 loff_t *pos, struct ras_debug_if *data)
 257 {
 258         ssize_t s = min_t(u64, 64, size);
 259         char str[65];
 260         char block_name[33];
 261         char err[9] = "ue";
 262         int op = -1;
 263         int block_id;
 264         uint32_t sub_block;
 265         u64 address, value;
 266         /* default value is 0 if the mask is not set by user */
 267         u32 instance_mask = 0;
 268
 269         if (*pos)
 270                 return -EINVAL;
 271         *pos = size;
 272
 273         memset(str, 0, sizeof(str));
 274         memset(data, 0, sizeof(*data));
 275
 276         if (copy_from_user(str, buf, s))
 277                 return -EINVAL;
 278
 279         if (sscanf(str, "disable %32s", block_name) == 1)
 280                 op = 0;
 281         else if (sscanf(str, "enable %32s %8s", block_name, err) == 2)
 282                 op = 1;
 283         else if (sscanf(str, "inject %32s %8s", block_name, err) == 2)
 284                 op = 2;
 285         else if (strstr(str, "retire_page") != NULL)
 286                 op = 3;
 287         else if (str[0] && str[1] && str[2] && str[3])
 288                 /* ascii string, but commands are not matched. */
 289                 return -EINVAL;
 290
 291         if (op != -1) {
 292                 if (op == 3) {
 293                         if (sscanf(str, "%*s 0x%llx", &address) != 1 &&
 294                             sscanf(str, "%*s %llu", &address) != 1)
 295                                 return -EINVAL;
 296
 297                         data->op = op;
 298                         data->inject.address = address;
 299
 300                         return 0;
 301                 }
 302
 303                 if (amdgpu_ras_find_block_id_by_name(block_name, &block_id))
 304                         return -EINVAL;
 305
 306                 data->head.block = block_id;
 307                 /* only ue and ce errors are supported */
 308                 if (!memcmp("ue", err, 2))
 309                         data->head.type = AMDGPU_RAS_ERROR__MULTI_UNCORRECTABLE;
 310                 else if (!memcmp("ce", err, 2))
 311                         data->head.type = AMDGPU_RAS_ERROR__SINGLE_CORRECTABLE;
 312                 else
 313                         return -EINVAL;
 314
 315                 data->op = op;
 316
 317                 if (op == 2) {
 318                         if (sscanf(str, "%*s %*s %*s 0x%x 0x%llx 0x%llx 0x%x",
 319                                    &sub_block, &address, &value, &instance_mask) != 4 &&
 320                             sscanf(str, "%*s %*s %*s %u %llu %llu %u",
 321                                    &sub_block, &address, &value, &instance_mask) != 4 &&
 322                                 sscanf(str, "%*s %*s %*s 0x%x 0x%llx 0x%llx",
 323                                    &sub_block, &address, &value) != 3 &&
 324                             sscanf(str, "%*s %*s %*s %u %llu %llu",
 325                                    &sub_block, &address, &value) != 3)
 326                                 return -EINVAL;
 327                         data->head.sub_block_index = sub_block;
 328                         data->inject.address = address;
 329                         data->inject.value = value;
 330                         data->inject.instance_mask = instance_mask;
 331                 }
 332         } else {
 333                 if (size < sizeof(*data))
 334                         return -EINVAL;
 335
 336                 if (copy_from_user(data, buf, sizeof(*data)))
 337                         return -EINVAL;
 338         }
 339
 340         return 0;
 341 }
 342
 343 static void amdgpu_ras_instance_mask_check(struct amdgpu_device *adev,
 344                                 struct ras_debug_if *data)
 345 {
 346         int num_xcc = adev->gfx.xcc_mask ? NUM_XCC(adev->gfx.xcc_mask) : 1;
 347         uint32_t mask, inst_mask = data->inject.instance_mask;
 348
 349         /* no need to set instance mask if there is only one instance */
 350         if (num_xcc <= 1 && inst_mask) {
 351                 data->inject.instance_mask = 0;
 352                 dev_dbg(adev->dev,
 353                         "RAS inject mask(0x%x) isn't supported and force it to 0.\n",
 354                         inst_mask);
 355
 356                 return;
 357         }
 358
 359         switch (data->head.block) {
 360         case AMDGPU_RAS_BLOCK__GFX:
 361                 mask = GENMASK(num_xcc - 1, 0);
 362                 break;
 363         case AMDGPU_RAS_BLOCK__SDMA:
 364                 mask = GENMASK(adev->sdma.num_instances - 1, 0);
 365                 break;
 366         case AMDGPU_RAS_BLOCK__VCN:
 367         case AMDGPU_RAS_BLOCK__JPEG:
 368                 mask = GENMASK(adev->vcn.num_vcn_inst - 1, 0);
 369                 break;
 370         default:
 371                 mask = inst_mask;
 372                 break;
 373         }
 374
 375         /* remove invalid bits in instance mask */
 376         data->inject.instance_mask &= mask;
 377         if (inst_mask != data->inject.instance_mask)
 378                 dev_dbg(adev->dev,
 379                         "Adjust RAS inject mask 0x%x to 0x%x\n",
 380                         inst_mask, data->inject.instance_mask);
 381 }
 382
 383 /**
 384  * DOC: AMDGPU RAS debugfs control interface
 385  *
 386  * The control interface accepts struct ras_debug_if which has two members.
 387  *
 388  * First member: ras_debug_if::head or ras_debug_if::inject.
 389  *
 390  * head is used to indicate which IP block will be under control.
 391  *
 392  * head has four members, they are block, type, sub_block_index, name.
 393  * block: which IP will be under control.
 394  * type: what kind of error will be enabled/disabled/injected.
 395  * sub_block_index: some IPs have subcomponets. say, GFX, sDMA.
 396  * name: the name of IP.
 397  *
 398  * inject has three more members than head, they are address, value and mask.
 399  * As their names indicate, inject operation will write the
 400  * value to the address.
 401  *
 402  * The second member: struct ras_debug_if::op.
 403  * It has three kinds of operations.
 404  *
 405  * - 0: disable RAS on the block. Take ::head as its data.
 406  * - 1: enable RAS on the block. Take ::head as its data.
 407  * - 2: inject errors on the block. Take ::inject as its data.
 408  *
 409  * How to use the interface?
 410  *
 411  * In a program
 412  *
 413  * Copy the struct ras_debug_if in your code and initialize it.
 414  * Write the struct to the control interface.
 415  *
 416  * From shell
 417  *
 418  * .. code-block:: bash
 419  *
 420  *      echo "disable <block>" > /sys/kernel/debug/dri/<N>/ras/ras_ctrl
 421  *      echo "enable  <block> <error>" > /sys/kernel/debug/dri/<N>/ras/ras_ctrl
 422  *      echo "inject  <block> <error> <sub-block> <address> <value> <mask>" > /sys/kernel/debug/dri/<N>/ras/ras_ctrl
 423  *
 424  * Where N, is the card which you want to affect.
 425  *
 426  * "disable" requires only the block.
 427  * "enable" requires the block and error type.
 428  * "inject" requires the block, error type, address, and value.
 429  *
 430  * The block is one of: umc, sdma, gfx, etc.
 431  *      see ras_block_string[] for details
 432  *
 433  * The error type is one of: ue, ce, where,
 434  *      ue is multi-uncorrectable
 435  *      ce is single-correctable
 436  *
 437  * The sub-block is a the sub-block index, pass 0 if there is no sub-block.
 438  * The address and value are hexadecimal numbers, leading 0x is optional.
 439  * The mask means instance mask, is optional, default value is 0x1.
 440  *
 441  * For instance,
 442  *
 443  * .. code-block:: bash
 444  *
 445  *      echo inject umc ue 0x0 0x0 0x0 > /sys/kernel/debug/dri/0/ras/ras_ctrl
 446  *      echo inject umc ce 0 0 0 3 > /sys/kernel/debug/dri/0/ras/ras_ctrl
 447  *      echo disable umc > /sys/kernel/debug/dri/0/ras/ras_ctrl
 448  *
 449  * How to check the result of the operation?
 450  *
 451  * To check disable/enable, see "ras" features at,
 452  * /sys/class/drm/card[0/1/2...]/device/ras/features
 453  *
 454  * To check inject, see the corresponding error count at,
 455  * /sys/class/drm/card[0/1/2...]/device/ras/[gfx|sdma|umc|...]_err_count
 456  *
 457  * .. note::
 458  *      Operations are only allowed on blocks which are supported.
 459  *      Check the "ras" mask at /sys/module/amdgpu/parameters/ras_mask
 460  *      to see which blocks support RAS on a particular asic.
 461  *
 462  */
 463 static ssize_t amdgpu_ras_debugfs_ctrl_write(struct file *f,
 464                                              const char __user *buf,
 465                                              size_t size, loff_t *pos)
 466 {
 467         struct amdgpu_device *adev = (struct amdgpu_device *)file_inode(f)->i_private;
 468         struct ras_debug_if data;
 469         int ret = 0;
 470
 471         if (!amdgpu_ras_get_error_query_ready(adev)) {
 472                 dev_warn(adev->dev, "RAS WARN: error injection "
 473                                 "currently inaccessible\n");
 474                 return size;
 475         }
 476
 477         ret = amdgpu_ras_debugfs_ctrl_parse_data(f, buf, size, pos, &data);
 478         if (ret)
 479                 return ret;
 480
 481         if (data.op == 3) {
 482                 ret = amdgpu_reserve_page_direct(adev, data.inject.address);
 483                 if (!ret)
 484                         return size;
 485                 else
 486                         return ret;
 487         }
 488
 489         if (!amdgpu_ras_is_supported(adev, data.head.block))
 490                 return -EINVAL;
 491
 492         switch (data.op) {
 493         case 0:
 494                 ret = amdgpu_ras_feature_enable(adev, &data.head, 0);
 495                 break;
 496         case 1:
 497                 ret = amdgpu_ras_feature_enable(adev, &data.head, 1);
 498                 break;
 499         case 2:
 500                 if ((data.inject.address >= adev->gmc.mc_vram_size &&
 501                     adev->gmc.mc_vram_size) ||
 502                     (data.inject.address >= RAS_UMC_INJECT_ADDR_LIMIT)) {
 503                         dev_warn(adev->dev, "RAS WARN: input address "
 504                                         "0x%llx is invalid.",
 505                                         data.inject.address);
 506                         ret = -EINVAL;
 507                         break;
 508                 }
 509
 510                 /* umc ce/ue error injection for a bad page is not allowed */
 511                 if ((data.head.block == AMDGPU_RAS_BLOCK__UMC) &&
 512                     amdgpu_ras_check_bad_page(adev, data.inject.address)) {
 513                         dev_warn(adev->dev, "RAS WARN: inject: 0x%llx has "
 514                                  "already been marked as bad!\n",
 515                                  data.inject.address);
 516                         break;
 517                 }
 518
 519                 amdgpu_ras_instance_mask_check(adev, &data);
 520
 521                 /* data.inject.address is offset instead of absolute gpu address */
 522                 ret = amdgpu_ras_error_inject(adev, &data.inject);
 523                 break;
 524         default:
 525                 ret = -EINVAL;
 526                 break;
 527         }
 528
 529         if (ret)
 530                 return ret;
 531
 532         return size;
 533 }
 534
 535 /**
 536  * DOC: AMDGPU RAS debugfs EEPROM table reset interface
 537  *
 538  * Some boards contain an EEPROM which is used to persistently store a list of
 539  * bad pages which experiences ECC errors in vram.  This interface provides
 540  * a way to reset the EEPROM, e.g., after testing error injection.
 541  *
 542  * Usage:
 543  *
 544  * .. code-block:: bash
 545  *
 546  *      echo 1 > ../ras/ras_eeprom_reset
 547  *
 548  * will reset EEPROM table to 0 entries.
 549  *
 550  */
 551 static ssize_t amdgpu_ras_debugfs_eeprom_write(struct file *f,
 552                                                const char __user *buf,
 553                                                size_t size, loff_t *pos)
 554 {
 555         struct amdgpu_device *adev =
 556                 (struct amdgpu_device *)file_inode(f)->i_private;
 557         int ret;
 558
 559         ret = amdgpu_ras_eeprom_reset_table(
 560                 &(amdgpu_ras_get_context(adev)->eeprom_control));
 561
 562         if (!ret) {
 563                 /* Something was written to EEPROM.
 564                  */
 565                 amdgpu_ras_get_context(adev)->flags = RAS_DEFAULT_FLAGS;
 566                 return size;
 567         } else {
 568                 return ret;
 569         }
 570 }
 571
 572 static const struct file_operations amdgpu_ras_debugfs_ctrl_ops = {
 573         .owner = THIS_MODULE,
 574         .read = NULL,
 575         .write = amdgpu_ras_debugfs_ctrl_write,
 576         .llseek = default_llseek
 577 };
 578
 579 static const struct file_operations amdgpu_ras_debugfs_eeprom_ops = {
 580         .owner = THIS_MODULE,
 581         .read = NULL,
 582         .write = amdgpu_ras_debugfs_eeprom_write,
 583         .llseek = default_llseek
 584 };
 585
 586 /**
 587  * DOC: AMDGPU RAS sysfs Error Count Interface
 588  *
 589  * It allows the user to read the error count for each IP block on the gpu through
 590  * /sys/class/drm/card[0/1/2...]/device/ras/[gfx/sdma/...]_err_count
 591  *
 592  * It outputs the multiple lines which report the uncorrected (ue) and corrected
 593  * (ce) error counts.
 594  *
 595  * The format of one line is below,
 596  *
 597  * [ce|ue]: count
 598  *
 599  * Example:
 600  *
 601  * .. code-block:: bash
 602  *
 603  *      ue: 0
 604  *      ce: 1
 605  *
 606  */
 607 static ssize_t amdgpu_ras_sysfs_read(struct device *dev,
 608                 struct device_attribute *attr, char *buf)
 609 {
 610         struct ras_manager *obj = container_of(attr, struct ras_manager, sysfs_attr);
 611         struct ras_query_if info = {
 612                 .head = obj->head,
 613         };
 614
 615         if (!amdgpu_ras_get_error_query_ready(obj->adev))
 616                 return sysfs_emit(buf, "Query currently inaccessible\n");
 617
 618         if (amdgpu_ras_query_error_status(obj->adev, &info))
 619                 return -EINVAL;
 620
 621         if (amdgpu_ip_version(obj->adev, MP0_HWIP, 0) != IP_VERSION(11, 0, 2) &&
 622             amdgpu_ip_version(obj->adev, MP0_HWIP, 0) != IP_VERSION(11, 0, 4)) {
 623                 if (amdgpu_ras_reset_error_status(obj->adev, info.head.block))
 624                         dev_warn(obj->adev->dev, "Failed to reset error counter and error status");
 625         }
 626
 627         return sysfs_emit(buf, "%s: %lu\n%s: %lu\n", "ue", info.ue_count,
 628                           "ce", info.ce_count);
 629 }
 630
 631 /* obj begin */
 632
 633 #define get_obj(obj) do { (obj)->use++; } while (0)
 634 #define alive_obj(obj) ((obj)->use)
 635
 636 static inline void put_obj(struct ras_manager *obj)
 637 {
 638         if (obj && (--obj->use == 0))
 639                 list_del(&obj->node);
 640         if (obj && (obj->use < 0))
 641                 DRM_ERROR("RAS ERROR: Unbalance obj(%s) use\n", get_ras_block_str(&obj->head));
 642 }
 643
 644 /* make one obj and return it. */
 645 static struct ras_manager *amdgpu_ras_create_obj(struct amdgpu_device *adev,
 646                 struct ras_common_if *head)
 647 {
 648         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
 649         struct ras_manager *obj;
 650
 651         if (!adev->ras_enabled || !con)
 652                 return NULL;
 653
 654         if (head->block >= AMDGPU_RAS_BLOCK_COUNT)
 655                 return NULL;
 656
 657         if (head->block == AMDGPU_RAS_BLOCK__MCA) {
 658                 if (head->sub_block_index >= AMDGPU_RAS_MCA_BLOCK__LAST)
 659                         return NULL;
 660
 661                 obj = &con->objs[AMDGPU_RAS_BLOCK__LAST + head->sub_block_index];
 662         } else
 663                 obj = &con->objs[head->block];
 664
 665         /* already exist. return obj? */
 666         if (alive_obj(obj))
 667                 return NULL;
 668
 669         obj->head = *head;
 670         obj->adev = adev;
 671         list_add(&obj->node, &con->head);
 672         get_obj(obj);
 673
 674         return obj;
 675 }
 676
 677 /* return an obj equal to head, or the first when head is NULL */
 678 struct ras_manager *amdgpu_ras_find_obj(struct amdgpu_device *adev,
 679                 struct ras_common_if *head)
 680 {
 681         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
 682         struct ras_manager *obj;
 683         int i;
 684
 685         if (!adev->ras_enabled || !con)
 686                 return NULL;
 687
 688         if (head) {
 689                 if (head->block >= AMDGPU_RAS_BLOCK_COUNT)
 690                         return NULL;
 691
 692                 if (head->block == AMDGPU_RAS_BLOCK__MCA) {
 693                         if (head->sub_block_index >= AMDGPU_RAS_MCA_BLOCK__LAST)
 694                                 return NULL;
 695
 696                         obj = &con->objs[AMDGPU_RAS_BLOCK__LAST + head->sub_block_index];
 697                 } else
 698                         obj = &con->objs[head->block];
 699
 700                 if (alive_obj(obj))
 701                         return obj;
 702         } else {
 703                 for (i = 0; i < AMDGPU_RAS_BLOCK_COUNT + AMDGPU_RAS_MCA_BLOCK_COUNT; i++) {
 704                         obj = &con->objs[i];
 705                         if (alive_obj(obj))
 706                                 return obj;
 707                 }
 708         }
 709
 710         return NULL;
 711 }
 712 /* obj end */
 713
 714 /* feature ctl begin */
 715 static int amdgpu_ras_is_feature_allowed(struct amdgpu_device *adev,
 716                                          struct ras_common_if *head)
 717 {
 718         return adev->ras_hw_enabled & BIT(head->block);
 719 }
 720
 721 static int amdgpu_ras_is_feature_enabled(struct amdgpu_device *adev,
 722                 struct ras_common_if *head)
 723 {
 724         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
 725
 726         return con->features & BIT(head->block);
 727 }
 728
 729 /*
 730  * if obj is not created, then create one.
 731  * set feature enable flag.
 732  */
 733 static int __amdgpu_ras_feature_enable(struct amdgpu_device *adev,
 734                 struct ras_common_if *head, int enable)
 735 {
 736         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
 737         struct ras_manager *obj = amdgpu_ras_find_obj(adev, head);
 738
 739         /* If hardware does not support ras, then do not create obj.
 740          * But if hardware support ras, we can create the obj.
 741          * Ras framework checks con->hw_supported to see if it need do
 742          * corresponding initialization.
 743          * IP checks con->support to see if it need disable ras.
 744          */
 745         if (!amdgpu_ras_is_feature_allowed(adev, head))
 746                 return 0;
 747
 748         if (enable) {
 749                 if (!obj) {
 750                         obj = amdgpu_ras_create_obj(adev, head);
 751                         if (!obj)
 752                                 return -EINVAL;
 753                 } else {
 754                         /* In case we create obj somewhere else */
 755                         get_obj(obj);
 756                 }
 757                 con->features |= BIT(head->block);
 758         } else {
 759                 if (obj && amdgpu_ras_is_feature_enabled(adev, head)) {
 760                         con->features &= ~BIT(head->block);
 761                         put_obj(obj);
 762                 }
 763         }
 764
 765         return 0;
 766 }
 767
 768 /* wrapper of psp_ras_enable_features */
 769 int amdgpu_ras_feature_enable(struct amdgpu_device *adev,
 770                 struct ras_common_if *head, bool enable)
 771 {
 772         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
 773         union ta_ras_cmd_input *info;
 774         int ret;
 775
 776         if (!con)
 777                 return -EINVAL;
 778
 779         /* For non-gfx ip, do not enable ras feature if it is not allowed */
 780         /* For gfx ip, regardless of feature support status, */
 781         /* Force issue enable or disable ras feature commands */
 782         if (head->block != AMDGPU_RAS_BLOCK__GFX &&
 783             !amdgpu_ras_is_feature_allowed(adev, head))
 784                 return 0;
 785
 786         /* Only enable gfx ras feature from host side */
 787         if (head->block == AMDGPU_RAS_BLOCK__GFX &&
 788             !amdgpu_sriov_vf(adev) &&
 789             !amdgpu_ras_intr_triggered()) {
 790                 info = kzalloc(sizeof(union ta_ras_cmd_input), GFP_KERNEL);
 791                 if (!info)
 792                         return -ENOMEM;
 793
 794                 if (!enable) {
 795                         info->disable_features = (struct ta_ras_disable_features_input) {
 796                                 .block_id =  amdgpu_ras_block_to_ta(head->block),
 797                                 .error_type = amdgpu_ras_error_to_ta(head->type),
 798                         };
 799                 } else {
 800                         info->enable_features = (struct ta_ras_enable_features_input) {
 801                                 .block_id =  amdgpu_ras_block_to_ta(head->block),
 802                                 .error_type = amdgpu_ras_error_to_ta(head->type),
 803                         };
 804                 }
 805
 806                 ret = psp_ras_enable_features(&adev->psp, info, enable);
 807                 if (ret) {
 808                         dev_err(adev->dev, "ras %s %s failed poison:%d ret:%d\n",
 809                                 enable ? "enable":"disable",
 810                                 get_ras_block_str(head),
 811                                 amdgpu_ras_is_poison_mode_supported(adev), ret);
 812                         kfree(info);
 813                         return ret;
 814                 }
 815
 816                 kfree(info);
 817         }
 818
 819         /* setup the obj */
 820         __amdgpu_ras_feature_enable(adev, head, enable);
 821
 822         return 0;
 823 }
 824
 825 /* Only used in device probe stage and called only once. */
 826 int amdgpu_ras_feature_enable_on_boot(struct amdgpu_device *adev,
 827                 struct ras_common_if *head, bool enable)
 828 {
 829         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
 830         int ret;
 831
 832         if (!con)
 833                 return -EINVAL;
 834
 835         if (con->flags & AMDGPU_RAS_FLAG_INIT_BY_VBIOS) {
 836                 if (enable) {
 837                         /* There is no harm to issue a ras TA cmd regardless of
 838                          * the currecnt ras state.
 839                          * If current state == target state, it will do nothing
 840                          * But sometimes it requests driver to reset and repost
 841                          * with error code -EAGAIN.
 842                          */
 843                         ret = amdgpu_ras_feature_enable(adev, head, 1);
 844                         /* With old ras TA, we might fail to enable ras.
 845                          * Log it and just setup the object.
 846                          * TODO need remove this WA in the future.
 847                          */
 848                         if (ret == -EINVAL) {
 849                                 ret = __amdgpu_ras_feature_enable(adev, head, 1);
 850                                 if (!ret)
 851                                         dev_info(adev->dev,
 852                                                 "RAS INFO: %s setup object\n",
 853                                                 get_ras_block_str(head));
 854                         }
 855                 } else {
 856                         /* setup the object then issue a ras TA disable cmd.*/
 857                         ret = __amdgpu_ras_feature_enable(adev, head, 1);
 858                         if (ret)
 859                                 return ret;
 860
 861                         /* gfx block ras dsiable cmd must send to ras-ta */
 862                         if (head->block == AMDGPU_RAS_BLOCK__GFX)
 863                                 con->features |= BIT(head->block);
 864
 865                         ret = amdgpu_ras_feature_enable(adev, head, 0);
 866
 867                         /* clean gfx block ras features flag */
 868                         if (adev->ras_enabled && head->block == AMDGPU_RAS_BLOCK__GFX)
 869                                 con->features &= ~BIT(head->block);
 870                 }
 871         } else
 872                 ret = amdgpu_ras_feature_enable(adev, head, enable);
 873
 874         return ret;
 875 }
 876
 877 static int amdgpu_ras_disable_all_features(struct amdgpu_device *adev,
 878                 bool bypass)
 879 {
 880         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
 881         struct ras_manager *obj, *tmp;
 882
 883         list_for_each_entry_safe(obj, tmp, &con->head, node) {
 884                 /* bypass psp.
 885                  * aka just release the obj and corresponding flags
 886                  */
 887                 if (bypass) {
 888                         if (__amdgpu_ras_feature_enable(adev, &obj->head, 0))
 889                                 break;
 890                 } else {
 891                         if (amdgpu_ras_feature_enable(adev, &obj->head, 0))
 892                                 break;
 893                 }
 894         }
 895
 896         return con->features;
 897 }
 898
 899 static int amdgpu_ras_enable_all_features(struct amdgpu_device *adev,
 900                 bool bypass)
 901 {
 902         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
 903         int i;
 904         const enum amdgpu_ras_error_type default_ras_type = AMDGPU_RAS_ERROR__NONE;
 905
 906         for (i = 0; i < AMDGPU_RAS_BLOCK_COUNT; i++) {
 907                 struct ras_common_if head = {
 908                         .block = i,
 909                         .type = default_ras_type,
 910                         .sub_block_index = 0,
 911                 };
 912
 913                 if (i == AMDGPU_RAS_BLOCK__MCA)
 914                         continue;
 915
 916                 if (bypass) {
 917                         /*
 918                          * bypass psp. vbios enable ras for us.
 919                          * so just create the obj
 920                          */
 921                         if (__amdgpu_ras_feature_enable(adev, &head, 1))
 922                                 break;
 923                 } else {
 924                         if (amdgpu_ras_feature_enable(adev, &head, 1))
 925                                 break;
 926                 }
 927         }
 928
 929         for (i = 0; i < AMDGPU_RAS_MCA_BLOCK_COUNT; i++) {
 930                 struct ras_common_if head = {
 931                         .block = AMDGPU_RAS_BLOCK__MCA,
 932                         .type = default_ras_type,
 933                         .sub_block_index = i,
 934                 };
 935
 936                 if (bypass) {
 937                         /*
 938                          * bypass psp. vbios enable ras for us.
 939                          * so just create the obj
 940                          */
 941                         if (__amdgpu_ras_feature_enable(adev, &head, 1))
 942                                 break;
 943                 } else {
 944                         if (amdgpu_ras_feature_enable(adev, &head, 1))
 945                                 break;
 946                 }
 947         }
 948
 949         return con->features;
 950 }
 951 /* feature ctl end */
 952
 953 static int amdgpu_ras_block_match_default(struct amdgpu_ras_block_object *block_obj,
 954                 enum amdgpu_ras_block block)
 955 {
 956         if (!block_obj)
 957                 return -EINVAL;
 958
 959         if (block_obj->ras_comm.block == block)
 960                 return 0;
 961
 962         return -EINVAL;
 963 }
 964
 965 static struct amdgpu_ras_block_object *amdgpu_ras_get_ras_block(struct amdgpu_device *adev,
 966                                         enum amdgpu_ras_block block, uint32_t sub_block_index)
 967 {
 968         struct amdgpu_ras_block_list *node, *tmp;
 969         struct amdgpu_ras_block_object *obj;
 970
 971         if (block >= AMDGPU_RAS_BLOCK__LAST)
 972                 return NULL;
 973
 974         list_for_each_entry_safe(node, tmp, &adev->ras_list, node) {
 975                 if (!node->ras_obj) {
 976                         dev_warn(adev->dev, "Warning: abnormal ras list node.\n");
 977                         continue;
 978                 }
 979
 980                 obj = node->ras_obj;
 981                 if (obj->ras_block_match) {
 982                         if (obj->ras_block_match(obj, block, sub_block_index) == 0)
 983                                 return obj;
 984                 } else {
 985                         if (amdgpu_ras_block_match_default(obj, block) == 0)
 986                                 return obj;
 987                 }
 988         }
 989
 990         return NULL;
 991 }
 992
 993 static void amdgpu_ras_get_ecc_info(struct amdgpu_device *adev, struct ras_err_data *err_data)
 994 {
 995         struct amdgpu_ras *ras = amdgpu_ras_get_context(adev);
 996         int ret = 0;
 997
 998         /*
 999          * choosing right query method according to
1000          * whether smu support query error information
1001          */
1002         ret = amdgpu_dpm_get_ecc_info(adev, (void *)&(ras->umc_ecc));
1003         if (ret == -EOPNOTSUPP) {
1004                 if (adev->umc.ras && adev->umc.ras->ras_block.hw_ops &&
1005                         adev->umc.ras->ras_block.hw_ops->query_ras_error_count)
1006                         adev->umc.ras->ras_block.hw_ops->query_ras_error_count(adev, err_data);
1007
1008                 /* umc query_ras_error_address is also responsible for clearing
1009                  * error status
1010                  */
1011                 if (adev->umc.ras && adev->umc.ras->ras_block.hw_ops &&
1012                     adev->umc.ras->ras_block.hw_ops->query_ras_error_address)
1013                         adev->umc.ras->ras_block.hw_ops->query_ras_error_address(adev, err_data);
1014         } else if (!ret) {
1015                 if (adev->umc.ras &&
1016                         adev->umc.ras->ecc_info_query_ras_error_count)
1017                         adev->umc.ras->ecc_info_query_ras_error_count(adev, err_data);
1018
1019                 if (adev->umc.ras &&
1020                         adev->umc.ras->ecc_info_query_ras_error_address)
1021                         adev->umc.ras->ecc_info_query_ras_error_address(adev, err_data);
1022         }
1023 }
1024
1025 static void amdgpu_ras_error_print_error_data(struct amdgpu_device *adev,
1026                                               struct ras_query_if *query_if,
1027                                               struct ras_err_data *err_data,
1028                                               bool is_ue)
1029 {
1030         struct ras_manager *ras_mgr = amdgpu_ras_find_obj(adev, &query_if->head);
1031         const char *blk_name = get_ras_block_str(&query_if->head);
1032         struct amdgpu_smuio_mcm_config_info *mcm_info;
1033         struct ras_err_node *err_node;
1034         struct ras_err_info *err_info;
1035
1036         if (is_ue)
1037                 dev_info(adev->dev, "%ld uncorrectable hardware errors detected in %s block\n",
1038                          ras_mgr->err_data.ue_count, blk_name);
1039         else
1040                 dev_info(adev->dev, "%ld correctable hardware errors detected in %s block\n",
1041                          ras_mgr->err_data.ue_count, blk_name);
1042
1043         for_each_ras_error(err_node, err_data) {
1044                 err_info = &err_node->err_info;
1045                 mcm_info = &err_info->mcm_info;
1046                 if (is_ue && err_info->ue_count) {
1047                         dev_info(adev->dev, "socket: %d, die: %d "
1048                                  "%lld uncorrectable hardware errors detected in %s block\n",
1049                                  mcm_info->socket_id,
1050                                  mcm_info->die_id,
1051                                  err_info->ue_count,
1052                                  blk_name);
1053                 } else if (!is_ue && err_info->ce_count) {
1054                         dev_info(adev->dev, "socket: %d, die: %d "
1055                                  "%lld correctable hardware errors detected in %s block\n",
1056                                  mcm_info->socket_id,
1057                                  mcm_info->die_id,
1058                                  err_info->ue_count,
1059                                  blk_name);
1060                 }
1061         }
1062 }
1063
1064 static void amdgpu_ras_error_generate_report(struct amdgpu_device *adev,
1065                                              struct ras_query_if *query_if,
1066                                              struct ras_err_data *err_data)
1067 {
1068         struct ras_manager *ras_mgr = amdgpu_ras_find_obj(adev, &query_if->head);
1069         const char *blk_name = get_ras_block_str(&query_if->head);
1070
1071         if (err_data->ce_count) {
1072                 if (!list_empty(&err_data->err_node_list)) {
1073                         amdgpu_ras_error_print_error_data(adev, query_if,
1074                                                           err_data, false);
1075                 } else if (!adev->aid_mask &&
1076                            adev->smuio.funcs &&
1077                            adev->smuio.funcs->get_socket_id &&
1078                            adev->smuio.funcs->get_die_id) {
1079                         dev_info(adev->dev, "socket: %d, die: %d "
1080                                  "%ld correctable hardware errors "
1081                                  "detected in %s block, no user "
1082                                  "action is needed.\n",
1083                                  adev->smuio.funcs->get_socket_id(adev),
1084                                  adev->smuio.funcs->get_die_id(adev),
1085                                  ras_mgr->err_data.ce_count,
1086                                  blk_name);
1087                 } else {
1088                         dev_info(adev->dev, "%ld correctable hardware errors "
1089                                  "detected in %s block, no user "
1090                                  "action is needed.\n",
1091                                  ras_mgr->err_data.ce_count,
1092                                  blk_name);
1093                 }
1094         }
1095
1096         if (err_data->ue_count) {
1097                 if (!list_empty(&err_data->err_node_list)) {
1098                         amdgpu_ras_error_print_error_data(adev, query_if,
1099                                                           err_data, true);
1100                 } else if (!adev->aid_mask &&
1101                            adev->smuio.funcs &&
1102                            adev->smuio.funcs->get_socket_id &&
1103                            adev->smuio.funcs->get_die_id) {
1104                         dev_info(adev->dev, "socket: %d, die: %d "
1105                                  "%ld uncorrectable hardware errors "
1106                                  "detected in %s block\n",
1107                                  adev->smuio.funcs->get_socket_id(adev),
1108                                  adev->smuio.funcs->get_die_id(adev),
1109                                  ras_mgr->err_data.ue_count,
1110                                  blk_name);
1111                 } else {
1112                         dev_info(adev->dev, "%ld uncorrectable hardware errors "
1113                                  "detected in %s block\n",
1114                                  ras_mgr->err_data.ue_count,
1115                                  blk_name);
1116                 }
1117         }
1118
1119 }
1120
1121 /* query/inject/cure begin */
1122 int amdgpu_ras_query_error_status(struct amdgpu_device *adev,
1123                                   struct ras_query_if *info)
1124 {
1125         struct amdgpu_ras_block_object *block_obj = NULL;
1126         struct ras_manager *obj = amdgpu_ras_find_obj(adev, &info->head);
1127         struct ras_err_data err_data;
1128         int ret;
1129
1130         if (!obj)
1131                 return -EINVAL;
1132
1133         ret = amdgpu_ras_error_data_init(&err_data);
1134         if (ret)
1135                 return ret;
1136
1137         if (info->head.block == AMDGPU_RAS_BLOCK__UMC) {
1138                 amdgpu_ras_get_ecc_info(adev, &err_data);
1139         } else {
1140                 block_obj = amdgpu_ras_get_ras_block(adev, info->head.block, 0);
1141                 if (!block_obj || !block_obj->hw_ops)   {
1142                         dev_dbg_once(adev->dev, "%s doesn't config RAS function\n",
1143                                      get_ras_block_str(&info->head));
1144                         ret = -EINVAL;
1145                         goto out_fini_err_data;
1146                 }
1147
1148                 if (block_obj->hw_ops->query_ras_error_count)
1149                         block_obj->hw_ops->query_ras_error_count(adev, &err_data);
1150
1151                 if ((info->head.block == AMDGPU_RAS_BLOCK__SDMA) ||
1152                     (info->head.block == AMDGPU_RAS_BLOCK__GFX) ||
1153                     (info->head.block == AMDGPU_RAS_BLOCK__MMHUB)) {
1154                                 if (block_obj->hw_ops->query_ras_error_status)
1155                                         block_obj->hw_ops->query_ras_error_status(adev);
1156                         }
1157         }
1158
1159         obj->err_data.ue_count += err_data.ue_count;
1160         obj->err_data.ce_count += err_data.ce_count;
1161
1162         info->ue_count = obj->err_data.ue_count;
1163         info->ce_count = obj->err_data.ce_count;
1164
1165         amdgpu_ras_error_generate_report(adev, info, &err_data);
1166
1167 out_fini_err_data:
1168         amdgpu_ras_error_data_fini(&err_data);
1169
1170         return ret;
1171 }
1172
1173 int amdgpu_ras_reset_error_status(struct amdgpu_device *adev,
1174                 enum amdgpu_ras_block block)
1175 {
1176         struct amdgpu_ras_block_object *block_obj = amdgpu_ras_get_ras_block(adev, block, 0);
1177
1178         if (!block_obj || !block_obj->hw_ops) {
1179                 dev_dbg_once(adev->dev, "%s doesn't config RAS function\n",
1180                              ras_block_str(block));
1181                 return 0;
1182         }
1183
1184         if (!amdgpu_ras_is_supported(adev, block))
1185                 return 0;
1186
1187         if (block_obj->hw_ops->reset_ras_error_count)
1188                 block_obj->hw_ops->reset_ras_error_count(adev);
1189
1190         if ((block == AMDGPU_RAS_BLOCK__GFX) ||
1191             (block == AMDGPU_RAS_BLOCK__MMHUB)) {
1192                 if (block_obj->hw_ops->reset_ras_error_status)
1193                         block_obj->hw_ops->reset_ras_error_status(adev);
1194         }
1195
1196         return 0;
1197 }
1198
1199 /* wrapper of psp_ras_trigger_error */
1200 int amdgpu_ras_error_inject(struct amdgpu_device *adev,
1201                 struct ras_inject_if *info)
1202 {
1203         struct ras_manager *obj = amdgpu_ras_find_obj(adev, &info->head);
1204         struct ta_ras_trigger_error_input block_info = {
1205                 .block_id =  amdgpu_ras_block_to_ta(info->head.block),
1206                 .inject_error_type = amdgpu_ras_error_to_ta(info->head.type),
1207                 .sub_block_index = info->head.sub_block_index,
1208                 .address = info->address,
1209                 .value = info->value,
1210         };
1211         int ret = -EINVAL;
1212         struct amdgpu_ras_block_object *block_obj = amdgpu_ras_get_ras_block(adev,
1213                                                         info->head.block,
1214                                                         info->head.sub_block_index);
1215
1216         /* inject on guest isn't allowed, return success directly */
1217         if (amdgpu_sriov_vf(adev))
1218                 return 0;
1219
1220         if (!obj)
1221                 return -EINVAL;
1222
1223         if (!block_obj || !block_obj->hw_ops)   {
1224                 dev_dbg_once(adev->dev, "%s doesn't config RAS function\n",
1225                              get_ras_block_str(&info->head));
1226                 return -EINVAL;
1227         }
1228
1229         /* Calculate XGMI relative offset */
1230         if (adev->gmc.xgmi.num_physical_nodes > 1 &&
1231             info->head.block != AMDGPU_RAS_BLOCK__GFX) {
1232                 block_info.address =
1233                         amdgpu_xgmi_get_relative_phy_addr(adev,
1234                                                           block_info.address);
1235         }
1236
1237         if (block_obj->hw_ops->ras_error_inject) {
1238                 if (info->head.block == AMDGPU_RAS_BLOCK__GFX)
1239                         ret = block_obj->hw_ops->ras_error_inject(adev, info, info->instance_mask);
1240                 else /* Special ras_error_inject is defined (e.g: xgmi) */
1241                         ret = block_obj->hw_ops->ras_error_inject(adev, &block_info,
1242                                                 info->instance_mask);
1243         } else {
1244                 /* default path */
1245                 ret = psp_ras_trigger_error(&adev->psp, &block_info, info->instance_mask);
1246         }
1247
1248         if (ret)
1249                 dev_err(adev->dev, "ras inject %s failed %d\n",
1250                         get_ras_block_str(&info->head), ret);
1251
1252         return ret;
1253 }
1254
1255 /**
1256  * amdgpu_ras_query_error_count_helper -- Get error counter for specific IP
1257  * @adev: pointer to AMD GPU device
1258  * @ce_count: pointer to an integer to be set to the count of correctible errors.
1259  * @ue_count: pointer to an integer to be set to the count of uncorrectible errors.
1260  * @query_info: pointer to ras_query_if
1261  *
1262  * Return 0 for query success or do nothing, otherwise return an error
1263  * on failures
1264  */
1265 static int amdgpu_ras_query_error_count_helper(struct amdgpu_device *adev,
1266                                                unsigned long *ce_count,
1267                                                unsigned long *ue_count,
1268                                                struct ras_query_if *query_info)
1269 {
1270         int ret;
1271
1272         if (!query_info)
1273                 /* do nothing if query_info is not specified */
1274                 return 0;
1275
1276         ret = amdgpu_ras_query_error_status(adev, query_info);
1277         if (ret)
1278                 return ret;
1279
1280         *ce_count += query_info->ce_count;
1281         *ue_count += query_info->ue_count;
1282
1283         /* some hardware/IP supports read to clear
1284          * no need to explictly reset the err status after the query call */
1285         if (amdgpu_ip_version(adev, MP0_HWIP, 0) != IP_VERSION(11, 0, 2) &&
1286             amdgpu_ip_version(adev, MP0_HWIP, 0) != IP_VERSION(11, 0, 4)) {
1287                 if (amdgpu_ras_reset_error_status(adev, query_info->head.block))
1288                         dev_warn(adev->dev,
1289                                  "Failed to reset error counter and error status\n");
1290         }
1291
1292         return 0;
1293 }
1294
1295 /**
1296  * amdgpu_ras_query_error_count -- Get error counts of all IPs or specific IP
1297  * @adev: pointer to AMD GPU device
1298  * @ce_count: pointer to an integer to be set to the count of correctible errors.
1299  * @ue_count: pointer to an integer to be set to the count of uncorrectible
1300  * errors.
1301  * @query_info: pointer to ras_query_if if the query request is only for
1302  * specific ip block; if info is NULL, then the qurey request is for
1303  * all the ip blocks that support query ras error counters/status
1304  *
1305  * If set, @ce_count or @ue_count, count and return the corresponding
1306  * error counts in those integer pointers. Return 0 if the device
1307  * supports RAS. Return -EOPNOTSUPP if the device doesn't support RAS.
1308  */
1309 int amdgpu_ras_query_error_count(struct amdgpu_device *adev,
1310                                  unsigned long *ce_count,
1311                                  unsigned long *ue_count,
1312                                  struct ras_query_if *query_info)
1313 {
1314         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
1315         struct ras_manager *obj;
1316         unsigned long ce, ue;
1317         int ret;
1318
1319         if (!adev->ras_enabled || !con)
1320                 return -EOPNOTSUPP;
1321
1322         /* Don't count since no reporting.
1323          */
1324         if (!ce_count && !ue_count)
1325                 return 0;
1326
1327         ce = 0;
1328         ue = 0;
1329         if (!query_info) {
1330                 /* query all the ip blocks that support ras query interface */
1331                 list_for_each_entry(obj, &con->head, node) {
1332                         struct ras_query_if info = {
1333                                 .head = obj->head,
1334                         };
1335
1336                         ret = amdgpu_ras_query_error_count_helper(adev, &ce, &ue, &info);
1337                 }
1338         } else {
1339                 /* query specific ip block */
1340                 ret = amdgpu_ras_query_error_count_helper(adev, &ce, &ue, query_info);
1341         }
1342
1343         if (ret)
1344                 return ret;
1345
1346         if (ce_count)
1347                 *ce_count = ce;
1348
1349         if (ue_count)
1350                 *ue_count = ue;
1351
1352         return 0;
1353 }
1354 /* query/inject/cure end */
1355
1356
1357 /* sysfs begin */
1358
1359 static int amdgpu_ras_badpages_read(struct amdgpu_device *adev,
1360                 struct ras_badpage **bps, unsigned int *count);
1361
1362 static char *amdgpu_ras_badpage_flags_str(unsigned int flags)
1363 {
1364         switch (flags) {
1365         case AMDGPU_RAS_RETIRE_PAGE_RESERVED:
1366                 return "R";
1367         case AMDGPU_RAS_RETIRE_PAGE_PENDING:
1368                 return "P";
1369         case AMDGPU_RAS_RETIRE_PAGE_FAULT:
1370         default:
1371                 return "F";
1372         }
1373 }
1374
1375 /**
1376  * DOC: AMDGPU RAS sysfs gpu_vram_bad_pages Interface
1377  *
1378  * It allows user to read the bad pages of vram on the gpu through
1379  * /sys/class/drm/card[0/1/2...]/device/ras/gpu_vram_bad_pages
1380  *
1381  * It outputs multiple lines, and each line stands for one gpu page.
1382  *
1383  * The format of one line is below,
1384  * gpu pfn : gpu page size : flags
1385  *
1386  * gpu pfn and gpu page size are printed in hex format.
1387  * flags can be one of below character,
1388  *
1389  * R: reserved, this gpu page is reserved and not able to use.
1390  *
1391  * P: pending for reserve, this gpu page is marked as bad, will be reserved
1392  * in next window of page_reserve.
1393  *
1394  * F: unable to reserve. this gpu page can't be reserved due to some reasons.
1395  *
1396  * Examples:
1397  *
1398  * .. code-block:: bash
1399  *
1400  *      0x00000001 : 0x00001000 : R
1401  *      0x00000002 : 0x00001000 : P
1402  *
1403  */
1404
1405 static ssize_t amdgpu_ras_sysfs_badpages_read(struct file *f,
1406                 struct kobject *kobj, struct bin_attribute *attr,
1407                 char *buf, loff_t ppos, size_t count)
1408 {
1409         struct amdgpu_ras *con =
1410                 container_of(attr, struct amdgpu_ras, badpages_attr);
1411         struct amdgpu_device *adev = con->adev;
1412         const unsigned int element_size =
1413                 sizeof("0xabcdabcd : 0x12345678 : R\n") - 1;
1414         unsigned int start = div64_ul(ppos + element_size - 1, element_size);
1415         unsigned int end = div64_ul(ppos + count - 1, element_size);
1416         ssize_t s = 0;
1417         struct ras_badpage *bps = NULL;
1418         unsigned int bps_count = 0;
1419
1420         memset(buf, 0, count);
1421
1422         if (amdgpu_ras_badpages_read(adev, &bps, &bps_count))
1423                 return 0;
1424
1425         for (; start < end && start < bps_count; start++)
1426                 s += scnprintf(&buf[s], element_size + 1,
1427                                 "0x%08x : 0x%08x : %1s\n",
1428                                 bps[start].bp,
1429                                 bps[start].size,
1430                                 amdgpu_ras_badpage_flags_str(bps[start].flags));
1431
1432         kfree(bps);
1433
1434         return s;
1435 }
1436
1437 static ssize_t amdgpu_ras_sysfs_features_read(struct device *dev,
1438                 struct device_attribute *attr, char *buf)
1439 {
1440         struct amdgpu_ras *con =
1441                 container_of(attr, struct amdgpu_ras, features_attr);
1442
1443         return sysfs_emit(buf, "feature mask: 0x%x\n", con->features);
1444 }
1445
1446 static ssize_t amdgpu_ras_sysfs_version_show(struct device *dev,
1447                 struct device_attribute *attr, char *buf)
1448 {
1449         struct amdgpu_ras *con =
1450                 container_of(attr, struct amdgpu_ras, version_attr);
1451         return sysfs_emit(buf, "table version: 0x%x\n", con->eeprom_control.tbl_hdr.version);
1452 }
1453
1454 static ssize_t amdgpu_ras_sysfs_schema_show(struct device *dev,
1455                 struct device_attribute *attr, char *buf)
1456 {
1457         struct amdgpu_ras *con =
1458                 container_of(attr, struct amdgpu_ras, schema_attr);
1459         return sysfs_emit(buf, "schema: 0x%x\n", con->schema);
1460 }
1461
1462 static void amdgpu_ras_sysfs_remove_bad_page_node(struct amdgpu_device *adev)
1463 {
1464         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
1465
1466         sysfs_remove_file_from_group(&adev->dev->kobj,
1467                                 &con->badpages_attr.attr,
1468                                 RAS_FS_NAME);
1469 }
1470
1471 static int amdgpu_ras_sysfs_remove_dev_attr_node(struct amdgpu_device *adev)
1472 {
1473         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
1474         struct attribute *attrs[] = {
1475                 &con->features_attr.attr,
1476                 &con->version_attr.attr,
1477                 &con->schema_attr.attr,
1478                 NULL
1479         };
1480         struct attribute_group group = {
1481                 .name = RAS_FS_NAME,
1482                 .attrs = attrs,
1483         };
1484
1485         sysfs_remove_group(&adev->dev->kobj, &group);
1486
1487         return 0;
1488 }
1489
1490 int amdgpu_ras_sysfs_create(struct amdgpu_device *adev,
1491                 struct ras_common_if *head)
1492 {
1493         struct ras_manager *obj = amdgpu_ras_find_obj(adev, head);
1494
1495         if (!obj || obj->attr_inuse)
1496                 return -EINVAL;
1497
1498         get_obj(obj);
1499
1500         snprintf(obj->fs_data.sysfs_name, sizeof(obj->fs_data.sysfs_name),
1501                 "%s_err_count", head->name);
1502
1503         obj->sysfs_attr = (struct device_attribute){
1504                 .attr = {
1505                         .name = obj->fs_data.sysfs_name,
1506                         .mode = S_IRUGO,
1507                 },
1508                         .show = amdgpu_ras_sysfs_read,
1509         };
1510         sysfs_attr_init(&obj->sysfs_attr.attr);
1511
1512         if (sysfs_add_file_to_group(&adev->dev->kobj,
1513                                 &obj->sysfs_attr.attr,
1514                                 RAS_FS_NAME)) {
1515                 put_obj(obj);
1516                 return -EINVAL;
1517         }
1518
1519         obj->attr_inuse = 1;
1520
1521         return 0;
1522 }
1523
1524 int amdgpu_ras_sysfs_remove(struct amdgpu_device *adev,
1525                 struct ras_common_if *head)
1526 {
1527         struct ras_manager *obj = amdgpu_ras_find_obj(adev, head);
1528
1529         if (!obj || !obj->attr_inuse)
1530                 return -EINVAL;
1531
1532         sysfs_remove_file_from_group(&adev->dev->kobj,
1533                                 &obj->sysfs_attr.attr,
1534                                 RAS_FS_NAME);
1535         obj->attr_inuse = 0;
1536         put_obj(obj);
1537
1538         return 0;
1539 }
1540
1541 static int amdgpu_ras_sysfs_remove_all(struct amdgpu_device *adev)
1542 {
1543         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
1544         struct ras_manager *obj, *tmp;
1545
1546         list_for_each_entry_safe(obj, tmp, &con->head, node) {
1547                 amdgpu_ras_sysfs_remove(adev, &obj->head);
1548         }
1549
1550         if (amdgpu_bad_page_threshold != 0)
1551                 amdgpu_ras_sysfs_remove_bad_page_node(adev);
1552
1553         amdgpu_ras_sysfs_remove_dev_attr_node(adev);
1554
1555         return 0;
1556 }
1557 /* sysfs end */
1558
1559 /**
1560  * DOC: AMDGPU RAS Reboot Behavior for Unrecoverable Errors
1561  *
1562  * Normally when there is an uncorrectable error, the driver will reset
1563  * the GPU to recover.  However, in the event of an unrecoverable error,
1564  * the driver provides an interface to reboot the system automatically
1565  * in that event.
1566  *
1567  * The following file in debugfs provides that interface:
1568  * /sys/kernel/debug/dri/[0/1/2...]/ras/auto_reboot
1569  *
1570  * Usage:
1571  *
1572  * .. code-block:: bash
1573  *
1574  *      echo true > .../ras/auto_reboot
1575  *
1576  */
1577 /* debugfs begin */
1578 static struct dentry *amdgpu_ras_debugfs_create_ctrl_node(struct amdgpu_device *adev)
1579 {
1580         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
1581         struct amdgpu_ras_eeprom_control *eeprom = &con->eeprom_control;
1582         struct drm_minor  *minor = adev_to_drm(adev)->primary;
1583         struct dentry     *dir;
1584
1585         dir = debugfs_create_dir(RAS_FS_NAME, minor->debugfs_root);
1586         debugfs_create_file("ras_ctrl", S_IWUGO | S_IRUGO, dir, adev,
1587                             &amdgpu_ras_debugfs_ctrl_ops);
1588         debugfs_create_file("ras_eeprom_reset", S_IWUGO | S_IRUGO, dir, adev,
1589                             &amdgpu_ras_debugfs_eeprom_ops);
1590         debugfs_create_u32("bad_page_cnt_threshold", 0444, dir,
1591                            &con->bad_page_cnt_threshold);
1592         debugfs_create_u32("ras_num_recs", 0444, dir, &eeprom->ras_num_recs);
1593         debugfs_create_x32("ras_hw_enabled", 0444, dir, &adev->ras_hw_enabled);
1594         debugfs_create_x32("ras_enabled", 0444, dir, &adev->ras_enabled);
1595         debugfs_create_file("ras_eeprom_size", S_IRUGO, dir, adev,
1596                             &amdgpu_ras_debugfs_eeprom_size_ops);
1597         con->de_ras_eeprom_table = debugfs_create_file("ras_eeprom_table",
1598                                                        S_IRUGO, dir, adev,
1599                                                        &amdgpu_ras_debugfs_eeprom_table_ops);
1600         amdgpu_ras_debugfs_set_ret_size(&con->eeprom_control);
1601
1602         /*
1603          * After one uncorrectable error happens, usually GPU recovery will
1604          * be scheduled. But due to the known problem in GPU recovery failing
1605          * to bring GPU back, below interface provides one direct way to
1606          * user to reboot system automatically in such case within
1607          * ERREVENT_ATHUB_INTERRUPT generated. Normal GPU recovery routine
1608          * will never be called.
1609          */
1610         debugfs_create_bool("auto_reboot", S_IWUGO | S_IRUGO, dir, &con->reboot);
1611
1612         /*
1613          * User could set this not to clean up hardware's error count register
1614          * of RAS IPs during ras recovery.
1615          */
1616         debugfs_create_bool("disable_ras_err_cnt_harvest", 0644, dir,
1617                             &con->disable_ras_err_cnt_harvest);
1618         return dir;
1619 }
1620
1621 static void amdgpu_ras_debugfs_create(struct amdgpu_device *adev,
1622                                       struct ras_fs_if *head,
1623                                       struct dentry *dir)
1624 {
1625         struct ras_manager *obj = amdgpu_ras_find_obj(adev, &head->head);
1626
1627         if (!obj || !dir)
1628                 return;
1629
1630         get_obj(obj);
1631
1632         memcpy(obj->fs_data.debugfs_name,
1633                         head->debugfs_name,
1634                         sizeof(obj->fs_data.debugfs_name));
1635
1636         debugfs_create_file(obj->fs_data.debugfs_name, S_IWUGO | S_IRUGO, dir,
1637                             obj, &amdgpu_ras_debugfs_ops);
1638 }
1639
1640 void amdgpu_ras_debugfs_create_all(struct amdgpu_device *adev)
1641 {
1642         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
1643         struct dentry *dir;
1644         struct ras_manager *obj;
1645         struct ras_fs_if fs_info;
1646
1647         /*
1648          * it won't be called in resume path, no need to check
1649          * suspend and gpu reset status
1650          */
1651         if (!IS_ENABLED(CONFIG_DEBUG_FS) || !con)
1652                 return;
1653
1654         dir = amdgpu_ras_debugfs_create_ctrl_node(adev);
1655
1656         list_for_each_entry(obj, &con->head, node) {
1657                 if (amdgpu_ras_is_supported(adev, obj->head.block) &&
1658                         (obj->attr_inuse == 1)) {
1659                         sprintf(fs_info.debugfs_name, "%s_err_inject",
1660                                         get_ras_block_str(&obj->head));
1661                         fs_info.head = obj->head;
1662                         amdgpu_ras_debugfs_create(adev, &fs_info, dir);
1663                 }
1664         }
1665
1666         amdgpu_mca_smu_debugfs_init(adev, dir);
1667 }
1668
1669 /* debugfs end */
1670
1671 /* ras fs */
1672 static BIN_ATTR(gpu_vram_bad_pages, S_IRUGO,
1673                 amdgpu_ras_sysfs_badpages_read, NULL, 0);
1674 static DEVICE_ATTR(features, S_IRUGO,
1675                 amdgpu_ras_sysfs_features_read, NULL);
1676 static DEVICE_ATTR(version, 0444,
1677                 amdgpu_ras_sysfs_version_show, NULL);
1678 static DEVICE_ATTR(schema, 0444,
1679                 amdgpu_ras_sysfs_schema_show, NULL);
1680 static int amdgpu_ras_fs_init(struct amdgpu_device *adev)
1681 {
1682         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
1683         struct attribute_group group = {
1684                 .name = RAS_FS_NAME,
1685         };
1686         struct attribute *attrs[] = {
1687                 &con->features_attr.attr,
1688                 &con->version_attr.attr,
1689                 &con->schema_attr.attr,
1690                 NULL
1691         };
1692         struct bin_attribute *bin_attrs[] = {
1693                 NULL,
1694                 NULL,
1695         };
1696         int r;
1697
1698         group.attrs = attrs;
1699
1700         /* add features entry */
1701         con->features_attr = dev_attr_features;
1702         sysfs_attr_init(attrs[0]);
1703
1704         /* add version entry */
1705         con->version_attr = dev_attr_version;
1706         sysfs_attr_init(attrs[1]);
1707
1708         /* add schema entry */
1709         con->schema_attr = dev_attr_schema;
1710         sysfs_attr_init(attrs[2]);
1711
1712         if (amdgpu_bad_page_threshold != 0) {
1713                 /* add bad_page_features entry */
1714                 bin_attr_gpu_vram_bad_pages.private = NULL;
1715                 con->badpages_attr = bin_attr_gpu_vram_bad_pages;
1716                 bin_attrs[0] = &con->badpages_attr;
1717                 group.bin_attrs = bin_attrs;
1718                 sysfs_bin_attr_init(bin_attrs[0]);
1719         }
1720
1721         r = sysfs_create_group(&adev->dev->kobj, &group);
1722         if (r)
1723                 dev_err(adev->dev, "Failed to create RAS sysfs group!");
1724
1725         return 0;
1726 }
1727
1728 static int amdgpu_ras_fs_fini(struct amdgpu_device *adev)
1729 {
1730         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
1731         struct ras_manager *con_obj, *ip_obj, *tmp;
1732
1733         if (IS_ENABLED(CONFIG_DEBUG_FS)) {
1734                 list_for_each_entry_safe(con_obj, tmp, &con->head, node) {
1735                         ip_obj = amdgpu_ras_find_obj(adev, &con_obj->head);
1736                         if (ip_obj)
1737                                 put_obj(ip_obj);
1738                 }
1739         }
1740
1741         amdgpu_ras_sysfs_remove_all(adev);
1742         return 0;
1743 }
1744 /* ras fs end */
1745
1746 /* ih begin */
1747
1748 /* For the hardware that cannot enable bif ring for both ras_controller_irq
1749  * and ras_err_evnet_athub_irq ih cookies, the driver has to poll status
1750  * register to check whether the interrupt is triggered or not, and properly
1751  * ack the interrupt if it is there
1752  */
1753 void amdgpu_ras_interrupt_fatal_error_handler(struct amdgpu_device *adev)
1754 {
1755         /* Fatal error events are handled on host side */
1756         if (amdgpu_sriov_vf(adev))
1757                 return;
1758
1759         if (adev->nbio.ras &&
1760             adev->nbio.ras->handle_ras_controller_intr_no_bifring)
1761                 adev->nbio.ras->handle_ras_controller_intr_no_bifring(adev);
1762
1763         if (adev->nbio.ras &&
1764             adev->nbio.ras->handle_ras_err_event_athub_intr_no_bifring)
1765                 adev->nbio.ras->handle_ras_err_event_athub_intr_no_bifring(adev);
1766 }
1767
1768 static void amdgpu_ras_interrupt_poison_consumption_handler(struct ras_manager *obj,
1769                                 struct amdgpu_iv_entry *entry)
1770 {
1771         bool poison_stat = false;
1772         struct amdgpu_device *adev = obj->adev;
1773         struct amdgpu_ras_block_object *block_obj =
1774                 amdgpu_ras_get_ras_block(adev, obj->head.block, 0);
1775
1776         if (!block_obj)
1777                 return;
1778
1779         /* both query_poison_status and handle_poison_consumption are optional,
1780          * but at least one of them should be implemented if we need poison
1781          * consumption handler
1782          */
1783         if (block_obj->hw_ops && block_obj->hw_ops->query_poison_status) {
1784                 poison_stat = block_obj->hw_ops->query_poison_status(adev);
1785                 if (!poison_stat) {
1786                         /* Not poison consumption interrupt, no need to handle it */
1787                         dev_info(adev->dev, "No RAS poison status in %s poison IH.\n",
1788                                         block_obj->ras_comm.name);
1789
1790                         return;
1791                 }
1792         }
1793
1794         amdgpu_umc_poison_handler(adev, false);
1795
1796         if (block_obj->hw_ops && block_obj->hw_ops->handle_poison_consumption)
1797                 poison_stat = block_obj->hw_ops->handle_poison_consumption(adev);
1798
1799         /* gpu reset is fallback for failed and default cases */
1800         if (poison_stat) {
1801                 dev_info(adev->dev, "GPU reset for %s RAS poison consumption is issued!\n",
1802                                 block_obj->ras_comm.name);
1803                 amdgpu_ras_reset_gpu(adev);
1804         } else {
1805                 amdgpu_gfx_poison_consumption_handler(adev, entry);
1806         }
1807 }
1808
1809 static void amdgpu_ras_interrupt_poison_creation_handler(struct ras_manager *obj,
1810                                 struct amdgpu_iv_entry *entry)
1811 {
1812         dev_info(obj->adev->dev,
1813                 "Poison is created, no user action is needed.\n");
1814 }
1815
1816 static void amdgpu_ras_interrupt_umc_handler(struct ras_manager *obj,
1817                                 struct amdgpu_iv_entry *entry)
1818 {
1819         struct ras_ih_data *data = &obj->ih_data;
1820         struct ras_err_data err_data;
1821         int ret;
1822
1823         if (!data->cb)
1824                 return;
1825
1826         ret = amdgpu_ras_error_data_init(&err_data);
1827         if (ret)
1828                 return;
1829
1830         /* Let IP handle its data, maybe we need get the output
1831          * from the callback to update the error type/count, etc
1832          */
1833         ret = data->cb(obj->adev, &err_data, entry);
1834         /* ue will trigger an interrupt, and in that case
1835          * we need do a reset to recovery the whole system.
1836          * But leave IP do that recovery, here we just dispatch
1837          * the error.
1838          */
1839         if (ret == AMDGPU_RAS_SUCCESS) {
1840                 /* these counts could be left as 0 if
1841                  * some blocks do not count error number
1842                  */
1843                 obj->err_data.ue_count += err_data.ue_count;
1844                 obj->err_data.ce_count += err_data.ce_count;
1845         }
1846
1847         amdgpu_ras_error_data_fini(&err_data);
1848 }
1849
1850 static void amdgpu_ras_interrupt_handler(struct ras_manager *obj)
1851 {
1852         struct ras_ih_data *data = &obj->ih_data;
1853         struct amdgpu_iv_entry entry;
1854
1855         while (data->rptr != data->wptr) {
1856                 rmb();
1857                 memcpy(&entry, &data->ring[data->rptr],
1858                                 data->element_size);
1859
1860                 wmb();
1861                 data->rptr = (data->aligned_element_size +
1862                                 data->rptr) % data->ring_size;
1863
1864                 if (amdgpu_ras_is_poison_mode_supported(obj->adev)) {
1865                         if (obj->head.block == AMDGPU_RAS_BLOCK__UMC)
1866                                 amdgpu_ras_interrupt_poison_creation_handler(obj, &entry);
1867                         else
1868                                 amdgpu_ras_interrupt_poison_consumption_handler(obj, &entry);
1869                 } else {
1870                         if (obj->head.block == AMDGPU_RAS_BLOCK__UMC)
1871                                 amdgpu_ras_interrupt_umc_handler(obj, &entry);
1872                         else
1873                                 dev_warn(obj->adev->dev,
1874                                         "No RAS interrupt handler for non-UMC block with poison disabled.\n");
1875                 }
1876         }
1877 }
1878
1879 static void amdgpu_ras_interrupt_process_handler(struct work_struct *work)
1880 {
1881         struct ras_ih_data *data =
1882                 container_of(work, struct ras_ih_data, ih_work);
1883         struct ras_manager *obj =
1884                 container_of(data, struct ras_manager, ih_data);
1885
1886         amdgpu_ras_interrupt_handler(obj);
1887 }
1888
1889 int amdgpu_ras_interrupt_dispatch(struct amdgpu_device *adev,
1890                 struct ras_dispatch_if *info)
1891 {
1892         struct ras_manager *obj = amdgpu_ras_find_obj(adev, &info->head);
1893         struct ras_ih_data *data = &obj->ih_data;
1894
1895         if (!obj)
1896                 return -EINVAL;
1897
1898         if (data->inuse == 0)
1899                 return 0;
1900
1901         /* Might be overflow... */
1902         memcpy(&data->ring[data->wptr], info->entry,
1903                         data->element_size);
1904
1905         wmb();
1906         data->wptr = (data->aligned_element_size +
1907                         data->wptr) % data->ring_size;
1908
1909         schedule_work(&data->ih_work);
1910
1911         return 0;
1912 }
1913
1914 int amdgpu_ras_interrupt_remove_handler(struct amdgpu_device *adev,
1915                 struct ras_common_if *head)
1916 {
1917         struct ras_manager *obj = amdgpu_ras_find_obj(adev, head);
1918         struct ras_ih_data *data;
1919
1920         if (!obj)
1921                 return -EINVAL;
1922
1923         data = &obj->ih_data;
1924         if (data->inuse == 0)
1925                 return 0;
1926
1927         cancel_work_sync(&data->ih_work);
1928
1929         kfree(data->ring);
1930         memset(data, 0, sizeof(*data));
1931         put_obj(obj);
1932
1933         return 0;
1934 }
1935
1936 int amdgpu_ras_interrupt_add_handler(struct amdgpu_device *adev,
1937                 struct ras_common_if *head)
1938 {
1939         struct ras_manager *obj = amdgpu_ras_find_obj(adev, head);
1940         struct ras_ih_data *data;
1941         struct amdgpu_ras_block_object *ras_obj;
1942
1943         if (!obj) {
1944                 /* in case we registe the IH before enable ras feature */
1945                 obj = amdgpu_ras_create_obj(adev, head);
1946                 if (!obj)
1947                         return -EINVAL;
1948         } else
1949                 get_obj(obj);
1950
1951         ras_obj = container_of(head, struct amdgpu_ras_block_object, ras_comm);
1952
1953         data = &obj->ih_data;
1954         /* add the callback.etc */
1955         *data = (struct ras_ih_data) {
1956                 .inuse = 0,
1957                 .cb = ras_obj->ras_cb,
1958                 .element_size = sizeof(struct amdgpu_iv_entry),
1959                 .rptr = 0,
1960                 .wptr = 0,
1961         };
1962
1963         INIT_WORK(&data->ih_work, amdgpu_ras_interrupt_process_handler);
1964
1965         data->aligned_element_size = ALIGN(data->element_size, 8);
1966         /* the ring can store 64 iv entries. */
1967         data->ring_size = 64 * data->aligned_element_size;
1968         data->ring = kmalloc(data->ring_size, GFP_KERNEL);
1969         if (!data->ring) {
1970                 put_obj(obj);
1971                 return -ENOMEM;
1972         }
1973
1974         /* IH is ready */
1975         data->inuse = 1;
1976
1977         return 0;
1978 }
1979
1980 static int amdgpu_ras_interrupt_remove_all(struct amdgpu_device *adev)
1981 {
1982         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
1983         struct ras_manager *obj, *tmp;
1984
1985         list_for_each_entry_safe(obj, tmp, &con->head, node) {
1986                 amdgpu_ras_interrupt_remove_handler(adev, &obj->head);
1987         }
1988
1989         return 0;
1990 }
1991 /* ih end */
1992
1993 /* traversal all IPs except NBIO to query error counter */
1994 static void amdgpu_ras_log_on_err_counter(struct amdgpu_device *adev)
1995 {
1996         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
1997         struct ras_manager *obj;
1998
1999         if (!adev->ras_enabled || !con)
2000                 return;
2001
2002         list_for_each_entry(obj, &con->head, node) {
2003                 struct ras_query_if info = {
2004                         .head = obj->head,
2005                 };
2006
2007                 /*
2008                  * PCIE_BIF IP has one different isr by ras controller
2009                  * interrupt, the specific ras counter query will be
2010                  * done in that isr. So skip such block from common
2011                  * sync flood interrupt isr calling.
2012                  */
2013                 if (info.head.block == AMDGPU_RAS_BLOCK__PCIE_BIF)
2014                         continue;
2015
2016                 /*
2017                  * this is a workaround for aldebaran, skip send msg to
2018                  * smu to get ecc_info table due to smu handle get ecc
2019                  * info table failed temporarily.
2020                  * should be removed until smu fix handle ecc_info table.
2021                  */
2022                 if ((info.head.block == AMDGPU_RAS_BLOCK__UMC) &&
2023                     (amdgpu_ip_version(adev, MP1_HWIP, 0) ==
2024                      IP_VERSION(13, 0, 2)))
2025                         continue;
2026
2027                 amdgpu_ras_query_error_status(adev, &info);
2028
2029                 if (amdgpu_ip_version(adev, MP0_HWIP, 0) !=
2030                             IP_VERSION(11, 0, 2) &&
2031                     amdgpu_ip_version(adev, MP0_HWIP, 0) !=
2032                             IP_VERSION(11, 0, 4) &&
2033                     amdgpu_ip_version(adev, MP0_HWIP, 0) !=
2034                             IP_VERSION(13, 0, 0)) {
2035                         if (amdgpu_ras_reset_error_status(adev, info.head.block))
2036                                 dev_warn(adev->dev, "Failed to reset error counter and error status");
2037                 }
2038         }
2039 }
2040
2041 /* Parse RdRspStatus and WrRspStatus */
2042 static void amdgpu_ras_error_status_query(struct amdgpu_device *adev,
2043                                           struct ras_query_if *info)
2044 {
2045         struct amdgpu_ras_block_object *block_obj;
2046         /*
2047          * Only two block need to query read/write
2048          * RspStatus at current state
2049          */
2050         if ((info->head.block != AMDGPU_RAS_BLOCK__GFX) &&
2051                 (info->head.block != AMDGPU_RAS_BLOCK__MMHUB))
2052                 return;
2053
2054         block_obj = amdgpu_ras_get_ras_block(adev,
2055                                         info->head.block,
2056                                         info->head.sub_block_index);
2057
2058         if (!block_obj || !block_obj->hw_ops) {
2059                 dev_dbg_once(adev->dev, "%s doesn't config RAS function\n",
2060                              get_ras_block_str(&info->head));
2061                 return;
2062         }
2063
2064         if (block_obj->hw_ops->query_ras_error_status)
2065                 block_obj->hw_ops->query_ras_error_status(adev);
2066
2067 }
2068
2069 static void amdgpu_ras_query_err_status(struct amdgpu_device *adev)
2070 {
2071         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
2072         struct ras_manager *obj;
2073
2074         if (!adev->ras_enabled || !con)
2075                 return;
2076
2077         list_for_each_entry(obj, &con->head, node) {
2078                 struct ras_query_if info = {
2079                         .head = obj->head,
2080                 };
2081
2082                 amdgpu_ras_error_status_query(adev, &info);
2083         }
2084 }
2085
2086 /* recovery begin */
2087
2088 /* return 0 on success.
2089  * caller need free bps.
2090  */
2091 static int amdgpu_ras_badpages_read(struct amdgpu_device *adev,
2092                 struct ras_badpage **bps, unsigned int *count)
2093 {
2094         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
2095         struct ras_err_handler_data *data;
2096         int i = 0;
2097         int ret = 0, status;
2098
2099         if (!con || !con->eh_data || !bps || !count)
2100                 return -EINVAL;
2101
2102         mutex_lock(&con->recovery_lock);
2103         data = con->eh_data;
2104         if (!data || data->count == 0) {
2105                 *bps = NULL;
2106                 ret = -EINVAL;
2107                 goto out;
2108         }
2109
2110         *bps = kmalloc(sizeof(struct ras_badpage) * data->count, GFP_KERNEL);
2111         if (!*bps) {
2112                 ret = -ENOMEM;
2113                 goto out;
2114         }
2115
2116         for (; i < data->count; i++) {
2117                 (*bps)[i] = (struct ras_badpage){
2118                         .bp = data->bps[i].retired_page,
2119                         .size = AMDGPU_GPU_PAGE_SIZE,
2120                         .flags = AMDGPU_RAS_RETIRE_PAGE_RESERVED,
2121                 };
2122                 status = amdgpu_vram_mgr_query_page_status(&adev->mman.vram_mgr,
2123                                 data->bps[i].retired_page);
2124                 if (status == -EBUSY)
2125                         (*bps)[i].flags = AMDGPU_RAS_RETIRE_PAGE_PENDING;
2126                 else if (status == -ENOENT)
2127                         (*bps)[i].flags = AMDGPU_RAS_RETIRE_PAGE_FAULT;
2128         }
2129
2130         *count = data->count;
2131 out:
2132         mutex_unlock(&con->recovery_lock);
2133         return ret;
2134 }
2135
2136 static void amdgpu_ras_do_recovery(struct work_struct *work)
2137 {
2138         struct amdgpu_ras *ras =
2139                 container_of(work, struct amdgpu_ras, recovery_work);
2140         struct amdgpu_device *remote_adev = NULL;
2141         struct amdgpu_device *adev = ras->adev;
2142         struct list_head device_list, *device_list_handle =  NULL;
2143
2144         if (!ras->disable_ras_err_cnt_harvest) {
2145                 struct amdgpu_hive_info *hive = amdgpu_get_xgmi_hive(adev);
2146
2147                 /* Build list of devices to query RAS related errors */
2148                 if  (hive && adev->gmc.xgmi.num_physical_nodes > 1) {
2149                         device_list_handle = &hive->device_list;
2150                 } else {
2151                         INIT_LIST_HEAD(&device_list);
2152                         list_add_tail(&adev->gmc.xgmi.head, &device_list);
2153                         device_list_handle = &device_list;
2154                 }
2155
2156                 list_for_each_entry(remote_adev,
2157                                 device_list_handle, gmc.xgmi.head) {
2158                         amdgpu_ras_query_err_status(remote_adev);
2159                         amdgpu_ras_log_on_err_counter(remote_adev);
2160                 }
2161
2162                 amdgpu_put_xgmi_hive(hive);
2163         }
2164
2165         if (amdgpu_device_should_recover_gpu(ras->adev)) {
2166                 struct amdgpu_reset_context reset_context;
2167                 memset(&reset_context, 0, sizeof(reset_context));
2168
2169                 reset_context.method = AMD_RESET_METHOD_NONE;
2170                 reset_context.reset_req_dev = adev;
2171
2172                 /* Perform full reset in fatal error mode */
2173                 if (!amdgpu_ras_is_poison_mode_supported(ras->adev))
2174                         set_bit(AMDGPU_NEED_FULL_RESET, &reset_context.flags);
2175                 else {
2176                         clear_bit(AMDGPU_NEED_FULL_RESET, &reset_context.flags);
2177
2178                         if (ras->gpu_reset_flags & AMDGPU_RAS_GPU_RESET_MODE2_RESET) {
2179                                 ras->gpu_reset_flags &= ~AMDGPU_RAS_GPU_RESET_MODE2_RESET;
2180                                 reset_context.method = AMD_RESET_METHOD_MODE2;
2181                         }
2182
2183                         /* Fatal error occurs in poison mode, mode1 reset is used to
2184                          * recover gpu.
2185                          */
2186                         if (ras->gpu_reset_flags & AMDGPU_RAS_GPU_RESET_MODE1_RESET) {
2187                                 ras->gpu_reset_flags &= ~AMDGPU_RAS_GPU_RESET_MODE1_RESET;
2188                                 set_bit(AMDGPU_NEED_FULL_RESET, &reset_context.flags);
2189
2190                                 psp_fatal_error_recovery_quirk(&adev->psp);
2191                         }
2192                 }
2193
2194                 amdgpu_device_gpu_recover(ras->adev, NULL, &reset_context);
2195         }
2196         atomic_set(&ras->in_recovery, 0);
2197 }
2198
2199 /* alloc/realloc bps array */
2200 static int amdgpu_ras_realloc_eh_data_space(struct amdgpu_device *adev,
2201                 struct ras_err_handler_data *data, int pages)
2202 {
2203         unsigned int old_space = data->count + data->space_left;
2204         unsigned int new_space = old_space + pages;
2205         unsigned int align_space = ALIGN(new_space, 512);
2206         void *bps = kmalloc(align_space * sizeof(*data->bps), GFP_KERNEL);
2207
2208         if (!bps) {
2209                 return -ENOMEM;
2210         }
2211
2212         if (data->bps) {
2213                 memcpy(bps, data->bps,
2214                                 data->count * sizeof(*data->bps));
2215                 kfree(data->bps);
2216         }
2217
2218         data->bps = bps;
2219         data->space_left += align_space - old_space;
2220         return 0;
2221 }
2222
2223 /* it deal with vram only. */
2224 int amdgpu_ras_add_bad_pages(struct amdgpu_device *adev,
2225                 struct eeprom_table_record *bps, int pages)
2226 {
2227         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
2228         struct ras_err_handler_data *data;
2229         int ret = 0;
2230         uint32_t i;
2231
2232         if (!con || !con->eh_data || !bps || pages <= 0)
2233                 return 0;
2234
2235         mutex_lock(&con->recovery_lock);
2236         data = con->eh_data;
2237         if (!data)
2238                 goto out;
2239
2240         for (i = 0; i < pages; i++) {
2241                 if (amdgpu_ras_check_bad_page_unlock(con,
2242                         bps[i].retired_page << AMDGPU_GPU_PAGE_SHIFT))
2243                         continue;
2244
2245                 if (!data->space_left &&
2246                         amdgpu_ras_realloc_eh_data_space(adev, data, 256)) {
2247                         ret = -ENOMEM;
2248                         goto out;
2249                 }
2250
2251                 amdgpu_vram_mgr_reserve_range(&adev->mman.vram_mgr,
2252                         bps[i].retired_page << AMDGPU_GPU_PAGE_SHIFT,
2253                         AMDGPU_GPU_PAGE_SIZE);
2254
2255                 memcpy(&data->bps[data->count], &bps[i], sizeof(*data->bps));
2256                 data->count++;
2257                 data->space_left--;
2258         }
2259 out:
2260         mutex_unlock(&con->recovery_lock);
2261
2262         return ret;
2263 }
2264
2265 /*
2266  * write error record array to eeprom, the function should be
2267  * protected by recovery_lock
2268  * new_cnt: new added UE count, excluding reserved bad pages, can be NULL
2269  */
2270 int amdgpu_ras_save_bad_pages(struct amdgpu_device *adev,
2271                 unsigned long *new_cnt)
2272 {
2273         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
2274         struct ras_err_handler_data *data;
2275         struct amdgpu_ras_eeprom_control *control;
2276         int save_count;
2277
2278         if (!con || !con->eh_data) {
2279                 if (new_cnt)
2280                         *new_cnt = 0;
2281
2282                 return 0;
2283         }
2284
2285         mutex_lock(&con->recovery_lock);
2286         control = &con->eeprom_control;
2287         data = con->eh_data;
2288         save_count = data->count - control->ras_num_recs;
2289         mutex_unlock(&con->recovery_lock);
2290
2291         if (new_cnt)
2292                 *new_cnt = save_count / adev->umc.retire_unit;
2293
2294         /* only new entries are saved */
2295         if (save_count > 0) {
2296                 if (amdgpu_ras_eeprom_append(control,
2297                                              &data->bps[control->ras_num_recs],
2298                                              save_count)) {
2299                         dev_err(adev->dev, "Failed to save EEPROM table data!");
2300                         return -EIO;
2301                 }
2302
2303                 dev_info(adev->dev, "Saved %d pages to EEPROM table.\n", save_count);
2304         }
2305
2306         return 0;
2307 }
2308
2309 /*
2310  * read error record array in eeprom and reserve enough space for
2311  * storing new bad pages
2312  */
2313 static int amdgpu_ras_load_bad_pages(struct amdgpu_device *adev)
2314 {
2315         struct amdgpu_ras_eeprom_control *control =
2316                 &adev->psp.ras_context.ras->eeprom_control;
2317         struct eeprom_table_record *bps;
2318         int ret;
2319
2320         /* no bad page record, skip eeprom access */
2321         if (control->ras_num_recs == 0 || amdgpu_bad_page_threshold == 0)
2322                 return 0;
2323
2324         bps = kcalloc(control->ras_num_recs, sizeof(*bps), GFP_KERNEL);
2325         if (!bps)
2326                 return -ENOMEM;
2327
2328         ret = amdgpu_ras_eeprom_read(control, bps, control->ras_num_recs);
2329         if (ret)
2330                 dev_err(adev->dev, "Failed to load EEPROM table records!");
2331         else
2332                 ret = amdgpu_ras_add_bad_pages(adev, bps, control->ras_num_recs);
2333
2334         kfree(bps);
2335         return ret;
2336 }
2337
2338 static bool amdgpu_ras_check_bad_page_unlock(struct amdgpu_ras *con,
2339                                 uint64_t addr)
2340 {
2341         struct ras_err_handler_data *data = con->eh_data;
2342         int i;
2343
2344         addr >>= AMDGPU_GPU_PAGE_SHIFT;
2345         for (i = 0; i < data->count; i++)
2346                 if (addr == data->bps[i].retired_page)
2347                         return true;
2348
2349         return false;
2350 }
2351
2352 /*
2353  * check if an address belongs to bad page
2354  *
2355  * Note: this check is only for umc block
2356  */
2357 static bool amdgpu_ras_check_bad_page(struct amdgpu_device *adev,
2358                                 uint64_t addr)
2359 {
2360         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
2361         bool ret = false;
2362
2363         if (!con || !con->eh_data)
2364                 return ret;
2365
2366         mutex_lock(&con->recovery_lock);
2367         ret = amdgpu_ras_check_bad_page_unlock(con, addr);
2368         mutex_unlock(&con->recovery_lock);
2369         return ret;
2370 }
2371
2372 static void amdgpu_ras_validate_threshold(struct amdgpu_device *adev,
2373                                           uint32_t max_count)
2374 {
2375         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
2376
2377         /*
2378          * Justification of value bad_page_cnt_threshold in ras structure
2379          *
2380          * Generally, 0 <= amdgpu_bad_page_threshold <= max record length
2381          * in eeprom or amdgpu_bad_page_threshold == -2, introduce two
2382          * scenarios accordingly.
2383          *
2384          * Bad page retirement enablement:
2385          *    - If amdgpu_bad_page_threshold = -2,
2386          *      bad_page_cnt_threshold = typical value by formula.
2387          *
2388          *    - When the value from user is 0 < amdgpu_bad_page_threshold <
2389          *      max record length in eeprom, use it directly.
2390          *
2391          * Bad page retirement disablement:
2392          *    - If amdgpu_bad_page_threshold = 0, bad page retirement
2393          *      functionality is disabled, and bad_page_cnt_threshold will
2394          *      take no effect.
2395          */
2396
2397         if (amdgpu_bad_page_threshold < 0) {
2398                 u64 val = adev->gmc.mc_vram_size;
2399
2400                 do_div(val, RAS_BAD_PAGE_COVER);
2401                 con->bad_page_cnt_threshold = min(lower_32_bits(val),
2402                                                   max_count);
2403         } else {
2404                 con->bad_page_cnt_threshold = min_t(int, max_count,
2405                                                     amdgpu_bad_page_threshold);
2406         }
2407 }
2408
2409 int amdgpu_ras_recovery_init(struct amdgpu_device *adev)
2410 {
2411         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
2412         struct ras_err_handler_data **data;
2413         u32  max_eeprom_records_count = 0;
2414         bool exc_err_limit = false;
2415         int ret;
2416
2417         if (!con || amdgpu_sriov_vf(adev))
2418                 return 0;
2419
2420         /* Allow access to RAS EEPROM via debugfs, when the ASIC
2421          * supports RAS and debugfs is enabled, but when
2422          * adev->ras_enabled is unset, i.e. when "ras_enable"
2423          * module parameter is set to 0.
2424          */
2425         con->adev = adev;
2426
2427         if (!adev->ras_enabled)
2428                 return 0;
2429
2430         data = &con->eh_data;
2431         *data = kmalloc(sizeof(**data), GFP_KERNEL | __GFP_ZERO);
2432         if (!*data) {
2433                 ret = -ENOMEM;
2434                 goto out;
2435         }
2436
2437         mutex_init(&con->recovery_lock);
2438         INIT_WORK(&con->recovery_work, amdgpu_ras_do_recovery);
2439         atomic_set(&con->in_recovery, 0);
2440         con->eeprom_control.bad_channel_bitmap = 0;
2441
2442         max_eeprom_records_count = amdgpu_ras_eeprom_max_record_count(&con->eeprom_control);
2443         amdgpu_ras_validate_threshold(adev, max_eeprom_records_count);
2444
2445         /* Todo: During test the SMU might fail to read the eeprom through I2C
2446          * when the GPU is pending on XGMI reset during probe time
2447          * (Mostly after second bus reset), skip it now
2448          */
2449         if (adev->gmc.xgmi.pending_reset)
2450                 return 0;
2451         ret = amdgpu_ras_eeprom_init(&con->eeprom_control, &exc_err_limit);
2452         /*
2453          * This calling fails when exc_err_limit is true or
2454          * ret != 0.
2455          */
2456         if (exc_err_limit || ret)
2457                 goto free;
2458
2459         if (con->eeprom_control.ras_num_recs) {
2460                 ret = amdgpu_ras_load_bad_pages(adev);
2461                 if (ret)
2462                         goto free;
2463
2464                 amdgpu_dpm_send_hbm_bad_pages_num(adev, con->eeprom_control.ras_num_recs);
2465
2466                 if (con->update_channel_flag == true) {
2467                         amdgpu_dpm_send_hbm_bad_channel_flag(adev, con->eeprom_control.bad_channel_bitmap);
2468                         con->update_channel_flag = false;
2469                 }
2470         }
2471
2472 #ifdef CONFIG_X86_MCE_AMD
2473         if ((adev->asic_type == CHIP_ALDEBARAN) &&
2474             (adev->gmc.xgmi.connected_to_cpu))
2475                 amdgpu_register_bad_pages_mca_notifier(adev);
2476 #endif
2477         return 0;
2478
2479 free:
2480         kfree((*data)->bps);
2481         kfree(*data);
2482         con->eh_data = NULL;
2483 out:
2484         dev_warn(adev->dev, "Failed to initialize ras recovery! (%d)\n", ret);
2485
2486         /*
2487          * Except error threshold exceeding case, other failure cases in this
2488          * function would not fail amdgpu driver init.
2489          */
2490         if (!exc_err_limit)
2491                 ret = 0;
2492         else
2493                 ret = -EINVAL;
2494
2495         return ret;
2496 }
2497
2498 static int amdgpu_ras_recovery_fini(struct amdgpu_device *adev)
2499 {
2500         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
2501         struct ras_err_handler_data *data = con->eh_data;
2502
2503         /* recovery_init failed to init it, fini is useless */
2504         if (!data)
2505                 return 0;
2506
2507         cancel_work_sync(&con->recovery_work);
2508
2509         mutex_lock(&con->recovery_lock);
2510         con->eh_data = NULL;
2511         kfree(data->bps);
2512         kfree(data);
2513         mutex_unlock(&con->recovery_lock);
2514
2515         return 0;
2516 }
2517 /* recovery end */
2518
2519 static bool amdgpu_ras_asic_supported(struct amdgpu_device *adev)
2520 {
2521         if (amdgpu_sriov_vf(adev)) {
2522                 switch (amdgpu_ip_version(adev, MP0_HWIP, 0)) {
2523                 case IP_VERSION(13, 0, 2):
2524                 case IP_VERSION(13, 0, 6):
2525                         return true;
2526                 default:
2527                         return false;
2528                 }
2529         }
2530
2531         if (adev->asic_type == CHIP_IP_DISCOVERY) {
2532                 switch (amdgpu_ip_version(adev, MP0_HWIP, 0)) {
2533                 case IP_VERSION(13, 0, 0):
2534                 case IP_VERSION(13, 0, 6):
2535                 case IP_VERSION(13, 0, 10):
2536                         return true;
2537                 default:
2538                         return false;
2539                 }
2540         }
2541
2542         return adev->asic_type == CHIP_VEGA10 ||
2543                 adev->asic_type == CHIP_VEGA20 ||
2544                 adev->asic_type == CHIP_ARCTURUS ||
2545                 adev->asic_type == CHIP_ALDEBARAN ||
2546                 adev->asic_type == CHIP_SIENNA_CICHLID;
2547 }
2548
2549 /*
2550  * this is workaround for vega20 workstation sku,
2551  * force enable gfx ras, ignore vbios gfx ras flag
2552  * due to GC EDC can not write
2553  */
2554 static void amdgpu_ras_get_quirks(struct amdgpu_device *adev)
2555 {
2556         struct atom_context *ctx = adev->mode_info.atom_context;
2557
2558         if (!ctx)
2559                 return;
2560
2561         if (strnstr(ctx->vbios_pn, "D16406",
2562                     sizeof(ctx->vbios_pn)) ||
2563                 strnstr(ctx->vbios_pn, "D36002",
2564                         sizeof(ctx->vbios_pn)))
2565                 adev->ras_hw_enabled |= (1 << AMDGPU_RAS_BLOCK__GFX);
2566 }
2567
2568 /*
2569  * check hardware's ras ability which will be saved in hw_supported.
2570  * if hardware does not support ras, we can skip some ras initializtion and
2571  * forbid some ras operations from IP.
2572  * if software itself, say boot parameter, limit the ras ability. We still
2573  * need allow IP do some limited operations, like disable. In such case,
2574  * we have to initialize ras as normal. but need check if operation is
2575  * allowed or not in each function.
2576  */
2577 static void amdgpu_ras_check_supported(struct amdgpu_device *adev)
2578 {
2579         adev->ras_hw_enabled = adev->ras_enabled = 0;
2580
2581         if (!amdgpu_ras_asic_supported(adev))
2582                 return;
2583
2584         if (!adev->gmc.xgmi.connected_to_cpu && !adev->gmc.is_app_apu) {
2585                 if (amdgpu_atomfirmware_mem_ecc_supported(adev)) {
2586                         dev_info(adev->dev, "MEM ECC is active.\n");
2587                         adev->ras_hw_enabled |= (1 << AMDGPU_RAS_BLOCK__UMC |
2588                                                    1 << AMDGPU_RAS_BLOCK__DF);
2589                 } else {
2590                         dev_info(adev->dev, "MEM ECC is not presented.\n");
2591                 }
2592
2593                 if (amdgpu_atomfirmware_sram_ecc_supported(adev)) {
2594                         dev_info(adev->dev, "SRAM ECC is active.\n");
2595                         if (!amdgpu_sriov_vf(adev))
2596                                 adev->ras_hw_enabled |= ~(1 << AMDGPU_RAS_BLOCK__UMC |
2597                                                             1 << AMDGPU_RAS_BLOCK__DF);
2598                         else
2599                                 adev->ras_hw_enabled |= (1 << AMDGPU_RAS_BLOCK__PCIE_BIF |
2600                                                                 1 << AMDGPU_RAS_BLOCK__SDMA |
2601                                                                 1 << AMDGPU_RAS_BLOCK__GFX);
2602
2603                         /* VCN/JPEG RAS can be supported on both bare metal and
2604                          * SRIOV environment
2605                          */
2606                         if (amdgpu_ip_version(adev, VCN_HWIP, 0) ==
2607                                     IP_VERSION(2, 6, 0) ||
2608                             amdgpu_ip_version(adev, VCN_HWIP, 0) ==
2609                                     IP_VERSION(4, 0, 0))
2610                                 adev->ras_hw_enabled |= (1 << AMDGPU_RAS_BLOCK__VCN |
2611                                                         1 << AMDGPU_RAS_BLOCK__JPEG);
2612                         else
2613                                 adev->ras_hw_enabled &= ~(1 << AMDGPU_RAS_BLOCK__VCN |
2614                                                         1 << AMDGPU_RAS_BLOCK__JPEG);
2615
2616                         /*
2617                          * XGMI RAS is not supported if xgmi num physical nodes
2618                          * is zero
2619                          */
2620                         if (!adev->gmc.xgmi.num_physical_nodes)
2621                                 adev->ras_hw_enabled &= ~(1 << AMDGPU_RAS_BLOCK__XGMI_WAFL);
2622                 } else {
2623                         dev_info(adev->dev, "SRAM ECC is not presented.\n");
2624                 }
2625         } else {
2626                 /* driver only manages a few IP blocks RAS feature
2627                  * when GPU is connected cpu through XGMI */
2628                 adev->ras_hw_enabled |= (1 << AMDGPU_RAS_BLOCK__GFX |
2629                                            1 << AMDGPU_RAS_BLOCK__SDMA |
2630                                            1 << AMDGPU_RAS_BLOCK__MMHUB);
2631         }
2632
2633         amdgpu_ras_get_quirks(adev);
2634
2635         /* hw_supported needs to be aligned with RAS block mask. */
2636         adev->ras_hw_enabled &= AMDGPU_RAS_BLOCK_MASK;
2637
2638
2639         /*
2640          * Disable ras feature for aqua vanjaram
2641          * by default on apu platform.
2642          */
2643         if (amdgpu_ip_version(adev, MP0_HWIP, 0) == IP_VERSION(13, 0, 6) &&
2644             adev->gmc.is_app_apu)
2645                 adev->ras_enabled = amdgpu_ras_enable != 1 ? 0 :
2646                         adev->ras_hw_enabled & amdgpu_ras_mask;
2647         else
2648                 adev->ras_enabled = amdgpu_ras_enable == 0 ? 0 :
2649                         adev->ras_hw_enabled & amdgpu_ras_mask;
2650 }
2651
2652 static void amdgpu_ras_counte_dw(struct work_struct *work)
2653 {
2654         struct amdgpu_ras *con = container_of(work, struct amdgpu_ras,
2655                                               ras_counte_delay_work.work);
2656         struct amdgpu_device *adev = con->adev;
2657         struct drm_device *dev = adev_to_drm(adev);
2658         unsigned long ce_count, ue_count;
2659         int res;
2660
2661         res = pm_runtime_get_sync(dev->dev);
2662         if (res < 0)
2663                 goto Out;
2664
2665         /* Cache new values.
2666          */
2667         if (amdgpu_ras_query_error_count(adev, &ce_count, &ue_count, NULL) == 0) {
2668                 atomic_set(&con->ras_ce_count, ce_count);
2669                 atomic_set(&con->ras_ue_count, ue_count);
2670         }
2671
2672         pm_runtime_mark_last_busy(dev->dev);
2673 Out:
2674         pm_runtime_put_autosuspend(dev->dev);
2675 }
2676
2677 static void amdgpu_ras_query_poison_mode(struct amdgpu_device *adev)
2678 {
2679         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
2680         bool df_poison, umc_poison;
2681
2682         /* poison setting is useless on SRIOV guest */
2683         if (amdgpu_sriov_vf(adev) || !con)
2684                 return;
2685
2686         /* Init poison supported flag, the default value is false */
2687         if (adev->gmc.xgmi.connected_to_cpu) {
2688                 /* enabled by default when GPU is connected to CPU */
2689                 con->poison_supported = true;
2690         } else if (adev->df.funcs &&
2691             adev->df.funcs->query_ras_poison_mode &&
2692             adev->umc.ras &&
2693             adev->umc.ras->query_ras_poison_mode) {
2694                 df_poison =
2695                         adev->df.funcs->query_ras_poison_mode(adev);
2696                 umc_poison =
2697                         adev->umc.ras->query_ras_poison_mode(adev);
2698
2699                 /* Only poison is set in both DF and UMC, we can support it */
2700                 if (df_poison && umc_poison)
2701                         con->poison_supported = true;
2702                 else if (df_poison != umc_poison)
2703                         dev_warn(adev->dev,
2704                                 "Poison setting is inconsistent in DF/UMC(%d:%d)!\n",
2705                                 df_poison, umc_poison);
2706         }
2707 }
2708
2709 static int amdgpu_get_ras_schema(struct amdgpu_device *adev)
2710 {
2711         return  amdgpu_ras_is_poison_mode_supported(adev) ? AMDGPU_RAS_ERROR__POISON : 0 |
2712                         AMDGPU_RAS_ERROR__SINGLE_CORRECTABLE |
2713                         AMDGPU_RAS_ERROR__MULTI_UNCORRECTABLE |
2714                         AMDGPU_RAS_ERROR__PARITY;
2715 }
2716
2717 int amdgpu_ras_init(struct amdgpu_device *adev)
2718 {
2719         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
2720         int r;
2721
2722         if (con)
2723                 return 0;
2724
2725         con = kmalloc(sizeof(struct amdgpu_ras) +
2726                         sizeof(struct ras_manager) * AMDGPU_RAS_BLOCK_COUNT +
2727                         sizeof(struct ras_manager) * AMDGPU_RAS_MCA_BLOCK_COUNT,
2728                         GFP_KERNEL|__GFP_ZERO);
2729         if (!con)
2730                 return -ENOMEM;
2731
2732         con->adev = adev;
2733         INIT_DELAYED_WORK(&con->ras_counte_delay_work, amdgpu_ras_counte_dw);
2734         atomic_set(&con->ras_ce_count, 0);
2735         atomic_set(&con->ras_ue_count, 0);
2736
2737         con->objs = (struct ras_manager *)(con + 1);
2738
2739         amdgpu_ras_set_context(adev, con);
2740
2741         amdgpu_ras_check_supported(adev);
2742
2743         if (!adev->ras_enabled || adev->asic_type == CHIP_VEGA10) {
2744                 /* set gfx block ras context feature for VEGA20 Gaming
2745                  * send ras disable cmd to ras ta during ras late init.
2746                  */
2747                 if (!adev->ras_enabled && adev->asic_type == CHIP_VEGA20) {
2748                         con->features |= BIT(AMDGPU_RAS_BLOCK__GFX);
2749
2750                         return 0;
2751                 }
2752
2753                 r = 0;
2754                 goto release_con;
2755         }
2756
2757         con->update_channel_flag = false;
2758         con->features = 0;
2759         con->schema = 0;
2760         INIT_LIST_HEAD(&con->head);
2761         /* Might need get this flag from vbios. */
2762         con->flags = RAS_DEFAULT_FLAGS;
2763
2764         /* initialize nbio ras function ahead of any other
2765          * ras functions so hardware fatal error interrupt
2766          * can be enabled as early as possible */
2767         switch (amdgpu_ip_version(adev, NBIO_HWIP, 0)) {
2768         case IP_VERSION(7, 4, 0):
2769         case IP_VERSION(7, 4, 1):
2770         case IP_VERSION(7, 4, 4):
2771                 if (!adev->gmc.xgmi.connected_to_cpu)
2772                         adev->nbio.ras = &nbio_v7_4_ras;
2773                 break;
2774         case IP_VERSION(4, 3, 0):
2775                 if (adev->ras_hw_enabled & (1 << AMDGPU_RAS_BLOCK__DF))
2776                         /* unlike other generation of nbio ras,
2777                          * nbio v4_3 only support fatal error interrupt
2778                          * to inform software that DF is freezed due to
2779                          * system fatal error event. driver should not
2780                          * enable nbio ras in such case. Instead,
2781                          * check DF RAS */
2782                         adev->nbio.ras = &nbio_v4_3_ras;
2783                 break;
2784         case IP_VERSION(7, 9, 0):
2785                 if (!adev->gmc.is_app_apu)
2786                         adev->nbio.ras = &nbio_v7_9_ras;
2787                 break;
2788         default:
2789                 /* nbio ras is not available */
2790                 break;
2791         }
2792
2793         /* nbio ras block needs to be enabled ahead of other ras blocks
2794          * to handle fatal error */
2795         r = amdgpu_nbio_ras_sw_init(adev);
2796         if (r)
2797                 return r;
2798
2799         if (adev->nbio.ras &&
2800             adev->nbio.ras->init_ras_controller_interrupt) {
2801                 r = adev->nbio.ras->init_ras_controller_interrupt(adev);
2802                 if (r)
2803                         goto release_con;
2804         }
2805
2806         if (adev->nbio.ras &&
2807             adev->nbio.ras->init_ras_err_event_athub_interrupt) {
2808                 r = adev->nbio.ras->init_ras_err_event_athub_interrupt(adev);
2809                 if (r)
2810                         goto release_con;
2811         }
2812
2813         amdgpu_ras_query_poison_mode(adev);
2814
2815         /* Get RAS schema for particular SOC */
2816         con->schema = amdgpu_get_ras_schema(adev);
2817
2818         if (amdgpu_ras_fs_init(adev)) {
2819                 r = -EINVAL;
2820                 goto release_con;
2821         }
2822
2823         dev_info(adev->dev, "RAS INFO: ras initialized successfully, "
2824                  "hardware ability[%x] ras_mask[%x]\n",
2825                  adev->ras_hw_enabled, adev->ras_enabled);
2826
2827         return 0;
2828 release_con:
2829         amdgpu_ras_set_context(adev, NULL);
2830         kfree(con);
2831
2832         return r;
2833 }
2834
2835 int amdgpu_persistent_edc_harvesting_supported(struct amdgpu_device *adev)
2836 {
2837         if (adev->gmc.xgmi.connected_to_cpu ||
2838             adev->gmc.is_app_apu)
2839                 return 1;
2840         return 0;
2841 }
2842
2843 static int amdgpu_persistent_edc_harvesting(struct amdgpu_device *adev,
2844                                         struct ras_common_if *ras_block)
2845 {
2846         struct ras_query_if info = {
2847                 .head = *ras_block,
2848         };
2849
2850         if (!amdgpu_persistent_edc_harvesting_supported(adev))
2851                 return 0;
2852
2853         if (amdgpu_ras_query_error_status(adev, &info) != 0)
2854                 DRM_WARN("RAS init harvest failure");
2855
2856         if (amdgpu_ras_reset_error_status(adev, ras_block->block) != 0)
2857                 DRM_WARN("RAS init harvest reset failure");
2858
2859         return 0;
2860 }
2861
2862 bool amdgpu_ras_is_poison_mode_supported(struct amdgpu_device *adev)
2863 {
2864        struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
2865
2866        if (!con)
2867                return false;
2868
2869        return con->poison_supported;
2870 }
2871
2872 /* helper function to handle common stuff in ip late init phase */
2873 int amdgpu_ras_block_late_init(struct amdgpu_device *adev,
2874                          struct ras_common_if *ras_block)
2875 {
2876         struct amdgpu_ras_block_object *ras_obj = NULL;
2877         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
2878         struct ras_query_if *query_info;
2879         unsigned long ue_count, ce_count;
2880         int r;
2881
2882         /* disable RAS feature per IP block if it is not supported */
2883         if (!amdgpu_ras_is_supported(adev, ras_block->block)) {
2884                 amdgpu_ras_feature_enable_on_boot(adev, ras_block, 0);
2885                 return 0;
2886         }
2887
2888         r = amdgpu_ras_feature_enable_on_boot(adev, ras_block, 1);
2889         if (r) {
2890                 if (adev->in_suspend || amdgpu_in_reset(adev)) {
2891                         /* in resume phase, if fail to enable ras,
2892                          * clean up all ras fs nodes, and disable ras */
2893                         goto cleanup;
2894                 } else
2895                         return r;
2896         }
2897
2898         /* check for errors on warm reset edc persisant supported ASIC */
2899         amdgpu_persistent_edc_harvesting(adev, ras_block);
2900
2901         /* in resume phase, no need to create ras fs node */
2902         if (adev->in_suspend || amdgpu_in_reset(adev))
2903                 return 0;
2904
2905         ras_obj = container_of(ras_block, struct amdgpu_ras_block_object, ras_comm);
2906         if (ras_obj->ras_cb || (ras_obj->hw_ops &&
2907             (ras_obj->hw_ops->query_poison_status ||
2908             ras_obj->hw_ops->handle_poison_consumption))) {
2909                 r = amdgpu_ras_interrupt_add_handler(adev, ras_block);
2910                 if (r)
2911                         goto cleanup;
2912         }
2913
2914         if (ras_obj->hw_ops &&
2915             (ras_obj->hw_ops->query_ras_error_count ||
2916              ras_obj->hw_ops->query_ras_error_status)) {
2917                 r = amdgpu_ras_sysfs_create(adev, ras_block);
2918                 if (r)
2919                         goto interrupt;
2920
2921                 /* Those are the cached values at init.
2922                  */
2923                 query_info = kzalloc(sizeof(*query_info), GFP_KERNEL);
2924                 if (!query_info)
2925                         return -ENOMEM;
2926                 memcpy(&query_info->head, ras_block, sizeof(struct ras_common_if));
2927
2928                 if (amdgpu_ras_query_error_count(adev, &ce_count, &ue_count, query_info) == 0) {
2929                         atomic_set(&con->ras_ce_count, ce_count);
2930                         atomic_set(&con->ras_ue_count, ue_count);
2931                 }
2932
2933                 kfree(query_info);
2934         }
2935
2936         return 0;
2937
2938 interrupt:
2939         if (ras_obj->ras_cb)
2940                 amdgpu_ras_interrupt_remove_handler(adev, ras_block);
2941 cleanup:
2942         amdgpu_ras_feature_enable(adev, ras_block, 0);
2943         return r;
2944 }
2945
2946 static int amdgpu_ras_block_late_init_default(struct amdgpu_device *adev,
2947                          struct ras_common_if *ras_block)
2948 {
2949         return amdgpu_ras_block_late_init(adev, ras_block);
2950 }
2951
2952 /* helper function to remove ras fs node and interrupt handler */
2953 void amdgpu_ras_block_late_fini(struct amdgpu_device *adev,
2954                           struct ras_common_if *ras_block)
2955 {
2956         struct amdgpu_ras_block_object *ras_obj;
2957         if (!ras_block)
2958                 return;
2959
2960         amdgpu_ras_sysfs_remove(adev, ras_block);
2961
2962         ras_obj = container_of(ras_block, struct amdgpu_ras_block_object, ras_comm);
2963         if (ras_obj->ras_cb)
2964                 amdgpu_ras_interrupt_remove_handler(adev, ras_block);
2965 }
2966
2967 static void amdgpu_ras_block_late_fini_default(struct amdgpu_device *adev,
2968                           struct ras_common_if *ras_block)
2969 {
2970         return amdgpu_ras_block_late_fini(adev, ras_block);
2971 }
2972
2973 /* do some init work after IP late init as dependence.
2974  * and it runs in resume/gpu reset/booting up cases.
2975  */
2976 void amdgpu_ras_resume(struct amdgpu_device *adev)
2977 {
2978         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
2979         struct ras_manager *obj, *tmp;
2980
2981         if (!adev->ras_enabled || !con) {
2982                 /* clean ras context for VEGA20 Gaming after send ras disable cmd */
2983                 amdgpu_release_ras_context(adev);
2984
2985                 return;
2986         }
2987
2988         if (con->flags & AMDGPU_RAS_FLAG_INIT_BY_VBIOS) {
2989                 /* Set up all other IPs which are not implemented. There is a
2990                  * tricky thing that IP's actual ras error type should be
2991                  * MULTI_UNCORRECTABLE, but as driver does not handle it, so
2992                  * ERROR_NONE make sense anyway.
2993                  */
2994                 amdgpu_ras_enable_all_features(adev, 1);
2995
2996                 /* We enable ras on all hw_supported block, but as boot
2997                  * parameter might disable some of them and one or more IP has
2998                  * not implemented yet. So we disable them on behalf.
2999                  */
3000                 list_for_each_entry_safe(obj, tmp, &con->head, node) {
3001                         if (!amdgpu_ras_is_supported(adev, obj->head.block)) {
3002                                 amdgpu_ras_feature_enable(adev, &obj->head, 0);
3003                                 /* there should be no any reference. */
3004                                 WARN_ON(alive_obj(obj));
3005                         }
3006                 }
3007         }
3008 }
3009
3010 void amdgpu_ras_suspend(struct amdgpu_device *adev)
3011 {
3012         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
3013
3014         if (!adev->ras_enabled || !con)
3015                 return;
3016
3017         amdgpu_ras_disable_all_features(adev, 0);
3018         /* Make sure all ras objects are disabled. */
3019         if (con->features)
3020                 amdgpu_ras_disable_all_features(adev, 1);
3021 }
3022
3023 int amdgpu_ras_late_init(struct amdgpu_device *adev)
3024 {
3025         struct amdgpu_ras_block_list *node, *tmp;
3026         struct amdgpu_ras_block_object *obj;
3027         int r;
3028
3029         /* Guest side doesn't need init ras feature */
3030         if (amdgpu_sriov_vf(adev))
3031                 return 0;
3032
3033         list_for_each_entry_safe(node, tmp, &adev->ras_list, node) {
3034                 if (!node->ras_obj) {
3035                         dev_warn(adev->dev, "Warning: abnormal ras list node.\n");
3036                         continue;
3037                 }
3038
3039                 obj = node->ras_obj;
3040                 if (obj->ras_late_init) {
3041                         r = obj->ras_late_init(adev, &obj->ras_comm);
3042                         if (r) {
3043                                 dev_err(adev->dev, "%s failed to execute ras_late_init! ret:%d\n",
3044                                         obj->ras_comm.name, r);
3045                                 return r;
3046                         }
3047                 } else
3048                         amdgpu_ras_block_late_init_default(adev, &obj->ras_comm);
3049         }
3050
3051         return 0;
3052 }
3053
3054 /* do some fini work before IP fini as dependence */
3055 int amdgpu_ras_pre_fini(struct amdgpu_device *adev)
3056 {
3057         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
3058
3059         if (!adev->ras_enabled || !con)
3060                 return 0;
3061
3062
3063         /* Need disable ras on all IPs here before ip [hw/sw]fini */
3064         if (con->features)
3065                 amdgpu_ras_disable_all_features(adev, 0);
3066         amdgpu_ras_recovery_fini(adev);
3067         return 0;
3068 }
3069
3070 int amdgpu_ras_fini(struct amdgpu_device *adev)
3071 {
3072         struct amdgpu_ras_block_list *ras_node, *tmp;
3073         struct amdgpu_ras_block_object *obj = NULL;
3074         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
3075
3076         if (!adev->ras_enabled || !con)
3077                 return 0;
3078
3079         list_for_each_entry_safe(ras_node, tmp, &adev->ras_list, node) {
3080                 if (ras_node->ras_obj) {
3081                         obj = ras_node->ras_obj;
3082                         if (amdgpu_ras_is_supported(adev, obj->ras_comm.block) &&
3083                             obj->ras_fini)
3084                                 obj->ras_fini(adev, &obj->ras_comm);
3085                         else
3086                                 amdgpu_ras_block_late_fini_default(adev, &obj->ras_comm);
3087                 }
3088
3089                 /* Clear ras blocks from ras_list and free ras block list node */
3090                 list_del(&ras_node->node);
3091                 kfree(ras_node);
3092         }
3093
3094         amdgpu_ras_fs_fini(adev);
3095         amdgpu_ras_interrupt_remove_all(adev);
3096
3097         WARN(con->features, "Feature mask is not cleared");
3098
3099         if (con->features)
3100                 amdgpu_ras_disable_all_features(adev, 1);
3101
3102         cancel_delayed_work_sync(&con->ras_counte_delay_work);
3103
3104         amdgpu_ras_set_context(adev, NULL);
3105         kfree(con);
3106
3107         return 0;
3108 }
3109
3110 void amdgpu_ras_global_ras_isr(struct amdgpu_device *adev)
3111 {
3112         if (atomic_cmpxchg(&amdgpu_ras_in_intr, 0, 1) == 0) {
3113                 struct amdgpu_ras *ras = amdgpu_ras_get_context(adev);
3114
3115                 dev_info(adev->dev, "uncorrectable hardware error"
3116                         "(ERREVENT_ATHUB_INTERRUPT) detected!\n");
3117
3118                 ras->gpu_reset_flags |= AMDGPU_RAS_GPU_RESET_MODE1_RESET;
3119                 amdgpu_ras_reset_gpu(adev);
3120         }
3121 }
3122
3123 bool amdgpu_ras_need_emergency_restart(struct amdgpu_device *adev)
3124 {
3125         if (adev->asic_type == CHIP_VEGA20 &&
3126             adev->pm.fw_version <= 0x283400) {
3127                 return !(amdgpu_asic_reset_method(adev) == AMD_RESET_METHOD_BACO) &&
3128                                 amdgpu_ras_intr_triggered();
3129         }
3130
3131         return false;
3132 }
3133
3134 void amdgpu_release_ras_context(struct amdgpu_device *adev)
3135 {
3136         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
3137
3138         if (!con)
3139                 return;
3140
3141         if (!adev->ras_enabled && con->features & BIT(AMDGPU_RAS_BLOCK__GFX)) {
3142                 con->features &= ~BIT(AMDGPU_RAS_BLOCK__GFX);
3143                 amdgpu_ras_set_context(adev, NULL);
3144                 kfree(con);
3145         }
3146 }
3147
3148 #ifdef CONFIG_X86_MCE_AMD
3149 static struct amdgpu_device *find_adev(uint32_t node_id)
3150 {
3151         int i;
3152         struct amdgpu_device *adev = NULL;
3153
3154         for (i = 0; i < mce_adev_list.num_gpu; i++) {
3155                 adev = mce_adev_list.devs[i];
3156
3157                 if (adev && adev->gmc.xgmi.connected_to_cpu &&
3158                     adev->gmc.xgmi.physical_node_id == node_id)
3159                         break;
3160                 adev = NULL;
3161         }
3162
3163         return adev;
3164 }
3165
3166 #define GET_MCA_IPID_GPUID(m)   (((m) >> 44) & 0xF)
3167 #define GET_UMC_INST(m)         (((m) >> 21) & 0x7)
3168 #define GET_CHAN_INDEX(m)       ((((m) >> 12) & 0x3) | (((m) >> 18) & 0x4))
3169 #define GPU_ID_OFFSET           8
3170
3171 static int amdgpu_bad_page_notifier(struct notifier_block *nb,
3172                                     unsigned long val, void *data)
3173 {
3174         struct mce *m = (struct mce *)data;
3175         struct amdgpu_device *adev = NULL;
3176         uint32_t gpu_id = 0;
3177         uint32_t umc_inst = 0, ch_inst = 0;
3178
3179         /*
3180          * If the error was generated in UMC_V2, which belongs to GPU UMCs,
3181          * and error occurred in DramECC (Extended error code = 0) then only
3182          * process the error, else bail out.
3183          */
3184         if (!m || !((smca_get_bank_type(m->extcpu, m->bank) == SMCA_UMC_V2) &&
3185                     (XEC(m->status, 0x3f) == 0x0)))
3186                 return NOTIFY_DONE;
3187
3188         /*
3189          * If it is correctable error, return.
3190          */
3191         if (mce_is_correctable(m))
3192                 return NOTIFY_OK;
3193
3194         /*
3195          * GPU Id is offset by GPU_ID_OFFSET in MCA_IPID_UMC register.
3196          */
3197         gpu_id = GET_MCA_IPID_GPUID(m->ipid) - GPU_ID_OFFSET;
3198
3199         adev = find_adev(gpu_id);
3200         if (!adev) {
3201                 DRM_WARN("%s: Unable to find adev for gpu_id: %d\n", __func__,
3202                                                                 gpu_id);
3203                 return NOTIFY_DONE;
3204         }
3205
3206         /*
3207          * If it is uncorrectable error, then find out UMC instance and
3208          * channel index.
3209          */
3210         umc_inst = GET_UMC_INST(m->ipid);
3211         ch_inst = GET_CHAN_INDEX(m->ipid);
3212
3213         dev_info(adev->dev, "Uncorrectable error detected in UMC inst: %d, chan_idx: %d",
3214                              umc_inst, ch_inst);
3215
3216         if (!amdgpu_umc_page_retirement_mca(adev, m->addr, ch_inst, umc_inst))
3217                 return NOTIFY_OK;
3218         else
3219                 return NOTIFY_DONE;
3220 }
3221
3222 static struct notifier_block amdgpu_bad_page_nb = {
3223         .notifier_call  = amdgpu_bad_page_notifier,
3224         .priority       = MCE_PRIO_UC,
3225 };
3226
3227 static void amdgpu_register_bad_pages_mca_notifier(struct amdgpu_device *adev)
3228 {
3229         /*
3230          * Add the adev to the mce_adev_list.
3231          * During mode2 reset, amdgpu device is temporarily
3232          * removed from the mgpu_info list which can cause
3233          * page retirement to fail.
3234          * Use this list instead of mgpu_info to find the amdgpu
3235          * device on which the UMC error was reported.
3236          */
3237         mce_adev_list.devs[mce_adev_list.num_gpu++] = adev;
3238
3239         /*
3240          * Register the x86 notifier only once
3241          * with MCE subsystem.
3242          */
3243         if (notifier_registered == false) {
3244                 mce_register_decode_chain(&amdgpu_bad_page_nb);
3245                 notifier_registered = true;
3246         }
3247 }
3248 #endif
3249
3250 struct amdgpu_ras *amdgpu_ras_get_context(struct amdgpu_device *adev)
3251 {
3252         if (!adev)
3253                 return NULL;
3254
3255         return adev->psp.ras_context.ras;
3256 }
3257
3258 int amdgpu_ras_set_context(struct amdgpu_device *adev, struct amdgpu_ras *ras_con)
3259 {
3260         if (!adev)
3261                 return -EINVAL;
3262
3263         adev->psp.ras_context.ras = ras_con;
3264         return 0;
3265 }
3266
3267 /* check if ras is supported on block, say, sdma, gfx */
3268 int amdgpu_ras_is_supported(struct amdgpu_device *adev,
3269                 unsigned int block)
3270 {
3271         int ret = 0;
3272         struct amdgpu_ras *ras = amdgpu_ras_get_context(adev);
3273
3274         if (block >= AMDGPU_RAS_BLOCK_COUNT)
3275                 return 0;
3276
3277         ret = ras && (adev->ras_enabled & (1 << block));
3278
3279         /* For the special asic with mem ecc enabled but sram ecc
3280          * not enabled, even if the ras block is not supported on
3281          * .ras_enabled, if the asic supports poison mode and the
3282          * ras block has ras configuration, it can be considered
3283          * that the ras block supports ras function.
3284          */
3285         if (!ret &&
3286             (block == AMDGPU_RAS_BLOCK__GFX ||
3287              block == AMDGPU_RAS_BLOCK__SDMA ||
3288              block == AMDGPU_RAS_BLOCK__VCN ||
3289              block == AMDGPU_RAS_BLOCK__JPEG) &&
3290             amdgpu_ras_is_poison_mode_supported(adev) &&
3291             amdgpu_ras_get_ras_block(adev, block, 0))
3292                 ret = 1;
3293
3294         return ret;
3295 }
3296
3297 int amdgpu_ras_reset_gpu(struct amdgpu_device *adev)
3298 {
3299         struct amdgpu_ras *ras = amdgpu_ras_get_context(adev);
3300
3301         if (atomic_cmpxchg(&ras->in_recovery, 0, 1) == 0)
3302                 amdgpu_reset_domain_schedule(ras->adev->reset_domain, &ras->recovery_work);
3303         return 0;
3304 }
3305
3306
3307 /* Register each ip ras block into amdgpu ras */
3308 int amdgpu_ras_register_ras_block(struct amdgpu_device *adev,
3309                 struct amdgpu_ras_block_object *ras_block_obj)
3310 {
3311         struct amdgpu_ras_block_list *ras_node;
3312         if (!adev || !ras_block_obj)
3313                 return -EINVAL;
3314
3315         ras_node = kzalloc(sizeof(*ras_node), GFP_KERNEL);
3316         if (!ras_node)
3317                 return -ENOMEM;
3318
3319         INIT_LIST_HEAD(&ras_node->node);
3320         ras_node->ras_obj = ras_block_obj;
3321         list_add_tail(&ras_node->node, &adev->ras_list);
3322
3323         return 0;
3324 }
3325
3326 void amdgpu_ras_get_error_type_name(uint32_t err_type, char *err_type_name)
3327 {
3328         if (!err_type_name)
3329                 return;
3330
3331         switch (err_type) {
3332         case AMDGPU_RAS_ERROR__SINGLE_CORRECTABLE:
3333                 sprintf(err_type_name, "correctable");
3334                 break;
3335         case AMDGPU_RAS_ERROR__MULTI_UNCORRECTABLE:
3336                 sprintf(err_type_name, "uncorrectable");
3337                 break;
3338         default:
3339                 sprintf(err_type_name, "unknown");
3340                 break;
3341         }
3342 }
3343
3344 bool amdgpu_ras_inst_get_memory_id_field(struct amdgpu_device *adev,
3345                                          const struct amdgpu_ras_err_status_reg_entry *reg_entry,
3346                                          uint32_t instance,
3347                                          uint32_t *memory_id)
3348 {
3349         uint32_t err_status_lo_data, err_status_lo_offset;
3350
3351         if (!reg_entry)
3352                 return false;
3353
3354         err_status_lo_offset =
3355                 AMDGPU_RAS_REG_ENTRY_OFFSET(reg_entry->hwip, instance,
3356                                             reg_entry->seg_lo, reg_entry->reg_lo);
3357         err_status_lo_data = RREG32(err_status_lo_offset);
3358
3359         if ((reg_entry->flags & AMDGPU_RAS_ERR_STATUS_VALID) &&
3360             !REG_GET_FIELD(err_status_lo_data, ERR_STATUS_LO, ERR_STATUS_VALID_FLAG))
3361                 return false;
3362
3363         *memory_id = REG_GET_FIELD(err_status_lo_data, ERR_STATUS_LO, MEMORY_ID);
3364
3365         return true;
3366 }
3367
3368 bool amdgpu_ras_inst_get_err_cnt_field(struct amdgpu_device *adev,
3369                                        const struct amdgpu_ras_err_status_reg_entry *reg_entry,
3370                                        uint32_t instance,
3371                                        unsigned long *err_cnt)
3372 {
3373         uint32_t err_status_hi_data, err_status_hi_offset;
3374
3375         if (!reg_entry)
3376                 return false;
3377
3378         err_status_hi_offset =
3379                 AMDGPU_RAS_REG_ENTRY_OFFSET(reg_entry->hwip, instance,
3380                                             reg_entry->seg_hi, reg_entry->reg_hi);
3381         err_status_hi_data = RREG32(err_status_hi_offset);
3382
3383         if ((reg_entry->flags & AMDGPU_RAS_ERR_INFO_VALID) &&
3384             !REG_GET_FIELD(err_status_hi_data, ERR_STATUS_HI, ERR_INFO_VALID_FLAG))
3385                 /* keep the check here in case we need to refer to the result later */
3386                 dev_dbg(adev->dev, "Invalid err_info field\n");
3387
3388         /* read err count */
3389         *err_cnt = REG_GET_FIELD(err_status_hi_data, ERR_STATUS, ERR_CNT);
3390
3391         return true;
3392 }
3393
3394 void amdgpu_ras_inst_query_ras_error_count(struct amdgpu_device *adev,
3395                                            const struct amdgpu_ras_err_status_reg_entry *reg_list,
3396                                            uint32_t reg_list_size,
3397                                            const struct amdgpu_ras_memory_id_entry *mem_list,
3398                                            uint32_t mem_list_size,
3399                                            uint32_t instance,
3400                                            uint32_t err_type,
3401                                            unsigned long *err_count)
3402 {
3403         uint32_t memory_id;
3404         unsigned long err_cnt;
3405         char err_type_name[16];
3406         uint32_t i, j;
3407
3408         for (i = 0; i < reg_list_size; i++) {
3409                 /* query memory_id from err_status_lo */
3410                 if (!amdgpu_ras_inst_get_memory_id_field(adev, &reg_list[i],
3411                                                          instance, &memory_id))
3412                         continue;
3413
3414                 /* query err_cnt from err_status_hi */
3415                 if (!amdgpu_ras_inst_get_err_cnt_field(adev, &reg_list[i],
3416                                                        instance, &err_cnt) ||
3417                     !err_cnt)
3418                         continue;
3419
3420                 *err_count += err_cnt;
3421
3422                 /* log the errors */
3423                 amdgpu_ras_get_error_type_name(err_type, err_type_name);
3424                 if (!mem_list) {
3425                         /* memory_list is not supported */
3426                         dev_info(adev->dev,
3427                                  "%ld %s hardware errors detected in %s, instance: %d, memory_id: %d\n",
3428                                  err_cnt, err_type_name,
3429                                  reg_list[i].block_name,
3430                                  instance, memory_id);
3431                 } else {
3432                         for (j = 0; j < mem_list_size; j++) {
3433                                 if (memory_id == mem_list[j].memory_id) {
3434                                         dev_info(adev->dev,
3435                                                  "%ld %s hardware errors detected in %s, instance: %d, memory block: %s\n",
3436                                                  err_cnt, err_type_name,
3437                                                  reg_list[i].block_name,
3438                                                  instance, mem_list[j].name);
3439                                         break;
3440                                 }
3441                         }
3442                 }
3443         }
3444 }
3445
3446 void amdgpu_ras_inst_reset_ras_error_count(struct amdgpu_device *adev,
3447                                            const struct amdgpu_ras_err_status_reg_entry *reg_list,
3448                                            uint32_t reg_list_size,
3449                                            uint32_t instance)
3450 {
3451         uint32_t err_status_lo_offset, err_status_hi_offset;
3452         uint32_t i;
3453
3454         for (i = 0; i < reg_list_size; i++) {
3455                 err_status_lo_offset =
3456                         AMDGPU_RAS_REG_ENTRY_OFFSET(reg_list[i].hwip, instance,
3457                                                     reg_list[i].seg_lo, reg_list[i].reg_lo);
3458                 err_status_hi_offset =
3459                         AMDGPU_RAS_REG_ENTRY_OFFSET(reg_list[i].hwip, instance,
3460                                                     reg_list[i].seg_hi, reg_list[i].reg_hi);
3461                 WREG32(err_status_lo_offset, 0);
3462                 WREG32(err_status_hi_offset, 0);
3463         }
3464 }
3465
3466 int amdgpu_ras_error_data_init(struct ras_err_data *err_data)
3467 {
3468         memset(err_data, 0, sizeof(*err_data));
3469
3470         INIT_LIST_HEAD(&err_data->err_node_list);
3471
3472         return 0;
3473 }
3474
3475 static void amdgpu_ras_error_node_release(struct ras_err_node *err_node)
3476 {
3477         if (!err_node)
3478                 return;
3479
3480         list_del(&err_node->node);
3481         kvfree(err_node);
3482 }
3483
3484 void amdgpu_ras_error_data_fini(struct ras_err_data *err_data)
3485 {
3486         struct ras_err_node *err_node, *tmp;
3487
3488         list_for_each_entry_safe(err_node, tmp, &err_data->err_node_list, node) {
3489                 amdgpu_ras_error_node_release(err_node);
3490                 list_del(&err_node->node);
3491         }
3492 }
3493
3494 static struct ras_err_node *amdgpu_ras_error_find_node_by_id(struct ras_err_data *err_data,
3495                                                              struct amdgpu_smuio_mcm_config_info *mcm_info)
3496 {
3497         struct ras_err_node *err_node;
3498         struct amdgpu_smuio_mcm_config_info *ref_id;
3499
3500         if (!err_data || !mcm_info)
3501                 return NULL;
3502
3503         for_each_ras_error(err_node, err_data) {
3504                 ref_id = &err_node->err_info.mcm_info;
3505                 if ((mcm_info->socket_id >= 0 && mcm_info->socket_id != ref_id->socket_id) ||
3506                     (mcm_info->die_id >= 0 && mcm_info->die_id != ref_id->die_id))
3507                         continue;
3508
3509                 return err_node;
3510         }
3511
3512         return NULL;
3513 }
3514
3515 static struct ras_err_node *amdgpu_ras_error_node_new(void)
3516 {
3517         struct ras_err_node *err_node;
3518
3519         err_node = kvzalloc(sizeof(*err_node), GFP_KERNEL);
3520         if (!err_node)
3521                 return NULL;
3522
3523         INIT_LIST_HEAD(&err_node->node);
3524
3525         return err_node;
3526 }
3527
3528 static struct ras_err_info *amdgpu_ras_error_get_info(struct ras_err_data *err_data,
3529                                                       struct amdgpu_smuio_mcm_config_info *mcm_info)
3530 {
3531         struct ras_err_node *err_node;
3532
3533         err_node = amdgpu_ras_error_find_node_by_id(err_data, mcm_info);
3534         if (err_node)
3535                 return &err_node->err_info;
3536
3537         err_node = amdgpu_ras_error_node_new();
3538         if (!err_node)
3539                 return NULL;
3540
3541         memcpy(&err_node->err_info.mcm_info, mcm_info, sizeof(*mcm_info));
3542
3543         err_data->err_list_count++;
3544         list_add_tail(&err_node->node, &err_data->err_node_list);
3545
3546         return &err_node->err_info;
3547 }
3548
3549 int amdgpu_ras_error_statistic_ue_count(struct ras_err_data *err_data,
3550                                         struct amdgpu_smuio_mcm_config_info *mcm_info, u64 count)
3551 {
3552         struct ras_err_info *err_info;
3553
3554         if (!err_data || !mcm_info)
3555                 return -EINVAL;
3556
3557         if (!count)
3558                 return 0;
3559
3560         err_info = amdgpu_ras_error_get_info(err_data, mcm_info);
3561         if (!err_info)
3562                 return -EINVAL;
3563
3564         err_info->ue_count += count;
3565         err_data->ue_count += count;
3566
3567         return 0;
3568 }
3569
3570 int amdgpu_ras_error_statistic_ce_count(struct ras_err_data *err_data,
3571                                         struct amdgpu_smuio_mcm_config_info *mcm_info, u64 count)
3572 {
3573         struct ras_err_info *err_info;
3574
3575         if (!err_data || !mcm_info)
3576                 return -EINVAL;
3577
3578         if (!count)
3579                 return 0;
3580
3581         err_info = amdgpu_ras_error_get_info(err_data, mcm_info);
3582         if (!err_info)
3583                 return -EINVAL;
3584
3585         err_info->ce_count += count;
3586         err_data->ce_count += count;
3587
3588         return 0;
3589 }