drivers/gpu/drm/meson/meson_venc.c

   1 /*
   2  * Copyright (C) 2016 BayLibre, SAS
   3  * Author: Neil Armstrong <[email protected]>
   4  * Copyright (C) 2015 Amlogic, Inc. All rights reserved.
   5  *
   6  * This program is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU General Public License as
   8  * published by the Free Software Foundation; either version 2 of the
   9  * License, or (at your option) any later version.
  10  *
  11  * This program is distributed in the hope that it will be useful, but
  12  * WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  14  * General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU General Public License
  17  * along with this program; if not, see <http://www.gnu.org/licenses/>.
  18  */
  19
  20 #include <linux/kernel.h>
  21 #include <linux/module.h>
  22 #include <drm/drmP.h>
  23 #include "meson_drv.h"
  24 #include "meson_venc.h"
  25 #include "meson_vpp.h"
  26 #include "meson_vclk.h"
  27 #include "meson_registers.h"
  28
  29 /**
  30  * DOC: Video Encoder
  31  *
  32  * VENC Handle the pixels encoding to the output formats.
  33  * We handle the following encodings :
  34  *
  35  * - CVBS Encoding via the ENCI encoder and VDAC digital to analog converter
  36  * - TMDS/HDMI Encoding via ENCI_DIV and ENCP
  37  * - Setup of more clock rates for HDMI modes
  38  *
  39  * What is missing :
  40  *
  41  * - LCD Panel encoding via ENCL
  42  * - TV Panel encoding via ENCT
  43  *
  44  * VENC paths :
  45  *
  46  * .. code::
  47  *
  48  *          _____   _____   ____________________
  49  *   vd1---|     |-|     | | VENC     /---------|----VDAC
  50  *   vd2---| VIU |-| VPP |-|-----ENCI/-ENCI_DVI-|-|
  51  *   osd1--|     |-|     | | \                  | X--HDMI-TX
  52  *   osd2--|_____|-|_____| |  |\-ENCP--ENCP_DVI-|-|
  53  *                         |  |                 |
  54  *                         |  \--ENCL-----------|----LVDS
  55  *                         |____________________|
  56  *
  57  * The ENCI is designed for PAl or NTSC encoding and can go through the VDAC
  58  * directly for CVBS encoding or through the ENCI_DVI encoder for HDMI.
  59  * The ENCP is designed for Progressive encoding but can also generate
  60  * 1080i interlaced pixels, and was initialy desined to encode pixels for
  61  * VDAC to output RGB ou YUV analog outputs.
  62  * It's output is only used through the ENCP_DVI encoder for HDMI.
  63  * The ENCL LVDS encoder is not implemented.
  64  *
  65  * The ENCI and ENCP encoders needs specially defined parameters for each
  66  * supported mode and thus cannot be determined from standard video timings.
  67  *
  68  * The ENCI end ENCP DVI encoders are more generic and can generate any timings
  69  * from the pixel data generated by ENCI or ENCP, so can use the standard video
  70  * timings are source for HW parameters.
  71  */
  72
  73 /* HHI Registers */
  74 #define HHI_GCLK_MPEG2          0x148 /* 0x52 offset in data sheet */
  75 #define HHI_VDAC_CNTL0          0x2F4 /* 0xbd offset in data sheet */
  76 #define HHI_VDAC_CNTL1          0x2F8 /* 0xbe offset in data sheet */
  77 #define HHI_HDMI_PHY_CNTL0      0x3a0 /* 0xe8 offset in data sheet */
  78
  79 struct meson_cvbs_enci_mode meson_cvbs_enci_pal = {
  80         .mode_tag = MESON_VENC_MODE_CVBS_PAL,
  81         .hso_begin = 3,
  82         .hso_end = 129,
  83         .vso_even = 3,
  84         .vso_odd = 260,
  85         .macv_max_amp = 7,
  86         .video_prog_mode = 0xff,
  87         .video_mode = 0x13,
  88         .sch_adjust = 0x28,
  89         .yc_delay = 0x343,
  90         .pixel_start = 251,
  91         .pixel_end = 1691,
  92         .top_field_line_start = 22,
  93         .top_field_line_end = 310,
  94         .bottom_field_line_start = 23,
  95         .bottom_field_line_end = 311,
  96         .video_saturation = 9,
  97         .video_contrast = 0,
  98         .video_brightness = 0,
  99         .video_hue = 0,
 100         .analog_sync_adj = 0x8080,
 101 };
 102
 103 struct meson_cvbs_enci_mode meson_cvbs_enci_ntsc = {
 104         .mode_tag = MESON_VENC_MODE_CVBS_NTSC,
 105         .hso_begin = 5,
 106         .hso_end = 129,
 107         .vso_even = 3,
 108         .vso_odd = 260,
 109         .macv_max_amp = 0xb,
 110         .video_prog_mode = 0xf0,
 111         .video_mode = 0x8,
 112         .sch_adjust = 0x20,
 113         .yc_delay = 0x333,
 114         .pixel_start = 227,
 115         .pixel_end = 1667,
 116         .top_field_line_start = 18,
 117         .top_field_line_end = 258,
 118         .bottom_field_line_start = 19,
 119         .bottom_field_line_end = 259,
 120         .video_saturation = 18,
 121         .video_contrast = 3,
 122         .video_brightness = 0,
 123         .video_hue = 0,
 124         .analog_sync_adj = 0x9c00,
 125 };
 126
 127 union meson_hdmi_venc_mode {
 128         struct {
 129                 unsigned int mode_tag;
 130                 unsigned int hso_begin;
 131                 unsigned int hso_end;
 132                 unsigned int vso_even;
 133                 unsigned int vso_odd;
 134                 unsigned int macv_max_amp;
 135                 unsigned int video_prog_mode;
 136                 unsigned int video_mode;
 137                 unsigned int sch_adjust;
 138                 unsigned int yc_delay;
 139                 unsigned int pixel_start;
 140                 unsigned int pixel_end;
 141                 unsigned int top_field_line_start;
 142                 unsigned int top_field_line_end;
 143                 unsigned int bottom_field_line_start;
 144                 unsigned int bottom_field_line_end;
 145         } enci;
 146         struct {
 147                 unsigned int dvi_settings;
 148                 unsigned int video_mode;
 149                 unsigned int video_mode_adv;
 150                 unsigned int video_prog_mode;
 151                 bool video_prog_mode_present;
 152                 unsigned int video_sync_mode;
 153                 bool video_sync_mode_present;
 154                 unsigned int video_yc_dly;
 155                 bool video_yc_dly_present;
 156                 unsigned int video_rgb_ctrl;
 157                 bool video_rgb_ctrl_present;
 158                 unsigned int video_filt_ctrl;
 159                 bool video_filt_ctrl_present;
 160                 unsigned int video_ofld_voav_ofst;
 161                 bool video_ofld_voav_ofst_present;
 162                 unsigned int yfp1_htime;
 163                 unsigned int yfp2_htime;
 164                 unsigned int max_pxcnt;
 165                 unsigned int hspuls_begin;
 166                 unsigned int hspuls_end;
 167                 unsigned int hspuls_switch;
 168                 unsigned int vspuls_begin;
 169                 unsigned int vspuls_end;
 170                 unsigned int vspuls_bline;
 171                 unsigned int vspuls_eline;
 172                 unsigned int eqpuls_begin;
 173                 bool eqpuls_begin_present;
 174                 unsigned int eqpuls_end;
 175                 bool eqpuls_end_present;
 176                 unsigned int eqpuls_bline;
 177                 bool eqpuls_bline_present;
 178                 unsigned int eqpuls_eline;
 179                 bool eqpuls_eline_present;
 180                 unsigned int havon_begin;
 181                 unsigned int havon_end;
 182                 unsigned int vavon_bline;
 183                 unsigned int vavon_eline;
 184                 unsigned int hso_begin;
 185                 unsigned int hso_end;
 186                 unsigned int vso_begin;
 187                 unsigned int vso_end;
 188                 unsigned int vso_bline;
 189                 unsigned int vso_eline;
 190                 bool vso_eline_present;
 191                 unsigned int sy_val;
 192                 bool sy_val_present;
 193                 unsigned int sy2_val;
 194                 bool sy2_val_present;
 195                 unsigned int max_lncnt;
 196         } encp;
 197 };
 198
 199 union meson_hdmi_venc_mode meson_hdmi_enci_mode_480i = {
 200         .enci = {
 201                 .hso_begin = 5,
 202                 .hso_end = 129,
 203                 .vso_even = 3,
 204                 .vso_odd = 260,
 205                 .macv_max_amp = 0x810b,
 206                 .video_prog_mode = 0xf0,
 207                 .video_mode = 0x8,
 208                 .sch_adjust = 0x20,
 209                 .yc_delay = 0,
 210                 .pixel_start = 227,
 211                 .pixel_end = 1667,
 212                 .top_field_line_start = 18,
 213                 .top_field_line_end = 258,
 214                 .bottom_field_line_start = 19,
 215                 .bottom_field_line_end = 259,
 216         },
 217 };
 218
 219 union meson_hdmi_venc_mode meson_hdmi_enci_mode_576i = {
 220         .enci = {
 221                 .hso_begin = 3,
 222                 .hso_end = 129,
 223                 .vso_even = 3,
 224                 .vso_odd = 260,
 225                 .macv_max_amp = 8107,
 226                 .video_prog_mode = 0xff,
 227                 .video_mode = 0x13,
 228                 .sch_adjust = 0x28,
 229                 .yc_delay = 0x333,
 230                 .pixel_start = 251,
 231                 .pixel_end = 1691,
 232                 .top_field_line_start = 22,
 233                 .top_field_line_end = 310,
 234                 .bottom_field_line_start = 23,
 235                 .bottom_field_line_end = 311,
 236         },
 237 };
 238
 239 union meson_hdmi_venc_mode meson_hdmi_encp_mode_480p = {
 240         .encp = {
 241                 .dvi_settings = 0x21,
 242                 .video_mode = 0x4000,
 243                 .video_mode_adv = 0x9,
 244                 .video_prog_mode = 0,
 245                 .video_prog_mode_present = true,
 246                 .video_sync_mode = 7,
 247                 .video_sync_mode_present = true,
 248                 /* video_yc_dly */
 249                 /* video_rgb_ctrl */
 250                 .video_filt_ctrl = 0x2052,
 251                 .video_filt_ctrl_present = true,
 252                 /* video_ofld_voav_ofst */
 253                 .yfp1_htime = 244,
 254                 .yfp2_htime = 1630,
 255                 .max_pxcnt = 1715,
 256                 .hspuls_begin = 0x22,
 257                 .hspuls_end = 0xa0,
 258                 .hspuls_switch = 88,
 259                 .vspuls_begin = 0,
 260                 .vspuls_end = 1589,
 261                 .vspuls_bline = 0,
 262                 .vspuls_eline = 5,
 263                 .havon_begin = 249,
 264                 .havon_end = 1689,
 265                 .vavon_bline = 42,
 266                 .vavon_eline = 521,
 267                 /* eqpuls_begin */
 268                 /* eqpuls_end */
 269                 /* eqpuls_bline */
 270                 /* eqpuls_eline */
 271                 .hso_begin = 3,
 272                 .hso_end = 5,
 273                 .vso_begin = 3,
 274                 .vso_end = 5,
 275                 .vso_bline = 0,
 276                 /* vso_eline */
 277                 .sy_val = 8,
 278                 .sy_val_present = true,
 279                 .sy2_val = 0x1d8,
 280                 .sy2_val_present = true,
 281                 .max_lncnt = 524,
 282         },
 283 };
 284
 285 union meson_hdmi_venc_mode meson_hdmi_encp_mode_576p = {
 286         .encp = {
 287                 .dvi_settings = 0x21,
 288                 .video_mode = 0x4000,
 289                 .video_mode_adv = 0x9,
 290                 .video_prog_mode = 0,
 291                 .video_prog_mode_present = true,
 292                 .video_sync_mode = 7,
 293                 .video_sync_mode_present = true,
 294                 /* video_yc_dly */
 295                 /* video_rgb_ctrl */
 296                 .video_filt_ctrl = 0x52,
 297                 .video_filt_ctrl_present = true,
 298                 /* video_ofld_voav_ofst */
 299                 .yfp1_htime = 235,
 300                 .yfp2_htime = 1674,
 301                 .max_pxcnt = 1727,
 302                 .hspuls_begin = 0,
 303                 .hspuls_end = 0x80,
 304                 .hspuls_switch = 88,
 305                 .vspuls_begin = 0,
 306                 .vspuls_end = 1599,
 307                 .vspuls_bline = 0,
 308                 .vspuls_eline = 4,
 309                 .havon_begin = 235,
 310                 .havon_end = 1674,
 311                 .vavon_bline = 44,
 312                 .vavon_eline = 619,
 313                 /* eqpuls_begin */
 314                 /* eqpuls_end */
 315                 /* eqpuls_bline */
 316                 /* eqpuls_eline */
 317                 .hso_begin = 0x80,
 318                 .hso_end = 0,
 319                 .vso_begin = 0,
 320                 .vso_end = 5,
 321                 .vso_bline = 0,
 322                 /* vso_eline */
 323                 .sy_val = 8,
 324                 .sy_val_present = true,
 325                 .sy2_val = 0x1d8,
 326                 .sy2_val_present = true,
 327                 .max_lncnt = 624,
 328         },
 329 };
 330
 331 union meson_hdmi_venc_mode meson_hdmi_encp_mode_720p60 = {
 332         .encp = {
 333                 .dvi_settings = 0x2029,
 334                 .video_mode = 0x4040,
 335                 .video_mode_adv = 0x19,
 336                 /* video_prog_mode */
 337                 /* video_sync_mode */
 338                 /* video_yc_dly */
 339                 /* video_rgb_ctrl */
 340                 /* video_filt_ctrl */
 341                 /* video_ofld_voav_ofst */
 342                 .yfp1_htime = 648,
 343                 .yfp2_htime = 3207,
 344                 .max_pxcnt = 3299,
 345                 .hspuls_begin = 80,
 346                 .hspuls_end = 240,
 347                 .hspuls_switch = 80,
 348                 .vspuls_begin = 688,
 349                 .vspuls_end = 3248,
 350                 .vspuls_bline = 4,
 351                 .vspuls_eline = 8,
 352                 .havon_begin = 648,
 353                 .havon_end = 3207,
 354                 .vavon_bline = 29,
 355                 .vavon_eline = 748,
 356                 /* eqpuls_begin */
 357                 /* eqpuls_end */
 358                 /* eqpuls_bline */
 359                 /* eqpuls_eline */
 360                 .hso_begin = 256,
 361                 .hso_end = 168,
 362                 .vso_begin = 168,
 363                 .vso_end = 256,
 364                 .vso_bline = 0,
 365                 .vso_eline = 5,
 366                 .vso_eline_present = true,
 367                 /* sy_val */
 368                 /* sy2_val */
 369                 .max_lncnt = 749,
 370         },
 371 };
 372
 373 union meson_hdmi_venc_mode meson_hdmi_encp_mode_720p50 = {
 374         .encp = {
 375                 .dvi_settings = 0x202d,
 376                 .video_mode = 0x4040,
 377                 .video_mode_adv = 0x19,
 378                 .video_prog_mode = 0x100,
 379                 .video_prog_mode_present = true,
 380                 .video_sync_mode = 0x407,
 381                 .video_sync_mode_present = true,
 382                 .video_yc_dly = 0,
 383                 .video_yc_dly_present = true,
 384                 /* video_rgb_ctrl */
 385                 /* video_filt_ctrl */
 386                 /* video_ofld_voav_ofst */
 387                 .yfp1_htime = 648,
 388                 .yfp2_htime = 3207,
 389                 .max_pxcnt = 3959,
 390                 .hspuls_begin = 80,
 391                 .hspuls_end = 240,
 392                 .hspuls_switch = 80,
 393                 .vspuls_begin = 688,
 394                 .vspuls_end = 3248,
 395                 .vspuls_bline = 4,
 396                 .vspuls_eline = 8,
 397                 .havon_begin = 648,
 398                 .havon_end = 3207,
 399                 .vavon_bline = 29,
 400                 .vavon_eline = 748,
 401                 /* eqpuls_begin */
 402                 /* eqpuls_end */
 403                 /* eqpuls_bline */
 404                 /* eqpuls_eline */
 405                 .hso_begin = 128,
 406                 .hso_end = 208,
 407                 .vso_begin = 128,
 408                 .vso_end = 128,
 409                 .vso_bline = 0,
 410                 .vso_eline = 5,
 411                 .vso_eline_present = true,
 412                 /* sy_val */
 413                 /* sy2_val */
 414                 .max_lncnt = 749,
 415         },
 416 };
 417
 418 union meson_hdmi_venc_mode meson_hdmi_encp_mode_1080i60 = {
 419         .encp = {
 420                 .dvi_settings = 0x2029,
 421                 .video_mode = 0x5ffc,
 422                 .video_mode_adv = 0x19,
 423                 .video_prog_mode = 0x100,
 424                 .video_prog_mode_present = true,
 425                 .video_sync_mode = 0x207,
 426                 .video_sync_mode_present = true,
 427                 /* video_yc_dly */
 428                 /* video_rgb_ctrl */
 429                 /* video_filt_ctrl */
 430                 .video_ofld_voav_ofst = 0x11,
 431                 .video_ofld_voav_ofst_present = true,
 432                 .yfp1_htime = 516,
 433                 .yfp2_htime = 4355,
 434                 .max_pxcnt = 4399,
 435                 .hspuls_begin = 88,
 436                 .hspuls_end = 264,
 437                 .hspuls_switch = 88,
 438                 .vspuls_begin = 440,
 439                 .vspuls_end = 2200,
 440                 .vspuls_bline = 0,
 441                 .vspuls_eline = 4,
 442                 .havon_begin = 516,
 443                 .havon_end = 4355,
 444                 .vavon_bline = 20,
 445                 .vavon_eline = 559,
 446                 .eqpuls_begin = 2288,
 447                 .eqpuls_begin_present = true,
 448                 .eqpuls_end = 2464,
 449                 .eqpuls_end_present = true,
 450                 .eqpuls_bline = 0,
 451                 .eqpuls_bline_present = true,
 452                 .eqpuls_eline = 4,
 453                 .eqpuls_eline_present = true,
 454                 .hso_begin = 264,
 455                 .hso_end = 176,
 456                 .vso_begin = 88,
 457                 .vso_end = 88,
 458                 .vso_bline = 0,
 459                 .vso_eline = 5,
 460                 .vso_eline_present = true,
 461                 /* sy_val */
 462                 /* sy2_val */
 463                 .max_lncnt = 1124,
 464         },
 465 };
 466
 467 union meson_hdmi_venc_mode meson_hdmi_encp_mode_1080i50 = {
 468         .encp = {
 469                 .dvi_settings = 0x202d,
 470                 .video_mode = 0x5ffc,
 471                 .video_mode_adv = 0x19,
 472                 .video_prog_mode = 0x100,
 473                 .video_prog_mode_present = true,
 474                 .video_sync_mode = 0x7,
 475                 .video_sync_mode_present = true,
 476                 /* video_yc_dly */
 477                 /* video_rgb_ctrl */
 478                 /* video_filt_ctrl */
 479                 .video_ofld_voav_ofst = 0x11,
 480                 .video_ofld_voav_ofst_present = true,
 481                 .yfp1_htime = 526,
 482                 .yfp2_htime = 4365,
 483                 .max_pxcnt = 5279,
 484                 .hspuls_begin = 88,
 485                 .hspuls_end = 264,
 486                 .hspuls_switch = 88,
 487                 .vspuls_begin = 440,
 488                 .vspuls_end = 2200,
 489                 .vspuls_bline = 0,
 490                 .vspuls_eline = 4,
 491                 .havon_begin = 526,
 492                 .havon_end = 4365,
 493                 .vavon_bline = 20,
 494                 .vavon_eline = 559,
 495                 .eqpuls_begin = 2288,
 496                 .eqpuls_begin_present = true,
 497                 .eqpuls_end = 2464,
 498                 .eqpuls_end_present = true,
 499                 .eqpuls_bline = 0,
 500                 .eqpuls_bline_present = true,
 501                 .eqpuls_eline = 4,
 502                 .eqpuls_eline_present = true,
 503                 .hso_begin = 142,
 504                 .hso_end = 230,
 505                 .vso_begin = 142,
 506                 .vso_end = 142,
 507                 .vso_bline = 0,
 508                 .vso_eline = 5,
 509                 .vso_eline_present = true,
 510                 /* sy_val */
 511                 /* sy2_val */
 512                 .max_lncnt = 1124,
 513         },
 514 };
 515
 516 union meson_hdmi_venc_mode meson_hdmi_encp_mode_1080p24 = {
 517         .encp = {
 518                 .dvi_settings = 0xd,
 519                 .video_mode = 0x4040,
 520                 .video_mode_adv = 0x18,
 521                 .video_prog_mode = 0x100,
 522                 .video_prog_mode_present = true,
 523                 .video_sync_mode = 0x7,
 524                 .video_sync_mode_present = true,
 525                 .video_yc_dly = 0,
 526                 .video_yc_dly_present = true,
 527                 .video_rgb_ctrl = 2,
 528                 .video_rgb_ctrl_present = true,
 529                 .video_filt_ctrl = 0x1052,
 530                 .video_filt_ctrl_present = true,
 531                 /* video_ofld_voav_ofst */
 532                 .yfp1_htime = 271,
 533                 .yfp2_htime = 2190,
 534                 .max_pxcnt = 2749,
 535                 .hspuls_begin = 44,
 536                 .hspuls_end = 132,
 537                 .hspuls_switch = 44,
 538                 .vspuls_begin = 220,
 539                 .vspuls_end = 2140,
 540                 .vspuls_bline = 0,
 541                 .vspuls_eline = 4,
 542                 .havon_begin = 271,
 543                 .havon_end = 2190,
 544                 .vavon_bline = 41,
 545                 .vavon_eline = 1120,
 546                 /* eqpuls_begin */
 547                 /* eqpuls_end */
 548                 .eqpuls_bline = 0,
 549                 .eqpuls_bline_present = true,
 550                 .eqpuls_eline = 4,
 551                 .eqpuls_eline_present = true,
 552                 .hso_begin = 79,
 553                 .hso_end = 123,
 554                 .vso_begin = 79,
 555                 .vso_end = 79,
 556                 .vso_bline = 0,
 557                 .vso_eline = 5,
 558                 .vso_eline_present = true,
 559                 /* sy_val */
 560                 /* sy2_val */
 561                 .max_lncnt = 1124,
 562         },
 563 };
 564
 565 union meson_hdmi_venc_mode meson_hdmi_encp_mode_1080p30 = {
 566         .encp = {
 567                 .dvi_settings = 0x1,
 568                 .video_mode = 0x4040,
 569                 .video_mode_adv = 0x18,
 570                 .video_prog_mode = 0x100,
 571                 .video_prog_mode_present = true,
 572                 /* video_sync_mode */
 573                 /* video_yc_dly */
 574                 /* video_rgb_ctrl */
 575                 .video_filt_ctrl = 0x1052,
 576                 .video_filt_ctrl_present = true,
 577                 /* video_ofld_voav_ofst */
 578                 .yfp1_htime = 140,
 579                 .yfp2_htime = 2060,
 580                 .max_pxcnt = 2199,
 581                 .hspuls_begin = 2156,
 582                 .hspuls_end = 44,
 583                 .hspuls_switch = 44,
 584                 .vspuls_begin = 140,
 585                 .vspuls_end = 2059,
 586                 .vspuls_bline = 0,
 587                 .vspuls_eline = 4,
 588                 .havon_begin = 148,
 589                 .havon_end = 2067,
 590                 .vavon_bline = 41,
 591                 .vavon_eline = 1120,
 592                 /* eqpuls_begin */
 593                 /* eqpuls_end */
 594                 /* eqpuls_bline */
 595                 /* eqpuls_eline */
 596                 .hso_begin = 44,
 597                 .hso_end = 2156,
 598                 .vso_begin = 2100,
 599                 .vso_end = 2164,
 600                 .vso_bline = 0,
 601                 .vso_eline = 5,
 602                 .vso_eline_present = true,
 603                 /* sy_val */
 604                 /* sy2_val */
 605                 .max_lncnt = 1124,
 606         },
 607 };
 608
 609 union meson_hdmi_venc_mode meson_hdmi_encp_mode_1080p50 = {
 610         .encp = {
 611                 .dvi_settings = 0xd,
 612                 .video_mode = 0x4040,
 613                 .video_mode_adv = 0x18,
 614                 .video_prog_mode = 0x100,
 615                 .video_prog_mode_present = true,
 616                 .video_sync_mode = 0x7,
 617                 .video_sync_mode_present = true,
 618                 .video_yc_dly = 0,
 619                 .video_yc_dly_present = true,
 620                 .video_rgb_ctrl = 2,
 621                 .video_rgb_ctrl_present = true,
 622                 /* video_filt_ctrl */
 623                 /* video_ofld_voav_ofst */
 624                 .yfp1_htime = 271,
 625                 .yfp2_htime = 2190,
 626                 .max_pxcnt = 2639,
 627                 .hspuls_begin = 44,
 628                 .hspuls_end = 132,
 629                 .hspuls_switch = 44,
 630                 .vspuls_begin = 220,
 631                 .vspuls_end = 2140,
 632                 .vspuls_bline = 0,
 633                 .vspuls_eline = 4,
 634                 .havon_begin = 271,
 635                 .havon_end = 2190,
 636                 .vavon_bline = 41,
 637                 .vavon_eline = 1120,
 638                 /* eqpuls_begin */
 639                 /* eqpuls_end */
 640                 .eqpuls_bline = 0,
 641                 .eqpuls_bline_present = true,
 642                 .eqpuls_eline = 4,
 643                 .eqpuls_eline_present = true,
 644                 .hso_begin = 79,
 645                 .hso_end = 123,
 646                 .vso_begin = 79,
 647                 .vso_end = 79,
 648                 .vso_bline = 0,
 649                 .vso_eline = 5,
 650                 .vso_eline_present = true,
 651                 /* sy_val */
 652                 /* sy2_val */
 653                 .max_lncnt = 1124,
 654         },
 655 };
 656
 657 union meson_hdmi_venc_mode meson_hdmi_encp_mode_1080p60 = {
 658         .encp = {
 659                 .dvi_settings = 0x1,
 660                 .video_mode = 0x4040,
 661                 .video_mode_adv = 0x18,
 662                 .video_prog_mode = 0x100,
 663                 .video_prog_mode_present = true,
 664                 /* video_sync_mode */
 665                 /* video_yc_dly */
 666                 /* video_rgb_ctrl */
 667                 .video_filt_ctrl = 0x1052,
 668                 .video_filt_ctrl_present = true,
 669                 /* video_ofld_voav_ofst */
 670                 .yfp1_htime = 140,
 671                 .yfp2_htime = 2060,
 672                 .max_pxcnt = 2199,
 673                 .hspuls_begin = 2156,
 674                 .hspuls_end = 44,
 675                 .hspuls_switch = 44,
 676                 .vspuls_begin = 140,
 677                 .vspuls_end = 2059,
 678                 .vspuls_bline = 0,
 679                 .vspuls_eline = 4,
 680                 .havon_begin = 148,
 681                 .havon_end = 2067,
 682                 .vavon_bline = 41,
 683                 .vavon_eline = 1120,
 684                 /* eqpuls_begin */
 685                 /* eqpuls_end */
 686                 /* eqpuls_bline */
 687                 /* eqpuls_eline */
 688                 .hso_begin = 44,
 689                 .hso_end = 2156,
 690                 .vso_begin = 2100,
 691                 .vso_end = 2164,
 692                 .vso_bline = 0,
 693                 .vso_eline = 5,
 694                 .vso_eline_present = true,
 695                 /* sy_val */
 696                 /* sy2_val */
 697                 .max_lncnt = 1124,
 698         },
 699 };
 700
 701 union meson_hdmi_venc_mode meson_hdmi_encp_mode_2160p24 = {
 702         .encp = {
 703                 .dvi_settings = 0x1,
 704                 .video_mode = 0x4040,
 705                 .video_mode_adv = 0x8,
 706                 /* video_sync_mode */
 707                 /* video_yc_dly */
 708                 /* video_rgb_ctrl */
 709                 .video_filt_ctrl = 0x1000,
 710                 .video_filt_ctrl_present = true,
 711                 /* video_ofld_voav_ofst */
 712                 .yfp1_htime = 140,
 713                 .yfp2_htime = 140+3840,
 714                 .max_pxcnt = 3840+1660-1,
 715                 .hspuls_begin = 2156+1920,
 716                 .hspuls_end = 44,
 717                 .hspuls_switch = 44,
 718                 .vspuls_begin = 140,
 719                 .vspuls_end = 2059+1920,
 720                 .vspuls_bline = 0,
 721                 .vspuls_eline = 4,
 722                 .havon_begin = 148,
 723                 .havon_end = 3987,
 724                 .vavon_bline = 89,
 725                 .vavon_eline = 2248,
 726                 /* eqpuls_begin */
 727                 /* eqpuls_end */
 728                 /* eqpuls_bline */
 729                 /* eqpuls_eline */
 730                 .hso_begin = 44,
 731                 .hso_end = 2156+1920,
 732                 .vso_begin = 2100+1920,
 733                 .vso_end = 2164+1920,
 734                 .vso_bline = 51,
 735                 .vso_eline = 53,
 736                 .vso_eline_present = true,
 737                 /* sy_val */
 738                 /* sy2_val */
 739                 .max_lncnt = 2249,
 740         },
 741 };
 742
 743 union meson_hdmi_venc_mode meson_hdmi_encp_mode_2160p25 = {
 744         .encp = {
 745                 .dvi_settings = 0x1,
 746                 .video_mode = 0x4040,
 747                 .video_mode_adv = 0x8,
 748                 /* video_sync_mode */
 749                 /* video_yc_dly */
 750                 /* video_rgb_ctrl */
 751                 .video_filt_ctrl = 0x1000,
 752                 .video_filt_ctrl_present = true,
 753                 /* video_ofld_voav_ofst */
 754                 .yfp1_htime = 140,
 755                 .yfp2_htime = 140+3840,
 756                 .max_pxcnt = 3840+1440-1,
 757                 .hspuls_begin = 2156+1920,
 758                 .hspuls_end = 44,
 759                 .hspuls_switch = 44,
 760                 .vspuls_begin = 140,
 761                 .vspuls_end = 2059+1920,
 762                 .vspuls_bline = 0,
 763                 .vspuls_eline = 4,
 764                 .havon_begin = 148,
 765                 .havon_end = 3987,
 766                 .vavon_bline = 89,
 767                 .vavon_eline = 2248,
 768                 /* eqpuls_begin */
 769                 /* eqpuls_end */
 770                 /* eqpuls_bline */
 771                 /* eqpuls_eline */
 772                 .hso_begin = 44,
 773                 .hso_end = 2156+1920,
 774                 .vso_begin = 2100+1920,
 775                 .vso_end = 2164+1920,
 776                 .vso_bline = 51,
 777                 .vso_eline = 53,
 778                 .vso_eline_present = true,
 779                 /* sy_val */
 780                 /* sy2_val */
 781                 .max_lncnt = 2249,
 782         },
 783 };
 784
 785 union meson_hdmi_venc_mode meson_hdmi_encp_mode_2160p30 = {
 786         .encp = {
 787                 .dvi_settings = 0x1,
 788                 .video_mode = 0x4040,
 789                 .video_mode_adv = 0x8,
 790                 /* video_sync_mode */
 791                 /* video_yc_dly */
 792                 /* video_rgb_ctrl */
 793                 .video_filt_ctrl = 0x1000,
 794                 .video_filt_ctrl_present = true,
 795                 /* video_ofld_voav_ofst */
 796                 .yfp1_htime = 140,
 797                 .yfp2_htime = 140+3840,
 798                 .max_pxcnt = 3840+560-1,
 799                 .hspuls_begin = 2156+1920,
 800                 .hspuls_end = 44,
 801                 .hspuls_switch = 44,
 802                 .vspuls_begin = 140,
 803                 .vspuls_end = 2059+1920,
 804                 .vspuls_bline = 0,
 805                 .vspuls_eline = 4,
 806                 .havon_begin = 148,
 807                 .havon_end = 3987,
 808                 .vavon_bline = 89,
 809                 .vavon_eline = 2248,
 810                 /* eqpuls_begin */
 811                 /* eqpuls_end */
 812                 /* eqpuls_bline */
 813                 /* eqpuls_eline */
 814                 .hso_begin = 44,
 815                 .hso_end = 2156+1920,
 816                 .vso_begin = 2100+1920,
 817                 .vso_end = 2164+1920,
 818                 .vso_bline = 51,
 819                 .vso_eline = 53,
 820                 .vso_eline_present = true,
 821                 /* sy_val */
 822                 /* sy2_val */
 823                 .max_lncnt = 2249,
 824         },
 825 };
 826
 827 struct meson_hdmi_venc_vic_mode {
 828         unsigned int vic;
 829         union meson_hdmi_venc_mode *mode;
 830 } meson_hdmi_venc_vic_modes[] = {
 831         { 6, &meson_hdmi_enci_mode_480i },
 832         { 7, &meson_hdmi_enci_mode_480i },
 833         { 21, &meson_hdmi_enci_mode_576i },
 834         { 22, &meson_hdmi_enci_mode_576i },
 835         { 2, &meson_hdmi_encp_mode_480p },
 836         { 3, &meson_hdmi_encp_mode_480p },
 837         { 17, &meson_hdmi_encp_mode_576p },
 838         { 18, &meson_hdmi_encp_mode_576p },
 839         { 4, &meson_hdmi_encp_mode_720p60 },
 840         { 19, &meson_hdmi_encp_mode_720p50 },
 841         { 5, &meson_hdmi_encp_mode_1080i60 },
 842         { 20, &meson_hdmi_encp_mode_1080i50 },
 843         { 32, &meson_hdmi_encp_mode_1080p24 },
 844         { 33, &meson_hdmi_encp_mode_1080p50 },
 845         { 34, &meson_hdmi_encp_mode_1080p30 },
 846         { 31, &meson_hdmi_encp_mode_1080p50 },
 847         { 16, &meson_hdmi_encp_mode_1080p60 },
 848         { 93, &meson_hdmi_encp_mode_2160p24 },
 849         { 94, &meson_hdmi_encp_mode_2160p25 },
 850         { 95, &meson_hdmi_encp_mode_2160p30 },
 851         { 0, NULL}, /* sentinel */
 852 };
 853
 854 static signed int to_signed(unsigned int a)
 855 {
 856         if (a <= 7)
 857                 return a;
 858         else
 859                 return a - 16;
 860 }
 861
 862 static unsigned long modulo(unsigned long a, unsigned long b)
 863 {
 864         if (a >= b)
 865                 return a - b;
 866         else
 867                 return a;
 868 }
 869
 870 enum drm_mode_status
 871 meson_venc_hdmi_supported_mode(const struct drm_display_mode *mode)
 872 {
 873         if (mode->flags & ~(DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NHSYNC |
 874                             DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC))
 875                 return MODE_BAD;
 876
 877         if (mode->hdisplay < 640 || mode->hdisplay > 1920)
 878                 return MODE_BAD_HVALUE;
 879
 880         if (mode->vdisplay < 480 || mode->vdisplay > 1200)
 881                 return MODE_BAD_VVALUE;
 882
 883         return MODE_OK;
 884 }
 885 EXPORT_SYMBOL_GPL(meson_venc_hdmi_supported_mode);
 886
 887 bool meson_venc_hdmi_supported_vic(int vic)
 888 {
 889         struct meson_hdmi_venc_vic_mode *vmode = meson_hdmi_venc_vic_modes;
 890
 891         while (vmode->vic && vmode->mode) {
 892                 if (vmode->vic == vic)
 893                         return true;
 894                 vmode++;
 895         }
 896
 897         return false;
 898 }
 899 EXPORT_SYMBOL_GPL(meson_venc_hdmi_supported_vic);
 900
 901 void meson_venc_hdmi_get_dmt_vmode(const struct drm_display_mode *mode,
 902                                    union meson_hdmi_venc_mode *dmt_mode)
 903 {
 904         memset(dmt_mode, 0, sizeof(*dmt_mode));
 905
 906         dmt_mode->encp.dvi_settings = 0x21;
 907         dmt_mode->encp.video_mode = 0x4040;
 908         dmt_mode->encp.video_mode_adv = 0x18;
 909         dmt_mode->encp.max_pxcnt = mode->htotal - 1;
 910         dmt_mode->encp.havon_begin = mode->htotal - mode->hsync_start;
 911         dmt_mode->encp.havon_end = dmt_mode->encp.havon_begin +
 912                                    mode->hdisplay - 1;
 913         dmt_mode->encp.vavon_bline = mode->vtotal - mode->vsync_start;
 914         dmt_mode->encp.vavon_eline = dmt_mode->encp.vavon_bline +
 915                                      mode->vdisplay - 1;
 916         dmt_mode->encp.hso_begin = 0;
 917         dmt_mode->encp.hso_end = mode->hsync_end - mode->hsync_start;
 918         dmt_mode->encp.vso_begin = 30;
 919         dmt_mode->encp.vso_end = 50;
 920         dmt_mode->encp.vso_bline = 0;
 921         dmt_mode->encp.vso_eline = mode->vsync_end - mode->vsync_start;
 922         dmt_mode->encp.vso_eline_present = true;
 923         dmt_mode->encp.max_lncnt = mode->vtotal - 1;
 924 }
 925
 926 static union meson_hdmi_venc_mode *meson_venc_hdmi_get_vic_vmode(int vic)
 927 {
 928         struct meson_hdmi_venc_vic_mode *vmode = meson_hdmi_venc_vic_modes;
 929
 930         while (vmode->vic && vmode->mode) {
 931                 if (vmode->vic == vic)
 932                         return vmode->mode;
 933                 vmode++;
 934         }
 935
 936         return NULL;
 937 }
 938
 939 bool meson_venc_hdmi_venc_repeat(int vic)
 940 {
 941         /* Repeat VENC pixels for 480/576i/p, 720p50/60 and 1080p50/60 */
 942         if (vic == 6 || vic == 7 || /* 480i */
 943             vic == 21 || vic == 22 || /* 576i */
 944             vic == 17 || vic == 18 || /* 576p */
 945             vic == 2 || vic == 3 || /* 480p */
 946             vic == 4 || /* 720p60 */
 947             vic == 19 || /* 720p50 */
 948             vic == 5 || /* 1080i60 */
 949             vic == 20)  /* 1080i50 */
 950                 return true;
 951
 952         return false;
 953 }
 954 EXPORT_SYMBOL_GPL(meson_venc_hdmi_venc_repeat);
 955
 956 void meson_venc_hdmi_mode_set(struct meson_drm *priv, int vic,
 957                               struct drm_display_mode *mode)
 958 {
 959         union meson_hdmi_venc_mode *vmode = NULL;
 960         union meson_hdmi_venc_mode vmode_dmt;
 961         bool use_enci = false;
 962         bool venc_repeat = false;
 963         bool hdmi_repeat = false;
 964         unsigned int venc_hdmi_latency = 2;
 965         unsigned long total_pixels_venc = 0;
 966         unsigned long active_pixels_venc = 0;
 967         unsigned long front_porch_venc = 0;
 968         unsigned long hsync_pixels_venc = 0;
 969         unsigned long de_h_begin = 0;
 970         unsigned long de_h_end = 0;
 971         unsigned long de_v_begin_even = 0;
 972         unsigned long de_v_end_even = 0;
 973         unsigned long de_v_begin_odd = 0;
 974         unsigned long de_v_end_odd = 0;
 975         unsigned long hs_begin = 0;
 976         unsigned long hs_end = 0;
 977         unsigned long vs_adjust = 0;
 978         unsigned long vs_bline_evn = 0;
 979         unsigned long vs_eline_evn = 0;
 980         unsigned long vs_bline_odd = 0;
 981         unsigned long vs_eline_odd = 0;
 982         unsigned long vso_begin_evn = 0;
 983         unsigned long vso_begin_odd = 0;
 984         unsigned int eof_lines;
 985         unsigned int sof_lines;
 986         unsigned int vsync_lines;
 987
 988         /* Use VENCI for 480i and 576i and double HDMI pixels */
 989         if (mode->flags & DRM_MODE_FLAG_DBLCLK) {
 990                 hdmi_repeat = true;
 991                 use_enci = true;
 992                 venc_hdmi_latency = 1;
 993         }
 994
 995         if (meson_venc_hdmi_supported_vic(vic)) {
 996                 vmode = meson_venc_hdmi_get_vic_vmode(vic);
 997                 if (!vmode) {
 998                         dev_err(priv->dev, "%s: Fatal Error, unsupported mode "
 999                                 DRM_MODE_FMT "\n", __func__,
1000                                 DRM_MODE_ARG(mode));
1001                         return;
1002                 }
1003         } else {
1004                 meson_venc_hdmi_get_dmt_vmode(mode, &vmode_dmt);
1005                 vmode = &vmode_dmt;
1006                 use_enci = false;
1007         }
1008
1009         /* Repeat VENC pixels for 480/576i/p, 720p50/60 and 1080p50/60 */
1010         if (meson_venc_hdmi_venc_repeat(vic))
1011                 venc_repeat = true;
1012
1013         eof_lines = mode->vsync_start - mode->vdisplay;
1014         if (mode->flags & DRM_MODE_FLAG_INTERLACE)
1015                 eof_lines /= 2;
1016         sof_lines = mode->vtotal - mode->vsync_end;
1017         if (mode->flags & DRM_MODE_FLAG_INTERLACE)
1018                 sof_lines /= 2;
1019         vsync_lines = mode->vsync_end - mode->vsync_start;
1020         if (mode->flags & DRM_MODE_FLAG_INTERLACE)
1021                 vsync_lines /= 2;
1022
1023         total_pixels_venc = mode->htotal;
1024         if (hdmi_repeat)
1025                 total_pixels_venc /= 2;
1026         if (venc_repeat)
1027                 total_pixels_venc *= 2;
1028
1029         active_pixels_venc = mode->hdisplay;
1030         if (hdmi_repeat)
1031                 active_pixels_venc /= 2;
1032         if (venc_repeat)
1033                 active_pixels_venc *= 2;
1034
1035         front_porch_venc = (mode->hsync_start - mode->hdisplay);
1036         if (hdmi_repeat)
1037                 front_porch_venc /= 2;
1038         if (venc_repeat)
1039                 front_porch_venc *= 2;
1040
1041         hsync_pixels_venc = (mode->hsync_end - mode->hsync_start);
1042         if (hdmi_repeat)
1043                 hsync_pixels_venc /= 2;
1044         if (venc_repeat)
1045                 hsync_pixels_venc *= 2;
1046
1047         /* Disable VDACs */
1048         writel_bits_relaxed(0xff, 0xff,
1049                         priv->io_base + _REG(VENC_VDAC_SETTING));
1050
1051         writel_relaxed(0, priv->io_base + _REG(ENCI_VIDEO_EN));
1052         writel_relaxed(0, priv->io_base + _REG(ENCP_VIDEO_EN));
1053
1054         if (use_enci) {
1055                 unsigned int lines_f0;
1056                 unsigned int lines_f1;
1057
1058                 /* CVBS Filter settings */
1059                 writel_relaxed(0x12, priv->io_base + _REG(ENCI_CFILT_CTRL));
1060                 writel_relaxed(0x12, priv->io_base + _REG(ENCI_CFILT_CTRL2));
1061
1062                 /* Digital Video Select : Interlace, clk27 clk, external */
1063                 writel_relaxed(0, priv->io_base + _REG(VENC_DVI_SETTING));
1064
1065                 /* Reset Video Mode */
1066                 writel_relaxed(0, priv->io_base + _REG(ENCI_VIDEO_MODE));
1067                 writel_relaxed(0, priv->io_base + _REG(ENCI_VIDEO_MODE_ADV));
1068
1069                 /* Horizontal sync signal output */
1070                 writel_relaxed(vmode->enci.hso_begin,
1071                                 priv->io_base + _REG(ENCI_SYNC_HSO_BEGIN));
1072                 writel_relaxed(vmode->enci.hso_end,
1073                                 priv->io_base + _REG(ENCI_SYNC_HSO_END));
1074
1075                 /* Vertical Sync lines */
1076                 writel_relaxed(vmode->enci.vso_even,
1077                                 priv->io_base + _REG(ENCI_SYNC_VSO_EVNLN));
1078                 writel_relaxed(vmode->enci.vso_odd,
1079                                 priv->io_base + _REG(ENCI_SYNC_VSO_ODDLN));
1080
1081                 /* Macrovision max amplitude change */
1082                 writel_relaxed(vmode->enci.macv_max_amp,
1083                                 priv->io_base + _REG(ENCI_MACV_MAX_AMP));
1084
1085                 /* Video mode */
1086                 writel_relaxed(vmode->enci.video_prog_mode,
1087                                 priv->io_base + _REG(VENC_VIDEO_PROG_MODE));
1088                 writel_relaxed(vmode->enci.video_mode,
1089                                 priv->io_base + _REG(ENCI_VIDEO_MODE));
1090
1091                 /* Advanced Video Mode :
1092                  * Demux shifting 0x2
1093                  * Blank line end at line17/22
1094                  * High bandwidth Luma Filter
1095                  * Low bandwidth Chroma Filter
1096                  * Bypass luma low pass filter
1097                  * No macrovision on CSYNC
1098                  */
1099                 writel_relaxed(0x26, priv->io_base + _REG(ENCI_VIDEO_MODE_ADV));
1100
1101                 writel(vmode->enci.sch_adjust,
1102                                 priv->io_base + _REG(ENCI_VIDEO_SCH));
1103
1104                 /* Sync mode : MASTER Master mode, free run, send HSO/VSO out */
1105                 writel_relaxed(0x07, priv->io_base + _REG(ENCI_SYNC_MODE));
1106
1107                 if (vmode->enci.yc_delay)
1108                         writel_relaxed(vmode->enci.yc_delay,
1109                                         priv->io_base + _REG(ENCI_YC_DELAY));
1110
1111
1112                 /* UNreset Interlaced TV Encoder */
1113                 writel_relaxed(0, priv->io_base + _REG(ENCI_DBG_PX_RST));
1114
1115                 /* Enable Vfifo2vd, Y_Cb_Y_Cr select */
1116                 writel_relaxed(0x4e01, priv->io_base + _REG(ENCI_VFIFO2VD_CTL));
1117
1118                 /* Timings */
1119                 writel_relaxed(vmode->enci.pixel_start,
1120                         priv->io_base + _REG(ENCI_VFIFO2VD_PIXEL_START));
1121                 writel_relaxed(vmode->enci.pixel_end,
1122                         priv->io_base + _REG(ENCI_VFIFO2VD_PIXEL_END));
1123
1124                 writel_relaxed(vmode->enci.top_field_line_start,
1125                         priv->io_base + _REG(ENCI_VFIFO2VD_LINE_TOP_START));
1126                 writel_relaxed(vmode->enci.top_field_line_end,
1127                         priv->io_base + _REG(ENCI_VFIFO2VD_LINE_TOP_END));
1128
1129                 writel_relaxed(vmode->enci.bottom_field_line_start,
1130                         priv->io_base + _REG(ENCI_VFIFO2VD_LINE_BOT_START));
1131                 writel_relaxed(vmode->enci.bottom_field_line_end,
1132                         priv->io_base + _REG(ENCI_VFIFO2VD_LINE_BOT_END));
1133
1134                 /* Select ENCI for VIU */
1135                 meson_vpp_setup_mux(priv, MESON_VIU_VPP_MUX_ENCI);
1136
1137                 /* Interlace video enable */
1138                 writel_relaxed(1, priv->io_base + _REG(ENCI_VIDEO_EN));
1139
1140                 lines_f0 = mode->vtotal >> 1;
1141                 lines_f1 = lines_f0 + 1;
1142
1143                 de_h_begin = modulo(readl_relaxed(priv->io_base +
1144                                         _REG(ENCI_VFIFO2VD_PIXEL_START))
1145                                         + venc_hdmi_latency,
1146                                     total_pixels_venc);
1147                 de_h_end  = modulo(de_h_begin + active_pixels_venc,
1148                                    total_pixels_venc);
1149
1150                 writel_relaxed(de_h_begin,
1151                                 priv->io_base + _REG(ENCI_DE_H_BEGIN));
1152                 writel_relaxed(de_h_end,
1153                                 priv->io_base + _REG(ENCI_DE_H_END));
1154
1155                 de_v_begin_even = readl_relaxed(priv->io_base +
1156                                         _REG(ENCI_VFIFO2VD_LINE_TOP_START));
1157                 de_v_end_even  = de_v_begin_even + mode->vdisplay;
1158                 de_v_begin_odd = readl_relaxed(priv->io_base +
1159                                         _REG(ENCI_VFIFO2VD_LINE_BOT_START));
1160                 de_v_end_odd = de_v_begin_odd + mode->vdisplay;
1161
1162                 writel_relaxed(de_v_begin_even,
1163                                 priv->io_base + _REG(ENCI_DE_V_BEGIN_EVEN));
1164                 writel_relaxed(de_v_end_even,
1165                                 priv->io_base + _REG(ENCI_DE_V_END_EVEN));
1166                 writel_relaxed(de_v_begin_odd,
1167                                 priv->io_base + _REG(ENCI_DE_V_BEGIN_ODD));
1168                 writel_relaxed(de_v_end_odd,
1169                                 priv->io_base + _REG(ENCI_DE_V_END_ODD));
1170
1171                 /* Program Hsync timing */
1172                 hs_begin = de_h_end + front_porch_venc;
1173                 if (de_h_end + front_porch_venc >= total_pixels_venc) {
1174                         hs_begin -= total_pixels_venc;
1175                         vs_adjust  = 1;
1176                 } else {
1177                         hs_begin = de_h_end + front_porch_venc;
1178                         vs_adjust  = 0;
1179                 }
1180
1181                 hs_end = modulo(hs_begin + hsync_pixels_venc,
1182                                 total_pixels_venc);
1183                 writel_relaxed(hs_begin,
1184                                 priv->io_base + _REG(ENCI_DVI_HSO_BEGIN));
1185                 writel_relaxed(hs_end,
1186                                 priv->io_base + _REG(ENCI_DVI_HSO_END));
1187
1188                 /* Program Vsync timing for even field */
1189                 if (((de_v_end_odd - 1) + eof_lines + vs_adjust) >= lines_f1) {
1190                         vs_bline_evn = (de_v_end_odd - 1)
1191                                         + eof_lines
1192                                         + vs_adjust
1193                                         - lines_f1;
1194                         vs_eline_evn = vs_bline_evn + vsync_lines;
1195
1196                         writel_relaxed(vs_bline_evn,
1197                                 priv->io_base + _REG(ENCI_DVI_VSO_BLINE_EVN));
1198
1199                         writel_relaxed(vs_eline_evn,
1200                                 priv->io_base + _REG(ENCI_DVI_VSO_ELINE_EVN));
1201
1202                         writel_relaxed(hs_begin,
1203                                 priv->io_base + _REG(ENCI_DVI_VSO_BEGIN_EVN));
1204                         writel_relaxed(hs_begin,
1205                                 priv->io_base + _REG(ENCI_DVI_VSO_END_EVN));
1206                 } else {
1207                         vs_bline_odd = (de_v_end_odd - 1)
1208                                         + eof_lines
1209                                         + vs_adjust;
1210
1211                         writel_relaxed(vs_bline_odd,
1212                                 priv->io_base + _REG(ENCI_DVI_VSO_BLINE_ODD));
1213
1214                         writel_relaxed(hs_begin,
1215                                 priv->io_base + _REG(ENCI_DVI_VSO_BEGIN_ODD));
1216
1217                         if ((vs_bline_odd + vsync_lines) >= lines_f1) {
1218                                 vs_eline_evn = vs_bline_odd
1219                                                 + vsync_lines
1220                                                 - lines_f1;
1221
1222                                 writel_relaxed(vs_eline_evn, priv->io_base
1223                                                 + _REG(ENCI_DVI_VSO_ELINE_EVN));
1224
1225                                 writel_relaxed(hs_begin, priv->io_base
1226                                                 + _REG(ENCI_DVI_VSO_END_EVN));
1227                         } else {
1228                                 vs_eline_odd = vs_bline_odd
1229                                                 + vsync_lines;
1230
1231                                 writel_relaxed(vs_eline_odd, priv->io_base
1232                                                 + _REG(ENCI_DVI_VSO_ELINE_ODD));
1233
1234                                 writel_relaxed(hs_begin, priv->io_base
1235                                                 + _REG(ENCI_DVI_VSO_END_ODD));
1236                         }
1237                 }
1238
1239                 /* Program Vsync timing for odd field */
1240                 if (((de_v_end_even - 1) + (eof_lines + 1)) >= lines_f0) {
1241                         vs_bline_odd = (de_v_end_even - 1)
1242                                         + (eof_lines + 1)
1243                                         - lines_f0;
1244                         vs_eline_odd = vs_bline_odd + vsync_lines;
1245
1246                         writel_relaxed(vs_bline_odd,
1247                                 priv->io_base + _REG(ENCI_DVI_VSO_BLINE_ODD));
1248
1249                         writel_relaxed(vs_eline_odd,
1250                                 priv->io_base + _REG(ENCI_DVI_VSO_ELINE_ODD));
1251
1252                         vso_begin_odd  = modulo(hs_begin
1253                                                 + (total_pixels_venc >> 1),
1254                                                 total_pixels_venc);
1255
1256                         writel_relaxed(vso_begin_odd,
1257                                 priv->io_base + _REG(ENCI_DVI_VSO_BEGIN_ODD));
1258                         writel_relaxed(vso_begin_odd,
1259                                 priv->io_base + _REG(ENCI_DVI_VSO_END_ODD));
1260                 } else {
1261                         vs_bline_evn = (de_v_end_even - 1)
1262                                         + (eof_lines + 1);
1263
1264                         writel_relaxed(vs_bline_evn,
1265                                 priv->io_base + _REG(ENCI_DVI_VSO_BLINE_EVN));
1266
1267                         vso_begin_evn  = modulo(hs_begin
1268                                                 + (total_pixels_venc >> 1),
1269                                                 total_pixels_venc);
1270
1271                         writel_relaxed(vso_begin_evn, priv->io_base
1272                                         + _REG(ENCI_DVI_VSO_BEGIN_EVN));
1273
1274                         if (vs_bline_evn + vsync_lines >= lines_f0) {
1275                                 vs_eline_odd = vs_bline_evn
1276                                                 + vsync_lines
1277                                                 - lines_f0;
1278
1279                                 writel_relaxed(vs_eline_odd, priv->io_base
1280                                                 + _REG(ENCI_DVI_VSO_ELINE_ODD));
1281
1282                                 writel_relaxed(vso_begin_evn, priv->io_base
1283                                                 + _REG(ENCI_DVI_VSO_END_ODD));
1284                         } else {
1285                                 vs_eline_evn = vs_bline_evn + vsync_lines;
1286
1287                                 writel_relaxed(vs_eline_evn, priv->io_base
1288                                                 + _REG(ENCI_DVI_VSO_ELINE_EVN));
1289
1290                                 writel_relaxed(vso_begin_evn, priv->io_base
1291                                                 + _REG(ENCI_DVI_VSO_END_EVN));
1292                         }
1293                 }
1294         } else {
1295                 writel_relaxed(vmode->encp.dvi_settings,
1296                                 priv->io_base + _REG(VENC_DVI_SETTING));
1297                 writel_relaxed(vmode->encp.video_mode,
1298                                 priv->io_base + _REG(ENCP_VIDEO_MODE));
1299                 writel_relaxed(vmode->encp.video_mode_adv,
1300                                 priv->io_base + _REG(ENCP_VIDEO_MODE_ADV));
1301                 if (vmode->encp.video_prog_mode_present)
1302                         writel_relaxed(vmode->encp.video_prog_mode,
1303                                 priv->io_base + _REG(VENC_VIDEO_PROG_MODE));
1304                 if (vmode->encp.video_sync_mode_present)
1305                         writel_relaxed(vmode->encp.video_sync_mode,
1306                                 priv->io_base + _REG(ENCP_VIDEO_SYNC_MODE));
1307                 if (vmode->encp.video_yc_dly_present)
1308                         writel_relaxed(vmode->encp.video_yc_dly,
1309                                 priv->io_base + _REG(ENCP_VIDEO_YC_DLY));
1310                 if (vmode->encp.video_rgb_ctrl_present)
1311                         writel_relaxed(vmode->encp.video_rgb_ctrl,
1312                                 priv->io_base + _REG(ENCP_VIDEO_RGB_CTRL));
1313                 if (vmode->encp.video_filt_ctrl_present)
1314                         writel_relaxed(vmode->encp.video_filt_ctrl,
1315                                 priv->io_base + _REG(ENCP_VIDEO_FILT_CTRL));
1316                 if (vmode->encp.video_ofld_voav_ofst_present)
1317                         writel_relaxed(vmode->encp.video_ofld_voav_ofst,
1318                                 priv->io_base
1319                                 + _REG(ENCP_VIDEO_OFLD_VOAV_OFST));
1320                 writel_relaxed(vmode->encp.yfp1_htime,
1321                                 priv->io_base + _REG(ENCP_VIDEO_YFP1_HTIME));
1322                 writel_relaxed(vmode->encp.yfp2_htime,
1323                                 priv->io_base + _REG(ENCP_VIDEO_YFP2_HTIME));
1324                 writel_relaxed(vmode->encp.max_pxcnt,
1325                                 priv->io_base + _REG(ENCP_VIDEO_MAX_PXCNT));
1326                 writel_relaxed(vmode->encp.hspuls_begin,
1327                                 priv->io_base + _REG(ENCP_VIDEO_HSPULS_BEGIN));
1328                 writel_relaxed(vmode->encp.hspuls_end,
1329                                 priv->io_base + _REG(ENCP_VIDEO_HSPULS_END));
1330                 writel_relaxed(vmode->encp.hspuls_switch,
1331                                 priv->io_base + _REG(ENCP_VIDEO_HSPULS_SWITCH));
1332                 writel_relaxed(vmode->encp.vspuls_begin,
1333                                 priv->io_base + _REG(ENCP_VIDEO_VSPULS_BEGIN));
1334                 writel_relaxed(vmode->encp.vspuls_end,
1335                                 priv->io_base + _REG(ENCP_VIDEO_VSPULS_END));
1336                 writel_relaxed(vmode->encp.vspuls_bline,
1337                                 priv->io_base + _REG(ENCP_VIDEO_VSPULS_BLINE));
1338                 writel_relaxed(vmode->encp.vspuls_eline,
1339                                 priv->io_base + _REG(ENCP_VIDEO_VSPULS_ELINE));
1340                 if (vmode->encp.eqpuls_begin_present)
1341                         writel_relaxed(vmode->encp.eqpuls_begin,
1342                                 priv->io_base + _REG(ENCP_VIDEO_EQPULS_BEGIN));
1343                 if (vmode->encp.eqpuls_end_present)
1344                         writel_relaxed(vmode->encp.eqpuls_end,
1345                                 priv->io_base + _REG(ENCP_VIDEO_EQPULS_END));
1346                 if (vmode->encp.eqpuls_bline_present)
1347                         writel_relaxed(vmode->encp.eqpuls_bline,
1348                                 priv->io_base + _REG(ENCP_VIDEO_EQPULS_BLINE));
1349                 if (vmode->encp.eqpuls_eline_present)
1350                         writel_relaxed(vmode->encp.eqpuls_eline,
1351                                 priv->io_base + _REG(ENCP_VIDEO_EQPULS_ELINE));
1352                 writel_relaxed(vmode->encp.havon_begin,
1353                                 priv->io_base + _REG(ENCP_VIDEO_HAVON_BEGIN));
1354                 writel_relaxed(vmode->encp.havon_end,
1355                                 priv->io_base + _REG(ENCP_VIDEO_HAVON_END));
1356                 writel_relaxed(vmode->encp.vavon_bline,
1357                                 priv->io_base + _REG(ENCP_VIDEO_VAVON_BLINE));
1358                 writel_relaxed(vmode->encp.vavon_eline,
1359                                 priv->io_base + _REG(ENCP_VIDEO_VAVON_ELINE));
1360                 writel_relaxed(vmode->encp.hso_begin,
1361                                 priv->io_base + _REG(ENCP_VIDEO_HSO_BEGIN));
1362                 writel_relaxed(vmode->encp.hso_end,
1363                                 priv->io_base + _REG(ENCP_VIDEO_HSO_END));
1364                 writel_relaxed(vmode->encp.vso_begin,
1365                                 priv->io_base + _REG(ENCP_VIDEO_VSO_BEGIN));
1366                 writel_relaxed(vmode->encp.vso_end,
1367                                 priv->io_base + _REG(ENCP_VIDEO_VSO_END));
1368                 writel_relaxed(vmode->encp.vso_bline,
1369                                 priv->io_base + _REG(ENCP_VIDEO_VSO_BLINE));
1370                 if (vmode->encp.vso_eline_present)
1371                         writel_relaxed(vmode->encp.vso_eline,
1372                                 priv->io_base + _REG(ENCP_VIDEO_VSO_ELINE));
1373                 if (vmode->encp.sy_val_present)
1374                         writel_relaxed(vmode->encp.sy_val,
1375                                 priv->io_base + _REG(ENCP_VIDEO_SY_VAL));
1376                 if (vmode->encp.sy2_val_present)
1377                         writel_relaxed(vmode->encp.sy2_val,
1378                                 priv->io_base + _REG(ENCP_VIDEO_SY2_VAL));
1379                 writel_relaxed(vmode->encp.max_lncnt,
1380                                 priv->io_base + _REG(ENCP_VIDEO_MAX_LNCNT));
1381
1382                 writel_relaxed(1, priv->io_base + _REG(ENCP_VIDEO_EN));
1383
1384                 /* Set DE signal’s polarity is active high */
1385                 writel_bits_relaxed(BIT(14), BIT(14),
1386                                     priv->io_base + _REG(ENCP_VIDEO_MODE));
1387
1388                 /* Program DE timing */
1389                 de_h_begin = modulo(readl_relaxed(priv->io_base +
1390                                         _REG(ENCP_VIDEO_HAVON_BEGIN))
1391                                         + venc_hdmi_latency,
1392                                     total_pixels_venc);
1393                 de_h_end = modulo(de_h_begin + active_pixels_venc,
1394                                   total_pixels_venc);
1395
1396                 writel_relaxed(de_h_begin,
1397                                 priv->io_base + _REG(ENCP_DE_H_BEGIN));
1398                 writel_relaxed(de_h_end,
1399                                 priv->io_base + _REG(ENCP_DE_H_END));
1400
1401                 /* Program DE timing for even field */
1402                 de_v_begin_even = readl_relaxed(priv->io_base
1403                                                 + _REG(ENCP_VIDEO_VAVON_BLINE));
1404                 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
1405                         de_v_end_even = de_v_begin_even +
1406                                         (mode->vdisplay / 2);
1407                 else
1408                         de_v_end_even = de_v_begin_even + mode->vdisplay;
1409
1410                 writel_relaxed(de_v_begin_even,
1411                                 priv->io_base + _REG(ENCP_DE_V_BEGIN_EVEN));
1412                 writel_relaxed(de_v_end_even,
1413                                 priv->io_base + _REG(ENCP_DE_V_END_EVEN));
1414
1415                 /* Program DE timing for odd field if needed */
1416                 if (mode->flags & DRM_MODE_FLAG_INTERLACE) {
1417                         unsigned int ofld_voav_ofst =
1418                                 readl_relaxed(priv->io_base +
1419                                         _REG(ENCP_VIDEO_OFLD_VOAV_OFST));
1420                         de_v_begin_odd = to_signed((ofld_voav_ofst & 0xf0) >> 4)
1421                                                 + de_v_begin_even
1422                                                 + ((mode->vtotal - 1) / 2);
1423                         de_v_end_odd = de_v_begin_odd + (mode->vdisplay / 2);
1424
1425                         writel_relaxed(de_v_begin_odd,
1426                                 priv->io_base + _REG(ENCP_DE_V_BEGIN_ODD));
1427                         writel_relaxed(de_v_end_odd,
1428                                 priv->io_base + _REG(ENCP_DE_V_END_ODD));
1429                 }
1430
1431                 /* Program Hsync timing */
1432                 if ((de_h_end + front_porch_venc) >= total_pixels_venc) {
1433                         hs_begin = de_h_end
1434                                    + front_porch_venc
1435                                    - total_pixels_venc;
1436                         vs_adjust  = 1;
1437                 } else {
1438                         hs_begin = de_h_end
1439                                    + front_porch_venc;
1440                         vs_adjust  = 0;
1441                 }
1442
1443                 hs_end = modulo(hs_begin + hsync_pixels_venc,
1444                                 total_pixels_venc);
1445
1446                 writel_relaxed(hs_begin,
1447                                 priv->io_base + _REG(ENCP_DVI_HSO_BEGIN));
1448                 writel_relaxed(hs_end,
1449                                 priv->io_base + _REG(ENCP_DVI_HSO_END));
1450
1451                 /* Program Vsync timing for even field */
1452                 if (de_v_begin_even >=
1453                                 (sof_lines + vsync_lines + (1 - vs_adjust)))
1454                         vs_bline_evn = de_v_begin_even
1455                                         - sof_lines
1456                                         - vsync_lines
1457                                         - (1 - vs_adjust);
1458                 else
1459                         vs_bline_evn = mode->vtotal
1460                                         + de_v_begin_even
1461                                         - sof_lines
1462                                         - vsync_lines
1463                                         - (1 - vs_adjust);
1464
1465                 vs_eline_evn = modulo(vs_bline_evn + vsync_lines,
1466                                         mode->vtotal);
1467
1468                 writel_relaxed(vs_bline_evn,
1469                                 priv->io_base + _REG(ENCP_DVI_VSO_BLINE_EVN));
1470                 writel_relaxed(vs_eline_evn,
1471                                 priv->io_base + _REG(ENCP_DVI_VSO_ELINE_EVN));
1472
1473                 vso_begin_evn = hs_begin;
1474                 writel_relaxed(vso_begin_evn,
1475                                 priv->io_base + _REG(ENCP_DVI_VSO_BEGIN_EVN));
1476                 writel_relaxed(vso_begin_evn,
1477                                 priv->io_base + _REG(ENCP_DVI_VSO_END_EVN));
1478
1479                 /* Program Vsync timing for odd field if needed */
1480                 if (mode->flags & DRM_MODE_FLAG_INTERLACE) {
1481                         vs_bline_odd = (de_v_begin_odd - 1)
1482                                         - sof_lines
1483                                         - vsync_lines;
1484                         vs_eline_odd = (de_v_begin_odd - 1)
1485                                         - vsync_lines;
1486                         vso_begin_odd  = modulo(hs_begin
1487                                                 + (total_pixels_venc >> 1),
1488                                                 total_pixels_venc);
1489
1490                         writel_relaxed(vs_bline_odd,
1491                                 priv->io_base + _REG(ENCP_DVI_VSO_BLINE_ODD));
1492                         writel_relaxed(vs_eline_odd,
1493                                 priv->io_base + _REG(ENCP_DVI_VSO_ELINE_ODD));
1494                         writel_relaxed(vso_begin_odd,
1495                                 priv->io_base + _REG(ENCP_DVI_VSO_BEGIN_ODD));
1496                         writel_relaxed(vso_begin_odd,
1497                                 priv->io_base + _REG(ENCP_DVI_VSO_END_ODD));
1498                 }
1499
1500                 /* Select ENCP for VIU */
1501                 meson_vpp_setup_mux(priv, MESON_VIU_VPP_MUX_ENCP);
1502         }
1503
1504         writel_relaxed((use_enci ? 1 : 2) |
1505                        (mode->flags & DRM_MODE_FLAG_PHSYNC ? 1 << 2 : 0) |
1506                        (mode->flags & DRM_MODE_FLAG_PVSYNC ? 1 << 3 : 0) |
1507                        4 << 5 |
1508                        (venc_repeat ? 1 << 8 : 0) |
1509                        (hdmi_repeat ? 1 << 12 : 0),
1510                        priv->io_base + _REG(VPU_HDMI_SETTING));
1511
1512         priv->venc.hdmi_repeat = hdmi_repeat;
1513         priv->venc.venc_repeat = venc_repeat;
1514         priv->venc.hdmi_use_enci = use_enci;
1515
1516         priv->venc.current_mode = MESON_VENC_MODE_HDMI;
1517 }
1518 EXPORT_SYMBOL_GPL(meson_venc_hdmi_mode_set);
1519
1520 void meson_venci_cvbs_mode_set(struct meson_drm *priv,
1521                                struct meson_cvbs_enci_mode *mode)
1522 {
1523         if (mode->mode_tag == priv->venc.current_mode)
1524                 return;
1525
1526         /* CVBS Filter settings */
1527         writel_relaxed(0x12, priv->io_base + _REG(ENCI_CFILT_CTRL));
1528         writel_relaxed(0x12, priv->io_base + _REG(ENCI_CFILT_CTRL2));
1529
1530         /* Digital Video Select : Interlace, clk27 clk, external */
1531         writel_relaxed(0, priv->io_base + _REG(VENC_DVI_SETTING));
1532
1533         /* Reset Video Mode */
1534         writel_relaxed(0, priv->io_base + _REG(ENCI_VIDEO_MODE));
1535         writel_relaxed(0, priv->io_base + _REG(ENCI_VIDEO_MODE_ADV));
1536
1537         /* Horizontal sync signal output */
1538         writel_relaxed(mode->hso_begin,
1539                         priv->io_base + _REG(ENCI_SYNC_HSO_BEGIN));
1540         writel_relaxed(mode->hso_end,
1541                         priv->io_base + _REG(ENCI_SYNC_HSO_END));
1542
1543         /* Vertical Sync lines */
1544         writel_relaxed(mode->vso_even,
1545                         priv->io_base + _REG(ENCI_SYNC_VSO_EVNLN));
1546         writel_relaxed(mode->vso_odd,
1547                         priv->io_base + _REG(ENCI_SYNC_VSO_ODDLN));
1548
1549         /* Macrovision max amplitude change */
1550         writel_relaxed(0x8100 + mode->macv_max_amp,
1551                         priv->io_base + _REG(ENCI_MACV_MAX_AMP));
1552
1553         /* Video mode */
1554         writel_relaxed(mode->video_prog_mode,
1555                         priv->io_base + _REG(VENC_VIDEO_PROG_MODE));
1556         writel_relaxed(mode->video_mode,
1557                         priv->io_base + _REG(ENCI_VIDEO_MODE));
1558
1559         /* Advanced Video Mode :
1560          * Demux shifting 0x2
1561          * Blank line end at line17/22
1562          * High bandwidth Luma Filter
1563          * Low bandwidth Chroma Filter
1564          * Bypass luma low pass filter
1565          * No macrovision on CSYNC
1566          */
1567         writel_relaxed(0x26, priv->io_base + _REG(ENCI_VIDEO_MODE_ADV));
1568
1569         writel(mode->sch_adjust, priv->io_base + _REG(ENCI_VIDEO_SCH));
1570
1571         /* Sync mode : MASTER Master mode, free run, send HSO/VSO out */
1572         writel_relaxed(0x07, priv->io_base + _REG(ENCI_SYNC_MODE));
1573
1574         /* 0x3 Y, C, and Component Y delay */
1575         writel_relaxed(mode->yc_delay, priv->io_base + _REG(ENCI_YC_DELAY));
1576
1577         /* Timings */
1578         writel_relaxed(mode->pixel_start,
1579                         priv->io_base + _REG(ENCI_VFIFO2VD_PIXEL_START));
1580         writel_relaxed(mode->pixel_end,
1581                         priv->io_base + _REG(ENCI_VFIFO2VD_PIXEL_END));
1582
1583         writel_relaxed(mode->top_field_line_start,
1584                         priv->io_base + _REG(ENCI_VFIFO2VD_LINE_TOP_START));
1585         writel_relaxed(mode->top_field_line_end,
1586                         priv->io_base + _REG(ENCI_VFIFO2VD_LINE_TOP_END));
1587
1588         writel_relaxed(mode->bottom_field_line_start,
1589                         priv->io_base + _REG(ENCI_VFIFO2VD_LINE_BOT_START));
1590         writel_relaxed(mode->bottom_field_line_end,
1591                         priv->io_base + _REG(ENCI_VFIFO2VD_LINE_BOT_END));
1592
1593         /* Internal Venc, Internal VIU Sync, Internal Vencoder */
1594         writel_relaxed(0, priv->io_base + _REG(VENC_SYNC_ROUTE));
1595
1596         /* UNreset Interlaced TV Encoder */
1597         writel_relaxed(0, priv->io_base + _REG(ENCI_DBG_PX_RST));
1598
1599         /* Enable Vfifo2vd, Y_Cb_Y_Cr select */
1600         writel_relaxed(0x4e01, priv->io_base + _REG(ENCI_VFIFO2VD_CTL));
1601
1602         /* Power UP Dacs */
1603         writel_relaxed(0, priv->io_base + _REG(VENC_VDAC_SETTING));
1604
1605         /* Video Upsampling */
1606         writel_relaxed(0x0061, priv->io_base + _REG(VENC_UPSAMPLE_CTRL0));
1607         writel_relaxed(0x4061, priv->io_base + _REG(VENC_UPSAMPLE_CTRL1));
1608         writel_relaxed(0x5061, priv->io_base + _REG(VENC_UPSAMPLE_CTRL2));
1609
1610         /* Select Interlace Y DACs */
1611         writel_relaxed(0, priv->io_base + _REG(VENC_VDAC_DACSEL0));
1612         writel_relaxed(0, priv->io_base + _REG(VENC_VDAC_DACSEL1));
1613         writel_relaxed(0, priv->io_base + _REG(VENC_VDAC_DACSEL2));
1614         writel_relaxed(0, priv->io_base + _REG(VENC_VDAC_DACSEL3));
1615         writel_relaxed(0, priv->io_base + _REG(VENC_VDAC_DACSEL4));
1616         writel_relaxed(0, priv->io_base + _REG(VENC_VDAC_DACSEL5));
1617
1618         /* Select ENCI for VIU */
1619         meson_vpp_setup_mux(priv, MESON_VIU_VPP_MUX_ENCI);
1620
1621         /* Enable ENCI FIFO */
1622         writel_relaxed(0x2000, priv->io_base + _REG(VENC_VDAC_FIFO_CTRL));
1623
1624         /* Select ENCI DACs 0, 1, 4, and 5 */
1625         writel_relaxed(0x11, priv->io_base + _REG(ENCI_DACSEL_0));
1626         writel_relaxed(0x11, priv->io_base + _REG(ENCI_DACSEL_1));
1627
1628         /* Interlace video enable */
1629         writel_relaxed(1, priv->io_base + _REG(ENCI_VIDEO_EN));
1630
1631         /* Configure Video Saturation / Contrast / Brightness / Hue */
1632         writel_relaxed(mode->video_saturation,
1633                         priv->io_base + _REG(ENCI_VIDEO_SAT));
1634         writel_relaxed(mode->video_contrast,
1635                         priv->io_base + _REG(ENCI_VIDEO_CONT));
1636         writel_relaxed(mode->video_brightness,
1637                         priv->io_base + _REG(ENCI_VIDEO_BRIGHT));
1638         writel_relaxed(mode->video_hue,
1639                         priv->io_base + _REG(ENCI_VIDEO_HUE));
1640
1641         /* Enable DAC0 Filter */
1642         writel_relaxed(0x1, priv->io_base + _REG(VENC_VDAC_DAC0_FILT_CTRL0));
1643         writel_relaxed(0xfc48, priv->io_base + _REG(VENC_VDAC_DAC0_FILT_CTRL1));
1644
1645         /* 0 in Macrovision register 0 */
1646         writel_relaxed(0, priv->io_base + _REG(ENCI_MACV_N0));
1647
1648         /* Analog Synchronization and color burst value adjust */
1649         writel_relaxed(mode->analog_sync_adj,
1650                         priv->io_base + _REG(ENCI_SYNC_ADJ));
1651
1652         priv->venc.current_mode = mode->mode_tag;
1653 }
1654
1655 /* Returns the current ENCI field polarity */
1656 unsigned int meson_venci_get_field(struct meson_drm *priv)
1657 {
1658         return readl_relaxed(priv->io_base + _REG(ENCI_INFO_READ)) & BIT(29);
1659 }
1660
1661 void meson_venc_enable_vsync(struct meson_drm *priv)
1662 {
1663         writel_relaxed(2, priv->io_base + _REG(VENC_INTCTRL));
1664         regmap_update_bits(priv->hhi, HHI_GCLK_MPEG2, BIT(25), BIT(25));
1665 }
1666
1667 void meson_venc_disable_vsync(struct meson_drm *priv)
1668 {
1669         regmap_update_bits(priv->hhi, HHI_GCLK_MPEG2, BIT(25), 0);
1670         writel_relaxed(0, priv->io_base + _REG(VENC_INTCTRL));
1671 }
1672
1673 void meson_venc_init(struct meson_drm *priv)
1674 {
1675         /* Disable CVBS VDAC */
1676         regmap_write(priv->hhi, HHI_VDAC_CNTL0, 0);
1677         regmap_write(priv->hhi, HHI_VDAC_CNTL1, 8);
1678
1679         /* Power Down Dacs */
1680         writel_relaxed(0xff, priv->io_base + _REG(VENC_VDAC_SETTING));
1681
1682         /* Disable HDMI PHY */
1683         regmap_write(priv->hhi, HHI_HDMI_PHY_CNTL0, 0);
1684
1685         /* Disable HDMI */
1686         writel_bits_relaxed(0x3, 0,
1687                             priv->io_base + _REG(VPU_HDMI_SETTING));
1688
1689         /* Disable all encoders */
1690         writel_relaxed(0, priv->io_base + _REG(ENCI_VIDEO_EN));
1691         writel_relaxed(0, priv->io_base + _REG(ENCP_VIDEO_EN));
1692         writel_relaxed(0, priv->io_base + _REG(ENCL_VIDEO_EN));
1693
1694         /* Disable VSync IRQ */
1695         meson_venc_disable_vsync(priv);
1696
1697         priv->venc.current_mode = MESON_VENC_MODE_NONE;
1698 }