drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c

   1 /*
   2  * Copyright 2017 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: Rafał Miłecki <[email protected]>
  23  *          Alex Deucher <[email protected]>
  24  */
  25 #include <drm/drmP.h>
  26 #include "amdgpu.h"
  27 #include "amdgpu_drv.h"
  28 #include "amdgpu_pm.h"
  29 #include "amdgpu_dpm.h"
  30 #include "atom.h"
  31 #include <linux/power_supply.h>
  32 #include <linux/hwmon.h>
  33 #include <linux/hwmon-sysfs.h>
  34
  35
  36 static int amdgpu_debugfs_pm_init(struct amdgpu_device *adev);
  37
  38 static const struct cg_flag_name clocks[] = {
  39         {AMD_CG_SUPPORT_GFX_MGCG, "Graphics Medium Grain Clock Gating"},
  40         {AMD_CG_SUPPORT_GFX_MGLS, "Graphics Medium Grain memory Light Sleep"},
  41         {AMD_CG_SUPPORT_GFX_CGCG, "Graphics Coarse Grain Clock Gating"},
  42         {AMD_CG_SUPPORT_GFX_CGLS, "Graphics Coarse Grain memory Light Sleep"},
  43         {AMD_CG_SUPPORT_GFX_CGTS, "Graphics Coarse Grain Tree Shader Clock Gating"},
  44         {AMD_CG_SUPPORT_GFX_CGTS_LS, "Graphics Coarse Grain Tree Shader Light Sleep"},
  45         {AMD_CG_SUPPORT_GFX_CP_LS, "Graphics Command Processor Light Sleep"},
  46         {AMD_CG_SUPPORT_GFX_RLC_LS, "Graphics Run List Controller Light Sleep"},
  47         {AMD_CG_SUPPORT_GFX_3D_CGCG, "Graphics 3D Coarse Grain Clock Gating"},
  48         {AMD_CG_SUPPORT_GFX_3D_CGLS, "Graphics 3D Coarse Grain memory Light Sleep"},
  49         {AMD_CG_SUPPORT_MC_LS, "Memory Controller Light Sleep"},
  50         {AMD_CG_SUPPORT_MC_MGCG, "Memory Controller Medium Grain Clock Gating"},
  51         {AMD_CG_SUPPORT_SDMA_LS, "System Direct Memory Access Light Sleep"},
  52         {AMD_CG_SUPPORT_SDMA_MGCG, "System Direct Memory Access Medium Grain Clock Gating"},
  53         {AMD_CG_SUPPORT_BIF_MGCG, "Bus Interface Medium Grain Clock Gating"},
  54         {AMD_CG_SUPPORT_BIF_LS, "Bus Interface Light Sleep"},
  55         {AMD_CG_SUPPORT_UVD_MGCG, "Unified Video Decoder Medium Grain Clock Gating"},
  56         {AMD_CG_SUPPORT_VCE_MGCG, "Video Compression Engine Medium Grain Clock Gating"},
  57         {AMD_CG_SUPPORT_HDP_LS, "Host Data Path Light Sleep"},
  58         {AMD_CG_SUPPORT_HDP_MGCG, "Host Data Path Medium Grain Clock Gating"},
  59         {AMD_CG_SUPPORT_DRM_MGCG, "Digital Right Management Medium Grain Clock Gating"},
  60         {AMD_CG_SUPPORT_DRM_LS, "Digital Right Management Light Sleep"},
  61         {AMD_CG_SUPPORT_ROM_MGCG, "Rom Medium Grain Clock Gating"},
  62         {AMD_CG_SUPPORT_DF_MGCG, "Data Fabric Medium Grain Clock Gating"},
  63         {0, NULL},
  64 };
  65
  66 void amdgpu_pm_acpi_event_handler(struct amdgpu_device *adev)
  67 {
  68         if (adev->pm.dpm_enabled) {
  69                 mutex_lock(&adev->pm.mutex);
  70                 if (power_supply_is_system_supplied() > 0)
  71                         adev->pm.dpm.ac_power = true;
  72                 else
  73                         adev->pm.dpm.ac_power = false;
  74                 if (adev->powerplay.pp_funcs->enable_bapm)
  75                         amdgpu_dpm_enable_bapm(adev, adev->pm.dpm.ac_power);
  76                 mutex_unlock(&adev->pm.mutex);
  77         }
  78 }
  79
  80 static ssize_t amdgpu_get_dpm_state(struct device *dev,
  81                                     struct device_attribute *attr,
  82                                     char *buf)
  83 {
  84         struct drm_device *ddev = dev_get_drvdata(dev);
  85         struct amdgpu_device *adev = ddev->dev_private;
  86         enum amd_pm_state_type pm;
  87
  88         if (adev->powerplay.pp_funcs->get_current_power_state)
  89                 pm = amdgpu_dpm_get_current_power_state(adev);
  90         else
  91                 pm = adev->pm.dpm.user_state;
  92
  93         return snprintf(buf, PAGE_SIZE, "%s\n",
  94                         (pm == POWER_STATE_TYPE_BATTERY) ? "battery" :
  95                         (pm == POWER_STATE_TYPE_BALANCED) ? "balanced" : "performance");
  96 }
  97
  98 static ssize_t amdgpu_set_dpm_state(struct device *dev,
  99                                     struct device_attribute *attr,
 100                                     const char *buf,
 101                                     size_t count)
 102 {
 103         struct drm_device *ddev = dev_get_drvdata(dev);
 104         struct amdgpu_device *adev = ddev->dev_private;
 105         enum amd_pm_state_type  state;
 106
 107         if (strncmp("battery", buf, strlen("battery")) == 0)
 108                 state = POWER_STATE_TYPE_BATTERY;
 109         else if (strncmp("balanced", buf, strlen("balanced")) == 0)
 110                 state = POWER_STATE_TYPE_BALANCED;
 111         else if (strncmp("performance", buf, strlen("performance")) == 0)
 112                 state = POWER_STATE_TYPE_PERFORMANCE;
 113         else {
 114                 count = -EINVAL;
 115                 goto fail;
 116         }
 117
 118         if (adev->powerplay.pp_funcs->dispatch_tasks) {
 119                 amdgpu_dpm_dispatch_task(adev, AMD_PP_TASK_ENABLE_USER_STATE, &state);
 120         } else {
 121                 mutex_lock(&adev->pm.mutex);
 122                 adev->pm.dpm.user_state = state;
 123                 mutex_unlock(&adev->pm.mutex);
 124
 125                 /* Can't set dpm state when the card is off */
 126                 if (!(adev->flags & AMD_IS_PX) ||
 127                     (ddev->switch_power_state == DRM_SWITCH_POWER_ON))
 128                         amdgpu_pm_compute_clocks(adev);
 129         }
 130 fail:
 131         return count;
 132 }
 133
 134 static ssize_t amdgpu_get_dpm_forced_performance_level(struct device *dev,
 135                                                 struct device_attribute *attr,
 136                                                                 char *buf)
 137 {
 138         struct drm_device *ddev = dev_get_drvdata(dev);
 139         struct amdgpu_device *adev = ddev->dev_private;
 140         enum amd_dpm_forced_level level = 0xff;
 141
 142         if  ((adev->flags & AMD_IS_PX) &&
 143              (ddev->switch_power_state != DRM_SWITCH_POWER_ON))
 144                 return snprintf(buf, PAGE_SIZE, "off\n");
 145
 146         if (adev->powerplay.pp_funcs->get_performance_level)
 147                 level = amdgpu_dpm_get_performance_level(adev);
 148         else
 149                 level = adev->pm.dpm.forced_level;
 150
 151         return snprintf(buf, PAGE_SIZE, "%s\n",
 152                         (level == AMD_DPM_FORCED_LEVEL_AUTO) ? "auto" :
 153                         (level == AMD_DPM_FORCED_LEVEL_LOW) ? "low" :
 154                         (level == AMD_DPM_FORCED_LEVEL_HIGH) ? "high" :
 155                         (level == AMD_DPM_FORCED_LEVEL_MANUAL) ? "manual" :
 156                         (level == AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD) ? "profile_standard" :
 157                         (level == AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK) ? "profile_min_sclk" :
 158                         (level == AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK) ? "profile_min_mclk" :
 159                         (level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK) ? "profile_peak" :
 160                         "unknown");
 161 }
 162
 163 static ssize_t amdgpu_set_dpm_forced_performance_level(struct device *dev,
 164                                                        struct device_attribute *attr,
 165                                                        const char *buf,
 166                                                        size_t count)
 167 {
 168         struct drm_device *ddev = dev_get_drvdata(dev);
 169         struct amdgpu_device *adev = ddev->dev_private;
 170         enum amd_dpm_forced_level level;
 171         enum amd_dpm_forced_level current_level = 0xff;
 172         int ret = 0;
 173
 174         /* Can't force performance level when the card is off */
 175         if  ((adev->flags & AMD_IS_PX) &&
 176              (ddev->switch_power_state != DRM_SWITCH_POWER_ON))
 177                 return -EINVAL;
 178
 179         if (adev->powerplay.pp_funcs->get_performance_level)
 180                 current_level = amdgpu_dpm_get_performance_level(adev);
 181
 182         if (strncmp("low", buf, strlen("low")) == 0) {
 183                 level = AMD_DPM_FORCED_LEVEL_LOW;
 184         } else if (strncmp("high", buf, strlen("high")) == 0) {
 185                 level = AMD_DPM_FORCED_LEVEL_HIGH;
 186         } else if (strncmp("auto", buf, strlen("auto")) == 0) {
 187                 level = AMD_DPM_FORCED_LEVEL_AUTO;
 188         } else if (strncmp("manual", buf, strlen("manual")) == 0) {
 189                 level = AMD_DPM_FORCED_LEVEL_MANUAL;
 190         } else if (strncmp("profile_exit", buf, strlen("profile_exit")) == 0) {
 191                 level = AMD_DPM_FORCED_LEVEL_PROFILE_EXIT;
 192         } else if (strncmp("profile_standard", buf, strlen("profile_standard")) == 0) {
 193                 level = AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD;
 194         } else if (strncmp("profile_min_sclk", buf, strlen("profile_min_sclk")) == 0) {
 195                 level = AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK;
 196         } else if (strncmp("profile_min_mclk", buf, strlen("profile_min_mclk")) == 0) {
 197                 level = AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK;
 198         } else if (strncmp("profile_peak", buf, strlen("profile_peak")) == 0) {
 199                 level = AMD_DPM_FORCED_LEVEL_PROFILE_PEAK;
 200         }  else {
 201                 count = -EINVAL;
 202                 goto fail;
 203         }
 204
 205         if (current_level == level)
 206                 return count;
 207
 208         if (adev->powerplay.pp_funcs->force_performance_level) {
 209                 mutex_lock(&adev->pm.mutex);
 210                 if (adev->pm.dpm.thermal_active) {
 211                         count = -EINVAL;
 212                         mutex_unlock(&adev->pm.mutex);
 213                         goto fail;
 214                 }
 215                 ret = amdgpu_dpm_force_performance_level(adev, level);
 216                 if (ret)
 217                         count = -EINVAL;
 218                 else
 219                         adev->pm.dpm.forced_level = level;
 220                 mutex_unlock(&adev->pm.mutex);
 221         }
 222
 223 fail:
 224         return count;
 225 }
 226
 227 static ssize_t amdgpu_get_pp_num_states(struct device *dev,
 228                 struct device_attribute *attr,
 229                 char *buf)
 230 {
 231         struct drm_device *ddev = dev_get_drvdata(dev);
 232         struct amdgpu_device *adev = ddev->dev_private;
 233         struct pp_states_info data;
 234         int i, buf_len;
 235
 236         if (adev->powerplay.pp_funcs->get_pp_num_states)
 237                 amdgpu_dpm_get_pp_num_states(adev, &data);
 238
 239         buf_len = snprintf(buf, PAGE_SIZE, "states: %d\n", data.nums);
 240         for (i = 0; i < data.nums; i++)
 241                 buf_len += snprintf(buf + buf_len, PAGE_SIZE, "%d %s\n", i,
 242                                 (data.states[i] == POWER_STATE_TYPE_INTERNAL_BOOT) ? "boot" :
 243                                 (data.states[i] == POWER_STATE_TYPE_BATTERY) ? "battery" :
 244                                 (data.states[i] == POWER_STATE_TYPE_BALANCED) ? "balanced" :
 245                                 (data.states[i] == POWER_STATE_TYPE_PERFORMANCE) ? "performance" : "default");
 246
 247         return buf_len;
 248 }
 249
 250 static ssize_t amdgpu_get_pp_cur_state(struct device *dev,
 251                 struct device_attribute *attr,
 252                 char *buf)
 253 {
 254         struct drm_device *ddev = dev_get_drvdata(dev);
 255         struct amdgpu_device *adev = ddev->dev_private;
 256         struct pp_states_info data;
 257         enum amd_pm_state_type pm = 0;
 258         int i = 0;
 259
 260         if (adev->powerplay.pp_funcs->get_current_power_state
 261                  && adev->powerplay.pp_funcs->get_pp_num_states) {
 262                 pm = amdgpu_dpm_get_current_power_state(adev);
 263                 amdgpu_dpm_get_pp_num_states(adev, &data);
 264
 265                 for (i = 0; i < data.nums; i++) {
 266                         if (pm == data.states[i])
 267                                 break;
 268                 }
 269
 270                 if (i == data.nums)
 271                         i = -EINVAL;
 272         }
 273
 274         return snprintf(buf, PAGE_SIZE, "%d\n", i);
 275 }
 276
 277 static ssize_t amdgpu_get_pp_force_state(struct device *dev,
 278                 struct device_attribute *attr,
 279                 char *buf)
 280 {
 281         struct drm_device *ddev = dev_get_drvdata(dev);
 282         struct amdgpu_device *adev = ddev->dev_private;
 283
 284         if (adev->pp_force_state_enabled)
 285                 return amdgpu_get_pp_cur_state(dev, attr, buf);
 286         else
 287                 return snprintf(buf, PAGE_SIZE, "\n");
 288 }
 289
 290 static ssize_t amdgpu_set_pp_force_state(struct device *dev,
 291                 struct device_attribute *attr,
 292                 const char *buf,
 293                 size_t count)
 294 {
 295         struct drm_device *ddev = dev_get_drvdata(dev);
 296         struct amdgpu_device *adev = ddev->dev_private;
 297         enum amd_pm_state_type state = 0;
 298         unsigned long idx;
 299         int ret;
 300
 301         if (strlen(buf) == 1)
 302                 adev->pp_force_state_enabled = false;
 303         else if (adev->powerplay.pp_funcs->dispatch_tasks &&
 304                         adev->powerplay.pp_funcs->get_pp_num_states) {
 305                 struct pp_states_info data;
 306
 307                 ret = kstrtoul(buf, 0, &idx);
 308                 if (ret || idx >= ARRAY_SIZE(data.states)) {
 309                         count = -EINVAL;
 310                         goto fail;
 311                 }
 312
 313                 amdgpu_dpm_get_pp_num_states(adev, &data);
 314                 state = data.states[idx];
 315                 /* only set user selected power states */
 316                 if (state != POWER_STATE_TYPE_INTERNAL_BOOT &&
 317                     state != POWER_STATE_TYPE_DEFAULT) {
 318                         amdgpu_dpm_dispatch_task(adev,
 319                                         AMD_PP_TASK_ENABLE_USER_STATE, &state);
 320                         adev->pp_force_state_enabled = true;
 321                 }
 322         }
 323 fail:
 324         return count;
 325 }
 326
 327 static ssize_t amdgpu_get_pp_table(struct device *dev,
 328                 struct device_attribute *attr,
 329                 char *buf)
 330 {
 331         struct drm_device *ddev = dev_get_drvdata(dev);
 332         struct amdgpu_device *adev = ddev->dev_private;
 333         char *table = NULL;
 334         int size;
 335
 336         if (adev->powerplay.pp_funcs->get_pp_table)
 337                 size = amdgpu_dpm_get_pp_table(adev, &table);
 338         else
 339                 return 0;
 340
 341         if (size >= PAGE_SIZE)
 342                 size = PAGE_SIZE - 1;
 343
 344         memcpy(buf, table, size);
 345
 346         return size;
 347 }
 348
 349 static ssize_t amdgpu_set_pp_table(struct device *dev,
 350                 struct device_attribute *attr,
 351                 const char *buf,
 352                 size_t count)
 353 {
 354         struct drm_device *ddev = dev_get_drvdata(dev);
 355         struct amdgpu_device *adev = ddev->dev_private;
 356
 357         if (adev->powerplay.pp_funcs->set_pp_table)
 358                 amdgpu_dpm_set_pp_table(adev, buf, count);
 359
 360         return count;
 361 }
 362
 363 static ssize_t amdgpu_set_pp_od_clk_voltage(struct device *dev,
 364                 struct device_attribute *attr,
 365                 const char *buf,
 366                 size_t count)
 367 {
 368         struct drm_device *ddev = dev_get_drvdata(dev);
 369         struct amdgpu_device *adev = ddev->dev_private;
 370         int ret;
 371         uint32_t parameter_size = 0;
 372         long parameter[64];
 373         char buf_cpy[128];
 374         char *tmp_str;
 375         char *sub_str;
 376         const char delimiter[3] = {' ', '\n', '\0'};
 377         uint32_t type;
 378
 379         if (count > 127)
 380                 return -EINVAL;
 381
 382         if (*buf == 's')
 383                 type = PP_OD_EDIT_SCLK_VDDC_TABLE;
 384         else if (*buf == 'm')
 385                 type = PP_OD_EDIT_MCLK_VDDC_TABLE;
 386         else if(*buf == 'r')
 387                 type = PP_OD_RESTORE_DEFAULT_TABLE;
 388         else if (*buf == 'c')
 389                 type = PP_OD_COMMIT_DPM_TABLE;
 390         else
 391                 return -EINVAL;
 392
 393         memcpy(buf_cpy, buf, count+1);
 394
 395         tmp_str = buf_cpy;
 396
 397         while (isspace(*++tmp_str));
 398
 399         while (tmp_str[0]) {
 400                 sub_str = strsep(&tmp_str, delimiter);
 401                 ret = kstrtol(sub_str, 0, &parameter[parameter_size]);
 402                 if (ret)
 403                         return -EINVAL;
 404                 parameter_size++;
 405
 406                 while (isspace(*tmp_str))
 407                         tmp_str++;
 408         }
 409
 410         if (adev->powerplay.pp_funcs->odn_edit_dpm_table)
 411                 ret = amdgpu_dpm_odn_edit_dpm_table(adev, type,
 412                                                 parameter, parameter_size);
 413
 414         if (ret)
 415                 return -EINVAL;
 416
 417         if (type == PP_OD_COMMIT_DPM_TABLE) {
 418                 if (adev->powerplay.pp_funcs->dispatch_tasks) {
 419                         amdgpu_dpm_dispatch_task(adev, AMD_PP_TASK_READJUST_POWER_STATE, NULL);
 420                         return count;
 421                 } else {
 422                         return -EINVAL;
 423                 }
 424         }
 425
 426         return count;
 427 }
 428
 429 static ssize_t amdgpu_get_pp_od_clk_voltage(struct device *dev,
 430                 struct device_attribute *attr,
 431                 char *buf)
 432 {
 433         struct drm_device *ddev = dev_get_drvdata(dev);
 434         struct amdgpu_device *adev = ddev->dev_private;
 435         uint32_t size = 0;
 436
 437         if (adev->powerplay.pp_funcs->print_clock_levels) {
 438                 size = amdgpu_dpm_print_clock_levels(adev, OD_SCLK, buf);
 439                 size += amdgpu_dpm_print_clock_levels(adev, OD_MCLK, buf+size);
 440                 return size;
 441         } else {
 442                 return snprintf(buf, PAGE_SIZE, "\n");
 443         }
 444
 445 }
 446
 447 static ssize_t amdgpu_get_pp_dpm_sclk(struct device *dev,
 448                 struct device_attribute *attr,
 449                 char *buf)
 450 {
 451         struct drm_device *ddev = dev_get_drvdata(dev);
 452         struct amdgpu_device *adev = ddev->dev_private;
 453
 454         if (adev->powerplay.pp_funcs->print_clock_levels)
 455                 return amdgpu_dpm_print_clock_levels(adev, PP_SCLK, buf);
 456         else
 457                 return snprintf(buf, PAGE_SIZE, "\n");
 458 }
 459
 460 static ssize_t amdgpu_set_pp_dpm_sclk(struct device *dev,
 461                 struct device_attribute *attr,
 462                 const char *buf,
 463                 size_t count)
 464 {
 465         struct drm_device *ddev = dev_get_drvdata(dev);
 466         struct amdgpu_device *adev = ddev->dev_private;
 467         int ret;
 468         long level;
 469         uint32_t i, mask = 0;
 470         char sub_str[2];
 471
 472         for (i = 0; i < strlen(buf); i++) {
 473                 if (*(buf + i) == '\n')
 474                         continue;
 475                 sub_str[0] = *(buf + i);
 476                 sub_str[1] = '\0';
 477                 ret = kstrtol(sub_str, 0, &level);
 478
 479                 if (ret) {
 480                         count = -EINVAL;
 481                         goto fail;
 482                 }
 483                 mask |= 1 << level;
 484         }
 485
 486         if (adev->powerplay.pp_funcs->force_clock_level)
 487                 amdgpu_dpm_force_clock_level(adev, PP_SCLK, mask);
 488
 489 fail:
 490         return count;
 491 }
 492
 493 static ssize_t amdgpu_get_pp_dpm_mclk(struct device *dev,
 494                 struct device_attribute *attr,
 495                 char *buf)
 496 {
 497         struct drm_device *ddev = dev_get_drvdata(dev);
 498         struct amdgpu_device *adev = ddev->dev_private;
 499
 500         if (adev->powerplay.pp_funcs->print_clock_levels)
 501                 return amdgpu_dpm_print_clock_levels(adev, PP_MCLK, buf);
 502         else
 503                 return snprintf(buf, PAGE_SIZE, "\n");
 504 }
 505
 506 static ssize_t amdgpu_set_pp_dpm_mclk(struct device *dev,
 507                 struct device_attribute *attr,
 508                 const char *buf,
 509                 size_t count)
 510 {
 511         struct drm_device *ddev = dev_get_drvdata(dev);
 512         struct amdgpu_device *adev = ddev->dev_private;
 513         int ret;
 514         long level;
 515         uint32_t i, mask = 0;
 516         char sub_str[2];
 517
 518         for (i = 0; i < strlen(buf); i++) {
 519                 if (*(buf + i) == '\n')
 520                         continue;
 521                 sub_str[0] = *(buf + i);
 522                 sub_str[1] = '\0';
 523                 ret = kstrtol(sub_str, 0, &level);
 524
 525                 if (ret) {
 526                         count = -EINVAL;
 527                         goto fail;
 528                 }
 529                 mask |= 1 << level;
 530         }
 531         if (adev->powerplay.pp_funcs->force_clock_level)
 532                 amdgpu_dpm_force_clock_level(adev, PP_MCLK, mask);
 533
 534 fail:
 535         return count;
 536 }
 537
 538 static ssize_t amdgpu_get_pp_dpm_pcie(struct device *dev,
 539                 struct device_attribute *attr,
 540                 char *buf)
 541 {
 542         struct drm_device *ddev = dev_get_drvdata(dev);
 543         struct amdgpu_device *adev = ddev->dev_private;
 544
 545         if (adev->powerplay.pp_funcs->print_clock_levels)
 546                 return amdgpu_dpm_print_clock_levels(adev, PP_PCIE, buf);
 547         else
 548                 return snprintf(buf, PAGE_SIZE, "\n");
 549 }
 550
 551 static ssize_t amdgpu_set_pp_dpm_pcie(struct device *dev,
 552                 struct device_attribute *attr,
 553                 const char *buf,
 554                 size_t count)
 555 {
 556         struct drm_device *ddev = dev_get_drvdata(dev);
 557         struct amdgpu_device *adev = ddev->dev_private;
 558         int ret;
 559         long level;
 560         uint32_t i, mask = 0;
 561         char sub_str[2];
 562
 563         for (i = 0; i < strlen(buf); i++) {
 564                 if (*(buf + i) == '\n')
 565                         continue;
 566                 sub_str[0] = *(buf + i);
 567                 sub_str[1] = '\0';
 568                 ret = kstrtol(sub_str, 0, &level);
 569
 570                 if (ret) {
 571                         count = -EINVAL;
 572                         goto fail;
 573                 }
 574                 mask |= 1 << level;
 575         }
 576         if (adev->powerplay.pp_funcs->force_clock_level)
 577                 amdgpu_dpm_force_clock_level(adev, PP_PCIE, mask);
 578
 579 fail:
 580         return count;
 581 }
 582
 583 static ssize_t amdgpu_get_pp_sclk_od(struct device *dev,
 584                 struct device_attribute *attr,
 585                 char *buf)
 586 {
 587         struct drm_device *ddev = dev_get_drvdata(dev);
 588         struct amdgpu_device *adev = ddev->dev_private;
 589         uint32_t value = 0;
 590
 591         if (adev->powerplay.pp_funcs->get_sclk_od)
 592                 value = amdgpu_dpm_get_sclk_od(adev);
 593
 594         return snprintf(buf, PAGE_SIZE, "%d\n", value);
 595 }
 596
 597 static ssize_t amdgpu_set_pp_sclk_od(struct device *dev,
 598                 struct device_attribute *attr,
 599                 const char *buf,
 600                 size_t count)
 601 {
 602         struct drm_device *ddev = dev_get_drvdata(dev);
 603         struct amdgpu_device *adev = ddev->dev_private;
 604         int ret;
 605         long int value;
 606
 607         ret = kstrtol(buf, 0, &value);
 608
 609         if (ret) {
 610                 count = -EINVAL;
 611                 goto fail;
 612         }
 613         if (adev->powerplay.pp_funcs->set_sclk_od)
 614                 amdgpu_dpm_set_sclk_od(adev, (uint32_t)value);
 615
 616         if (adev->powerplay.pp_funcs->dispatch_tasks) {
 617                 amdgpu_dpm_dispatch_task(adev, AMD_PP_TASK_READJUST_POWER_STATE, NULL);
 618         } else {
 619                 adev->pm.dpm.current_ps = adev->pm.dpm.boot_ps;
 620                 amdgpu_pm_compute_clocks(adev);
 621         }
 622
 623 fail:
 624         return count;
 625 }
 626
 627 static ssize_t amdgpu_get_pp_mclk_od(struct device *dev,
 628                 struct device_attribute *attr,
 629                 char *buf)
 630 {
 631         struct drm_device *ddev = dev_get_drvdata(dev);
 632         struct amdgpu_device *adev = ddev->dev_private;
 633         uint32_t value = 0;
 634
 635         if (adev->powerplay.pp_funcs->get_mclk_od)
 636                 value = amdgpu_dpm_get_mclk_od(adev);
 637
 638         return snprintf(buf, PAGE_SIZE, "%d\n", value);
 639 }
 640
 641 static ssize_t amdgpu_set_pp_mclk_od(struct device *dev,
 642                 struct device_attribute *attr,
 643                 const char *buf,
 644                 size_t count)
 645 {
 646         struct drm_device *ddev = dev_get_drvdata(dev);
 647         struct amdgpu_device *adev = ddev->dev_private;
 648         int ret;
 649         long int value;
 650
 651         ret = kstrtol(buf, 0, &value);
 652
 653         if (ret) {
 654                 count = -EINVAL;
 655                 goto fail;
 656         }
 657         if (adev->powerplay.pp_funcs->set_mclk_od)
 658                 amdgpu_dpm_set_mclk_od(adev, (uint32_t)value);
 659
 660         if (adev->powerplay.pp_funcs->dispatch_tasks) {
 661                 amdgpu_dpm_dispatch_task(adev, AMD_PP_TASK_READJUST_POWER_STATE, NULL);
 662         } else {
 663                 adev->pm.dpm.current_ps = adev->pm.dpm.boot_ps;
 664                 amdgpu_pm_compute_clocks(adev);
 665         }
 666
 667 fail:
 668         return count;
 669 }
 670
 671 static ssize_t amdgpu_get_pp_power_profile_mode(struct device *dev,
 672                 struct device_attribute *attr,
 673                 char *buf)
 674 {
 675         struct drm_device *ddev = dev_get_drvdata(dev);
 676         struct amdgpu_device *adev = ddev->dev_private;
 677
 678         if (adev->powerplay.pp_funcs->get_power_profile_mode)
 679                 return amdgpu_dpm_get_power_profile_mode(adev, buf);
 680
 681         return snprintf(buf, PAGE_SIZE, "\n");
 682 }
 683
 684
 685 static ssize_t amdgpu_set_pp_power_profile_mode(struct device *dev,
 686                 struct device_attribute *attr,
 687                 const char *buf,
 688                 size_t count)
 689 {
 690         int ret = 0xff;
 691         struct drm_device *ddev = dev_get_drvdata(dev);
 692         struct amdgpu_device *adev = ddev->dev_private;
 693         uint32_t parameter_size = 0;
 694         long parameter[64];
 695         char *sub_str, buf_cpy[128];
 696         char *tmp_str;
 697         uint32_t i = 0;
 698         char tmp[2];
 699         long int profile_mode = 0;
 700         const char delimiter[3] = {' ', '\n', '\0'};
 701
 702         tmp[0] = *(buf);
 703         tmp[1] = '\0';
 704         ret = kstrtol(tmp, 0, &profile_mode);
 705         if (ret)
 706                 goto fail;
 707
 708         if (profile_mode == PP_SMC_POWER_PROFILE_CUSTOM) {
 709                 if (count < 2 || count > 127)
 710                         return -EINVAL;
 711                 while (isspace(*++buf))
 712                         i++;
 713                 memcpy(buf_cpy, buf, count-i);
 714                 tmp_str = buf_cpy;
 715                 while (tmp_str[0]) {
 716                         sub_str = strsep(&tmp_str, delimiter);
 717                         ret = kstrtol(sub_str, 0, &parameter[parameter_size]);
 718                         if (ret) {
 719                                 count = -EINVAL;
 720                                 goto fail;
 721                         }
 722                         parameter_size++;
 723                         while (isspace(*tmp_str))
 724                                 tmp_str++;
 725                 }
 726         }
 727         parameter[parameter_size] = profile_mode;
 728         if (adev->powerplay.pp_funcs->set_power_profile_mode)
 729                 ret = amdgpu_dpm_set_power_profile_mode(adev, parameter, parameter_size);
 730
 731         if (!ret)
 732                 return count;
 733 fail:
 734         return -EINVAL;
 735 }
 736
 737 static ssize_t amdgpu_get_pp_power_profile(struct device *dev,
 738                 char *buf, struct amd_pp_profile *query)
 739 {
 740         struct drm_device *ddev = dev_get_drvdata(dev);
 741         struct amdgpu_device *adev = ddev->dev_private;
 742         int ret = 0xff;
 743
 744         if (adev->powerplay.pp_funcs->get_power_profile_state)
 745                 ret = amdgpu_dpm_get_power_profile_state(
 746                                 adev, query);
 747
 748         if (ret)
 749                 return ret;
 750
 751         return snprintf(buf, PAGE_SIZE,
 752                         "%d %d %d %d %d\n",
 753                         query->min_sclk / 100,
 754                         query->min_mclk / 100,
 755                         query->activity_threshold,
 756                         query->up_hyst,
 757                         query->down_hyst);
 758 }
 759
 760 static ssize_t amdgpu_get_pp_gfx_power_profile(struct device *dev,
 761                 struct device_attribute *attr,
 762                 char *buf)
 763 {
 764         struct amd_pp_profile query = {0};
 765
 766         query.type = AMD_PP_GFX_PROFILE;
 767
 768         return amdgpu_get_pp_power_profile(dev, buf, &query);
 769 }
 770
 771 static ssize_t amdgpu_get_pp_compute_power_profile(struct device *dev,
 772                 struct device_attribute *attr,
 773                 char *buf)
 774 {
 775         struct amd_pp_profile query = {0};
 776
 777         query.type = AMD_PP_COMPUTE_PROFILE;
 778
 779         return amdgpu_get_pp_power_profile(dev, buf, &query);
 780 }
 781
 782 static ssize_t amdgpu_set_pp_power_profile(struct device *dev,
 783                 const char *buf,
 784                 size_t count,
 785                 struct amd_pp_profile *request)
 786 {
 787         struct drm_device *ddev = dev_get_drvdata(dev);
 788         struct amdgpu_device *adev = ddev->dev_private;
 789         uint32_t loop = 0;
 790         char *sub_str, buf_cpy[128], *tmp_str;
 791         const char delimiter[3] = {' ', '\n', '\0'};
 792         long int value;
 793         int ret = 0xff;
 794
 795         if (strncmp("reset", buf, strlen("reset")) == 0) {
 796                 if (adev->powerplay.pp_funcs->reset_power_profile_state)
 797                         ret = amdgpu_dpm_reset_power_profile_state(
 798                                         adev, request);
 799                 if (ret) {
 800                         count = -EINVAL;
 801                         goto fail;
 802                 }
 803                 return count;
 804         }
 805
 806         if (strncmp("set", buf, strlen("set")) == 0) {
 807                 if (adev->powerplay.pp_funcs->set_power_profile_state)
 808                         ret = amdgpu_dpm_set_power_profile_state(
 809                                         adev, request);
 810
 811                 if (ret) {
 812                         count = -EINVAL;
 813                         goto fail;
 814                 }
 815                 return count;
 816         }
 817
 818         if (count + 1 >= 128) {
 819                 count = -EINVAL;
 820                 goto fail;
 821         }
 822
 823         memcpy(buf_cpy, buf, count + 1);
 824         tmp_str = buf_cpy;
 825
 826         while (tmp_str[0]) {
 827                 sub_str = strsep(&tmp_str, delimiter);
 828                 ret = kstrtol(sub_str, 0, &value);
 829                 if (ret) {
 830                         count = -EINVAL;
 831                         goto fail;
 832                 }
 833
 834                 switch (loop) {
 835                 case 0:
 836                         /* input unit MHz convert to dpm table unit 10KHz*/
 837                         request->min_sclk = (uint32_t)value * 100;
 838                         break;
 839                 case 1:
 840                         /* input unit MHz convert to dpm table unit 10KHz*/
 841                         request->min_mclk = (uint32_t)value * 100;
 842                         break;
 843                 case 2:
 844                         request->activity_threshold = (uint16_t)value;
 845                         break;
 846                 case 3:
 847                         request->up_hyst = (uint8_t)value;
 848                         break;
 849                 case 4:
 850                         request->down_hyst = (uint8_t)value;
 851                         break;
 852                 default:
 853                         break;
 854                 }
 855
 856                 loop++;
 857         }
 858         if (adev->powerplay.pp_funcs->set_power_profile_state)
 859                 ret = amdgpu_dpm_set_power_profile_state(adev, request);
 860
 861         if (ret)
 862                 count = -EINVAL;
 863
 864 fail:
 865         return count;
 866 }
 867
 868 static ssize_t amdgpu_set_pp_gfx_power_profile(struct device *dev,
 869                 struct device_attribute *attr,
 870                 const char *buf,
 871                 size_t count)
 872 {
 873         struct amd_pp_profile request = {0};
 874
 875         request.type = AMD_PP_GFX_PROFILE;
 876
 877         return amdgpu_set_pp_power_profile(dev, buf, count, &request);
 878 }
 879
 880 static ssize_t amdgpu_set_pp_compute_power_profile(struct device *dev,
 881                 struct device_attribute *attr,
 882                 const char *buf,
 883                 size_t count)
 884 {
 885         struct amd_pp_profile request = {0};
 886
 887         request.type = AMD_PP_COMPUTE_PROFILE;
 888
 889         return amdgpu_set_pp_power_profile(dev, buf, count, &request);
 890 }
 891
 892 static DEVICE_ATTR(power_dpm_state, S_IRUGO | S_IWUSR, amdgpu_get_dpm_state, amdgpu_set_dpm_state);
 893 static DEVICE_ATTR(power_dpm_force_performance_level, S_IRUGO | S_IWUSR,
 894                    amdgpu_get_dpm_forced_performance_level,
 895                    amdgpu_set_dpm_forced_performance_level);
 896 static DEVICE_ATTR(pp_num_states, S_IRUGO, amdgpu_get_pp_num_states, NULL);
 897 static DEVICE_ATTR(pp_cur_state, S_IRUGO, amdgpu_get_pp_cur_state, NULL);
 898 static DEVICE_ATTR(pp_force_state, S_IRUGO | S_IWUSR,
 899                 amdgpu_get_pp_force_state,
 900                 amdgpu_set_pp_force_state);
 901 static DEVICE_ATTR(pp_table, S_IRUGO | S_IWUSR,
 902                 amdgpu_get_pp_table,
 903                 amdgpu_set_pp_table);
 904 static DEVICE_ATTR(pp_dpm_sclk, S_IRUGO | S_IWUSR,
 905                 amdgpu_get_pp_dpm_sclk,
 906                 amdgpu_set_pp_dpm_sclk);
 907 static DEVICE_ATTR(pp_dpm_mclk, S_IRUGO | S_IWUSR,
 908                 amdgpu_get_pp_dpm_mclk,
 909                 amdgpu_set_pp_dpm_mclk);
 910 static DEVICE_ATTR(pp_dpm_pcie, S_IRUGO | S_IWUSR,
 911                 amdgpu_get_pp_dpm_pcie,
 912                 amdgpu_set_pp_dpm_pcie);
 913 static DEVICE_ATTR(pp_sclk_od, S_IRUGO | S_IWUSR,
 914                 amdgpu_get_pp_sclk_od,
 915                 amdgpu_set_pp_sclk_od);
 916 static DEVICE_ATTR(pp_mclk_od, S_IRUGO | S_IWUSR,
 917                 amdgpu_get_pp_mclk_od,
 918                 amdgpu_set_pp_mclk_od);
 919 static DEVICE_ATTR(pp_gfx_power_profile, S_IRUGO | S_IWUSR,
 920                 amdgpu_get_pp_gfx_power_profile,
 921                 amdgpu_set_pp_gfx_power_profile);
 922 static DEVICE_ATTR(pp_compute_power_profile, S_IRUGO | S_IWUSR,
 923                 amdgpu_get_pp_compute_power_profile,
 924                 amdgpu_set_pp_compute_power_profile);
 925 static DEVICE_ATTR(pp_power_profile_mode, S_IRUGO | S_IWUSR,
 926                 amdgpu_get_pp_power_profile_mode,
 927                 amdgpu_set_pp_power_profile_mode);
 928 static DEVICE_ATTR(pp_od_clk_voltage, S_IRUGO | S_IWUSR,
 929                 amdgpu_get_pp_od_clk_voltage,
 930                 amdgpu_set_pp_od_clk_voltage);
 931
 932 static ssize_t amdgpu_hwmon_show_temp(struct device *dev,
 933                                       struct device_attribute *attr,
 934                                       char *buf)
 935 {
 936         struct amdgpu_device *adev = dev_get_drvdata(dev);
 937         struct drm_device *ddev = adev->ddev;
 938         int r, temp, size = sizeof(temp);
 939
 940         /* Can't get temperature when the card is off */
 941         if  ((adev->flags & AMD_IS_PX) &&
 942              (ddev->switch_power_state != DRM_SWITCH_POWER_ON))
 943                 return -EINVAL;
 944
 945         /* sanity check PP is enabled */
 946         if (!(adev->powerplay.pp_funcs &&
 947               adev->powerplay.pp_funcs->read_sensor))
 948                 return -EINVAL;
 949
 950         /* get the temperature */
 951         r = amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_GPU_TEMP,
 952                                    (void *)&temp, &size);
 953         if (r)
 954                 return r;
 955
 956         return snprintf(buf, PAGE_SIZE, "%d\n", temp);
 957 }
 958
 959 static ssize_t amdgpu_hwmon_show_temp_thresh(struct device *dev,
 960                                              struct device_attribute *attr,
 961                                              char *buf)
 962 {
 963         struct amdgpu_device *adev = dev_get_drvdata(dev);
 964         int hyst = to_sensor_dev_attr(attr)->index;
 965         int temp;
 966
 967         if (hyst)
 968                 temp = adev->pm.dpm.thermal.min_temp;
 969         else
 970                 temp = adev->pm.dpm.thermal.max_temp;
 971
 972         return snprintf(buf, PAGE_SIZE, "%d\n", temp);
 973 }
 974
 975 static ssize_t amdgpu_hwmon_get_pwm1_enable(struct device *dev,
 976                                             struct device_attribute *attr,
 977                                             char *buf)
 978 {
 979         struct amdgpu_device *adev = dev_get_drvdata(dev);
 980         u32 pwm_mode = 0;
 981
 982         if (!adev->powerplay.pp_funcs->get_fan_control_mode)
 983                 return -EINVAL;
 984
 985         pwm_mode = amdgpu_dpm_get_fan_control_mode(adev);
 986
 987         return sprintf(buf, "%i\n", pwm_mode);
 988 }
 989
 990 static ssize_t amdgpu_hwmon_set_pwm1_enable(struct device *dev,
 991                                             struct device_attribute *attr,
 992                                             const char *buf,
 993                                             size_t count)
 994 {
 995         struct amdgpu_device *adev = dev_get_drvdata(dev);
 996         int err;
 997         int value;
 998
 999         /* Can't adjust fan when the card is off */
1000         if  ((adev->flags & AMD_IS_PX) &&
1001              (adev->ddev->switch_power_state != DRM_SWITCH_POWER_ON))
1002                 return -EINVAL;
1003
1004         if (!adev->powerplay.pp_funcs->set_fan_control_mode)
1005                 return -EINVAL;
1006
1007         err = kstrtoint(buf, 10, &value);
1008         if (err)
1009                 return err;
1010
1011         amdgpu_dpm_set_fan_control_mode(adev, value);
1012
1013         return count;
1014 }
1015
1016 static ssize_t amdgpu_hwmon_get_pwm1_min(struct device *dev,
1017                                          struct device_attribute *attr,
1018                                          char *buf)
1019 {
1020         return sprintf(buf, "%i\n", 0);
1021 }
1022
1023 static ssize_t amdgpu_hwmon_get_pwm1_max(struct device *dev,
1024                                          struct device_attribute *attr,
1025                                          char *buf)
1026 {
1027         return sprintf(buf, "%i\n", 255);
1028 }
1029
1030 static ssize_t amdgpu_hwmon_set_pwm1(struct device *dev,
1031                                      struct device_attribute *attr,
1032                                      const char *buf, size_t count)
1033 {
1034         struct amdgpu_device *adev = dev_get_drvdata(dev);
1035         int err;
1036         u32 value;
1037
1038         /* Can't adjust fan when the card is off */
1039         if  ((adev->flags & AMD_IS_PX) &&
1040              (adev->ddev->switch_power_state != DRM_SWITCH_POWER_ON))
1041                 return -EINVAL;
1042
1043         err = kstrtou32(buf, 10, &value);
1044         if (err)
1045                 return err;
1046
1047         value = (value * 100) / 255;
1048
1049         if (adev->powerplay.pp_funcs->set_fan_speed_percent) {
1050                 err = amdgpu_dpm_set_fan_speed_percent(adev, value);
1051                 if (err)
1052                         return err;
1053         }
1054
1055         return count;
1056 }
1057
1058 static ssize_t amdgpu_hwmon_get_pwm1(struct device *dev,
1059                                      struct device_attribute *attr,
1060                                      char *buf)
1061 {
1062         struct amdgpu_device *adev = dev_get_drvdata(dev);
1063         int err;
1064         u32 speed = 0;
1065
1066         /* Can't adjust fan when the card is off */
1067         if  ((adev->flags & AMD_IS_PX) &&
1068              (adev->ddev->switch_power_state != DRM_SWITCH_POWER_ON))
1069                 return -EINVAL;
1070
1071         if (adev->powerplay.pp_funcs->get_fan_speed_percent) {
1072                 err = amdgpu_dpm_get_fan_speed_percent(adev, &speed);
1073                 if (err)
1074                         return err;
1075         }
1076
1077         speed = (speed * 255) / 100;
1078
1079         return sprintf(buf, "%i\n", speed);
1080 }
1081
1082 static ssize_t amdgpu_hwmon_get_fan1_input(struct device *dev,
1083                                            struct device_attribute *attr,
1084                                            char *buf)
1085 {
1086         struct amdgpu_device *adev = dev_get_drvdata(dev);
1087         int err;
1088         u32 speed = 0;
1089
1090         /* Can't adjust fan when the card is off */
1091         if  ((adev->flags & AMD_IS_PX) &&
1092              (adev->ddev->switch_power_state != DRM_SWITCH_POWER_ON))
1093                 return -EINVAL;
1094
1095         if (adev->powerplay.pp_funcs->get_fan_speed_rpm) {
1096                 err = amdgpu_dpm_get_fan_speed_rpm(adev, &speed);
1097                 if (err)
1098                         return err;
1099         }
1100
1101         return sprintf(buf, "%i\n", speed);
1102 }
1103
1104 static ssize_t amdgpu_hwmon_show_vddgfx(struct device *dev,
1105                                         struct device_attribute *attr,
1106                                         char *buf)
1107 {
1108         struct amdgpu_device *adev = dev_get_drvdata(dev);
1109         struct drm_device *ddev = adev->ddev;
1110         u32 vddgfx;
1111         int r, size = sizeof(vddgfx);
1112
1113         /* Can't get voltage when the card is off */
1114         if  ((adev->flags & AMD_IS_PX) &&
1115              (ddev->switch_power_state != DRM_SWITCH_POWER_ON))
1116                 return -EINVAL;
1117
1118         /* sanity check PP is enabled */
1119         if (!(adev->powerplay.pp_funcs &&
1120               adev->powerplay.pp_funcs->read_sensor))
1121               return -EINVAL;
1122
1123         /* get the voltage */
1124         r = amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_VDDGFX,
1125                                    (void *)&vddgfx, &size);
1126         if (r)
1127                 return r;
1128
1129         return snprintf(buf, PAGE_SIZE, "%d\n", vddgfx);
1130 }
1131
1132 static ssize_t amdgpu_hwmon_show_vddgfx_label(struct device *dev,
1133                                               struct device_attribute *attr,
1134                                               char *buf)
1135 {
1136         return snprintf(buf, PAGE_SIZE, "vddgfx\n");
1137 }
1138
1139 static ssize_t amdgpu_hwmon_show_vddnb(struct device *dev,
1140                                        struct device_attribute *attr,
1141                                        char *buf)
1142 {
1143         struct amdgpu_device *adev = dev_get_drvdata(dev);
1144         struct drm_device *ddev = adev->ddev;
1145         u32 vddnb;
1146         int r, size = sizeof(vddnb);
1147
1148         /* only APUs have vddnb */
1149         if  (adev->flags & AMD_IS_APU)
1150                 return -EINVAL;
1151
1152         /* Can't get voltage when the card is off */
1153         if  ((adev->flags & AMD_IS_PX) &&
1154              (ddev->switch_power_state != DRM_SWITCH_POWER_ON))
1155                 return -EINVAL;
1156
1157         /* sanity check PP is enabled */
1158         if (!(adev->powerplay.pp_funcs &&
1159               adev->powerplay.pp_funcs->read_sensor))
1160               return -EINVAL;
1161
1162         /* get the voltage */
1163         r = amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_VDDNB,
1164                                    (void *)&vddnb, &size);
1165         if (r)
1166                 return r;
1167
1168         return snprintf(buf, PAGE_SIZE, "%d\n", vddnb);
1169 }
1170
1171 static ssize_t amdgpu_hwmon_show_vddnb_label(struct device *dev,
1172                                               struct device_attribute *attr,
1173                                               char *buf)
1174 {
1175         return snprintf(buf, PAGE_SIZE, "vddnb\n");
1176 }
1177
1178 static ssize_t amdgpu_hwmon_show_power_avg(struct device *dev,
1179                                            struct device_attribute *attr,
1180                                            char *buf)
1181 {
1182         struct amdgpu_device *adev = dev_get_drvdata(dev);
1183         struct drm_device *ddev = adev->ddev;
1184         struct pp_gpu_power query = {0};
1185         int r, size = sizeof(query);
1186         unsigned uw;
1187
1188         /* Can't get power when the card is off */
1189         if  ((adev->flags & AMD_IS_PX) &&
1190              (ddev->switch_power_state != DRM_SWITCH_POWER_ON))
1191                 return -EINVAL;
1192
1193         /* sanity check PP is enabled */
1194         if (!(adev->powerplay.pp_funcs &&
1195               adev->powerplay.pp_funcs->read_sensor))
1196               return -EINVAL;
1197
1198         /* get the voltage */
1199         r = amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_GPU_POWER,
1200                                    (void *)&query, &size);
1201         if (r)
1202                 return r;
1203
1204         /* convert to microwatts */
1205         uw = (query.average_gpu_power >> 8) * 1000000;
1206
1207         return snprintf(buf, PAGE_SIZE, "%u\n", uw);
1208 }
1209
1210 static ssize_t amdgpu_hwmon_show_power_cap_min(struct device *dev,
1211                                          struct device_attribute *attr,
1212                                          char *buf)
1213 {
1214         return sprintf(buf, "%i\n", 0);
1215 }
1216
1217 static ssize_t amdgpu_hwmon_show_power_cap_max(struct device *dev,
1218                                          struct device_attribute *attr,
1219                                          char *buf)
1220 {
1221         struct amdgpu_device *adev = dev_get_drvdata(dev);
1222         uint32_t limit = 0;
1223
1224         if (adev->powerplay.pp_funcs && adev->powerplay.pp_funcs->get_power_limit) {
1225                 adev->powerplay.pp_funcs->get_power_limit(adev->powerplay.pp_handle, &limit, true);
1226                 return snprintf(buf, PAGE_SIZE, "%u\n", limit * 1000000);
1227         } else {
1228                 return snprintf(buf, PAGE_SIZE, "\n");
1229         }
1230 }
1231
1232 static ssize_t amdgpu_hwmon_show_power_cap(struct device *dev,
1233                                          struct device_attribute *attr,
1234                                          char *buf)
1235 {
1236         struct amdgpu_device *adev = dev_get_drvdata(dev);
1237         uint32_t limit = 0;
1238
1239         if (adev->powerplay.pp_funcs && adev->powerplay.pp_funcs->get_power_limit) {
1240                 adev->powerplay.pp_funcs->get_power_limit(adev->powerplay.pp_handle, &limit, false);
1241                 return snprintf(buf, PAGE_SIZE, "%u\n", limit * 1000000);
1242         } else {
1243                 return snprintf(buf, PAGE_SIZE, "\n");
1244         }
1245 }
1246
1247
1248 static ssize_t amdgpu_hwmon_set_power_cap(struct device *dev,
1249                 struct device_attribute *attr,
1250                 const char *buf,
1251                 size_t count)
1252 {
1253         struct amdgpu_device *adev = dev_get_drvdata(dev);
1254         int err;
1255         u32 value;
1256
1257         err = kstrtou32(buf, 10, &value);
1258         if (err)
1259                 return err;
1260
1261         value = value / 1000000; /* convert to Watt */
1262         if (adev->powerplay.pp_funcs && adev->powerplay.pp_funcs->set_power_limit) {
1263                 err = adev->powerplay.pp_funcs->set_power_limit(adev->powerplay.pp_handle, value);
1264                 if (err)
1265                         return err;
1266         } else {
1267                 return -EINVAL;
1268         }
1269
1270         return count;
1271 }
1272
1273 static SENSOR_DEVICE_ATTR(temp1_input, S_IRUGO, amdgpu_hwmon_show_temp, NULL, 0);
1274 static SENSOR_DEVICE_ATTR(temp1_crit, S_IRUGO, amdgpu_hwmon_show_temp_thresh, NULL, 0);
1275 static SENSOR_DEVICE_ATTR(temp1_crit_hyst, S_IRUGO, amdgpu_hwmon_show_temp_thresh, NULL, 1);
1276 static SENSOR_DEVICE_ATTR(pwm1, S_IRUGO | S_IWUSR, amdgpu_hwmon_get_pwm1, amdgpu_hwmon_set_pwm1, 0);
1277 static SENSOR_DEVICE_ATTR(pwm1_enable, S_IRUGO | S_IWUSR, amdgpu_hwmon_get_pwm1_enable, amdgpu_hwmon_set_pwm1_enable, 0);
1278 static SENSOR_DEVICE_ATTR(pwm1_min, S_IRUGO, amdgpu_hwmon_get_pwm1_min, NULL, 0);
1279 static SENSOR_DEVICE_ATTR(pwm1_max, S_IRUGO, amdgpu_hwmon_get_pwm1_max, NULL, 0);
1280 static SENSOR_DEVICE_ATTR(fan1_input, S_IRUGO, amdgpu_hwmon_get_fan1_input, NULL, 0);
1281 static SENSOR_DEVICE_ATTR(in0_input, S_IRUGO, amdgpu_hwmon_show_vddgfx, NULL, 0);
1282 static SENSOR_DEVICE_ATTR(in0_label, S_IRUGO, amdgpu_hwmon_show_vddgfx_label, NULL, 0);
1283 static SENSOR_DEVICE_ATTR(in1_input, S_IRUGO, amdgpu_hwmon_show_vddnb, NULL, 0);
1284 static SENSOR_DEVICE_ATTR(in1_label, S_IRUGO, amdgpu_hwmon_show_vddnb_label, NULL, 0);
1285 static SENSOR_DEVICE_ATTR(power1_average, S_IRUGO, amdgpu_hwmon_show_power_avg, NULL, 0);
1286 static SENSOR_DEVICE_ATTR(power1_cap_max, S_IRUGO, amdgpu_hwmon_show_power_cap_max, NULL, 0);
1287 static SENSOR_DEVICE_ATTR(power1_cap_min, S_IRUGO, amdgpu_hwmon_show_power_cap_min, NULL, 0);
1288 static SENSOR_DEVICE_ATTR(power1_cap, S_IRUGO | S_IWUSR, amdgpu_hwmon_show_power_cap, amdgpu_hwmon_set_power_cap, 0);
1289
1290 static struct attribute *hwmon_attributes[] = {
1291         &sensor_dev_attr_temp1_input.dev_attr.attr,
1292         &sensor_dev_attr_temp1_crit.dev_attr.attr,
1293         &sensor_dev_attr_temp1_crit_hyst.dev_attr.attr,
1294         &sensor_dev_attr_pwm1.dev_attr.attr,
1295         &sensor_dev_attr_pwm1_enable.dev_attr.attr,
1296         &sensor_dev_attr_pwm1_min.dev_attr.attr,
1297         &sensor_dev_attr_pwm1_max.dev_attr.attr,
1298         &sensor_dev_attr_fan1_input.dev_attr.attr,
1299         &sensor_dev_attr_in0_input.dev_attr.attr,
1300         &sensor_dev_attr_in0_label.dev_attr.attr,
1301         &sensor_dev_attr_in1_input.dev_attr.attr,
1302         &sensor_dev_attr_in1_label.dev_attr.attr,
1303         &sensor_dev_attr_power1_average.dev_attr.attr,
1304         &sensor_dev_attr_power1_cap_max.dev_attr.attr,
1305         &sensor_dev_attr_power1_cap_min.dev_attr.attr,
1306         &sensor_dev_attr_power1_cap.dev_attr.attr,
1307         NULL
1308 };
1309
1310 static umode_t hwmon_attributes_visible(struct kobject *kobj,
1311                                         struct attribute *attr, int index)
1312 {
1313         struct device *dev = kobj_to_dev(kobj);
1314         struct amdgpu_device *adev = dev_get_drvdata(dev);
1315         umode_t effective_mode = attr->mode;
1316
1317         /* handle non-powerplay limitations */
1318         if (!adev->powerplay.cgs_device) {
1319                 /* Skip fan attributes if fan is not present */
1320                 if (adev->pm.no_fan &&
1321                     (attr == &sensor_dev_attr_pwm1.dev_attr.attr ||
1322                      attr == &sensor_dev_attr_pwm1_enable.dev_attr.attr ||
1323                      attr == &sensor_dev_attr_pwm1_max.dev_attr.attr ||
1324                      attr == &sensor_dev_attr_pwm1_min.dev_attr.attr))
1325                         return 0;
1326                 /* requires powerplay */
1327                 if (attr == &sensor_dev_attr_fan1_input.dev_attr.attr)
1328                         return 0;
1329         }
1330
1331         /* Skip limit attributes if DPM is not enabled */
1332         if (!adev->pm.dpm_enabled &&
1333             (attr == &sensor_dev_attr_temp1_crit.dev_attr.attr ||
1334              attr == &sensor_dev_attr_temp1_crit_hyst.dev_attr.attr ||
1335              attr == &sensor_dev_attr_pwm1.dev_attr.attr ||
1336              attr == &sensor_dev_attr_pwm1_enable.dev_attr.attr ||
1337              attr == &sensor_dev_attr_pwm1_max.dev_attr.attr ||
1338              attr == &sensor_dev_attr_pwm1_min.dev_attr.attr))
1339                 return 0;
1340
1341         /* mask fan attributes if we have no bindings for this asic to expose */
1342         if ((!adev->powerplay.pp_funcs->get_fan_speed_percent &&
1343              attr == &sensor_dev_attr_pwm1.dev_attr.attr) || /* can't query fan */
1344             (!adev->powerplay.pp_funcs->get_fan_control_mode &&
1345              attr == &sensor_dev_attr_pwm1_enable.dev_attr.attr)) /* can't query state */
1346                 effective_mode &= ~S_IRUGO;
1347
1348         if ((!adev->powerplay.pp_funcs->set_fan_speed_percent &&
1349              attr == &sensor_dev_attr_pwm1.dev_attr.attr) || /* can't manage fan */
1350             (!adev->powerplay.pp_funcs->set_fan_control_mode &&
1351              attr == &sensor_dev_attr_pwm1_enable.dev_attr.attr)) /* can't manage state */
1352                 effective_mode &= ~S_IWUSR;
1353
1354         if ((adev->flags & AMD_IS_APU) &&
1355             (attr == &sensor_dev_attr_power1_cap_max.dev_attr.attr ||
1356              attr == &sensor_dev_attr_power1_cap_min.dev_attr.attr||
1357              attr == &sensor_dev_attr_power1_cap.dev_attr.attr))
1358                 return 0;
1359
1360         /* hide max/min values if we can't both query and manage the fan */
1361         if ((!adev->powerplay.pp_funcs->set_fan_speed_percent &&
1362              !adev->powerplay.pp_funcs->get_fan_speed_percent) &&
1363             (attr == &sensor_dev_attr_pwm1_max.dev_attr.attr ||
1364              attr == &sensor_dev_attr_pwm1_min.dev_attr.attr))
1365                 return 0;
1366
1367         /* only APUs have vddnb */
1368         if (!(adev->flags & AMD_IS_APU) &&
1369             (attr == &sensor_dev_attr_in1_input.dev_attr.attr ||
1370              attr == &sensor_dev_attr_in1_label.dev_attr.attr))
1371                 return 0;
1372
1373         return effective_mode;
1374 }
1375
1376 static const struct attribute_group hwmon_attrgroup = {
1377         .attrs = hwmon_attributes,
1378         .is_visible = hwmon_attributes_visible,
1379 };
1380
1381 static const struct attribute_group *hwmon_groups[] = {
1382         &hwmon_attrgroup,
1383         NULL
1384 };
1385
1386 void amdgpu_dpm_thermal_work_handler(struct work_struct *work)
1387 {
1388         struct amdgpu_device *adev =
1389                 container_of(work, struct amdgpu_device,
1390                              pm.dpm.thermal.work);
1391         /* switch to the thermal state */
1392         enum amd_pm_state_type dpm_state = POWER_STATE_TYPE_INTERNAL_THERMAL;
1393         int temp, size = sizeof(temp);
1394
1395         if (!adev->pm.dpm_enabled)
1396                 return;
1397
1398         if (adev->powerplay.pp_funcs &&
1399             adev->powerplay.pp_funcs->read_sensor &&
1400             !amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_GPU_TEMP,
1401                                     (void *)&temp, &size)) {
1402                 if (temp < adev->pm.dpm.thermal.min_temp)
1403                         /* switch back the user state */
1404                         dpm_state = adev->pm.dpm.user_state;
1405         } else {
1406                 if (adev->pm.dpm.thermal.high_to_low)
1407                         /* switch back the user state */
1408                         dpm_state = adev->pm.dpm.user_state;
1409         }
1410         mutex_lock(&adev->pm.mutex);
1411         if (dpm_state == POWER_STATE_TYPE_INTERNAL_THERMAL)
1412                 adev->pm.dpm.thermal_active = true;
1413         else
1414                 adev->pm.dpm.thermal_active = false;
1415         adev->pm.dpm.state = dpm_state;
1416         mutex_unlock(&adev->pm.mutex);
1417
1418         amdgpu_pm_compute_clocks(adev);
1419 }
1420
1421 static struct amdgpu_ps *amdgpu_dpm_pick_power_state(struct amdgpu_device *adev,
1422                                                      enum amd_pm_state_type dpm_state)
1423 {
1424         int i;
1425         struct amdgpu_ps *ps;
1426         u32 ui_class;
1427         bool single_display = (adev->pm.dpm.new_active_crtc_count < 2) ?
1428                 true : false;
1429
1430         /* check if the vblank period is too short to adjust the mclk */
1431         if (single_display && adev->powerplay.pp_funcs->vblank_too_short) {
1432                 if (amdgpu_dpm_vblank_too_short(adev))
1433                         single_display = false;
1434         }
1435
1436         /* certain older asics have a separare 3D performance state,
1437          * so try that first if the user selected performance
1438          */
1439         if (dpm_state == POWER_STATE_TYPE_PERFORMANCE)
1440                 dpm_state = POWER_STATE_TYPE_INTERNAL_3DPERF;
1441         /* balanced states don't exist at the moment */
1442         if (dpm_state == POWER_STATE_TYPE_BALANCED)
1443                 dpm_state = POWER_STATE_TYPE_PERFORMANCE;
1444
1445 restart_search:
1446         /* Pick the best power state based on current conditions */
1447         for (i = 0; i < adev->pm.dpm.num_ps; i++) {
1448                 ps = &adev->pm.dpm.ps[i];
1449                 ui_class = ps->class & ATOM_PPLIB_CLASSIFICATION_UI_MASK;
1450                 switch (dpm_state) {
1451                 /* user states */
1452                 case POWER_STATE_TYPE_BATTERY:
1453                         if (ui_class == ATOM_PPLIB_CLASSIFICATION_UI_BATTERY) {
1454                                 if (ps->caps & ATOM_PPLIB_SINGLE_DISPLAY_ONLY) {
1455                                         if (single_display)
1456                                                 return ps;
1457                                 } else
1458                                         return ps;
1459                         }
1460                         break;
1461                 case POWER_STATE_TYPE_BALANCED:
1462                         if (ui_class == ATOM_PPLIB_CLASSIFICATION_UI_BALANCED) {
1463                                 if (ps->caps & ATOM_PPLIB_SINGLE_DISPLAY_ONLY) {
1464                                         if (single_display)
1465                                                 return ps;
1466                                 } else
1467                                         return ps;
1468                         }
1469                         break;
1470                 case POWER_STATE_TYPE_PERFORMANCE:
1471                         if (ui_class == ATOM_PPLIB_CLASSIFICATION_UI_PERFORMANCE) {
1472                                 if (ps->caps & ATOM_PPLIB_SINGLE_DISPLAY_ONLY) {
1473                                         if (single_display)
1474                                                 return ps;
1475                                 } else
1476                                         return ps;
1477                         }
1478                         break;
1479                 /* internal states */
1480                 case POWER_STATE_TYPE_INTERNAL_UVD:
1481                         if (adev->pm.dpm.uvd_ps)
1482                                 return adev->pm.dpm.uvd_ps;
1483                         else
1484                                 break;
1485                 case POWER_STATE_TYPE_INTERNAL_UVD_SD:
1486                         if (ps->class & ATOM_PPLIB_CLASSIFICATION_SDSTATE)
1487                                 return ps;
1488                         break;
1489                 case POWER_STATE_TYPE_INTERNAL_UVD_HD:
1490                         if (ps->class & ATOM_PPLIB_CLASSIFICATION_HDSTATE)
1491                                 return ps;
1492                         break;
1493                 case POWER_STATE_TYPE_INTERNAL_UVD_HD2:
1494                         if (ps->class & ATOM_PPLIB_CLASSIFICATION_HD2STATE)
1495                                 return ps;
1496                         break;
1497                 case POWER_STATE_TYPE_INTERNAL_UVD_MVC:
1498                         if (ps->class2 & ATOM_PPLIB_CLASSIFICATION2_MVC)
1499                                 return ps;
1500                         break;
1501                 case POWER_STATE_TYPE_INTERNAL_BOOT:
1502                         return adev->pm.dpm.boot_ps;
1503                 case POWER_STATE_TYPE_INTERNAL_THERMAL:
1504                         if (ps->class & ATOM_PPLIB_CLASSIFICATION_THERMAL)
1505                                 return ps;
1506                         break;
1507                 case POWER_STATE_TYPE_INTERNAL_ACPI:
1508                         if (ps->class & ATOM_PPLIB_CLASSIFICATION_ACPI)
1509                                 return ps;
1510                         break;
1511                 case POWER_STATE_TYPE_INTERNAL_ULV:
1512                         if (ps->class2 & ATOM_PPLIB_CLASSIFICATION2_ULV)
1513                                 return ps;
1514                         break;
1515                 case POWER_STATE_TYPE_INTERNAL_3DPERF:
1516                         if (ps->class & ATOM_PPLIB_CLASSIFICATION_3DPERFORMANCE)
1517                                 return ps;
1518                         break;
1519                 default:
1520                         break;
1521                 }
1522         }
1523         /* use a fallback state if we didn't match */
1524         switch (dpm_state) {
1525         case POWER_STATE_TYPE_INTERNAL_UVD_SD:
1526                 dpm_state = POWER_STATE_TYPE_INTERNAL_UVD_HD;
1527                 goto restart_search;
1528         case POWER_STATE_TYPE_INTERNAL_UVD_HD:
1529         case POWER_STATE_TYPE_INTERNAL_UVD_HD2:
1530         case POWER_STATE_TYPE_INTERNAL_UVD_MVC:
1531                 if (adev->pm.dpm.uvd_ps) {
1532                         return adev->pm.dpm.uvd_ps;
1533                 } else {
1534                         dpm_state = POWER_STATE_TYPE_PERFORMANCE;
1535                         goto restart_search;
1536                 }
1537         case POWER_STATE_TYPE_INTERNAL_THERMAL:
1538                 dpm_state = POWER_STATE_TYPE_INTERNAL_ACPI;
1539                 goto restart_search;
1540         case POWER_STATE_TYPE_INTERNAL_ACPI:
1541                 dpm_state = POWER_STATE_TYPE_BATTERY;
1542                 goto restart_search;
1543         case POWER_STATE_TYPE_BATTERY:
1544         case POWER_STATE_TYPE_BALANCED:
1545         case POWER_STATE_TYPE_INTERNAL_3DPERF:
1546                 dpm_state = POWER_STATE_TYPE_PERFORMANCE;
1547                 goto restart_search;
1548         default:
1549                 break;
1550         }
1551
1552         return NULL;
1553 }
1554
1555 static void amdgpu_dpm_change_power_state_locked(struct amdgpu_device *adev)
1556 {
1557         struct amdgpu_ps *ps;
1558         enum amd_pm_state_type dpm_state;
1559         int ret;
1560         bool equal = false;
1561
1562         /* if dpm init failed */
1563         if (!adev->pm.dpm_enabled)
1564                 return;
1565
1566         if (adev->pm.dpm.user_state != adev->pm.dpm.state) {
1567                 /* add other state override checks here */
1568                 if ((!adev->pm.dpm.thermal_active) &&
1569                     (!adev->pm.dpm.uvd_active))
1570                         adev->pm.dpm.state = adev->pm.dpm.user_state;
1571         }
1572         dpm_state = adev->pm.dpm.state;
1573
1574         ps = amdgpu_dpm_pick_power_state(adev, dpm_state);
1575         if (ps)
1576                 adev->pm.dpm.requested_ps = ps;
1577         else
1578                 return;
1579
1580         if (amdgpu_dpm == 1 && adev->powerplay.pp_funcs->print_power_state) {
1581                 printk("switching from power state:\n");
1582                 amdgpu_dpm_print_power_state(adev, adev->pm.dpm.current_ps);
1583                 printk("switching to power state:\n");
1584                 amdgpu_dpm_print_power_state(adev, adev->pm.dpm.requested_ps);
1585         }
1586
1587         /* update whether vce is active */
1588         ps->vce_active = adev->pm.dpm.vce_active;
1589         if (adev->powerplay.pp_funcs->display_configuration_changed)
1590                 amdgpu_dpm_display_configuration_changed(adev);
1591
1592         ret = amdgpu_dpm_pre_set_power_state(adev);
1593         if (ret)
1594                 return;
1595
1596         if (adev->powerplay.pp_funcs->check_state_equal) {
1597                 if (0 != amdgpu_dpm_check_state_equal(adev, adev->pm.dpm.current_ps, adev->pm.dpm.requested_ps, &equal))
1598                         equal = false;
1599         }
1600
1601         if (equal)
1602                 return;
1603
1604         amdgpu_dpm_set_power_state(adev);
1605         amdgpu_dpm_post_set_power_state(adev);
1606
1607         adev->pm.dpm.current_active_crtcs = adev->pm.dpm.new_active_crtcs;
1608         adev->pm.dpm.current_active_crtc_count = adev->pm.dpm.new_active_crtc_count;
1609
1610         if (adev->powerplay.pp_funcs->force_performance_level) {
1611                 if (adev->pm.dpm.thermal_active) {
1612                         enum amd_dpm_forced_level level = adev->pm.dpm.forced_level;
1613                         /* force low perf level for thermal */
1614                         amdgpu_dpm_force_performance_level(adev, AMD_DPM_FORCED_LEVEL_LOW);
1615                         /* save the user's level */
1616                         adev->pm.dpm.forced_level = level;
1617                 } else {
1618                         /* otherwise, user selected level */
1619                         amdgpu_dpm_force_performance_level(adev, adev->pm.dpm.forced_level);
1620                 }
1621         }
1622 }
1623
1624 void amdgpu_dpm_enable_uvd(struct amdgpu_device *adev, bool enable)
1625 {
1626         if (adev->powerplay.pp_funcs->powergate_uvd) {
1627                 /* enable/disable UVD */
1628                 mutex_lock(&adev->pm.mutex);
1629                 amdgpu_dpm_powergate_uvd(adev, !enable);
1630                 mutex_unlock(&adev->pm.mutex);
1631         } else {
1632                 if (enable) {
1633                         mutex_lock(&adev->pm.mutex);
1634                         adev->pm.dpm.uvd_active = true;
1635                         adev->pm.dpm.state = POWER_STATE_TYPE_INTERNAL_UVD;
1636                         mutex_unlock(&adev->pm.mutex);
1637                 } else {
1638                         mutex_lock(&adev->pm.mutex);
1639                         adev->pm.dpm.uvd_active = false;
1640                         mutex_unlock(&adev->pm.mutex);
1641                 }
1642                 amdgpu_pm_compute_clocks(adev);
1643         }
1644 }
1645
1646 void amdgpu_dpm_enable_vce(struct amdgpu_device *adev, bool enable)
1647 {
1648         if (adev->powerplay.pp_funcs->powergate_vce) {
1649                 /* enable/disable VCE */
1650                 mutex_lock(&adev->pm.mutex);
1651                 amdgpu_dpm_powergate_vce(adev, !enable);
1652                 mutex_unlock(&adev->pm.mutex);
1653         } else {
1654                 if (enable) {
1655                         mutex_lock(&adev->pm.mutex);
1656                         adev->pm.dpm.vce_active = true;
1657                         /* XXX select vce level based on ring/task */
1658                         adev->pm.dpm.vce_level = AMD_VCE_LEVEL_AC_ALL;
1659                         mutex_unlock(&adev->pm.mutex);
1660                         amdgpu_device_ip_set_clockgating_state(adev, AMD_IP_BLOCK_TYPE_VCE,
1661                                                                AMD_CG_STATE_UNGATE);
1662                         amdgpu_device_ip_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_VCE,
1663                                                                AMD_PG_STATE_UNGATE);
1664                         amdgpu_pm_compute_clocks(adev);
1665                 } else {
1666                         amdgpu_device_ip_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_VCE,
1667                                                                AMD_PG_STATE_GATE);
1668                         amdgpu_device_ip_set_clockgating_state(adev, AMD_IP_BLOCK_TYPE_VCE,
1669                                                                AMD_CG_STATE_GATE);
1670                         mutex_lock(&adev->pm.mutex);
1671                         adev->pm.dpm.vce_active = false;
1672                         mutex_unlock(&adev->pm.mutex);
1673                         amdgpu_pm_compute_clocks(adev);
1674                 }
1675
1676         }
1677 }
1678
1679 void amdgpu_pm_print_power_states(struct amdgpu_device *adev)
1680 {
1681         int i;
1682
1683         if (adev->powerplay.pp_funcs->print_power_state == NULL)
1684                 return;
1685
1686         for (i = 0; i < adev->pm.dpm.num_ps; i++)
1687                 amdgpu_dpm_print_power_state(adev, &adev->pm.dpm.ps[i]);
1688
1689 }
1690
1691 int amdgpu_pm_sysfs_init(struct amdgpu_device *adev)
1692 {
1693         int ret;
1694
1695         if (adev->pm.sysfs_initialized)
1696                 return 0;
1697
1698         if (adev->pm.dpm_enabled == 0)
1699                 return 0;
1700
1701         adev->pm.int_hwmon_dev = hwmon_device_register_with_groups(adev->dev,
1702                                                                    DRIVER_NAME, adev,
1703                                                                    hwmon_groups);
1704         if (IS_ERR(adev->pm.int_hwmon_dev)) {
1705                 ret = PTR_ERR(adev->pm.int_hwmon_dev);
1706                 dev_err(adev->dev,
1707                         "Unable to register hwmon device: %d\n", ret);
1708                 return ret;
1709         }
1710
1711         ret = device_create_file(adev->dev, &dev_attr_power_dpm_state);
1712         if (ret) {
1713                 DRM_ERROR("failed to create device file for dpm state\n");
1714                 return ret;
1715         }
1716         ret = device_create_file(adev->dev, &dev_attr_power_dpm_force_performance_level);
1717         if (ret) {
1718                 DRM_ERROR("failed to create device file for dpm state\n");
1719                 return ret;
1720         }
1721
1722
1723         ret = device_create_file(adev->dev, &dev_attr_pp_num_states);
1724         if (ret) {
1725                 DRM_ERROR("failed to create device file pp_num_states\n");
1726                 return ret;
1727         }
1728         ret = device_create_file(adev->dev, &dev_attr_pp_cur_state);
1729         if (ret) {
1730                 DRM_ERROR("failed to create device file pp_cur_state\n");
1731                 return ret;
1732         }
1733         ret = device_create_file(adev->dev, &dev_attr_pp_force_state);
1734         if (ret) {
1735                 DRM_ERROR("failed to create device file pp_force_state\n");
1736                 return ret;
1737         }
1738         ret = device_create_file(adev->dev, &dev_attr_pp_table);
1739         if (ret) {
1740                 DRM_ERROR("failed to create device file pp_table\n");
1741                 return ret;
1742         }
1743
1744         ret = device_create_file(adev->dev, &dev_attr_pp_dpm_sclk);
1745         if (ret) {
1746                 DRM_ERROR("failed to create device file pp_dpm_sclk\n");
1747                 return ret;
1748         }
1749         ret = device_create_file(adev->dev, &dev_attr_pp_dpm_mclk);
1750         if (ret) {
1751                 DRM_ERROR("failed to create device file pp_dpm_mclk\n");
1752                 return ret;
1753         }
1754         ret = device_create_file(adev->dev, &dev_attr_pp_dpm_pcie);
1755         if (ret) {
1756                 DRM_ERROR("failed to create device file pp_dpm_pcie\n");
1757                 return ret;
1758         }
1759         ret = device_create_file(adev->dev, &dev_attr_pp_sclk_od);
1760         if (ret) {
1761                 DRM_ERROR("failed to create device file pp_sclk_od\n");
1762                 return ret;
1763         }
1764         ret = device_create_file(adev->dev, &dev_attr_pp_mclk_od);
1765         if (ret) {
1766                 DRM_ERROR("failed to create device file pp_mclk_od\n");
1767                 return ret;
1768         }
1769         ret = device_create_file(adev->dev,
1770                         &dev_attr_pp_gfx_power_profile);
1771         if (ret) {
1772                 DRM_ERROR("failed to create device file "
1773                                 "pp_gfx_power_profile\n");
1774                 return ret;
1775         }
1776         ret = device_create_file(adev->dev,
1777                         &dev_attr_pp_compute_power_profile);
1778         if (ret) {
1779                 DRM_ERROR("failed to create device file "
1780                                 "pp_compute_power_profile\n");
1781                 return ret;
1782         }
1783
1784         ret = device_create_file(adev->dev,
1785                         &dev_attr_pp_power_profile_mode);
1786         if (ret) {
1787                 DRM_ERROR("failed to create device file "
1788                                 "pp_power_profile_mode\n");
1789                 return ret;
1790         }
1791         ret = device_create_file(adev->dev,
1792                         &dev_attr_pp_od_clk_voltage);
1793         if (ret) {
1794                 DRM_ERROR("failed to create device file "
1795                                 "pp_od_clk_voltage\n");
1796                 return ret;
1797         }
1798         ret = amdgpu_debugfs_pm_init(adev);
1799         if (ret) {
1800                 DRM_ERROR("Failed to register debugfs file for dpm!\n");
1801                 return ret;
1802         }
1803
1804         adev->pm.sysfs_initialized = true;
1805
1806         return 0;
1807 }
1808
1809 void amdgpu_pm_sysfs_fini(struct amdgpu_device *adev)
1810 {
1811         if (adev->pm.dpm_enabled == 0)
1812                 return;
1813
1814         if (adev->pm.int_hwmon_dev)
1815                 hwmon_device_unregister(adev->pm.int_hwmon_dev);
1816         device_remove_file(adev->dev, &dev_attr_power_dpm_state);
1817         device_remove_file(adev->dev, &dev_attr_power_dpm_force_performance_level);
1818
1819         device_remove_file(adev->dev, &dev_attr_pp_num_states);
1820         device_remove_file(adev->dev, &dev_attr_pp_cur_state);
1821         device_remove_file(adev->dev, &dev_attr_pp_force_state);
1822         device_remove_file(adev->dev, &dev_attr_pp_table);
1823
1824         device_remove_file(adev->dev, &dev_attr_pp_dpm_sclk);
1825         device_remove_file(adev->dev, &dev_attr_pp_dpm_mclk);
1826         device_remove_file(adev->dev, &dev_attr_pp_dpm_pcie);
1827         device_remove_file(adev->dev, &dev_attr_pp_sclk_od);
1828         device_remove_file(adev->dev, &dev_attr_pp_mclk_od);
1829         device_remove_file(adev->dev,
1830                         &dev_attr_pp_gfx_power_profile);
1831         device_remove_file(adev->dev,
1832                         &dev_attr_pp_compute_power_profile);
1833         device_remove_file(adev->dev,
1834                         &dev_attr_pp_power_profile_mode);
1835         device_remove_file(adev->dev,
1836                         &dev_attr_pp_od_clk_voltage);
1837 }
1838
1839 void amdgpu_pm_compute_clocks(struct amdgpu_device *adev)
1840 {
1841         struct drm_device *ddev = adev->ddev;
1842         struct drm_crtc *crtc;
1843         struct amdgpu_crtc *amdgpu_crtc;
1844         int i = 0;
1845
1846         if (!adev->pm.dpm_enabled)
1847                 return;
1848
1849         if (adev->mode_info.num_crtc)
1850                 amdgpu_display_bandwidth_update(adev);
1851
1852         for (i = 0; i < AMDGPU_MAX_RINGS; i++) {
1853                 struct amdgpu_ring *ring = adev->rings[i];
1854                 if (ring && ring->ready)
1855                         amdgpu_fence_wait_empty(ring);
1856         }
1857
1858         if (adev->powerplay.pp_funcs->dispatch_tasks) {
1859                 amdgpu_dpm_dispatch_task(adev, AMD_PP_TASK_DISPLAY_CONFIG_CHANGE, NULL);
1860         } else {
1861                 mutex_lock(&adev->pm.mutex);
1862                 adev->pm.dpm.new_active_crtcs = 0;
1863                 adev->pm.dpm.new_active_crtc_count = 0;
1864                 if (adev->mode_info.num_crtc && adev->mode_info.mode_config_initialized) {
1865                         list_for_each_entry(crtc,
1866                                             &ddev->mode_config.crtc_list, head) {
1867                                 amdgpu_crtc = to_amdgpu_crtc(crtc);
1868                                 if (amdgpu_crtc->enabled) {
1869                                         adev->pm.dpm.new_active_crtcs |= (1 << amdgpu_crtc->crtc_id);
1870                                         adev->pm.dpm.new_active_crtc_count++;
1871                                 }
1872                         }
1873                 }
1874                 /* update battery/ac status */
1875                 if (power_supply_is_system_supplied() > 0)
1876                         adev->pm.dpm.ac_power = true;
1877                 else
1878                         adev->pm.dpm.ac_power = false;
1879
1880                 amdgpu_dpm_change_power_state_locked(adev);
1881
1882                 mutex_unlock(&adev->pm.mutex);
1883         }
1884 }
1885
1886 /*
1887  * Debugfs info
1888  */
1889 #if defined(CONFIG_DEBUG_FS)
1890
1891 static int amdgpu_debugfs_pm_info_pp(struct seq_file *m, struct amdgpu_device *adev)
1892 {
1893         uint32_t value;
1894         struct pp_gpu_power query = {0};
1895         int size;
1896
1897         /* sanity check PP is enabled */
1898         if (!(adev->powerplay.pp_funcs &&
1899               adev->powerplay.pp_funcs->read_sensor))
1900               return -EINVAL;
1901
1902         /* GPU Clocks */
1903         size = sizeof(value);
1904         seq_printf(m, "GFX Clocks and Power:\n");
1905         if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_GFX_MCLK, (void *)&value, &size))
1906                 seq_printf(m, "\t%u MHz (MCLK)\n", value/100);
1907         if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_GFX_SCLK, (void *)&value, &size))
1908                 seq_printf(m, "\t%u MHz (SCLK)\n", value/100);
1909         if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_STABLE_PSTATE_SCLK, (void *)&value, &size))
1910                 seq_printf(m, "\t%u MHz (PSTATE_SCLK)\n", value/100);
1911         if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_STABLE_PSTATE_MCLK, (void *)&value, &size))
1912                 seq_printf(m, "\t%u MHz (PSTATE_MCLK)\n", value/100);
1913         if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_VDDGFX, (void *)&value, &size))
1914                 seq_printf(m, "\t%u mV (VDDGFX)\n", value);
1915         if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_VDDNB, (void *)&value, &size))
1916                 seq_printf(m, "\t%u mV (VDDNB)\n", value);
1917         size = sizeof(query);
1918         if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_GPU_POWER, (void *)&query, &size)) {
1919                 seq_printf(m, "\t%u.%u W (VDDC)\n", query.vddc_power >> 8,
1920                                 query.vddc_power & 0xff);
1921                 seq_printf(m, "\t%u.%u W (VDDCI)\n", query.vddci_power >> 8,
1922                                 query.vddci_power & 0xff);
1923                 seq_printf(m, "\t%u.%u W (max GPU)\n", query.max_gpu_power >> 8,
1924                                 query.max_gpu_power & 0xff);
1925                 seq_printf(m, "\t%u.%u W (average GPU)\n", query.average_gpu_power >> 8,
1926                                 query.average_gpu_power & 0xff);
1927         }
1928         size = sizeof(value);
1929         seq_printf(m, "\n");
1930
1931         /* GPU Temp */
1932         if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_GPU_TEMP, (void *)&value, &size))
1933                 seq_printf(m, "GPU Temperature: %u C\n", value/1000);
1934
1935         /* GPU Load */
1936         if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_GPU_LOAD, (void *)&value, &size))
1937                 seq_printf(m, "GPU Load: %u %%\n", value);
1938         seq_printf(m, "\n");
1939
1940         /* UVD clocks */
1941         if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_UVD_POWER, (void *)&value, &size)) {
1942                 if (!value) {
1943                         seq_printf(m, "UVD: Disabled\n");
1944                 } else {
1945                         seq_printf(m, "UVD: Enabled\n");
1946                         if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_UVD_DCLK, (void *)&value, &size))
1947                                 seq_printf(m, "\t%u MHz (DCLK)\n", value/100);
1948                         if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_UVD_VCLK, (void *)&value, &size))
1949                                 seq_printf(m, "\t%u MHz (VCLK)\n", value/100);
1950                 }
1951         }
1952         seq_printf(m, "\n");
1953
1954         /* VCE clocks */
1955         if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_VCE_POWER, (void *)&value, &size)) {
1956                 if (!value) {
1957                         seq_printf(m, "VCE: Disabled\n");
1958                 } else {
1959                         seq_printf(m, "VCE: Enabled\n");
1960                         if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_VCE_ECCLK, (void *)&value, &size))
1961                                 seq_printf(m, "\t%u MHz (ECCLK)\n", value/100);
1962                 }
1963         }
1964
1965         return 0;
1966 }
1967
1968 static void amdgpu_parse_cg_state(struct seq_file *m, u32 flags)
1969 {
1970         int i;
1971
1972         for (i = 0; clocks[i].flag; i++)
1973                 seq_printf(m, "\t%s: %s\n", clocks[i].name,
1974                            (flags & clocks[i].flag) ? "On" : "Off");
1975 }
1976
1977 static int amdgpu_debugfs_pm_info(struct seq_file *m, void *data)
1978 {
1979         struct drm_info_node *node = (struct drm_info_node *) m->private;
1980         struct drm_device *dev = node->minor->dev;
1981         struct amdgpu_device *adev = dev->dev_private;
1982         struct drm_device *ddev = adev->ddev;
1983         u32 flags = 0;
1984
1985         amdgpu_device_ip_get_clockgating_state(adev, &flags);
1986         seq_printf(m, "Clock Gating Flags Mask: 0x%x\n", flags);
1987         amdgpu_parse_cg_state(m, flags);
1988         seq_printf(m, "\n");
1989
1990         if (!adev->pm.dpm_enabled) {
1991                 seq_printf(m, "dpm not enabled\n");
1992                 return 0;
1993         }
1994         if  ((adev->flags & AMD_IS_PX) &&
1995              (ddev->switch_power_state != DRM_SWITCH_POWER_ON)) {
1996                 seq_printf(m, "PX asic powered off\n");
1997         } else if (adev->powerplay.pp_funcs->debugfs_print_current_performance_level) {
1998                 mutex_lock(&adev->pm.mutex);
1999                 if (adev->powerplay.pp_funcs->debugfs_print_current_performance_level)
2000                         adev->powerplay.pp_funcs->debugfs_print_current_performance_level(adev, m);
2001                 else
2002                         seq_printf(m, "Debugfs support not implemented for this asic\n");
2003                 mutex_unlock(&adev->pm.mutex);
2004         } else {
2005                 return amdgpu_debugfs_pm_info_pp(m, adev);
2006         }
2007
2008         return 0;
2009 }
2010
2011 static const struct drm_info_list amdgpu_pm_info_list[] = {
2012         {"amdgpu_pm_info", amdgpu_debugfs_pm_info, 0, NULL},
2013 };
2014 #endif
2015
2016 static int amdgpu_debugfs_pm_init(struct amdgpu_device *adev)
2017 {
2018 #if defined(CONFIG_DEBUG_FS)
2019         return amdgpu_debugfs_add_files(adev, amdgpu_pm_info_list, ARRAY_SIZE(amdgpu_pm_info_list));
2020 #else
2021         return 0;
2022 #endif
2023 }