drivers/media/dvb-frontends/stv0367.c

   1 /*
   2  * stv0367.c
   3  *
   4  * Driver for ST STV0367 DVB-T & DVB-C demodulator IC.
   5  *
   6  * Copyright (C) ST Microelectronics.
   7  * Copyright (C) 2010,2011 NetUP Inc.
   8  * Copyright (C) 2010,2011 Igor M. Liplianin <[email protected]>
   9  *
  10  * This program is free software; you can redistribute it and/or modify
  11  * it under the terms of the GNU General Public License as published by
  12  * the Free Software Foundation; either version 2 of the License, or
  13  * (at your option) any later version.
  14  *
  15  * This program is distributed in the hope that it will be useful,
  16  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  17  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  18  *
  19  * GNU General Public License for more details.
  20  */
  21
  22 #include <linux/kernel.h>
  23 #include <linux/module.h>
  24 #include <linux/string.h>
  25 #include <linux/slab.h>
  26 #include <linux/i2c.h>
  27
  28 #include "stv0367.h"
  29 #include "stv0367_regs.h"
  30 #include "stv0367_priv.h"
  31
  32 /* Max transfer size done by I2C transfer functions */
  33 #define MAX_XFER_SIZE  64
  34
  35 static int stvdebug;
  36 module_param_named(debug, stvdebug, int, 0644);
  37
  38 static int i2cdebug;
  39 module_param_named(i2c_debug, i2cdebug, int, 0644);
  40
  41 #define dprintk(args...) \
  42         do { \
  43                 if (stvdebug) \
  44                         printk(KERN_DEBUG args); \
  45         } while (0)
  46         /* DVB-C */
  47
  48 struct stv0367cab_state {
  49         enum stv0367_cab_signal_type    state;
  50         u32     mclk;
  51         u32     adc_clk;
  52         s32     search_range;
  53         s32     derot_offset;
  54         /* results */
  55         int locked;                     /* channel found                */
  56         u32 freq_khz;                   /* found frequency (in kHz)     */
  57         u32 symbol_rate;                /* found symbol rate (in Bds)   */
  58         enum fe_spectral_inversion spect_inv; /* Spectrum Inversion     */
  59 };
  60
  61 struct stv0367ter_state {
  62         /* DVB-T */
  63         enum stv0367_ter_signal_type state;
  64         enum stv0367_ter_if_iq_mode if_iq_mode;
  65         enum stv0367_ter_mode mode;/* mode 2K or 8K */
  66         enum fe_guard_interval guard;
  67         enum stv0367_ter_hierarchy hierarchy;
  68         u32 frequency;
  69         enum fe_spectral_inversion sense; /*  current search spectrum */
  70         u8  force; /* force mode/guard */
  71         u8  bw; /* channel width 6, 7 or 8 in MHz */
  72         u8  pBW; /* channel width used during previous lock */
  73         u32 pBER;
  74         u32 pPER;
  75         u32 ucblocks;
  76         s8  echo_pos; /* echo position */
  77         u8  first_lock;
  78         u8  unlock_counter;
  79         u32 agc_val;
  80 };
  81
  82 struct stv0367_state {
  83         struct dvb_frontend fe;
  84         struct i2c_adapter *i2c;
  85         /* config settings */
  86         const struct stv0367_config *config;
  87         u8 chip_id;
  88         /* DVB-C */
  89         struct stv0367cab_state *cab_state;
  90         /* DVB-T */
  91         struct stv0367ter_state *ter_state;
  92 };
  93
  94 struct st_register {
  95         u16     addr;
  96         u8      value;
  97 };
  98
  99 /* values for STV4100 XTAL=30M int clk=53.125M*/
 100 static struct st_register def0367ter[STV0367TER_NBREGS] = {
 101         {R367TER_ID,            0x60},
 102         {R367TER_I2CRPT,        0xa0},
 103         /* {R367TER_I2CRPT,     0x22},*/
 104         {R367TER_TOPCTRL,       0x00},/* for xc5000; was 0x02 */
 105         {R367TER_IOCFG0,        0x40},
 106         {R367TER_DAC0R,         0x00},
 107         {R367TER_IOCFG1,        0x00},
 108         {R367TER_DAC1R,         0x00},
 109         {R367TER_IOCFG2,        0x62},
 110         {R367TER_SDFR,          0x00},
 111         {R367TER_STATUS,        0xf8},
 112         {R367TER_AUX_CLK,       0x0a},
 113         {R367TER_FREESYS1,      0x00},
 114         {R367TER_FREESYS2,      0x00},
 115         {R367TER_FREESYS3,      0x00},
 116         {R367TER_GPIO_CFG,      0x55},
 117         {R367TER_GPIO_CMD,      0x00},
 118         {R367TER_AGC2MAX,       0xff},
 119         {R367TER_AGC2MIN,       0x00},
 120         {R367TER_AGC1MAX,       0xff},
 121         {R367TER_AGC1MIN,       0x00},
 122         {R367TER_AGCR,          0xbc},
 123         {R367TER_AGC2TH,        0x00},
 124         {R367TER_AGC12C,        0x00},
 125         {R367TER_AGCCTRL1,      0x85},
 126         {R367TER_AGCCTRL2,      0x1f},
 127         {R367TER_AGC1VAL1,      0x00},
 128         {R367TER_AGC1VAL2,      0x00},
 129         {R367TER_AGC2VAL1,      0x6f},
 130         {R367TER_AGC2VAL2,      0x05},
 131         {R367TER_AGC2PGA,       0x00},
 132         {R367TER_OVF_RATE1,     0x00},
 133         {R367TER_OVF_RATE2,     0x00},
 134         {R367TER_GAIN_SRC1,     0xaa},/* for xc5000; was 0x2b */
 135         {R367TER_GAIN_SRC2,     0xd6},/* for xc5000; was 0x04 */
 136         {R367TER_INC_DEROT1,    0x55},
 137         {R367TER_INC_DEROT2,    0x55},
 138         {R367TER_PPM_CPAMP_DIR, 0x2c},
 139         {R367TER_PPM_CPAMP_INV, 0x00},
 140         {R367TER_FREESTFE_1,    0x00},
 141         {R367TER_FREESTFE_2,    0x1c},
 142         {R367TER_DCOFFSET,      0x00},
 143         {R367TER_EN_PROCESS,    0x05},
 144         {R367TER_SDI_SMOOTHER,  0x80},
 145         {R367TER_FE_LOOP_OPEN,  0x1c},
 146         {R367TER_FREQOFF1,      0x00},
 147         {R367TER_FREQOFF2,      0x00},
 148         {R367TER_FREQOFF3,      0x00},
 149         {R367TER_TIMOFF1,       0x00},
 150         {R367TER_TIMOFF2,       0x00},
 151         {R367TER_EPQ,           0x02},
 152         {R367TER_EPQAUTO,       0x01},
 153         {R367TER_SYR_UPDATE,    0xf5},
 154         {R367TER_CHPFREE,       0x00},
 155         {R367TER_PPM_STATE_MAC, 0x23},
 156         {R367TER_INR_THRESHOLD, 0xff},
 157         {R367TER_EPQ_TPS_ID_CELL, 0xf9},
 158         {R367TER_EPQ_CFG,       0x00},
 159         {R367TER_EPQ_STATUS,    0x01},
 160         {R367TER_AUTORELOCK,    0x81},
 161         {R367TER_BER_THR_VMSB,  0x00},
 162         {R367TER_BER_THR_MSB,   0x00},
 163         {R367TER_BER_THR_LSB,   0x00},
 164         {R367TER_CCD,           0x83},
 165         {R367TER_SPECTR_CFG,    0x00},
 166         {R367TER_CHC_DUMMY,     0x18},
 167         {R367TER_INC_CTL,       0x88},
 168         {R367TER_INCTHRES_COR1, 0xb4},
 169         {R367TER_INCTHRES_COR2, 0x96},
 170         {R367TER_INCTHRES_DET1, 0x0e},
 171         {R367TER_INCTHRES_DET2, 0x11},
 172         {R367TER_IIR_CELLNB,    0x8d},
 173         {R367TER_IIRCX_COEFF1_MSB, 0x00},
 174         {R367TER_IIRCX_COEFF1_LSB, 0x00},
 175         {R367TER_IIRCX_COEFF2_MSB, 0x09},
 176         {R367TER_IIRCX_COEFF2_LSB, 0x18},
 177         {R367TER_IIRCX_COEFF3_MSB, 0x14},
 178         {R367TER_IIRCX_COEFF3_LSB, 0x9c},
 179         {R367TER_IIRCX_COEFF4_MSB, 0x00},
 180         {R367TER_IIRCX_COEFF4_LSB, 0x00},
 181         {R367TER_IIRCX_COEFF5_MSB, 0x36},
 182         {R367TER_IIRCX_COEFF5_LSB, 0x42},
 183         {R367TER_FEPATH_CFG,    0x00},
 184         {R367TER_PMC1_FUNC,     0x65},
 185         {R367TER_PMC1_FOR,      0x00},
 186         {R367TER_PMC2_FUNC,     0x00},
 187         {R367TER_STATUS_ERR_DA, 0xe0},
 188         {R367TER_DIG_AGC_R,     0xfe},
 189         {R367TER_COMAGC_TARMSB, 0x0b},
 190         {R367TER_COM_AGC_TAR_ENMODE, 0x41},
 191         {R367TER_COM_AGC_CFG,   0x3e},
 192         {R367TER_COM_AGC_GAIN1, 0x39},
 193         {R367TER_AUT_AGC_TARGETMSB, 0x0b},
 194         {R367TER_LOCK_DET_MSB,  0x01},
 195         {R367TER_AGCTAR_LOCK_LSBS, 0x40},
 196         {R367TER_AUT_GAIN_EN,   0xf4},
 197         {R367TER_AUT_CFG,       0xf0},
 198         {R367TER_LOCKN,         0x23},
 199         {R367TER_INT_X_3,       0x00},
 200         {R367TER_INT_X_2,       0x03},
 201         {R367TER_INT_X_1,       0x8d},
 202         {R367TER_INT_X_0,       0xa0},
 203         {R367TER_MIN_ERRX_MSB,  0x00},
 204         {R367TER_COR_CTL,       0x23},
 205         {R367TER_COR_STAT,      0xf6},
 206         {R367TER_COR_INTEN,     0x00},
 207         {R367TER_COR_INTSTAT,   0x3f},
 208         {R367TER_COR_MODEGUARD, 0x03},
 209         {R367TER_AGC_CTL,       0x08},
 210         {R367TER_AGC_MANUAL1,   0x00},
 211         {R367TER_AGC_MANUAL2,   0x00},
 212         {R367TER_AGC_TARG,      0x16},
 213         {R367TER_AGC_GAIN1,     0x53},
 214         {R367TER_AGC_GAIN2,     0x1d},
 215         {R367TER_RESERVED_1,    0x00},
 216         {R367TER_RESERVED_2,    0x00},
 217         {R367TER_RESERVED_3,    0x00},
 218         {R367TER_CAS_CTL,       0x44},
 219         {R367TER_CAS_FREQ,      0xb3},
 220         {R367TER_CAS_DAGCGAIN,  0x12},
 221         {R367TER_SYR_CTL,       0x04},
 222         {R367TER_SYR_STAT,      0x10},
 223         {R367TER_SYR_NCO1,      0x00},
 224         {R367TER_SYR_NCO2,      0x00},
 225         {R367TER_SYR_OFFSET1,   0x00},
 226         {R367TER_SYR_OFFSET2,   0x00},
 227         {R367TER_FFT_CTL,       0x00},
 228         {R367TER_SCR_CTL,       0x70},
 229         {R367TER_PPM_CTL1,      0xf8},
 230         {R367TER_TRL_CTL,       0x14},/* for xc5000; was 0xac */
 231         {R367TER_TRL_NOMRATE1,  0xae},/* for xc5000; was 0x1e */
 232         {R367TER_TRL_NOMRATE2,  0x56},/* for xc5000; was 0x58 */
 233         {R367TER_TRL_TIME1,     0x1d},
 234         {R367TER_TRL_TIME2,     0xfc},
 235         {R367TER_CRL_CTL,       0x24},
 236         {R367TER_CRL_FREQ1,     0xad},
 237         {R367TER_CRL_FREQ2,     0x9d},
 238         {R367TER_CRL_FREQ3,     0xff},
 239         {R367TER_CHC_CTL,       0x01},
 240         {R367TER_CHC_SNR,       0xf0},
 241         {R367TER_BDI_CTL,       0x00},
 242         {R367TER_DMP_CTL,       0x00},
 243         {R367TER_TPS_RCVD1,     0x30},
 244         {R367TER_TPS_RCVD2,     0x02},
 245         {R367TER_TPS_RCVD3,     0x01},
 246         {R367TER_TPS_RCVD4,     0x00},
 247         {R367TER_TPS_ID_CELL1,  0x00},
 248         {R367TER_TPS_ID_CELL2,  0x00},
 249         {R367TER_TPS_RCVD5_SET1, 0x02},
 250         {R367TER_TPS_SET2,      0x02},
 251         {R367TER_TPS_SET3,      0x01},
 252         {R367TER_TPS_CTL,       0x00},
 253         {R367TER_CTL_FFTOSNUM,  0x34},
 254         {R367TER_TESTSELECT,    0x09},
 255         {R367TER_MSC_REV,       0x0a},
 256         {R367TER_PIR_CTL,       0x00},
 257         {R367TER_SNR_CARRIER1,  0xa1},
 258         {R367TER_SNR_CARRIER2,  0x9a},
 259         {R367TER_PPM_CPAMP,     0x2c},
 260         {R367TER_TSM_AP0,       0x00},
 261         {R367TER_TSM_AP1,       0x00},
 262         {R367TER_TSM_AP2 ,      0x00},
 263         {R367TER_TSM_AP3,       0x00},
 264         {R367TER_TSM_AP4,       0x00},
 265         {R367TER_TSM_AP5,       0x00},
 266         {R367TER_TSM_AP6,       0x00},
 267         {R367TER_TSM_AP7,       0x00},
 268         {R367TER_TSTRES,        0x00},
 269         {R367TER_ANACTRL,       0x0D},/* PLL stoped, restart at init!!! */
 270         {R367TER_TSTBUS,        0x00},
 271         {R367TER_TSTRATE,       0x00},
 272         {R367TER_CONSTMODE,     0x01},
 273         {R367TER_CONSTCARR1,    0x00},
 274         {R367TER_CONSTCARR2,    0x00},
 275         {R367TER_ICONSTEL,      0x0a},
 276         {R367TER_QCONSTEL,      0x15},
 277         {R367TER_TSTBISTRES0,   0x00},
 278         {R367TER_TSTBISTRES1,   0x00},
 279         {R367TER_TSTBISTRES2,   0x28},
 280         {R367TER_TSTBISTRES3,   0x00},
 281         {R367TER_RF_AGC1,       0xff},
 282         {R367TER_RF_AGC2,       0x83},
 283         {R367TER_ANADIGCTRL,    0x19},
 284         {R367TER_PLLMDIV,       0x01},/* for xc5000; was 0x0c */
 285         {R367TER_PLLNDIV,       0x06},/* for xc5000; was 0x55 */
 286         {R367TER_PLLSETUP,      0x18},
 287         {R367TER_DUAL_AD12,     0x0C},/* for xc5000 AGC voltage 1.6V */
 288         {R367TER_TSTBIST,       0x00},
 289         {R367TER_PAD_COMP_CTRL, 0x00},
 290         {R367TER_PAD_COMP_WR,   0x00},
 291         {R367TER_PAD_COMP_RD,   0xe0},
 292         {R367TER_SYR_TARGET_FFTADJT_MSB, 0x00},
 293         {R367TER_SYR_TARGET_FFTADJT_LSB, 0x00},
 294         {R367TER_SYR_TARGET_CHCADJT_MSB, 0x00},
 295         {R367TER_SYR_TARGET_CHCADJT_LSB, 0x00},
 296         {R367TER_SYR_FLAG,      0x00},
 297         {R367TER_CRL_TARGET1,   0x00},
 298         {R367TER_CRL_TARGET2,   0x00},
 299         {R367TER_CRL_TARGET3,   0x00},
 300         {R367TER_CRL_TARGET4,   0x00},
 301         {R367TER_CRL_FLAG,      0x00},
 302         {R367TER_TRL_TARGET1,   0x00},
 303         {R367TER_TRL_TARGET2,   0x00},
 304         {R367TER_TRL_CHC,       0x00},
 305         {R367TER_CHC_SNR_TARG,  0x00},
 306         {R367TER_TOP_TRACK,     0x00},
 307         {R367TER_TRACKER_FREE1, 0x00},
 308         {R367TER_ERROR_CRL1,    0x00},
 309         {R367TER_ERROR_CRL2,    0x00},
 310         {R367TER_ERROR_CRL3,    0x00},
 311         {R367TER_ERROR_CRL4,    0x00},
 312         {R367TER_DEC_NCO1,      0x2c},
 313         {R367TER_DEC_NCO2,      0x0f},
 314         {R367TER_DEC_NCO3,      0x20},
 315         {R367TER_SNR,           0xf1},
 316         {R367TER_SYR_FFTADJ1,   0x00},
 317         {R367TER_SYR_FFTADJ2,   0x00},
 318         {R367TER_SYR_CHCADJ1,   0x00},
 319         {R367TER_SYR_CHCADJ2,   0x00},
 320         {R367TER_SYR_OFF,       0x00},
 321         {R367TER_PPM_OFFSET1,   0x00},
 322         {R367TER_PPM_OFFSET2,   0x03},
 323         {R367TER_TRACKER_FREE2, 0x00},
 324         {R367TER_DEBG_LT10,     0x00},
 325         {R367TER_DEBG_LT11,     0x00},
 326         {R367TER_DEBG_LT12,     0x00},
 327         {R367TER_DEBG_LT13,     0x00},
 328         {R367TER_DEBG_LT14,     0x00},
 329         {R367TER_DEBG_LT15,     0x00},
 330         {R367TER_DEBG_LT16,     0x00},
 331         {R367TER_DEBG_LT17,     0x00},
 332         {R367TER_DEBG_LT18,     0x00},
 333         {R367TER_DEBG_LT19,     0x00},
 334         {R367TER_DEBG_LT1A,     0x00},
 335         {R367TER_DEBG_LT1B,     0x00},
 336         {R367TER_DEBG_LT1C,     0x00},
 337         {R367TER_DEBG_LT1D,     0x00},
 338         {R367TER_DEBG_LT1E,     0x00},
 339         {R367TER_DEBG_LT1F,     0x00},
 340         {R367TER_RCCFGH,        0x00},
 341         {R367TER_RCCFGM,        0x00},
 342         {R367TER_RCCFGL,        0x00},
 343         {R367TER_RCINSDELH,     0x00},
 344         {R367TER_RCINSDELM,     0x00},
 345         {R367TER_RCINSDELL,     0x00},
 346         {R367TER_RCSTATUS,      0x00},
 347         {R367TER_RCSPEED,       0x6f},
 348         {R367TER_RCDEBUGM,      0xe7},
 349         {R367TER_RCDEBUGL,      0x9b},
 350         {R367TER_RCOBSCFG,      0x00},
 351         {R367TER_RCOBSM,        0x00},
 352         {R367TER_RCOBSL,        0x00},
 353         {R367TER_RCFECSPY,      0x00},
 354         {R367TER_RCFSPYCFG,     0x00},
 355         {R367TER_RCFSPYDATA,    0x00},
 356         {R367TER_RCFSPYOUT,     0x00},
 357         {R367TER_RCFSTATUS,     0x00},
 358         {R367TER_RCFGOODPACK,   0x00},
 359         {R367TER_RCFPACKCNT,    0x00},
 360         {R367TER_RCFSPYMISC,    0x00},
 361         {R367TER_RCFBERCPT4,    0x00},
 362         {R367TER_RCFBERCPT3,    0x00},
 363         {R367TER_RCFBERCPT2,    0x00},
 364         {R367TER_RCFBERCPT1,    0x00},
 365         {R367TER_RCFBERCPT0,    0x00},
 366         {R367TER_RCFBERERR2,    0x00},
 367         {R367TER_RCFBERERR1,    0x00},
 368         {R367TER_RCFBERERR0,    0x00},
 369         {R367TER_RCFSTATESM,    0x00},
 370         {R367TER_RCFSTATESL,    0x00},
 371         {R367TER_RCFSPYBER,     0x00},
 372         {R367TER_RCFSPYDISTM,   0x00},
 373         {R367TER_RCFSPYDISTL,   0x00},
 374         {R367TER_RCFSPYOBS7,    0x00},
 375         {R367TER_RCFSPYOBS6,    0x00},
 376         {R367TER_RCFSPYOBS5,    0x00},
 377         {R367TER_RCFSPYOBS4,    0x00},
 378         {R367TER_RCFSPYOBS3,    0x00},
 379         {R367TER_RCFSPYOBS2,    0x00},
 380         {R367TER_RCFSPYOBS1,    0x00},
 381         {R367TER_RCFSPYOBS0,    0x00},
 382         {R367TER_TSGENERAL,     0x00},
 383         {R367TER_RC1SPEED,      0x6f},
 384         {R367TER_TSGSTATUS,     0x18},
 385         {R367TER_FECM,          0x01},
 386         {R367TER_VTH12,         0xff},
 387         {R367TER_VTH23,         0xa1},
 388         {R367TER_VTH34,         0x64},
 389         {R367TER_VTH56,         0x40},
 390         {R367TER_VTH67,         0x00},
 391         {R367TER_VTH78,         0x2c},
 392         {R367TER_VITCURPUN,     0x12},
 393         {R367TER_VERROR,        0x01},
 394         {R367TER_PRVIT,         0x3f},
 395         {R367TER_VAVSRVIT,      0x00},
 396         {R367TER_VSTATUSVIT,    0xbd},
 397         {R367TER_VTHINUSE,      0xa1},
 398         {R367TER_KDIV12,        0x20},
 399         {R367TER_KDIV23,        0x40},
 400         {R367TER_KDIV34,        0x20},
 401         {R367TER_KDIV56,        0x30},
 402         {R367TER_KDIV67,        0x00},
 403         {R367TER_KDIV78,        0x30},
 404         {R367TER_SIGPOWER,      0x54},
 405         {R367TER_DEMAPVIT,      0x40},
 406         {R367TER_VITSCALE,      0x00},
 407         {R367TER_FFEC1PRG,      0x00},
 408         {R367TER_FVITCURPUN,    0x12},
 409         {R367TER_FVERROR,       0x01},
 410         {R367TER_FVSTATUSVIT,   0xbd},
 411         {R367TER_DEBUG_LT1,     0x00},
 412         {R367TER_DEBUG_LT2,     0x00},
 413         {R367TER_DEBUG_LT3,     0x00},
 414         {R367TER_TSTSFMET,      0x00},
 415         {R367TER_SELOUT,        0x00},
 416         {R367TER_TSYNC,         0x00},
 417         {R367TER_TSTERR,        0x00},
 418         {R367TER_TSFSYNC,       0x00},
 419         {R367TER_TSTSFERR,      0x00},
 420         {R367TER_TSTTSSF1,      0x01},
 421         {R367TER_TSTTSSF2,      0x1f},
 422         {R367TER_TSTTSSF3,      0x00},
 423         {R367TER_TSTTS1,        0x00},
 424         {R367TER_TSTTS2,        0x1f},
 425         {R367TER_TSTTS3,        0x01},
 426         {R367TER_TSTTS4,        0x00},
 427         {R367TER_TSTTSRC,       0x00},
 428         {R367TER_TSTTSRS,       0x00},
 429         {R367TER_TSSTATEM,      0xb0},
 430         {R367TER_TSSTATEL,      0x40},
 431         {R367TER_TSCFGH,        0xC0},
 432         {R367TER_TSCFGM,        0xc0},/* for xc5000; was 0x00 */
 433         {R367TER_TSCFGL,        0x20},
 434         {R367TER_TSSYNC,        0x00},
 435         {R367TER_TSINSDELH,     0x00},
 436         {R367TER_TSINSDELM,     0x00},
 437         {R367TER_TSINSDELL,     0x00},
 438         {R367TER_TSDIVN,        0x03},
 439         {R367TER_TSDIVPM,       0x00},
 440         {R367TER_TSDIVPL,       0x00},
 441         {R367TER_TSDIVQM,       0x00},
 442         {R367TER_TSDIVQL,       0x00},
 443         {R367TER_TSDILSTKM,     0x00},
 444         {R367TER_TSDILSTKL,     0x00},
 445         {R367TER_TSSPEED,       0x40},/* for xc5000; was 0x6f */
 446         {R367TER_TSSTATUS,      0x81},
 447         {R367TER_TSSTATUS2,     0x6a},
 448         {R367TER_TSBITRATEM,    0x0f},
 449         {R367TER_TSBITRATEL,    0xc6},
 450         {R367TER_TSPACKLENM,    0x00},
 451         {R367TER_TSPACKLENL,    0xfc},
 452         {R367TER_TSBLOCLENM,    0x0a},
 453         {R367TER_TSBLOCLENL,    0x80},
 454         {R367TER_TSDLYH,        0x90},
 455         {R367TER_TSDLYM,        0x68},
 456         {R367TER_TSDLYL,        0x01},
 457         {R367TER_TSNPDAV,       0x00},
 458         {R367TER_TSBUFSTATH,    0x00},
 459         {R367TER_TSBUFSTATM,    0x00},
 460         {R367TER_TSBUFSTATL,    0x00},
 461         {R367TER_TSDEBUGM,      0xcf},
 462         {R367TER_TSDEBUGL,      0x1e},
 463         {R367TER_TSDLYSETH,     0x00},
 464         {R367TER_TSDLYSETM,     0x68},
 465         {R367TER_TSDLYSETL,     0x00},
 466         {R367TER_TSOBSCFG,      0x00},
 467         {R367TER_TSOBSM,        0x47},
 468         {R367TER_TSOBSL,        0x1f},
 469         {R367TER_ERRCTRL1,      0x95},
 470         {R367TER_ERRCNT1H,      0x80},
 471         {R367TER_ERRCNT1M,      0x00},
 472         {R367TER_ERRCNT1L,      0x00},
 473         {R367TER_ERRCTRL2,      0x95},
 474         {R367TER_ERRCNT2H,      0x00},
 475         {R367TER_ERRCNT2M,      0x00},
 476         {R367TER_ERRCNT2L,      0x00},
 477         {R367TER_FECSPY,        0x88},
 478         {R367TER_FSPYCFG,       0x2c},
 479         {R367TER_FSPYDATA,      0x3a},
 480         {R367TER_FSPYOUT,       0x06},
 481         {R367TER_FSTATUS,       0x61},
 482         {R367TER_FGOODPACK,     0xff},
 483         {R367TER_FPACKCNT,      0xff},
 484         {R367TER_FSPYMISC,      0x66},
 485         {R367TER_FBERCPT4,      0x00},
 486         {R367TER_FBERCPT3,      0x00},
 487         {R367TER_FBERCPT2,      0x36},
 488         {R367TER_FBERCPT1,      0x36},
 489         {R367TER_FBERCPT0,      0x14},
 490         {R367TER_FBERERR2,      0x00},
 491         {R367TER_FBERERR1,      0x03},
 492         {R367TER_FBERERR0,      0x28},
 493         {R367TER_FSTATESM,      0x00},
 494         {R367TER_FSTATESL,      0x02},
 495         {R367TER_FSPYBER,       0x00},
 496         {R367TER_FSPYDISTM,     0x01},
 497         {R367TER_FSPYDISTL,     0x9f},
 498         {R367TER_FSPYOBS7,      0xc9},
 499         {R367TER_FSPYOBS6,      0x99},
 500         {R367TER_FSPYOBS5,      0x08},
 501         {R367TER_FSPYOBS4,      0xec},
 502         {R367TER_FSPYOBS3,      0x01},
 503         {R367TER_FSPYOBS2,      0x0f},
 504         {R367TER_FSPYOBS1,      0xf5},
 505         {R367TER_FSPYOBS0,      0x08},
 506         {R367TER_SFDEMAP,       0x40},
 507         {R367TER_SFERROR,       0x00},
 508         {R367TER_SFAVSR,        0x30},
 509         {R367TER_SFECSTATUS,    0xcc},
 510         {R367TER_SFKDIV12,      0x20},
 511         {R367TER_SFKDIV23,      0x40},
 512         {R367TER_SFKDIV34,      0x20},
 513         {R367TER_SFKDIV56,      0x20},
 514         {R367TER_SFKDIV67,      0x00},
 515         {R367TER_SFKDIV78,      0x20},
 516         {R367TER_SFDILSTKM,     0x00},
 517         {R367TER_SFDILSTKL,     0x00},
 518         {R367TER_SFSTATUS,      0xb5},
 519         {R367TER_SFDLYH,        0x90},
 520         {R367TER_SFDLYM,        0x60},
 521         {R367TER_SFDLYL,        0x01},
 522         {R367TER_SFDLYSETH,     0xc0},
 523         {R367TER_SFDLYSETM,     0x60},
 524         {R367TER_SFDLYSETL,     0x00},
 525         {R367TER_SFOBSCFG,      0x00},
 526         {R367TER_SFOBSM,        0x47},
 527         {R367TER_SFOBSL,        0x05},
 528         {R367TER_SFECINFO,      0x40},
 529         {R367TER_SFERRCTRL,     0x74},
 530         {R367TER_SFERRCNTH,     0x80},
 531         {R367TER_SFERRCNTM ,    0x00},
 532         {R367TER_SFERRCNTL,     0x00},
 533         {R367TER_SYMBRATEM,     0x2f},
 534         {R367TER_SYMBRATEL,     0x50},
 535         {R367TER_SYMBSTATUS,    0x7f},
 536         {R367TER_SYMBCFG,       0x00},
 537         {R367TER_SYMBFIFOM,     0xf4},
 538         {R367TER_SYMBFIFOL,     0x0d},
 539         {R367TER_SYMBOFFSM,     0xf0},
 540         {R367TER_SYMBOFFSL,     0x2d},
 541         {R367TER_DEBUG_LT4,     0x00},
 542         {R367TER_DEBUG_LT5,     0x00},
 543         {R367TER_DEBUG_LT6,     0x00},
 544         {R367TER_DEBUG_LT7,     0x00},
 545         {R367TER_DEBUG_LT8,     0x00},
 546         {R367TER_DEBUG_LT9,     0x00},
 547 };
 548
 549 #define RF_LOOKUP_TABLE_SIZE  31
 550 #define RF_LOOKUP_TABLE2_SIZE 16
 551 /* RF Level (for RF AGC->AGC1) Lookup Table, depends on the board and tuner.*/
 552 static const s32 stv0367cab_RF_LookUp1[RF_LOOKUP_TABLE_SIZE][RF_LOOKUP_TABLE_SIZE] = {
 553         {/*AGC1*/
 554                 48, 50, 51, 53, 54, 56, 57, 58, 60, 61, 62, 63,
 555                 64, 65, 66, 67, 68, 69, 70, 71, 72, 73, 74, 75,
 556                 76, 77, 78, 80, 83, 85, 88,
 557         }, {/*RF(dbm)*/
 558                 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33,
 559                 34, 35, 36, 37, 38, 39, 41, 42, 43, 44, 46, 47,
 560                 49, 50, 52, 53, 54, 55, 56,
 561         }
 562 };
 563 /* RF Level (for IF AGC->AGC2) Lookup Table, depends on the board and tuner.*/
 564 static const s32 stv0367cab_RF_LookUp2[RF_LOOKUP_TABLE2_SIZE][RF_LOOKUP_TABLE2_SIZE] = {
 565         {/*AGC2*/
 566                 28, 29, 31, 32, 34, 35, 36, 37,
 567                 38, 39, 40, 41, 42, 43, 44, 45,
 568         }, {/*RF(dbm)*/
 569                 57, 58, 59, 60, 61, 62, 63, 64,
 570                 65, 66, 67, 68, 69, 70, 71, 72,
 571         }
 572 };
 573
 574 static struct st_register def0367cab[STV0367CAB_NBREGS] = {
 575         {R367CAB_ID,            0x60},
 576         {R367CAB_I2CRPT,        0xa0},
 577         /*{R367CAB_I2CRPT,      0x22},*/
 578         {R367CAB_TOPCTRL,       0x10},
 579         {R367CAB_IOCFG0,        0x80},
 580         {R367CAB_DAC0R,         0x00},
 581         {R367CAB_IOCFG1,        0x00},
 582         {R367CAB_DAC1R,         0x00},
 583         {R367CAB_IOCFG2,        0x00},
 584         {R367CAB_SDFR,          0x00},
 585         {R367CAB_AUX_CLK,       0x00},
 586         {R367CAB_FREESYS1,      0x00},
 587         {R367CAB_FREESYS2,      0x00},
 588         {R367CAB_FREESYS3,      0x00},
 589         {R367CAB_GPIO_CFG,      0x55},
 590         {R367CAB_GPIO_CMD,      0x01},
 591         {R367CAB_TSTRES,        0x00},
 592         {R367CAB_ANACTRL,       0x0d},/* was 0x00 need to check - I.M.L.*/
 593         {R367CAB_TSTBUS,        0x00},
 594         {R367CAB_RF_AGC1,       0xea},
 595         {R367CAB_RF_AGC2,       0x82},
 596         {R367CAB_ANADIGCTRL,    0x0b},
 597         {R367CAB_PLLMDIV,       0x01},
 598         {R367CAB_PLLNDIV,       0x08},
 599         {R367CAB_PLLSETUP,      0x18},
 600         {R367CAB_DUAL_AD12,     0x0C}, /* for xc5000 AGC voltage 1.6V */
 601         {R367CAB_TSTBIST,       0x00},
 602         {R367CAB_CTRL_1,        0x00},
 603         {R367CAB_CTRL_2,        0x03},
 604         {R367CAB_IT_STATUS1,    0x2b},
 605         {R367CAB_IT_STATUS2,    0x08},
 606         {R367CAB_IT_EN1,        0x00},
 607         {R367CAB_IT_EN2,        0x00},
 608         {R367CAB_CTRL_STATUS,   0x04},
 609         {R367CAB_TEST_CTL,      0x00},
 610         {R367CAB_AGC_CTL,       0x73},
 611         {R367CAB_AGC_IF_CFG,    0x50},
 612         {R367CAB_AGC_RF_CFG,    0x00},
 613         {R367CAB_AGC_PWM_CFG,   0x03},
 614         {R367CAB_AGC_PWR_REF_L, 0x5a},
 615         {R367CAB_AGC_PWR_REF_H, 0x00},
 616         {R367CAB_AGC_RF_TH_L,   0xff},
 617         {R367CAB_AGC_RF_TH_H,   0x07},
 618         {R367CAB_AGC_IF_LTH_L,  0x00},
 619         {R367CAB_AGC_IF_LTH_H,  0x08},
 620         {R367CAB_AGC_IF_HTH_L,  0xff},
 621         {R367CAB_AGC_IF_HTH_H,  0x07},
 622         {R367CAB_AGC_PWR_RD_L,  0xa0},
 623         {R367CAB_AGC_PWR_RD_M,  0xe9},
 624         {R367CAB_AGC_PWR_RD_H,  0x03},
 625         {R367CAB_AGC_PWM_IFCMD_L,       0xe4},
 626         {R367CAB_AGC_PWM_IFCMD_H,       0x00},
 627         {R367CAB_AGC_PWM_RFCMD_L,       0xff},
 628         {R367CAB_AGC_PWM_RFCMD_H,       0x07},
 629         {R367CAB_IQDEM_CFG,     0x01},
 630         {R367CAB_MIX_NCO_LL,    0x22},
 631         {R367CAB_MIX_NCO_HL,    0x96},
 632         {R367CAB_MIX_NCO_HH,    0x55},
 633         {R367CAB_SRC_NCO_LL,    0xff},
 634         {R367CAB_SRC_NCO_LH,    0x0c},
 635         {R367CAB_SRC_NCO_HL,    0xf5},
 636         {R367CAB_SRC_NCO_HH,    0x20},
 637         {R367CAB_IQDEM_GAIN_SRC_L,      0x06},
 638         {R367CAB_IQDEM_GAIN_SRC_H,      0x01},
 639         {R367CAB_IQDEM_DCRM_CFG_LL,     0xfe},
 640         {R367CAB_IQDEM_DCRM_CFG_LH,     0xff},
 641         {R367CAB_IQDEM_DCRM_CFG_HL,     0x0f},
 642         {R367CAB_IQDEM_DCRM_CFG_HH,     0x00},
 643         {R367CAB_IQDEM_ADJ_COEFF0,      0x34},
 644         {R367CAB_IQDEM_ADJ_COEFF1,      0xae},
 645         {R367CAB_IQDEM_ADJ_COEFF2,      0x46},
 646         {R367CAB_IQDEM_ADJ_COEFF3,      0x77},
 647         {R367CAB_IQDEM_ADJ_COEFF4,      0x96},
 648         {R367CAB_IQDEM_ADJ_COEFF5,      0x69},
 649         {R367CAB_IQDEM_ADJ_COEFF6,      0xc7},
 650         {R367CAB_IQDEM_ADJ_COEFF7,      0x01},
 651         {R367CAB_IQDEM_ADJ_EN,  0x04},
 652         {R367CAB_IQDEM_ADJ_AGC_REF,     0x94},
 653         {R367CAB_ALLPASSFILT1,  0xc9},
 654         {R367CAB_ALLPASSFILT2,  0x2d},
 655         {R367CAB_ALLPASSFILT3,  0xa3},
 656         {R367CAB_ALLPASSFILT4,  0xfb},
 657         {R367CAB_ALLPASSFILT5,  0xf6},
 658         {R367CAB_ALLPASSFILT6,  0x45},
 659         {R367CAB_ALLPASSFILT7,  0x6f},
 660         {R367CAB_ALLPASSFILT8,  0x7e},
 661         {R367CAB_ALLPASSFILT9,  0x05},
 662         {R367CAB_ALLPASSFILT10, 0x0a},
 663         {R367CAB_ALLPASSFILT11, 0x51},
 664         {R367CAB_TRL_AGC_CFG,   0x20},
 665         {R367CAB_TRL_LPF_CFG,   0x28},
 666         {R367CAB_TRL_LPF_ACQ_GAIN,      0x44},
 667         {R367CAB_TRL_LPF_TRK_GAIN,      0x22},
 668         {R367CAB_TRL_LPF_OUT_GAIN,      0x03},
 669         {R367CAB_TRL_LOCKDET_LTH,       0x04},
 670         {R367CAB_TRL_LOCKDET_HTH,       0x11},
 671         {R367CAB_TRL_LOCKDET_TRGVAL,    0x20},
 672         {R367CAB_IQ_QAM,        0x01},
 673         {R367CAB_FSM_STATE,     0xa0},
 674         {R367CAB_FSM_CTL,       0x08},
 675         {R367CAB_FSM_STS,       0x0c},
 676         {R367CAB_FSM_SNR0_HTH,  0x00},
 677         {R367CAB_FSM_SNR1_HTH,  0x00},
 678         {R367CAB_FSM_SNR2_HTH,  0x23},/* 0x00 */
 679         {R367CAB_FSM_SNR0_LTH,  0x00},
 680         {R367CAB_FSM_SNR1_LTH,  0x00},
 681         {R367CAB_FSM_EQA1_HTH,  0x00},
 682         {R367CAB_FSM_TEMPO,     0x32},
 683         {R367CAB_FSM_CONFIG,    0x03},
 684         {R367CAB_EQU_I_TESTTAP_L,       0x11},
 685         {R367CAB_EQU_I_TESTTAP_M,       0x00},
 686         {R367CAB_EQU_I_TESTTAP_H,       0x00},
 687         {R367CAB_EQU_TESTAP_CFG,        0x00},
 688         {R367CAB_EQU_Q_TESTTAP_L,       0xff},
 689         {R367CAB_EQU_Q_TESTTAP_M,       0x00},
 690         {R367CAB_EQU_Q_TESTTAP_H,       0x00},
 691         {R367CAB_EQU_TAP_CTRL,  0x00},
 692         {R367CAB_EQU_CTR_CRL_CONTROL_L, 0x11},
 693         {R367CAB_EQU_CTR_CRL_CONTROL_H, 0x05},
 694         {R367CAB_EQU_CTR_HIPOW_L,       0x00},
 695         {R367CAB_EQU_CTR_HIPOW_H,       0x00},
 696         {R367CAB_EQU_I_EQU_LO,  0xef},
 697         {R367CAB_EQU_I_EQU_HI,  0x00},
 698         {R367CAB_EQU_Q_EQU_LO,  0xee},
 699         {R367CAB_EQU_Q_EQU_HI,  0x00},
 700         {R367CAB_EQU_MAPPER,    0xc5},
 701         {R367CAB_EQU_SWEEP_RATE,        0x80},
 702         {R367CAB_EQU_SNR_LO,    0x64},
 703         {R367CAB_EQU_SNR_HI,    0x03},
 704         {R367CAB_EQU_GAMMA_LO,  0x00},
 705         {R367CAB_EQU_GAMMA_HI,  0x00},
 706         {R367CAB_EQU_ERR_GAIN,  0x36},
 707         {R367CAB_EQU_RADIUS,    0xaa},
 708         {R367CAB_EQU_FFE_MAINTAP,       0x00},
 709         {R367CAB_EQU_FFE_LEAKAGE,       0x63},
 710         {R367CAB_EQU_FFE_MAINTAP_POS,   0xdf},
 711         {R367CAB_EQU_GAIN_WIDE, 0x88},
 712         {R367CAB_EQU_GAIN_NARROW,       0x41},
 713         {R367CAB_EQU_CTR_LPF_GAIN,      0xd1},
 714         {R367CAB_EQU_CRL_LPF_GAIN,      0xa7},
 715         {R367CAB_EQU_GLOBAL_GAIN,       0x06},
 716         {R367CAB_EQU_CRL_LD_SEN,        0x85},
 717         {R367CAB_EQU_CRL_LD_VAL,        0xe2},
 718         {R367CAB_EQU_CRL_TFR,   0x20},
 719         {R367CAB_EQU_CRL_BISTH_LO,      0x00},
 720         {R367CAB_EQU_CRL_BISTH_HI,      0x00},
 721         {R367CAB_EQU_SWEEP_RANGE_LO,    0x00},
 722         {R367CAB_EQU_SWEEP_RANGE_HI,    0x00},
 723         {R367CAB_EQU_CRL_LIMITER,       0x40},
 724         {R367CAB_EQU_MODULUS_MAP,       0x90},
 725         {R367CAB_EQU_PNT_GAIN,  0xa7},
 726         {R367CAB_FEC_AC_CTR_0,  0x16},
 727         {R367CAB_FEC_AC_CTR_1,  0x0b},
 728         {R367CAB_FEC_AC_CTR_2,  0x88},
 729         {R367CAB_FEC_AC_CTR_3,  0x02},
 730         {R367CAB_FEC_STATUS,    0x12},
 731         {R367CAB_RS_COUNTER_0,  0x7d},
 732         {R367CAB_RS_COUNTER_1,  0xd0},
 733         {R367CAB_RS_COUNTER_2,  0x19},
 734         {R367CAB_RS_COUNTER_3,  0x0b},
 735         {R367CAB_RS_COUNTER_4,  0xa3},
 736         {R367CAB_RS_COUNTER_5,  0x00},
 737         {R367CAB_BERT_0,        0x01},
 738         {R367CAB_BERT_1,        0x25},
 739         {R367CAB_BERT_2,        0x41},
 740         {R367CAB_BERT_3,        0x39},
 741         {R367CAB_OUTFORMAT_0,   0xc2},
 742         {R367CAB_OUTFORMAT_1,   0x22},
 743         {R367CAB_SMOOTHER_2,    0x28},
 744         {R367CAB_TSMF_CTRL_0,   0x01},
 745         {R367CAB_TSMF_CTRL_1,   0xc6},
 746         {R367CAB_TSMF_CTRL_3,   0x43},
 747         {R367CAB_TS_ON_ID_0,    0x00},
 748         {R367CAB_TS_ON_ID_1,    0x00},
 749         {R367CAB_TS_ON_ID_2,    0x00},
 750         {R367CAB_TS_ON_ID_3,    0x00},
 751         {R367CAB_RE_STATUS_0,   0x00},
 752         {R367CAB_RE_STATUS_1,   0x00},
 753         {R367CAB_RE_STATUS_2,   0x00},
 754         {R367CAB_RE_STATUS_3,   0x00},
 755         {R367CAB_TS_STATUS_0,   0x00},
 756         {R367CAB_TS_STATUS_1,   0x00},
 757         {R367CAB_TS_STATUS_2,   0xa0},
 758         {R367CAB_TS_STATUS_3,   0x00},
 759         {R367CAB_T_O_ID_0,      0x00},
 760         {R367CAB_T_O_ID_1,      0x00},
 761         {R367CAB_T_O_ID_2,      0x00},
 762         {R367CAB_T_O_ID_3,      0x00},
 763 };
 764
 765 static
 766 int stv0367_writeregs(struct stv0367_state *state, u16 reg, u8 *data, int len)
 767 {
 768         u8 buf[MAX_XFER_SIZE];
 769         struct i2c_msg msg = {
 770                 .addr = state->config->demod_address,
 771                 .flags = 0,
 772                 .buf = buf,
 773                 .len = len + 2
 774         };
 775         int ret;
 776
 777         if (2 + len > sizeof(buf)) {
 778                 printk(KERN_WARNING
 779                        "%s: i2c wr reg=%04x: len=%d is too big!\n",
 780                        KBUILD_MODNAME, reg, len);
 781                 return -EINVAL;
 782         }
 783
 784
 785         buf[0] = MSB(reg);
 786         buf[1] = LSB(reg);
 787         memcpy(buf + 2, data, len);
 788
 789         if (i2cdebug)
 790                 printk(KERN_DEBUG "%s: [%02x] %02x: %02x\n", __func__,
 791                         state->config->demod_address, reg, buf[2]);
 792
 793         ret = i2c_transfer(state->i2c, &msg, 1);
 794         if (ret != 1)
 795                 printk(KERN_ERR "%s: i2c write error! ([%02x] %02x: %02x)\n",
 796                         __func__, state->config->demod_address, reg, buf[2]);
 797
 798         return (ret != 1) ? -EREMOTEIO : 0;
 799 }
 800
 801 static int stv0367_writereg(struct stv0367_state *state, u16 reg, u8 data)
 802 {
 803         return stv0367_writeregs(state, reg, &data, 1);
 804 }
 805
 806 static u8 stv0367_readreg(struct stv0367_state *state, u16 reg)
 807 {
 808         u8 b0[] = { 0, 0 };
 809         u8 b1[] = { 0 };
 810         struct i2c_msg msg[] = {
 811                 {
 812                         .addr = state->config->demod_address,
 813                         .flags = 0,
 814                         .buf = b0,
 815                         .len = 2
 816                 }, {
 817                         .addr = state->config->demod_address,
 818                         .flags = I2C_M_RD,
 819                         .buf = b1,
 820                         .len = 1
 821                 }
 822         };
 823         int ret;
 824
 825         b0[0] = MSB(reg);
 826         b0[1] = LSB(reg);
 827
 828         ret = i2c_transfer(state->i2c, msg, 2);
 829         if (ret != 2)
 830                 printk(KERN_ERR "%s: i2c read error ([%02x] %02x: %02x)\n",
 831                         __func__, state->config->demod_address, reg, b1[0]);
 832
 833         if (i2cdebug)
 834                 printk(KERN_DEBUG "%s: [%02x] %02x: %02x\n", __func__,
 835                         state->config->demod_address, reg, b1[0]);
 836
 837         return b1[0];
 838 }
 839
 840 static void extract_mask_pos(u32 label, u8 *mask, u8 *pos)
 841 {
 842         u8 position = 0, i = 0;
 843
 844         (*mask) = label & 0xff;
 845
 846         while ((position == 0) && (i < 8)) {
 847                 position = ((*mask) >> i) & 0x01;
 848                 i++;
 849         }
 850
 851         (*pos) = (i - 1);
 852 }
 853
 854 static void stv0367_writebits(struct stv0367_state *state, u32 label, u8 val)
 855 {
 856         u8 reg, mask, pos;
 857
 858         reg = stv0367_readreg(state, (label >> 16) & 0xffff);
 859         extract_mask_pos(label, &mask, &pos);
 860
 861         val = mask & (val << pos);
 862
 863         reg = (reg & (~mask)) | val;
 864         stv0367_writereg(state, (label >> 16) & 0xffff, reg);
 865
 866 }
 867
 868 static void stv0367_setbits(u8 *reg, u32 label, u8 val)
 869 {
 870         u8 mask, pos;
 871
 872         extract_mask_pos(label, &mask, &pos);
 873
 874         val = mask & (val << pos);
 875
 876         (*reg) = ((*reg) & (~mask)) | val;
 877 }
 878
 879 static u8 stv0367_readbits(struct stv0367_state *state, u32 label)
 880 {
 881         u8 val = 0xff;
 882         u8 mask, pos;
 883
 884         extract_mask_pos(label, &mask, &pos);
 885
 886         val = stv0367_readreg(state, label >> 16);
 887         val = (val & mask) >> pos;
 888
 889         return val;
 890 }
 891
 892 #if 0 /* Currently, unused */
 893 static u8 stv0367_getbits(u8 reg, u32 label)
 894 {
 895         u8 mask, pos;
 896
 897         extract_mask_pos(label, &mask, &pos);
 898
 899         return (reg & mask) >> pos;
 900 }
 901 #endif
 902 static int stv0367ter_gate_ctrl(struct dvb_frontend *fe, int enable)
 903 {
 904         struct stv0367_state *state = fe->demodulator_priv;
 905         u8 tmp = stv0367_readreg(state, R367TER_I2CRPT);
 906
 907         dprintk("%s:\n", __func__);
 908
 909         if (enable) {
 910                 stv0367_setbits(&tmp, F367TER_STOP_ENABLE, 0);
 911                 stv0367_setbits(&tmp, F367TER_I2CT_ON, 1);
 912         } else {
 913                 stv0367_setbits(&tmp, F367TER_STOP_ENABLE, 1);
 914                 stv0367_setbits(&tmp, F367TER_I2CT_ON, 0);
 915         }
 916
 917         stv0367_writereg(state, R367TER_I2CRPT, tmp);
 918
 919         return 0;
 920 }
 921
 922 static u32 stv0367_get_tuner_freq(struct dvb_frontend *fe)
 923 {
 924         struct dvb_frontend_ops *frontend_ops = &fe->ops;
 925         struct dvb_tuner_ops    *tuner_ops = &frontend_ops->tuner_ops;
 926         u32 freq = 0;
 927         int err = 0;
 928
 929         dprintk("%s:\n", __func__);
 930
 931         if (tuner_ops->get_frequency) {
 932                 err = tuner_ops->get_frequency(fe, &freq);
 933                 if (err < 0) {
 934                         printk(KERN_ERR "%s: Invalid parameter\n", __func__);
 935                         return err;
 936                 }
 937
 938                 dprintk("%s: frequency=%d\n", __func__, freq);
 939
 940         } else
 941                 return -1;
 942
 943         return freq;
 944 }
 945
 946 static u16 CellsCoeffs_8MHz_367cofdm[3][6][5] = {
 947         {
 948                 {0x10EF, 0xE205, 0x10EF, 0xCE49, 0x6DA7}, /* CELL 1 COEFFS 27M*/
 949                 {0x2151, 0xc557, 0x2151, 0xc705, 0x6f93}, /* CELL 2 COEFFS */
 950                 {0x2503, 0xc000, 0x2503, 0xc375, 0x7194}, /* CELL 3 COEFFS */
 951                 {0x20E9, 0xca94, 0x20e9, 0xc153, 0x7194}, /* CELL 4 COEFFS */
 952                 {0x06EF, 0xF852, 0x06EF, 0xC057, 0x7207}, /* CELL 5 COEFFS */
 953                 {0x0000, 0x0ECC, 0x0ECC, 0x0000, 0x3647} /* CELL 6 COEFFS */
 954         }, {
 955                 {0x10A0, 0xE2AF, 0x10A1, 0xCE76, 0x6D6D}, /* CELL 1 COEFFS 25M*/
 956                 {0x20DC, 0xC676, 0x20D9, 0xC80A, 0x6F29},
 957                 {0x2532, 0xC000, 0x251D, 0xC391, 0x706F},
 958                 {0x1F7A, 0xCD2B, 0x2032, 0xC15E, 0x711F},
 959                 {0x0698, 0xFA5E, 0x0568, 0xC059, 0x7193},
 960                 {0x0000, 0x0918, 0x149C, 0x0000, 0x3642} /* CELL 6 COEFFS */
 961         }, {
 962                 {0x0000, 0x0000, 0x0000, 0x0000, 0x0000}, /* 30M */
 963                 {0x0000, 0x0000, 0x0000, 0x0000, 0x0000},
 964                 {0x0000, 0x0000, 0x0000, 0x0000, 0x0000},
 965                 {0x0000, 0x0000, 0x0000, 0x0000, 0x0000},
 966                 {0x0000, 0x0000, 0x0000, 0x0000, 0x0000},
 967                 {0x0000, 0x0000, 0x0000, 0x0000, 0x0000}
 968         }
 969 };
 970
 971 static u16 CellsCoeffs_7MHz_367cofdm[3][6][5] = {
 972         {
 973                 {0x12CA, 0xDDAF, 0x12CA, 0xCCEB, 0x6FB1}, /* CELL 1 COEFFS 27M*/
 974                 {0x2329, 0xC000, 0x2329, 0xC6B0, 0x725F}, /* CELL 2 COEFFS */
 975                 {0x2394, 0xC000, 0x2394, 0xC2C7, 0x7410}, /* CELL 3 COEFFS */
 976                 {0x251C, 0xC000, 0x251C, 0xC103, 0x74D9}, /* CELL 4 COEFFS */
 977                 {0x0804, 0xF546, 0x0804, 0xC040, 0x7544}, /* CELL 5 COEFFS */
 978                 {0x0000, 0x0CD9, 0x0CD9, 0x0000, 0x370A} /* CELL 6 COEFFS */
 979         }, {
 980                 {0x1285, 0xDE47, 0x1285, 0xCD17, 0x6F76}, /*25M*/
 981                 {0x234C, 0xC000, 0x2348, 0xC6DA, 0x7206},
 982                 {0x23B4, 0xC000, 0x23AC, 0xC2DB, 0x73B3},
 983                 {0x253D, 0xC000, 0x25B6, 0xC10B, 0x747F},
 984                 {0x0721, 0xF79C, 0x065F, 0xC041, 0x74EB},
 985                 {0x0000, 0x08FA, 0x1162, 0x0000, 0x36FF}
 986         }, {
 987                 {0x0000, 0x0000, 0x0000, 0x0000, 0x0000}, /* 30M */
 988                 {0x0000, 0x0000, 0x0000, 0x0000, 0x0000},
 989                 {0x0000, 0x0000, 0x0000, 0x0000, 0x0000},
 990                 {0x0000, 0x0000, 0x0000, 0x0000, 0x0000},
 991                 {0x0000, 0x0000, 0x0000, 0x0000, 0x0000},
 992                 {0x0000, 0x0000, 0x0000, 0x0000, 0x0000}
 993         }
 994 };
 995
 996 static u16 CellsCoeffs_6MHz_367cofdm[3][6][5] = {
 997         {
 998                 {0x1699, 0xD5B8, 0x1699, 0xCBC3, 0x713B}, /* CELL 1 COEFFS 27M*/
 999                 {0x2245, 0xC000, 0x2245, 0xC568, 0x74D5}, /* CELL 2 COEFFS */
1000                 {0x227F, 0xC000, 0x227F, 0xC1FC, 0x76C6}, /* CELL 3 COEFFS */
1001                 {0x235E, 0xC000, 0x235E, 0xC0A7, 0x778A}, /* CELL 4 COEFFS */
1002                 {0x0ECB, 0xEA0B, 0x0ECB, 0xC027, 0x77DD}, /* CELL 5 COEFFS */
1003                 {0x0000, 0x0B68, 0x0B68, 0x0000, 0xC89A}, /* CELL 6 COEFFS */
1004         }, {
1005                 {0x1655, 0xD64E, 0x1658, 0xCBEF, 0x70FE}, /*25M*/
1006                 {0x225E, 0xC000, 0x2256, 0xC589, 0x7489},
1007                 {0x2293, 0xC000, 0x2295, 0xC209, 0x767E},
1008                 {0x2377, 0xC000, 0x23AA, 0xC0AB, 0x7746},
1009                 {0x0DC7, 0xEBC8, 0x0D07, 0xC027, 0x7799},
1010                 {0x0000, 0x0888, 0x0E9C, 0x0000, 0x3757}
1011
1012         }, {
1013                 {0x0000, 0x0000, 0x0000, 0x0000, 0x0000}, /* 30M */
1014                 {0x0000, 0x0000, 0x0000, 0x0000, 0x0000},
1015                 {0x0000, 0x0000, 0x0000, 0x0000, 0x0000},
1016                 {0x0000, 0x0000, 0x0000, 0x0000, 0x0000},
1017                 {0x0000, 0x0000, 0x0000, 0x0000, 0x0000},
1018                 {0x0000, 0x0000, 0x0000, 0x0000, 0x0000}
1019         }
1020 };
1021
1022 static u32 stv0367ter_get_mclk(struct stv0367_state *state, u32 ExtClk_Hz)
1023 {
1024         u32 mclk_Hz = 0; /* master clock frequency (Hz) */
1025         u32 m, n, p;
1026
1027         dprintk("%s:\n", __func__);
1028
1029         if (stv0367_readbits(state, F367TER_BYPASS_PLLXN) == 0) {
1030                 n = (u32)stv0367_readbits(state, F367TER_PLL_NDIV);
1031                 if (n == 0)
1032                         n = n + 1;
1033
1034                 m = (u32)stv0367_readbits(state, F367TER_PLL_MDIV);
1035                 if (m == 0)
1036                         m = m + 1;
1037
1038                 p = (u32)stv0367_readbits(state, F367TER_PLL_PDIV);
1039                 if (p > 5)
1040                         p = 5;
1041
1042                 mclk_Hz = ((ExtClk_Hz / 2) * n) / (m * (1 << p));
1043
1044                 dprintk("N=%d M=%d P=%d mclk_Hz=%d ExtClk_Hz=%d\n",
1045                                 n, m, p, mclk_Hz, ExtClk_Hz);
1046         } else
1047                 mclk_Hz = ExtClk_Hz;
1048
1049         dprintk("%s: mclk_Hz=%d\n", __func__, mclk_Hz);
1050
1051         return mclk_Hz;
1052 }
1053
1054 static int stv0367ter_filt_coeff_init(struct stv0367_state *state,
1055                                 u16 CellsCoeffs[3][6][5], u32 DemodXtal)
1056 {
1057         int i, j, k, freq;
1058
1059         dprintk("%s:\n", __func__);
1060
1061         freq = stv0367ter_get_mclk(state, DemodXtal);
1062
1063         if (freq == 53125000)
1064                 k = 1; /* equivalent to Xtal 25M on 362*/
1065         else if (freq == 54000000)
1066                 k = 0; /* equivalent to Xtal 27M on 362*/
1067         else if (freq == 52500000)
1068                 k = 2; /* equivalent to Xtal 30M on 362*/
1069         else
1070                 return 0;
1071
1072         for (i = 1; i <= 6; i++) {
1073                 stv0367_writebits(state, F367TER_IIR_CELL_NB, i - 1);
1074
1075                 for (j = 1; j <= 5; j++) {
1076                         stv0367_writereg(state,
1077                                 (R367TER_IIRCX_COEFF1_MSB + 2 * (j - 1)),
1078                                 MSB(CellsCoeffs[k][i-1][j-1]));
1079                         stv0367_writereg(state,
1080                                 (R367TER_IIRCX_COEFF1_LSB + 2 * (j - 1)),
1081                                 LSB(CellsCoeffs[k][i-1][j-1]));
1082                 }
1083         }
1084
1085         return 1;
1086
1087 }
1088
1089 static void stv0367ter_agc_iir_lock_detect_set(struct stv0367_state *state)
1090 {
1091         dprintk("%s:\n", __func__);
1092
1093         stv0367_writebits(state, F367TER_LOCK_DETECT_LSB, 0x00);
1094
1095         /* Lock detect 1 */
1096         stv0367_writebits(state, F367TER_LOCK_DETECT_CHOICE, 0x00);
1097         stv0367_writebits(state, F367TER_LOCK_DETECT_MSB, 0x06);
1098         stv0367_writebits(state, F367TER_AUT_AGC_TARGET_LSB, 0x04);
1099
1100         /* Lock detect 2 */
1101         stv0367_writebits(state, F367TER_LOCK_DETECT_CHOICE, 0x01);
1102         stv0367_writebits(state, F367TER_LOCK_DETECT_MSB, 0x06);
1103         stv0367_writebits(state, F367TER_AUT_AGC_TARGET_LSB, 0x04);
1104
1105         /* Lock detect 3 */
1106         stv0367_writebits(state, F367TER_LOCK_DETECT_CHOICE, 0x02);
1107         stv0367_writebits(state, F367TER_LOCK_DETECT_MSB, 0x01);
1108         stv0367_writebits(state, F367TER_AUT_AGC_TARGET_LSB, 0x00);
1109
1110         /* Lock detect 4 */
1111         stv0367_writebits(state, F367TER_LOCK_DETECT_CHOICE, 0x03);
1112         stv0367_writebits(state, F367TER_LOCK_DETECT_MSB, 0x01);
1113         stv0367_writebits(state, F367TER_AUT_AGC_TARGET_LSB, 0x00);
1114
1115 }
1116
1117 static int stv0367_iir_filt_init(struct stv0367_state *state, u8 Bandwidth,
1118                                                         u32 DemodXtalValue)
1119 {
1120         dprintk("%s:\n", __func__);
1121
1122         stv0367_writebits(state, F367TER_NRST_IIR, 0);
1123
1124         switch (Bandwidth) {
1125         case 6:
1126                 if (!stv0367ter_filt_coeff_init(state,
1127                                 CellsCoeffs_6MHz_367cofdm,
1128                                 DemodXtalValue))
1129                         return 0;
1130                 break;
1131         case 7:
1132                 if (!stv0367ter_filt_coeff_init(state,
1133                                 CellsCoeffs_7MHz_367cofdm,
1134                                 DemodXtalValue))
1135                         return 0;
1136                 break;
1137         case 8:
1138                 if (!stv0367ter_filt_coeff_init(state,
1139                                 CellsCoeffs_8MHz_367cofdm,
1140                                 DemodXtalValue))
1141                         return 0;
1142                 break;
1143         default:
1144                 return 0;
1145         }
1146
1147         stv0367_writebits(state, F367TER_NRST_IIR, 1);
1148
1149         return 1;
1150 }
1151
1152 static void stv0367ter_agc_iir_rst(struct stv0367_state *state)
1153 {
1154
1155         u8 com_n;
1156
1157         dprintk("%s:\n", __func__);
1158
1159         com_n = stv0367_readbits(state, F367TER_COM_N);
1160
1161         stv0367_writebits(state, F367TER_COM_N, 0x07);
1162
1163         stv0367_writebits(state, F367TER_COM_SOFT_RSTN, 0x00);
1164         stv0367_writebits(state, F367TER_COM_AGC_ON, 0x00);
1165
1166         stv0367_writebits(state, F367TER_COM_SOFT_RSTN, 0x01);
1167         stv0367_writebits(state, F367TER_COM_AGC_ON, 0x01);
1168
1169         stv0367_writebits(state, F367TER_COM_N, com_n);
1170
1171 }
1172
1173 static int stv0367ter_duration(s32 mode, int tempo1, int tempo2, int tempo3)
1174 {
1175         int local_tempo = 0;
1176         switch (mode) {
1177         case 0:
1178                 local_tempo = tempo1;
1179                 break;
1180         case 1:
1181                 local_tempo = tempo2;
1182                 break ;
1183
1184         case 2:
1185                 local_tempo = tempo3;
1186                 break;
1187
1188         default:
1189                 break;
1190         }
1191         /*      msleep(local_tempo);  */
1192         return local_tempo;
1193 }
1194
1195 static enum
1196 stv0367_ter_signal_type stv0367ter_check_syr(struct stv0367_state *state)
1197 {
1198         int wd = 100;
1199         unsigned short int SYR_var;
1200         s32 SYRStatus;
1201
1202         dprintk("%s:\n", __func__);
1203
1204         SYR_var = stv0367_readbits(state, F367TER_SYR_LOCK);
1205
1206         while ((!SYR_var) && (wd > 0)) {
1207                 usleep_range(2000, 3000);
1208                 wd -= 2;
1209                 SYR_var = stv0367_readbits(state, F367TER_SYR_LOCK);
1210         }
1211
1212         if (!SYR_var)
1213                 SYRStatus = FE_TER_NOSYMBOL;
1214         else
1215                 SYRStatus =  FE_TER_SYMBOLOK;
1216
1217         dprintk("stv0367ter_check_syr SYRStatus %s\n",
1218                                 SYR_var == 0 ? "No Symbol" : "OK");
1219
1220         return SYRStatus;
1221 }
1222
1223 static enum
1224 stv0367_ter_signal_type stv0367ter_check_cpamp(struct stv0367_state *state,
1225                                                                 s32 FFTmode)
1226 {
1227
1228         s32  CPAMPvalue = 0, CPAMPStatus, CPAMPMin;
1229         int wd = 0;
1230
1231         dprintk("%s:\n", __func__);
1232
1233         switch (FFTmode) {
1234         case 0: /*2k mode*/
1235                 CPAMPMin = 20;
1236                 wd = 10;
1237                 break;
1238         case 1: /*8k mode*/
1239                 CPAMPMin = 80;
1240                 wd = 55;
1241                 break;
1242         case 2: /*4k mode*/
1243                 CPAMPMin = 40;
1244                 wd = 30;
1245                 break;
1246         default:
1247                 CPAMPMin = 0xffff;  /*drives to NOCPAMP */
1248                 break;
1249         }
1250
1251         dprintk("%s: CPAMPMin=%d wd=%d\n", __func__, CPAMPMin, wd);
1252
1253         CPAMPvalue = stv0367_readbits(state, F367TER_PPM_CPAMP_DIRECT);
1254         while ((CPAMPvalue < CPAMPMin) && (wd > 0)) {
1255                 usleep_range(1000, 2000);
1256                 wd -= 1;
1257                 CPAMPvalue = stv0367_readbits(state, F367TER_PPM_CPAMP_DIRECT);
1258                 /*dprintk("CPAMPvalue= %d at wd=%d\n",CPAMPvalue,wd); */
1259         }
1260         dprintk("******last CPAMPvalue= %d at wd=%d\n", CPAMPvalue, wd);
1261         if (CPAMPvalue < CPAMPMin) {
1262                 CPAMPStatus = FE_TER_NOCPAMP;
1263                 printk(KERN_ERR "CPAMP failed\n");
1264         } else {
1265                 printk(KERN_ERR "CPAMP OK !\n");
1266                 CPAMPStatus = FE_TER_CPAMPOK;
1267         }
1268
1269         return CPAMPStatus;
1270 }
1271
1272 static enum stv0367_ter_signal_type
1273 stv0367ter_lock_algo(struct stv0367_state *state)
1274 {
1275         enum stv0367_ter_signal_type ret_flag;
1276         short int wd, tempo;
1277         u8 try, u_var1 = 0, u_var2 = 0, u_var3 = 0, u_var4 = 0, mode, guard;
1278         u8 tmp, tmp2;
1279
1280         dprintk("%s:\n", __func__);
1281
1282         if (state == NULL)
1283                 return FE_TER_SWNOK;
1284
1285         try = 0;
1286         do {
1287                 ret_flag = FE_TER_LOCKOK;
1288
1289                 stv0367_writebits(state, F367TER_CORE_ACTIVE, 0);
1290
1291                 if (state->config->if_iq_mode != 0)
1292                         stv0367_writebits(state, F367TER_COM_N, 0x07);
1293
1294                 stv0367_writebits(state, F367TER_GUARD, 3);/* suggest 2k 1/4 */
1295                 stv0367_writebits(state, F367TER_MODE, 0);
1296                 stv0367_writebits(state, F367TER_SYR_TR_DIS, 0);
1297                 usleep_range(5000, 10000);
1298
1299                 stv0367_writebits(state, F367TER_CORE_ACTIVE, 1);
1300
1301
1302                 if (stv0367ter_check_syr(state) == FE_TER_NOSYMBOL)
1303                         return FE_TER_NOSYMBOL;
1304                 else { /*
1305                         if chip locked on wrong mode first try,
1306                         it must lock correctly second try */
1307                         mode = stv0367_readbits(state, F367TER_SYR_MODE);
1308                         if (stv0367ter_check_cpamp(state, mode) ==
1309                                                         FE_TER_NOCPAMP) {
1310                                 if (try == 0)
1311                                         ret_flag = FE_TER_NOCPAMP;
1312
1313                         }
1314                 }
1315
1316                 try++;
1317         } while ((try < 10) && (ret_flag != FE_TER_LOCKOK));
1318
1319         tmp  = stv0367_readreg(state, R367TER_SYR_STAT);
1320         tmp2 = stv0367_readreg(state, R367TER_STATUS);
1321         dprintk("state=%p\n", state);
1322         dprintk("LOCK OK! mode=%d SYR_STAT=0x%x R367TER_STATUS=0x%x\n",
1323                                                         mode, tmp, tmp2);
1324
1325         tmp  = stv0367_readreg(state, R367TER_PRVIT);
1326         tmp2 = stv0367_readreg(state, R367TER_I2CRPT);
1327         dprintk("PRVIT=0x%x I2CRPT=0x%x\n", tmp, tmp2);
1328
1329         tmp  = stv0367_readreg(state, R367TER_GAIN_SRC1);
1330         dprintk("GAIN_SRC1=0x%x\n", tmp);
1331
1332         if ((mode != 0) && (mode != 1) && (mode != 2))
1333                 return FE_TER_SWNOK;
1334
1335         /*guard=stv0367_readbits(state,F367TER_SYR_GUARD); */
1336
1337         /*suppress EPQ auto for SYR_GARD 1/16 or 1/32
1338         and set channel predictor in automatic */
1339 #if 0
1340         switch (guard) {
1341
1342         case 0:
1343         case 1:
1344                 stv0367_writebits(state, F367TER_AUTO_LE_EN, 0);
1345                 stv0367_writereg(state, R367TER_CHC_CTL, 0x01);
1346                 break;
1347         case 2:
1348         case 3:
1349                 stv0367_writebits(state, F367TER_AUTO_LE_EN, 1);
1350                 stv0367_writereg(state, R367TER_CHC_CTL, 0x11);
1351                 break;
1352
1353         default:
1354                 return FE_TER_SWNOK;
1355         }
1356 #endif
1357
1358         /*reset fec an reedsolo FOR 367 only*/
1359         stv0367_writebits(state, F367TER_RST_SFEC, 1);
1360         stv0367_writebits(state, F367TER_RST_REEDSOLO, 1);
1361         usleep_range(1000, 2000);
1362         stv0367_writebits(state, F367TER_RST_SFEC, 0);
1363         stv0367_writebits(state, F367TER_RST_REEDSOLO, 0);
1364
1365         u_var1 = stv0367_readbits(state, F367TER_LK);
1366         u_var2 = stv0367_readbits(state, F367TER_PRF);
1367         u_var3 = stv0367_readbits(state, F367TER_TPS_LOCK);
1368         /*      u_var4=stv0367_readbits(state,F367TER_TSFIFO_LINEOK); */
1369
1370         wd = stv0367ter_duration(mode, 125, 500, 250);
1371         tempo = stv0367ter_duration(mode, 4, 16, 8);
1372
1373         /*while ( ((!u_var1)||(!u_var2)||(!u_var3)||(!u_var4))  && (wd>=0)) */
1374         while (((!u_var1) || (!u_var2) || (!u_var3)) && (wd >= 0)) {
1375                 usleep_range(1000 * tempo, 1000 * (tempo + 1));
1376                 wd -= tempo;
1377                 u_var1 = stv0367_readbits(state, F367TER_LK);
1378                 u_var2 = stv0367_readbits(state, F367TER_PRF);
1379                 u_var3 = stv0367_readbits(state, F367TER_TPS_LOCK);
1380                 /*u_var4=stv0367_readbits(state, F367TER_TSFIFO_LINEOK); */
1381         }
1382
1383         if (!u_var1)
1384                 return FE_TER_NOLOCK;
1385
1386
1387         if (!u_var2)
1388                 return FE_TER_NOPRFOUND;
1389
1390         if (!u_var3)
1391                 return FE_TER_NOTPS;
1392
1393         guard = stv0367_readbits(state, F367TER_SYR_GUARD);
1394         stv0367_writereg(state, R367TER_CHC_CTL, 0x11);
1395         switch (guard) {
1396         case 0:
1397         case 1:
1398                 stv0367_writebits(state, F367TER_AUTO_LE_EN, 0);
1399                 /*stv0367_writereg(state,R367TER_CHC_CTL, 0x1);*/
1400                 stv0367_writebits(state, F367TER_SYR_FILTER, 0);
1401                 break;
1402         case 2:
1403         case 3:
1404                 stv0367_writebits(state, F367TER_AUTO_LE_EN, 1);
1405                 /*stv0367_writereg(state,R367TER_CHC_CTL, 0x11);*/
1406                 stv0367_writebits(state, F367TER_SYR_FILTER, 1);
1407                 break;
1408
1409         default:
1410                 return FE_TER_SWNOK;
1411         }
1412
1413         /* apply Sfec workaround if 8K 64QAM CR!=1/2*/
1414         if ((stv0367_readbits(state, F367TER_TPS_CONST) == 2) &&
1415                         (mode == 1) &&
1416                         (stv0367_readbits(state, F367TER_TPS_HPCODE) != 0)) {
1417                 stv0367_writereg(state, R367TER_SFDLYSETH, 0xc0);
1418                 stv0367_writereg(state, R367TER_SFDLYSETM, 0x60);
1419                 stv0367_writereg(state, R367TER_SFDLYSETL, 0x0);
1420         } else
1421                 stv0367_writereg(state, R367TER_SFDLYSETH, 0x0);
1422
1423         wd = stv0367ter_duration(mode, 125, 500, 250);
1424         u_var4 = stv0367_readbits(state, F367TER_TSFIFO_LINEOK);
1425
1426         while ((!u_var4) && (wd >= 0)) {
1427                 usleep_range(1000 * tempo, 1000 * (tempo + 1));
1428                 wd -= tempo;
1429                 u_var4 = stv0367_readbits(state, F367TER_TSFIFO_LINEOK);
1430         }
1431
1432         if (!u_var4)
1433                 return FE_TER_NOLOCK;
1434
1435         /* for 367 leave COM_N at 0x7 for IQ_mode*/
1436         /*if(ter_state->if_iq_mode!=FE_TER_NORMAL_IF_TUNER) {
1437                 tempo=0;
1438                 while ((stv0367_readbits(state,F367TER_COM_USEGAINTRK)!=1) &&
1439                 (stv0367_readbits(state,F367TER_COM_AGCLOCK)!=1)&&(tempo<100)) {
1440                         ChipWaitOrAbort(state,1);
1441                         tempo+=1;
1442                 }
1443
1444                 stv0367_writebits(state,F367TER_COM_N,0x17);
1445         } */
1446
1447         stv0367_writebits(state, F367TER_SYR_TR_DIS, 1);
1448
1449         dprintk("FE_TER_LOCKOK !!!\n");
1450
1451         return  FE_TER_LOCKOK;
1452
1453 }
1454
1455 static void stv0367ter_set_ts_mode(struct stv0367_state *state,
1456                                         enum stv0367_ts_mode PathTS)
1457 {
1458
1459         dprintk("%s:\n", __func__);
1460
1461         if (state == NULL)
1462                 return;
1463
1464         stv0367_writebits(state, F367TER_TS_DIS, 0);
1465         switch (PathTS) {
1466         default:
1467                 /*for removing warning :default we can assume in parallel mode*/
1468         case STV0367_PARALLEL_PUNCT_CLOCK:
1469                 stv0367_writebits(state, F367TER_TSFIFO_SERIAL, 0);
1470                 stv0367_writebits(state, F367TER_TSFIFO_DVBCI, 0);
1471                 break;
1472         case STV0367_SERIAL_PUNCT_CLOCK:
1473                 stv0367_writebits(state, F367TER_TSFIFO_SERIAL, 1);
1474                 stv0367_writebits(state, F367TER_TSFIFO_DVBCI, 1);
1475                 break;
1476         }
1477 }
1478
1479 static void stv0367ter_set_clk_pol(struct stv0367_state *state,
1480                                         enum stv0367_clk_pol clock)
1481 {
1482
1483         dprintk("%s:\n", __func__);
1484
1485         if (state == NULL)
1486                 return;
1487
1488         switch (clock) {
1489         case STV0367_RISINGEDGE_CLOCK:
1490                 stv0367_writebits(state, F367TER_TS_BYTE_CLK_INV, 1);
1491                 break;
1492         case STV0367_FALLINGEDGE_CLOCK:
1493                 stv0367_writebits(state, F367TER_TS_BYTE_CLK_INV, 0);
1494                 break;
1495                 /*case FE_TER_CLOCK_POLARITY_DEFAULT:*/
1496         default:
1497                 stv0367_writebits(state, F367TER_TS_BYTE_CLK_INV, 0);
1498                 break;
1499         }
1500 }
1501
1502 #if 0
1503 static void stv0367ter_core_sw(struct stv0367_state *state)
1504 {
1505
1506         dprintk("%s:\n", __func__);
1507
1508         stv0367_writebits(state, F367TER_CORE_ACTIVE, 0);
1509         stv0367_writebits(state, F367TER_CORE_ACTIVE, 1);
1510         msleep(350);
1511 }
1512 #endif
1513 static int stv0367ter_standby(struct dvb_frontend *fe, u8 standby_on)
1514 {
1515         struct stv0367_state *state = fe->demodulator_priv;
1516
1517         dprintk("%s:\n", __func__);
1518
1519         if (standby_on) {
1520                 stv0367_writebits(state, F367TER_STDBY, 1);
1521                 stv0367_writebits(state, F367TER_STDBY_FEC, 1);
1522                 stv0367_writebits(state, F367TER_STDBY_CORE, 1);
1523         } else {
1524                 stv0367_writebits(state, F367TER_STDBY, 0);
1525                 stv0367_writebits(state, F367TER_STDBY_FEC, 0);
1526                 stv0367_writebits(state, F367TER_STDBY_CORE, 0);
1527         }
1528
1529         return 0;
1530 }
1531
1532 static int stv0367ter_sleep(struct dvb_frontend *fe)
1533 {
1534         return stv0367ter_standby(fe, 1);
1535 }
1536
1537 static int stv0367ter_init(struct dvb_frontend *fe)
1538 {
1539         struct stv0367_state *state = fe->demodulator_priv;
1540         struct stv0367ter_state *ter_state = state->ter_state;
1541         int i;
1542
1543         dprintk("%s:\n", __func__);
1544
1545         ter_state->pBER = 0;
1546
1547         for (i = 0; i < STV0367TER_NBREGS; i++)
1548                 stv0367_writereg(state, def0367ter[i].addr,
1549                                         def0367ter[i].value);
1550
1551         switch (state->config->xtal) {
1552                 /*set internal freq to 53.125MHz */
1553         case 16000000:
1554                 stv0367_writereg(state, R367TER_PLLMDIV, 0x2);
1555                 stv0367_writereg(state, R367TER_PLLNDIV, 0x1b);
1556                 stv0367_writereg(state, R367TER_PLLSETUP, 0x18);
1557                 break;
1558         case 25000000:
1559                 stv0367_writereg(state, R367TER_PLLMDIV, 0xa);
1560                 stv0367_writereg(state, R367TER_PLLNDIV, 0x55);
1561                 stv0367_writereg(state, R367TER_PLLSETUP, 0x18);
1562                 break;
1563         default:
1564         case 27000000:
1565                 dprintk("FE_STV0367TER_SetCLKgen for 27Mhz\n");
1566                 stv0367_writereg(state, R367TER_PLLMDIV, 0x1);
1567                 stv0367_writereg(state, R367TER_PLLNDIV, 0x8);
1568                 stv0367_writereg(state, R367TER_PLLSETUP, 0x18);
1569                 break;
1570         case 30000000:
1571                 stv0367_writereg(state, R367TER_PLLMDIV, 0xc);
1572                 stv0367_writereg(state, R367TER_PLLNDIV, 0x55);
1573                 stv0367_writereg(state, R367TER_PLLSETUP, 0x18);
1574                 break;
1575         }
1576
1577         stv0367_writereg(state, R367TER_I2CRPT, 0xa0);
1578         stv0367_writereg(state, R367TER_ANACTRL, 0x00);
1579
1580         /*Set TS1 and TS2 to serial or parallel mode */
1581         stv0367ter_set_ts_mode(state, state->config->ts_mode);
1582         stv0367ter_set_clk_pol(state, state->config->clk_pol);
1583
1584         state->chip_id = stv0367_readreg(state, R367TER_ID);
1585         ter_state->first_lock = 0;
1586         ter_state->unlock_counter = 2;
1587
1588         return 0;
1589 }
1590
1591 static int stv0367ter_algo(struct dvb_frontend *fe)
1592 {
1593         struct dtv_frontend_properties *p = &fe->dtv_property_cache;
1594         struct stv0367_state *state = fe->demodulator_priv;
1595         struct stv0367ter_state *ter_state = state->ter_state;
1596         int offset = 0, tempo = 0;
1597         u8 u_var;
1598         u8 /*constell,*/ counter;
1599         s8 step;
1600         s32 timing_offset = 0;
1601         u32 trl_nomrate = 0, InternalFreq = 0, temp = 0;
1602
1603         dprintk("%s:\n", __func__);
1604
1605         ter_state->frequency = p->frequency;
1606         ter_state->force = FE_TER_FORCENONE
1607                         + stv0367_readbits(state, F367TER_FORCE) * 2;
1608         ter_state->if_iq_mode = state->config->if_iq_mode;
1609         switch (state->config->if_iq_mode) {
1610         case FE_TER_NORMAL_IF_TUNER:  /* Normal IF mode */
1611                 dprintk("ALGO: FE_TER_NORMAL_IF_TUNER selected\n");
1612                 stv0367_writebits(state, F367TER_TUNER_BB, 0);
1613                 stv0367_writebits(state, F367TER_LONGPATH_IF, 0);
1614                 stv0367_writebits(state, F367TER_DEMUX_SWAP, 0);
1615                 break;
1616         case FE_TER_LONGPATH_IF_TUNER:  /* Long IF mode */
1617                 dprintk("ALGO: FE_TER_LONGPATH_IF_TUNER selected\n");
1618                 stv0367_writebits(state, F367TER_TUNER_BB, 0);
1619                 stv0367_writebits(state, F367TER_LONGPATH_IF, 1);
1620                 stv0367_writebits(state, F367TER_DEMUX_SWAP, 1);
1621                 break;
1622         case FE_TER_IQ_TUNER:  /* IQ mode */
1623                 dprintk("ALGO: FE_TER_IQ_TUNER selected\n");
1624                 stv0367_writebits(state, F367TER_TUNER_BB, 1);
1625                 stv0367_writebits(state, F367TER_PPM_INVSEL, 0);
1626                 break;
1627         default:
1628                 printk(KERN_ERR "ALGO: wrong TUNER type selected\n");
1629                 return -EINVAL;
1630         }
1631
1632         usleep_range(5000, 7000);
1633
1634         switch (p->inversion) {
1635         case INVERSION_AUTO:
1636         default:
1637                 dprintk("%s: inversion AUTO\n", __func__);
1638                 if (ter_state->if_iq_mode == FE_TER_IQ_TUNER)
1639                         stv0367_writebits(state, F367TER_IQ_INVERT,
1640                                                 ter_state->sense);
1641                 else
1642                         stv0367_writebits(state, F367TER_INV_SPECTR,
1643                                                 ter_state->sense);
1644
1645                 break;
1646         case INVERSION_ON:
1647         case INVERSION_OFF:
1648                 if (ter_state->if_iq_mode == FE_TER_IQ_TUNER)
1649                         stv0367_writebits(state, F367TER_IQ_INVERT,
1650                                                 p->inversion);
1651                 else
1652                         stv0367_writebits(state, F367TER_INV_SPECTR,
1653                                                 p->inversion);
1654
1655                 break;
1656         }
1657
1658         if ((ter_state->if_iq_mode != FE_TER_NORMAL_IF_TUNER) &&
1659                                 (ter_state->pBW != ter_state->bw)) {
1660                 stv0367ter_agc_iir_lock_detect_set(state);
1661
1662                 /*set fine agc target to 180 for LPIF or IQ mode*/
1663                 /* set Q_AGCTarget */
1664                 stv0367_writebits(state, F367TER_SEL_IQNTAR, 1);
1665                 stv0367_writebits(state, F367TER_AUT_AGC_TARGET_MSB, 0xB);
1666                 /*stv0367_writebits(state,AUT_AGC_TARGET_LSB,0x04); */
1667
1668                 /* set Q_AGCTarget */
1669                 stv0367_writebits(state, F367TER_SEL_IQNTAR, 0);
1670                 stv0367_writebits(state, F367TER_AUT_AGC_TARGET_MSB, 0xB);
1671                 /*stv0367_writebits(state,AUT_AGC_TARGET_LSB,0x04); */
1672
1673                 if (!stv0367_iir_filt_init(state, ter_state->bw,
1674                                                 state->config->xtal))
1675                         return -EINVAL;
1676                 /*set IIR filter once for 6,7 or 8MHz BW*/
1677                 ter_state->pBW = ter_state->bw;
1678
1679                 stv0367ter_agc_iir_rst(state);
1680         }
1681
1682         if (ter_state->hierarchy == FE_TER_HIER_LOW_PRIO)
1683                 stv0367_writebits(state, F367TER_BDI_LPSEL, 0x01);
1684         else
1685                 stv0367_writebits(state, F367TER_BDI_LPSEL, 0x00);
1686
1687         InternalFreq = stv0367ter_get_mclk(state, state->config->xtal) / 1000;
1688         temp = (int)
1689                 ((((ter_state->bw * 64 * (1 << 15) * 100)
1690                                                 / (InternalFreq)) * 10) / 7);
1691
1692         stv0367_writebits(state, F367TER_TRL_NOMRATE_LSB, temp % 2);
1693         temp = temp / 2;
1694         stv0367_writebits(state, F367TER_TRL_NOMRATE_HI, temp / 256);
1695         stv0367_writebits(state, F367TER_TRL_NOMRATE_LO, temp % 256);
1696
1697         temp = stv0367_readbits(state, F367TER_TRL_NOMRATE_HI) * 512 +
1698                         stv0367_readbits(state, F367TER_TRL_NOMRATE_LO) * 2 +
1699                         stv0367_readbits(state, F367TER_TRL_NOMRATE_LSB);
1700         temp = (int)(((1 << 17) * ter_state->bw * 1000) / (7 * (InternalFreq)));
1701         stv0367_writebits(state, F367TER_GAIN_SRC_HI, temp / 256);
1702         stv0367_writebits(state, F367TER_GAIN_SRC_LO, temp % 256);
1703         temp = stv0367_readbits(state, F367TER_GAIN_SRC_HI) * 256 +
1704                         stv0367_readbits(state, F367TER_GAIN_SRC_LO);
1705
1706         temp = (int)
1707                 ((InternalFreq - state->config->if_khz) * (1 << 16)
1708                                                         / (InternalFreq));
1709
1710         dprintk("DEROT temp=0x%x\n", temp);
1711         stv0367_writebits(state, F367TER_INC_DEROT_HI, temp / 256);
1712         stv0367_writebits(state, F367TER_INC_DEROT_LO, temp % 256);
1713
1714         ter_state->echo_pos = 0;
1715         ter_state->ucblocks = 0; /* liplianin */
1716         ter_state->pBER = 0; /* liplianin */
1717         stv0367_writebits(state, F367TER_LONG_ECHO, ter_state->echo_pos);
1718
1719         if (stv0367ter_lock_algo(state) != FE_TER_LOCKOK)
1720                 return 0;
1721
1722         ter_state->state = FE_TER_LOCKOK;
1723
1724         ter_state->mode = stv0367_readbits(state, F367TER_SYR_MODE);
1725         ter_state->guard = stv0367_readbits(state, F367TER_SYR_GUARD);
1726
1727         ter_state->first_lock = 1; /* we know sense now :) */
1728
1729         ter_state->agc_val =
1730                         (stv0367_readbits(state, F367TER_AGC1_VAL_LO) << 16) +
1731                         (stv0367_readbits(state, F367TER_AGC1_VAL_HI) << 24) +
1732                         stv0367_readbits(state, F367TER_AGC2_VAL_LO) +
1733                         (stv0367_readbits(state, F367TER_AGC2_VAL_HI) << 8);
1734
1735         /* Carrier offset calculation */
1736         stv0367_writebits(state, F367TER_FREEZE, 1);
1737         offset = (stv0367_readbits(state, F367TER_CRL_FOFFSET_VHI) << 16) ;
1738         offset += (stv0367_readbits(state, F367TER_CRL_FOFFSET_HI) << 8);
1739         offset += (stv0367_readbits(state, F367TER_CRL_FOFFSET_LO));
1740         stv0367_writebits(state, F367TER_FREEZE, 0);
1741         if (offset > 8388607)
1742                 offset -= 16777216;
1743
1744         offset = offset * 2 / 16384;
1745
1746         if (ter_state->mode == FE_TER_MODE_2K)
1747                 offset = (offset * 4464) / 1000;/*** 1 FFT BIN=4.464khz***/
1748         else if (ter_state->mode == FE_TER_MODE_4K)
1749                 offset = (offset * 223) / 100;/*** 1 FFT BIN=2.23khz***/
1750         else  if (ter_state->mode == FE_TER_MODE_8K)
1751                 offset = (offset * 111) / 100;/*** 1 FFT BIN=1.1khz***/
1752
1753         if (stv0367_readbits(state, F367TER_PPM_INVSEL) == 1) {
1754                 if ((stv0367_readbits(state, F367TER_INV_SPECTR) ==
1755                                 (stv0367_readbits(state,
1756                                         F367TER_STATUS_INV_SPECRUM) == 1)))
1757                         offset = offset * -1;
1758         }
1759
1760         if (ter_state->bw == 6)
1761                 offset = (offset * 6) / 8;
1762         else if (ter_state->bw == 7)
1763                 offset = (offset * 7) / 8;
1764
1765         ter_state->frequency += offset;
1766
1767         tempo = 10;  /* exit even if timing_offset stays null */
1768         while ((timing_offset == 0) && (tempo > 0)) {
1769                 usleep_range(10000, 20000);     /*was 20ms  */
1770                 /* fine tuning of timing offset if required */
1771                 timing_offset = stv0367_readbits(state, F367TER_TRL_TOFFSET_LO)
1772                                 + 256 * stv0367_readbits(state,
1773                                                         F367TER_TRL_TOFFSET_HI);
1774                 if (timing_offset >= 32768)
1775                         timing_offset -= 65536;
1776                 trl_nomrate = (512 * stv0367_readbits(state,
1777                                                         F367TER_TRL_NOMRATE_HI)
1778                         + stv0367_readbits(state, F367TER_TRL_NOMRATE_LO) * 2
1779                         + stv0367_readbits(state, F367TER_TRL_NOMRATE_LSB));
1780
1781                 timing_offset = ((signed)(1000000 / trl_nomrate) *
1782                                                         timing_offset) / 2048;
1783                 tempo--;
1784         }
1785
1786         if (timing_offset <= 0) {
1787                 timing_offset = (timing_offset - 11) / 22;
1788                 step = -1;
1789         } else {
1790                 timing_offset = (timing_offset + 11) / 22;
1791                 step = 1;
1792         }
1793
1794         for (counter = 0; counter < abs(timing_offset); counter++) {
1795                 trl_nomrate += step;
1796                 stv0367_writebits(state, F367TER_TRL_NOMRATE_LSB,
1797                                                 trl_nomrate % 2);
1798                 stv0367_writebits(state, F367TER_TRL_NOMRATE_LO,
1799                                                 trl_nomrate / 2);
1800                 usleep_range(1000, 2000);
1801         }
1802
1803         usleep_range(5000, 6000);
1804         /* unlocks could happen in case of trl centring big step,
1805         then a core off/on restarts demod */
1806         u_var = stv0367_readbits(state, F367TER_LK);
1807
1808         if (!u_var) {
1809                 stv0367_writebits(state, F367TER_CORE_ACTIVE, 0);
1810                 msleep(20);
1811                 stv0367_writebits(state, F367TER_CORE_ACTIVE, 1);
1812         }
1813
1814         return 0;
1815 }
1816
1817 static int stv0367ter_set_frontend(struct dvb_frontend *fe)
1818 {
1819         struct dtv_frontend_properties *p = &fe->dtv_property_cache;
1820         struct stv0367_state *state = fe->demodulator_priv;
1821         struct stv0367ter_state *ter_state = state->ter_state;
1822
1823         /*u8 trials[2]; */
1824         s8 num_trials, index;
1825         u8 SenseTrials[] = { INVERSION_ON, INVERSION_OFF };
1826
1827         stv0367ter_init(fe);
1828
1829         if (fe->ops.tuner_ops.set_params) {
1830                 if (fe->ops.i2c_gate_ctrl)
1831                         fe->ops.i2c_gate_ctrl(fe, 1);
1832                 fe->ops.tuner_ops.set_params(fe);
1833                 if (fe->ops.i2c_gate_ctrl)
1834                         fe->ops.i2c_gate_ctrl(fe, 0);
1835         }
1836
1837         switch (p->transmission_mode) {
1838         default:
1839         case TRANSMISSION_MODE_AUTO:
1840         case TRANSMISSION_MODE_2K:
1841                 ter_state->mode = FE_TER_MODE_2K;
1842                 break;
1843 /*      case TRANSMISSION_MODE_4K:
1844                 pLook.mode = FE_TER_MODE_4K;
1845                 break;*/
1846         case TRANSMISSION_MODE_8K:
1847                 ter_state->mode = FE_TER_MODE_8K;
1848                 break;
1849         }
1850
1851         switch (p->guard_interval) {
1852         default:
1853         case GUARD_INTERVAL_1_32:
1854         case GUARD_INTERVAL_1_16:
1855         case GUARD_INTERVAL_1_8:
1856         case GUARD_INTERVAL_1_4:
1857                 ter_state->guard = p->guard_interval;
1858                 break;
1859         case GUARD_INTERVAL_AUTO:
1860                 ter_state->guard = GUARD_INTERVAL_1_32;
1861                 break;
1862         }
1863
1864         switch (p->bandwidth_hz) {
1865         case 6000000:
1866                 ter_state->bw = FE_TER_CHAN_BW_6M;
1867                 break;
1868         case 7000000:
1869                 ter_state->bw = FE_TER_CHAN_BW_7M;
1870                 break;
1871         case 8000000:
1872         default:
1873                 ter_state->bw = FE_TER_CHAN_BW_8M;
1874         }
1875
1876         ter_state->hierarchy = FE_TER_HIER_NONE;
1877
1878         switch (p->inversion) {
1879         case INVERSION_OFF:
1880         case INVERSION_ON:
1881                 num_trials = 1;
1882                 break;
1883         default:
1884                 num_trials = 2;
1885                 if (ter_state->first_lock)
1886                         num_trials = 1;
1887                 break;
1888         }
1889
1890         ter_state->state = FE_TER_NOLOCK;
1891         index = 0;
1892
1893         while (((index) < num_trials) && (ter_state->state != FE_TER_LOCKOK)) {
1894                 if (!ter_state->first_lock) {
1895                         if (p->inversion == INVERSION_AUTO)
1896                                 ter_state->sense = SenseTrials[index];
1897
1898                 }
1899                 stv0367ter_algo(fe);
1900
1901                 if ((ter_state->state == FE_TER_LOCKOK) &&
1902                                 (p->inversion == INVERSION_AUTO) &&
1903                                                                 (index == 1)) {
1904                         /* invert spectrum sense */
1905                         SenseTrials[index] = SenseTrials[0];
1906                         SenseTrials[(index + 1) % 2] = (SenseTrials[1] + 1) % 2;
1907                 }
1908
1909                 index++;
1910         }
1911
1912         return 0;
1913 }
1914
1915 static int stv0367ter_read_ucblocks(struct dvb_frontend *fe, u32 *ucblocks)
1916 {
1917         struct stv0367_state *state = fe->demodulator_priv;
1918         struct stv0367ter_state *ter_state = state->ter_state;
1919         u32 errs = 0;
1920
1921         /*wait for counting completion*/
1922         if (stv0367_readbits(state, F367TER_SFERRC_OLDVALUE) == 0) {
1923                 errs =
1924                         ((u32)stv0367_readbits(state, F367TER_ERR_CNT1)
1925                         * (1 << 16))
1926                         + ((u32)stv0367_readbits(state, F367TER_ERR_CNT1_HI)
1927                         * (1 << 8))
1928                         + ((u32)stv0367_readbits(state, F367TER_ERR_CNT1_LO));
1929                 ter_state->ucblocks = errs;
1930         }
1931
1932         (*ucblocks) = ter_state->ucblocks;
1933
1934         return 0;
1935 }
1936
1937 static int stv0367ter_get_frontend(struct dvb_frontend *fe,
1938                                    struct dtv_frontend_properties *p)
1939 {
1940         struct stv0367_state *state = fe->demodulator_priv;
1941         struct stv0367ter_state *ter_state = state->ter_state;
1942         enum stv0367_ter_mode mode;
1943         int constell = 0,/* snr = 0,*/ Data = 0;
1944
1945         p->frequency = stv0367_get_tuner_freq(fe);
1946         if ((int)p->frequency < 0)
1947                 p->frequency = -p->frequency;
1948
1949         constell = stv0367_readbits(state, F367TER_TPS_CONST);
1950         if (constell == 0)
1951                 p->modulation = QPSK;
1952         else if (constell == 1)
1953                 p->modulation = QAM_16;
1954         else
1955                 p->modulation = QAM_64;
1956
1957         p->inversion = stv0367_readbits(state, F367TER_INV_SPECTR);
1958
1959         /* Get the Hierarchical mode */
1960         Data = stv0367_readbits(state, F367TER_TPS_HIERMODE);
1961
1962         switch (Data) {
1963         case 0:
1964                 p->hierarchy = HIERARCHY_NONE;
1965                 break;
1966         case 1:
1967                 p->hierarchy = HIERARCHY_1;
1968                 break;
1969         case 2:
1970                 p->hierarchy = HIERARCHY_2;
1971                 break;
1972         case 3:
1973                 p->hierarchy = HIERARCHY_4;
1974                 break;
1975         default:
1976                 p->hierarchy = HIERARCHY_AUTO;
1977                 break; /* error */
1978         }
1979
1980         /* Get the FEC Rate */
1981         if (ter_state->hierarchy == FE_TER_HIER_LOW_PRIO)
1982                 Data = stv0367_readbits(state, F367TER_TPS_LPCODE);
1983         else
1984                 Data = stv0367_readbits(state, F367TER_TPS_HPCODE);
1985
1986         switch (Data) {
1987         case 0:
1988                 p->code_rate_HP = FEC_1_2;
1989                 break;
1990         case 1:
1991                 p->code_rate_HP = FEC_2_3;
1992                 break;
1993         case 2:
1994                 p->code_rate_HP = FEC_3_4;
1995                 break;
1996         case 3:
1997                 p->code_rate_HP = FEC_5_6;
1998                 break;
1999         case 4:
2000                 p->code_rate_HP = FEC_7_8;
2001                 break;
2002         default:
2003                 p->code_rate_HP = FEC_AUTO;
2004                 break; /* error */
2005         }
2006
2007         mode = stv0367_readbits(state, F367TER_SYR_MODE);
2008
2009         switch (mode) {
2010         case FE_TER_MODE_2K:
2011                 p->transmission_mode = TRANSMISSION_MODE_2K;
2012                 break;
2013 /*      case FE_TER_MODE_4K:
2014                 p->transmission_mode = TRANSMISSION_MODE_4K;
2015                 break;*/
2016         case FE_TER_MODE_8K:
2017                 p->transmission_mode = TRANSMISSION_MODE_8K;
2018                 break;
2019         default:
2020                 p->transmission_mode = TRANSMISSION_MODE_AUTO;
2021         }
2022
2023         p->guard_interval = stv0367_readbits(state, F367TER_SYR_GUARD);
2024
2025         return 0;
2026 }
2027
2028 static int stv0367ter_read_snr(struct dvb_frontend *fe, u16 *snr)
2029 {
2030         struct stv0367_state *state = fe->demodulator_priv;
2031         u32 snru32 = 0;
2032         int cpt = 0;
2033         u8 cut = stv0367_readbits(state, F367TER_IDENTIFICATIONREG);
2034
2035         while (cpt < 10) {
2036                 usleep_range(2000, 3000);
2037                 if (cut == 0x50) /*cut 1.0 cut 1.1*/
2038                         snru32 += stv0367_readbits(state, F367TER_CHCSNR) / 4;
2039                 else /*cu2.0*/
2040                         snru32 += 125 * stv0367_readbits(state, F367TER_CHCSNR);
2041
2042                 cpt++;
2043         }
2044
2045         snru32 /= 10;/*average on 10 values*/
2046
2047         *snr = snru32 / 1000;
2048
2049         return 0;
2050 }
2051
2052 #if 0
2053 static int stv0367ter_status(struct dvb_frontend *fe)
2054 {
2055
2056         struct stv0367_state *state = fe->demodulator_priv;
2057         struct stv0367ter_state *ter_state = state->ter_state;
2058         int locked = FALSE;
2059
2060         locked = (stv0367_readbits(state, F367TER_LK));
2061         if (!locked)
2062                 ter_state->unlock_counter += 1;
2063         else
2064                 ter_state->unlock_counter = 0;
2065
2066         if (ter_state->unlock_counter > 2) {
2067                 if (!stv0367_readbits(state, F367TER_TPS_LOCK) ||
2068                                 (!stv0367_readbits(state, F367TER_LK))) {
2069                         stv0367_writebits(state, F367TER_CORE_ACTIVE, 0);
2070                         usleep_range(2000, 3000);
2071                         stv0367_writebits(state, F367TER_CORE_ACTIVE, 1);
2072                         msleep(350);
2073                         locked = (stv0367_readbits(state, F367TER_TPS_LOCK)) &&
2074                                         (stv0367_readbits(state, F367TER_LK));
2075                 }
2076
2077         }
2078
2079         return locked;
2080 }
2081 #endif
2082 static int stv0367ter_read_status(struct dvb_frontend *fe,
2083                                   enum fe_status *status)
2084 {
2085         struct stv0367_state *state = fe->demodulator_priv;
2086
2087         dprintk("%s:\n", __func__);
2088
2089         *status = 0;
2090
2091         if (stv0367_readbits(state, F367TER_LK)) {
2092                 *status |= FE_HAS_LOCK;
2093                 dprintk("%s: stv0367 has locked\n", __func__);
2094         }
2095
2096         return 0;
2097 }
2098
2099 static int stv0367ter_read_ber(struct dvb_frontend *fe, u32 *ber)
2100 {
2101         struct stv0367_state *state = fe->demodulator_priv;
2102         struct stv0367ter_state *ter_state = state->ter_state;
2103         u32 Errors = 0, tber = 0, temporary = 0;
2104         int abc = 0, def = 0;
2105
2106
2107         /*wait for counting completion*/
2108         if (stv0367_readbits(state, F367TER_SFERRC_OLDVALUE) == 0)
2109                 Errors = ((u32)stv0367_readbits(state, F367TER_SFEC_ERR_CNT)
2110                         * (1 << 16))
2111                         + ((u32)stv0367_readbits(state, F367TER_SFEC_ERR_CNT_HI)
2112                         * (1 << 8))
2113                         + ((u32)stv0367_readbits(state,
2114                                                 F367TER_SFEC_ERR_CNT_LO));
2115         /*measurement not completed, load previous value*/
2116         else {
2117                 tber = ter_state->pBER;
2118                 return 0;
2119         }
2120
2121         abc = stv0367_readbits(state, F367TER_SFEC_ERR_SOURCE);
2122         def = stv0367_readbits(state, F367TER_SFEC_NUM_EVENT);
2123
2124         if (Errors == 0) {
2125                 tber = 0;
2126         } else if (abc == 0x7) {
2127                 if (Errors <= 4) {
2128                         temporary = (Errors * 1000000000) / (8 * (1 << 14));
2129                         temporary =  temporary;
2130                 } else if (Errors <= 42) {
2131                         temporary = (Errors * 100000000) / (8 * (1 << 14));
2132                         temporary = temporary * 10;
2133                 } else if (Errors <= 429) {
2134                         temporary = (Errors * 10000000) / (8 * (1 << 14));
2135                         temporary = temporary * 100;
2136                 } else if (Errors <= 4294) {
2137                         temporary = (Errors * 1000000) / (8 * (1 << 14));
2138                         temporary = temporary * 1000;
2139                 } else if (Errors <= 42949) {
2140                         temporary = (Errors * 100000) / (8 * (1 << 14));
2141                         temporary = temporary * 10000;
2142                 } else if (Errors <= 429496) {
2143                         temporary = (Errors * 10000) / (8 * (1 << 14));
2144                         temporary = temporary * 100000;
2145                 } else { /*if (Errors<4294967) 2^22 max error*/
2146                         temporary = (Errors * 1000) / (8 * (1 << 14));
2147                         temporary = temporary * 100000; /* still to *10 */
2148                 }
2149
2150                 /* Byte error*/
2151                 if (def == 2)
2152                         /*tber=Errors/(8*(1 <<14));*/
2153                         tber = temporary;
2154                 else if (def == 3)
2155                         /*tber=Errors/(8*(1 <<16));*/
2156                         tber = temporary / 4;
2157                 else if (def == 4)
2158                         /*tber=Errors/(8*(1 <<18));*/
2159                         tber = temporary / 16;
2160                 else if (def == 5)
2161                         /*tber=Errors/(8*(1 <<20));*/
2162                         tber = temporary / 64;
2163                 else if (def == 6)
2164                         /*tber=Errors/(8*(1 <<22));*/
2165                         tber = temporary / 256;
2166                 else
2167                         /* should not pass here*/
2168                         tber = 0;
2169
2170                 if ((Errors < 4294967) && (Errors > 429496))
2171                         tber *= 10;
2172
2173         }
2174
2175         /* save actual value */
2176         ter_state->pBER = tber;
2177
2178         (*ber) = tber;
2179
2180         return 0;
2181 }
2182 #if 0
2183 static u32 stv0367ter_get_per(struct stv0367_state *state)
2184 {
2185         struct stv0367ter_state *ter_state = state->ter_state;
2186         u32 Errors = 0, Per = 0, temporary = 0;
2187         int abc = 0, def = 0, cpt = 0;
2188
2189         while (((stv0367_readbits(state, F367TER_SFERRC_OLDVALUE) == 1) &&
2190                         (cpt < 400)) || ((Errors == 0) && (cpt < 400))) {
2191                 usleep_range(1000, 2000);
2192                 Errors = ((u32)stv0367_readbits(state, F367TER_ERR_CNT1)
2193                         * (1 << 16))
2194                         + ((u32)stv0367_readbits(state, F367TER_ERR_CNT1_HI)
2195                         * (1 << 8))
2196                         + ((u32)stv0367_readbits(state, F367TER_ERR_CNT1_LO));
2197                 cpt++;
2198         }
2199         abc = stv0367_readbits(state, F367TER_ERR_SRC1);
2200         def = stv0367_readbits(state, F367TER_NUM_EVT1);
2201
2202         if (Errors == 0)
2203                 Per = 0;
2204         else if (abc == 0x9) {
2205                 if (Errors <= 4) {
2206                         temporary = (Errors * 1000000000) / (8 * (1 << 8));
2207                         temporary =  temporary;
2208                 } else if (Errors <= 42) {
2209                         temporary = (Errors * 100000000) / (8 * (1 << 8));
2210                         temporary = temporary * 10;
2211                 } else if (Errors <= 429) {
2212                         temporary = (Errors * 10000000) / (8 * (1 << 8));
2213                         temporary = temporary * 100;
2214                 } else if (Errors <= 4294) {
2215                         temporary = (Errors * 1000000) / (8 * (1 << 8));
2216                         temporary = temporary * 1000;
2217                 } else if (Errors <= 42949) {
2218                         temporary = (Errors * 100000) / (8 * (1 << 8));
2219                         temporary = temporary * 10000;
2220                 } else { /*if(Errors<=429496)  2^16 errors max*/
2221                         temporary = (Errors * 10000) / (8 * (1 << 8));
2222                         temporary = temporary * 100000;
2223                 }
2224
2225                 /* pkt error*/
2226                 if (def == 2)
2227                         /*Per=Errors/(1 << 8);*/
2228                         Per = temporary;
2229                 else if (def == 3)
2230                         /*Per=Errors/(1 << 10);*/
2231                         Per = temporary / 4;
2232                 else if (def == 4)
2233                         /*Per=Errors/(1 << 12);*/
2234                         Per = temporary / 16;
2235                 else if (def == 5)
2236                         /*Per=Errors/(1 << 14);*/
2237                         Per = temporary / 64;
2238                 else if (def == 6)
2239                         /*Per=Errors/(1 << 16);*/
2240                         Per = temporary / 256;
2241                 else
2242                         Per = 0;
2243
2244         }
2245         /* save actual value */
2246         ter_state->pPER = Per;
2247
2248         return Per;
2249 }
2250 #endif
2251 static int stv0367_get_tune_settings(struct dvb_frontend *fe,
2252                                         struct dvb_frontend_tune_settings
2253                                         *fe_tune_settings)
2254 {
2255         fe_tune_settings->min_delay_ms = 1000;
2256         fe_tune_settings->step_size = 0;
2257         fe_tune_settings->max_drift = 0;
2258
2259         return 0;
2260 }
2261
2262 static void stv0367_release(struct dvb_frontend *fe)
2263 {
2264         struct stv0367_state *state = fe->demodulator_priv;
2265
2266         kfree(state->ter_state);
2267         kfree(state->cab_state);
2268         kfree(state);
2269 }
2270
2271 static const struct dvb_frontend_ops stv0367ter_ops = {
2272         .delsys = { SYS_DVBT },
2273         .info = {
2274                 .name                   = "ST STV0367 DVB-T",
2275                 .frequency_min          = 47000000,
2276                 .frequency_max          = 862000000,
2277                 .frequency_stepsize     = 15625,
2278                 .frequency_tolerance    = 0,
2279                 .caps = FE_CAN_FEC_1_2 | FE_CAN_FEC_2_3 |
2280                         FE_CAN_FEC_3_4 | FE_CAN_FEC_5_6 | FE_CAN_FEC_7_8 |
2281                         FE_CAN_FEC_AUTO |
2282                         FE_CAN_QPSK | FE_CAN_QAM_16 | FE_CAN_QAM_64 |
2283                         FE_CAN_QAM_128 | FE_CAN_QAM_256 | FE_CAN_QAM_AUTO |
2284                         FE_CAN_TRANSMISSION_MODE_AUTO | FE_CAN_RECOVER |
2285                         FE_CAN_INVERSION_AUTO |
2286                         FE_CAN_MUTE_TS
2287         },
2288         .release = stv0367_release,
2289         .init = stv0367ter_init,
2290         .sleep = stv0367ter_sleep,
2291         .i2c_gate_ctrl = stv0367ter_gate_ctrl,
2292         .set_frontend = stv0367ter_set_frontend,
2293         .get_frontend = stv0367ter_get_frontend,
2294         .get_tune_settings = stv0367_get_tune_settings,
2295         .read_status = stv0367ter_read_status,
2296         .read_ber = stv0367ter_read_ber,/* too slow */
2297 /*      .read_signal_strength = stv0367_read_signal_strength,*/
2298         .read_snr = stv0367ter_read_snr,
2299         .read_ucblocks = stv0367ter_read_ucblocks,
2300 };
2301
2302 struct dvb_frontend *stv0367ter_attach(const struct stv0367_config *config,
2303                                    struct i2c_adapter *i2c)
2304 {
2305         struct stv0367_state *state = NULL;
2306         struct stv0367ter_state *ter_state = NULL;
2307
2308         /* allocate memory for the internal state */
2309         state = kzalloc(sizeof(struct stv0367_state), GFP_KERNEL);
2310         if (state == NULL)
2311                 goto error;
2312         ter_state = kzalloc(sizeof(struct stv0367ter_state), GFP_KERNEL);
2313         if (ter_state == NULL)
2314                 goto error;
2315
2316         /* setup the state */
2317         state->i2c = i2c;
2318         state->config = config;
2319         state->ter_state = ter_state;
2320         state->fe.ops = stv0367ter_ops;
2321         state->fe.demodulator_priv = state;
2322         state->chip_id = stv0367_readreg(state, 0xf000);
2323
2324         dprintk("%s: chip_id = 0x%x\n", __func__, state->chip_id);
2325
2326         /* check if the demod is there */
2327         if ((state->chip_id != 0x50) && (state->chip_id != 0x60))
2328                 goto error;
2329
2330         return &state->fe;
2331
2332 error:
2333         kfree(ter_state);
2334         kfree(state);
2335         return NULL;
2336 }
2337 EXPORT_SYMBOL(stv0367ter_attach);
2338
2339 static int stv0367cab_gate_ctrl(struct dvb_frontend *fe, int enable)
2340 {
2341         struct stv0367_state *state = fe->demodulator_priv;
2342
2343         dprintk("%s:\n", __func__);
2344
2345         stv0367_writebits(state, F367CAB_I2CT_ON, (enable > 0) ? 1 : 0);
2346
2347         return 0;
2348 }
2349
2350 static u32 stv0367cab_get_mclk(struct dvb_frontend *fe, u32 ExtClk_Hz)
2351 {
2352         struct stv0367_state *state = fe->demodulator_priv;
2353         u32 mclk_Hz = 0;/* master clock frequency (Hz) */
2354         u32 M, N, P;
2355
2356
2357         if (stv0367_readbits(state, F367CAB_BYPASS_PLLXN) == 0) {
2358                 N = (u32)stv0367_readbits(state, F367CAB_PLL_NDIV);
2359                 if (N == 0)
2360                         N = N + 1;
2361
2362                 M = (u32)stv0367_readbits(state, F367CAB_PLL_MDIV);
2363                 if (M == 0)
2364                         M = M + 1;
2365
2366                 P = (u32)stv0367_readbits(state, F367CAB_PLL_PDIV);
2367
2368                 if (P > 5)
2369                         P = 5;
2370
2371                 mclk_Hz = ((ExtClk_Hz / 2) * N) / (M * (1 << P));
2372                 dprintk("stv0367cab_get_mclk BYPASS_PLLXN mclk_Hz=%d\n",
2373                                                                 mclk_Hz);
2374         } else
2375                 mclk_Hz = ExtClk_Hz;
2376
2377         dprintk("stv0367cab_get_mclk final mclk_Hz=%d\n", mclk_Hz);
2378
2379         return mclk_Hz;
2380 }
2381
2382 static u32 stv0367cab_get_adc_freq(struct dvb_frontend *fe, u32 ExtClk_Hz)
2383 {
2384         u32 ADCClk_Hz = ExtClk_Hz;
2385
2386         ADCClk_Hz = stv0367cab_get_mclk(fe, ExtClk_Hz);
2387
2388         return ADCClk_Hz;
2389 }
2390
2391 static enum stv0367cab_mod stv0367cab_SetQamSize(struct stv0367_state *state,
2392                                                  u32 SymbolRate,
2393                                                  enum stv0367cab_mod QAMSize)
2394 {
2395         /* Set QAM size */
2396         stv0367_writebits(state, F367CAB_QAM_MODE, QAMSize);
2397
2398         /* Set Registers settings specific to the QAM size */
2399         switch (QAMSize) {
2400         case FE_CAB_MOD_QAM4:
2401                 stv0367_writereg(state, R367CAB_IQDEM_ADJ_AGC_REF, 0x00);
2402                 break;
2403         case FE_CAB_MOD_QAM16:
2404                 stv0367_writereg(state, R367CAB_AGC_PWR_REF_L, 0x64);
2405                 stv0367_writereg(state, R367CAB_IQDEM_ADJ_AGC_REF, 0x00);
2406                 stv0367_writereg(state, R367CAB_FSM_STATE, 0x90);
2407                 stv0367_writereg(state, R367CAB_EQU_CTR_LPF_GAIN, 0xc1);
2408                 stv0367_writereg(state, R367CAB_EQU_CRL_LPF_GAIN, 0xa7);
2409                 stv0367_writereg(state, R367CAB_EQU_CRL_LD_SEN, 0x95);
2410                 stv0367_writereg(state, R367CAB_EQU_CRL_LIMITER, 0x40);
2411                 stv0367_writereg(state, R367CAB_EQU_PNT_GAIN, 0x8a);
2412                 break;
2413         case FE_CAB_MOD_QAM32:
2414                 stv0367_writereg(state, R367CAB_IQDEM_ADJ_AGC_REF, 0x00);
2415                 stv0367_writereg(state, R367CAB_AGC_PWR_REF_L, 0x6e);
2416                 stv0367_writereg(state, R367CAB_FSM_STATE, 0xb0);
2417                 stv0367_writereg(state, R367CAB_EQU_CTR_LPF_GAIN, 0xc1);
2418                 stv0367_writereg(state, R367CAB_EQU_CRL_LPF_GAIN, 0xb7);
2419                 stv0367_writereg(state, R367CAB_EQU_CRL_LD_SEN, 0x9d);
2420                 stv0367_writereg(state, R367CAB_EQU_CRL_LIMITER, 0x7f);
2421                 stv0367_writereg(state, R367CAB_EQU_PNT_GAIN, 0xa7);
2422                 break;
2423         case FE_CAB_MOD_QAM64:
2424                 stv0367_writereg(state, R367CAB_IQDEM_ADJ_AGC_REF, 0x82);
2425                 stv0367_writereg(state, R367CAB_AGC_PWR_REF_L, 0x5a);
2426                 if (SymbolRate > 45000000) {
2427                         stv0367_writereg(state, R367CAB_FSM_STATE, 0xb0);
2428                         stv0367_writereg(state, R367CAB_EQU_CTR_LPF_GAIN, 0xc1);
2429                         stv0367_writereg(state, R367CAB_EQU_CRL_LPF_GAIN, 0xa5);
2430                 } else if (SymbolRate > 25000000) {
2431                         stv0367_writereg(state, R367CAB_FSM_STATE, 0xa0);
2432                         stv0367_writereg(state, R367CAB_EQU_CTR_LPF_GAIN, 0xc1);
2433                         stv0367_writereg(state, R367CAB_EQU_CRL_LPF_GAIN, 0xa6);
2434                 } else {
2435                         stv0367_writereg(state, R367CAB_FSM_STATE, 0xa0);
2436                         stv0367_writereg(state, R367CAB_EQU_CTR_LPF_GAIN, 0xd1);
2437                         stv0367_writereg(state, R367CAB_EQU_CRL_LPF_GAIN, 0xa7);
2438                 }
2439                 stv0367_writereg(state, R367CAB_EQU_CRL_LD_SEN, 0x95);
2440                 stv0367_writereg(state, R367CAB_EQU_CRL_LIMITER, 0x40);
2441                 stv0367_writereg(state, R367CAB_EQU_PNT_GAIN, 0x99);
2442                 break;
2443         case FE_CAB_MOD_QAM128:
2444                 stv0367_writereg(state, R367CAB_IQDEM_ADJ_AGC_REF, 0x00);
2445                 stv0367_writereg(state, R367CAB_AGC_PWR_REF_L, 0x76);
2446                 stv0367_writereg(state, R367CAB_FSM_STATE, 0x90);
2447                 stv0367_writereg(state, R367CAB_EQU_CTR_LPF_GAIN, 0xb1);
2448                 if (SymbolRate > 45000000)
2449                         stv0367_writereg(state, R367CAB_EQU_CRL_LPF_GAIN, 0xa7);
2450                 else if (SymbolRate > 25000000)
2451                         stv0367_writereg(state, R367CAB_EQU_CRL_LPF_GAIN, 0xa6);
2452                 else
2453                         stv0367_writereg(state, R367CAB_EQU_CRL_LPF_GAIN, 0x97);
2454
2455                 stv0367_writereg(state, R367CAB_EQU_CRL_LD_SEN, 0x8e);
2456                 stv0367_writereg(state, R367CAB_EQU_CRL_LIMITER, 0x7f);
2457                 stv0367_writereg(state, R367CAB_EQU_PNT_GAIN, 0xa7);
2458                 break;
2459         case FE_CAB_MOD_QAM256:
2460                 stv0367_writereg(state, R367CAB_IQDEM_ADJ_AGC_REF, 0x94);
2461                 stv0367_writereg(state, R367CAB_AGC_PWR_REF_L, 0x5a);
2462                 stv0367_writereg(state, R367CAB_FSM_STATE, 0xa0);
2463                 if (SymbolRate > 45000000)
2464                         stv0367_writereg(state, R367CAB_EQU_CTR_LPF_GAIN, 0xc1);
2465                 else if (SymbolRate > 25000000)
2466                         stv0367_writereg(state, R367CAB_EQU_CTR_LPF_GAIN, 0xc1);
2467                 else
2468                         stv0367_writereg(state, R367CAB_EQU_CTR_LPF_GAIN, 0xd1);
2469
2470                 stv0367_writereg(state, R367CAB_EQU_CRL_LPF_GAIN, 0xa7);
2471                 stv0367_writereg(state, R367CAB_EQU_CRL_LD_SEN, 0x85);
2472                 stv0367_writereg(state, R367CAB_EQU_CRL_LIMITER, 0x40);
2473                 stv0367_writereg(state, R367CAB_EQU_PNT_GAIN, 0xa7);
2474                 break;
2475         case FE_CAB_MOD_QAM512:
2476                 stv0367_writereg(state, R367CAB_IQDEM_ADJ_AGC_REF, 0x00);
2477                 break;
2478         case FE_CAB_MOD_QAM1024:
2479                 stv0367_writereg(state, R367CAB_IQDEM_ADJ_AGC_REF, 0x00);
2480                 break;
2481         default:
2482                 break;
2483         }
2484
2485         return QAMSize;
2486 }
2487
2488 static u32 stv0367cab_set_derot_freq(struct stv0367_state *state,
2489                                         u32 adc_hz, s32 derot_hz)
2490 {
2491         u32 sampled_if = 0;
2492         u32 adc_khz;
2493
2494         adc_khz = adc_hz / 1000;
2495
2496         dprintk("%s: adc_hz=%d derot_hz=%d\n", __func__, adc_hz, derot_hz);
2497
2498         if (adc_khz != 0) {
2499                 if (derot_hz < 1000000)
2500                         derot_hz = adc_hz / 4; /* ZIF operation */
2501                 if (derot_hz > adc_hz)
2502                         derot_hz = derot_hz - adc_hz;
2503                 sampled_if = (u32)derot_hz / 1000;
2504                 sampled_if *= 32768;
2505                 sampled_if /= adc_khz;
2506                 sampled_if *= 256;
2507         }
2508
2509         if (sampled_if > 8388607)
2510                 sampled_if = 8388607;
2511
2512         dprintk("%s: sampled_if=0x%x\n", __func__, sampled_if);
2513
2514         stv0367_writereg(state, R367CAB_MIX_NCO_LL, sampled_if);
2515         stv0367_writereg(state, R367CAB_MIX_NCO_HL, (sampled_if >> 8));
2516         stv0367_writebits(state, F367CAB_MIX_NCO_INC_HH, (sampled_if >> 16));
2517
2518         return derot_hz;
2519 }
2520
2521 static u32 stv0367cab_get_derot_freq(struct stv0367_state *state, u32 adc_hz)
2522 {
2523         u32 sampled_if;
2524
2525         sampled_if = stv0367_readbits(state, F367CAB_MIX_NCO_INC_LL) +
2526                         (stv0367_readbits(state, F367CAB_MIX_NCO_INC_HL) << 8) +
2527                         (stv0367_readbits(state, F367CAB_MIX_NCO_INC_HH) << 16);
2528
2529         sampled_if /= 256;
2530         sampled_if *= (adc_hz / 1000);
2531         sampled_if += 1;
2532         sampled_if /= 32768;
2533
2534         return sampled_if;
2535 }
2536
2537 static u32 stv0367cab_set_srate(struct stv0367_state *state, u32 adc_hz,
2538                         u32 mclk_hz, u32 SymbolRate,
2539                         enum stv0367cab_mod QAMSize)
2540 {
2541         u32 QamSizeCorr = 0;
2542         u32 u32_tmp = 0, u32_tmp1 = 0;
2543         u32 adp_khz;
2544
2545         dprintk("%s:\n", __func__);
2546
2547         /* Set Correction factor of SRC gain */
2548         switch (QAMSize) {
2549         case FE_CAB_MOD_QAM4:
2550                 QamSizeCorr = 1110;
2551                 break;
2552         case FE_CAB_MOD_QAM16:
2553                 QamSizeCorr = 1032;
2554                 break;
2555         case FE_CAB_MOD_QAM32:
2556                 QamSizeCorr =  954;
2557                 break;
2558         case FE_CAB_MOD_QAM64:
2559                 QamSizeCorr =  983;
2560                 break;
2561         case FE_CAB_MOD_QAM128:
2562                 QamSizeCorr =  957;
2563                 break;
2564         case FE_CAB_MOD_QAM256:
2565                 QamSizeCorr =  948;
2566                 break;
2567         case FE_CAB_MOD_QAM512:
2568                 QamSizeCorr =    0;
2569                 break;
2570         case FE_CAB_MOD_QAM1024:
2571                 QamSizeCorr =  944;
2572                 break;
2573         default:
2574                 break;
2575         }
2576
2577         /* Transfer ratio calculation */
2578         if (adc_hz != 0) {
2579                 u32_tmp = 256 * SymbolRate;
2580                 u32_tmp = u32_tmp / adc_hz;
2581         }
2582         stv0367_writereg(state, R367CAB_EQU_CRL_TFR, (u8)u32_tmp);
2583
2584         /* Symbol rate and SRC gain calculation */
2585         adp_khz = (mclk_hz >> 1) / 1000;/* TRL works at half the system clock */
2586         if (adp_khz != 0) {
2587                 u32_tmp = SymbolRate;
2588                 u32_tmp1 = SymbolRate;
2589
2590                 if (u32_tmp < 2097152) { /* 2097152 = 2^21 */
2591                         /* Symbol rate calculation */
2592                         u32_tmp *= 2048; /* 2048 = 2^11 */
2593                         u32_tmp = u32_tmp / adp_khz;
2594                         u32_tmp = u32_tmp * 16384; /* 16384 = 2^14 */
2595                         u32_tmp /= 125 ; /* 125 = 1000/2^3 */
2596                         u32_tmp = u32_tmp * 8; /* 8 = 2^3 */
2597
2598                         /* SRC Gain Calculation */
2599                         u32_tmp1 *= 2048; /* *2*2^10 */
2600                         u32_tmp1 /= 439; /* *2/878 */
2601                         u32_tmp1 *= 256; /* *2^8 */
2602                         u32_tmp1 = u32_tmp1 / adp_khz; /* /(AdpClk in kHz) */
2603                         u32_tmp1 *= QamSizeCorr * 9; /* *1000*corr factor */
2604                         u32_tmp1 = u32_tmp1 / 10000000;
2605
2606                 } else if (u32_tmp < 4194304) { /* 4194304 = 2**22 */
2607                         /* Symbol rate calculation */
2608                         u32_tmp *= 1024 ; /* 1024 = 2**10 */
2609                         u32_tmp = u32_tmp / adp_khz;
2610                         u32_tmp = u32_tmp * 16384; /* 16384 = 2**14 */
2611                         u32_tmp /= 125 ; /* 125 = 1000/2**3 */
2612                         u32_tmp = u32_tmp * 16; /* 16 = 2**4 */
2613
2614                         /* SRC Gain Calculation */
2615                         u32_tmp1 *= 1024; /* *2*2^9 */
2616                         u32_tmp1 /= 439; /* *2/878 */
2617                         u32_tmp1 *= 256; /* *2^8 */
2618                         u32_tmp1 = u32_tmp1 / adp_khz; /* /(AdpClk in kHz)*/
2619                         u32_tmp1 *= QamSizeCorr * 9; /* *1000*corr factor */
2620                         u32_tmp1 = u32_tmp1 / 5000000;
2621                 } else if (u32_tmp < 8388607) { /* 8388607 = 2**23 */
2622                         /* Symbol rate calculation */
2623                         u32_tmp *= 512 ; /* 512 = 2**9 */
2624                         u32_tmp = u32_tmp / adp_khz;
2625                         u32_tmp = u32_tmp * 16384; /* 16384 = 2**14 */
2626                         u32_tmp /= 125 ; /* 125 = 1000/2**3 */
2627                         u32_tmp = u32_tmp * 32; /* 32 = 2**5 */
2628
2629                         /* SRC Gain Calculation */
2630                         u32_tmp1 *= 512; /* *2*2^8 */
2631                         u32_tmp1 /= 439; /* *2/878 */
2632                         u32_tmp1 *= 256; /* *2^8 */
2633                         u32_tmp1 = u32_tmp1 / adp_khz; /* /(AdpClk in kHz) */
2634                         u32_tmp1 *= QamSizeCorr * 9; /* *1000*corr factor */
2635                         u32_tmp1 = u32_tmp1 / 2500000;
2636                 } else {
2637                         /* Symbol rate calculation */
2638                         u32_tmp *= 256 ; /* 256 = 2**8 */
2639                         u32_tmp = u32_tmp / adp_khz;
2640                         u32_tmp = u32_tmp * 16384; /* 16384 = 2**13 */
2641                         u32_tmp /= 125 ; /* 125 = 1000/2**3 */
2642                         u32_tmp = u32_tmp * 64; /* 64 = 2**6 */
2643
2644                         /* SRC Gain Calculation */
2645                         u32_tmp1 *= 256; /* 2*2^7 */
2646                         u32_tmp1 /= 439; /* *2/878 */
2647                         u32_tmp1 *= 256; /* *2^8 */
2648                         u32_tmp1 = u32_tmp1 / adp_khz; /* /(AdpClk in kHz) */
2649                         u32_tmp1 *= QamSizeCorr * 9; /* *1000*corr factor */
2650                         u32_tmp1 = u32_tmp1 / 1250000;
2651                 }
2652         }
2653 #if 0
2654         /* Filters' coefficients are calculated and written
2655         into registers only if the filters are enabled */
2656         if (stv0367_readbits(state, F367CAB_ADJ_EN)) {
2657                 stv0367cab_SetIirAdjacentcoefficient(state, mclk_hz,
2658                                                                 SymbolRate);
2659                 /* AllPass filter must be enabled
2660                 when the adjacents filter is used */
2661                 stv0367_writebits(state, F367CAB_ALLPASSFILT_EN, 1);
2662                 stv0367cab_SetAllPasscoefficient(state, mclk_hz, SymbolRate);
2663         } else
2664                 /* AllPass filter must be disabled
2665                 when the adjacents filter is not used */
2666 #endif
2667         stv0367_writebits(state, F367CAB_ALLPASSFILT_EN, 0);
2668
2669         stv0367_writereg(state, R367CAB_SRC_NCO_LL, u32_tmp);
2670         stv0367_writereg(state, R367CAB_SRC_NCO_LH, (u32_tmp >> 8));
2671         stv0367_writereg(state, R367CAB_SRC_NCO_HL, (u32_tmp >> 16));
2672         stv0367_writereg(state, R367CAB_SRC_NCO_HH, (u32_tmp >> 24));
2673
2674         stv0367_writereg(state, R367CAB_IQDEM_GAIN_SRC_L, u32_tmp1 & 0x00ff);
2675         stv0367_writebits(state, F367CAB_GAIN_SRC_HI, (u32_tmp1 >> 8) & 0x00ff);
2676
2677         return SymbolRate ;
2678 }
2679
2680 static u32 stv0367cab_GetSymbolRate(struct stv0367_state *state, u32 mclk_hz)
2681 {
2682         u32 regsym;
2683         u32 adp_khz;
2684
2685         regsym = stv0367_readreg(state, R367CAB_SRC_NCO_LL) +
2686                 (stv0367_readreg(state, R367CAB_SRC_NCO_LH) << 8) +
2687                 (stv0367_readreg(state, R367CAB_SRC_NCO_HL) << 16) +
2688                 (stv0367_readreg(state, R367CAB_SRC_NCO_HH) << 24);
2689
2690         adp_khz = (mclk_hz >> 1) / 1000;/* TRL works at half the system clock */
2691
2692         if (regsym < 134217728) {               /* 134217728L = 2**27*/
2693                 regsym = regsym * 32;           /* 32 = 2**5 */
2694                 regsym = regsym / 32768;        /* 32768L = 2**15 */
2695                 regsym = adp_khz * regsym;      /* AdpClk in kHz */
2696                 regsym = regsym / 128;          /* 128 = 2**7 */
2697                 regsym *= 125 ;                 /* 125 = 1000/2**3 */
2698                 regsym /= 2048 ;                /* 2048 = 2**11 */
2699         } else if (regsym < 268435456) {        /* 268435456L = 2**28 */
2700                 regsym = regsym * 16;           /* 16 = 2**4 */
2701                 regsym = regsym / 32768;        /* 32768L = 2**15 */
2702                 regsym = adp_khz * regsym;      /* AdpClk in kHz */
2703                 regsym = regsym / 128;          /* 128 = 2**7 */
2704                 regsym *= 125 ;                 /* 125 = 1000/2**3*/
2705                 regsym /= 1024 ;                /* 256 = 2**10*/
2706         } else if (regsym < 536870912) {        /* 536870912L = 2**29*/
2707                 regsym = regsym * 8;            /* 8 = 2**3 */
2708                 regsym = regsym / 32768;        /* 32768L = 2**15 */
2709                 regsym = adp_khz * regsym;      /* AdpClk in kHz */
2710                 regsym = regsym / 128;          /* 128 = 2**7 */
2711                 regsym *= 125 ;                 /* 125 = 1000/2**3 */
2712                 regsym /= 512 ;                 /* 128 = 2**9 */
2713         } else {
2714                 regsym = regsym * 4;            /* 4 = 2**2 */
2715                 regsym = regsym / 32768;        /* 32768L = 2**15 */
2716                 regsym = adp_khz * regsym;      /* AdpClk in kHz */
2717                 regsym = regsym / 128;          /* 128 = 2**7 */
2718                 regsym *= 125 ;                 /* 125 = 1000/2**3 */
2719                 regsym /= 256 ;                 /* 64 = 2**8 */
2720         }
2721
2722         return regsym;
2723 }
2724
2725 static int stv0367cab_read_status(struct dvb_frontend *fe,
2726                                   enum fe_status *status)
2727 {
2728         struct stv0367_state *state = fe->demodulator_priv;
2729
2730         dprintk("%s:\n", __func__);
2731
2732         *status = 0;
2733
2734         if (stv0367_readbits(state, F367CAB_QAMFEC_LOCK)) {
2735                 *status |= FE_HAS_LOCK;
2736                 dprintk("%s: stv0367 has locked\n", __func__);
2737         }
2738
2739         return 0;
2740 }
2741
2742 static int stv0367cab_standby(struct dvb_frontend *fe, u8 standby_on)
2743 {
2744         struct stv0367_state *state = fe->demodulator_priv;
2745
2746         dprintk("%s:\n", __func__);
2747
2748         if (standby_on) {
2749                 stv0367_writebits(state, F367CAB_BYPASS_PLLXN, 0x03);
2750                 stv0367_writebits(state, F367CAB_STDBY_PLLXN, 0x01);
2751                 stv0367_writebits(state, F367CAB_STDBY, 1);
2752                 stv0367_writebits(state, F367CAB_STDBY_CORE, 1);
2753                 stv0367_writebits(state, F367CAB_EN_BUFFER_I, 0);
2754                 stv0367_writebits(state, F367CAB_EN_BUFFER_Q, 0);
2755                 stv0367_writebits(state, F367CAB_POFFQ, 1);
2756                 stv0367_writebits(state, F367CAB_POFFI, 1);
2757         } else {
2758                 stv0367_writebits(state, F367CAB_STDBY_PLLXN, 0x00);
2759                 stv0367_writebits(state, F367CAB_BYPASS_PLLXN, 0x00);
2760                 stv0367_writebits(state, F367CAB_STDBY, 0);
2761                 stv0367_writebits(state, F367CAB_STDBY_CORE, 0);
2762                 stv0367_writebits(state, F367CAB_EN_BUFFER_I, 1);
2763                 stv0367_writebits(state, F367CAB_EN_BUFFER_Q, 1);
2764                 stv0367_writebits(state, F367CAB_POFFQ, 0);
2765                 stv0367_writebits(state, F367CAB_POFFI, 0);
2766         }
2767
2768         return 0;
2769 }
2770
2771 static int stv0367cab_sleep(struct dvb_frontend *fe)
2772 {
2773         return stv0367cab_standby(fe, 1);
2774 }
2775
2776 static int stv0367cab_init(struct dvb_frontend *fe)
2777 {
2778         struct stv0367_state *state = fe->demodulator_priv;
2779         struct stv0367cab_state *cab_state = state->cab_state;
2780         int i;
2781
2782         dprintk("%s:\n", __func__);
2783
2784         for (i = 0; i < STV0367CAB_NBREGS; i++)
2785                 stv0367_writereg(state, def0367cab[i].addr,
2786                                                 def0367cab[i].value);
2787
2788         switch (state->config->ts_mode) {
2789         case STV0367_DVBCI_CLOCK:
2790                 dprintk("Setting TSMode = STV0367_DVBCI_CLOCK\n");
2791                 stv0367_writebits(state, F367CAB_OUTFORMAT, 0x03);
2792                 break;
2793         case STV0367_SERIAL_PUNCT_CLOCK:
2794         case STV0367_SERIAL_CONT_CLOCK:
2795                 stv0367_writebits(state, F367CAB_OUTFORMAT, 0x01);
2796                 break;
2797         case STV0367_PARALLEL_PUNCT_CLOCK:
2798         case STV0367_OUTPUTMODE_DEFAULT:
2799                 stv0367_writebits(state, F367CAB_OUTFORMAT, 0x00);
2800                 break;
2801         }
2802
2803         switch (state->config->clk_pol) {
2804         case STV0367_RISINGEDGE_CLOCK:
2805                 stv0367_writebits(state, F367CAB_CLK_POLARITY, 0x00);
2806                 break;
2807         case STV0367_FALLINGEDGE_CLOCK:
2808         case STV0367_CLOCKPOLARITY_DEFAULT:
2809                 stv0367_writebits(state, F367CAB_CLK_POLARITY, 0x01);
2810                 break;
2811         }
2812
2813         stv0367_writebits(state, F367CAB_SYNC_STRIP, 0x00);
2814
2815         stv0367_writebits(state, F367CAB_CT_NBST, 0x01);
2816
2817         stv0367_writebits(state, F367CAB_TS_SWAP, 0x01);
2818
2819         stv0367_writebits(state, F367CAB_FIFO_BYPASS, 0x00);
2820
2821         stv0367_writereg(state, R367CAB_ANACTRL, 0x00);/*PLL enabled and used */
2822
2823         cab_state->mclk = stv0367cab_get_mclk(fe, state->config->xtal);
2824         cab_state->adc_clk = stv0367cab_get_adc_freq(fe, state->config->xtal);
2825
2826         return 0;
2827 }
2828 static
2829 enum stv0367_cab_signal_type stv0367cab_algo(struct stv0367_state *state,
2830                                              struct dtv_frontend_properties *p)
2831 {
2832         struct stv0367cab_state *cab_state = state->cab_state;
2833         enum stv0367_cab_signal_type signalType = FE_CAB_NOAGC;
2834         u32     QAMFEC_Lock, QAM_Lock, u32_tmp,
2835                 LockTime, TRLTimeOut, AGCTimeOut, CRLSymbols,
2836                 CRLTimeOut, EQLTimeOut, DemodTimeOut, FECTimeOut;
2837         u8      TrackAGCAccum;
2838         s32     tmp;
2839
2840         dprintk("%s:\n", __func__);
2841
2842         /* Timeouts calculation */
2843         /* A max lock time of 25 ms is allowed for delayed AGC */
2844         AGCTimeOut = 25;
2845         /* 100000 symbols needed by the TRL as a maximum value */
2846         TRLTimeOut = 100000000 / p->symbol_rate;
2847         /* CRLSymbols is the needed number of symbols to achieve a lock
2848            within [-4%, +4%] of the symbol rate.
2849            CRL timeout is calculated
2850            for a lock within [-search_range, +search_range].
2851            EQL timeout can be changed depending on
2852            the micro-reflections we want to handle.
2853            A characterization must be performed
2854            with these echoes to get new timeout values.
2855         */
2856         switch (p->modulation) {
2857         case QAM_16:
2858                 CRLSymbols = 150000;
2859                 EQLTimeOut = 100;
2860                 break;
2861         case QAM_32:
2862                 CRLSymbols = 250000;
2863                 EQLTimeOut = 100;
2864                 break;
2865         case QAM_64:
2866                 CRLSymbols = 200000;
2867                 EQLTimeOut = 100;
2868                 break;
2869         case QAM_128:
2870                 CRLSymbols = 250000;
2871                 EQLTimeOut = 100;
2872                 break;
2873         case QAM_256:
2874                 CRLSymbols = 250000;
2875                 EQLTimeOut = 100;
2876                 break;
2877         default:
2878                 CRLSymbols = 200000;
2879                 EQLTimeOut = 100;
2880                 break;
2881         }
2882 #if 0
2883         if (pIntParams->search_range < 0) {
2884                 CRLTimeOut = (25 * CRLSymbols *
2885                                 (-pIntParams->search_range / 1000)) /
2886                                         (pIntParams->symbol_rate / 1000);
2887         } else
2888 #endif
2889         CRLTimeOut = (25 * CRLSymbols * (cab_state->search_range / 1000)) /
2890                                         (p->symbol_rate / 1000);
2891
2892         CRLTimeOut = (1000 * CRLTimeOut) / p->symbol_rate;
2893         /* Timeouts below 50ms are coerced */
2894         if (CRLTimeOut < 50)
2895                 CRLTimeOut = 50;
2896         /* A maximum of 100 TS packets is needed to get FEC lock even in case
2897         the spectrum inversion needs to be changed.
2898            This is equal to 20 ms in case of the lowest symbol rate of 0.87Msps
2899         */
2900         FECTimeOut = 20;
2901         DemodTimeOut = AGCTimeOut + TRLTimeOut + CRLTimeOut + EQLTimeOut;
2902
2903         dprintk("%s: DemodTimeOut=%d\n", __func__, DemodTimeOut);
2904
2905         /* Reset the TRL to ensure nothing starts until the
2906            AGC is stable which ensures a better lock time
2907         */
2908         stv0367_writereg(state, R367CAB_CTRL_1, 0x04);
2909         /* Set AGC accumulation time to minimum and lock threshold to maximum
2910         in order to speed up the AGC lock */
2911         TrackAGCAccum = stv0367_readbits(state, F367CAB_AGC_ACCUMRSTSEL);
2912         stv0367_writebits(state, F367CAB_AGC_ACCUMRSTSEL, 0x0);
2913         /* Modulus Mapper is disabled */
2914         stv0367_writebits(state, F367CAB_MODULUSMAP_EN, 0);
2915         /* Disable the sweep function */
2916         stv0367_writebits(state, F367CAB_SWEEP_EN, 0);
2917         /* The sweep function is never used, Sweep rate must be set to 0 */
2918         /* Set the derotator frequency in Hz */
2919         stv0367cab_set_derot_freq(state, cab_state->adc_clk,
2920                 (1000 * (s32)state->config->if_khz + cab_state->derot_offset));
2921         /* Disable the Allpass Filter when the symbol rate is out of range */
2922         if ((p->symbol_rate > 10800000) | (p->symbol_rate < 1800000)) {
2923                 stv0367_writebits(state, F367CAB_ADJ_EN, 0);
2924                 stv0367_writebits(state, F367CAB_ALLPASSFILT_EN, 0);
2925         }
2926 #if 0
2927         /* Check if the tuner is locked */
2928         tuner_lock = stv0367cab_tuner_get_status(fe);
2929         if (tuner_lock == 0)
2930                 return FE_367CAB_NOTUNER;
2931 #endif
2932         /* Release the TRL to start demodulator acquisition */
2933         /* Wait for QAM lock */
2934         LockTime = 0;
2935         stv0367_writereg(state, R367CAB_CTRL_1, 0x00);
2936         do {
2937                 QAM_Lock = stv0367_readbits(state, F367CAB_FSM_STATUS);
2938                 if ((LockTime >= (DemodTimeOut - EQLTimeOut)) &&
2939                                                         (QAM_Lock == 0x04))
2940                         /*
2941                          * We don't wait longer, the frequency/phase offset
2942                          * must be too big
2943                          */
2944                         LockTime = DemodTimeOut;
2945                 else if ((LockTime >= (AGCTimeOut + TRLTimeOut)) &&
2946                                                         (QAM_Lock == 0x02))
2947                         /*
2948                          * We don't wait longer, either there is no signal or
2949                          * it is not the right symbol rate or it is an analog
2950                          * carrier
2951                          */
2952                 {
2953                         LockTime = DemodTimeOut;
2954                         u32_tmp = stv0367_readbits(state,
2955                                                 F367CAB_AGC_PWR_WORD_LO) +
2956                                         (stv0367_readbits(state,
2957                                                 F367CAB_AGC_PWR_WORD_ME) << 8) +
2958                                         (stv0367_readbits(state,
2959                                                 F367CAB_AGC_PWR_WORD_HI) << 16);
2960                         if (u32_tmp >= 131072)
2961                                 u32_tmp = 262144 - u32_tmp;
2962                         u32_tmp = u32_tmp / (1 << (11 - stv0367_readbits(state,
2963                                                         F367CAB_AGC_IF_BWSEL)));
2964
2965                         if (u32_tmp < stv0367_readbits(state,
2966                                                 F367CAB_AGC_PWRREF_LO) +
2967                                         256 * stv0367_readbits(state,
2968                                                 F367CAB_AGC_PWRREF_HI) - 10)
2969                                 QAM_Lock = 0x0f;
2970                 } else {
2971                         usleep_range(10000, 20000);
2972                         LockTime += 10;
2973                 }
2974                 dprintk("QAM_Lock=0x%x LockTime=%d\n", QAM_Lock, LockTime);
2975                 tmp = stv0367_readreg(state, R367CAB_IT_STATUS1);
2976
2977                 dprintk("R367CAB_IT_STATUS1=0x%x\n", tmp);
2978
2979         } while (((QAM_Lock != 0x0c) && (QAM_Lock != 0x0b)) &&
2980                                                 (LockTime < DemodTimeOut));
2981
2982         dprintk("QAM_Lock=0x%x\n", QAM_Lock);
2983
2984         tmp = stv0367_readreg(state, R367CAB_IT_STATUS1);
2985         dprintk("R367CAB_IT_STATUS1=0x%x\n", tmp);
2986         tmp = stv0367_readreg(state, R367CAB_IT_STATUS2);
2987         dprintk("R367CAB_IT_STATUS2=0x%x\n", tmp);
2988
2989         tmp  = stv0367cab_get_derot_freq(state, cab_state->adc_clk);
2990         dprintk("stv0367cab_get_derot_freq=0x%x\n", tmp);
2991
2992         if ((QAM_Lock == 0x0c) || (QAM_Lock == 0x0b)) {
2993                 /* Wait for FEC lock */
2994                 LockTime = 0;
2995                 do {
2996                         usleep_range(5000, 7000);
2997                         LockTime += 5;
2998                         QAMFEC_Lock = stv0367_readbits(state,
2999                                                         F367CAB_QAMFEC_LOCK);
3000                 } while (!QAMFEC_Lock && (LockTime < FECTimeOut));
3001         } else
3002                 QAMFEC_Lock = 0;
3003
3004         if (QAMFEC_Lock) {
3005                 signalType = FE_CAB_DATAOK;
3006                 cab_state->spect_inv = stv0367_readbits(state,
3007                                                         F367CAB_QUAD_INV);
3008 #if 0
3009 /* not clear for me */
3010                 if (state->config->if_khz != 0) {
3011                         if (state->config->if_khz > cab_state->adc_clk / 1000) {
3012                                 cab_state->freq_khz =
3013                                         FE_Cab_TunerGetFrequency(pIntParams->hTuner)
3014                                 - stv0367cab_get_derot_freq(state, cab_state->adc_clk)
3015                                 - cab_state->adc_clk / 1000 + state->config->if_khz;
3016                         } else {
3017                                 cab_state->freq_khz =
3018                                                 FE_Cab_TunerGetFrequency(pIntParams->hTuner)
3019                                                 - stv0367cab_get_derot_freq(state, cab_state->adc_clk)
3020                                                                                 + state->config->if_khz;
3021                         }
3022                 } else {
3023                         cab_state->freq_khz =
3024                                 FE_Cab_TunerGetFrequency(pIntParams->hTuner) +
3025                                 stv0367cab_get_derot_freq(state,
3026                                                         cab_state->adc_clk) -
3027                                 cab_state->adc_clk / 4000;
3028                 }
3029 #endif
3030                 cab_state->symbol_rate = stv0367cab_GetSymbolRate(state,
3031                                                         cab_state->mclk);
3032                 cab_state->locked = 1;
3033
3034                 /* stv0367_setbits(state, F367CAB_AGC_ACCUMRSTSEL,7);*/
3035         } else {
3036                 switch (QAM_Lock) {
3037                 case 1:
3038                         signalType = FE_CAB_NOAGC;
3039                         break;
3040                 case 2:
3041                         signalType = FE_CAB_NOTIMING;
3042                         break;
3043                 case 3:
3044                         signalType = FE_CAB_TIMINGOK;
3045                         break;
3046                 case 4:
3047                         signalType = FE_CAB_NOCARRIER;
3048                         break;
3049                 case 5:
3050                         signalType = FE_CAB_CARRIEROK;
3051                         break;
3052                 case 7:
3053                         signalType = FE_CAB_NOBLIND;
3054                         break;
3055                 case 8:
3056                         signalType = FE_CAB_BLINDOK;
3057                         break;
3058                 case 10:
3059                         signalType = FE_CAB_NODEMOD;
3060                         break;
3061                 case 11:
3062                         signalType = FE_CAB_DEMODOK;
3063                         break;
3064                 case 12:
3065                         signalType = FE_CAB_DEMODOK;
3066                         break;
3067                 case 13:
3068                         signalType = FE_CAB_NODEMOD;
3069                         break;
3070                 case 14:
3071                         signalType = FE_CAB_NOBLIND;
3072                         break;
3073                 case 15:
3074                         signalType = FE_CAB_NOSIGNAL;
3075                         break;
3076                 default:
3077                         break;
3078                 }
3079
3080         }
3081
3082         /* Set the AGC control values to tracking values */
3083         stv0367_writebits(state, F367CAB_AGC_ACCUMRSTSEL, TrackAGCAccum);
3084         return signalType;
3085 }
3086
3087 static int stv0367cab_set_frontend(struct dvb_frontend *fe)
3088 {
3089         struct dtv_frontend_properties *p = &fe->dtv_property_cache;
3090         struct stv0367_state *state = fe->demodulator_priv;
3091         struct stv0367cab_state *cab_state = state->cab_state;
3092         enum stv0367cab_mod QAMSize = 0;
3093
3094         dprintk("%s: freq = %d, srate = %d\n", __func__,
3095                                         p->frequency, p->symbol_rate);
3096
3097         cab_state->derot_offset = 0;
3098
3099         switch (p->modulation) {
3100         case QAM_16:
3101                 QAMSize = FE_CAB_MOD_QAM16;
3102                 break;
3103         case QAM_32:
3104                 QAMSize = FE_CAB_MOD_QAM32;
3105                 break;
3106         case QAM_64:
3107                 QAMSize = FE_CAB_MOD_QAM64;
3108                 break;
3109         case QAM_128:
3110                 QAMSize = FE_CAB_MOD_QAM128;
3111                 break;
3112         case QAM_256:
3113                 QAMSize = FE_CAB_MOD_QAM256;
3114                 break;
3115         default:
3116                 break;
3117         }
3118
3119         stv0367cab_init(fe);
3120
3121         /* Tuner Frequency Setting */
3122         if (fe->ops.tuner_ops.set_params) {
3123                 if (fe->ops.i2c_gate_ctrl)
3124                         fe->ops.i2c_gate_ctrl(fe, 1);
3125                 fe->ops.tuner_ops.set_params(fe);
3126                 if (fe->ops.i2c_gate_ctrl)
3127                         fe->ops.i2c_gate_ctrl(fe, 0);
3128         }
3129
3130         stv0367cab_SetQamSize(
3131                         state,
3132                         p->symbol_rate,
3133                         QAMSize);
3134
3135         stv0367cab_set_srate(state,
3136                         cab_state->adc_clk,
3137                         cab_state->mclk,
3138                         p->symbol_rate,
3139                         QAMSize);
3140         /* Search algorithm launch, [-1.1*RangeOffset, +1.1*RangeOffset] scan */
3141         cab_state->state = stv0367cab_algo(state, p);
3142         return 0;
3143 }
3144
3145 static int stv0367cab_get_frontend(struct dvb_frontend *fe,
3146                                    struct dtv_frontend_properties *p)
3147 {
3148         struct stv0367_state *state = fe->demodulator_priv;
3149         struct stv0367cab_state *cab_state = state->cab_state;
3150
3151         enum stv0367cab_mod QAMSize;
3152
3153         dprintk("%s:\n", __func__);
3154
3155         p->symbol_rate = stv0367cab_GetSymbolRate(state, cab_state->mclk);
3156
3157         QAMSize = stv0367_readbits(state, F367CAB_QAM_MODE);
3158         switch (QAMSize) {
3159         case FE_CAB_MOD_QAM16:
3160                 p->modulation = QAM_16;
3161                 break;
3162         case FE_CAB_MOD_QAM32:
3163                 p->modulation = QAM_32;
3164                 break;
3165         case FE_CAB_MOD_QAM64:
3166                 p->modulation = QAM_64;
3167                 break;
3168         case FE_CAB_MOD_QAM128:
3169                 p->modulation = QAM_128;
3170                 break;
3171         case FE_CAB_MOD_QAM256:
3172                 p->modulation = QAM_256;
3173                 break;
3174         default:
3175                 break;
3176         }
3177
3178         p->frequency = stv0367_get_tuner_freq(fe);
3179
3180         dprintk("%s: tuner frequency = %d\n", __func__, p->frequency);
3181
3182         if (state->config->if_khz == 0) {
3183                 p->frequency +=
3184                         (stv0367cab_get_derot_freq(state, cab_state->adc_clk) -
3185                         cab_state->adc_clk / 4000);
3186                 return 0;
3187         }
3188
3189         if (state->config->if_khz > cab_state->adc_clk / 1000)
3190                 p->frequency += (state->config->if_khz
3191                         - stv0367cab_get_derot_freq(state, cab_state->adc_clk)
3192                         - cab_state->adc_clk / 1000);
3193         else
3194                 p->frequency += (state->config->if_khz
3195                         - stv0367cab_get_derot_freq(state, cab_state->adc_clk));
3196
3197         return 0;
3198 }
3199
3200 #if 0
3201 void stv0367cab_GetErrorCount(state, enum stv0367cab_mod QAMSize,
3202                         u32 symbol_rate, FE_367qam_Monitor *Monitor_results)
3203 {
3204         stv0367cab_OptimiseNByteAndGetBER(state, QAMSize, symbol_rate, Monitor_results);
3205         stv0367cab_GetPacketsCount(state, Monitor_results);
3206
3207         return;
3208 }
3209
3210 static int stv0367cab_read_ber(struct dvb_frontend *fe, u32 *ber)
3211 {
3212         struct stv0367_state *state = fe->demodulator_priv;
3213
3214         return 0;
3215 }
3216 #endif
3217 static s32 stv0367cab_get_rf_lvl(struct stv0367_state *state)
3218 {
3219         s32 rfLevel = 0;
3220         s32 RfAgcPwm = 0, IfAgcPwm = 0;
3221         u8 i;
3222
3223         stv0367_writebits(state, F367CAB_STDBY_ADCGP, 0x0);
3224
3225         RfAgcPwm =
3226                 (stv0367_readbits(state, F367CAB_RF_AGC1_LEVEL_LO) & 0x03) +
3227                 (stv0367_readbits(state, F367CAB_RF_AGC1_LEVEL_HI) << 2);
3228         RfAgcPwm = 100 * RfAgcPwm / 1023;
3229
3230         IfAgcPwm =
3231                 stv0367_readbits(state, F367CAB_AGC_IF_PWMCMD_LO) +
3232                 (stv0367_readbits(state, F367CAB_AGC_IF_PWMCMD_HI) << 8);
3233         if (IfAgcPwm >= 2048)
3234                 IfAgcPwm -= 2048;
3235         else
3236                 IfAgcPwm += 2048;
3237
3238         IfAgcPwm = 100 * IfAgcPwm / 4095;
3239
3240         /* For DTT75467 on NIM */
3241         if (RfAgcPwm < 90  && IfAgcPwm < 28) {
3242                 for (i = 0; i < RF_LOOKUP_TABLE_SIZE; i++) {
3243                         if (RfAgcPwm <= stv0367cab_RF_LookUp1[0][i]) {
3244                                 rfLevel = (-1) * stv0367cab_RF_LookUp1[1][i];
3245                                 break;
3246                         }
3247                 }
3248                 if (i == RF_LOOKUP_TABLE_SIZE)
3249                         rfLevel = -56;
3250         } else { /*if IF AGC>10*/
3251                 for (i = 0; i < RF_LOOKUP_TABLE2_SIZE; i++) {
3252                         if (IfAgcPwm <= stv0367cab_RF_LookUp2[0][i]) {
3253                                 rfLevel = (-1) * stv0367cab_RF_LookUp2[1][i];
3254                                 break;
3255                         }
3256                 }
3257                 if (i == RF_LOOKUP_TABLE2_SIZE)
3258                         rfLevel = -72;
3259         }
3260         return rfLevel;
3261 }
3262
3263 static int stv0367cab_read_strength(struct dvb_frontend *fe, u16 *strength)
3264 {
3265         struct stv0367_state *state = fe->demodulator_priv;
3266
3267         s32 signal =  stv0367cab_get_rf_lvl(state);
3268
3269         dprintk("%s: signal=%d dBm\n", __func__, signal);
3270
3271         if (signal <= -72)
3272                 *strength = 65535;
3273         else
3274                 *strength = (22 + signal) * (-1311);
3275
3276         dprintk("%s: strength=%d\n", __func__, (*strength));
3277
3278         return 0;
3279 }
3280
3281 static int stv0367cab_read_snr(struct dvb_frontend *fe, u16 *snr)
3282 {
3283         struct stv0367_state *state = fe->demodulator_priv;
3284         u32 noisepercentage;
3285         enum stv0367cab_mod QAMSize;
3286         u32 regval = 0, temp = 0;
3287         int power, i;
3288
3289         QAMSize = stv0367_readbits(state, F367CAB_QAM_MODE);
3290         switch (QAMSize) {
3291         case FE_CAB_MOD_QAM4:
3292                 power = 21904;
3293                 break;
3294         case FE_CAB_MOD_QAM16:
3295                 power = 20480;
3296                 break;
3297         case FE_CAB_MOD_QAM32:
3298                 power = 23040;
3299                 break;
3300         case FE_CAB_MOD_QAM64:
3301                 power = 21504;
3302                 break;
3303         case FE_CAB_MOD_QAM128:
3304                 power = 23616;
3305                 break;
3306         case FE_CAB_MOD_QAM256:
3307                 power = 21760;
3308                 break;
3309         case FE_CAB_MOD_QAM512:
3310                 power = 1;
3311                 break;
3312         case FE_CAB_MOD_QAM1024:
3313                 power = 21280;
3314                 break;
3315         default:
3316                 power = 1;
3317                 break;
3318         }
3319
3320         for (i = 0; i < 10; i++) {
3321                 regval += (stv0367_readbits(state, F367CAB_SNR_LO)
3322                         + 256 * stv0367_readbits(state, F367CAB_SNR_HI));
3323         }
3324
3325         regval /= 10; /*for average over 10 times in for loop above*/
3326         if (regval != 0) {
3327                 temp = power
3328                         * (1 << (3 + stv0367_readbits(state, F367CAB_SNR_PER)));
3329                 temp /= regval;
3330         }
3331
3332         /* table values, not needed to calculate logarithms */
3333         if (temp >= 5012)
3334                 noisepercentage = 100;
3335         else if (temp >= 3981)
3336                 noisepercentage = 93;
3337         else if (temp >= 3162)
3338                 noisepercentage = 86;
3339         else if (temp >= 2512)
3340                 noisepercentage = 79;
3341         else if (temp >= 1995)
3342                 noisepercentage = 72;
3343         else if (temp >= 1585)
3344                 noisepercentage = 65;
3345         else if (temp >= 1259)
3346                 noisepercentage = 58;
3347         else if (temp >= 1000)
3348                 noisepercentage = 50;
3349         else if (temp >= 794)
3350                 noisepercentage = 43;
3351         else if (temp >= 501)
3352                 noisepercentage = 36;
3353         else if (temp >= 316)
3354                 noisepercentage = 29;
3355         else if (temp >= 200)
3356                 noisepercentage = 22;
3357         else if (temp >= 158)
3358                 noisepercentage = 14;
3359         else if (temp >= 126)
3360                 noisepercentage = 7;
3361         else
3362                 noisepercentage = 0;
3363
3364         dprintk("%s: noisepercentage=%d\n", __func__, noisepercentage);
3365
3366         *snr = (noisepercentage * 65535) / 100;
3367
3368         return 0;
3369 }
3370
3371 static int stv0367cab_read_ucblcks(struct dvb_frontend *fe, u32 *ucblocks)
3372 {
3373         struct stv0367_state *state = fe->demodulator_priv;
3374         int corrected, tscount;
3375
3376         *ucblocks = (stv0367_readreg(state, R367CAB_RS_COUNTER_5) << 8)
3377                         | stv0367_readreg(state, R367CAB_RS_COUNTER_4);
3378         corrected = (stv0367_readreg(state, R367CAB_RS_COUNTER_3) << 8)
3379                         | stv0367_readreg(state, R367CAB_RS_COUNTER_2);
3380         tscount = (stv0367_readreg(state, R367CAB_RS_COUNTER_2) << 8)
3381                         | stv0367_readreg(state, R367CAB_RS_COUNTER_1);
3382
3383         dprintk("%s: uncorrected blocks=%d corrected blocks=%d tscount=%d\n",
3384                                 __func__, *ucblocks, corrected, tscount);
3385
3386         return 0;
3387 };
3388
3389 static const struct dvb_frontend_ops stv0367cab_ops = {
3390         .delsys = { SYS_DVBC_ANNEX_A },
3391         .info = {
3392                 .name = "ST STV0367 DVB-C",
3393                 .frequency_min = 47000000,
3394                 .frequency_max = 862000000,
3395                 .frequency_stepsize = 62500,
3396                 .symbol_rate_min = 870000,
3397                 .symbol_rate_max = 11700000,
3398                 .caps = 0x400 |/* FE_CAN_QAM_4 */
3399                         FE_CAN_QAM_16 | FE_CAN_QAM_32  |
3400                         FE_CAN_QAM_64 | FE_CAN_QAM_128 |
3401                         FE_CAN_QAM_256 | FE_CAN_FEC_AUTO
3402         },
3403         .release                                = stv0367_release,
3404         .init                                   = stv0367cab_init,
3405         .sleep                                  = stv0367cab_sleep,
3406         .i2c_gate_ctrl                          = stv0367cab_gate_ctrl,
3407         .set_frontend                           = stv0367cab_set_frontend,
3408         .get_frontend                           = stv0367cab_get_frontend,
3409         .read_status                            = stv0367cab_read_status,
3410 /*      .read_ber                               = stv0367cab_read_ber, */
3411         .read_signal_strength                   = stv0367cab_read_strength,
3412         .read_snr                               = stv0367cab_read_snr,
3413         .read_ucblocks                          = stv0367cab_read_ucblcks,
3414         .get_tune_settings                      = stv0367_get_tune_settings,
3415 };
3416
3417 struct dvb_frontend *stv0367cab_attach(const struct stv0367_config *config,
3418                                    struct i2c_adapter *i2c)
3419 {
3420         struct stv0367_state *state = NULL;
3421         struct stv0367cab_state *cab_state = NULL;
3422
3423         /* allocate memory for the internal state */
3424         state = kzalloc(sizeof(struct stv0367_state), GFP_KERNEL);
3425         if (state == NULL)
3426                 goto error;
3427         cab_state = kzalloc(sizeof(struct stv0367cab_state), GFP_KERNEL);
3428         if (cab_state == NULL)
3429                 goto error;
3430
3431         /* setup the state */
3432         state->i2c = i2c;
3433         state->config = config;
3434         cab_state->search_range = 280000;
3435         state->cab_state = cab_state;
3436         state->fe.ops = stv0367cab_ops;
3437         state->fe.demodulator_priv = state;
3438         state->chip_id = stv0367_readreg(state, 0xf000);
3439
3440         dprintk("%s: chip_id = 0x%x\n", __func__, state->chip_id);
3441
3442         /* check if the demod is there */
3443         if ((state->chip_id != 0x50) && (state->chip_id != 0x60))
3444                 goto error;
3445
3446         return &state->fe;
3447
3448 error:
3449         kfree(cab_state);
3450         kfree(state);
3451         return NULL;
3452 }
3453 EXPORT_SYMBOL(stv0367cab_attach);
3454
3455 MODULE_PARM_DESC(debug, "Set debug");
3456 MODULE_PARM_DESC(i2c_debug, "Set i2c debug");
3457
3458 MODULE_AUTHOR("Igor M. Liplianin");
3459 MODULE_DESCRIPTION("ST STV0367 DVB-C/T demodulator driver");
3460 MODULE_LICENSE("GPL");