drivers/crypto/omap-aes.c

   1 /*
   2  * Cryptographic API.
   3  *
   4  * Support for OMAP AES HW acceleration.
   5  *
   6  * Copyright (c) 2010 Nokia Corporation
   7  * Author: Dmitry Kasatkin <[email protected]>
   8  * Copyright (c) 2011 Texas Instruments Incorporated
   9  *
  10  * This program is free software; you can redistribute it and/or modify
  11  * it under the terms of the GNU General Public License version 2 as published
  12  * by the Free Software Foundation.
  13  *
  14  */
  15
  16 #define pr_fmt(fmt) "%20s: " fmt, __func__
  17 #define prn(num) pr_debug(#num "=%d\n", num)
  18 #define prx(num) pr_debug(#num "=%x\n", num)
  19
  20 #include <linux/err.h>
  21 #include <linux/module.h>
  22 #include <linux/init.h>
  23 #include <linux/errno.h>
  24 #include <linux/kernel.h>
  25 #include <linux/platform_device.h>
  26 #include <linux/scatterlist.h>
  27 #include <linux/dma-mapping.h>
  28 #include <linux/dmaengine.h>
  29 #include <linux/pm_runtime.h>
  30 #include <linux/of.h>
  31 #include <linux/of_device.h>
  32 #include <linux/of_address.h>
  33 #include <linux/io.h>
  34 #include <linux/crypto.h>
  35 #include <linux/interrupt.h>
  36 #include <crypto/scatterwalk.h>
  37 #include <crypto/aes.h>
  38 #include <crypto/engine.h>
  39 #include <crypto/internal/skcipher.h>
  40
  41 #define DST_MAXBURST                    4
  42 #define DMA_MIN                         (DST_MAXBURST * sizeof(u32))
  43
  44 #define _calc_walked(inout) (dd->inout##_walk.offset - dd->inout##_sg->offset)
  45
  46 /* OMAP TRM gives bitfields as start:end, where start is the higher bit
  47    number. For example 7:0 */
  48 #define FLD_MASK(start, end)    (((1 << ((start) - (end) + 1)) - 1) << (end))
  49 #define FLD_VAL(val, start, end) (((val) << (end)) & FLD_MASK(start, end))
  50
  51 #define AES_REG_KEY(dd, x)              ((dd)->pdata->key_ofs - \
  52                                                 ((x ^ 0x01) * 0x04))
  53 #define AES_REG_IV(dd, x)               ((dd)->pdata->iv_ofs + ((x) * 0x04))
  54
  55 #define AES_REG_CTRL(dd)                ((dd)->pdata->ctrl_ofs)
  56 #define AES_REG_CTRL_CTR_WIDTH_MASK     GENMASK(8, 7)
  57 #define AES_REG_CTRL_CTR_WIDTH_32       0
  58 #define AES_REG_CTRL_CTR_WIDTH_64       BIT(7)
  59 #define AES_REG_CTRL_CTR_WIDTH_96       BIT(8)
  60 #define AES_REG_CTRL_CTR_WIDTH_128      GENMASK(8, 7)
  61 #define AES_REG_CTRL_CTR                BIT(6)
  62 #define AES_REG_CTRL_CBC                BIT(5)
  63 #define AES_REG_CTRL_KEY_SIZE           GENMASK(4, 3)
  64 #define AES_REG_CTRL_DIRECTION          BIT(2)
  65 #define AES_REG_CTRL_INPUT_READY        BIT(1)
  66 #define AES_REG_CTRL_OUTPUT_READY       BIT(0)
  67 #define AES_REG_CTRL_MASK               GENMASK(24, 2)
  68
  69 #define AES_REG_DATA_N(dd, x)           ((dd)->pdata->data_ofs + ((x) * 0x04))
  70
  71 #define AES_REG_REV(dd)                 ((dd)->pdata->rev_ofs)
  72
  73 #define AES_REG_MASK(dd)                ((dd)->pdata->mask_ofs)
  74 #define AES_REG_MASK_SIDLE              BIT(6)
  75 #define AES_REG_MASK_START              BIT(5)
  76 #define AES_REG_MASK_DMA_OUT_EN         BIT(3)
  77 #define AES_REG_MASK_DMA_IN_EN          BIT(2)
  78 #define AES_REG_MASK_SOFTRESET          BIT(1)
  79 #define AES_REG_AUTOIDLE                BIT(0)
  80
  81 #define AES_REG_LENGTH_N(x)             (0x54 + ((x) * 0x04))
  82
  83 #define AES_REG_IRQ_STATUS(dd)         ((dd)->pdata->irq_status_ofs)
  84 #define AES_REG_IRQ_ENABLE(dd)         ((dd)->pdata->irq_enable_ofs)
  85 #define AES_REG_IRQ_DATA_IN            BIT(1)
  86 #define AES_REG_IRQ_DATA_OUT           BIT(2)
  87 #define DEFAULT_TIMEOUT         (5*HZ)
  88
  89 #define DEFAULT_AUTOSUSPEND_DELAY       1000
  90
  91 #define FLAGS_MODE_MASK         0x000f
  92 #define FLAGS_ENCRYPT           BIT(0)
  93 #define FLAGS_CBC               BIT(1)
  94 #define FLAGS_GIV               BIT(2)
  95 #define FLAGS_CTR               BIT(3)
  96
  97 #define FLAGS_INIT              BIT(4)
  98 #define FLAGS_FAST              BIT(5)
  99 #define FLAGS_BUSY              BIT(6)
 100
 101 #define AES_BLOCK_WORDS         (AES_BLOCK_SIZE >> 2)
 102
 103 struct omap_aes_ctx {
 104         struct omap_aes_dev *dd;
 105
 106         int             keylen;
 107         u32             key[AES_KEYSIZE_256 / sizeof(u32)];
 108         unsigned long   flags;
 109         struct crypto_skcipher  *fallback;
 110 };
 111
 112 struct omap_aes_reqctx {
 113         unsigned long mode;
 114 };
 115
 116 #define OMAP_AES_QUEUE_LENGTH   1
 117 #define OMAP_AES_CACHE_SIZE     0
 118
 119 struct omap_aes_algs_info {
 120         struct crypto_alg       *algs_list;
 121         unsigned int            size;
 122         unsigned int            registered;
 123 };
 124
 125 struct omap_aes_pdata {
 126         struct omap_aes_algs_info       *algs_info;
 127         unsigned int    algs_info_size;
 128
 129         void            (*trigger)(struct omap_aes_dev *dd, int length);
 130
 131         u32             key_ofs;
 132         u32             iv_ofs;
 133         u32             ctrl_ofs;
 134         u32             data_ofs;
 135         u32             rev_ofs;
 136         u32             mask_ofs;
 137         u32             irq_enable_ofs;
 138         u32             irq_status_ofs;
 139
 140         u32             dma_enable_in;
 141         u32             dma_enable_out;
 142         u32             dma_start;
 143
 144         u32             major_mask;
 145         u32             major_shift;
 146         u32             minor_mask;
 147         u32             minor_shift;
 148 };
 149
 150 struct omap_aes_dev {
 151         struct list_head        list;
 152         unsigned long           phys_base;
 153         void __iomem            *io_base;
 154         struct omap_aes_ctx     *ctx;
 155         struct device           *dev;
 156         unsigned long           flags;
 157         int                     err;
 158
 159         struct tasklet_struct   done_task;
 160
 161         struct ablkcipher_request       *req;
 162         struct crypto_engine            *engine;
 163
 164         /*
 165          * total is used by PIO mode for book keeping so introduce
 166          * variable total_save as need it to calc page_order
 167          */
 168         size_t                          total;
 169         size_t                          total_save;
 170
 171         struct scatterlist              *in_sg;
 172         struct scatterlist              *out_sg;
 173
 174         /* Buffers for copying for unaligned cases */
 175         struct scatterlist              in_sgl;
 176         struct scatterlist              out_sgl;
 177         struct scatterlist              *orig_out;
 178         int                             sgs_copied;
 179
 180         struct scatter_walk             in_walk;
 181         struct scatter_walk             out_walk;
 182         struct dma_chan         *dma_lch_in;
 183         struct dma_chan         *dma_lch_out;
 184         int                     in_sg_len;
 185         int                     out_sg_len;
 186         int                     pio_only;
 187         const struct omap_aes_pdata     *pdata;
 188 };
 189
 190 /* keep registered devices data here */
 191 static LIST_HEAD(dev_list);
 192 static DEFINE_SPINLOCK(list_lock);
 193
 194 #ifdef DEBUG
 195 #define omap_aes_read(dd, offset)                               \
 196 ({                                                              \
 197         int _read_ret;                                          \
 198         _read_ret = __raw_readl(dd->io_base + offset);          \
 199         pr_debug("omap_aes_read(" #offset "=%#x)= %#x\n",       \
 200                  offset, _read_ret);                            \
 201         _read_ret;                                              \
 202 })
 203 #else
 204 static inline u32 omap_aes_read(struct omap_aes_dev *dd, u32 offset)
 205 {
 206         return __raw_readl(dd->io_base + offset);
 207 }
 208 #endif
 209
 210 #ifdef DEBUG
 211 #define omap_aes_write(dd, offset, value)                               \
 212         do {                                                            \
 213                 pr_debug("omap_aes_write(" #offset "=%#x) value=%#x\n", \
 214                          offset, value);                                \
 215                 __raw_writel(value, dd->io_base + offset);              \
 216         } while (0)
 217 #else
 218 static inline void omap_aes_write(struct omap_aes_dev *dd, u32 offset,
 219                                   u32 value)
 220 {
 221         __raw_writel(value, dd->io_base + offset);
 222 }
 223 #endif
 224
 225 static inline void omap_aes_write_mask(struct omap_aes_dev *dd, u32 offset,
 226                                         u32 value, u32 mask)
 227 {
 228         u32 val;
 229
 230         val = omap_aes_read(dd, offset);
 231         val &= ~mask;
 232         val |= value;
 233         omap_aes_write(dd, offset, val);
 234 }
 235
 236 static void omap_aes_write_n(struct omap_aes_dev *dd, u32 offset,
 237                                         u32 *value, int count)
 238 {
 239         for (; count--; value++, offset += 4)
 240                 omap_aes_write(dd, offset, *value);
 241 }
 242
 243 static int omap_aes_hw_init(struct omap_aes_dev *dd)
 244 {
 245         int err;
 246
 247         if (!(dd->flags & FLAGS_INIT)) {
 248                 dd->flags |= FLAGS_INIT;
 249                 dd->err = 0;
 250         }
 251
 252         err = pm_runtime_get_sync(dd->dev);
 253         if (err < 0) {
 254                 dev_err(dd->dev, "failed to get sync: %d\n", err);
 255                 return err;
 256         }
 257
 258         return 0;
 259 }
 260
 261 static int omap_aes_write_ctrl(struct omap_aes_dev *dd)
 262 {
 263         unsigned int key32;
 264         int i, err;
 265         u32 val;
 266
 267         err = omap_aes_hw_init(dd);
 268         if (err)
 269                 return err;
 270
 271         key32 = dd->ctx->keylen / sizeof(u32);
 272
 273         /* it seems a key should always be set even if it has not changed */
 274         for (i = 0; i < key32; i++) {
 275                 omap_aes_write(dd, AES_REG_KEY(dd, i),
 276                         __le32_to_cpu(dd->ctx->key[i]));
 277         }
 278
 279         if ((dd->flags & (FLAGS_CBC | FLAGS_CTR)) && dd->req->info)
 280                 omap_aes_write_n(dd, AES_REG_IV(dd, 0), dd->req->info, 4);
 281
 282         val = FLD_VAL(((dd->ctx->keylen >> 3) - 1), 4, 3);
 283         if (dd->flags & FLAGS_CBC)
 284                 val |= AES_REG_CTRL_CBC;
 285         if (dd->flags & FLAGS_CTR)
 286                 val |= AES_REG_CTRL_CTR | AES_REG_CTRL_CTR_WIDTH_128;
 287
 288         if (dd->flags & FLAGS_ENCRYPT)
 289                 val |= AES_REG_CTRL_DIRECTION;
 290
 291         omap_aes_write_mask(dd, AES_REG_CTRL(dd), val, AES_REG_CTRL_MASK);
 292
 293         return 0;
 294 }
 295
 296 static void omap_aes_dma_trigger_omap2(struct omap_aes_dev *dd, int length)
 297 {
 298         u32 mask, val;
 299
 300         val = dd->pdata->dma_start;
 301
 302         if (dd->dma_lch_out != NULL)
 303                 val |= dd->pdata->dma_enable_out;
 304         if (dd->dma_lch_in != NULL)
 305                 val |= dd->pdata->dma_enable_in;
 306
 307         mask = dd->pdata->dma_enable_out | dd->pdata->dma_enable_in |
 308                dd->pdata->dma_start;
 309
 310         omap_aes_write_mask(dd, AES_REG_MASK(dd), val, mask);
 311
 312 }
 313
 314 static void omap_aes_dma_trigger_omap4(struct omap_aes_dev *dd, int length)
 315 {
 316         omap_aes_write(dd, AES_REG_LENGTH_N(0), length);
 317         omap_aes_write(dd, AES_REG_LENGTH_N(1), 0);
 318
 319         omap_aes_dma_trigger_omap2(dd, length);
 320 }
 321
 322 static void omap_aes_dma_stop(struct omap_aes_dev *dd)
 323 {
 324         u32 mask;
 325
 326         mask = dd->pdata->dma_enable_out | dd->pdata->dma_enable_in |
 327                dd->pdata->dma_start;
 328
 329         omap_aes_write_mask(dd, AES_REG_MASK(dd), 0, mask);
 330 }
 331
 332 static struct omap_aes_dev *omap_aes_find_dev(struct omap_aes_ctx *ctx)
 333 {
 334         struct omap_aes_dev *dd;
 335
 336         spin_lock_bh(&list_lock);
 337         dd = list_first_entry(&dev_list, struct omap_aes_dev, list);
 338         list_move_tail(&dd->list, &dev_list);
 339         ctx->dd = dd;
 340         spin_unlock_bh(&list_lock);
 341
 342         return dd;
 343 }
 344
 345 static void omap_aes_dma_out_callback(void *data)
 346 {
 347         struct omap_aes_dev *dd = data;
 348
 349         /* dma_lch_out - completed */
 350         tasklet_schedule(&dd->done_task);
 351 }
 352
 353 static int omap_aes_dma_init(struct omap_aes_dev *dd)
 354 {
 355         int err;
 356
 357         dd->dma_lch_out = NULL;
 358         dd->dma_lch_in = NULL;
 359
 360         dd->dma_lch_in = dma_request_chan(dd->dev, "rx");
 361         if (IS_ERR(dd->dma_lch_in)) {
 362                 dev_err(dd->dev, "Unable to request in DMA channel\n");
 363                 return PTR_ERR(dd->dma_lch_in);
 364         }
 365
 366         dd->dma_lch_out = dma_request_chan(dd->dev, "tx");
 367         if (IS_ERR(dd->dma_lch_out)) {
 368                 dev_err(dd->dev, "Unable to request out DMA channel\n");
 369                 err = PTR_ERR(dd->dma_lch_out);
 370                 goto err_dma_out;
 371         }
 372
 373         return 0;
 374
 375 err_dma_out:
 376         dma_release_channel(dd->dma_lch_in);
 377
 378         return err;
 379 }
 380
 381 static void omap_aes_dma_cleanup(struct omap_aes_dev *dd)
 382 {
 383         if (dd->pio_only)
 384                 return;
 385
 386         dma_release_channel(dd->dma_lch_out);
 387         dma_release_channel(dd->dma_lch_in);
 388 }
 389
 390 static void sg_copy_buf(void *buf, struct scatterlist *sg,
 391                               unsigned int start, unsigned int nbytes, int out)
 392 {
 393         struct scatter_walk walk;
 394
 395         if (!nbytes)
 396                 return;
 397
 398         scatterwalk_start(&walk, sg);
 399         scatterwalk_advance(&walk, start);
 400         scatterwalk_copychunks(buf, &walk, nbytes, out);
 401         scatterwalk_done(&walk, out, 0);
 402 }
 403
 404 static int omap_aes_crypt_dma(struct crypto_tfm *tfm,
 405                 struct scatterlist *in_sg, struct scatterlist *out_sg,
 406                 int in_sg_len, int out_sg_len)
 407 {
 408         struct omap_aes_ctx *ctx = crypto_tfm_ctx(tfm);
 409         struct omap_aes_dev *dd = ctx->dd;
 410         struct dma_async_tx_descriptor *tx_in, *tx_out;
 411         struct dma_slave_config cfg;
 412         int ret;
 413
 414         if (dd->pio_only) {
 415                 scatterwalk_start(&dd->in_walk, dd->in_sg);
 416                 scatterwalk_start(&dd->out_walk, dd->out_sg);
 417
 418                 /* Enable DATAIN interrupt and let it take
 419                    care of the rest */
 420                 omap_aes_write(dd, AES_REG_IRQ_ENABLE(dd), 0x2);
 421                 return 0;
 422         }
 423
 424         dma_sync_sg_for_device(dd->dev, dd->in_sg, in_sg_len, DMA_TO_DEVICE);
 425
 426         memset(&cfg, 0, sizeof(cfg));
 427
 428         cfg.src_addr = dd->phys_base + AES_REG_DATA_N(dd, 0);
 429         cfg.dst_addr = dd->phys_base + AES_REG_DATA_N(dd, 0);
 430         cfg.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
 431         cfg.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
 432         cfg.src_maxburst = DST_MAXBURST;
 433         cfg.dst_maxburst = DST_MAXBURST;
 434
 435         /* IN */
 436         ret = dmaengine_slave_config(dd->dma_lch_in, &cfg);
 437         if (ret) {
 438                 dev_err(dd->dev, "can't configure IN dmaengine slave: %d\n",
 439                         ret);
 440                 return ret;
 441         }
 442
 443         tx_in = dmaengine_prep_slave_sg(dd->dma_lch_in, in_sg, in_sg_len,
 444                                         DMA_MEM_TO_DEV,
 445                                         DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
 446         if (!tx_in) {
 447                 dev_err(dd->dev, "IN prep_slave_sg() failed\n");
 448                 return -EINVAL;
 449         }
 450
 451         /* No callback necessary */
 452         tx_in->callback_param = dd;
 453
 454         /* OUT */
 455         ret = dmaengine_slave_config(dd->dma_lch_out, &cfg);
 456         if (ret) {
 457                 dev_err(dd->dev, "can't configure OUT dmaengine slave: %d\n",
 458                         ret);
 459                 return ret;
 460         }
 461
 462         tx_out = dmaengine_prep_slave_sg(dd->dma_lch_out, out_sg, out_sg_len,
 463                                         DMA_DEV_TO_MEM,
 464                                         DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
 465         if (!tx_out) {
 466                 dev_err(dd->dev, "OUT prep_slave_sg() failed\n");
 467                 return -EINVAL;
 468         }
 469
 470         tx_out->callback = omap_aes_dma_out_callback;
 471         tx_out->callback_param = dd;
 472
 473         dmaengine_submit(tx_in);
 474         dmaengine_submit(tx_out);
 475
 476         dma_async_issue_pending(dd->dma_lch_in);
 477         dma_async_issue_pending(dd->dma_lch_out);
 478
 479         /* start DMA */
 480         dd->pdata->trigger(dd, dd->total);
 481
 482         return 0;
 483 }
 484
 485 static int omap_aes_crypt_dma_start(struct omap_aes_dev *dd)
 486 {
 487         struct crypto_tfm *tfm = crypto_ablkcipher_tfm(
 488                                         crypto_ablkcipher_reqtfm(dd->req));
 489         int err;
 490
 491         pr_debug("total: %d\n", dd->total);
 492
 493         if (!dd->pio_only) {
 494                 err = dma_map_sg(dd->dev, dd->in_sg, dd->in_sg_len,
 495                                  DMA_TO_DEVICE);
 496                 if (!err) {
 497                         dev_err(dd->dev, "dma_map_sg() error\n");
 498                         return -EINVAL;
 499                 }
 500
 501                 err = dma_map_sg(dd->dev, dd->out_sg, dd->out_sg_len,
 502                                  DMA_FROM_DEVICE);
 503                 if (!err) {
 504                         dev_err(dd->dev, "dma_map_sg() error\n");
 505                         return -EINVAL;
 506                 }
 507         }
 508
 509         err = omap_aes_crypt_dma(tfm, dd->in_sg, dd->out_sg, dd->in_sg_len,
 510                                  dd->out_sg_len);
 511         if (err && !dd->pio_only) {
 512                 dma_unmap_sg(dd->dev, dd->in_sg, dd->in_sg_len, DMA_TO_DEVICE);
 513                 dma_unmap_sg(dd->dev, dd->out_sg, dd->out_sg_len,
 514                              DMA_FROM_DEVICE);
 515         }
 516
 517         return err;
 518 }
 519
 520 static void omap_aes_finish_req(struct omap_aes_dev *dd, int err)
 521 {
 522         struct ablkcipher_request *req = dd->req;
 523
 524         pr_debug("err: %d\n", err);
 525
 526         crypto_finalize_cipher_request(dd->engine, req, err);
 527
 528         pm_runtime_mark_last_busy(dd->dev);
 529         pm_runtime_put_autosuspend(dd->dev);
 530 }
 531
 532 static int omap_aes_crypt_dma_stop(struct omap_aes_dev *dd)
 533 {
 534         pr_debug("total: %d\n", dd->total);
 535
 536         omap_aes_dma_stop(dd);
 537
 538
 539         return 0;
 540 }
 541
 542 static int omap_aes_check_aligned(struct scatterlist *sg, int total)
 543 {
 544         int len = 0;
 545
 546         if (!IS_ALIGNED(total, AES_BLOCK_SIZE))
 547                 return -EINVAL;
 548
 549         while (sg) {
 550                 if (!IS_ALIGNED(sg->offset, 4))
 551                         return -1;
 552                 if (!IS_ALIGNED(sg->length, AES_BLOCK_SIZE))
 553                         return -1;
 554
 555                 len += sg->length;
 556                 sg = sg_next(sg);
 557         }
 558
 559         if (len != total)
 560                 return -1;
 561
 562         return 0;
 563 }
 564
 565 static int omap_aes_copy_sgs(struct omap_aes_dev *dd)
 566 {
 567         void *buf_in, *buf_out;
 568         int pages, total;
 569
 570         total = ALIGN(dd->total, AES_BLOCK_SIZE);
 571         pages = get_order(total);
 572
 573         buf_in = (void *)__get_free_pages(GFP_ATOMIC, pages);
 574         buf_out = (void *)__get_free_pages(GFP_ATOMIC, pages);
 575
 576         if (!buf_in || !buf_out) {
 577                 pr_err("Couldn't allocated pages for unaligned cases.\n");
 578                 return -1;
 579         }
 580
 581         dd->orig_out = dd->out_sg;
 582
 583         sg_copy_buf(buf_in, dd->in_sg, 0, dd->total, 0);
 584
 585         sg_init_table(&dd->in_sgl, 1);
 586         sg_set_buf(&dd->in_sgl, buf_in, total);
 587         dd->in_sg = &dd->in_sgl;
 588         dd->in_sg_len = 1;
 589
 590         sg_init_table(&dd->out_sgl, 1);
 591         sg_set_buf(&dd->out_sgl, buf_out, total);
 592         dd->out_sg = &dd->out_sgl;
 593         dd->out_sg_len = 1;
 594
 595         return 0;
 596 }
 597
 598 static int omap_aes_handle_queue(struct omap_aes_dev *dd,
 599                                  struct ablkcipher_request *req)
 600 {
 601         if (req)
 602                 return crypto_transfer_cipher_request_to_engine(dd->engine, req);
 603
 604         return 0;
 605 }
 606
 607 static int omap_aes_prepare_req(struct crypto_engine *engine,
 608                                 struct ablkcipher_request *req)
 609 {
 610         struct omap_aes_ctx *ctx = crypto_ablkcipher_ctx(
 611                         crypto_ablkcipher_reqtfm(req));
 612         struct omap_aes_dev *dd = ctx->dd;
 613         struct omap_aes_reqctx *rctx;
 614
 615         if (!dd)
 616                 return -ENODEV;
 617
 618         /* assign new request to device */
 619         dd->req = req;
 620         dd->total = req->nbytes;
 621         dd->total_save = req->nbytes;
 622         dd->in_sg = req->src;
 623         dd->out_sg = req->dst;
 624
 625         dd->in_sg_len = sg_nents_for_len(dd->in_sg, dd->total);
 626         if (dd->in_sg_len < 0)
 627                 return dd->in_sg_len;
 628
 629         dd->out_sg_len = sg_nents_for_len(dd->out_sg, dd->total);
 630         if (dd->out_sg_len < 0)
 631                 return dd->out_sg_len;
 632
 633         if (omap_aes_check_aligned(dd->in_sg, dd->total) ||
 634             omap_aes_check_aligned(dd->out_sg, dd->total)) {
 635                 if (omap_aes_copy_sgs(dd))
 636                         pr_err("Failed to copy SGs for unaligned cases\n");
 637                 dd->sgs_copied = 1;
 638         } else {
 639                 dd->sgs_copied = 0;
 640         }
 641
 642         rctx = ablkcipher_request_ctx(req);
 643         ctx = crypto_ablkcipher_ctx(crypto_ablkcipher_reqtfm(req));
 644         rctx->mode &= FLAGS_MODE_MASK;
 645         dd->flags = (dd->flags & ~FLAGS_MODE_MASK) | rctx->mode;
 646
 647         dd->ctx = ctx;
 648         ctx->dd = dd;
 649
 650         return omap_aes_write_ctrl(dd);
 651 }
 652
 653 static int omap_aes_crypt_req(struct crypto_engine *engine,
 654                               struct ablkcipher_request *req)
 655 {
 656         struct omap_aes_ctx *ctx = crypto_ablkcipher_ctx(
 657                         crypto_ablkcipher_reqtfm(req));
 658         struct omap_aes_dev *dd = ctx->dd;
 659
 660         if (!dd)
 661                 return -ENODEV;
 662
 663         return omap_aes_crypt_dma_start(dd);
 664 }
 665
 666 static void omap_aes_done_task(unsigned long data)
 667 {
 668         struct omap_aes_dev *dd = (struct omap_aes_dev *)data;
 669         void *buf_in, *buf_out;
 670         int pages, len;
 671
 672         pr_debug("enter done_task\n");
 673
 674         if (!dd->pio_only) {
 675                 dma_sync_sg_for_device(dd->dev, dd->out_sg, dd->out_sg_len,
 676                                        DMA_FROM_DEVICE);
 677                 dma_unmap_sg(dd->dev, dd->in_sg, dd->in_sg_len, DMA_TO_DEVICE);
 678                 dma_unmap_sg(dd->dev, dd->out_sg, dd->out_sg_len,
 679                              DMA_FROM_DEVICE);
 680                 omap_aes_crypt_dma_stop(dd);
 681         }
 682
 683         if (dd->sgs_copied) {
 684                 buf_in = sg_virt(&dd->in_sgl);
 685                 buf_out = sg_virt(&dd->out_sgl);
 686
 687                 sg_copy_buf(buf_out, dd->orig_out, 0, dd->total_save, 1);
 688
 689                 len = ALIGN(dd->total_save, AES_BLOCK_SIZE);
 690                 pages = get_order(len);
 691                 free_pages((unsigned long)buf_in, pages);
 692                 free_pages((unsigned long)buf_out, pages);
 693         }
 694
 695         omap_aes_finish_req(dd, 0);
 696
 697         pr_debug("exit\n");
 698 }
 699
 700 static int omap_aes_crypt(struct ablkcipher_request *req, unsigned long mode)
 701 {
 702         struct omap_aes_ctx *ctx = crypto_ablkcipher_ctx(
 703                         crypto_ablkcipher_reqtfm(req));
 704         struct omap_aes_reqctx *rctx = ablkcipher_request_ctx(req);
 705         struct omap_aes_dev *dd;
 706         int ret;
 707
 708         pr_debug("nbytes: %d, enc: %d, cbc: %d\n", req->nbytes,
 709                   !!(mode & FLAGS_ENCRYPT),
 710                   !!(mode & FLAGS_CBC));
 711
 712         if (req->nbytes < 200) {
 713                 SKCIPHER_REQUEST_ON_STACK(subreq, ctx->fallback);
 714
 715                 skcipher_request_set_tfm(subreq, ctx->fallback);
 716                 skcipher_request_set_callback(subreq, req->base.flags, NULL,
 717                                               NULL);
 718                 skcipher_request_set_crypt(subreq, req->src, req->dst,
 719                                            req->nbytes, req->info);
 720
 721                 if (mode & FLAGS_ENCRYPT)
 722                         ret = crypto_skcipher_encrypt(subreq);
 723                 else
 724                         ret = crypto_skcipher_decrypt(subreq);
 725
 726                 skcipher_request_zero(subreq);
 727                 return ret;
 728         }
 729         dd = omap_aes_find_dev(ctx);
 730         if (!dd)
 731                 return -ENODEV;
 732
 733         rctx->mode = mode;
 734
 735         return omap_aes_handle_queue(dd, req);
 736 }
 737
 738 /* ********************** ALG API ************************************ */
 739
 740 static int omap_aes_setkey(struct crypto_ablkcipher *tfm, const u8 *key,
 741                            unsigned int keylen)
 742 {
 743         struct omap_aes_ctx *ctx = crypto_ablkcipher_ctx(tfm);
 744         int ret;
 745
 746         if (keylen != AES_KEYSIZE_128 && keylen != AES_KEYSIZE_192 &&
 747                    keylen != AES_KEYSIZE_256)
 748                 return -EINVAL;
 749
 750         pr_debug("enter, keylen: %d\n", keylen);
 751
 752         memcpy(ctx->key, key, keylen);
 753         ctx->keylen = keylen;
 754
 755         crypto_skcipher_clear_flags(ctx->fallback, CRYPTO_TFM_REQ_MASK);
 756         crypto_skcipher_set_flags(ctx->fallback, tfm->base.crt_flags &
 757                                                  CRYPTO_TFM_REQ_MASK);
 758
 759         ret = crypto_skcipher_setkey(ctx->fallback, key, keylen);
 760         if (!ret)
 761                 return 0;
 762
 763         return 0;
 764 }
 765
 766 static int omap_aes_ecb_encrypt(struct ablkcipher_request *req)
 767 {
 768         return omap_aes_crypt(req, FLAGS_ENCRYPT);
 769 }
 770
 771 static int omap_aes_ecb_decrypt(struct ablkcipher_request *req)
 772 {
 773         return omap_aes_crypt(req, 0);
 774 }
 775
 776 static int omap_aes_cbc_encrypt(struct ablkcipher_request *req)
 777 {
 778         return omap_aes_crypt(req, FLAGS_ENCRYPT | FLAGS_CBC);
 779 }
 780
 781 static int omap_aes_cbc_decrypt(struct ablkcipher_request *req)
 782 {
 783         return omap_aes_crypt(req, FLAGS_CBC);
 784 }
 785
 786 static int omap_aes_ctr_encrypt(struct ablkcipher_request *req)
 787 {
 788         return omap_aes_crypt(req, FLAGS_ENCRYPT | FLAGS_CTR);
 789 }
 790
 791 static int omap_aes_ctr_decrypt(struct ablkcipher_request *req)
 792 {
 793         return omap_aes_crypt(req, FLAGS_CTR);
 794 }
 795
 796 static int omap_aes_cra_init(struct crypto_tfm *tfm)
 797 {
 798         const char *name = crypto_tfm_alg_name(tfm);
 799         const u32 flags = CRYPTO_ALG_ASYNC | CRYPTO_ALG_NEED_FALLBACK;
 800         struct omap_aes_ctx *ctx = crypto_tfm_ctx(tfm);
 801         struct crypto_skcipher *blk;
 802
 803         blk = crypto_alloc_skcipher(name, 0, flags);
 804         if (IS_ERR(blk))
 805                 return PTR_ERR(blk);
 806
 807         ctx->fallback = blk;
 808
 809         tfm->crt_ablkcipher.reqsize = sizeof(struct omap_aes_reqctx);
 810
 811         return 0;
 812 }
 813
 814 static void omap_aes_cra_exit(struct crypto_tfm *tfm)
 815 {
 816         struct omap_aes_ctx *ctx = crypto_tfm_ctx(tfm);
 817
 818         if (ctx->fallback)
 819                 crypto_free_skcipher(ctx->fallback);
 820
 821         ctx->fallback = NULL;
 822 }
 823
 824 /* ********************** ALGS ************************************ */
 825
 826 static struct crypto_alg algs_ecb_cbc[] = {
 827 {
 828         .cra_name               = "ecb(aes)",
 829         .cra_driver_name        = "ecb-aes-omap",
 830         .cra_priority           = 300,
 831         .cra_flags              = CRYPTO_ALG_TYPE_ABLKCIPHER |
 832                                   CRYPTO_ALG_KERN_DRIVER_ONLY |
 833                                   CRYPTO_ALG_ASYNC | CRYPTO_ALG_NEED_FALLBACK,
 834         .cra_blocksize          = AES_BLOCK_SIZE,
 835         .cra_ctxsize            = sizeof(struct omap_aes_ctx),
 836         .cra_alignmask          = 0,
 837         .cra_type               = &crypto_ablkcipher_type,
 838         .cra_module             = THIS_MODULE,
 839         .cra_init               = omap_aes_cra_init,
 840         .cra_exit               = omap_aes_cra_exit,
 841         .cra_u.ablkcipher = {
 842                 .min_keysize    = AES_MIN_KEY_SIZE,
 843                 .max_keysize    = AES_MAX_KEY_SIZE,
 844                 .setkey         = omap_aes_setkey,
 845                 .encrypt        = omap_aes_ecb_encrypt,
 846                 .decrypt        = omap_aes_ecb_decrypt,
 847         }
 848 },
 849 {
 850         .cra_name               = "cbc(aes)",
 851         .cra_driver_name        = "cbc-aes-omap",
 852         .cra_priority           = 300,
 853         .cra_flags              = CRYPTO_ALG_TYPE_ABLKCIPHER |
 854                                   CRYPTO_ALG_KERN_DRIVER_ONLY |
 855                                   CRYPTO_ALG_ASYNC | CRYPTO_ALG_NEED_FALLBACK,
 856         .cra_blocksize          = AES_BLOCK_SIZE,
 857         .cra_ctxsize            = sizeof(struct omap_aes_ctx),
 858         .cra_alignmask          = 0,
 859         .cra_type               = &crypto_ablkcipher_type,
 860         .cra_module             = THIS_MODULE,
 861         .cra_init               = omap_aes_cra_init,
 862         .cra_exit               = omap_aes_cra_exit,
 863         .cra_u.ablkcipher = {
 864                 .min_keysize    = AES_MIN_KEY_SIZE,
 865                 .max_keysize    = AES_MAX_KEY_SIZE,
 866                 .ivsize         = AES_BLOCK_SIZE,
 867                 .setkey         = omap_aes_setkey,
 868                 .encrypt        = omap_aes_cbc_encrypt,
 869                 .decrypt        = omap_aes_cbc_decrypt,
 870         }
 871 }
 872 };
 873
 874 static struct crypto_alg algs_ctr[] = {
 875 {
 876         .cra_name               = "ctr(aes)",
 877         .cra_driver_name        = "ctr-aes-omap",
 878         .cra_priority           = 300,
 879         .cra_flags              = CRYPTO_ALG_TYPE_ABLKCIPHER |
 880                                   CRYPTO_ALG_KERN_DRIVER_ONLY |
 881                                   CRYPTO_ALG_ASYNC | CRYPTO_ALG_NEED_FALLBACK,
 882         .cra_blocksize          = AES_BLOCK_SIZE,
 883         .cra_ctxsize            = sizeof(struct omap_aes_ctx),
 884         .cra_alignmask          = 0,
 885         .cra_type               = &crypto_ablkcipher_type,
 886         .cra_module             = THIS_MODULE,
 887         .cra_init               = omap_aes_cra_init,
 888         .cra_exit               = omap_aes_cra_exit,
 889         .cra_u.ablkcipher = {
 890                 .min_keysize    = AES_MIN_KEY_SIZE,
 891                 .max_keysize    = AES_MAX_KEY_SIZE,
 892                 .geniv          = "eseqiv",
 893                 .ivsize         = AES_BLOCK_SIZE,
 894                 .setkey         = omap_aes_setkey,
 895                 .encrypt        = omap_aes_ctr_encrypt,
 896                 .decrypt        = omap_aes_ctr_decrypt,
 897         }
 898 } ,
 899 };
 900
 901 static struct omap_aes_algs_info omap_aes_algs_info_ecb_cbc[] = {
 902         {
 903                 .algs_list      = algs_ecb_cbc,
 904                 .size           = ARRAY_SIZE(algs_ecb_cbc),
 905         },
 906 };
 907
 908 static const struct omap_aes_pdata omap_aes_pdata_omap2 = {
 909         .algs_info      = omap_aes_algs_info_ecb_cbc,
 910         .algs_info_size = ARRAY_SIZE(omap_aes_algs_info_ecb_cbc),
 911         .trigger        = omap_aes_dma_trigger_omap2,
 912         .key_ofs        = 0x1c,
 913         .iv_ofs         = 0x20,
 914         .ctrl_ofs       = 0x30,
 915         .data_ofs       = 0x34,
 916         .rev_ofs        = 0x44,
 917         .mask_ofs       = 0x48,
 918         .dma_enable_in  = BIT(2),
 919         .dma_enable_out = BIT(3),
 920         .dma_start      = BIT(5),
 921         .major_mask     = 0xf0,
 922         .major_shift    = 4,
 923         .minor_mask     = 0x0f,
 924         .minor_shift    = 0,
 925 };
 926
 927 #ifdef CONFIG_OF
 928 static struct omap_aes_algs_info omap_aes_algs_info_ecb_cbc_ctr[] = {
 929         {
 930                 .algs_list      = algs_ecb_cbc,
 931                 .size           = ARRAY_SIZE(algs_ecb_cbc),
 932         },
 933         {
 934                 .algs_list      = algs_ctr,
 935                 .size           = ARRAY_SIZE(algs_ctr),
 936         },
 937 };
 938
 939 static const struct omap_aes_pdata omap_aes_pdata_omap3 = {
 940         .algs_info      = omap_aes_algs_info_ecb_cbc_ctr,
 941         .algs_info_size = ARRAY_SIZE(omap_aes_algs_info_ecb_cbc_ctr),
 942         .trigger        = omap_aes_dma_trigger_omap2,
 943         .key_ofs        = 0x1c,
 944         .iv_ofs         = 0x20,
 945         .ctrl_ofs       = 0x30,
 946         .data_ofs       = 0x34,
 947         .rev_ofs        = 0x44,
 948         .mask_ofs       = 0x48,
 949         .dma_enable_in  = BIT(2),
 950         .dma_enable_out = BIT(3),
 951         .dma_start      = BIT(5),
 952         .major_mask     = 0xf0,
 953         .major_shift    = 4,
 954         .minor_mask     = 0x0f,
 955         .minor_shift    = 0,
 956 };
 957
 958 static const struct omap_aes_pdata omap_aes_pdata_omap4 = {
 959         .algs_info      = omap_aes_algs_info_ecb_cbc_ctr,
 960         .algs_info_size = ARRAY_SIZE(omap_aes_algs_info_ecb_cbc_ctr),
 961         .trigger        = omap_aes_dma_trigger_omap4,
 962         .key_ofs        = 0x3c,
 963         .iv_ofs         = 0x40,
 964         .ctrl_ofs       = 0x50,
 965         .data_ofs       = 0x60,
 966         .rev_ofs        = 0x80,
 967         .mask_ofs       = 0x84,
 968         .irq_status_ofs = 0x8c,
 969         .irq_enable_ofs = 0x90,
 970         .dma_enable_in  = BIT(5),
 971         .dma_enable_out = BIT(6),
 972         .major_mask     = 0x0700,
 973         .major_shift    = 8,
 974         .minor_mask     = 0x003f,
 975         .minor_shift    = 0,
 976 };
 977
 978 static irqreturn_t omap_aes_irq(int irq, void *dev_id)
 979 {
 980         struct omap_aes_dev *dd = dev_id;
 981         u32 status, i;
 982         u32 *src, *dst;
 983
 984         status = omap_aes_read(dd, AES_REG_IRQ_STATUS(dd));
 985         if (status & AES_REG_IRQ_DATA_IN) {
 986                 omap_aes_write(dd, AES_REG_IRQ_ENABLE(dd), 0x0);
 987
 988                 BUG_ON(!dd->in_sg);
 989
 990                 BUG_ON(_calc_walked(in) > dd->in_sg->length);
 991
 992                 src = sg_virt(dd->in_sg) + _calc_walked(in);
 993
 994                 for (i = 0; i < AES_BLOCK_WORDS; i++) {
 995                         omap_aes_write(dd, AES_REG_DATA_N(dd, i), *src);
 996
 997                         scatterwalk_advance(&dd->in_walk, 4);
 998                         if (dd->in_sg->length == _calc_walked(in)) {
 999                                 dd->in_sg = sg_next(dd->in_sg);
1000                                 if (dd->in_sg) {
1001                                         scatterwalk_start(&dd->in_walk,
1002                                                           dd->in_sg);
1003                                         src = sg_virt(dd->in_sg) +
1004                                               _calc_walked(in);
1005                                 }
1006                         } else {
1007                                 src++;
1008                         }
1009                 }
1010
1011                 /* Clear IRQ status */
1012                 status &= ~AES_REG_IRQ_DATA_IN;
1013                 omap_aes_write(dd, AES_REG_IRQ_STATUS(dd), status);
1014
1015                 /* Enable DATA_OUT interrupt */
1016                 omap_aes_write(dd, AES_REG_IRQ_ENABLE(dd), 0x4);
1017
1018         } else if (status & AES_REG_IRQ_DATA_OUT) {
1019                 omap_aes_write(dd, AES_REG_IRQ_ENABLE(dd), 0x0);
1020
1021                 BUG_ON(!dd->out_sg);
1022
1023                 BUG_ON(_calc_walked(out) > dd->out_sg->length);
1024
1025                 dst = sg_virt(dd->out_sg) + _calc_walked(out);
1026
1027                 for (i = 0; i < AES_BLOCK_WORDS; i++) {
1028                         *dst = omap_aes_read(dd, AES_REG_DATA_N(dd, i));
1029                         scatterwalk_advance(&dd->out_walk, 4);
1030                         if (dd->out_sg->length == _calc_walked(out)) {
1031                                 dd->out_sg = sg_next(dd->out_sg);
1032                                 if (dd->out_sg) {
1033                                         scatterwalk_start(&dd->out_walk,
1034                                                           dd->out_sg);
1035                                         dst = sg_virt(dd->out_sg) +
1036                                               _calc_walked(out);
1037                                 }
1038                         } else {
1039                                 dst++;
1040                         }
1041                 }
1042
1043                 dd->total -= min_t(size_t, AES_BLOCK_SIZE, dd->total);
1044
1045                 /* Clear IRQ status */
1046                 status &= ~AES_REG_IRQ_DATA_OUT;
1047                 omap_aes_write(dd, AES_REG_IRQ_STATUS(dd), status);
1048
1049                 if (!dd->total)
1050                         /* All bytes read! */
1051                         tasklet_schedule(&dd->done_task);
1052                 else
1053                         /* Enable DATA_IN interrupt for next block */
1054                         omap_aes_write(dd, AES_REG_IRQ_ENABLE(dd), 0x2);
1055         }
1056
1057         return IRQ_HANDLED;
1058 }
1059
1060 static const struct of_device_id omap_aes_of_match[] = {
1061         {
1062                 .compatible     = "ti,omap2-aes",
1063                 .data           = &omap_aes_pdata_omap2,
1064         },
1065         {
1066                 .compatible     = "ti,omap3-aes",
1067                 .data           = &omap_aes_pdata_omap3,
1068         },
1069         {
1070                 .compatible     = "ti,omap4-aes",
1071                 .data           = &omap_aes_pdata_omap4,
1072         },
1073         {},
1074 };
1075 MODULE_DEVICE_TABLE(of, omap_aes_of_match);
1076
1077 static int omap_aes_get_res_of(struct omap_aes_dev *dd,
1078                 struct device *dev, struct resource *res)
1079 {
1080         struct device_node *node = dev->of_node;
1081         const struct of_device_id *match;
1082         int err = 0;
1083
1084         match = of_match_device(of_match_ptr(omap_aes_of_match), dev);
1085         if (!match) {
1086                 dev_err(dev, "no compatible OF match\n");
1087                 err = -EINVAL;
1088                 goto err;
1089         }
1090
1091         err = of_address_to_resource(node, 0, res);
1092         if (err < 0) {
1093                 dev_err(dev, "can't translate OF node address\n");
1094                 err = -EINVAL;
1095                 goto err;
1096         }
1097
1098         dd->pdata = match->data;
1099
1100 err:
1101         return err;
1102 }
1103 #else
1104 static const struct of_device_id omap_aes_of_match[] = {
1105         {},
1106 };
1107
1108 static int omap_aes_get_res_of(struct omap_aes_dev *dd,
1109                 struct device *dev, struct resource *res)
1110 {
1111         return -EINVAL;
1112 }
1113 #endif
1114
1115 static int omap_aes_get_res_pdev(struct omap_aes_dev *dd,
1116                 struct platform_device *pdev, struct resource *res)
1117 {
1118         struct device *dev = &pdev->dev;
1119         struct resource *r;
1120         int err = 0;
1121
1122         /* Get the base address */
1123         r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1124         if (!r) {
1125                 dev_err(dev, "no MEM resource info\n");
1126                 err = -ENODEV;
1127                 goto err;
1128         }
1129         memcpy(res, r, sizeof(*res));
1130
1131         /* Only OMAP2/3 can be non-DT */
1132         dd->pdata = &omap_aes_pdata_omap2;
1133
1134 err:
1135         return err;
1136 }
1137
1138 static int omap_aes_probe(struct platform_device *pdev)
1139 {
1140         struct device *dev = &pdev->dev;
1141         struct omap_aes_dev *dd;
1142         struct crypto_alg *algp;
1143         struct resource res;
1144         int err = -ENOMEM, i, j, irq = -1;
1145         u32 reg;
1146
1147         dd = devm_kzalloc(dev, sizeof(struct omap_aes_dev), GFP_KERNEL);
1148         if (dd == NULL) {
1149                 dev_err(dev, "unable to alloc data struct.\n");
1150                 goto err_data;
1151         }
1152         dd->dev = dev;
1153         platform_set_drvdata(pdev, dd);
1154
1155         err = (dev->of_node) ? omap_aes_get_res_of(dd, dev, &res) :
1156                                omap_aes_get_res_pdev(dd, pdev, &res);
1157         if (err)
1158                 goto err_res;
1159
1160         dd->io_base = devm_ioremap_resource(dev, &res);
1161         if (IS_ERR(dd->io_base)) {
1162                 err = PTR_ERR(dd->io_base);
1163                 goto err_res;
1164         }
1165         dd->phys_base = res.start;
1166
1167         pm_runtime_use_autosuspend(dev);
1168         pm_runtime_set_autosuspend_delay(dev, DEFAULT_AUTOSUSPEND_DELAY);
1169
1170         pm_runtime_enable(dev);
1171         err = pm_runtime_get_sync(dev);
1172         if (err < 0) {
1173                 dev_err(dev, "%s: failed to get_sync(%d)\n",
1174                         __func__, err);
1175                 goto err_res;
1176         }
1177
1178         omap_aes_dma_stop(dd);
1179
1180         reg = omap_aes_read(dd, AES_REG_REV(dd));
1181
1182         pm_runtime_put_sync(dev);
1183
1184         dev_info(dev, "OMAP AES hw accel rev: %u.%u\n",
1185                  (reg & dd->pdata->major_mask) >> dd->pdata->major_shift,
1186                  (reg & dd->pdata->minor_mask) >> dd->pdata->minor_shift);
1187
1188         tasklet_init(&dd->done_task, omap_aes_done_task, (unsigned long)dd);
1189
1190         err = omap_aes_dma_init(dd);
1191         if (err == -EPROBE_DEFER) {
1192                 goto err_irq;
1193         } else if (err && AES_REG_IRQ_STATUS(dd) && AES_REG_IRQ_ENABLE(dd)) {
1194                 dd->pio_only = 1;
1195
1196                 irq = platform_get_irq(pdev, 0);
1197                 if (irq < 0) {
1198                         dev_err(dev, "can't get IRQ resource\n");
1199                         goto err_irq;
1200                 }
1201
1202                 err = devm_request_irq(dev, irq, omap_aes_irq, 0,
1203                                 dev_name(dev), dd);
1204                 if (err) {
1205                         dev_err(dev, "Unable to grab omap-aes IRQ\n");
1206                         goto err_irq;
1207                 }
1208         }
1209
1210
1211         INIT_LIST_HEAD(&dd->list);
1212         spin_lock(&list_lock);
1213         list_add_tail(&dd->list, &dev_list);
1214         spin_unlock(&list_lock);
1215
1216         /* Initialize crypto engine */
1217         dd->engine = crypto_engine_alloc_init(dev, 1);
1218         if (!dd->engine) {
1219                 err = -ENOMEM;
1220                 goto err_engine;
1221         }
1222
1223         dd->engine->prepare_cipher_request = omap_aes_prepare_req;
1224         dd->engine->cipher_one_request = omap_aes_crypt_req;
1225         err = crypto_engine_start(dd->engine);
1226         if (err)
1227                 goto err_engine;
1228
1229         for (i = 0; i < dd->pdata->algs_info_size; i++) {
1230                 if (!dd->pdata->algs_info[i].registered) {
1231                         for (j = 0; j < dd->pdata->algs_info[i].size; j++) {
1232                                 algp = &dd->pdata->algs_info[i].algs_list[j];
1233
1234                                 pr_debug("reg alg: %s\n", algp->cra_name);
1235                                 INIT_LIST_HEAD(&algp->cra_list);
1236
1237                                 err = crypto_register_alg(algp);
1238                                 if (err)
1239                                         goto err_algs;
1240
1241                                 dd->pdata->algs_info[i].registered++;
1242                         }
1243                 }
1244         }
1245
1246         return 0;
1247 err_algs:
1248         for (i = dd->pdata->algs_info_size - 1; i >= 0; i--)
1249                 for (j = dd->pdata->algs_info[i].registered - 1; j >= 0; j--)
1250                         crypto_unregister_alg(
1251                                         &dd->pdata->algs_info[i].algs_list[j]);
1252
1253 err_engine:
1254         if (dd->engine)
1255                 crypto_engine_exit(dd->engine);
1256
1257         omap_aes_dma_cleanup(dd);
1258 err_irq:
1259         tasklet_kill(&dd->done_task);
1260         pm_runtime_disable(dev);
1261 err_res:
1262         dd = NULL;
1263 err_data:
1264         dev_err(dev, "initialization failed.\n");
1265         return err;
1266 }
1267
1268 static int omap_aes_remove(struct platform_device *pdev)
1269 {
1270         struct omap_aes_dev *dd = platform_get_drvdata(pdev);
1271         int i, j;
1272
1273         if (!dd)
1274                 return -ENODEV;
1275
1276         spin_lock(&list_lock);
1277         list_del(&dd->list);
1278         spin_unlock(&list_lock);
1279
1280         for (i = dd->pdata->algs_info_size - 1; i >= 0; i--)
1281                 for (j = dd->pdata->algs_info[i].registered - 1; j >= 0; j--)
1282                         crypto_unregister_alg(
1283                                         &dd->pdata->algs_info[i].algs_list[j]);
1284
1285         crypto_engine_exit(dd->engine);
1286         tasklet_kill(&dd->done_task);
1287         omap_aes_dma_cleanup(dd);
1288         pm_runtime_disable(dd->dev);
1289         dd = NULL;
1290
1291         return 0;
1292 }
1293
1294 #ifdef CONFIG_PM_SLEEP
1295 static int omap_aes_suspend(struct device *dev)
1296 {
1297         pm_runtime_put_sync(dev);
1298         return 0;
1299 }
1300
1301 static int omap_aes_resume(struct device *dev)
1302 {
1303         pm_runtime_get_sync(dev);
1304         return 0;
1305 }
1306 #endif
1307
1308 static SIMPLE_DEV_PM_OPS(omap_aes_pm_ops, omap_aes_suspend, omap_aes_resume);
1309
1310 static struct platform_driver omap_aes_driver = {
1311         .probe  = omap_aes_probe,
1312         .remove = omap_aes_remove,
1313         .driver = {
1314                 .name   = "omap-aes",
1315                 .pm     = &omap_aes_pm_ops,
1316                 .of_match_table = omap_aes_of_match,
1317         },
1318 };
1319
1320 module_platform_driver(omap_aes_driver);
1321
1322 MODULE_DESCRIPTION("OMAP AES hw acceleration support.");
1323 MODULE_LICENSE("GPL v2");
1324 MODULE_AUTHOR("Dmitry Kasatkin");
1325