drivers/soc/imx/imx8m-blk-ctrl.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2
   3 /*
   4  * Copyright 2021 Pengutronix, Lucas Stach <[email protected]>
   5  */
   6
   7 #include <linux/device.h>
   8 #include <linux/interconnect.h>
   9 #include <linux/module.h>
  10 #include <linux/of_device.h>
  11 #include <linux/platform_device.h>
  12 #include <linux/pm_domain.h>
  13 #include <linux/pm_runtime.h>
  14 #include <linux/regmap.h>
  15 #include <linux/clk.h>
  16
  17 #include <dt-bindings/power/imx8mm-power.h>
  18 #include <dt-bindings/power/imx8mn-power.h>
  19 #include <dt-bindings/power/imx8mp-power.h>
  20 #include <dt-bindings/power/imx8mq-power.h>
  21
  22 #define BLK_SFT_RSTN    0x0
  23 #define BLK_CLK_EN      0x4
  24 #define BLK_MIPI_RESET_DIV      0x8 /* Mini/Nano/Plus DISPLAY_BLK_CTRL only */
  25
  26 struct imx8m_blk_ctrl_domain;
  27
  28 struct imx8m_blk_ctrl {
  29         struct device *dev;
  30         struct notifier_block power_nb;
  31         struct device *bus_power_dev;
  32         struct regmap *regmap;
  33         struct imx8m_blk_ctrl_domain *domains;
  34         struct genpd_onecell_data onecell_data;
  35 };
  36
  37 struct imx8m_blk_ctrl_domain_data {
  38         const char *name;
  39         const char * const *clk_names;
  40         int num_clks;
  41         const char * const *path_names;
  42         int num_paths;
  43         const char *gpc_name;
  44         u32 rst_mask;
  45         u32 clk_mask;
  46
  47         /*
  48          * i.MX8M Mini, Nano and Plus have a third DISPLAY_BLK_CTRL register
  49          * which is used to control the reset for the MIPI Phy.
  50          * Since it's only present in certain circumstances,
  51          * an if-statement should be used before setting and clearing this
  52          * register.
  53          */
  54         u32 mipi_phy_rst_mask;
  55 };
  56
  57 #define DOMAIN_MAX_CLKS 4
  58 #define DOMAIN_MAX_PATHS 4
  59
  60 struct imx8m_blk_ctrl_domain {
  61         struct generic_pm_domain genpd;
  62         const struct imx8m_blk_ctrl_domain_data *data;
  63         struct clk_bulk_data clks[DOMAIN_MAX_CLKS];
  64         struct icc_bulk_data paths[DOMAIN_MAX_PATHS];
  65         struct device *power_dev;
  66         struct imx8m_blk_ctrl *bc;
  67         int num_paths;
  68 };
  69
  70 struct imx8m_blk_ctrl_data {
  71         int max_reg;
  72         notifier_fn_t power_notifier_fn;
  73         const struct imx8m_blk_ctrl_domain_data *domains;
  74         int num_domains;
  75 };
  76
  77 static inline struct imx8m_blk_ctrl_domain *
  78 to_imx8m_blk_ctrl_domain(struct generic_pm_domain *genpd)
  79 {
  80         return container_of(genpd, struct imx8m_blk_ctrl_domain, genpd);
  81 }
  82
  83 static int imx8m_blk_ctrl_power_on(struct generic_pm_domain *genpd)
  84 {
  85         struct imx8m_blk_ctrl_domain *domain = to_imx8m_blk_ctrl_domain(genpd);
  86         const struct imx8m_blk_ctrl_domain_data *data = domain->data;
  87         struct imx8m_blk_ctrl *bc = domain->bc;
  88         int ret;
  89
  90         /* make sure bus domain is awake */
  91         ret = pm_runtime_get_sync(bc->bus_power_dev);
  92         if (ret < 0) {
  93                 pm_runtime_put_noidle(bc->bus_power_dev);
  94                 dev_err(bc->dev, "failed to power up bus domain\n");
  95                 return ret;
  96         }
  97
  98         /* put devices into reset */
  99         regmap_clear_bits(bc->regmap, BLK_SFT_RSTN, data->rst_mask);
 100         if (data->mipi_phy_rst_mask)
 101                 regmap_clear_bits(bc->regmap, BLK_MIPI_RESET_DIV, data->mipi_phy_rst_mask);
 102
 103         /* enable upstream and blk-ctrl clocks to allow reset to propagate */
 104         ret = clk_bulk_prepare_enable(data->num_clks, domain->clks);
 105         if (ret) {
 106                 dev_err(bc->dev, "failed to enable clocks\n");
 107                 goto bus_put;
 108         }
 109         regmap_set_bits(bc->regmap, BLK_CLK_EN, data->clk_mask);
 110
 111         /* power up upstream GPC domain */
 112         ret = pm_runtime_get_sync(domain->power_dev);
 113         if (ret < 0) {
 114                 dev_err(bc->dev, "failed to power up peripheral domain\n");
 115                 goto clk_disable;
 116         }
 117
 118         /* wait for reset to propagate */
 119         udelay(5);
 120
 121         /* release reset */
 122         regmap_set_bits(bc->regmap, BLK_SFT_RSTN, data->rst_mask);
 123         if (data->mipi_phy_rst_mask)
 124                 regmap_set_bits(bc->regmap, BLK_MIPI_RESET_DIV, data->mipi_phy_rst_mask);
 125
 126         ret = icc_bulk_set_bw(domain->num_paths, domain->paths);
 127         if (ret)
 128                 dev_err(bc->dev, "failed to set icc bw\n");
 129
 130         /* disable upstream clocks */
 131         clk_bulk_disable_unprepare(data->num_clks, domain->clks);
 132
 133         return 0;
 134
 135 clk_disable:
 136         clk_bulk_disable_unprepare(data->num_clks, domain->clks);
 137 bus_put:
 138         pm_runtime_put(bc->bus_power_dev);
 139
 140         return ret;
 141 }
 142
 143 static int imx8m_blk_ctrl_power_off(struct generic_pm_domain *genpd)
 144 {
 145         struct imx8m_blk_ctrl_domain *domain = to_imx8m_blk_ctrl_domain(genpd);
 146         const struct imx8m_blk_ctrl_domain_data *data = domain->data;
 147         struct imx8m_blk_ctrl *bc = domain->bc;
 148
 149         /* put devices into reset and disable clocks */
 150         if (data->mipi_phy_rst_mask)
 151                 regmap_clear_bits(bc->regmap, BLK_MIPI_RESET_DIV, data->mipi_phy_rst_mask);
 152
 153         regmap_clear_bits(bc->regmap, BLK_SFT_RSTN, data->rst_mask);
 154         regmap_clear_bits(bc->regmap, BLK_CLK_EN, data->clk_mask);
 155
 156         /* power down upstream GPC domain */
 157         pm_runtime_put(domain->power_dev);
 158
 159         /* allow bus domain to suspend */
 160         pm_runtime_put(bc->bus_power_dev);
 161
 162         return 0;
 163 }
 164
 165 static struct lock_class_key blk_ctrl_genpd_lock_class;
 166
 167 static int imx8m_blk_ctrl_probe(struct platform_device *pdev)
 168 {
 169         const struct imx8m_blk_ctrl_data *bc_data;
 170         struct device *dev = &pdev->dev;
 171         struct imx8m_blk_ctrl *bc;
 172         void __iomem *base;
 173         int i, ret;
 174
 175         struct regmap_config regmap_config = {
 176                 .reg_bits       = 32,
 177                 .val_bits       = 32,
 178                 .reg_stride     = 4,
 179         };
 180
 181         bc = devm_kzalloc(dev, sizeof(*bc), GFP_KERNEL);
 182         if (!bc)
 183                 return -ENOMEM;
 184
 185         bc->dev = dev;
 186
 187         bc_data = of_device_get_match_data(dev);
 188
 189         base = devm_platform_ioremap_resource(pdev, 0);
 190         if (IS_ERR(base))
 191                 return PTR_ERR(base);
 192
 193         regmap_config.max_register = bc_data->max_reg;
 194         bc->regmap = devm_regmap_init_mmio(dev, base, &regmap_config);
 195         if (IS_ERR(bc->regmap))
 196                 return dev_err_probe(dev, PTR_ERR(bc->regmap),
 197                                      "failed to init regmap\n");
 198
 199         bc->domains = devm_kcalloc(dev, bc_data->num_domains,
 200                                    sizeof(struct imx8m_blk_ctrl_domain),
 201                                    GFP_KERNEL);
 202         if (!bc->domains)
 203                 return -ENOMEM;
 204
 205         bc->onecell_data.num_domains = bc_data->num_domains;
 206         bc->onecell_data.domains =
 207                 devm_kcalloc(dev, bc_data->num_domains,
 208                              sizeof(struct generic_pm_domain *), GFP_KERNEL);
 209         if (!bc->onecell_data.domains)
 210                 return -ENOMEM;
 211
 212         bc->bus_power_dev = genpd_dev_pm_attach_by_name(dev, "bus");
 213         if (IS_ERR(bc->bus_power_dev)) {
 214                 if (PTR_ERR(bc->bus_power_dev) == -ENODEV)
 215                         return dev_err_probe(dev, -EPROBE_DEFER,
 216                                              "failed to attach power domain \"bus\"\n");
 217                 else
 218                         return dev_err_probe(dev, PTR_ERR(bc->bus_power_dev),
 219                                              "failed to attach power domain \"bus\"\n");
 220         }
 221
 222         for (i = 0; i < bc_data->num_domains; i++) {
 223                 const struct imx8m_blk_ctrl_domain_data *data = &bc_data->domains[i];
 224                 struct imx8m_blk_ctrl_domain *domain = &bc->domains[i];
 225                 int j;
 226
 227                 domain->data = data;
 228                 domain->num_paths = data->num_paths;
 229
 230                 for (j = 0; j < data->num_clks; j++)
 231                         domain->clks[j].id = data->clk_names[j];
 232
 233                 for (j = 0; j < data->num_paths; j++) {
 234                         domain->paths[j].name = data->path_names[j];
 235                         /* Fake value for now, just let ICC could configure NoC mode/priority */
 236                         domain->paths[j].avg_bw = 1;
 237                         domain->paths[j].peak_bw = 1;
 238                 }
 239
 240                 ret = devm_of_icc_bulk_get(dev, data->num_paths, domain->paths);
 241                 if (ret) {
 242                         if (ret != -EPROBE_DEFER) {
 243                                 dev_warn_once(dev, "Could not get interconnect paths, NoC will stay unconfigured!\n");
 244                                 domain->num_paths = 0;
 245                         } else {
 246                                 dev_err_probe(dev, ret, "failed to get noc entries\n");
 247                                 goto cleanup_pds;
 248                         }
 249                 }
 250
 251                 ret = devm_clk_bulk_get(dev, data->num_clks, domain->clks);
 252                 if (ret) {
 253                         dev_err_probe(dev, ret, "failed to get clock\n");
 254                         goto cleanup_pds;
 255                 }
 256
 257                 domain->power_dev =
 258                         dev_pm_domain_attach_by_name(dev, data->gpc_name);
 259                 if (IS_ERR(domain->power_dev)) {
 260                         dev_err_probe(dev, PTR_ERR(domain->power_dev),
 261                                       "failed to attach power domain \"%s\"\n",
 262                                       data->gpc_name);
 263                         ret = PTR_ERR(domain->power_dev);
 264                         goto cleanup_pds;
 265                 }
 266
 267                 domain->genpd.name = data->name;
 268                 domain->genpd.power_on = imx8m_blk_ctrl_power_on;
 269                 domain->genpd.power_off = imx8m_blk_ctrl_power_off;
 270                 domain->bc = bc;
 271
 272                 ret = pm_genpd_init(&domain->genpd, NULL, true);
 273                 if (ret) {
 274                         dev_err_probe(dev, ret,
 275                                       "failed to init power domain \"%s\"\n",
 276                                       data->gpc_name);
 277                         dev_pm_domain_detach(domain->power_dev, true);
 278                         goto cleanup_pds;
 279                 }
 280
 281                 /*
 282                  * We use runtime PM to trigger power on/off of the upstream GPC
 283                  * domain, as a strict hierarchical parent/child power domain
 284                  * setup doesn't allow us to meet the sequencing requirements.
 285                  * This means we have nested locking of genpd locks, without the
 286                  * nesting being visible at the genpd level, so we need a
 287                  * separate lock class to make lockdep aware of the fact that
 288                  * this are separate domain locks that can be nested without a
 289                  * self-deadlock.
 290                  */
 291                 lockdep_set_class(&domain->genpd.mlock,
 292                                   &blk_ctrl_genpd_lock_class);
 293
 294                 bc->onecell_data.domains[i] = &domain->genpd;
 295         }
 296
 297         ret = of_genpd_add_provider_onecell(dev->of_node, &bc->onecell_data);
 298         if (ret) {
 299                 dev_err_probe(dev, ret, "failed to add power domain provider\n");
 300                 goto cleanup_pds;
 301         }
 302
 303         bc->power_nb.notifier_call = bc_data->power_notifier_fn;
 304         ret = dev_pm_genpd_add_notifier(bc->bus_power_dev, &bc->power_nb);
 305         if (ret) {
 306                 dev_err_probe(dev, ret, "failed to add power notifier\n");
 307                 goto cleanup_provider;
 308         }
 309
 310         dev_set_drvdata(dev, bc);
 311
 312         return 0;
 313
 314 cleanup_provider:
 315         of_genpd_del_provider(dev->of_node);
 316 cleanup_pds:
 317         for (i--; i >= 0; i--) {
 318                 pm_genpd_remove(&bc->domains[i].genpd);
 319                 dev_pm_domain_detach(bc->domains[i].power_dev, true);
 320         }
 321
 322         dev_pm_domain_detach(bc->bus_power_dev, true);
 323
 324         return ret;
 325 }
 326
 327 static int imx8m_blk_ctrl_remove(struct platform_device *pdev)
 328 {
 329         struct imx8m_blk_ctrl *bc = dev_get_drvdata(&pdev->dev);
 330         int i;
 331
 332         of_genpd_del_provider(pdev->dev.of_node);
 333
 334         for (i = 0; bc->onecell_data.num_domains; i++) {
 335                 struct imx8m_blk_ctrl_domain *domain = &bc->domains[i];
 336
 337                 pm_genpd_remove(&domain->genpd);
 338                 dev_pm_domain_detach(domain->power_dev, true);
 339         }
 340
 341         dev_pm_genpd_remove_notifier(bc->bus_power_dev);
 342
 343         dev_pm_domain_detach(bc->bus_power_dev, true);
 344
 345         return 0;
 346 }
 347
 348 #ifdef CONFIG_PM_SLEEP
 349 static int imx8m_blk_ctrl_suspend(struct device *dev)
 350 {
 351         struct imx8m_blk_ctrl *bc = dev_get_drvdata(dev);
 352         int ret, i;
 353
 354         /*
 355          * This may look strange, but is done so the generic PM_SLEEP code
 356          * can power down our domains and more importantly power them up again
 357          * after resume, without tripping over our usage of runtime PM to
 358          * control the upstream GPC domains. Things happen in the right order
 359          * in the system suspend/resume paths due to the device parent/child
 360          * hierarchy.
 361          */
 362         ret = pm_runtime_get_sync(bc->bus_power_dev);
 363         if (ret < 0) {
 364                 pm_runtime_put_noidle(bc->bus_power_dev);
 365                 return ret;
 366         }
 367
 368         for (i = 0; i < bc->onecell_data.num_domains; i++) {
 369                 struct imx8m_blk_ctrl_domain *domain = &bc->domains[i];
 370
 371                 ret = pm_runtime_get_sync(domain->power_dev);
 372                 if (ret < 0) {
 373                         pm_runtime_put_noidle(domain->power_dev);
 374                         goto out_fail;
 375                 }
 376         }
 377
 378         return 0;
 379
 380 out_fail:
 381         for (i--; i >= 0; i--)
 382                 pm_runtime_put(bc->domains[i].power_dev);
 383
 384         pm_runtime_put(bc->bus_power_dev);
 385
 386         return ret;
 387 }
 388
 389 static int imx8m_blk_ctrl_resume(struct device *dev)
 390 {
 391         struct imx8m_blk_ctrl *bc = dev_get_drvdata(dev);
 392         int i;
 393
 394         for (i = 0; i < bc->onecell_data.num_domains; i++)
 395                 pm_runtime_put(bc->domains[i].power_dev);
 396
 397         pm_runtime_put(bc->bus_power_dev);
 398
 399         return 0;
 400 }
 401 #endif
 402
 403 static const struct dev_pm_ops imx8m_blk_ctrl_pm_ops = {
 404         SET_SYSTEM_SLEEP_PM_OPS(imx8m_blk_ctrl_suspend, imx8m_blk_ctrl_resume)
 405 };
 406
 407 static int imx8mm_vpu_power_notifier(struct notifier_block *nb,
 408                                      unsigned long action, void *data)
 409 {
 410         struct imx8m_blk_ctrl *bc = container_of(nb, struct imx8m_blk_ctrl,
 411                                                  power_nb);
 412
 413         if (action != GENPD_NOTIFY_ON && action != GENPD_NOTIFY_PRE_OFF)
 414                 return NOTIFY_OK;
 415
 416         /*
 417          * The ADB in the VPUMIX domain has no separate reset and clock
 418          * enable bits, but is ungated together with the VPU clocks. To
 419          * allow the handshake with the GPC to progress we put the VPUs
 420          * in reset and ungate the clocks.
 421          */
 422         regmap_clear_bits(bc->regmap, BLK_SFT_RSTN, BIT(0) | BIT(1) | BIT(2));
 423         regmap_set_bits(bc->regmap, BLK_CLK_EN, BIT(0) | BIT(1) | BIT(2));
 424
 425         if (action == GENPD_NOTIFY_ON) {
 426                 /*
 427                  * On power up we have no software backchannel to the GPC to
 428                  * wait for the ADB handshake to happen, so we just delay for a
 429                  * bit. On power down the GPC driver waits for the handshake.
 430                  */
 431                 udelay(5);
 432
 433                 /* set "fuse" bits to enable the VPUs */
 434                 regmap_set_bits(bc->regmap, 0x8, 0xffffffff);
 435                 regmap_set_bits(bc->regmap, 0xc, 0xffffffff);
 436                 regmap_set_bits(bc->regmap, 0x10, 0xffffffff);
 437                 regmap_set_bits(bc->regmap, 0x14, 0xffffffff);
 438         }
 439
 440         return NOTIFY_OK;
 441 }
 442
 443 static const struct imx8m_blk_ctrl_domain_data imx8mm_vpu_blk_ctl_domain_data[] = {
 444         [IMX8MM_VPUBLK_PD_G1] = {
 445                 .name = "vpublk-g1",
 446                 .clk_names = (const char *[]){ "g1", },
 447                 .num_clks = 1,
 448                 .gpc_name = "g1",
 449                 .rst_mask = BIT(1),
 450                 .clk_mask = BIT(1),
 451         },
 452         [IMX8MM_VPUBLK_PD_G2] = {
 453                 .name = "vpublk-g2",
 454                 .clk_names = (const char *[]){ "g2", },
 455                 .num_clks = 1,
 456                 .gpc_name = "g2",
 457                 .rst_mask = BIT(0),
 458                 .clk_mask = BIT(0),
 459         },
 460         [IMX8MM_VPUBLK_PD_H1] = {
 461                 .name = "vpublk-h1",
 462                 .clk_names = (const char *[]){ "h1", },
 463                 .num_clks = 1,
 464                 .gpc_name = "h1",
 465                 .rst_mask = BIT(2),
 466                 .clk_mask = BIT(2),
 467         },
 468 };
 469
 470 static const struct imx8m_blk_ctrl_data imx8mm_vpu_blk_ctl_dev_data = {
 471         .max_reg = 0x18,
 472         .power_notifier_fn = imx8mm_vpu_power_notifier,
 473         .domains = imx8mm_vpu_blk_ctl_domain_data,
 474         .num_domains = ARRAY_SIZE(imx8mm_vpu_blk_ctl_domain_data),
 475 };
 476
 477 static const struct imx8m_blk_ctrl_domain_data imx8mp_vpu_blk_ctl_domain_data[] = {
 478         [IMX8MP_VPUBLK_PD_G1] = {
 479                 .name = "vpublk-g1",
 480                 .clk_names = (const char *[]){ "g1", },
 481                 .num_clks = 1,
 482                 .gpc_name = "g1",
 483                 .rst_mask = BIT(1),
 484                 .clk_mask = BIT(1),
 485                 .path_names = (const char *[]){"g1"},
 486                 .num_paths = 1,
 487         },
 488         [IMX8MP_VPUBLK_PD_G2] = {
 489                 .name = "vpublk-g2",
 490                 .clk_names = (const char *[]){ "g2", },
 491                 .num_clks = 1,
 492                 .gpc_name = "g2",
 493                 .rst_mask = BIT(0),
 494                 .clk_mask = BIT(0),
 495                 .path_names = (const char *[]){"g2"},
 496                 .num_paths = 1,
 497         },
 498         [IMX8MP_VPUBLK_PD_VC8000E] = {
 499                 .name = "vpublk-vc8000e",
 500                 .clk_names = (const char *[]){ "vc8000e", },
 501                 .num_clks = 1,
 502                 .gpc_name = "vc8000e",
 503                 .rst_mask = BIT(2),
 504                 .clk_mask = BIT(2),
 505                 .path_names = (const char *[]){"vc8000e"},
 506                 .num_paths = 1,
 507         },
 508 };
 509
 510 static const struct imx8m_blk_ctrl_data imx8mp_vpu_blk_ctl_dev_data = {
 511         .max_reg = 0x18,
 512         .power_notifier_fn = imx8mm_vpu_power_notifier,
 513         .domains = imx8mp_vpu_blk_ctl_domain_data,
 514         .num_domains = ARRAY_SIZE(imx8mp_vpu_blk_ctl_domain_data),
 515 };
 516
 517 static int imx8mm_disp_power_notifier(struct notifier_block *nb,
 518                                       unsigned long action, void *data)
 519 {
 520         struct imx8m_blk_ctrl *bc = container_of(nb, struct imx8m_blk_ctrl,
 521                                                  power_nb);
 522
 523         if (action != GENPD_NOTIFY_ON && action != GENPD_NOTIFY_PRE_OFF)
 524                 return NOTIFY_OK;
 525
 526         /* Enable bus clock and deassert bus reset */
 527         regmap_set_bits(bc->regmap, BLK_CLK_EN, BIT(12));
 528         regmap_set_bits(bc->regmap, BLK_SFT_RSTN, BIT(6));
 529
 530         /*
 531          * On power up we have no software backchannel to the GPC to
 532          * wait for the ADB handshake to happen, so we just delay for a
 533          * bit. On power down the GPC driver waits for the handshake.
 534          */
 535         if (action == GENPD_NOTIFY_ON)
 536                 udelay(5);
 537
 538
 539         return NOTIFY_OK;
 540 }
 541
 542 static const struct imx8m_blk_ctrl_domain_data imx8mm_disp_blk_ctl_domain_data[] = {
 543         [IMX8MM_DISPBLK_PD_CSI_BRIDGE] = {
 544                 .name = "dispblk-csi-bridge",
 545                 .clk_names = (const char *[]){ "csi-bridge-axi", "csi-bridge-apb",
 546                                                "csi-bridge-core", },
 547                 .num_clks = 3,
 548                 .gpc_name = "csi-bridge",
 549                 .rst_mask = BIT(0) | BIT(1) | BIT(2),
 550                 .clk_mask = BIT(0) | BIT(1) | BIT(2) | BIT(3) | BIT(4) | BIT(5),
 551         },
 552         [IMX8MM_DISPBLK_PD_LCDIF] = {
 553                 .name = "dispblk-lcdif",
 554                 .clk_names = (const char *[]){ "lcdif-axi", "lcdif-apb", "lcdif-pix", },
 555                 .num_clks = 3,
 556                 .gpc_name = "lcdif",
 557                 .clk_mask = BIT(6) | BIT(7),
 558         },
 559         [IMX8MM_DISPBLK_PD_MIPI_DSI] = {
 560                 .name = "dispblk-mipi-dsi",
 561                 .clk_names = (const char *[]){ "dsi-pclk", "dsi-ref", },
 562                 .num_clks = 2,
 563                 .gpc_name = "mipi-dsi",
 564                 .rst_mask = BIT(5),
 565                 .clk_mask = BIT(8) | BIT(9),
 566                 .mipi_phy_rst_mask = BIT(17),
 567         },
 568         [IMX8MM_DISPBLK_PD_MIPI_CSI] = {
 569                 .name = "dispblk-mipi-csi",
 570                 .clk_names = (const char *[]){ "csi-aclk", "csi-pclk" },
 571                 .num_clks = 2,
 572                 .gpc_name = "mipi-csi",
 573                 .rst_mask = BIT(3) | BIT(4),
 574                 .clk_mask = BIT(10) | BIT(11),
 575                 .mipi_phy_rst_mask = BIT(16),
 576         },
 577 };
 578
 579 static const struct imx8m_blk_ctrl_data imx8mm_disp_blk_ctl_dev_data = {
 580         .max_reg = 0x2c,
 581         .power_notifier_fn = imx8mm_disp_power_notifier,
 582         .domains = imx8mm_disp_blk_ctl_domain_data,
 583         .num_domains = ARRAY_SIZE(imx8mm_disp_blk_ctl_domain_data),
 584 };
 585
 586
 587 static int imx8mn_disp_power_notifier(struct notifier_block *nb,
 588                                       unsigned long action, void *data)
 589 {
 590         struct imx8m_blk_ctrl *bc = container_of(nb, struct imx8m_blk_ctrl,
 591                                                  power_nb);
 592
 593         if (action != GENPD_NOTIFY_ON && action != GENPD_NOTIFY_PRE_OFF)
 594                 return NOTIFY_OK;
 595
 596         /* Enable bus clock and deassert bus reset */
 597         regmap_set_bits(bc->regmap, BLK_CLK_EN, BIT(8));
 598         regmap_set_bits(bc->regmap, BLK_SFT_RSTN, BIT(8));
 599
 600         /*
 601          * On power up we have no software backchannel to the GPC to
 602          * wait for the ADB handshake to happen, so we just delay for a
 603          * bit. On power down the GPC driver waits for the handshake.
 604          */
 605         if (action == GENPD_NOTIFY_ON)
 606                 udelay(5);
 607
 608
 609         return NOTIFY_OK;
 610 }
 611
 612 static const struct imx8m_blk_ctrl_domain_data imx8mn_disp_blk_ctl_domain_data[] = {
 613         [IMX8MN_DISPBLK_PD_MIPI_DSI] = {
 614                 .name = "dispblk-mipi-dsi",
 615                 .clk_names = (const char *[]){ "dsi-pclk", "dsi-ref", },
 616                 .num_clks = 2,
 617                 .gpc_name = "mipi-dsi",
 618                 .rst_mask = BIT(0) | BIT(1),
 619                 .clk_mask = BIT(0) | BIT(1),
 620                 .mipi_phy_rst_mask = BIT(17),
 621         },
 622         [IMX8MN_DISPBLK_PD_MIPI_CSI] = {
 623                 .name = "dispblk-mipi-csi",
 624                 .clk_names = (const char *[]){ "csi-aclk", "csi-pclk" },
 625                 .num_clks = 2,
 626                 .gpc_name = "mipi-csi",
 627                 .rst_mask = BIT(2) | BIT(3),
 628                 .clk_mask = BIT(2) | BIT(3),
 629                 .mipi_phy_rst_mask = BIT(16),
 630         },
 631         [IMX8MN_DISPBLK_PD_LCDIF] = {
 632                 .name = "dispblk-lcdif",
 633                 .clk_names = (const char *[]){ "lcdif-axi", "lcdif-apb", "lcdif-pix", },
 634                 .num_clks = 3,
 635                 .gpc_name = "lcdif",
 636                 .rst_mask = BIT(4) | BIT(5),
 637                 .clk_mask = BIT(4) | BIT(5),
 638         },
 639         [IMX8MN_DISPBLK_PD_ISI] = {
 640                 .name = "dispblk-isi",
 641                 .clk_names = (const char *[]){ "disp_axi", "disp_apb", "disp_axi_root",
 642                                                 "disp_apb_root"},
 643                 .num_clks = 4,
 644                 .gpc_name = "isi",
 645                 .rst_mask = BIT(6) | BIT(7),
 646                 .clk_mask = BIT(6) | BIT(7),
 647         },
 648 };
 649
 650 static const struct imx8m_blk_ctrl_data imx8mn_disp_blk_ctl_dev_data = {
 651         .max_reg = 0x84,
 652         .power_notifier_fn = imx8mn_disp_power_notifier,
 653         .domains = imx8mn_disp_blk_ctl_domain_data,
 654         .num_domains = ARRAY_SIZE(imx8mn_disp_blk_ctl_domain_data),
 655 };
 656
 657 static int imx8mp_media_power_notifier(struct notifier_block *nb,
 658                                 unsigned long action, void *data)
 659 {
 660         struct imx8m_blk_ctrl *bc = container_of(nb, struct imx8m_blk_ctrl,
 661                                                  power_nb);
 662
 663         if (action != GENPD_NOTIFY_ON && action != GENPD_NOTIFY_PRE_OFF)
 664                 return NOTIFY_OK;
 665
 666         /* Enable bus clock and deassert bus reset */
 667         regmap_set_bits(bc->regmap, BLK_CLK_EN, BIT(8));
 668         regmap_set_bits(bc->regmap, BLK_SFT_RSTN, BIT(8));
 669
 670         /*
 671          * On power up we have no software backchannel to the GPC to
 672          * wait for the ADB handshake to happen, so we just delay for a
 673          * bit. On power down the GPC driver waits for the handshake.
 674          */
 675         if (action == GENPD_NOTIFY_ON)
 676                 udelay(5);
 677
 678         return NOTIFY_OK;
 679 }
 680
 681 /*
 682  * From i.MX 8M Plus Applications Processor Reference Manual, Rev. 1,
 683  * section 13.2.2, 13.2.3
 684  * isp-ahb and dwe are not in Figure 13-5. Media BLK_CTRL Clocks
 685  */
 686 static const struct imx8m_blk_ctrl_domain_data imx8mp_media_blk_ctl_domain_data[] = {
 687         [IMX8MP_MEDIABLK_PD_MIPI_DSI_1] = {
 688                 .name = "mediablk-mipi-dsi-1",
 689                 .clk_names = (const char *[]){ "apb", "phy", },
 690                 .num_clks = 2,
 691                 .gpc_name = "mipi-dsi1",
 692                 .rst_mask = BIT(0) | BIT(1),
 693                 .clk_mask = BIT(0) | BIT(1),
 694                 .mipi_phy_rst_mask = BIT(17),
 695         },
 696         [IMX8MP_MEDIABLK_PD_MIPI_CSI2_1] = {
 697                 .name = "mediablk-mipi-csi2-1",
 698                 .clk_names = (const char *[]){ "apb", "cam1" },
 699                 .num_clks = 2,
 700                 .gpc_name = "mipi-csi1",
 701                 .rst_mask = BIT(2) | BIT(3),
 702                 .clk_mask = BIT(2) | BIT(3),
 703                 .mipi_phy_rst_mask = BIT(16),
 704         },
 705         [IMX8MP_MEDIABLK_PD_LCDIF_1] = {
 706                 .name = "mediablk-lcdif-1",
 707                 .clk_names = (const char *[]){ "disp1", "apb", "axi", },
 708                 .num_clks = 3,
 709                 .gpc_name = "lcdif1",
 710                 .rst_mask = BIT(4) | BIT(5) | BIT(23),
 711                 .clk_mask = BIT(4) | BIT(5) | BIT(23),
 712                 .path_names = (const char *[]){"lcdif-rd", "lcdif-wr"},
 713                 .num_paths = 2,
 714         },
 715         [IMX8MP_MEDIABLK_PD_ISI] = {
 716                 .name = "mediablk-isi",
 717                 .clk_names = (const char *[]){ "axi", "apb" },
 718                 .num_clks = 2,
 719                 .gpc_name = "isi",
 720                 .rst_mask = BIT(6) | BIT(7),
 721                 .clk_mask = BIT(6) | BIT(7),
 722                 .path_names = (const char *[]){"isi0", "isi1", "isi2"},
 723                 .num_paths = 3,
 724         },
 725         [IMX8MP_MEDIABLK_PD_MIPI_CSI2_2] = {
 726                 .name = "mediablk-mipi-csi2-2",
 727                 .clk_names = (const char *[]){ "apb", "cam2" },
 728                 .num_clks = 2,
 729                 .gpc_name = "mipi-csi2",
 730                 .rst_mask = BIT(9) | BIT(10),
 731                 .clk_mask = BIT(9) | BIT(10),
 732                 .mipi_phy_rst_mask = BIT(30),
 733         },
 734         [IMX8MP_MEDIABLK_PD_LCDIF_2] = {
 735                 .name = "mediablk-lcdif-2",
 736                 .clk_names = (const char *[]){ "disp2", "apb", "axi", },
 737                 .num_clks = 3,
 738                 .gpc_name = "lcdif2",
 739                 .rst_mask = BIT(11) | BIT(12) | BIT(24),
 740                 .clk_mask = BIT(11) | BIT(12) | BIT(24),
 741                 .path_names = (const char *[]){"lcdif-rd", "lcdif-wr"},
 742                 .num_paths = 2,
 743         },
 744         [IMX8MP_MEDIABLK_PD_ISP] = {
 745                 .name = "mediablk-isp",
 746                 .clk_names = (const char *[]){ "isp", "axi", "apb" },
 747                 .num_clks = 3,
 748                 .gpc_name = "isp",
 749                 .rst_mask = BIT(16) | BIT(17) | BIT(18),
 750                 .clk_mask = BIT(16) | BIT(17) | BIT(18),
 751                 .path_names = (const char *[]){"isp0", "isp1"},
 752                 .num_paths = 2,
 753         },
 754         [IMX8MP_MEDIABLK_PD_DWE] = {
 755                 .name = "mediablk-dwe",
 756                 .clk_names = (const char *[]){ "axi", "apb" },
 757                 .num_clks = 2,
 758                 .gpc_name = "dwe",
 759                 .rst_mask = BIT(19) | BIT(20) | BIT(21),
 760                 .clk_mask = BIT(19) | BIT(20) | BIT(21),
 761                 .path_names = (const char *[]){"dwe"},
 762                 .num_paths = 1,
 763         },
 764         [IMX8MP_MEDIABLK_PD_MIPI_DSI_2] = {
 765                 .name = "mediablk-mipi-dsi-2",
 766                 .clk_names = (const char *[]){ "phy", },
 767                 .num_clks = 1,
 768                 .gpc_name = "mipi-dsi2",
 769                 .rst_mask = BIT(22),
 770                 .clk_mask = BIT(22),
 771                 .mipi_phy_rst_mask = BIT(29),
 772         },
 773 };
 774
 775 static const struct imx8m_blk_ctrl_data imx8mp_media_blk_ctl_dev_data = {
 776         .max_reg = 0x138,
 777         .power_notifier_fn = imx8mp_media_power_notifier,
 778         .domains = imx8mp_media_blk_ctl_domain_data,
 779         .num_domains = ARRAY_SIZE(imx8mp_media_blk_ctl_domain_data),
 780 };
 781
 782 static int imx8mq_vpu_power_notifier(struct notifier_block *nb,
 783                                      unsigned long action, void *data)
 784 {
 785         struct imx8m_blk_ctrl *bc = container_of(nb, struct imx8m_blk_ctrl,
 786                                                  power_nb);
 787
 788         if (action != GENPD_NOTIFY_ON && action != GENPD_NOTIFY_PRE_OFF)
 789                 return NOTIFY_OK;
 790
 791         /*
 792          * The ADB in the VPUMIX domain has no separate reset and clock
 793          * enable bits, but is ungated and reset together with the VPUs. The
 794          * reset and clock enable inputs to the ADB is a logical OR of the
 795          * VPU bits. In order to set the G2 fuse bits, the G2 clock must
 796          * also be enabled.
 797          */
 798         regmap_set_bits(bc->regmap, BLK_SFT_RSTN, BIT(0) | BIT(1));
 799         regmap_set_bits(bc->regmap, BLK_CLK_EN, BIT(0) | BIT(1));
 800
 801         if (action == GENPD_NOTIFY_ON) {
 802                 /*
 803                  * On power up we have no software backchannel to the GPC to
 804                  * wait for the ADB handshake to happen, so we just delay for a
 805                  * bit. On power down the GPC driver waits for the handshake.
 806                  */
 807                 udelay(5);
 808
 809                 /* set "fuse" bits to enable the VPUs */
 810                 regmap_set_bits(bc->regmap, 0x8, 0xffffffff);
 811                 regmap_set_bits(bc->regmap, 0xc, 0xffffffff);
 812                 regmap_set_bits(bc->regmap, 0x10, 0xffffffff);
 813         }
 814
 815         return NOTIFY_OK;
 816 }
 817
 818 static const struct imx8m_blk_ctrl_domain_data imx8mq_vpu_blk_ctl_domain_data[] = {
 819         [IMX8MQ_VPUBLK_PD_G1] = {
 820                 .name = "vpublk-g1",
 821                 .clk_names = (const char *[]){ "g1", },
 822                 .num_clks = 1,
 823                 .gpc_name = "g1",
 824                 .rst_mask = BIT(1),
 825                 .clk_mask = BIT(1),
 826         },
 827         [IMX8MQ_VPUBLK_PD_G2] = {
 828                 .name = "vpublk-g2",
 829                 .clk_names = (const char *[]){ "g2", },
 830                 .num_clks = 1,
 831                 .gpc_name = "g2",
 832                 .rst_mask = BIT(0),
 833                 .clk_mask = BIT(0),
 834         },
 835 };
 836
 837 static const struct imx8m_blk_ctrl_data imx8mq_vpu_blk_ctl_dev_data = {
 838         .max_reg = 0x14,
 839         .power_notifier_fn = imx8mq_vpu_power_notifier,
 840         .domains = imx8mq_vpu_blk_ctl_domain_data,
 841         .num_domains = ARRAY_SIZE(imx8mq_vpu_blk_ctl_domain_data),
 842 };
 843
 844 static const struct of_device_id imx8m_blk_ctrl_of_match[] = {
 845         {
 846                 .compatible = "fsl,imx8mm-vpu-blk-ctrl",
 847                 .data = &imx8mm_vpu_blk_ctl_dev_data
 848         }, {
 849                 .compatible = "fsl,imx8mm-disp-blk-ctrl",
 850                 .data = &imx8mm_disp_blk_ctl_dev_data
 851         }, {
 852                 .compatible = "fsl,imx8mn-disp-blk-ctrl",
 853                 .data = &imx8mn_disp_blk_ctl_dev_data
 854         }, {
 855                 .compatible = "fsl,imx8mp-media-blk-ctrl",
 856                 .data = &imx8mp_media_blk_ctl_dev_data
 857         }, {
 858                 .compatible = "fsl,imx8mq-vpu-blk-ctrl",
 859                 .data = &imx8mq_vpu_blk_ctl_dev_data
 860         }, {
 861                 .compatible = "fsl,imx8mp-vpu-blk-ctrl",
 862                 .data = &imx8mp_vpu_blk_ctl_dev_data
 863         }, {
 864                 /* Sentinel */
 865         }
 866 };
 867 MODULE_DEVICE_TABLE(of, imx8m_blk_ctrl_of_match);
 868
 869 static struct platform_driver imx8m_blk_ctrl_driver = {
 870         .probe = imx8m_blk_ctrl_probe,
 871         .remove = imx8m_blk_ctrl_remove,
 872         .driver = {
 873                 .name = "imx8m-blk-ctrl",
 874                 .pm = &imx8m_blk_ctrl_pm_ops,
 875                 .of_match_table = imx8m_blk_ctrl_of_match,
 876         },
 877 };
 878 module_platform_driver(imx8m_blk_ctrl_driver);