drivers/clk/qcom/gcc-msm8939.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * Copyright 2020 Linaro Limited
   4  */
   5
   6 #include <linux/kernel.h>
   7 #include <linux/bitops.h>
   8 #include <linux/err.h>
   9 #include <linux/platform_device.h>
  10 #include <linux/module.h>
  11 #include <linux/of.h>
  12 #include <linux/of_device.h>
  13 #include <linux/clk-provider.h>
  14 #include <linux/regmap.h>
  15 #include <linux/reset-controller.h>
  16
  17 #include <dt-bindings/clock/qcom,gcc-msm8939.h>
  18 #include <dt-bindings/reset/qcom,gcc-msm8939.h>
  19
  20 #include "common.h"
  21 #include "clk-regmap.h"
  22 #include "clk-pll.h"
  23 #include "clk-rcg.h"
  24 #include "clk-branch.h"
  25 #include "reset.h"
  26 #include "gdsc.h"
  27
  28 enum {
  29         P_XO,
  30         P_GPLL0,
  31         P_GPLL0_AUX,
  32         P_BIMC,
  33         P_GPLL1,
  34         P_GPLL1_AUX,
  35         P_GPLL2,
  36         P_GPLL2_AUX,
  37         P_GPLL3,
  38         P_GPLL3_AUX,
  39         P_GPLL4,
  40         P_GPLL5,
  41         P_GPLL5_AUX,
  42         P_GPLL5_EARLY,
  43         P_GPLL6,
  44         P_GPLL6_AUX,
  45         P_SLEEP_CLK,
  46         P_DSI0_PHYPLL_BYTE,
  47         P_DSI0_PHYPLL_DSI,
  48         P_EXT_PRI_I2S,
  49         P_EXT_SEC_I2S,
  50         P_EXT_MCLK,
  51 };
  52
  53 static struct clk_pll gpll0 = {
  54         .l_reg = 0x21004,
  55         .m_reg = 0x21008,
  56         .n_reg = 0x2100c,
  57         .config_reg = 0x21010,
  58         .mode_reg = 0x21000,
  59         .status_reg = 0x2101c,
  60         .status_bit = 17,
  61         .clkr.hw.init = &(struct clk_init_data){
  62                 .name = "gpll0",
  63                 .parent_data = &(const struct clk_parent_data) {
  64                         .fw_name = "xo",
  65                 },
  66                 .num_parents = 1,
  67                 .ops = &clk_pll_ops,
  68         },
  69 };
  70
  71 static struct clk_regmap gpll0_vote = {
  72         .enable_reg = 0x45000,
  73         .enable_mask = BIT(0),
  74         .hw.init = &(struct clk_init_data){
  75                 .name = "gpll0_vote",
  76                 .parent_data = &(const struct clk_parent_data) {
  77                         .hw = &gpll0.clkr.hw,
  78                 },
  79                 .num_parents = 1,
  80                 .ops = &clk_pll_vote_ops,
  81         },
  82 };
  83
  84 static struct clk_pll gpll1 = {
  85         .l_reg = 0x20004,
  86         .m_reg = 0x20008,
  87         .n_reg = 0x2000c,
  88         .config_reg = 0x20010,
  89         .mode_reg = 0x20000,
  90         .status_reg = 0x2001c,
  91         .status_bit = 17,
  92         .clkr.hw.init = &(struct clk_init_data){
  93                 .name = "gpll1",
  94                 .parent_data = &(const struct clk_parent_data) {
  95                         .fw_name = "xo",
  96                 },
  97                 .num_parents = 1,
  98                 .ops = &clk_pll_ops,
  99         },
 100 };
 101
 102 static struct clk_regmap gpll1_vote = {
 103         .enable_reg = 0x45000,
 104         .enable_mask = BIT(1),
 105         .hw.init = &(struct clk_init_data){
 106                 .name = "gpll1_vote",
 107                 .parent_data = &(const struct clk_parent_data) {
 108                         .hw = &gpll1.clkr.hw,
 109                 },
 110                 .num_parents = 1,
 111                 .ops = &clk_pll_vote_ops,
 112         },
 113 };
 114
 115 static struct clk_pll gpll2 = {
 116         .l_reg = 0x4a004,
 117         .m_reg = 0x4a008,
 118         .n_reg = 0x4a00c,
 119         .config_reg = 0x4a010,
 120         .mode_reg = 0x4a000,
 121         .status_reg = 0x4a01c,
 122         .status_bit = 17,
 123         .clkr.hw.init = &(struct clk_init_data){
 124                 .name = "gpll2",
 125                 .parent_data = &(const struct clk_parent_data) {
 126                         .fw_name = "xo",
 127                 },
 128                 .num_parents = 1,
 129                 .ops = &clk_pll_ops,
 130         },
 131 };
 132
 133 static struct clk_regmap gpll2_vote = {
 134         .enable_reg = 0x45000,
 135         .enable_mask = BIT(2),
 136         .hw.init = &(struct clk_init_data){
 137                 .name = "gpll2_vote",
 138                 .parent_data = &(const struct clk_parent_data) {
 139                         .hw = &gpll2.clkr.hw,
 140                 },
 141                 .num_parents = 1,
 142                 .ops = &clk_pll_vote_ops,
 143         },
 144 };
 145
 146 static struct clk_pll bimc_pll = {
 147         .l_reg = 0x23004,
 148         .m_reg = 0x23008,
 149         .n_reg = 0x2300c,
 150         .config_reg = 0x23010,
 151         .mode_reg = 0x23000,
 152         .status_reg = 0x2301c,
 153         .status_bit = 17,
 154         .clkr.hw.init = &(struct clk_init_data){
 155                 .name = "bimc_pll",
 156                 .parent_data = &(const struct clk_parent_data) {
 157                         .fw_name = "xo",
 158                 },
 159                 .num_parents = 1,
 160                 .ops = &clk_pll_ops,
 161         },
 162 };
 163
 164 static struct clk_regmap bimc_pll_vote = {
 165         .enable_reg = 0x45000,
 166         .enable_mask = BIT(3),
 167         .hw.init = &(struct clk_init_data){
 168                 .name = "bimc_pll_vote",
 169                 .parent_data = &(const struct clk_parent_data) {
 170                         .hw = &bimc_pll.clkr.hw,
 171                 },
 172                 .num_parents = 1,
 173                 .ops = &clk_pll_vote_ops,
 174         },
 175 };
 176
 177 static struct clk_pll gpll3 = {
 178         .l_reg = 0x22004,
 179         .m_reg = 0x22008,
 180         .n_reg = 0x2200c,
 181         .config_reg = 0x22010,
 182         .mode_reg = 0x22000,
 183         .status_reg = 0x2201c,
 184         .status_bit = 17,
 185         .clkr.hw.init = &(struct clk_init_data){
 186                 .name = "gpll3",
 187                 .parent_data = &(const struct clk_parent_data) {
 188                         .fw_name = "xo",
 189                 },
 190                 .num_parents = 1,
 191                 .ops = &clk_pll_ops,
 192         },
 193 };
 194
 195 static struct clk_regmap gpll3_vote = {
 196         .enable_reg = 0x45000,
 197         .enable_mask = BIT(4),
 198         .hw.init = &(struct clk_init_data){
 199                 .name = "gpll3_vote",
 200                 .parent_data = &(const struct clk_parent_data) {
 201                         .hw = &gpll3.clkr.hw,
 202                 },
 203                 .num_parents = 1,
 204                 .ops = &clk_pll_vote_ops,
 205         },
 206 };
 207
 208 /* GPLL3 at 1100 MHz, main output enabled. */
 209 static const struct pll_config gpll3_config = {
 210         .l = 57,
 211         .m = 7,
 212         .n = 24,
 213         .vco_val = 0x0,
 214         .vco_mask = BIT(20),
 215         .pre_div_val = 0x0,
 216         .pre_div_mask = BIT(12),
 217         .post_div_val = 0x0,
 218         .post_div_mask = BIT(9) | BIT(8),
 219         .mn_ena_mask = BIT(24),
 220         .main_output_mask = BIT(0),
 221         .aux_output_mask = BIT(1),
 222 };
 223
 224 static struct clk_pll gpll4 = {
 225         .l_reg = 0x24004,
 226         .m_reg = 0x24008,
 227         .n_reg = 0x2400c,
 228         .config_reg = 0x24010,
 229         .mode_reg = 0x24000,
 230         .status_reg = 0x2401c,
 231         .status_bit = 17,
 232         .clkr.hw.init = &(struct clk_init_data){
 233                 .name = "gpll4",
 234                 .parent_data = &(const struct clk_parent_data) {
 235                         .fw_name = "xo",
 236                 },
 237                 .num_parents = 1,
 238                 .ops = &clk_pll_ops,
 239         },
 240 };
 241
 242 static struct clk_regmap gpll4_vote = {
 243         .enable_reg = 0x45000,
 244         .enable_mask = BIT(5),
 245         .hw.init = &(struct clk_init_data){
 246                 .name = "gpll4_vote",
 247                 .parent_data = &(const struct clk_parent_data) {
 248                         .hw = &gpll4.clkr.hw,
 249                 },
 250                 .num_parents = 1,
 251                 .ops = &clk_pll_vote_ops,
 252         },
 253 };
 254
 255 /* GPLL4 at 1200 MHz, main output enabled. */
 256 static struct pll_config gpll4_config = {
 257         .l = 62,
 258         .m = 1,
 259         .n = 2,
 260         .vco_val = 0x0,
 261         .vco_mask = BIT(20),
 262         .pre_div_val = 0x0,
 263         .pre_div_mask = BIT(12),
 264         .post_div_val = 0x0,
 265         .post_div_mask = BIT(9) | BIT(8),
 266         .mn_ena_mask = BIT(24),
 267         .main_output_mask = BIT(0),
 268 };
 269
 270 static struct clk_pll gpll5 = {
 271         .l_reg = 0x25004,
 272         .m_reg = 0x25008,
 273         .n_reg = 0x2500c,
 274         .config_reg = 0x25010,
 275         .mode_reg = 0x25000,
 276         .status_reg = 0x2501c,
 277         .status_bit = 17,
 278         .clkr.hw.init = &(struct clk_init_data){
 279                 .name = "gpll5",
 280                 .parent_data = &(const struct clk_parent_data) {
 281                         .fw_name = "xo",
 282                 },
 283                 .num_parents = 1,
 284                 .ops = &clk_pll_ops,
 285         },
 286 };
 287
 288 static struct clk_regmap gpll5_vote = {
 289         .enable_reg = 0x45000,
 290         .enable_mask = BIT(6),
 291         .hw.init = &(struct clk_init_data){
 292                 .name = "gpll5_vote",
 293                 .parent_data = &(const struct clk_parent_data) {
 294                         .hw = &gpll5.clkr.hw,
 295                 },
 296                 .num_parents = 1,
 297                 .ops = &clk_pll_vote_ops,
 298         },
 299 };
 300
 301 static struct clk_pll gpll6 = {
 302         .l_reg = 0x37004,
 303         .m_reg = 0x37008,
 304         .n_reg = 0x3700c,
 305         .config_reg = 0x37010,
 306         .mode_reg = 0x37000,
 307         .status_reg = 0x3701c,
 308         .status_bit = 17,
 309         .clkr.hw.init = &(struct clk_init_data){
 310                 .name = "gpll6",
 311                 .parent_data = &(const struct clk_parent_data) {
 312                         .fw_name = "xo",
 313                 },
 314                 .num_parents = 1,
 315                 .ops = &clk_pll_ops,
 316         },
 317 };
 318
 319 static struct clk_regmap gpll6_vote = {
 320         .enable_reg = 0x45000,
 321         .enable_mask = BIT(7),
 322         .hw.init = &(struct clk_init_data){
 323                 .name = "gpll6_vote",
 324                 .parent_data = &(const struct clk_parent_data) {
 325                         .hw = &gpll6.clkr.hw,
 326                 },
 327                 .num_parents = 1,
 328                 .ops = &clk_pll_vote_ops,
 329         },
 330 };
 331
 332 static const struct parent_map gcc_xo_gpll0_map[] = {
 333         { P_XO, 0 },
 334         { P_GPLL0, 1 },
 335 };
 336
 337 static const struct clk_parent_data gcc_xo_gpll0_parent_data[] = {
 338         { .fw_name = "xo" },
 339         { .hw = &gpll0_vote.hw },
 340 };
 341
 342 static const struct parent_map gcc_xo_gpll0_bimc_map[] = {
 343         { P_XO, 0 },
 344         { P_GPLL0, 1 },
 345         { P_BIMC, 2 },
 346 };
 347
 348 static const struct clk_parent_data gcc_xo_gpll0_bimc_parent_data[] = {
 349         { .fw_name = "xo" },
 350         { .hw = &gpll0_vote.hw },
 351         { .hw = &bimc_pll_vote.hw },
 352 };
 353
 354 static const struct parent_map gcc_xo_gpll0_gpll6a_map[] = {
 355         { P_XO, 0 },
 356         { P_GPLL0, 1 },
 357         { P_GPLL6_AUX, 2 },
 358 };
 359
 360 static const struct clk_parent_data gcc_xo_gpll0_gpll6a_parent_data[] = {
 361         { .fw_name = "xo" },
 362         { .hw = &gpll0_vote.hw },
 363         { .hw = &gpll6_vote.hw },
 364 };
 365
 366 static const struct parent_map gcc_xo_gpll0_gpll2a_gpll3_gpll6a_map[] = {
 367         { P_XO, 0 },
 368         { P_GPLL0, 1 },
 369         { P_GPLL2_AUX, 4 },
 370         { P_GPLL3, 2 },
 371         { P_GPLL6_AUX, 3 },
 372 };
 373
 374 static const struct clk_parent_data gcc_xo_gpll0_gpll2a_gpll3_gpll6a_parent_data[] = {
 375         { .fw_name = "xo" },
 376         { .hw = &gpll0_vote.hw },
 377         { .hw = &gpll2_vote.hw },
 378         { .hw = &gpll3_vote.hw },
 379         { .hw = &gpll6_vote.hw },
 380 };
 381
 382 static const struct parent_map gcc_xo_gpll0_gpll2_map[] = {
 383         { P_XO, 0 },
 384         { P_GPLL0, 1 },
 385         { P_GPLL2, 2 },
 386 };
 387
 388 static const struct clk_parent_data gcc_xo_gpll0_gpll2_parent_data[] = {
 389         { .fw_name = "xo" },
 390         { .hw = &gpll0_vote.hw },
 391         { .hw = &gpll2_vote.hw },
 392 };
 393
 394 static const struct parent_map gcc_xo_gpll0_gpll2_gpll4_map[] = {
 395         { P_XO, 0 },
 396         { P_GPLL0, 1 },
 397         { P_GPLL2, 3 },
 398         { P_GPLL4, 2 },
 399 };
 400
 401 static const struct clk_parent_data gcc_xo_gpll0_gpll2_gpll4_parent_data[] = {
 402         { .fw_name = "xo" },
 403         { .hw = &gpll0_vote.hw },
 404         { .hw = &gpll2_vote.hw },
 405         { .hw = &gpll4_vote.hw },
 406 };
 407
 408 static const struct parent_map gcc_xo_gpll0a_map[] = {
 409         { P_XO, 0 },
 410         { P_GPLL0_AUX, 2 },
 411 };
 412
 413 static const struct clk_parent_data gcc_xo_gpll0a_parent_data[] = {
 414         { .fw_name = "xo" },
 415         { .hw = &gpll0_vote.hw },
 416 };
 417
 418 static const struct parent_map gcc_xo_gpll0_gpll1a_sleep_map[] = {
 419         { P_XO, 0 },
 420         { P_GPLL0, 1 },
 421         { P_GPLL1_AUX, 2 },
 422         { P_SLEEP_CLK, 6 },
 423 };
 424
 425 static const struct clk_parent_data gcc_xo_gpll0_gpll1a_sleep_parent_data[] = {
 426         { .fw_name = "xo" },
 427         { .hw = &gpll0_vote.hw },
 428         { .hw = &gpll1_vote.hw },
 429         { .fw_name = "sleep_clk", .name = "sleep_clk" },
 430 };
 431
 432 static const struct parent_map gcc_xo_gpll0_gpll1a_gpll6_sleep_map[] = {
 433         { P_XO, 0 },
 434         { P_GPLL0, 1 },
 435         { P_GPLL1_AUX, 2 },
 436         { P_GPLL6, 2 },
 437         { P_SLEEP_CLK, 6 },
 438 };
 439
 440 static const struct clk_parent_data gcc_xo_gpll0_gpll1a_gpll6_sleep_parent_data[] = {
 441         { .fw_name = "xo" },
 442         { .hw = &gpll0_vote.hw },
 443         { .hw = &gpll1_vote.hw },
 444         { .hw = &gpll6_vote.hw },
 445         { .fw_name = "sleep_clk", .name = "sleep_clk" },
 446 };
 447
 448 static const struct parent_map gcc_xo_gpll0_gpll1a_map[] = {
 449         { P_XO, 0 },
 450         { P_GPLL0, 1 },
 451         { P_GPLL1_AUX, 2 },
 452 };
 453
 454 static const struct clk_parent_data gcc_xo_gpll0_gpll1a_parent_data[] = {
 455         { .fw_name = "xo" },
 456         { .hw = &gpll0_vote.hw },
 457         { .hw = &gpll1_vote.hw },
 458 };
 459
 460 static const struct parent_map gcc_xo_dsibyte_map[] = {
 461         { P_XO, 0, },
 462         { P_DSI0_PHYPLL_BYTE, 2 },
 463 };
 464
 465 static const struct clk_parent_data gcc_xo_dsibyte_parent_data[] = {
 466         { .fw_name = "xo" },
 467         { .fw_name = "dsi0pllbyte", .name = "dsi0pllbyte" },
 468 };
 469
 470 static const struct parent_map gcc_xo_gpll0a_dsibyte_map[] = {
 471         { P_XO, 0 },
 472         { P_GPLL0_AUX, 2 },
 473         { P_DSI0_PHYPLL_BYTE, 1 },
 474 };
 475
 476 static const struct clk_parent_data gcc_xo_gpll0a_dsibyte_parent_data[] = {
 477         { .fw_name = "xo" },
 478         { .hw = &gpll0_vote.hw },
 479         { .fw_name = "dsi0pllbyte", .name = "dsi0pllbyte" },
 480 };
 481
 482 static const struct parent_map gcc_xo_gpll1_dsiphy_gpll6_gpll3a_gpll0a_map[] = {
 483         { P_XO, 0 },
 484         { P_GPLL1, 1 },
 485         { P_DSI0_PHYPLL_DSI, 2 },
 486         { P_GPLL6, 3 },
 487         { P_GPLL3_AUX, 4 },
 488         { P_GPLL0_AUX, 5 },
 489 };
 490
 491 static const struct clk_parent_data gcc_xo_gpll1_dsiphy_gpll6_gpll3a_gpll0a_parent_data[] = {
 492         { .fw_name = "xo" },
 493         { .hw = &gpll1_vote.hw },
 494         { .fw_name = "dsi0pll", .name = "dsi0pll" },
 495         { .hw = &gpll6_vote.hw },
 496         { .hw = &gpll3_vote.hw },
 497         { .hw = &gpll0_vote.hw },
 498 };
 499
 500 static const struct parent_map gcc_xo_gpll0a_dsiphy_map[] = {
 501         { P_XO, 0 },
 502         { P_GPLL0_AUX, 2 },
 503         { P_DSI0_PHYPLL_DSI, 1 },
 504 };
 505
 506 static const struct clk_parent_data gcc_xo_gpll0a_dsiphy_parent_data[] = {
 507         { .fw_name = "xo" },
 508         { .hw = &gpll0_vote.hw },
 509         { .fw_name = "dsi0pll", .name = "dsi0pll" },
 510 };
 511
 512 static const struct parent_map gcc_xo_gpll0_gpll5a_gpll6_bimc_map[] = {
 513         { P_XO, 0 },
 514         { P_GPLL0, 1 },
 515         { P_GPLL5_AUX, 3 },
 516         { P_GPLL6, 2 },
 517         { P_BIMC, 4 },
 518 };
 519
 520 static const struct clk_parent_data gcc_xo_gpll0_gpll5a_gpll6_bimc_parent_data[] = {
 521         { .fw_name = "xo" },
 522         { .hw = &gpll0_vote.hw },
 523         { .hw = &gpll5_vote.hw },
 524         { .hw = &gpll6_vote.hw },
 525         { .hw = &bimc_pll_vote.hw },
 526 };
 527
 528 static const struct parent_map gcc_xo_gpll0_gpll1_sleep_map[] = {
 529         { P_XO, 0 },
 530         { P_GPLL0, 1 },
 531         { P_GPLL1, 2 },
 532         { P_SLEEP_CLK, 6 }
 533 };
 534
 535 static const struct clk_parent_data gcc_xo_gpll0_gpll1_sleep_parent_data[] = {
 536         { .fw_name = "xo" },
 537         { .hw = &gpll0_vote.hw },
 538         { .hw = &gpll1_vote.hw },
 539         { .fw_name = "sleep_clk", .name = "sleep_clk" },
 540 };
 541
 542 static const struct parent_map gcc_xo_gpll1_epi2s_emclk_sleep_map[] = {
 543         { P_XO, 0 },
 544         { P_GPLL1, 1 },
 545         { P_EXT_PRI_I2S, 2 },
 546         { P_EXT_MCLK, 3 },
 547         { P_SLEEP_CLK, 6 }
 548 };
 549
 550 static const struct clk_parent_data gcc_xo_gpll1_epi2s_emclk_sleep_parent_data[] = {
 551         { .fw_name = "xo" },
 552         { .hw = &gpll0_vote.hw },
 553         { .fw_name = "ext_pri_i2s", .name = "ext_pri_i2s" },
 554         { .fw_name = "ext_mclk", .name = "ext_mclk" },
 555         { .fw_name = "sleep_clk", .name = "sleep_clk" },
 556 };
 557
 558 static const struct parent_map gcc_xo_gpll1_esi2s_emclk_sleep_map[] = {
 559         { P_XO, 0 },
 560         { P_GPLL1, 1 },
 561         { P_EXT_SEC_I2S, 2 },
 562         { P_EXT_MCLK, 3 },
 563         { P_SLEEP_CLK, 6 }
 564 };
 565
 566 static const struct clk_parent_data gcc_xo_gpll1_esi2s_emclk_sleep_parent_data[] = {
 567         { .fw_name = "xo" },
 568         { .hw = &gpll1_vote.hw },
 569         { .fw_name = "ext_sec_i2s", .name = "ext_sec_i2s" },
 570         { .fw_name = "ext_mclk", .name = "ext_mclk" },
 571         { .fw_name = "sleep_clk", .name = "sleep_clk" },
 572 };
 573
 574 static const struct parent_map gcc_xo_sleep_map[] = {
 575         { P_XO, 0 },
 576         { P_SLEEP_CLK, 6 }
 577 };
 578
 579 static const struct clk_parent_data gcc_xo_sleep_parent_data[] = {
 580         { .fw_name = "xo" },
 581         { .fw_name = "sleep_clk", .name = "sleep_clk" },
 582 };
 583
 584 static const struct parent_map gcc_xo_gpll1_emclk_sleep_map[] = {
 585         { P_XO, 0 },
 586         { P_GPLL1, 1 },
 587         { P_EXT_MCLK, 2 },
 588         { P_SLEEP_CLK, 6 }
 589 };
 590
 591 static const struct clk_parent_data gcc_xo_gpll1_emclk_sleep_parent_data[] = {
 592         { .fw_name = "xo" },
 593         { .hw = &gpll1_vote.hw },
 594         { .fw_name = "ext_mclk", .name = "ext_mclk" },
 595         { .fw_name = "sleep_clk", .name = "sleep_clk" },
 596 };
 597
 598 static const struct clk_parent_data gcc_xo_gpll6_gpll0_parent_data[] = {
 599         { .fw_name = "xo" },
 600         { .hw = &gpll6_vote.hw },
 601         { .hw = &gpll0_vote.hw },
 602 };
 603
 604 static const struct clk_parent_data gcc_xo_gpll6_gpll0a_parent_data[] = {
 605         { .fw_name = "xo" },
 606         { .hw = &gpll6_vote.hw },
 607         { .hw = &gpll0_vote.hw },
 608 };
 609
 610 static struct clk_rcg2 pcnoc_bfdcd_clk_src = {
 611         .cmd_rcgr = 0x27000,
 612         .hid_width = 5,
 613         .parent_map = gcc_xo_gpll0_map,
 614         .clkr.hw.init = &(struct clk_init_data){
 615                 .name = "pcnoc_bfdcd_clk_src",
 616                 .parent_data = gcc_xo_gpll0_parent_data,
 617                 .num_parents = ARRAY_SIZE(gcc_xo_gpll0_parent_data),
 618                 .ops = &clk_rcg2_ops,
 619         },
 620 };
 621
 622 static struct clk_rcg2 system_noc_bfdcd_clk_src = {
 623         .cmd_rcgr = 0x26004,
 624         .hid_width = 5,
 625         .parent_map = gcc_xo_gpll0_gpll6a_map,
 626         .clkr.hw.init = &(struct clk_init_data){
 627                 .name = "system_noc_bfdcd_clk_src",
 628                 .parent_data = gcc_xo_gpll0_gpll6a_parent_data,
 629                 .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll6a_parent_data),
 630                 .ops = &clk_rcg2_ops,
 631         },
 632 };
 633
 634 static struct clk_rcg2 bimc_ddr_clk_src = {
 635         .cmd_rcgr = 0x32024,
 636         .hid_width = 5,
 637         .parent_map = gcc_xo_gpll0_bimc_map,
 638         .clkr.hw.init = &(struct clk_init_data){
 639                 .name = "bimc_ddr_clk_src",
 640                 .parent_data = gcc_xo_gpll0_bimc_parent_data,
 641                 .num_parents = ARRAY_SIZE(gcc_xo_gpll0_bimc_parent_data),
 642                 .ops = &clk_rcg2_ops,
 643                 .flags = CLK_GET_RATE_NOCACHE,
 644         },
 645 };
 646
 647 static struct clk_rcg2 system_mm_noc_bfdcd_clk_src = {
 648         .cmd_rcgr = 0x2600c,
 649         .hid_width = 5,
 650         .parent_map = gcc_xo_gpll0_gpll6a_map,
 651         .clkr.hw.init = &(struct clk_init_data){
 652                 .name = "system_mm_noc_bfdcd_clk_src",
 653                 .parent_data = gcc_xo_gpll0_gpll6a_parent_data,
 654                 .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll6a_parent_data),
 655                 .ops = &clk_rcg2_ops,
 656         },
 657 };
 658
 659 static const struct freq_tbl ftbl_gcc_camss_ahb_clk[] = {
 660         F(40000000, P_GPLL0, 10, 1, 2),
 661         F(80000000, P_GPLL0, 10, 0, 0),
 662         { }
 663 };
 664
 665 static struct clk_rcg2 camss_ahb_clk_src = {
 666         .cmd_rcgr = 0x5a000,
 667         .mnd_width = 8,
 668         .hid_width = 5,
 669         .parent_map = gcc_xo_gpll0_map,
 670         .freq_tbl = ftbl_gcc_camss_ahb_clk,
 671         .clkr.hw.init = &(struct clk_init_data){
 672                 .name = "camss_ahb_clk_src",
 673                 .parent_data = gcc_xo_gpll0_parent_data,
 674                 .num_parents = ARRAY_SIZE(gcc_xo_gpll0_parent_data),
 675                 .ops = &clk_rcg2_ops,
 676         },
 677 };
 678
 679 static const struct freq_tbl ftbl_apss_ahb_clk[] = {
 680         F(19200000, P_XO, 1, 0, 0),
 681         F(50000000, P_GPLL0, 16, 0, 0),
 682         F(100000000, P_GPLL0, 8, 0, 0),
 683         F(133330000, P_GPLL0, 6, 0, 0),
 684         { }
 685 };
 686
 687 static struct clk_rcg2 apss_ahb_clk_src = {
 688         .cmd_rcgr = 0x46000,
 689         .hid_width = 5,
 690         .parent_map = gcc_xo_gpll0_map,
 691         .freq_tbl = ftbl_apss_ahb_clk,
 692         .clkr.hw.init = &(struct clk_init_data){
 693                 .name = "apss_ahb_clk_src",
 694                 .parent_data = gcc_xo_gpll0_parent_data,
 695                 .num_parents = ARRAY_SIZE(gcc_xo_gpll0_parent_data),
 696                 .ops = &clk_rcg2_ops,
 697         },
 698 };
 699
 700 static const struct freq_tbl ftbl_gcc_camss_csi0_1_clk[] = {
 701         F(100000000, P_GPLL0, 8, 0,     0),
 702         F(200000000, P_GPLL0, 4, 0,     0),
 703         { }
 704 };
 705
 706 static struct clk_rcg2 csi0_clk_src = {
 707         .cmd_rcgr = 0x4e020,
 708         .hid_width = 5,
 709         .parent_map = gcc_xo_gpll0_map,
 710         .freq_tbl = ftbl_gcc_camss_csi0_1_clk,
 711         .clkr.hw.init = &(struct clk_init_data){
 712                 .name = "csi0_clk_src",
 713                 .parent_data = gcc_xo_gpll0_parent_data,
 714                 .num_parents = ARRAY_SIZE(gcc_xo_gpll0_parent_data),
 715                 .ops = &clk_rcg2_ops,
 716         },
 717 };
 718
 719 static struct clk_rcg2 csi1_clk_src = {
 720         .cmd_rcgr = 0x4f020,
 721         .hid_width = 5,
 722         .parent_map = gcc_xo_gpll0_map,
 723         .freq_tbl = ftbl_gcc_camss_csi0_1_clk,
 724         .clkr.hw.init = &(struct clk_init_data){
 725                 .name = "csi1_clk_src",
 726                 .parent_data = gcc_xo_gpll0_parent_data,
 727                 .num_parents = ARRAY_SIZE(gcc_xo_gpll0_parent_data),
 728                 .ops = &clk_rcg2_ops,
 729         },
 730 };
 731
 732 static const struct freq_tbl ftbl_gcc_oxili_gfx3d_clk[] = {
 733         F(19200000, P_XO, 1, 0, 0),
 734         F(50000000, P_GPLL0, 16, 0, 0),
 735         F(80000000, P_GPLL0, 10, 0, 0),
 736         F(100000000, P_GPLL0, 8, 0, 0),
 737         F(160000000, P_GPLL0, 5, 0, 0),
 738         F(200000000, P_GPLL0, 4, 0, 0),
 739         F(220000000, P_GPLL3, 5, 0, 0),
 740         F(266670000, P_GPLL0, 3, 0, 0),
 741         F(310000000, P_GPLL2_AUX, 3, 0, 0),
 742         F(400000000, P_GPLL0, 2, 0, 0),
 743         F(465000000, P_GPLL2_AUX, 2, 0, 0),
 744         F(550000000, P_GPLL3, 2, 0, 0),
 745         { }
 746 };
 747
 748 static struct clk_rcg2 gfx3d_clk_src = {
 749         .cmd_rcgr = 0x59000,
 750         .hid_width = 5,
 751         .parent_map = gcc_xo_gpll0_gpll2a_gpll3_gpll6a_map,
 752         .freq_tbl = ftbl_gcc_oxili_gfx3d_clk,
 753         .clkr.hw.init = &(struct clk_init_data){
 754                 .name = "gfx3d_clk_src",
 755                 .parent_data = gcc_xo_gpll0_gpll2a_gpll3_gpll6a_parent_data,
 756                 .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll2a_gpll3_gpll6a_parent_data),
 757                 .ops = &clk_rcg2_ops,
 758         },
 759 };
 760
 761 static const struct freq_tbl ftbl_gcc_camss_vfe0_clk[] = {
 762         F(50000000, P_GPLL0, 16, 0, 0),
 763         F(80000000, P_GPLL0, 10, 0, 0),
 764         F(100000000, P_GPLL0, 8, 0, 0),
 765         F(160000000, P_GPLL0, 5, 0, 0),
 766         F(177780000, P_GPLL0, 4.5, 0, 0),
 767         F(200000000, P_GPLL0, 4, 0, 0),
 768         F(266670000, P_GPLL0, 3, 0, 0),
 769         F(320000000, P_GPLL0, 2.5, 0, 0),
 770         F(400000000, P_GPLL0, 2, 0, 0),
 771         F(465000000, P_GPLL2, 2, 0, 0),
 772         F(480000000, P_GPLL4, 2.5, 0, 0),
 773         F(600000000, P_GPLL4, 2, 0, 0),
 774         { }
 775 };
 776
 777 static struct clk_rcg2 vfe0_clk_src = {
 778         .cmd_rcgr = 0x58000,
 779         .hid_width = 5,
 780         .parent_map = gcc_xo_gpll0_gpll2_gpll4_map,
 781         .freq_tbl = ftbl_gcc_camss_vfe0_clk,
 782         .clkr.hw.init = &(struct clk_init_data){
 783                 .name = "vfe0_clk_src",
 784                 .parent_data = gcc_xo_gpll0_gpll2_gpll4_parent_data,
 785                 .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll2_gpll4_parent_data),
 786                 .ops = &clk_rcg2_ops,
 787         },
 788 };
 789
 790 static const struct freq_tbl ftbl_gcc_blsp1_qup1_6_i2c_apps_clk[] = {
 791         F(19200000, P_XO, 1, 0, 0),
 792         F(50000000, P_GPLL0, 16, 0, 0),
 793         { }
 794 };
 795
 796 static struct clk_rcg2 blsp1_qup1_i2c_apps_clk_src = {
 797         .cmd_rcgr = 0x0200c,
 798         .hid_width = 5,
 799         .parent_map = gcc_xo_gpll0_map,
 800         .freq_tbl = ftbl_gcc_blsp1_qup1_6_i2c_apps_clk,
 801         .clkr.hw.init = &(struct clk_init_data){
 802                 .name = "blsp1_qup1_i2c_apps_clk_src",
 803                 .parent_data = gcc_xo_gpll0_parent_data,
 804                 .num_parents = ARRAY_SIZE(gcc_xo_gpll0_parent_data),
 805                 .ops = &clk_rcg2_ops,
 806         },
 807 };
 808
 809 static const struct freq_tbl ftbl_gcc_blsp1_qup1_6_spi_apps_clk[] = {
 810         F(960000, P_XO, 10, 1, 2),
 811         F(4800000, P_XO, 4, 0, 0),
 812         F(9600000, P_XO, 2, 0, 0),
 813         F(16000000, P_GPLL0, 10, 1, 5),
 814         F(19200000, P_XO, 1, 0, 0),
 815         F(25000000, P_GPLL0, 16, 1, 2),
 816         F(50000000, P_GPLL0, 16, 0, 0),
 817         { }
 818 };
 819
 820 static struct clk_rcg2 blsp1_qup1_spi_apps_clk_src = {
 821         .cmd_rcgr = 0x02024,
 822         .mnd_width = 8,
 823         .hid_width = 5,
 824         .parent_map = gcc_xo_gpll0_map,
 825         .freq_tbl = ftbl_gcc_blsp1_qup1_6_spi_apps_clk,
 826         .clkr.hw.init = &(struct clk_init_data){
 827                 .name = "blsp1_qup1_spi_apps_clk_src",
 828                 .parent_data = gcc_xo_gpll0_parent_data,
 829                 .num_parents = ARRAY_SIZE(gcc_xo_gpll0_parent_data),
 830                 .ops = &clk_rcg2_ops,
 831         },
 832 };
 833
 834 static struct clk_rcg2 blsp1_qup2_i2c_apps_clk_src = {
 835         .cmd_rcgr = 0x03000,
 836         .hid_width = 5,
 837         .parent_map = gcc_xo_gpll0_map,
 838         .freq_tbl = ftbl_gcc_blsp1_qup1_6_i2c_apps_clk,
 839         .clkr.hw.init = &(struct clk_init_data){
 840                 .name = "blsp1_qup2_i2c_apps_clk_src",
 841                 .parent_data = gcc_xo_gpll0_parent_data,
 842                 .num_parents = ARRAY_SIZE(gcc_xo_gpll0_parent_data),
 843                 .ops = &clk_rcg2_ops,
 844         },
 845 };
 846
 847 static struct clk_rcg2 blsp1_qup2_spi_apps_clk_src = {
 848         .cmd_rcgr = 0x03014,
 849         .mnd_width = 8,
 850         .hid_width = 5,
 851         .parent_map = gcc_xo_gpll0_map,
 852         .freq_tbl = ftbl_gcc_blsp1_qup1_6_spi_apps_clk,
 853         .clkr.hw.init = &(struct clk_init_data){
 854                 .name = "blsp1_qup2_spi_apps_clk_src",
 855                 .parent_data = gcc_xo_gpll0_parent_data,
 856                 .num_parents = ARRAY_SIZE(gcc_xo_gpll0_parent_data),
 857                 .ops = &clk_rcg2_ops,
 858         },
 859 };
 860
 861 static struct clk_rcg2 blsp1_qup3_i2c_apps_clk_src = {
 862         .cmd_rcgr = 0x04000,
 863         .hid_width = 5,
 864         .parent_map = gcc_xo_gpll0_map,
 865         .freq_tbl = ftbl_gcc_blsp1_qup1_6_i2c_apps_clk,
 866         .clkr.hw.init = &(struct clk_init_data){
 867                 .name = "blsp1_qup3_i2c_apps_clk_src",
 868                 .parent_data = gcc_xo_gpll0_parent_data,
 869                 .num_parents = ARRAY_SIZE(gcc_xo_gpll0_parent_data),
 870                 .ops = &clk_rcg2_ops,
 871         },
 872 };
 873
 874 static struct clk_rcg2 blsp1_qup3_spi_apps_clk_src = {
 875         .cmd_rcgr = 0x04024,
 876         .mnd_width = 8,
 877         .hid_width = 5,
 878         .parent_map = gcc_xo_gpll0_map,
 879         .freq_tbl = ftbl_gcc_blsp1_qup1_6_spi_apps_clk,
 880         .clkr.hw.init = &(struct clk_init_data){
 881                 .name = "blsp1_qup3_spi_apps_clk_src",
 882                 .parent_data = gcc_xo_gpll0_parent_data,
 883                 .num_parents = ARRAY_SIZE(gcc_xo_gpll0_parent_data),
 884                 .ops = &clk_rcg2_ops,
 885         },
 886 };
 887
 888 static struct clk_rcg2 blsp1_qup4_i2c_apps_clk_src = {
 889         .cmd_rcgr = 0x05000,
 890         .hid_width = 5,
 891         .parent_map = gcc_xo_gpll0_map,
 892         .freq_tbl = ftbl_gcc_blsp1_qup1_6_i2c_apps_clk,
 893         .clkr.hw.init = &(struct clk_init_data){
 894                 .name = "blsp1_qup4_i2c_apps_clk_src",
 895                 .parent_data = gcc_xo_gpll0_parent_data,
 896                 .num_parents = ARRAY_SIZE(gcc_xo_gpll0_parent_data),
 897                 .ops = &clk_rcg2_ops,
 898         },
 899 };
 900
 901 static struct clk_rcg2 blsp1_qup4_spi_apps_clk_src = {
 902         .cmd_rcgr = 0x05024,
 903         .mnd_width = 8,
 904         .hid_width = 5,
 905         .parent_map = gcc_xo_gpll0_map,
 906         .freq_tbl = ftbl_gcc_blsp1_qup1_6_spi_apps_clk,
 907         .clkr.hw.init = &(struct clk_init_data){
 908                 .name = "blsp1_qup4_spi_apps_clk_src",
 909                 .parent_data = gcc_xo_gpll0_parent_data,
 910                 .num_parents = ARRAY_SIZE(gcc_xo_gpll0_parent_data),
 911                 .ops = &clk_rcg2_ops,
 912         },
 913 };
 914
 915 static struct clk_rcg2 blsp1_qup5_i2c_apps_clk_src = {
 916         .cmd_rcgr = 0x06000,
 917         .hid_width = 5,
 918         .parent_map = gcc_xo_gpll0_map,
 919         .freq_tbl = ftbl_gcc_blsp1_qup1_6_i2c_apps_clk,
 920         .clkr.hw.init = &(struct clk_init_data){
 921                 .name = "blsp1_qup5_i2c_apps_clk_src",
 922                 .parent_data = gcc_xo_gpll0_parent_data,
 923                 .num_parents = ARRAY_SIZE(gcc_xo_gpll0_parent_data),
 924                 .ops = &clk_rcg2_ops,
 925         },
 926 };
 927
 928 static struct clk_rcg2 blsp1_qup5_spi_apps_clk_src = {
 929         .cmd_rcgr = 0x06024,
 930         .mnd_width = 8,
 931         .hid_width = 5,
 932         .parent_map = gcc_xo_gpll0_map,
 933         .freq_tbl = ftbl_gcc_blsp1_qup1_6_spi_apps_clk,
 934         .clkr.hw.init = &(struct clk_init_data){
 935                 .name = "blsp1_qup5_spi_apps_clk_src",
 936                 .parent_data = gcc_xo_gpll0_parent_data,
 937                 .num_parents = ARRAY_SIZE(gcc_xo_gpll0_parent_data),
 938                 .ops = &clk_rcg2_ops,
 939         },
 940 };
 941
 942 static struct clk_rcg2 blsp1_qup6_i2c_apps_clk_src = {
 943         .cmd_rcgr = 0x07000,
 944         .hid_width = 5,
 945         .parent_map = gcc_xo_gpll0_map,
 946         .freq_tbl = ftbl_gcc_blsp1_qup1_6_i2c_apps_clk,
 947         .clkr.hw.init = &(struct clk_init_data){
 948                 .name = "blsp1_qup6_i2c_apps_clk_src",
 949                 .parent_data = gcc_xo_gpll0_parent_data,
 950                 .num_parents = ARRAY_SIZE(gcc_xo_gpll0_parent_data),
 951                 .ops = &clk_rcg2_ops,
 952         },
 953 };
 954
 955 static struct clk_rcg2 blsp1_qup6_spi_apps_clk_src = {
 956         .cmd_rcgr = 0x07024,
 957         .mnd_width = 8,
 958         .hid_width = 5,
 959         .parent_map = gcc_xo_gpll0_map,
 960         .freq_tbl = ftbl_gcc_blsp1_qup1_6_spi_apps_clk,
 961         .clkr.hw.init = &(struct clk_init_data){
 962                 .name = "blsp1_qup6_spi_apps_clk_src",
 963                 .parent_data = gcc_xo_gpll0_parent_data,
 964                 .num_parents = ARRAY_SIZE(gcc_xo_gpll0_parent_data),
 965                 .ops = &clk_rcg2_ops,
 966         },
 967 };
 968
 969 static const struct freq_tbl ftbl_gcc_blsp1_uart1_6_apps_clk[] = {
 970         F(3686400, P_GPLL0, 1, 72, 15625),
 971         F(7372800, P_GPLL0, 1, 144, 15625),
 972         F(14745600, P_GPLL0, 1, 288, 15625),
 973         F(16000000, P_GPLL0, 10, 1, 5),
 974         F(19200000, P_XO, 1, 0, 0),
 975         F(24000000, P_GPLL0, 1, 3, 100),
 976         F(25000000, P_GPLL0, 16, 1, 2),
 977         F(32000000, P_GPLL0, 1, 1, 25),
 978         F(40000000, P_GPLL0, 1, 1, 20),
 979         F(46400000, P_GPLL0, 1, 29, 500),
 980         F(48000000, P_GPLL0, 1, 3, 50),
 981         F(51200000, P_GPLL0, 1, 8, 125),
 982         F(56000000, P_GPLL0, 1, 7, 100),
 983         F(58982400, P_GPLL0, 1, 1152, 15625),
 984         F(60000000, P_GPLL0, 1, 3, 40),
 985         { }
 986 };
 987
 988 static struct clk_rcg2 blsp1_uart1_apps_clk_src = {
 989         .cmd_rcgr = 0x02044,
 990         .mnd_width = 16,
 991         .hid_width = 5,
 992         .parent_map = gcc_xo_gpll0_map,
 993         .freq_tbl = ftbl_gcc_blsp1_uart1_6_apps_clk,
 994         .clkr.hw.init = &(struct clk_init_data){
 995                 .name = "blsp1_uart1_apps_clk_src",
 996                 .parent_data = gcc_xo_gpll0_parent_data,
 997                 .num_parents = ARRAY_SIZE(gcc_xo_gpll0_parent_data),
 998                 .ops = &clk_rcg2_ops,
 999         },
1000 };
1001
1002 static struct clk_rcg2 blsp1_uart2_apps_clk_src = {
1003         .cmd_rcgr = 0x03034,
1004         .mnd_width = 16,
1005         .hid_width = 5,
1006         .parent_map = gcc_xo_gpll0_map,
1007         .freq_tbl = ftbl_gcc_blsp1_uart1_6_apps_clk,
1008         .clkr.hw.init = &(struct clk_init_data){
1009                 .name = "blsp1_uart2_apps_clk_src",
1010                 .parent_data = gcc_xo_gpll0_parent_data,
1011                 .num_parents = ARRAY_SIZE(gcc_xo_gpll0_parent_data),
1012                 .ops = &clk_rcg2_ops,
1013         },
1014 };
1015
1016 static const struct freq_tbl ftbl_gcc_camss_cci_clk[] = {
1017         F(19200000, P_XO, 1, 0, 0),
1018         F(37500000, P_GPLL0, 1, 3, 64),
1019         { }
1020 };
1021
1022 static struct clk_rcg2 cci_clk_src = {
1023         .cmd_rcgr = 0x51000,
1024         .mnd_width = 8,
1025         .hid_width = 5,
1026         .parent_map = gcc_xo_gpll0a_map,
1027         .freq_tbl = ftbl_gcc_camss_cci_clk,
1028         .clkr.hw.init = &(struct clk_init_data){
1029                 .name = "cci_clk_src",
1030                 .parent_data = gcc_xo_gpll0a_parent_data,
1031                 .num_parents = ARRAY_SIZE(gcc_xo_gpll0a_parent_data),
1032                 .ops = &clk_rcg2_ops,
1033         },
1034 };
1035
1036 /*
1037  * This is a frequency table for "General Purpose" clocks.
1038  * These clocks can be muxed to the SoC pins and may be used by
1039  * external devices. They're often used as PWM source.
1040  *
1041  * See comment at ftbl_gcc_gp1_3_clk.
1042  */
1043 static const struct freq_tbl ftbl_gcc_camss_gp0_1_clk[] = {
1044         F(10000,   P_XO,    16,  1, 120),
1045         F(100000,  P_XO,    16,  1,  12),
1046         F(500000,  P_GPLL0, 16,  1, 100),
1047         F(1000000, P_GPLL0, 16,  1,  50),
1048         F(2500000, P_GPLL0, 16,  1,  20),
1049         F(5000000, P_GPLL0, 16,  1,  10),
1050         F(100000000, P_GPLL0, 8, 0, 0),
1051         F(200000000, P_GPLL0, 4, 0, 0),
1052         { }
1053 };
1054
1055 static struct clk_rcg2 camss_gp0_clk_src = {
1056         .cmd_rcgr = 0x54000,
1057         .mnd_width = 8,
1058         .hid_width = 5,
1059         .parent_map = gcc_xo_gpll0_gpll1a_sleep_map,
1060         .freq_tbl = ftbl_gcc_camss_gp0_1_clk,
1061         .clkr.hw.init = &(struct clk_init_data){
1062                 .name = "camss_gp0_clk_src",
1063                 .parent_data = gcc_xo_gpll0_gpll1a_sleep_parent_data,
1064                 .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll1a_sleep_parent_data),
1065                 .ops = &clk_rcg2_ops,
1066         },
1067 };
1068
1069 static struct clk_rcg2 camss_gp1_clk_src = {
1070         .cmd_rcgr = 0x55000,
1071         .mnd_width = 8,
1072         .hid_width = 5,
1073         .parent_map = gcc_xo_gpll0_gpll1a_sleep_map,
1074         .freq_tbl = ftbl_gcc_camss_gp0_1_clk,
1075         .clkr.hw.init = &(struct clk_init_data){
1076                 .name = "camss_gp1_clk_src",
1077                 .parent_data = gcc_xo_gpll0_gpll1a_sleep_parent_data,
1078                 .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll1a_sleep_parent_data),
1079                 .ops = &clk_rcg2_ops,
1080         },
1081 };
1082
1083 static const struct freq_tbl ftbl_gcc_camss_jpeg0_clk[] = {
1084         F(133330000, P_GPLL0, 6, 0,     0),
1085         F(266670000, P_GPLL0, 3, 0,     0),
1086         F(320000000, P_GPLL0, 2.5, 0, 0),
1087         { }
1088 };
1089
1090 static struct clk_rcg2 jpeg0_clk_src = {
1091         .cmd_rcgr = 0x57000,
1092         .hid_width = 5,
1093         .parent_map = gcc_xo_gpll0_map,
1094         .freq_tbl = ftbl_gcc_camss_jpeg0_clk,
1095         .clkr.hw.init = &(struct clk_init_data){
1096                 .name = "jpeg0_clk_src",
1097                 .parent_data = gcc_xo_gpll0_parent_data,
1098                 .num_parents = ARRAY_SIZE(gcc_xo_gpll0_parent_data),
1099                 .ops = &clk_rcg2_ops,
1100         },
1101 };
1102
1103 static const struct freq_tbl ftbl_gcc_camss_mclk0_1_clk[] = {
1104         F(24000000, P_GPLL0, 1, 1, 45),
1105         F(66670000, P_GPLL0, 12, 0, 0),
1106         { }
1107 };
1108
1109 static struct clk_rcg2 mclk0_clk_src = {
1110         .cmd_rcgr = 0x52000,
1111         .mnd_width = 8,
1112         .hid_width = 5,
1113         .parent_map = gcc_xo_gpll0_gpll1a_gpll6_sleep_map,
1114         .freq_tbl = ftbl_gcc_camss_mclk0_1_clk,
1115         .clkr.hw.init = &(struct clk_init_data){
1116                 .name = "mclk0_clk_src",
1117                 .parent_data = gcc_xo_gpll0_gpll1a_gpll6_sleep_parent_data,
1118                 .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll1a_gpll6_sleep_parent_data),
1119                 .ops = &clk_rcg2_ops,
1120         },
1121 };
1122
1123 static struct clk_rcg2 mclk1_clk_src = {
1124         .cmd_rcgr = 0x53000,
1125         .mnd_width = 8,
1126         .hid_width = 5,
1127         .parent_map = gcc_xo_gpll0_gpll1a_gpll6_sleep_map,
1128         .freq_tbl = ftbl_gcc_camss_mclk0_1_clk,
1129         .clkr.hw.init = &(struct clk_init_data){
1130                 .name = "mclk1_clk_src",
1131                 .parent_data = gcc_xo_gpll0_gpll1a_gpll6_sleep_parent_data,
1132                 .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll1a_gpll6_sleep_parent_data),
1133                 .ops = &clk_rcg2_ops,
1134         },
1135 };
1136
1137 static const struct freq_tbl ftbl_gcc_camss_csi0_1phytimer_clk[] = {
1138         F(100000000, P_GPLL0, 8, 0,     0),
1139         F(200000000, P_GPLL0, 4, 0,     0),
1140         { }
1141 };
1142
1143 static struct clk_rcg2 csi0phytimer_clk_src = {
1144         .cmd_rcgr = 0x4e000,
1145         .hid_width = 5,
1146         .parent_map = gcc_xo_gpll0_gpll1a_map,
1147         .freq_tbl = ftbl_gcc_camss_csi0_1phytimer_clk,
1148         .clkr.hw.init = &(struct clk_init_data){
1149                 .name = "csi0phytimer_clk_src",
1150                 .parent_data = gcc_xo_gpll0_gpll1a_parent_data,
1151                 .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll1a_parent_data),
1152                 .ops = &clk_rcg2_ops,
1153         },
1154 };
1155
1156 static struct clk_rcg2 csi1phytimer_clk_src = {
1157         .cmd_rcgr = 0x4f000,
1158         .hid_width = 5,
1159         .parent_map = gcc_xo_gpll0_gpll1a_map,
1160         .freq_tbl = ftbl_gcc_camss_csi0_1phytimer_clk,
1161         .clkr.hw.init = &(struct clk_init_data){
1162                 .name = "csi1phytimer_clk_src",
1163                 .parent_data = gcc_xo_gpll0_gpll1a_parent_data,
1164                 .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll1a_parent_data),
1165                 .ops = &clk_rcg2_ops,
1166         },
1167 };
1168
1169 static const struct freq_tbl ftbl_gcc_camss_cpp_clk[] = {
1170         F(160000000, P_GPLL0, 5, 0, 0),
1171         F(200000000, P_GPLL0, 4, 0, 0),
1172         F(228570000, P_GPLL0, 3.5, 0, 0),
1173         F(266670000, P_GPLL0, 3, 0, 0),
1174         F(320000000, P_GPLL0, 2.5, 0, 0),
1175         F(465000000, P_GPLL2, 2, 0, 0),
1176         { }
1177 };
1178
1179 static struct clk_rcg2 cpp_clk_src = {
1180         .cmd_rcgr = 0x58018,
1181         .hid_width = 5,
1182         .parent_map = gcc_xo_gpll0_gpll2_map,
1183         .freq_tbl = ftbl_gcc_camss_cpp_clk,
1184         .clkr.hw.init = &(struct clk_init_data){
1185                 .name = "cpp_clk_src",
1186                 .parent_data = gcc_xo_gpll0_gpll2_parent_data,
1187                 .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll2_parent_data),
1188                 .ops = &clk_rcg2_ops,
1189         },
1190 };
1191
1192 static const struct freq_tbl ftbl_gcc_crypto_clk[] = {
1193         F(50000000, P_GPLL0, 16, 0, 0),
1194         F(80000000, P_GPLL0, 10, 0, 0),
1195         F(100000000, P_GPLL0, 8, 0, 0),
1196         F(160000000, P_GPLL0, 5, 0, 0),
1197         { }
1198 };
1199
1200 /* This is not in the documentation but is in the downstream driver */
1201 static struct clk_rcg2 crypto_clk_src = {
1202         .cmd_rcgr = 0x16004,
1203         .hid_width = 5,
1204         .parent_map = gcc_xo_gpll0_map,
1205         .freq_tbl = ftbl_gcc_crypto_clk,
1206         .clkr.hw.init = &(struct clk_init_data){
1207                 .name = "crypto_clk_src",
1208                 .parent_data = gcc_xo_gpll0_parent_data,
1209                 .num_parents = ARRAY_SIZE(gcc_xo_gpll0_parent_data),
1210                 .ops = &clk_rcg2_ops,
1211         },
1212 };
1213
1214 /*
1215  * This is a frequency table for "General Purpose" clocks.
1216  * These clocks can be muxed to the SoC pins and may be used by
1217  * external devices. They're often used as PWM source.
1218  *
1219  * Please note that MND divider must be enabled for duty-cycle
1220  * control to be possible. (M != N) Also since D register is configured
1221  * with a value multiplied by 2, and duty cycle is calculated as
1222  *                             (2 * D) % 2^W
1223  *                DutyCycle = ----------------
1224  *                              2 * (N % 2^W)
1225  * (where W = .mnd_width)
1226  * N must be half or less than maximum value for the register.
1227  * Otherwise duty-cycle control would be limited.
1228  * (e.g. for 8-bit NMD N should be less than 128)
1229  */
1230 static const struct freq_tbl ftbl_gcc_gp1_3_clk[] = {
1231         F(10000,   P_XO,    16,  1, 120),
1232         F(100000,  P_XO,    16,  1,  12),
1233         F(500000,  P_GPLL0, 16,  1, 100),
1234         F(1000000, P_GPLL0, 16,  1,  50),
1235         F(2500000, P_GPLL0, 16,  1,  20),
1236         F(5000000, P_GPLL0, 16,  1,  10),
1237         F(19200000, P_XO, 1, 0, 0),
1238         { }
1239 };
1240
1241 static struct clk_rcg2 gp1_clk_src = {
1242         .cmd_rcgr = 0x08004,
1243         .mnd_width = 8,
1244         .hid_width = 5,
1245         .parent_map = gcc_xo_gpll0_gpll1a_sleep_map,
1246         .freq_tbl = ftbl_gcc_gp1_3_clk,
1247         .clkr.hw.init = &(struct clk_init_data){
1248                 .name = "gp1_clk_src",
1249                 .parent_data = gcc_xo_gpll0_gpll1a_sleep_parent_data,
1250                 .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll1a_sleep_parent_data),
1251                 .ops = &clk_rcg2_ops,
1252         },
1253 };
1254
1255 static struct clk_rcg2 gp2_clk_src = {
1256         .cmd_rcgr = 0x09004,
1257         .mnd_width = 8,
1258         .hid_width = 5,
1259         .parent_map = gcc_xo_gpll0_gpll1a_sleep_map,
1260         .freq_tbl = ftbl_gcc_gp1_3_clk,
1261         .clkr.hw.init = &(struct clk_init_data){
1262                 .name = "gp2_clk_src",
1263                 .parent_data = gcc_xo_gpll0_gpll1a_sleep_parent_data,
1264                 .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll1a_sleep_parent_data),
1265                 .ops = &clk_rcg2_ops,
1266         },
1267 };
1268
1269 static struct clk_rcg2 gp3_clk_src = {
1270         .cmd_rcgr = 0x0a004,
1271         .mnd_width = 8,
1272         .hid_width = 5,
1273         .parent_map = gcc_xo_gpll0_gpll1a_sleep_map,
1274         .freq_tbl = ftbl_gcc_gp1_3_clk,
1275         .clkr.hw.init = &(struct clk_init_data){
1276                 .name = "gp3_clk_src",
1277                 .parent_data = gcc_xo_gpll0_gpll1a_sleep_parent_data,
1278                 .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll1a_sleep_parent_data),
1279                 .ops = &clk_rcg2_ops,
1280         },
1281 };
1282
1283 static struct clk_rcg2 byte0_clk_src = {
1284         .cmd_rcgr = 0x4d044,
1285         .hid_width = 5,
1286         .parent_map = gcc_xo_gpll0a_dsibyte_map,
1287         .clkr.hw.init = &(struct clk_init_data){
1288                 .name = "byte0_clk_src",
1289                 .parent_data = gcc_xo_gpll0a_dsibyte_parent_data,
1290                 .num_parents = ARRAY_SIZE(gcc_xo_gpll0a_dsibyte_parent_data),
1291                 .ops = &clk_byte2_ops,
1292                 .flags = CLK_SET_RATE_PARENT,
1293         },
1294 };
1295
1296 static struct clk_rcg2 byte1_clk_src = {
1297         .cmd_rcgr = 0x4d0b0,
1298         .hid_width = 5,
1299         .parent_map = gcc_xo_gpll0a_dsibyte_map,
1300         .clkr.hw.init = &(struct clk_init_data){
1301                 .name = "byte1_clk_src",
1302                 .parent_data = gcc_xo_gpll0a_dsibyte_parent_data,
1303                 .num_parents = ARRAY_SIZE(gcc_xo_gpll0a_dsibyte_parent_data),
1304                 .ops = &clk_byte2_ops,
1305                 .flags = CLK_SET_RATE_PARENT,
1306         },
1307 };
1308
1309 static const struct freq_tbl ftbl_gcc_mdss_esc_clk[] = {
1310         F(19200000, P_XO, 1, 0, 0),
1311         { }
1312 };
1313
1314 static struct clk_rcg2 esc0_clk_src = {
1315         .cmd_rcgr = 0x4d060,
1316         .hid_width = 5,
1317         .parent_map = gcc_xo_dsibyte_map,
1318         .freq_tbl = ftbl_gcc_mdss_esc_clk,
1319         .clkr.hw.init = &(struct clk_init_data){
1320                 .name = "esc0_clk_src",
1321                 .parent_data = gcc_xo_dsibyte_parent_data,
1322                 .num_parents = ARRAY_SIZE(gcc_xo_dsibyte_parent_data),
1323                 .ops = &clk_rcg2_ops,
1324         },
1325 };
1326
1327 static struct clk_rcg2 esc1_clk_src = {
1328         .cmd_rcgr = 0x4d0a8,
1329         .hid_width = 5,
1330         .parent_map = gcc_xo_dsibyte_map,
1331         .freq_tbl = ftbl_gcc_mdss_esc_clk,
1332         .clkr.hw.init = &(struct clk_init_data){
1333                 .name = "esc1_clk_src",
1334                 .parent_data = gcc_xo_dsibyte_parent_data,
1335                 .num_parents = ARRAY_SIZE(gcc_xo_dsibyte_parent_data),
1336                 .ops = &clk_rcg2_ops,
1337         },
1338 };
1339
1340 static const struct freq_tbl ftbl_gcc_mdss_mdp_clk[] = {
1341         F(50000000, P_GPLL0_AUX, 16, 0, 0),
1342         F(80000000, P_GPLL0_AUX, 10, 0, 0),
1343         F(100000000, P_GPLL0_AUX, 8, 0, 0),
1344         F(145500000, P_GPLL0_AUX, 5.5, 0, 0),
1345         F(153600000, P_GPLL0, 4, 0, 0),
1346         F(160000000, P_GPLL0_AUX, 5, 0, 0),
1347         F(177780000, P_GPLL0_AUX, 4.5, 0, 0),
1348         F(200000000, P_GPLL0_AUX, 4, 0, 0),
1349         F(266670000, P_GPLL0_AUX, 3, 0, 0),
1350         F(307200000, P_GPLL1, 2, 0, 0),
1351         F(366670000, P_GPLL3_AUX, 3, 0, 0),
1352         { }
1353 };
1354
1355 static struct clk_rcg2 mdp_clk_src = {
1356         .cmd_rcgr = 0x4d014,
1357         .hid_width = 5,
1358         .parent_map = gcc_xo_gpll1_dsiphy_gpll6_gpll3a_gpll0a_map,
1359         .freq_tbl = ftbl_gcc_mdss_mdp_clk,
1360         .clkr.hw.init = &(struct clk_init_data){
1361                 .name = "mdp_clk_src",
1362                 .parent_data = gcc_xo_gpll1_dsiphy_gpll6_gpll3a_gpll0a_parent_data,
1363                 .num_parents = ARRAY_SIZE(gcc_xo_gpll1_dsiphy_gpll6_gpll3a_gpll0a_parent_data),
1364                 .ops = &clk_rcg2_ops,
1365         },
1366 };
1367
1368 static struct clk_rcg2 pclk0_clk_src = {
1369         .cmd_rcgr = 0x4d000,
1370         .mnd_width = 8,
1371         .hid_width = 5,
1372         .parent_map = gcc_xo_gpll0a_dsiphy_map,
1373         .clkr.hw.init = &(struct clk_init_data){
1374                 .name = "pclk0_clk_src",
1375                 .parent_data = gcc_xo_gpll0a_dsiphy_parent_data,
1376                 .num_parents = ARRAY_SIZE(gcc_xo_gpll0a_dsiphy_parent_data),
1377                 .ops = &clk_pixel_ops,
1378                 .flags = CLK_SET_RATE_PARENT,
1379         },
1380 };
1381
1382 static struct clk_rcg2 pclk1_clk_src = {
1383         .cmd_rcgr = 0x4d0b8,
1384         .mnd_width = 8,
1385         .hid_width = 5,
1386         .parent_map = gcc_xo_gpll0a_dsiphy_map,
1387         .clkr.hw.init = &(struct clk_init_data){
1388                 .name = "pclk1_clk_src",
1389                 .parent_data = gcc_xo_gpll0a_dsiphy_parent_data,
1390                 .num_parents = ARRAY_SIZE(gcc_xo_gpll0a_dsiphy_parent_data),
1391                 .ops = &clk_pixel_ops,
1392                 .flags = CLK_SET_RATE_PARENT,
1393         },
1394 };
1395
1396 static const struct freq_tbl ftbl_gcc_mdss_vsync_clk[] = {
1397         F(19200000, P_XO, 1, 0, 0),
1398         { }
1399 };
1400
1401 static struct clk_rcg2 vsync_clk_src = {
1402         .cmd_rcgr = 0x4d02c,
1403         .hid_width = 5,
1404         .parent_map = gcc_xo_gpll0a_map,
1405         .freq_tbl = ftbl_gcc_mdss_vsync_clk,
1406         .clkr.hw.init = &(struct clk_init_data){
1407                 .name = "vsync_clk_src",
1408                 .parent_data = gcc_xo_gpll0a_parent_data,
1409                 .num_parents = ARRAY_SIZE(gcc_xo_gpll0a_parent_data),
1410                 .ops = &clk_rcg2_ops,
1411         },
1412 };
1413
1414 static const struct freq_tbl ftbl_gcc_pdm2_clk[] = {
1415         F(64000000, P_GPLL0, 12.5, 0, 0),
1416         { }
1417 };
1418
1419 /* This is not in the documentation but is in the downstream driver */
1420 static struct clk_rcg2 pdm2_clk_src = {
1421         .cmd_rcgr = 0x44010,
1422         .hid_width = 5,
1423         .parent_map = gcc_xo_gpll0_map,
1424         .freq_tbl = ftbl_gcc_pdm2_clk,
1425         .clkr.hw.init = &(struct clk_init_data){
1426                 .name = "pdm2_clk_src",
1427                 .parent_data = gcc_xo_gpll0_parent_data,
1428                 .num_parents = ARRAY_SIZE(gcc_xo_gpll0_parent_data),
1429                 .ops = &clk_rcg2_ops,
1430         },
1431 };
1432
1433 static const struct freq_tbl ftbl_gcc_sdcc_apps_clk[] = {
1434         F(144000, P_XO, 16, 3, 25),
1435         F(400000, P_XO, 12, 1, 4),
1436         F(20000000, P_GPLL0, 10, 1, 4),
1437         F(25000000, P_GPLL0, 16, 1, 2),
1438         F(50000000, P_GPLL0, 16, 0, 0),
1439         F(100000000, P_GPLL0, 8, 0, 0),
1440         F(177770000, P_GPLL0, 4.5, 0, 0),
1441         F(200000000, P_GPLL0, 4, 0, 0),
1442         { }
1443 };
1444
1445 static struct clk_rcg2 sdcc1_apps_clk_src = {
1446         .cmd_rcgr = 0x42004,
1447         .mnd_width = 8,
1448         .hid_width = 5,
1449         .parent_map = gcc_xo_gpll0_map,
1450         .freq_tbl = ftbl_gcc_sdcc_apps_clk,
1451         .clkr.hw.init = &(struct clk_init_data){
1452                 .name = "sdcc1_apps_clk_src",
1453                 .parent_data = gcc_xo_gpll0_parent_data,
1454                 .num_parents = ARRAY_SIZE(gcc_xo_gpll0_parent_data),
1455                 .ops = &clk_rcg2_floor_ops,
1456         },
1457 };
1458
1459 static struct clk_rcg2 sdcc2_apps_clk_src = {
1460         .cmd_rcgr = 0x43004,
1461         .mnd_width = 8,
1462         .hid_width = 5,
1463         .parent_map = gcc_xo_gpll0_map,
1464         .freq_tbl = ftbl_gcc_sdcc_apps_clk,
1465         .clkr.hw.init = &(struct clk_init_data){
1466                 .name = "sdcc2_apps_clk_src",
1467                 .parent_data = gcc_xo_gpll0_parent_data,
1468                 .num_parents = ARRAY_SIZE(gcc_xo_gpll0_parent_data),
1469                 .ops = &clk_rcg2_floor_ops,
1470         },
1471 };
1472
1473 static const struct freq_tbl ftbl_gcc_apss_tcu_clk[] = {
1474         F(154285000, P_GPLL6, 7, 0, 0),
1475         F(320000000, P_GPLL0, 2.5, 0, 0),
1476         F(400000000, P_GPLL0, 2, 0, 0),
1477         { }
1478 };
1479
1480 static struct clk_rcg2 apss_tcu_clk_src = {
1481         .cmd_rcgr = 0x1207c,
1482         .hid_width = 5,
1483         .parent_map = gcc_xo_gpll0_gpll5a_gpll6_bimc_map,
1484         .freq_tbl = ftbl_gcc_apss_tcu_clk,
1485         .clkr.hw.init = &(struct clk_init_data){
1486                 .name = "apss_tcu_clk_src",
1487                 .parent_data = gcc_xo_gpll0_gpll5a_gpll6_bimc_parent_data,
1488                 .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll5a_gpll6_bimc_parent_data),
1489                 .ops = &clk_rcg2_ops,
1490         },
1491 };
1492
1493 static const struct freq_tbl ftbl_gcc_bimc_gpu_clk[] = {
1494         F(19200000, P_XO, 1, 0, 0),
1495         F(100000000, P_GPLL0, 8, 0, 0),
1496         F(200000000, P_GPLL0, 4, 0, 0),
1497         F(266500000, P_BIMC, 4, 0, 0),
1498         F(400000000, P_GPLL0, 2, 0, 0),
1499         F(533000000, P_BIMC, 2, 0, 0),
1500         { }
1501 };
1502
1503 static struct clk_rcg2 bimc_gpu_clk_src = {
1504         .cmd_rcgr = 0x31028,
1505         .hid_width = 5,
1506         .parent_map = gcc_xo_gpll0_gpll5a_gpll6_bimc_map,
1507         .freq_tbl = ftbl_gcc_bimc_gpu_clk,
1508         .clkr.hw.init = &(struct clk_init_data){
1509                 .name = "bimc_gpu_clk_src",
1510                 .parent_data = gcc_xo_gpll0_gpll5a_gpll6_bimc_parent_data,
1511                 .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll5a_gpll6_bimc_parent_data),
1512                 .flags = CLK_GET_RATE_NOCACHE,
1513                 .ops = &clk_rcg2_ops,
1514         },
1515 };
1516
1517 static const struct freq_tbl ftbl_gcc_usb_hs_system_clk[] = {
1518         F(57140000, P_GPLL0, 14, 0, 0),
1519         F(80000000, P_GPLL0, 10, 0, 0),
1520         F(100000000, P_GPLL0, 8, 0, 0),
1521         { }
1522 };
1523
1524 static struct clk_rcg2 usb_hs_system_clk_src = {
1525         .cmd_rcgr = 0x41010,
1526         .hid_width = 5,
1527         .parent_map = gcc_xo_gpll0_map,
1528         .freq_tbl = ftbl_gcc_usb_hs_system_clk,
1529         .clkr.hw.init = &(struct clk_init_data){
1530                 .name = "usb_hs_system_clk_src",
1531                 .parent_data = gcc_xo_gpll0_parent_data,
1532                 .num_parents = ARRAY_SIZE(gcc_xo_gpll0_parent_data),
1533                 .ops = &clk_rcg2_ops,
1534         },
1535 };
1536
1537 static const struct freq_tbl ftbl_gcc_usb_fs_system_clk[] = {
1538         F(64000000, P_GPLL0, 12.5, 0, 0),
1539         { }
1540 };
1541
1542 static struct clk_rcg2 usb_fs_system_clk_src = {
1543         .cmd_rcgr = 0x3f010,
1544         .hid_width = 5,
1545         .parent_map = gcc_xo_gpll0_map,
1546         .freq_tbl = ftbl_gcc_usb_fs_system_clk,
1547         .clkr.hw.init = &(struct clk_init_data){
1548                 .name = "usb_fs_system_clk_src",
1549                 .parent_data = gcc_xo_gpll6_gpll0_parent_data,
1550                 .num_parents = ARRAY_SIZE(gcc_xo_gpll6_gpll0_parent_data),
1551                 .ops = &clk_rcg2_ops,
1552         },
1553 };
1554
1555 static const struct freq_tbl ftbl_gcc_usb_fs_ic_clk[] = {
1556         F(60000000, P_GPLL6, 1, 1, 18),
1557         { }
1558 };
1559
1560 static struct clk_rcg2 usb_fs_ic_clk_src = {
1561         .cmd_rcgr = 0x3f034,
1562         .hid_width = 5,
1563         .parent_map = gcc_xo_gpll0_map,
1564         .freq_tbl = ftbl_gcc_usb_fs_ic_clk,
1565         .clkr.hw.init = &(struct clk_init_data){
1566                 .name = "usb_fs_ic_clk_src",
1567                 .parent_data = gcc_xo_gpll6_gpll0a_parent_data,
1568                 .num_parents = ARRAY_SIZE(gcc_xo_gpll6_gpll0a_parent_data),
1569                 .ops = &clk_rcg2_ops,
1570         },
1571 };
1572
1573 static const struct freq_tbl ftbl_gcc_ultaudio_ahb_clk[] = {
1574         F(3200000, P_XO, 6, 0, 0),
1575         F(6400000, P_XO, 3, 0, 0),
1576         F(9600000, P_XO, 2, 0, 0),
1577         F(19200000, P_XO, 1, 0, 0),
1578         F(40000000, P_GPLL0, 10, 1, 2),
1579         F(66670000, P_GPLL0, 12, 0, 0),
1580         F(80000000, P_GPLL0, 10, 0, 0),
1581         F(100000000, P_GPLL0, 8, 0, 0),
1582         { }
1583 };
1584
1585 static struct clk_rcg2 ultaudio_ahbfabric_clk_src = {
1586         .cmd_rcgr = 0x1c010,
1587         .hid_width = 5,
1588         .mnd_width = 8,
1589         .parent_map = gcc_xo_gpll0_gpll1_sleep_map,
1590         .freq_tbl = ftbl_gcc_ultaudio_ahb_clk,
1591         .clkr.hw.init = &(struct clk_init_data){
1592                 .name = "ultaudio_ahbfabric_clk_src",
1593                 .parent_data = gcc_xo_gpll0_gpll1_sleep_parent_data,
1594                 .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll1_sleep_parent_data),
1595                 .ops = &clk_rcg2_ops,
1596         },
1597 };
1598
1599 static struct clk_branch gcc_ultaudio_ahbfabric_ixfabric_clk = {
1600         .halt_reg = 0x1c028,
1601         .clkr = {
1602                 .enable_reg = 0x1c028,
1603                 .enable_mask = BIT(0),
1604                 .hw.init = &(struct clk_init_data){
1605                         .name = "gcc_ultaudio_ahbfabric_ixfabric_clk",
1606                         .parent_hws = (const struct clk_hw*[]){
1607                                 &ultaudio_ahbfabric_clk_src.clkr.hw,
1608                         },
1609                         .num_parents = 1,
1610                         .flags = CLK_SET_RATE_PARENT,
1611                         .ops = &clk_branch2_ops,
1612                 },
1613         },
1614 };
1615
1616 static struct clk_branch gcc_ultaudio_ahbfabric_ixfabric_lpm_clk = {
1617         .halt_reg = 0x1c024,
1618         .clkr = {
1619                 .enable_reg = 0x1c024,
1620                 .enable_mask = BIT(0),
1621                 .hw.init = &(struct clk_init_data){
1622                         .name = "gcc_ultaudio_ahbfabric_ixfabric_lpm_clk",
1623                         .parent_hws = (const struct clk_hw*[]){
1624                                 &ultaudio_ahbfabric_clk_src.clkr.hw,
1625                         },
1626                         .num_parents = 1,
1627                         .flags = CLK_SET_RATE_PARENT,
1628                         .ops = &clk_branch2_ops,
1629                 },
1630         },
1631 };
1632
1633 static const struct freq_tbl ftbl_gcc_ultaudio_lpaif_i2s_clk[] = {
1634         F(128000, P_XO, 10, 1, 15),
1635         F(256000, P_XO, 5, 1, 15),
1636         F(384000, P_XO, 5, 1, 10),
1637         F(512000, P_XO, 5, 2, 15),
1638         F(576000, P_XO, 5, 3, 20),
1639         F(705600, P_GPLL1, 16, 1, 80),
1640         F(768000, P_XO, 5, 1, 5),
1641         F(800000, P_XO, 5, 5, 24),
1642         F(1024000, P_XO, 5, 4, 15),
1643         F(1152000, P_XO, 1, 3, 50),
1644         F(1411200, P_GPLL1, 16, 1, 40),
1645         F(1536000, P_XO, 1, 2, 25),
1646         F(1600000, P_XO, 12, 0, 0),
1647         F(1728000, P_XO, 5, 9, 20),
1648         F(2048000, P_XO, 5, 8, 15),
1649         F(2304000, P_XO, 5, 3, 5),
1650         F(2400000, P_XO, 8, 0, 0),
1651         F(2822400, P_GPLL1, 16, 1, 20),
1652         F(3072000, P_XO, 5, 4, 5),
1653         F(4096000, P_GPLL1, 9, 2, 49),
1654         F(4800000, P_XO, 4, 0, 0),
1655         F(5644800, P_GPLL1, 16, 1, 10),
1656         F(6144000, P_GPLL1, 7, 1, 21),
1657         F(8192000, P_GPLL1, 9, 4, 49),
1658         F(9600000, P_XO, 2, 0, 0),
1659         F(11289600, P_GPLL1, 16, 1, 5),
1660         F(12288000, P_GPLL1, 7, 2, 21),
1661         { }
1662 };
1663
1664 static struct clk_rcg2 ultaudio_lpaif_pri_i2s_clk_src = {
1665         .cmd_rcgr = 0x1c054,
1666         .hid_width = 5,
1667         .mnd_width = 8,
1668         .parent_map = gcc_xo_gpll1_epi2s_emclk_sleep_map,
1669         .freq_tbl = ftbl_gcc_ultaudio_lpaif_i2s_clk,
1670         .clkr.hw.init = &(struct clk_init_data){
1671                 .name = "ultaudio_lpaif_pri_i2s_clk_src",
1672                 .parent_data = gcc_xo_gpll1_epi2s_emclk_sleep_parent_data,
1673                 .num_parents = ARRAY_SIZE(gcc_xo_gpll1_epi2s_emclk_sleep_parent_data),
1674                 .ops = &clk_rcg2_ops,
1675         },
1676 };
1677
1678 static struct clk_branch gcc_ultaudio_lpaif_pri_i2s_clk = {
1679         .halt_reg = 0x1c068,
1680         .clkr = {
1681                 .enable_reg = 0x1c068,
1682                 .enable_mask = BIT(0),
1683                 .hw.init = &(struct clk_init_data){
1684                         .name = "gcc_ultaudio_lpaif_pri_i2s_clk",
1685                         .parent_hws = (const struct clk_hw*[]){
1686                                 &ultaudio_lpaif_pri_i2s_clk_src.clkr.hw,
1687                         },
1688                         .num_parents = 1,
1689                         .flags = CLK_SET_RATE_PARENT,
1690                         .ops = &clk_branch2_ops,
1691                 },
1692         },
1693 };
1694
1695 static struct clk_rcg2 ultaudio_lpaif_sec_i2s_clk_src = {
1696         .cmd_rcgr = 0x1c06c,
1697         .hid_width = 5,
1698         .mnd_width = 8,
1699         .parent_map = gcc_xo_gpll1_esi2s_emclk_sleep_map,
1700         .freq_tbl = ftbl_gcc_ultaudio_lpaif_i2s_clk,
1701         .clkr.hw.init = &(struct clk_init_data){
1702                 .name = "ultaudio_lpaif_sec_i2s_clk_src",
1703                 .parent_data = gcc_xo_gpll1_esi2s_emclk_sleep_parent_data,
1704                 .num_parents = ARRAY_SIZE(gcc_xo_gpll1_esi2s_emclk_sleep_parent_data),
1705                 .ops = &clk_rcg2_ops,
1706         },
1707 };
1708
1709 static struct clk_branch gcc_ultaudio_lpaif_sec_i2s_clk = {
1710         .halt_reg = 0x1c080,
1711         .clkr = {
1712                 .enable_reg = 0x1c080,
1713                 .enable_mask = BIT(0),
1714                 .hw.init = &(struct clk_init_data){
1715                         .name = "gcc_ultaudio_lpaif_sec_i2s_clk",
1716                         .parent_hws = (const struct clk_hw*[]){
1717                                 &ultaudio_lpaif_sec_i2s_clk_src.clkr.hw,
1718                         },
1719                         .num_parents = 1,
1720                         .flags = CLK_SET_RATE_PARENT,
1721                         .ops = &clk_branch2_ops,
1722                 },
1723         },
1724 };
1725
1726 static struct clk_rcg2 ultaudio_lpaif_aux_i2s_clk_src = {
1727         .cmd_rcgr = 0x1c084,
1728         .hid_width = 5,
1729         .mnd_width = 8,
1730         .parent_map = gcc_xo_gpll1_emclk_sleep_map,
1731         .freq_tbl = ftbl_gcc_ultaudio_lpaif_i2s_clk,
1732         .clkr.hw.init = &(struct clk_init_data){
1733                 .name = "ultaudio_lpaif_aux_i2s_clk_src",
1734                 .parent_data = gcc_xo_gpll1_esi2s_emclk_sleep_parent_data,
1735                 .num_parents = ARRAY_SIZE(gcc_xo_gpll1_esi2s_emclk_sleep_parent_data),
1736                 .ops = &clk_rcg2_ops,
1737         },
1738 };
1739
1740 static struct clk_branch gcc_ultaudio_lpaif_aux_i2s_clk = {
1741         .halt_reg = 0x1c098,
1742         .clkr = {
1743                 .enable_reg = 0x1c098,
1744                 .enable_mask = BIT(0),
1745                 .hw.init = &(struct clk_init_data){
1746                         .name = "gcc_ultaudio_lpaif_aux_i2s_clk",
1747                         .parent_hws = (const struct clk_hw*[]){
1748                                 &ultaudio_lpaif_aux_i2s_clk_src.clkr.hw,
1749                         },
1750                         .num_parents = 1,
1751                         .flags = CLK_SET_RATE_PARENT,
1752                         .ops = &clk_branch2_ops,
1753                 },
1754         },
1755 };
1756
1757 static const struct freq_tbl ftbl_gcc_ultaudio_xo_clk[] = {
1758         F(19200000, P_XO, 1, 0, 0),
1759         { }
1760 };
1761
1762 static struct clk_rcg2 ultaudio_xo_clk_src = {
1763         .cmd_rcgr = 0x1c034,
1764         .hid_width = 5,
1765         .parent_map = gcc_xo_sleep_map,
1766         .freq_tbl = ftbl_gcc_ultaudio_xo_clk,
1767         .clkr.hw.init = &(struct clk_init_data){
1768                 .name = "ultaudio_xo_clk_src",
1769                 .parent_data = gcc_xo_sleep_parent_data,
1770                 .num_parents = ARRAY_SIZE(gcc_xo_sleep_parent_data),
1771                 .ops = &clk_rcg2_ops,
1772         },
1773 };
1774
1775 static struct clk_branch gcc_ultaudio_avsync_xo_clk = {
1776         .halt_reg = 0x1c04c,
1777         .clkr = {
1778                 .enable_reg = 0x1c04c,
1779                 .enable_mask = BIT(0),
1780                 .hw.init = &(struct clk_init_data){
1781                         .name = "gcc_ultaudio_avsync_xo_clk",
1782                         .parent_hws = (const struct clk_hw*[]){
1783                                 &ultaudio_xo_clk_src.clkr.hw,
1784                         },
1785                         .num_parents = 1,
1786                         .flags = CLK_SET_RATE_PARENT,
1787                         .ops = &clk_branch2_ops,
1788                 },
1789         },
1790 };
1791
1792 static struct clk_branch gcc_ultaudio_stc_xo_clk = {
1793         .halt_reg = 0x1c050,
1794         .clkr = {
1795                 .enable_reg = 0x1c050,
1796                 .enable_mask = BIT(0),
1797                 .hw.init = &(struct clk_init_data){
1798                         .name = "gcc_ultaudio_stc_xo_clk",
1799                         .parent_hws = (const struct clk_hw*[]){
1800                                 &ultaudio_xo_clk_src.clkr.hw,
1801                         },
1802                         .num_parents = 1,
1803                         .flags = CLK_SET_RATE_PARENT,
1804                         .ops = &clk_branch2_ops,
1805                 },
1806         },
1807 };
1808
1809 static const struct freq_tbl ftbl_codec_clk[] = {
1810         F(9600000, P_XO, 2, 0, 0),
1811         F(12288000, P_XO, 1, 16, 25),
1812         F(19200000, P_XO, 1, 0, 0),
1813         F(11289600, P_EXT_MCLK, 1, 0, 0),
1814         { }
1815 };
1816
1817 static struct clk_rcg2 codec_digcodec_clk_src = {
1818         .cmd_rcgr = 0x1c09c,
1819         .mnd_width = 8,
1820         .hid_width = 5,
1821         .parent_map = gcc_xo_gpll1_emclk_sleep_map,
1822         .freq_tbl = ftbl_codec_clk,
1823         .clkr.hw.init = &(struct clk_init_data){
1824                 .name = "codec_digcodec_clk_src",
1825                 .parent_data = gcc_xo_gpll1_emclk_sleep_parent_data,
1826                 .num_parents = ARRAY_SIZE(gcc_xo_gpll1_emclk_sleep_parent_data),
1827                 .ops = &clk_rcg2_ops,
1828         },
1829 };
1830
1831 static struct clk_branch gcc_codec_digcodec_clk = {
1832         .halt_reg = 0x1c0b0,
1833         .clkr = {
1834                 .enable_reg = 0x1c0b0,
1835                 .enable_mask = BIT(0),
1836                 .hw.init = &(struct clk_init_data){
1837                         .name = "gcc_ultaudio_codec_digcodec_clk",
1838                         .parent_hws = (const struct clk_hw*[]){
1839                                 &codec_digcodec_clk_src.clkr.hw,
1840                         },
1841                         .num_parents = 1,
1842                         .flags = CLK_SET_RATE_PARENT,
1843                         .ops = &clk_branch2_ops,
1844                 },
1845         },
1846 };
1847
1848 static struct clk_branch gcc_ultaudio_pcnoc_mport_clk = {
1849         .halt_reg = 0x1c000,
1850         .clkr = {
1851                 .enable_reg = 0x1c000,
1852                 .enable_mask = BIT(0),
1853                 .hw.init = &(struct clk_init_data){
1854                         .name = "gcc_ultaudio_pcnoc_mport_clk",
1855                         .parent_hws = (const struct clk_hw*[]){
1856                                 &pcnoc_bfdcd_clk_src.clkr.hw,
1857                         },
1858                         .num_parents = 1,
1859                         .ops = &clk_branch2_ops,
1860                 },
1861         },
1862 };
1863
1864 static struct clk_branch gcc_ultaudio_pcnoc_sway_clk = {
1865         .halt_reg = 0x1c004,
1866         .clkr = {
1867                 .enable_reg = 0x1c004,
1868                 .enable_mask = BIT(0),
1869                 .hw.init = &(struct clk_init_data){
1870                         .name = "gcc_ultaudio_pcnoc_sway_clk",
1871                         .parent_hws = (const struct clk_hw*[]){
1872                                 &pcnoc_bfdcd_clk_src.clkr.hw,
1873                         },
1874                         .num_parents = 1,
1875                         .ops = &clk_branch2_ops,
1876                 },
1877         },
1878 };
1879
1880 static const struct freq_tbl ftbl_gcc_venus0_vcodec0_clk[] = {
1881         F(133330000, P_GPLL0, 6, 0, 0),
1882         F(200000000, P_GPLL0, 4, 0, 0),
1883         F(266670000, P_GPLL0, 3, 0, 0),
1884         { }
1885 };
1886
1887 static struct clk_rcg2 vcodec0_clk_src = {
1888         .cmd_rcgr = 0x4C000,
1889         .mnd_width = 8,
1890         .hid_width = 5,
1891         .parent_map = gcc_xo_gpll0_map,
1892         .freq_tbl = ftbl_gcc_venus0_vcodec0_clk,
1893         .clkr.hw.init = &(struct clk_init_data){
1894                 .name = "vcodec0_clk_src",
1895                 .parent_data = gcc_xo_gpll0_parent_data,
1896                 .num_parents = ARRAY_SIZE(gcc_xo_gpll0_parent_data),
1897                 .ops = &clk_rcg2_ops,
1898         },
1899 };
1900
1901 static struct clk_branch gcc_blsp1_ahb_clk = {
1902         .halt_reg = 0x01008,
1903         .halt_check = BRANCH_HALT_VOTED,
1904         .clkr = {
1905                 .enable_reg = 0x45004,
1906                 .enable_mask = BIT(10),
1907                 .hw.init = &(struct clk_init_data){
1908                         .name = "gcc_blsp1_ahb_clk",
1909                         .parent_hws = (const struct clk_hw*[]){
1910                                 &pcnoc_bfdcd_clk_src.clkr.hw,
1911                         },
1912                         .num_parents = 1,
1913                         .ops = &clk_branch2_ops,
1914                 },
1915         },
1916 };
1917
1918 static struct clk_branch gcc_blsp1_sleep_clk = {
1919         .halt_reg = 0x01004,
1920         .clkr = {
1921                 .enable_reg = 0x01004,
1922                 .enable_mask = BIT(0),
1923                 .hw.init = &(struct clk_init_data){
1924                         .name = "gcc_blsp1_sleep_clk",
1925                         .ops = &clk_branch2_ops,
1926                 },
1927         },
1928 };
1929
1930 static struct clk_branch gcc_blsp1_qup1_i2c_apps_clk = {
1931         .halt_reg = 0x02008,
1932         .clkr = {
1933                 .enable_reg = 0x02008,
1934                 .enable_mask = BIT(0),
1935                 .hw.init = &(struct clk_init_data){
1936                         .name = "gcc_blsp1_qup1_i2c_apps_clk",
1937                         .parent_hws = (const struct clk_hw*[]){
1938                                 &blsp1_qup1_i2c_apps_clk_src.clkr.hw,
1939                         },
1940                         .num_parents = 1,
1941                         .flags = CLK_SET_RATE_PARENT,
1942                         .ops = &clk_branch2_ops,
1943                 },
1944         },
1945 };
1946
1947 static struct clk_branch gcc_blsp1_qup1_spi_apps_clk = {
1948         .halt_reg = 0x02004,
1949         .clkr = {
1950                 .enable_reg = 0x02004,
1951                 .enable_mask = BIT(0),
1952                 .hw.init = &(struct clk_init_data){
1953                         .name = "gcc_blsp1_qup1_spi_apps_clk",
1954                         .parent_hws = (const struct clk_hw*[]){
1955                                 &blsp1_qup1_spi_apps_clk_src.clkr.hw,
1956                         },
1957                         .num_parents = 1,
1958                         .flags = CLK_SET_RATE_PARENT,
1959                         .ops = &clk_branch2_ops,
1960                 },
1961         },
1962 };
1963
1964 static struct clk_branch gcc_blsp1_qup2_i2c_apps_clk = {
1965         .halt_reg = 0x03010,
1966         .clkr = {
1967                 .enable_reg = 0x03010,
1968                 .enable_mask = BIT(0),
1969                 .hw.init = &(struct clk_init_data){
1970                         .name = "gcc_blsp1_qup2_i2c_apps_clk",
1971                         .parent_hws = (const struct clk_hw*[]){
1972                                 &blsp1_qup2_i2c_apps_clk_src.clkr.hw,
1973                         },
1974                         .num_parents = 1,
1975                         .flags = CLK_SET_RATE_PARENT,
1976                         .ops = &clk_branch2_ops,
1977                 },
1978         },
1979 };
1980
1981 static struct clk_branch gcc_blsp1_qup2_spi_apps_clk = {
1982         .halt_reg = 0x0300c,
1983         .clkr = {
1984                 .enable_reg = 0x0300c,
1985                 .enable_mask = BIT(0),
1986                 .hw.init = &(struct clk_init_data){
1987                         .name = "gcc_blsp1_qup2_spi_apps_clk",
1988                         .parent_hws = (const struct clk_hw*[]){
1989                                 &blsp1_qup2_spi_apps_clk_src.clkr.hw,
1990                         },
1991                         .num_parents = 1,
1992                         .flags = CLK_SET_RATE_PARENT,
1993                         .ops = &clk_branch2_ops,
1994                 },
1995         },
1996 };
1997
1998 static struct clk_branch gcc_blsp1_qup3_i2c_apps_clk = {
1999         .halt_reg = 0x04020,
2000         .clkr = {
2001                 .enable_reg = 0x04020,
2002                 .enable_mask = BIT(0),
2003                 .hw.init = &(struct clk_init_data){
2004                         .name = "gcc_blsp1_qup3_i2c_apps_clk",
2005                         .parent_hws = (const struct clk_hw*[]){
2006                                 &blsp1_qup3_i2c_apps_clk_src.clkr.hw,
2007                         },
2008                         .num_parents = 1,
2009                         .flags = CLK_SET_RATE_PARENT,
2010                         .ops = &clk_branch2_ops,
2011                 },
2012         },
2013 };
2014
2015 static struct clk_branch gcc_blsp1_qup3_spi_apps_clk = {
2016         .halt_reg = 0x0401c,
2017         .clkr = {
2018                 .enable_reg = 0x0401c,
2019                 .enable_mask = BIT(0),
2020                 .hw.init = &(struct clk_init_data){
2021                         .name = "gcc_blsp1_qup3_spi_apps_clk",
2022                         .parent_hws = (const struct clk_hw*[]){
2023                                 &blsp1_qup3_spi_apps_clk_src.clkr.hw,
2024                         },
2025                         .num_parents = 1,
2026                         .flags = CLK_SET_RATE_PARENT,
2027                         .ops = &clk_branch2_ops,
2028                 },
2029         },
2030 };
2031
2032 static struct clk_branch gcc_blsp1_qup4_i2c_apps_clk = {
2033         .halt_reg = 0x05020,
2034         .clkr = {
2035                 .enable_reg = 0x05020,
2036                 .enable_mask = BIT(0),
2037                 .hw.init = &(struct clk_init_data){
2038                         .name = "gcc_blsp1_qup4_i2c_apps_clk",
2039                         .parent_hws = (const struct clk_hw*[]){
2040                                 &blsp1_qup4_i2c_apps_clk_src.clkr.hw,
2041                         },
2042                         .num_parents = 1,
2043                         .flags = CLK_SET_RATE_PARENT,
2044                         .ops = &clk_branch2_ops,
2045                 },
2046         },
2047 };
2048
2049 static struct clk_branch gcc_blsp1_qup4_spi_apps_clk = {
2050         .halt_reg = 0x0501c,
2051         .clkr = {
2052                 .enable_reg = 0x0501c,
2053                 .enable_mask = BIT(0),
2054                 .hw.init = &(struct clk_init_data){
2055                         .name = "gcc_blsp1_qup4_spi_apps_clk",
2056                         .parent_hws = (const struct clk_hw*[]){
2057                                 &blsp1_qup4_spi_apps_clk_src.clkr.hw,
2058                         },
2059                         .num_parents = 1,
2060                         .flags = CLK_SET_RATE_PARENT,
2061                         .ops = &clk_branch2_ops,
2062                 },
2063         },
2064 };
2065
2066 static struct clk_branch gcc_blsp1_qup5_i2c_apps_clk = {
2067         .halt_reg = 0x06020,
2068         .clkr = {
2069                 .enable_reg = 0x06020,
2070                 .enable_mask = BIT(0),
2071                 .hw.init = &(struct clk_init_data){
2072                         .name = "gcc_blsp1_qup5_i2c_apps_clk",
2073                         .parent_hws = (const struct clk_hw*[]){
2074                                 &blsp1_qup5_i2c_apps_clk_src.clkr.hw,
2075                         },
2076                         .num_parents = 1,
2077                         .flags = CLK_SET_RATE_PARENT,
2078                         .ops = &clk_branch2_ops,
2079                 },
2080         },
2081 };
2082
2083 static struct clk_branch gcc_blsp1_qup5_spi_apps_clk = {
2084         .halt_reg = 0x0601c,
2085         .clkr = {
2086                 .enable_reg = 0x0601c,
2087                 .enable_mask = BIT(0),
2088                 .hw.init = &(struct clk_init_data){
2089                         .name = "gcc_blsp1_qup5_spi_apps_clk",
2090                         .parent_hws = (const struct clk_hw*[]){
2091                                 &blsp1_qup5_spi_apps_clk_src.clkr.hw,
2092                         },
2093                         .num_parents = 1,
2094                         .flags = CLK_SET_RATE_PARENT,
2095                         .ops = &clk_branch2_ops,
2096                 },
2097         },
2098 };
2099
2100 static struct clk_branch gcc_blsp1_qup6_i2c_apps_clk = {
2101         .halt_reg = 0x07020,
2102         .clkr = {
2103                 .enable_reg = 0x07020,
2104                 .enable_mask = BIT(0),
2105                 .hw.init = &(struct clk_init_data){
2106                         .name = "gcc_blsp1_qup6_i2c_apps_clk",
2107                         .parent_hws = (const struct clk_hw*[]){
2108                                 &blsp1_qup6_i2c_apps_clk_src.clkr.hw,
2109                         },
2110                         .num_parents = 1,
2111                         .flags = CLK_SET_RATE_PARENT,
2112                         .ops = &clk_branch2_ops,
2113                 },
2114         },
2115 };
2116
2117 static struct clk_branch gcc_blsp1_qup6_spi_apps_clk = {
2118         .halt_reg = 0x0701c,
2119         .clkr = {
2120                 .enable_reg = 0x0701c,
2121                 .enable_mask = BIT(0),
2122                 .hw.init = &(struct clk_init_data){
2123                         .name = "gcc_blsp1_qup6_spi_apps_clk",
2124                         .parent_hws = (const struct clk_hw*[]){
2125                                 &blsp1_qup6_spi_apps_clk_src.clkr.hw,
2126                         },
2127                         .num_parents = 1,
2128                         .flags = CLK_SET_RATE_PARENT,
2129                         .ops = &clk_branch2_ops,
2130                 },
2131         },
2132 };
2133
2134 static struct clk_branch gcc_blsp1_uart1_apps_clk = {
2135         .halt_reg = 0x0203c,
2136         .clkr = {
2137                 .enable_reg = 0x0203c,
2138                 .enable_mask = BIT(0),
2139                 .hw.init = &(struct clk_init_data){
2140                         .name = "gcc_blsp1_uart1_apps_clk",
2141                         .parent_hws = (const struct clk_hw*[]){
2142                                 &blsp1_uart1_apps_clk_src.clkr.hw,
2143                         },
2144                         .num_parents = 1,
2145                         .flags = CLK_SET_RATE_PARENT,
2146                         .ops = &clk_branch2_ops,
2147                 },
2148         },
2149 };
2150
2151 static struct clk_branch gcc_blsp1_uart2_apps_clk = {
2152         .halt_reg = 0x0302c,
2153         .clkr = {
2154                 .enable_reg = 0x0302c,
2155                 .enable_mask = BIT(0),
2156                 .hw.init = &(struct clk_init_data){
2157                         .name = "gcc_blsp1_uart2_apps_clk",
2158                         .parent_hws = (const struct clk_hw*[]){
2159                                 &blsp1_uart2_apps_clk_src.clkr.hw,
2160                         },
2161                         .num_parents = 1,
2162                         .flags = CLK_SET_RATE_PARENT,
2163                         .ops = &clk_branch2_ops,
2164                 },
2165         },
2166 };
2167
2168 static struct clk_branch gcc_boot_rom_ahb_clk = {
2169         .halt_reg = 0x1300c,
2170         .halt_check = BRANCH_HALT_VOTED,
2171         .clkr = {
2172                 .enable_reg = 0x45004,
2173                 .enable_mask = BIT(7),
2174                 .hw.init = &(struct clk_init_data){
2175                         .name = "gcc_boot_rom_ahb_clk",
2176                         .parent_hws = (const struct clk_hw*[]){
2177                                 &pcnoc_bfdcd_clk_src.clkr.hw,
2178                         },
2179                         .num_parents = 1,
2180                         .ops = &clk_branch2_ops,
2181                 },
2182         },
2183 };
2184
2185 static struct clk_branch gcc_camss_cci_ahb_clk = {
2186         .halt_reg = 0x5101c,
2187         .clkr = {
2188                 .enable_reg = 0x5101c,
2189                 .enable_mask = BIT(0),
2190                 .hw.init = &(struct clk_init_data){
2191                         .name = "gcc_camss_cci_ahb_clk",
2192                         .parent_hws = (const struct clk_hw*[]){
2193                                 &camss_ahb_clk_src.clkr.hw,
2194                         },
2195                         .num_parents = 1,
2196                         .flags = CLK_SET_RATE_PARENT,
2197                         .ops = &clk_branch2_ops,
2198                 },
2199         },
2200 };
2201
2202 static struct clk_branch gcc_camss_cci_clk = {
2203         .halt_reg = 0x51018,
2204         .clkr = {
2205                 .enable_reg = 0x51018,
2206                 .enable_mask = BIT(0),
2207                 .hw.init = &(struct clk_init_data){
2208                         .name = "gcc_camss_cci_clk",
2209                         .parent_hws = (const struct clk_hw*[]){
2210                                 &cci_clk_src.clkr.hw,
2211                         },
2212                         .num_parents = 1,
2213                         .flags = CLK_SET_RATE_PARENT,
2214                         .ops = &clk_branch2_ops,
2215                 },
2216         },
2217 };
2218
2219 static struct clk_branch gcc_camss_csi0_ahb_clk = {
2220         .halt_reg = 0x4e040,
2221         .clkr = {
2222                 .enable_reg = 0x4e040,
2223                 .enable_mask = BIT(0),
2224                 .hw.init = &(struct clk_init_data){
2225                         .name = "gcc_camss_csi0_ahb_clk",
2226                         .parent_hws = (const struct clk_hw*[]){
2227                                 &camss_ahb_clk_src.clkr.hw,
2228                         },
2229                         .num_parents = 1,
2230                         .flags = CLK_SET_RATE_PARENT,
2231                         .ops = &clk_branch2_ops,
2232                 },
2233         },
2234 };
2235
2236 static struct clk_branch gcc_camss_csi0_clk = {
2237         .halt_reg = 0x4e03c,
2238         .clkr = {
2239                 .enable_reg = 0x4e03c,
2240                 .enable_mask = BIT(0),
2241                 .hw.init = &(struct clk_init_data){
2242                         .name = "gcc_camss_csi0_clk",
2243                         .parent_hws = (const struct clk_hw*[]){
2244                                 &csi0_clk_src.clkr.hw,
2245                         },
2246                         .num_parents = 1,
2247                         .flags = CLK_SET_RATE_PARENT,
2248                         .ops = &clk_branch2_ops,
2249                 },
2250         },
2251 };
2252
2253 static struct clk_branch gcc_camss_csi0phy_clk = {
2254         .halt_reg = 0x4e048,
2255         .clkr = {
2256                 .enable_reg = 0x4e048,
2257                 .enable_mask = BIT(0),
2258                 .hw.init = &(struct clk_init_data){
2259                         .name = "gcc_camss_csi0phy_clk",
2260                         .parent_hws = (const struct clk_hw*[]){
2261                                 &csi0_clk_src.clkr.hw,
2262                         },
2263                         .num_parents = 1,
2264                         .flags = CLK_SET_RATE_PARENT,
2265                         .ops = &clk_branch2_ops,
2266                 },
2267         },
2268 };
2269
2270 static struct clk_branch gcc_camss_csi0pix_clk = {
2271         .halt_reg = 0x4e058,
2272         .clkr = {
2273                 .enable_reg = 0x4e058,
2274                 .enable_mask = BIT(0),
2275                 .hw.init = &(struct clk_init_data){
2276                         .name = "gcc_camss_csi0pix_clk",
2277                         .parent_hws = (const struct clk_hw*[]){
2278                                 &csi0_clk_src.clkr.hw,
2279                         },
2280                         .num_parents = 1,
2281                         .flags = CLK_SET_RATE_PARENT,
2282                         .ops = &clk_branch2_ops,
2283                 },
2284         },
2285 };
2286
2287 static struct clk_branch gcc_camss_csi0rdi_clk = {
2288         .halt_reg = 0x4e050,
2289         .clkr = {
2290                 .enable_reg = 0x4e050,
2291                 .enable_mask = BIT(0),
2292                 .hw.init = &(struct clk_init_data){
2293                         .name = "gcc_camss_csi0rdi_clk",
2294                         .parent_hws = (const struct clk_hw*[]){
2295                                 &csi0_clk_src.clkr.hw,
2296                         },
2297                         .num_parents = 1,
2298                         .flags = CLK_SET_RATE_PARENT,
2299                         .ops = &clk_branch2_ops,
2300                 },
2301         },
2302 };
2303
2304 static struct clk_branch gcc_camss_csi1_ahb_clk = {
2305         .halt_reg = 0x4f040,
2306         .clkr = {
2307                 .enable_reg = 0x4f040,
2308                 .enable_mask = BIT(0),
2309                 .hw.init = &(struct clk_init_data){
2310                         .name = "gcc_camss_csi1_ahb_clk",
2311                         .parent_hws = (const struct clk_hw*[]){
2312                                 &camss_ahb_clk_src.clkr.hw,
2313                         },
2314                         .num_parents = 1,
2315                         .flags = CLK_SET_RATE_PARENT,
2316                         .ops = &clk_branch2_ops,
2317                 },
2318         },
2319 };
2320
2321 static struct clk_branch gcc_camss_csi1_clk = {
2322         .halt_reg = 0x4f03c,
2323         .clkr = {
2324                 .enable_reg = 0x4f03c,
2325                 .enable_mask = BIT(0),
2326                 .hw.init = &(struct clk_init_data){
2327                         .name = "gcc_camss_csi1_clk",
2328                         .parent_hws = (const struct clk_hw*[]){
2329                                 &csi1_clk_src.clkr.hw,
2330                         },
2331                         .num_parents = 1,
2332                         .flags = CLK_SET_RATE_PARENT,
2333                         .ops = &clk_branch2_ops,
2334                 },
2335         },
2336 };
2337
2338 static struct clk_branch gcc_camss_csi1phy_clk = {
2339         .halt_reg = 0x4f048,
2340         .clkr = {
2341                 .enable_reg = 0x4f048,
2342                 .enable_mask = BIT(0),
2343                 .hw.init = &(struct clk_init_data){
2344                         .name = "gcc_camss_csi1phy_clk",
2345                         .parent_hws = (const struct clk_hw*[]){
2346                                 &csi1_clk_src.clkr.hw,
2347                         },
2348                         .num_parents = 1,
2349                         .flags = CLK_SET_RATE_PARENT,
2350                         .ops = &clk_branch2_ops,
2351                 },
2352         },
2353 };
2354
2355 static struct clk_branch gcc_camss_csi1pix_clk = {
2356         .halt_reg = 0x4f058,
2357         .clkr = {
2358                 .enable_reg = 0x4f058,
2359                 .enable_mask = BIT(0),
2360                 .hw.init = &(struct clk_init_data){
2361                         .name = "gcc_camss_csi1pix_clk",
2362                         .parent_hws = (const struct clk_hw*[]){
2363                                 &csi1_clk_src.clkr.hw,
2364                         },
2365                         .num_parents = 1,
2366                         .flags = CLK_SET_RATE_PARENT,
2367                         .ops = &clk_branch2_ops,
2368                 },
2369         },
2370 };
2371
2372 static struct clk_branch gcc_camss_csi1rdi_clk = {
2373         .halt_reg = 0x4f050,
2374         .clkr = {
2375                 .enable_reg = 0x4f050,
2376                 .enable_mask = BIT(0),
2377                 .hw.init = &(struct clk_init_data){
2378                         .name = "gcc_camss_csi1rdi_clk",
2379                         .parent_hws = (const struct clk_hw*[]){
2380                                 &csi1_clk_src.clkr.hw,
2381                         },
2382                         .num_parents = 1,
2383                         .flags = CLK_SET_RATE_PARENT,
2384                         .ops = &clk_branch2_ops,
2385                 },
2386         },
2387 };
2388
2389 static struct clk_branch gcc_camss_csi_vfe0_clk = {
2390         .halt_reg = 0x58050,
2391         .clkr = {
2392                 .enable_reg = 0x58050,
2393                 .enable_mask = BIT(0),
2394                 .hw.init = &(struct clk_init_data){
2395                         .name = "gcc_camss_csi_vfe0_clk",
2396                         .parent_hws = (const struct clk_hw*[]){
2397                                 &vfe0_clk_src.clkr.hw,
2398                         },
2399                         .num_parents = 1,
2400                         .flags = CLK_SET_RATE_PARENT,
2401                         .ops = &clk_branch2_ops,
2402                 },
2403         },
2404 };
2405
2406 static struct clk_branch gcc_camss_gp0_clk = {
2407         .halt_reg = 0x54018,
2408         .clkr = {
2409                 .enable_reg = 0x54018,
2410                 .enable_mask = BIT(0),
2411                 .hw.init = &(struct clk_init_data){
2412                         .name = "gcc_camss_gp0_clk",
2413                         .parent_hws = (const struct clk_hw*[]){
2414                                 &camss_gp0_clk_src.clkr.hw,
2415                         },
2416                         .num_parents = 1,
2417                         .flags = CLK_SET_RATE_PARENT,
2418                         .ops = &clk_branch2_ops,
2419                 },
2420         },
2421 };
2422
2423 static struct clk_branch gcc_camss_gp1_clk = {
2424         .halt_reg = 0x55018,
2425         .clkr = {
2426                 .enable_reg = 0x55018,
2427                 .enable_mask = BIT(0),
2428                 .hw.init = &(struct clk_init_data){
2429                         .name = "gcc_camss_gp1_clk",
2430                         .parent_hws = (const struct clk_hw*[]){
2431                                 &camss_gp1_clk_src.clkr.hw,
2432                         },
2433                         .num_parents = 1,
2434                         .flags = CLK_SET_RATE_PARENT,
2435                         .ops = &clk_branch2_ops,
2436                 },
2437         },
2438 };
2439
2440 static struct clk_branch gcc_camss_ispif_ahb_clk = {
2441         .halt_reg = 0x50004,
2442         .clkr = {
2443                 .enable_reg = 0x50004,
2444                 .enable_mask = BIT(0),
2445                 .hw.init = &(struct clk_init_data){
2446                         .name = "gcc_camss_ispif_ahb_clk",
2447                         .parent_hws = (const struct clk_hw*[]){
2448                                 &camss_ahb_clk_src.clkr.hw,
2449                         },
2450                         .num_parents = 1,
2451                         .flags = CLK_SET_RATE_PARENT,
2452                         .ops = &clk_branch2_ops,
2453                 },
2454         },
2455 };
2456
2457 static struct clk_branch gcc_camss_jpeg0_clk = {
2458         .halt_reg = 0x57020,
2459         .clkr = {
2460                 .enable_reg = 0x57020,
2461                 .enable_mask = BIT(0),
2462                 .hw.init = &(struct clk_init_data){
2463                         .name = "gcc_camss_jpeg0_clk",
2464                         .parent_hws = (const struct clk_hw*[]){
2465                                 &jpeg0_clk_src.clkr.hw,
2466                         },
2467                         .num_parents = 1,
2468                         .flags = CLK_SET_RATE_PARENT,
2469                         .ops = &clk_branch2_ops,
2470                 },
2471         },
2472 };
2473
2474 static struct clk_branch gcc_camss_jpeg_ahb_clk = {
2475         .halt_reg = 0x57024,
2476         .clkr = {
2477                 .enable_reg = 0x57024,
2478                 .enable_mask = BIT(0),
2479                 .hw.init = &(struct clk_init_data){
2480                         .name = "gcc_camss_jpeg_ahb_clk",
2481                         .parent_hws = (const struct clk_hw*[]){
2482                                 &camss_ahb_clk_src.clkr.hw,
2483                         },
2484                         .num_parents = 1,
2485                         .flags = CLK_SET_RATE_PARENT,
2486                         .ops = &clk_branch2_ops,
2487                 },
2488         },
2489 };
2490
2491 static struct clk_branch gcc_camss_jpeg_axi_clk = {
2492         .halt_reg = 0x57028,
2493         .clkr = {
2494                 .enable_reg = 0x57028,
2495                 .enable_mask = BIT(0),
2496                 .hw.init = &(struct clk_init_data){
2497                         .name = "gcc_camss_jpeg_axi_clk",
2498                         .parent_hws = (const struct clk_hw*[]){
2499                                 &system_mm_noc_bfdcd_clk_src.clkr.hw,
2500                         },
2501                         .num_parents = 1,
2502                         .flags = CLK_SET_RATE_PARENT,
2503                         .ops = &clk_branch2_ops,
2504                 },
2505         },
2506 };
2507
2508 static struct clk_branch gcc_camss_mclk0_clk = {
2509         .halt_reg = 0x52018,
2510         .clkr = {
2511                 .enable_reg = 0x52018,
2512                 .enable_mask = BIT(0),
2513                 .hw.init = &(struct clk_init_data){
2514                         .name = "gcc_camss_mclk0_clk",
2515                         .parent_hws = (const struct clk_hw*[]){
2516                                 &mclk0_clk_src.clkr.hw,
2517                         },
2518                         .num_parents = 1,
2519                         .flags = CLK_SET_RATE_PARENT,
2520                         .ops = &clk_branch2_ops,
2521                 },
2522         },
2523 };
2524
2525 static struct clk_branch gcc_camss_mclk1_clk = {
2526         .halt_reg = 0x53018,
2527         .clkr = {
2528                 .enable_reg = 0x53018,
2529                 .enable_mask = BIT(0),
2530                 .hw.init = &(struct clk_init_data){
2531                         .name = "gcc_camss_mclk1_clk",
2532                         .parent_hws = (const struct clk_hw*[]){
2533                                 &mclk1_clk_src.clkr.hw,
2534                         },
2535                         .num_parents = 1,
2536                         .flags = CLK_SET_RATE_PARENT,
2537                         .ops = &clk_branch2_ops,
2538                 },
2539         },
2540 };
2541
2542 static struct clk_branch gcc_camss_micro_ahb_clk = {
2543         .halt_reg = 0x5600c,
2544         .clkr = {
2545                 .enable_reg = 0x5600c,
2546                 .enable_mask = BIT(0),
2547                 .hw.init = &(struct clk_init_data){
2548                         .name = "gcc_camss_micro_ahb_clk",
2549                         .parent_hws = (const struct clk_hw*[]){
2550                                 &camss_ahb_clk_src.clkr.hw,
2551                         },
2552                         .num_parents = 1,
2553                         .flags = CLK_SET_RATE_PARENT,
2554                         .ops = &clk_branch2_ops,
2555                 },
2556         },
2557 };
2558
2559 static struct clk_branch gcc_camss_csi0phytimer_clk = {
2560         .halt_reg = 0x4e01c,
2561         .clkr = {
2562                 .enable_reg = 0x4e01c,
2563                 .enable_mask = BIT(0),
2564                 .hw.init = &(struct clk_init_data){
2565                         .name = "gcc_camss_csi0phytimer_clk",
2566                         .parent_hws = (const struct clk_hw*[]){
2567                                 &csi0phytimer_clk_src.clkr.hw,
2568                         },
2569                         .num_parents = 1,
2570                         .flags = CLK_SET_RATE_PARENT,
2571                         .ops = &clk_branch2_ops,
2572                 },
2573         },
2574 };
2575
2576 static struct clk_branch gcc_camss_csi1phytimer_clk = {
2577         .halt_reg = 0x4f01c,
2578         .clkr = {
2579                 .enable_reg = 0x4f01c,
2580                 .enable_mask = BIT(0),
2581                 .hw.init = &(struct clk_init_data){
2582                         .name = "gcc_camss_csi1phytimer_clk",
2583                         .parent_hws = (const struct clk_hw*[]){
2584                                 &csi1phytimer_clk_src.clkr.hw,
2585                         },
2586                         .num_parents = 1,
2587                         .flags = CLK_SET_RATE_PARENT,
2588                         .ops = &clk_branch2_ops,
2589                 },
2590         },
2591 };
2592
2593 static struct clk_branch gcc_camss_ahb_clk = {
2594         .halt_reg = 0x5a014,
2595         .clkr = {
2596                 .enable_reg = 0x5a014,
2597                 .enable_mask = BIT(0),
2598                 .hw.init = &(struct clk_init_data){
2599                         .name = "gcc_camss_ahb_clk",
2600                         .parent_hws = (const struct clk_hw*[]){
2601                                 &camss_ahb_clk_src.clkr.hw,
2602                         },
2603                         .num_parents = 1,
2604                         .flags = CLK_SET_RATE_PARENT,
2605                         .ops = &clk_branch2_ops,
2606                 },
2607         },
2608 };
2609
2610 static struct clk_branch gcc_camss_top_ahb_clk = {
2611         .halt_reg = 0x56004,
2612         .clkr = {
2613                 .enable_reg = 0x56004,
2614                 .enable_mask = BIT(0),
2615                 .hw.init = &(struct clk_init_data){
2616                         .name = "gcc_camss_top_ahb_clk",
2617                         .parent_hws = (const struct clk_hw*[]){
2618                                 &pcnoc_bfdcd_clk_src.clkr.hw,
2619                         },
2620                         .num_parents = 1,
2621                         .flags = CLK_SET_RATE_PARENT,
2622                         .ops = &clk_branch2_ops,
2623                 },
2624         },
2625 };
2626
2627 static struct clk_branch gcc_camss_cpp_ahb_clk = {
2628         .halt_reg = 0x58040,
2629         .clkr = {
2630                 .enable_reg = 0x58040,
2631                 .enable_mask = BIT(0),
2632                 .hw.init = &(struct clk_init_data){
2633                         .name = "gcc_camss_cpp_ahb_clk",
2634                         .parent_hws = (const struct clk_hw*[]){
2635                                 &camss_ahb_clk_src.clkr.hw,
2636                         },
2637                         .num_parents = 1,
2638                         .flags = CLK_SET_RATE_PARENT,
2639                         .ops = &clk_branch2_ops,
2640                 },
2641         },
2642 };
2643
2644 static struct clk_branch gcc_camss_cpp_clk = {
2645         .halt_reg = 0x5803c,
2646         .clkr = {
2647                 .enable_reg = 0x5803c,
2648                 .enable_mask = BIT(0),
2649                 .hw.init = &(struct clk_init_data){
2650                         .name = "gcc_camss_cpp_clk",
2651                         .parent_hws = (const struct clk_hw*[]){
2652                                 &cpp_clk_src.clkr.hw,
2653                         },
2654                         .num_parents = 1,
2655                         .flags = CLK_SET_RATE_PARENT,
2656                         .ops = &clk_branch2_ops,
2657                 },
2658         },
2659 };
2660
2661 static struct clk_branch gcc_camss_vfe0_clk = {
2662         .halt_reg = 0x58038,
2663         .clkr = {
2664                 .enable_reg = 0x58038,
2665                 .enable_mask = BIT(0),
2666                 .hw.init = &(struct clk_init_data){
2667                         .name = "gcc_camss_vfe0_clk",
2668                         .parent_hws = (const struct clk_hw*[]){
2669                                 &vfe0_clk_src.clkr.hw,
2670                         },
2671                         .num_parents = 1,
2672                         .flags = CLK_SET_RATE_PARENT,
2673                         .ops = &clk_branch2_ops,
2674                 },
2675         },
2676 };
2677
2678 static struct clk_branch gcc_camss_vfe_ahb_clk = {
2679         .halt_reg = 0x58044,
2680         .clkr = {
2681                 .enable_reg = 0x58044,
2682                 .enable_mask = BIT(0),
2683                 .hw.init = &(struct clk_init_data){
2684                         .name = "gcc_camss_vfe_ahb_clk",
2685                         .parent_hws = (const struct clk_hw*[]){
2686                                 &camss_ahb_clk_src.clkr.hw,
2687                         },
2688                         .num_parents = 1,
2689                         .flags = CLK_SET_RATE_PARENT,
2690                         .ops = &clk_branch2_ops,
2691                 },
2692         },
2693 };
2694
2695 static struct clk_branch gcc_camss_vfe_axi_clk = {
2696         .halt_reg = 0x58048,
2697         .clkr = {
2698                 .enable_reg = 0x58048,
2699                 .enable_mask = BIT(0),
2700                 .hw.init = &(struct clk_init_data){
2701                         .name = "gcc_camss_vfe_axi_clk",
2702                         .parent_hws = (const struct clk_hw*[]){
2703                                 &system_mm_noc_bfdcd_clk_src.clkr.hw,
2704                         },
2705                         .num_parents = 1,
2706                         .flags = CLK_SET_RATE_PARENT,
2707                         .ops = &clk_branch2_ops,
2708                 },
2709         },
2710 };
2711
2712 static struct clk_branch gcc_crypto_ahb_clk = {
2713         .halt_reg = 0x16024,
2714         .halt_check = BRANCH_HALT_VOTED,
2715         .clkr = {
2716                 .enable_reg = 0x45004,
2717                 .enable_mask = BIT(0),
2718                 .hw.init = &(struct clk_init_data){
2719                         .name = "gcc_crypto_ahb_clk",
2720                         .parent_hws = (const struct clk_hw*[]){
2721                                 &pcnoc_bfdcd_clk_src.clkr.hw,
2722                         },
2723                         .num_parents = 1,
2724                         .flags = CLK_SET_RATE_PARENT,
2725                         .ops = &clk_branch2_ops,
2726                 },
2727         },
2728 };
2729
2730 static struct clk_branch gcc_crypto_axi_clk = {
2731         .halt_reg = 0x16020,
2732         .halt_check = BRANCH_HALT_VOTED,
2733         .clkr = {
2734                 .enable_reg = 0x45004,
2735                 .enable_mask = BIT(1),
2736                 .hw.init = &(struct clk_init_data){
2737                         .name = "gcc_crypto_axi_clk",
2738                         .parent_hws = (const struct clk_hw*[]){
2739                                 &pcnoc_bfdcd_clk_src.clkr.hw,
2740                         },
2741                         .num_parents = 1,
2742                         .flags = CLK_SET_RATE_PARENT,
2743                         .ops = &clk_branch2_ops,
2744                 },
2745         },
2746 };
2747
2748 static struct clk_branch gcc_crypto_clk = {
2749         .halt_reg = 0x1601c,
2750         .halt_check = BRANCH_HALT_VOTED,
2751         .clkr = {
2752                 .enable_reg = 0x45004,
2753                 .enable_mask = BIT(2),
2754                 .hw.init = &(struct clk_init_data){
2755                         .name = "gcc_crypto_clk",
2756                         .parent_hws = (const struct clk_hw*[]){
2757                                 &crypto_clk_src.clkr.hw,
2758                         },
2759                         .num_parents = 1,
2760                         .flags = CLK_SET_RATE_PARENT,
2761                         .ops = &clk_branch2_ops,
2762                 },
2763         },
2764 };
2765
2766 static struct clk_branch gcc_oxili_gmem_clk = {
2767         .halt_reg = 0x59024,
2768         .clkr = {
2769                 .enable_reg = 0x59024,
2770                 .enable_mask = BIT(0),
2771                 .hw.init = &(struct clk_init_data){
2772                         .name = "gcc_oxili_gmem_clk",
2773                         .parent_hws = (const struct clk_hw*[]){
2774                                 &gfx3d_clk_src.clkr.hw,
2775                         },
2776                         .num_parents = 1,
2777                         .flags = CLK_SET_RATE_PARENT,
2778                         .ops = &clk_branch2_ops,
2779                 },
2780         },
2781 };
2782
2783 static struct clk_branch gcc_gp1_clk = {
2784         .halt_reg = 0x08000,
2785         .clkr = {
2786                 .enable_reg = 0x08000,
2787                 .enable_mask = BIT(0),
2788                 .hw.init = &(struct clk_init_data){
2789                         .name = "gcc_gp1_clk",
2790                         .parent_hws = (const struct clk_hw*[]){
2791                                 &gp1_clk_src.clkr.hw,
2792                         },
2793                         .num_parents = 1,
2794                         .flags = CLK_SET_RATE_PARENT,
2795                         .ops = &clk_branch2_ops,
2796                 },
2797         },
2798 };
2799
2800 static struct clk_branch gcc_gp2_clk = {
2801         .halt_reg = 0x09000,
2802         .clkr = {
2803                 .enable_reg = 0x09000,
2804                 .enable_mask = BIT(0),
2805                 .hw.init = &(struct clk_init_data){
2806                         .name = "gcc_gp2_clk",
2807                         .parent_hws = (const struct clk_hw*[]){
2808                                 &gp2_clk_src.clkr.hw,
2809                         },
2810                         .num_parents = 1,
2811                         .flags = CLK_SET_RATE_PARENT,
2812                         .ops = &clk_branch2_ops,
2813                 },
2814         },
2815 };
2816
2817 static struct clk_branch gcc_gp3_clk = {
2818         .halt_reg = 0x0a000,
2819         .clkr = {
2820                 .enable_reg = 0x0a000,
2821                 .enable_mask = BIT(0),
2822                 .hw.init = &(struct clk_init_data){
2823                         .name = "gcc_gp3_clk",
2824                         .parent_hws = (const struct clk_hw*[]){
2825                                 &gp3_clk_src.clkr.hw,
2826                         },
2827                         .num_parents = 1,
2828                         .flags = CLK_SET_RATE_PARENT,
2829                         .ops = &clk_branch2_ops,
2830                 },
2831         },
2832 };
2833
2834 static struct clk_branch gcc_mdss_ahb_clk = {
2835         .halt_reg = 0x4d07c,
2836         .clkr = {
2837                 .enable_reg = 0x4d07c,
2838                 .enable_mask = BIT(0),
2839                 .hw.init = &(struct clk_init_data){
2840                         .name = "gcc_mdss_ahb_clk",
2841                         .parent_hws = (const struct clk_hw*[]){
2842                                 &pcnoc_bfdcd_clk_src.clkr.hw,
2843                         },
2844                         .num_parents = 1,
2845                         .flags = CLK_SET_RATE_PARENT,
2846                         .ops = &clk_branch2_ops,
2847                 },
2848         },
2849 };
2850
2851 static struct clk_branch gcc_mdss_axi_clk = {
2852         .halt_reg = 0x4d080,
2853         .clkr = {
2854                 .enable_reg = 0x4d080,
2855                 .enable_mask = BIT(0),
2856                 .hw.init = &(struct clk_init_data){
2857                         .name = "gcc_mdss_axi_clk",
2858                         .parent_hws = (const struct clk_hw*[]){
2859                                 &system_mm_noc_bfdcd_clk_src.clkr.hw,
2860                         },
2861                         .num_parents = 1,
2862                         .flags = CLK_SET_RATE_PARENT,
2863                         .ops = &clk_branch2_ops,
2864                 },
2865         },
2866 };
2867
2868 static struct clk_branch gcc_mdss_byte0_clk = {
2869         .halt_reg = 0x4d094,
2870         .clkr = {
2871                 .enable_reg = 0x4d094,
2872                 .enable_mask = BIT(0),
2873                 .hw.init = &(struct clk_init_data){
2874                         .name = "gcc_mdss_byte0_clk",
2875                         .parent_hws = (const struct clk_hw*[]){
2876                                 &byte0_clk_src.clkr.hw,
2877                         },
2878                         .num_parents = 1,
2879                         .flags = CLK_SET_RATE_PARENT,
2880                         .ops = &clk_branch2_ops,
2881                 },
2882         },
2883 };
2884
2885 static struct clk_branch gcc_mdss_byte1_clk = {
2886         .halt_reg = 0x4d0a0,
2887         .clkr = {
2888                 .enable_reg = 0x4d0a0,
2889                 .enable_mask = BIT(0),
2890                 .hw.init = &(struct clk_init_data){
2891                         .name = "gcc_mdss_byte1_clk",
2892                         .parent_hws = (const struct clk_hw*[]){
2893                                 &byte1_clk_src.clkr.hw,
2894                         },
2895                         .num_parents = 1,
2896                         .flags = CLK_SET_RATE_PARENT,
2897                         .ops = &clk_branch2_ops,
2898                 },
2899         },
2900 };
2901
2902 static struct clk_branch gcc_mdss_esc0_clk = {
2903         .halt_reg = 0x4d098,
2904         .clkr = {
2905                 .enable_reg = 0x4d098,
2906                 .enable_mask = BIT(0),
2907                 .hw.init = &(struct clk_init_data){
2908                         .name = "gcc_mdss_esc0_clk",
2909                         .parent_hws = (const struct clk_hw*[]){
2910                                 &esc0_clk_src.clkr.hw,
2911                         },
2912                         .num_parents = 1,
2913                         .flags = CLK_SET_RATE_PARENT,
2914                         .ops = &clk_branch2_ops,
2915                 },
2916         },
2917 };
2918
2919 static struct clk_branch gcc_mdss_esc1_clk = {
2920         .halt_reg = 0x4d09c,
2921         .clkr = {
2922                 .enable_reg = 0x4d09c,
2923                 .enable_mask = BIT(0),
2924                 .hw.init = &(struct clk_init_data){
2925                         .name = "gcc_mdss_esc1_clk",
2926                         .parent_hws = (const struct clk_hw*[]){
2927                                 &esc1_clk_src.clkr.hw,
2928                         },
2929                         .num_parents = 1,
2930                         .flags = CLK_SET_RATE_PARENT,
2931                         .ops = &clk_branch2_ops,
2932                 },
2933         },
2934 };
2935
2936 static struct clk_branch gcc_mdss_mdp_clk = {
2937         .halt_reg = 0x4D088,
2938         .clkr = {
2939                 .enable_reg = 0x4D088,
2940                 .enable_mask = BIT(0),
2941                 .hw.init = &(struct clk_init_data){
2942                         .name = "gcc_mdss_mdp_clk",
2943                         .parent_hws = (const struct clk_hw*[]){
2944                                 &mdp_clk_src.clkr.hw,
2945                         },
2946                         .num_parents = 1,
2947                         .flags = CLK_SET_RATE_PARENT,
2948                         .ops = &clk_branch2_ops,
2949                 },
2950         },
2951 };
2952
2953 static struct clk_branch gcc_mdss_pclk0_clk = {
2954         .halt_reg = 0x4d084,
2955         .clkr = {
2956                 .enable_reg = 0x4d084,
2957                 .enable_mask = BIT(0),
2958                 .hw.init = &(struct clk_init_data){
2959                         .name = "gcc_mdss_pclk0_clk",
2960                         .parent_hws = (const struct clk_hw*[]){
2961                                 &pclk0_clk_src.clkr.hw,
2962                         },
2963                         .num_parents = 1,
2964                         .flags = CLK_SET_RATE_PARENT,
2965                         .ops = &clk_branch2_ops,
2966                 },
2967         },
2968 };
2969
2970 static struct clk_branch gcc_mdss_pclk1_clk = {
2971         .halt_reg = 0x4d0a4,
2972         .clkr = {
2973                 .enable_reg = 0x4d0a4,
2974                 .enable_mask = BIT(0),
2975                 .hw.init = &(struct clk_init_data){
2976                         .name = "gcc_mdss_pclk1_clk",
2977                         .parent_hws = (const struct clk_hw*[]){
2978                                 &pclk1_clk_src.clkr.hw,
2979                         },
2980                         .num_parents = 1,
2981                         .flags = CLK_SET_RATE_PARENT,
2982                         .ops = &clk_branch2_ops,
2983                 },
2984         },
2985 };
2986
2987 static struct clk_branch gcc_mdss_vsync_clk = {
2988         .halt_reg = 0x4d090,
2989         .clkr = {
2990                 .enable_reg = 0x4d090,
2991                 .enable_mask = BIT(0),
2992                 .hw.init = &(struct clk_init_data){
2993                         .name = "gcc_mdss_vsync_clk",
2994                         .parent_hws = (const struct clk_hw*[]){
2995                                 &vsync_clk_src.clkr.hw,
2996                         },
2997                         .num_parents = 1,
2998                         .flags = CLK_SET_RATE_PARENT,
2999                         .ops = &clk_branch2_ops,
3000                 },
3001         },
3002 };
3003
3004 static struct clk_branch gcc_mss_cfg_ahb_clk = {
3005         .halt_reg = 0x49000,
3006         .clkr = {
3007                 .enable_reg = 0x49000,
3008                 .enable_mask = BIT(0),
3009                 .hw.init = &(struct clk_init_data){
3010                         .name = "gcc_mss_cfg_ahb_clk",
3011                         .parent_hws = (const struct clk_hw*[]){
3012                                 &pcnoc_bfdcd_clk_src.clkr.hw,
3013                         },
3014                         .num_parents = 1,
3015                         .flags = CLK_SET_RATE_PARENT,
3016                         .ops = &clk_branch2_ops,
3017                 },
3018         },
3019 };
3020
3021 static struct clk_branch gcc_mss_q6_bimc_axi_clk = {
3022         .halt_reg = 0x49004,
3023         .clkr = {
3024                 .enable_reg = 0x49004,
3025                 .enable_mask = BIT(0),
3026                 .hw.init = &(struct clk_init_data){
3027                         .name = "gcc_mss_q6_bimc_axi_clk",
3028                         .parent_hws = (const struct clk_hw*[]){
3029                                 &bimc_ddr_clk_src.clkr.hw,
3030                         },
3031                         .num_parents = 1,
3032                         .flags = CLK_SET_RATE_PARENT,
3033                         .ops = &clk_branch2_ops,
3034                 },
3035         },
3036 };
3037
3038 static struct clk_branch gcc_oxili_ahb_clk = {
3039         .halt_reg = 0x59028,
3040         .clkr = {
3041                 .enable_reg = 0x59028,
3042                 .enable_mask = BIT(0),
3043                 .hw.init = &(struct clk_init_data){
3044                         .name = "gcc_oxili_ahb_clk",
3045                         .parent_hws = (const struct clk_hw*[]){
3046                                 &pcnoc_bfdcd_clk_src.clkr.hw,
3047                         },
3048                         .num_parents = 1,
3049                         .flags = CLK_SET_RATE_PARENT,
3050                         .ops = &clk_branch2_ops,
3051                 },
3052         },
3053 };
3054
3055 static struct clk_branch gcc_oxili_gfx3d_clk = {
3056         .halt_reg = 0x59020,
3057         .clkr = {
3058                 .enable_reg = 0x59020,
3059                 .enable_mask = BIT(0),
3060                 .hw.init = &(struct clk_init_data){
3061                         .name = "gcc_oxili_gfx3d_clk",
3062                         .parent_hws = (const struct clk_hw*[]){
3063                                 &gfx3d_clk_src.clkr.hw,
3064                         },
3065                         .num_parents = 1,
3066                         .flags = CLK_SET_RATE_PARENT,
3067                         .ops = &clk_branch2_ops,
3068                 },
3069         },
3070 };
3071
3072 static struct clk_branch gcc_pdm2_clk = {
3073         .halt_reg = 0x4400c,
3074         .clkr = {
3075                 .enable_reg = 0x4400c,
3076                 .enable_mask = BIT(0),
3077                 .hw.init = &(struct clk_init_data){
3078                         .name = "gcc_pdm2_clk",
3079                         .parent_hws = (const struct clk_hw*[]){
3080                                 &pdm2_clk_src.clkr.hw,
3081                         },
3082                         .num_parents = 1,
3083                         .flags = CLK_SET_RATE_PARENT,
3084                         .ops = &clk_branch2_ops,
3085                 },
3086         },
3087 };
3088
3089 static struct clk_branch gcc_pdm_ahb_clk = {
3090         .halt_reg = 0x44004,
3091         .clkr = {
3092                 .enable_reg = 0x44004,
3093                 .enable_mask = BIT(0),
3094                 .hw.init = &(struct clk_init_data){
3095                         .name = "gcc_pdm_ahb_clk",
3096                         .parent_hws = (const struct clk_hw*[]){
3097                                 &pcnoc_bfdcd_clk_src.clkr.hw,
3098                         },
3099                         .num_parents = 1,
3100                         .flags = CLK_SET_RATE_PARENT,
3101                         .ops = &clk_branch2_ops,
3102                 },
3103         },
3104 };
3105
3106 static struct clk_branch gcc_prng_ahb_clk = {
3107         .halt_reg = 0x13004,
3108         .halt_check = BRANCH_HALT_VOTED,
3109         .clkr = {
3110                 .enable_reg = 0x45004,
3111                 .enable_mask = BIT(8),
3112                 .hw.init = &(struct clk_init_data){
3113                         .name = "gcc_prng_ahb_clk",
3114                         .parent_hws = (const struct clk_hw*[]){
3115                                 &pcnoc_bfdcd_clk_src.clkr.hw,
3116                         },
3117                         .num_parents = 1,
3118                         .ops = &clk_branch2_ops,
3119                 },
3120         },
3121 };
3122
3123 static struct clk_branch gcc_sdcc1_ahb_clk = {
3124         .halt_reg = 0x4201c,
3125         .clkr = {
3126                 .enable_reg = 0x4201c,
3127                 .enable_mask = BIT(0),
3128                 .hw.init = &(struct clk_init_data){
3129                         .name = "gcc_sdcc1_ahb_clk",
3130                         .parent_hws = (const struct clk_hw*[]){
3131                                 &pcnoc_bfdcd_clk_src.clkr.hw,
3132                         },
3133                         .num_parents = 1,
3134                         .flags = CLK_SET_RATE_PARENT,
3135                         .ops = &clk_branch2_ops,
3136                 },
3137         },
3138 };
3139
3140 static struct clk_branch gcc_sdcc1_apps_clk = {
3141         .halt_reg = 0x42018,
3142         .clkr = {
3143                 .enable_reg = 0x42018,
3144                 .enable_mask = BIT(0),
3145                 .hw.init = &(struct clk_init_data){
3146                         .name = "gcc_sdcc1_apps_clk",
3147                         .parent_hws = (const struct clk_hw*[]){
3148                                 &sdcc1_apps_clk_src.clkr.hw,
3149                         },
3150                         .num_parents = 1,
3151                         .flags = CLK_SET_RATE_PARENT,
3152                         .ops = &clk_branch2_ops,
3153                 },
3154         },
3155 };
3156
3157 static struct clk_branch gcc_sdcc2_ahb_clk = {
3158         .halt_reg = 0x4301c,
3159         .clkr = {
3160                 .enable_reg = 0x4301c,
3161                 .enable_mask = BIT(0),
3162                 .hw.init = &(struct clk_init_data){
3163                         .name = "gcc_sdcc2_ahb_clk",
3164                         .parent_hws = (const struct clk_hw*[]){
3165                                 &pcnoc_bfdcd_clk_src.clkr.hw,
3166                         },
3167                         .num_parents = 1,
3168                         .flags = CLK_SET_RATE_PARENT,
3169                         .ops = &clk_branch2_ops,
3170                 },
3171         },
3172 };
3173
3174 static struct clk_branch gcc_sdcc2_apps_clk = {
3175         .halt_reg = 0x43018,
3176         .clkr = {
3177                 .enable_reg = 0x43018,
3178                 .enable_mask = BIT(0),
3179                 .hw.init = &(struct clk_init_data){
3180                         .name = "gcc_sdcc2_apps_clk",
3181                         .parent_hws = (const struct clk_hw*[]){
3182                                 &sdcc2_apps_clk_src.clkr.hw,
3183                         },
3184                         .num_parents = 1,
3185                         .flags = CLK_SET_RATE_PARENT,
3186                         .ops = &clk_branch2_ops,
3187                 },
3188         },
3189 };
3190
3191 static struct clk_branch gcc_apss_tcu_clk = {
3192         .halt_reg = 0x12018,
3193         .halt_check = BRANCH_HALT_VOTED,
3194         .clkr = {
3195                 .enable_reg = 0x4500c,
3196                 .enable_mask = BIT(1),
3197                 .hw.init = &(struct clk_init_data){
3198                         .name = "gcc_apss_tcu_clk",
3199                         .parent_hws = (const struct clk_hw*[]){
3200                                 &bimc_ddr_clk_src.clkr.hw,
3201                         },
3202                         .num_parents = 1,
3203                         .ops = &clk_branch2_ops,
3204                 },
3205         },
3206 };
3207
3208 static struct clk_branch gcc_gfx_tcu_clk = {
3209         .halt_reg = 0x12020,
3210         .halt_check = BRANCH_HALT_VOTED,
3211         .clkr = {
3212                 .enable_reg = 0x4500c,
3213                 .enable_mask = BIT(2),
3214                 .hw.init = &(struct clk_init_data){
3215                         .name = "gcc_gfx_tcu_clk",
3216                         .parent_hws = (const struct clk_hw*[]){
3217                                 &bimc_ddr_clk_src.clkr.hw,
3218                         },
3219                         .num_parents = 1,
3220                         .ops = &clk_branch2_ops,
3221                 },
3222         },
3223 };
3224
3225 static struct clk_branch gcc_gfx_tbu_clk = {
3226         .halt_reg = 0x12010,
3227         .halt_check = BRANCH_HALT_VOTED,
3228         .clkr = {
3229                 .enable_reg = 0x4500c,
3230                 .enable_mask = BIT(3),
3231                 .hw.init = &(struct clk_init_data){
3232                         .name = "gcc_gfx_tbu_clk",
3233                         .parent_hws = (const struct clk_hw*[]){
3234                                 &bimc_ddr_clk_src.clkr.hw,
3235                         },
3236                         .num_parents = 1,
3237                         .ops = &clk_branch2_ops,
3238                 },
3239         },
3240 };
3241
3242 static struct clk_branch gcc_mdp_tbu_clk = {
3243         .halt_reg = 0x1201c,
3244         .halt_check = BRANCH_HALT_VOTED,
3245         .clkr = {
3246                 .enable_reg = 0x4500c,
3247                 .enable_mask = BIT(4),
3248                 .hw.init = &(struct clk_init_data){
3249                         .name = "gcc_mdp_tbu_clk",
3250                         .parent_hws = (const struct clk_hw*[]){
3251                                 &system_mm_noc_bfdcd_clk_src.clkr.hw,
3252                         },
3253                         .num_parents = 1,
3254                         .flags = CLK_SET_RATE_PARENT,
3255                         .ops = &clk_branch2_ops,
3256                 },
3257         },
3258 };
3259
3260 static struct clk_branch gcc_venus_tbu_clk = {
3261         .halt_reg = 0x12014,
3262         .halt_check = BRANCH_HALT_VOTED,
3263         .clkr = {
3264                 .enable_reg = 0x4500c,
3265                 .enable_mask = BIT(5),
3266                 .hw.init = &(struct clk_init_data){
3267                         .name = "gcc_venus_tbu_clk",
3268                         .parent_hws = (const struct clk_hw*[]){
3269                                 &system_mm_noc_bfdcd_clk_src.clkr.hw,
3270                         },
3271                         .num_parents = 1,
3272                         .flags = CLK_SET_RATE_PARENT,
3273                         .ops = &clk_branch2_ops,
3274                 },
3275         },
3276 };
3277
3278 static struct clk_branch gcc_vfe_tbu_clk = {
3279         .halt_reg = 0x1203c,
3280         .halt_check = BRANCH_HALT_VOTED,
3281         .clkr = {
3282                 .enable_reg = 0x4500c,
3283                 .enable_mask = BIT(9),
3284                 .hw.init = &(struct clk_init_data){
3285                         .name = "gcc_vfe_tbu_clk",
3286                         .parent_hws = (const struct clk_hw*[]){
3287                                 &system_mm_noc_bfdcd_clk_src.clkr.hw,
3288                         },
3289                         .num_parents = 1,
3290                         .flags = CLK_SET_RATE_PARENT,
3291                         .ops = &clk_branch2_ops,
3292                 },
3293         },
3294 };
3295
3296 static struct clk_branch gcc_jpeg_tbu_clk = {
3297         .halt_reg = 0x12034,
3298         .halt_check = BRANCH_HALT_VOTED,
3299         .clkr = {
3300                 .enable_reg = 0x4500c,
3301                 .enable_mask = BIT(10),
3302                 .hw.init = &(struct clk_init_data){
3303                         .name = "gcc_jpeg_tbu_clk",
3304                         .parent_hws = (const struct clk_hw*[]){
3305                                 &system_mm_noc_bfdcd_clk_src.clkr.hw,
3306                         },
3307                         .num_parents = 1,
3308                         .flags = CLK_SET_RATE_PARENT,
3309                         .ops = &clk_branch2_ops,
3310                 },
3311         },
3312 };
3313
3314 static struct clk_branch gcc_smmu_cfg_clk = {
3315         .halt_reg = 0x12038,
3316         .halt_check = BRANCH_HALT_VOTED,
3317         .clkr = {
3318                 .enable_reg = 0x4500c,
3319                 .enable_mask = BIT(12),
3320                 .hw.init = &(struct clk_init_data){
3321                         .name = "gcc_smmu_cfg_clk",
3322                         .parent_hws = (const struct clk_hw*[]){
3323                                 &pcnoc_bfdcd_clk_src.clkr.hw,
3324                         },
3325                         .num_parents = 1,
3326                         .flags = CLK_SET_RATE_PARENT,
3327                         .ops = &clk_branch2_ops,
3328                 },
3329         },
3330 };
3331
3332 static struct clk_branch gcc_gtcu_ahb_clk = {
3333         .halt_reg = 0x12044,
3334         .halt_check = BRANCH_HALT_VOTED,
3335         .clkr = {
3336                 .enable_reg = 0x4500c,
3337                 .enable_mask = BIT(13),
3338                 .hw.init = &(struct clk_init_data){
3339                         .name = "gcc_gtcu_ahb_clk",
3340                         .parent_hws = (const struct clk_hw*[]){
3341                                 &pcnoc_bfdcd_clk_src.clkr.hw,
3342                         },
3343                         .num_parents = 1,
3344                         .flags = CLK_SET_RATE_PARENT,
3345                         .ops = &clk_branch2_ops,
3346                 },
3347         },
3348 };
3349
3350 static struct clk_branch gcc_cpp_tbu_clk = {
3351         .halt_reg = 0x12040,
3352         .halt_check = BRANCH_HALT_VOTED,
3353         .clkr = {
3354                 .enable_reg = 0x4500c,
3355                 .enable_mask = BIT(14),
3356                 .hw.init = &(struct clk_init_data){
3357                         .name = "gcc_cpp_tbu_clk",
3358                         .parent_hws = (const struct clk_hw*[]){
3359                                 &pcnoc_bfdcd_clk_src.clkr.hw,
3360                         },
3361                         .num_parents = 1,
3362                         .flags = CLK_SET_RATE_PARENT,
3363                         .ops = &clk_branch2_ops,
3364                 },
3365         },
3366 };
3367
3368 static struct clk_branch gcc_mdp_rt_tbu_clk = {
3369         .halt_reg = 0x1201c,
3370         .halt_check = BRANCH_HALT_VOTED,
3371         .clkr = {
3372                 .enable_reg = 0x4500c,
3373                 .enable_mask = BIT(15),
3374                 .hw.init = &(struct clk_init_data){
3375                         .name = "gcc_mdp_rt_tbu_clk",
3376                         .parent_hws = (const struct clk_hw*[]){
3377                                 &pcnoc_bfdcd_clk_src.clkr.hw,
3378                         },
3379                         .num_parents = 1,
3380                         .flags = CLK_SET_RATE_PARENT,
3381                         .ops = &clk_branch2_ops,
3382                 },
3383         },
3384 };
3385
3386 static struct clk_branch gcc_bimc_gfx_clk = {
3387         .halt_reg = 0x31024,
3388         .clkr = {
3389                 .enable_reg = 0x31024,
3390                 .enable_mask = BIT(0),
3391                 .hw.init = &(struct clk_init_data){
3392                         .name = "gcc_bimc_gfx_clk",
3393                         .parent_hws = (const struct clk_hw*[]){
3394                                 &bimc_gpu_clk_src.clkr.hw,
3395                         },
3396                         .num_parents = 1,
3397                         .flags = CLK_SET_RATE_PARENT,
3398                         .ops = &clk_branch2_ops,
3399                 },
3400         },
3401 };
3402
3403 static struct clk_branch gcc_bimc_gpu_clk = {
3404         .halt_reg = 0x31040,
3405         .clkr = {
3406                 .enable_reg = 0x31040,
3407                 .enable_mask = BIT(0),
3408                 .hw.init = &(struct clk_init_data){
3409                         .name = "gcc_bimc_gpu_clk",
3410                         .parent_hws = (const struct clk_hw*[]){
3411                                 &bimc_gpu_clk_src.clkr.hw,
3412                         },
3413                         .num_parents = 1,
3414                         .flags = CLK_SET_RATE_PARENT,
3415                         .ops = &clk_branch2_ops,
3416                 },
3417         },
3418 };
3419
3420 static struct clk_branch gcc_usb2a_phy_sleep_clk = {
3421         .halt_reg = 0x4102c,
3422         .clkr = {
3423                 .enable_reg = 0x4102c,
3424                 .enable_mask = BIT(0),
3425                 .hw.init = &(struct clk_init_data){
3426                         .name = "gcc_usb2a_phy_sleep_clk",
3427                         .ops = &clk_branch2_ops,
3428                 },
3429         },
3430 };
3431
3432 static struct clk_branch gcc_usb_fs_ahb_clk = {
3433         .halt_reg = 0x3f008,
3434         .clkr = {
3435                 .enable_reg = 0x3f008,
3436                 .enable_mask = BIT(0),
3437                 .hw.init = &(struct clk_init_data){
3438                         .name = "gcc_usb_fs_ahb_clk",
3439                         .parent_hws = (const struct clk_hw*[]){
3440                                 &pcnoc_bfdcd_clk_src.clkr.hw,
3441                         },
3442                         .num_parents = 1,
3443                         .flags = CLK_SET_RATE_PARENT,
3444                         .ops = &clk_branch2_ops,
3445                 },
3446         },
3447 };
3448
3449 static struct clk_branch gcc_usb_fs_ic_clk = {
3450         .halt_reg = 0x3f030,
3451         .clkr = {
3452                 .enable_reg = 0x3f030,
3453                 .enable_mask = BIT(0),
3454                 .hw.init = &(struct clk_init_data){
3455                         .name = "gcc_usb_fs_ic_clk",
3456                         .parent_hws = (const struct clk_hw*[]){
3457                                 &usb_fs_ic_clk_src.clkr.hw,
3458                         },
3459                         .num_parents = 1,
3460                         .flags = CLK_SET_RATE_PARENT,
3461                         .ops = &clk_branch2_ops,
3462                 },
3463         },
3464 };
3465
3466 static struct clk_branch gcc_usb_fs_system_clk = {
3467         .halt_reg = 0x3f004,
3468         .clkr = {
3469                 .enable_reg = 0x3f004,
3470                 .enable_mask = BIT(0),
3471                 .hw.init = &(struct clk_init_data){
3472                         .name = "gcc_usb_fs_system_clk",
3473                         .parent_hws = (const struct clk_hw*[]){
3474                                 &usb_fs_system_clk_src.clkr.hw,
3475                         },
3476                         .num_parents = 1,
3477                         .flags = CLK_SET_RATE_PARENT,
3478                         .ops = &clk_branch2_ops,
3479                 },
3480         },
3481 };
3482
3483 static struct clk_branch gcc_usb_hs_ahb_clk = {
3484         .halt_reg = 0x41008,
3485         .clkr = {
3486                 .enable_reg = 0x41008,
3487                 .enable_mask = BIT(0),
3488                 .hw.init = &(struct clk_init_data){
3489                         .name = "gcc_usb_hs_ahb_clk",
3490                         .parent_hws = (const struct clk_hw*[]){
3491                                 &pcnoc_bfdcd_clk_src.clkr.hw,
3492                         },
3493                         .num_parents = 1,
3494                         .flags = CLK_SET_RATE_PARENT,
3495                         .ops = &clk_branch2_ops,
3496                 },
3497         },
3498 };
3499
3500 static struct clk_branch gcc_usb_hs_system_clk = {
3501         .halt_reg = 0x41004,
3502         .clkr = {
3503                 .enable_reg = 0x41004,
3504                 .enable_mask = BIT(0),
3505                 .hw.init = &(struct clk_init_data){
3506                         .name = "gcc_usb_hs_system_clk",
3507                         .parent_hws = (const struct clk_hw*[]){
3508                                 &usb_hs_system_clk_src.clkr.hw,
3509                         },
3510                         .num_parents = 1,
3511                         .flags = CLK_SET_RATE_PARENT,
3512                         .ops = &clk_branch2_ops,
3513                 },
3514         },
3515 };
3516
3517 static struct clk_branch gcc_venus0_ahb_clk = {
3518         .halt_reg = 0x4c020,
3519         .clkr = {
3520                 .enable_reg = 0x4c020,
3521                 .enable_mask = BIT(0),
3522                 .hw.init = &(struct clk_init_data){
3523                         .name = "gcc_venus0_ahb_clk",
3524                         .parent_hws = (const struct clk_hw*[]){
3525                                 &pcnoc_bfdcd_clk_src.clkr.hw,
3526                         },
3527                         .num_parents = 1,
3528                         .flags = CLK_SET_RATE_PARENT,
3529                         .ops = &clk_branch2_ops,
3530                 },
3531         },
3532 };
3533
3534 static struct clk_branch gcc_venus0_axi_clk = {
3535         .halt_reg = 0x4c024,
3536         .clkr = {
3537                 .enable_reg = 0x4c024,
3538                 .enable_mask = BIT(0),
3539                 .hw.init = &(struct clk_init_data){
3540                         .name = "gcc_venus0_axi_clk",
3541                         .parent_hws = (const struct clk_hw*[]){
3542                                 &system_mm_noc_bfdcd_clk_src.clkr.hw,
3543                         },
3544                         .num_parents = 1,
3545                         .flags = CLK_SET_RATE_PARENT,
3546                         .ops = &clk_branch2_ops,
3547                 },
3548         },
3549 };
3550
3551 static struct clk_branch gcc_venus0_vcodec0_clk = {
3552         .halt_reg = 0x4c01c,
3553         .clkr = {
3554                 .enable_reg = 0x4c01c,
3555                 .enable_mask = BIT(0),
3556                 .hw.init = &(struct clk_init_data){
3557                         .name = "gcc_venus0_vcodec0_clk",
3558                         .parent_hws = (const struct clk_hw*[]){
3559                                 &vcodec0_clk_src.clkr.hw,
3560                         },
3561                         .num_parents = 1,
3562                         .flags = CLK_SET_RATE_PARENT,
3563                         .ops = &clk_branch2_ops,
3564                 },
3565         },
3566 };
3567
3568 static struct clk_branch gcc_venus0_core0_vcodec0_clk = {
3569         .halt_reg = 0x4c02c,
3570         .clkr = {
3571                 .enable_reg = 0x4c02c,
3572                 .enable_mask = BIT(0),
3573                 .hw.init = &(struct clk_init_data){
3574                         .name = "gcc_venus0_core0_vcodec0_clk",
3575                         .parent_hws = (const struct clk_hw*[]){
3576                                 &vcodec0_clk_src.clkr.hw,
3577                         },
3578                         .num_parents = 1,
3579                         .flags = CLK_SET_RATE_PARENT,
3580                         .ops = &clk_branch2_ops,
3581                 },
3582         },
3583 };
3584
3585 static struct clk_branch gcc_venus0_core1_vcodec0_clk = {
3586         .halt_reg = 0x4c034,
3587         .clkr = {
3588                 .enable_reg = 0x4c034,
3589                 .enable_mask = BIT(0),
3590                 .hw.init = &(struct clk_init_data){
3591                         .name = "gcc_venus0_core1_vcodec0_clk",
3592                         .parent_hws = (const struct clk_hw*[]){
3593                                 &vcodec0_clk_src.clkr.hw,
3594                         },
3595                         .num_parents = 1,
3596                         .flags = CLK_SET_RATE_PARENT,
3597                         .ops = &clk_branch2_ops,
3598                 },
3599         },
3600 };
3601
3602 static struct clk_branch gcc_oxili_timer_clk = {
3603         .halt_reg = 0x59040,
3604         .clkr = {
3605                 .enable_reg = 0x59040,
3606                 .enable_mask = BIT(0),
3607                 .hw.init = &(struct clk_init_data){
3608                         .name = "gcc_oxili_timer_clk",
3609                         .ops = &clk_branch2_ops,
3610                 },
3611         },
3612 };
3613
3614 static struct gdsc venus_gdsc = {
3615         .gdscr = 0x4c018,
3616         .pd = {
3617                 .name = "venus",
3618         },
3619         .pwrsts = PWRSTS_OFF_ON,
3620 };
3621
3622 static struct gdsc mdss_gdsc = {
3623         .gdscr = 0x4d078,
3624         .pd = {
3625                 .name = "mdss",
3626         },
3627         .pwrsts = PWRSTS_OFF_ON,
3628 };
3629
3630 static struct gdsc jpeg_gdsc = {
3631         .gdscr = 0x5701c,
3632         .pd = {
3633                 .name = "jpeg",
3634         },
3635         .pwrsts = PWRSTS_OFF_ON,
3636 };
3637
3638 static struct gdsc vfe_gdsc = {
3639         .gdscr = 0x58034,
3640         .pd = {
3641                 .name = "vfe",
3642         },
3643         .pwrsts = PWRSTS_OFF_ON,
3644 };
3645
3646 static struct gdsc oxili_gdsc = {
3647         .gdscr = 0x5901c,
3648         .pd = {
3649                 .name = "oxili",
3650         },
3651         .pwrsts = PWRSTS_OFF_ON,
3652 };
3653
3654 static struct gdsc venus_core0_gdsc = {
3655         .gdscr = 0x4c028,
3656         .pd = {
3657                 .name = "venus_core0",
3658         },
3659         .pwrsts = PWRSTS_OFF_ON,
3660 };
3661
3662 static struct gdsc venus_core1_gdsc = {
3663         .gdscr = 0x4c030,
3664         .pd = {
3665                 .name = "venus_core1",
3666         },
3667         .pwrsts = PWRSTS_OFF_ON,
3668 };
3669
3670 static struct clk_regmap *gcc_msm8939_clocks[] = {
3671         [GPLL0] = &gpll0.clkr,
3672         [GPLL0_VOTE] = &gpll0_vote,
3673         [BIMC_PLL] = &bimc_pll.clkr,
3674         [BIMC_PLL_VOTE] = &bimc_pll_vote,
3675         [GPLL1] = &gpll1.clkr,
3676         [GPLL1_VOTE] = &gpll1_vote,
3677         [GPLL2] = &gpll2.clkr,
3678         [GPLL2_VOTE] = &gpll2_vote,
3679         [PCNOC_BFDCD_CLK_SRC] = &pcnoc_bfdcd_clk_src.clkr,
3680         [SYSTEM_NOC_BFDCD_CLK_SRC] = &system_noc_bfdcd_clk_src.clkr,
3681         [SYSTEM_MM_NOC_BFDCD_CLK_SRC] = &system_mm_noc_bfdcd_clk_src.clkr,
3682         [CAMSS_AHB_CLK_SRC] = &camss_ahb_clk_src.clkr,
3683         [APSS_AHB_CLK_SRC] = &apss_ahb_clk_src.clkr,
3684         [CSI0_CLK_SRC] = &csi0_clk_src.clkr,
3685         [CSI1_CLK_SRC] = &csi1_clk_src.clkr,
3686         [GFX3D_CLK_SRC] = &gfx3d_clk_src.clkr,
3687         [VFE0_CLK_SRC] = &vfe0_clk_src.clkr,
3688         [BLSP1_QUP1_I2C_APPS_CLK_SRC] = &blsp1_qup1_i2c_apps_clk_src.clkr,
3689         [BLSP1_QUP1_SPI_APPS_CLK_SRC] = &blsp1_qup1_spi_apps_clk_src.clkr,
3690         [BLSP1_QUP2_I2C_APPS_CLK_SRC] = &blsp1_qup2_i2c_apps_clk_src.clkr,
3691         [BLSP1_QUP2_SPI_APPS_CLK_SRC] = &blsp1_qup2_spi_apps_clk_src.clkr,
3692         [BLSP1_QUP3_I2C_APPS_CLK_SRC] = &blsp1_qup3_i2c_apps_clk_src.clkr,
3693         [BLSP1_QUP3_SPI_APPS_CLK_SRC] = &blsp1_qup3_spi_apps_clk_src.clkr,
3694         [BLSP1_QUP4_I2C_APPS_CLK_SRC] = &blsp1_qup4_i2c_apps_clk_src.clkr,
3695         [BLSP1_QUP4_SPI_APPS_CLK_SRC] = &blsp1_qup4_spi_apps_clk_src.clkr,
3696         [BLSP1_QUP5_I2C_APPS_CLK_SRC] = &blsp1_qup5_i2c_apps_clk_src.clkr,
3697         [BLSP1_QUP5_SPI_APPS_CLK_SRC] = &blsp1_qup5_spi_apps_clk_src.clkr,
3698         [BLSP1_QUP6_I2C_APPS_CLK_SRC] = &blsp1_qup6_i2c_apps_clk_src.clkr,
3699         [BLSP1_QUP6_SPI_APPS_CLK_SRC] = &blsp1_qup6_spi_apps_clk_src.clkr,
3700         [BLSP1_UART1_APPS_CLK_SRC] = &blsp1_uart1_apps_clk_src.clkr,
3701         [BLSP1_UART2_APPS_CLK_SRC] = &blsp1_uart2_apps_clk_src.clkr,
3702         [CCI_CLK_SRC] = &cci_clk_src.clkr,
3703         [CAMSS_GP0_CLK_SRC] = &camss_gp0_clk_src.clkr,
3704         [CAMSS_GP1_CLK_SRC] = &camss_gp1_clk_src.clkr,
3705         [JPEG0_CLK_SRC] = &jpeg0_clk_src.clkr,
3706         [MCLK0_CLK_SRC] = &mclk0_clk_src.clkr,
3707         [MCLK1_CLK_SRC] = &mclk1_clk_src.clkr,
3708         [CSI0PHYTIMER_CLK_SRC] = &csi0phytimer_clk_src.clkr,
3709         [CSI1PHYTIMER_CLK_SRC] = &csi1phytimer_clk_src.clkr,
3710         [CPP_CLK_SRC] = &cpp_clk_src.clkr,
3711         [CRYPTO_CLK_SRC] = &crypto_clk_src.clkr,
3712         [GP1_CLK_SRC] = &gp1_clk_src.clkr,
3713         [GP2_CLK_SRC] = &gp2_clk_src.clkr,
3714         [GP3_CLK_SRC] = &gp3_clk_src.clkr,
3715         [BYTE0_CLK_SRC] = &byte0_clk_src.clkr,
3716         [ESC0_CLK_SRC] = &esc0_clk_src.clkr,
3717         [MDP_CLK_SRC] = &mdp_clk_src.clkr,
3718         [PCLK0_CLK_SRC] = &pclk0_clk_src.clkr,
3719         [VSYNC_CLK_SRC] = &vsync_clk_src.clkr,
3720         [PDM2_CLK_SRC] = &pdm2_clk_src.clkr,
3721         [SDCC1_APPS_CLK_SRC] = &sdcc1_apps_clk_src.clkr,
3722         [SDCC2_APPS_CLK_SRC] = &sdcc2_apps_clk_src.clkr,
3723         [APSS_TCU_CLK_SRC] = &apss_tcu_clk_src.clkr,
3724         [USB_HS_SYSTEM_CLK_SRC] = &usb_hs_system_clk_src.clkr,
3725         [VCODEC0_CLK_SRC] = &vcodec0_clk_src.clkr,
3726         [GCC_BLSP1_AHB_CLK] = &gcc_blsp1_ahb_clk.clkr,
3727         [GCC_BLSP1_SLEEP_CLK] = &gcc_blsp1_sleep_clk.clkr,
3728         [GCC_BLSP1_QUP1_I2C_APPS_CLK] = &gcc_blsp1_qup1_i2c_apps_clk.clkr,
3729         [GCC_BLSP1_QUP1_SPI_APPS_CLK] = &gcc_blsp1_qup1_spi_apps_clk.clkr,
3730         [GCC_BLSP1_QUP2_I2C_APPS_CLK] = &gcc_blsp1_qup2_i2c_apps_clk.clkr,
3731         [GCC_BLSP1_QUP2_SPI_APPS_CLK] = &gcc_blsp1_qup2_spi_apps_clk.clkr,
3732         [GCC_BLSP1_QUP3_I2C_APPS_CLK] = &gcc_blsp1_qup3_i2c_apps_clk.clkr,
3733         [GCC_BLSP1_QUP3_SPI_APPS_CLK] = &gcc_blsp1_qup3_spi_apps_clk.clkr,
3734         [GCC_BLSP1_QUP4_I2C_APPS_CLK] = &gcc_blsp1_qup4_i2c_apps_clk.clkr,
3735         [GCC_BLSP1_QUP4_SPI_APPS_CLK] = &gcc_blsp1_qup4_spi_apps_clk.clkr,
3736         [GCC_BLSP1_QUP5_I2C_APPS_CLK] = &gcc_blsp1_qup5_i2c_apps_clk.clkr,
3737         [GCC_BLSP1_QUP5_SPI_APPS_CLK] = &gcc_blsp1_qup5_spi_apps_clk.clkr,
3738         [GCC_BLSP1_QUP6_I2C_APPS_CLK] = &gcc_blsp1_qup6_i2c_apps_clk.clkr,
3739         [GCC_BLSP1_QUP6_SPI_APPS_CLK] = &gcc_blsp1_qup6_spi_apps_clk.clkr,
3740         [GCC_BLSP1_UART1_APPS_CLK] = &gcc_blsp1_uart1_apps_clk.clkr,
3741         [GCC_BLSP1_UART2_APPS_CLK] = &gcc_blsp1_uart2_apps_clk.clkr,
3742         [GCC_BOOT_ROM_AHB_CLK] = &gcc_boot_rom_ahb_clk.clkr,
3743         [GCC_CAMSS_CCI_AHB_CLK] = &gcc_camss_cci_ahb_clk.clkr,
3744         [GCC_CAMSS_CCI_CLK] = &gcc_camss_cci_clk.clkr,
3745         [GCC_CAMSS_CSI0_AHB_CLK] = &gcc_camss_csi0_ahb_clk.clkr,
3746         [GCC_CAMSS_CSI0_CLK] = &gcc_camss_csi0_clk.clkr,
3747         [GCC_CAMSS_CSI0PHY_CLK] = &gcc_camss_csi0phy_clk.clkr,
3748         [GCC_CAMSS_CSI0PIX_CLK] = &gcc_camss_csi0pix_clk.clkr,
3749         [GCC_CAMSS_CSI0RDI_CLK] = &gcc_camss_csi0rdi_clk.clkr,
3750         [GCC_CAMSS_CSI1_AHB_CLK] = &gcc_camss_csi1_ahb_clk.clkr,
3751         [GCC_CAMSS_CSI1_CLK] = &gcc_camss_csi1_clk.clkr,
3752         [GCC_CAMSS_CSI1PHY_CLK] = &gcc_camss_csi1phy_clk.clkr,
3753         [GCC_CAMSS_CSI1PIX_CLK] = &gcc_camss_csi1pix_clk.clkr,
3754         [GCC_CAMSS_CSI1RDI_CLK] = &gcc_camss_csi1rdi_clk.clkr,
3755         [GCC_CAMSS_CSI_VFE0_CLK] = &gcc_camss_csi_vfe0_clk.clkr,
3756         [GCC_CAMSS_GP0_CLK] = &gcc_camss_gp0_clk.clkr,
3757         [GCC_CAMSS_GP1_CLK] = &gcc_camss_gp1_clk.clkr,
3758         [GCC_CAMSS_ISPIF_AHB_CLK] = &gcc_camss_ispif_ahb_clk.clkr,
3759         [GCC_CAMSS_JPEG0_CLK] = &gcc_camss_jpeg0_clk.clkr,
3760         [GCC_CAMSS_JPEG_AHB_CLK] = &gcc_camss_jpeg_ahb_clk.clkr,
3761         [GCC_CAMSS_JPEG_AXI_CLK] = &gcc_camss_jpeg_axi_clk.clkr,
3762         [GCC_CAMSS_MCLK0_CLK] = &gcc_camss_mclk0_clk.clkr,
3763         [GCC_CAMSS_MCLK1_CLK] = &gcc_camss_mclk1_clk.clkr,
3764         [GCC_CAMSS_MICRO_AHB_CLK] = &gcc_camss_micro_ahb_clk.clkr,
3765         [GCC_CAMSS_CSI0PHYTIMER_CLK] = &gcc_camss_csi0phytimer_clk.clkr,
3766         [GCC_CAMSS_CSI1PHYTIMER_CLK] = &gcc_camss_csi1phytimer_clk.clkr,
3767         [GCC_CAMSS_AHB_CLK] = &gcc_camss_ahb_clk.clkr,
3768         [GCC_CAMSS_TOP_AHB_CLK] = &gcc_camss_top_ahb_clk.clkr,
3769         [GCC_CAMSS_CPP_AHB_CLK] = &gcc_camss_cpp_ahb_clk.clkr,
3770         [GCC_CAMSS_CPP_CLK] = &gcc_camss_cpp_clk.clkr,
3771         [GCC_CAMSS_VFE0_CLK] = &gcc_camss_vfe0_clk.clkr,
3772         [GCC_CAMSS_VFE_AHB_CLK] = &gcc_camss_vfe_ahb_clk.clkr,
3773         [GCC_CAMSS_VFE_AXI_CLK] = &gcc_camss_vfe_axi_clk.clkr,
3774         [GCC_CRYPTO_AHB_CLK] = &gcc_crypto_ahb_clk.clkr,
3775         [GCC_CRYPTO_AXI_CLK] = &gcc_crypto_axi_clk.clkr,
3776         [GCC_CRYPTO_CLK] = &gcc_crypto_clk.clkr,
3777         [GCC_OXILI_GMEM_CLK] = &gcc_oxili_gmem_clk.clkr,
3778         [GCC_GP1_CLK] = &gcc_gp1_clk.clkr,
3779         [GCC_GP2_CLK] = &gcc_gp2_clk.clkr,
3780         [GCC_GP3_CLK] = &gcc_gp3_clk.clkr,
3781         [GCC_MDSS_AHB_CLK] = &gcc_mdss_ahb_clk.clkr,
3782         [GCC_MDSS_AXI_CLK] = &gcc_mdss_axi_clk.clkr,
3783         [GCC_MDSS_BYTE0_CLK] = &gcc_mdss_byte0_clk.clkr,
3784         [GCC_MDSS_ESC0_CLK] = &gcc_mdss_esc0_clk.clkr,
3785         [GCC_MDSS_MDP_CLK] = &gcc_mdss_mdp_clk.clkr,
3786         [GCC_MDSS_PCLK0_CLK] = &gcc_mdss_pclk0_clk.clkr,
3787         [GCC_MDSS_VSYNC_CLK] = &gcc_mdss_vsync_clk.clkr,
3788         [GCC_MSS_CFG_AHB_CLK] = &gcc_mss_cfg_ahb_clk.clkr,
3789         [GCC_OXILI_AHB_CLK] = &gcc_oxili_ahb_clk.clkr,
3790         [GCC_OXILI_GFX3D_CLK] = &gcc_oxili_gfx3d_clk.clkr,
3791         [GCC_PDM2_CLK] = &gcc_pdm2_clk.clkr,
3792         [GCC_PDM_AHB_CLK] = &gcc_pdm_ahb_clk.clkr,
3793         [GCC_PRNG_AHB_CLK] = &gcc_prng_ahb_clk.clkr,
3794         [GCC_SDCC1_AHB_CLK] = &gcc_sdcc1_ahb_clk.clkr,
3795         [GCC_SDCC1_APPS_CLK] = &gcc_sdcc1_apps_clk.clkr,
3796         [GCC_SDCC2_AHB_CLK] = &gcc_sdcc2_ahb_clk.clkr,
3797         [GCC_SDCC2_APPS_CLK] = &gcc_sdcc2_apps_clk.clkr,
3798         [GCC_GTCU_AHB_CLK] = &gcc_gtcu_ahb_clk.clkr,
3799         [GCC_JPEG_TBU_CLK] = &gcc_jpeg_tbu_clk.clkr,
3800         [GCC_MDP_TBU_CLK] = &gcc_mdp_tbu_clk.clkr,
3801         [GCC_SMMU_CFG_CLK] = &gcc_smmu_cfg_clk.clkr,
3802         [GCC_VENUS_TBU_CLK] = &gcc_venus_tbu_clk.clkr,
3803         [GCC_VFE_TBU_CLK] = &gcc_vfe_tbu_clk.clkr,
3804         [GCC_USB2A_PHY_SLEEP_CLK] = &gcc_usb2a_phy_sleep_clk.clkr,
3805         [GCC_USB_HS_AHB_CLK] = &gcc_usb_hs_ahb_clk.clkr,
3806         [GCC_USB_HS_SYSTEM_CLK] = &gcc_usb_hs_system_clk.clkr,
3807         [GCC_VENUS0_AHB_CLK] = &gcc_venus0_ahb_clk.clkr,
3808         [GCC_VENUS0_AXI_CLK] = &gcc_venus0_axi_clk.clkr,
3809         [GCC_VENUS0_VCODEC0_CLK] = &gcc_venus0_vcodec0_clk.clkr,
3810         [BIMC_DDR_CLK_SRC] = &bimc_ddr_clk_src.clkr,
3811         [GCC_APSS_TCU_CLK] = &gcc_apss_tcu_clk.clkr,
3812         [GCC_GFX_TCU_CLK] = &gcc_gfx_tcu_clk.clkr,
3813         [BIMC_GPU_CLK_SRC] = &bimc_gpu_clk_src.clkr,
3814         [GCC_BIMC_GFX_CLK] = &gcc_bimc_gfx_clk.clkr,
3815         [GCC_BIMC_GPU_CLK] = &gcc_bimc_gpu_clk.clkr,
3816         [ULTAUDIO_AHBFABRIC_CLK_SRC] = &ultaudio_ahbfabric_clk_src.clkr,
3817         [ULTAUDIO_LPAIF_PRI_I2S_CLK_SRC] = &ultaudio_lpaif_pri_i2s_clk_src.clkr,
3818         [ULTAUDIO_LPAIF_SEC_I2S_CLK_SRC] = &ultaudio_lpaif_sec_i2s_clk_src.clkr,
3819         [ULTAUDIO_LPAIF_AUX_I2S_CLK_SRC] = &ultaudio_lpaif_aux_i2s_clk_src.clkr,
3820         [ULTAUDIO_XO_CLK_SRC] = &ultaudio_xo_clk_src.clkr,
3821         [CODEC_DIGCODEC_CLK_SRC] = &codec_digcodec_clk_src.clkr,
3822         [GCC_ULTAUDIO_PCNOC_MPORT_CLK] = &gcc_ultaudio_pcnoc_mport_clk.clkr,
3823         [GCC_ULTAUDIO_PCNOC_SWAY_CLK] = &gcc_ultaudio_pcnoc_sway_clk.clkr,
3824         [GCC_ULTAUDIO_AVSYNC_XO_CLK] = &gcc_ultaudio_avsync_xo_clk.clkr,
3825         [GCC_ULTAUDIO_STC_XO_CLK] = &gcc_ultaudio_stc_xo_clk.clkr,
3826         [GCC_ULTAUDIO_AHBFABRIC_IXFABRIC_CLK] = &gcc_ultaudio_ahbfabric_ixfabric_clk.clkr,
3827         [GCC_ULTAUDIO_AHBFABRIC_IXFABRIC_LPM_CLK] = &gcc_ultaudio_ahbfabric_ixfabric_lpm_clk.clkr,
3828         [GCC_ULTAUDIO_LPAIF_PRI_I2S_CLK] = &gcc_ultaudio_lpaif_pri_i2s_clk.clkr,
3829         [GCC_ULTAUDIO_LPAIF_SEC_I2S_CLK] = &gcc_ultaudio_lpaif_sec_i2s_clk.clkr,
3830         [GCC_ULTAUDIO_LPAIF_AUX_I2S_CLK] = &gcc_ultaudio_lpaif_aux_i2s_clk.clkr,
3831         [GCC_CODEC_DIGCODEC_CLK] = &gcc_codec_digcodec_clk.clkr,
3832         [GCC_MSS_Q6_BIMC_AXI_CLK] = &gcc_mss_q6_bimc_axi_clk.clkr,
3833         [GPLL3] = &gpll3.clkr,
3834         [GPLL3_VOTE] = &gpll3_vote,
3835         [GPLL4] = &gpll4.clkr,
3836         [GPLL4_VOTE] = &gpll4_vote,
3837         [GPLL5] = &gpll5.clkr,
3838         [GPLL5_VOTE] = &gpll5_vote,
3839         [GPLL6] = &gpll6.clkr,
3840         [GPLL6_VOTE] = &gpll6_vote,
3841         [BYTE1_CLK_SRC] = &byte1_clk_src.clkr,
3842         [GCC_MDSS_BYTE1_CLK] = &gcc_mdss_byte1_clk.clkr,
3843         [ESC1_CLK_SRC] = &esc1_clk_src.clkr,
3844         [GCC_MDSS_ESC1_CLK] = &gcc_mdss_esc1_clk.clkr,
3845         [PCLK1_CLK_SRC] = &pclk1_clk_src.clkr,
3846         [GCC_MDSS_PCLK1_CLK] = &gcc_mdss_pclk1_clk.clkr,
3847         [GCC_GFX_TBU_CLK] = &gcc_gfx_tbu_clk.clkr,
3848         [GCC_CPP_TBU_CLK] = &gcc_cpp_tbu_clk.clkr,
3849         [GCC_MDP_RT_TBU_CLK] = &gcc_mdp_rt_tbu_clk.clkr,
3850         [USB_FS_SYSTEM_CLK_SRC] = &usb_fs_system_clk_src.clkr,
3851         [USB_FS_IC_CLK_SRC] = &usb_fs_ic_clk_src.clkr,
3852         [GCC_USB_FS_AHB_CLK] = &gcc_usb_fs_ahb_clk.clkr,
3853         [GCC_USB_FS_IC_CLK] = &gcc_usb_fs_ic_clk.clkr,
3854         [GCC_USB_FS_SYSTEM_CLK] = &gcc_usb_fs_system_clk.clkr,
3855         [GCC_VENUS0_CORE0_VCODEC0_CLK] = &gcc_venus0_core0_vcodec0_clk.clkr,
3856         [GCC_VENUS0_CORE1_VCODEC0_CLK] = &gcc_venus0_core1_vcodec0_clk.clkr,
3857         [GCC_OXILI_TIMER_CLK] = &gcc_oxili_timer_clk.clkr,
3858 };
3859
3860 static struct gdsc *gcc_msm8939_gdscs[] = {
3861         [VENUS_GDSC] = &venus_gdsc,
3862         [MDSS_GDSC] = &mdss_gdsc,
3863         [JPEG_GDSC] = &jpeg_gdsc,
3864         [VFE_GDSC] = &vfe_gdsc,
3865         [OXILI_GDSC] = &oxili_gdsc,
3866         [VENUS_CORE0_GDSC] = &venus_core0_gdsc,
3867         [VENUS_CORE1_GDSC] = &venus_core1_gdsc,
3868 };
3869
3870 static const struct qcom_reset_map gcc_msm8939_resets[] = {
3871         [GCC_BLSP1_BCR] = { 0x01000 },
3872         [GCC_BLSP1_QUP1_BCR] = { 0x02000 },
3873         [GCC_BLSP1_UART1_BCR] = { 0x02038 },
3874         [GCC_BLSP1_QUP2_BCR] = { 0x03008 },
3875         [GCC_BLSP1_UART2_BCR] = { 0x03028 },
3876         [GCC_BLSP1_QUP3_BCR] = { 0x04018 },
3877         [GCC_BLSP1_UART3_BCR] = { 0x04038 },
3878         [GCC_BLSP1_QUP4_BCR] = { 0x05018 },
3879         [GCC_BLSP1_QUP5_BCR] = { 0x06018 },
3880         [GCC_BLSP1_QUP6_BCR] = { 0x07018 },
3881         [GCC_IMEM_BCR] = { 0x0e000 },
3882         [GCC_SMMU_BCR] = { 0x12000 },
3883         [GCC_APSS_TCU_BCR] = { 0x12050 },
3884         [GCC_SMMU_XPU_BCR] = { 0x12054 },
3885         [GCC_PCNOC_TBU_BCR] = { 0x12058 },
3886         [GCC_PRNG_BCR] = { 0x13000 },
3887         [GCC_BOOT_ROM_BCR] = { 0x13008 },
3888         [GCC_CRYPTO_BCR] = { 0x16000 },
3889         [GCC_SEC_CTRL_BCR] = { 0x1a000 },
3890         [GCC_AUDIO_CORE_BCR] = { 0x1c008 },
3891         [GCC_ULT_AUDIO_BCR] = { 0x1c0b4 },
3892         [GCC_DEHR_BCR] = { 0x1f000 },
3893         [GCC_SYSTEM_NOC_BCR] = { 0x26000 },
3894         [GCC_PCNOC_BCR] = { 0x27018 },
3895         [GCC_TCSR_BCR] = { 0x28000 },
3896         [GCC_QDSS_BCR] = { 0x29000 },
3897         [GCC_DCD_BCR] = { 0x2a000 },
3898         [GCC_MSG_RAM_BCR] = { 0x2b000 },
3899         [GCC_MPM_BCR] = { 0x2c000 },
3900         [GCC_SPMI_BCR] = { 0x2e000 },
3901         [GCC_SPDM_BCR] = { 0x2f000 },
3902         [GCC_MM_SPDM_BCR] = { 0x2f024 },
3903         [GCC_BIMC_BCR] = { 0x31000 },
3904         [GCC_RBCPR_BCR] = { 0x33000 },
3905         [GCC_TLMM_BCR] = { 0x34000 },
3906         [GCC_CAMSS_CSI2_BCR] = { 0x3c038 },
3907         [GCC_CAMSS_CSI2PHY_BCR] = { 0x3c044 },
3908         [GCC_CAMSS_CSI2RDI_BCR] = { 0x3c04c },
3909         [GCC_CAMSS_CSI2PIX_BCR] = { 0x3c054 },
3910         [GCC_USB_FS_BCR] = { 0x3f000 },
3911         [GCC_USB_HS_BCR] = { 0x41000 },
3912         [GCC_USB2A_PHY_BCR] = { 0x41028 },
3913         [GCC_SDCC1_BCR] = { 0x42000 },
3914         [GCC_SDCC2_BCR] = { 0x43000 },
3915         [GCC_PDM_BCR] = { 0x44000 },
3916         [GCC_SNOC_BUS_TIMEOUT0_BCR] = { 0x47000 },
3917         [GCC_PCNOC_BUS_TIMEOUT0_BCR] = { 0x48000 },
3918         [GCC_PCNOC_BUS_TIMEOUT1_BCR] = { 0x48008 },
3919         [GCC_PCNOC_BUS_TIMEOUT2_BCR] = { 0x48010 },
3920         [GCC_PCNOC_BUS_TIMEOUT3_BCR] = { 0x48018 },
3921         [GCC_PCNOC_BUS_TIMEOUT4_BCR] = { 0x48020 },
3922         [GCC_PCNOC_BUS_TIMEOUT5_BCR] = { 0x48028 },
3923         [GCC_PCNOC_BUS_TIMEOUT6_BCR] = { 0x48030 },
3924         [GCC_PCNOC_BUS_TIMEOUT7_BCR] = { 0x48038 },
3925         [GCC_PCNOC_BUS_TIMEOUT8_BCR] = { 0x48040 },
3926         [GCC_PCNOC_BUS_TIMEOUT9_BCR] = { 0x48048 },
3927         [GCC_MMSS_BCR] = { 0x4b000 },
3928         [GCC_VENUS0_BCR] = { 0x4c014 },
3929         [GCC_MDSS_BCR] = { 0x4d074 },
3930         [GCC_CAMSS_PHY0_BCR] = { 0x4e018 },
3931         [GCC_CAMSS_CSI0_BCR] = { 0x4e038 },
3932         [GCC_CAMSS_CSI0PHY_BCR] = { 0x4e044 },
3933         [GCC_CAMSS_CSI0RDI_BCR] = { 0x4e04c },
3934         [GCC_CAMSS_CSI0PIX_BCR] = { 0x4e054 },
3935         [GCC_CAMSS_PHY1_BCR] = { 0x4f018 },
3936         [GCC_CAMSS_CSI1_BCR] = { 0x4f038 },
3937         [GCC_CAMSS_CSI1PHY_BCR] = { 0x4f044 },
3938         [GCC_CAMSS_CSI1RDI_BCR] = { 0x4f04c },
3939         [GCC_CAMSS_CSI1PIX_BCR] = { 0x4f054 },
3940         [GCC_CAMSS_ISPIF_BCR] = { 0x50000 },
3941         [GCC_BLSP1_QUP4_SPI_APPS_CBCR] = { 0x0501c },
3942         [GCC_CAMSS_CCI_BCR] = { 0x51014 },
3943         [GCC_CAMSS_MCLK0_BCR] = { 0x52014 },
3944         [GCC_CAMSS_MCLK1_BCR] = { 0x53014 },
3945         [GCC_CAMSS_GP0_BCR] = { 0x54014 },
3946         [GCC_CAMSS_GP1_BCR] = { 0x55014 },
3947         [GCC_CAMSS_TOP_BCR] = { 0x56000 },
3948         [GCC_CAMSS_MICRO_BCR] = { 0x56008 },
3949         [GCC_CAMSS_JPEG_BCR] = { 0x57018 },
3950         [GCC_CAMSS_VFE_BCR] = { 0x58030 },
3951         [GCC_CAMSS_CSI_VFE0_BCR] = { 0x5804c },
3952         [GCC_OXILI_BCR] = { 0x59018 },
3953         [GCC_GMEM_BCR] = { 0x5902c },
3954         [GCC_CAMSS_AHB_BCR] = { 0x5a018 },
3955         [GCC_CAMSS_MCLK2_BCR] = { 0x5c014 },
3956         [GCC_MDP_TBU_BCR] = { 0x62000 },
3957         [GCC_GFX_TBU_BCR] = { 0x63000 },
3958         [GCC_GFX_TCU_BCR] = { 0x64000 },
3959         [GCC_MSS_TBU_AXI_BCR] = { 0x65000 },
3960         [GCC_MSS_TBU_GSS_AXI_BCR] = { 0x66000 },
3961         [GCC_MSS_TBU_Q6_AXI_BCR] = { 0x67000 },
3962         [GCC_GTCU_AHB_BCR] = { 0x68000 },
3963         [GCC_SMMU_CFG_BCR] = { 0x69000 },
3964         [GCC_VFE_TBU_BCR] = { 0x6a000 },
3965         [GCC_VENUS_TBU_BCR] = { 0x6b000 },
3966         [GCC_JPEG_TBU_BCR] = { 0x6c000 },
3967         [GCC_PRONTO_TBU_BCR] = { 0x6d000 },
3968         [GCC_CPP_TBU_BCR] = { 0x6e000 },
3969         [GCC_MDP_RT_TBU_BCR] = { 0x6f000 },
3970         [GCC_SMMU_CATS_BCR] = { 0x7c000 },
3971 };
3972
3973 static const struct regmap_config gcc_msm8939_regmap_config = {
3974         .reg_bits       = 32,
3975         .reg_stride     = 4,
3976         .val_bits       = 32,
3977         .max_register   = 0x80000,
3978         .fast_io        = true,
3979 };
3980
3981 static const struct qcom_cc_desc gcc_msm8939_desc = {
3982         .config = &gcc_msm8939_regmap_config,
3983         .clks = gcc_msm8939_clocks,
3984         .num_clks = ARRAY_SIZE(gcc_msm8939_clocks),
3985         .resets = gcc_msm8939_resets,
3986         .num_resets = ARRAY_SIZE(gcc_msm8939_resets),
3987         .gdscs = gcc_msm8939_gdscs,
3988         .num_gdscs = ARRAY_SIZE(gcc_msm8939_gdscs),
3989 };
3990
3991 static const struct of_device_id gcc_msm8939_match_table[] = {
3992         { .compatible = "qcom,gcc-msm8939" },
3993         { }
3994 };
3995 MODULE_DEVICE_TABLE(of, gcc_msm8939_match_table);
3996
3997 static int gcc_msm8939_probe(struct platform_device *pdev)
3998 {
3999         struct regmap *regmap;
4000
4001         regmap = qcom_cc_map(pdev, &gcc_msm8939_desc);
4002         if (IS_ERR(regmap))
4003                 return PTR_ERR(regmap);
4004
4005         clk_pll_configure_sr_hpm_lp(&gpll3, regmap, &gpll3_config, true);
4006         clk_pll_configure_sr_hpm_lp(&gpll4, regmap, &gpll4_config, true);
4007
4008         return qcom_cc_really_probe(pdev, &gcc_msm8939_desc, regmap);
4009 }
4010
4011 static struct platform_driver gcc_msm8939_driver = {
4012         .probe          = gcc_msm8939_probe,
4013         .driver         = {
4014                 .name   = "gcc-msm8939",
4015                 .of_match_table = gcc_msm8939_match_table,
4016         },
4017 };
4018
4019 static int __init gcc_msm8939_init(void)
4020 {
4021         return platform_driver_register(&gcc_msm8939_driver);
4022 }
4023 core_initcall(gcc_msm8939_init);
4024
4025 static void __exit gcc_msm8939_exit(void)
4026 {
4027         platform_driver_unregister(&gcc_msm8939_driver);
4028 }
4029 module_exit(gcc_msm8939_exit);
4030
4031 MODULE_DESCRIPTION("Qualcomm GCC MSM8939 Driver");
4032 MODULE_LICENSE("GPL v2");