drivers/usb/host/xhci-pci.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * xHCI host controller driver PCI Bus Glue.
   4  *
   5  * Copyright (C) 2008 Intel Corp.
   6  *
   7  * Author: Sarah Sharp
   8  * Some code borrowed from the Linux EHCI driver.
   9  */
  10
  11 #include <linux/pci.h>
  12 #include <linux/slab.h>
  13 #include <linux/module.h>
  14 #include <linux/acpi.h>
  15
  16 #include "xhci.h"
  17 #include "xhci-trace.h"
  18
  19 #define SSIC_PORT_NUM           2
  20 #define SSIC_PORT_CFG2          0x880c
  21 #define SSIC_PORT_CFG2_OFFSET   0x30
  22 #define PROG_DONE               (1 << 30)
  23 #define SSIC_PORT_UNUSED        (1 << 31)
  24
  25 /* Device for a quirk */
  26 #define PCI_VENDOR_ID_FRESCO_LOGIC      0x1b73
  27 #define PCI_DEVICE_ID_FRESCO_LOGIC_PDK  0x1000
  28 #define PCI_DEVICE_ID_FRESCO_LOGIC_FL1009       0x1009
  29 #define PCI_DEVICE_ID_FRESCO_LOGIC_FL1400       0x1400
  30
  31 #define PCI_VENDOR_ID_ETRON             0x1b6f
  32 #define PCI_DEVICE_ID_EJ168             0x7023
  33
  34 #define PCI_DEVICE_ID_INTEL_LYNXPOINT_XHCI      0x8c31
  35 #define PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_XHCI   0x9c31
  36 #define PCI_DEVICE_ID_INTEL_WILDCATPOINT_LP_XHCI        0x9cb1
  37 #define PCI_DEVICE_ID_INTEL_CHERRYVIEW_XHCI             0x22b5
  38 #define PCI_DEVICE_ID_INTEL_SUNRISEPOINT_H_XHCI         0xa12f
  39 #define PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_XHCI        0x9d2f
  40 #define PCI_DEVICE_ID_INTEL_BROXTON_M_XHCI              0x0aa8
  41 #define PCI_DEVICE_ID_INTEL_BROXTON_B_XHCI              0x1aa8
  42 #define PCI_DEVICE_ID_INTEL_APL_XHCI                    0x5aa8
  43 #define PCI_DEVICE_ID_INTEL_DNV_XHCI                    0x19d0
  44
  45 #define PCI_DEVICE_ID_AMD_PROMONTORYA_4                 0x43b9
  46 #define PCI_DEVICE_ID_AMD_PROMONTORYA_3                 0x43ba
  47 #define PCI_DEVICE_ID_AMD_PROMONTORYA_2                 0x43bb
  48 #define PCI_DEVICE_ID_AMD_PROMONTORYA_1                 0x43bc
  49 #define PCI_DEVICE_ID_ASMEDIA_1042A_XHCI                0x1142
  50
  51 static const char hcd_name[] = "xhci_hcd";
  52
  53 static struct hc_driver __read_mostly xhci_pci_hc_driver;
  54
  55 static int xhci_pci_setup(struct usb_hcd *hcd);
  56
  57 static const struct xhci_driver_overrides xhci_pci_overrides __initconst = {
  58         .reset = xhci_pci_setup,
  59 };
  60
  61 /* called after powerup, by probe or system-pm "wakeup" */
  62 static int xhci_pci_reinit(struct xhci_hcd *xhci, struct pci_dev *pdev)
  63 {
  64         /*
  65          * TODO: Implement finding debug ports later.
  66          * TODO: see if there are any quirks that need to be added to handle
  67          * new extended capabilities.
  68          */
  69
  70         /* PCI Memory-Write-Invalidate cycle support is optional (uncommon) */
  71         if (!pci_set_mwi(pdev))
  72                 xhci_dbg(xhci, "MWI active\n");
  73
  74         xhci_dbg(xhci, "Finished xhci_pci_reinit\n");
  75         return 0;
  76 }
  77
  78 static void xhci_pci_quirks(struct device *dev, struct xhci_hcd *xhci)
  79 {
  80         struct pci_dev          *pdev = to_pci_dev(dev);
  81
  82         /* Look for vendor-specific quirks */
  83         if (pdev->vendor == PCI_VENDOR_ID_FRESCO_LOGIC &&
  84                         (pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_PDK ||
  85                          pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_FL1400)) {
  86                 if (pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_PDK &&
  87                                 pdev->revision == 0x0) {
  88                         xhci->quirks |= XHCI_RESET_EP_QUIRK;
  89                         xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
  90                                 "QUIRK: Fresco Logic xHC needs configure"
  91                                 " endpoint cmd after reset endpoint");
  92                 }
  93                 if (pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_PDK &&
  94                                 pdev->revision == 0x4) {
  95                         xhci->quirks |= XHCI_SLOW_SUSPEND;
  96                         xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
  97                                 "QUIRK: Fresco Logic xHC revision %u"
  98                                 "must be suspended extra slowly",
  99                                 pdev->revision);
 100                 }
 101                 if (pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_PDK)
 102                         xhci->quirks |= XHCI_BROKEN_STREAMS;
 103                 /* Fresco Logic confirms: all revisions of this chip do not
 104                  * support MSI, even though some of them claim to in their PCI
 105                  * capabilities.
 106                  */
 107                 xhci->quirks |= XHCI_BROKEN_MSI;
 108                 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
 109                                 "QUIRK: Fresco Logic revision %u "
 110                                 "has broken MSI implementation",
 111                                 pdev->revision);
 112                 xhci->quirks |= XHCI_TRUST_TX_LENGTH;
 113         }
 114
 115         if (pdev->vendor == PCI_VENDOR_ID_FRESCO_LOGIC &&
 116                         pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_FL1009)
 117                 xhci->quirks |= XHCI_BROKEN_STREAMS;
 118
 119         if (pdev->vendor == PCI_VENDOR_ID_NEC)
 120                 xhci->quirks |= XHCI_NEC_HOST;
 121
 122         if (pdev->vendor == PCI_VENDOR_ID_AMD && xhci->hci_version == 0x96)
 123                 xhci->quirks |= XHCI_AMD_0x96_HOST;
 124
 125         /* AMD PLL quirk */
 126         if (pdev->vendor == PCI_VENDOR_ID_AMD && usb_amd_find_chipset_info())
 127                 xhci->quirks |= XHCI_AMD_PLL_FIX;
 128
 129         if (pdev->vendor == PCI_VENDOR_ID_AMD &&
 130                 (pdev->device == 0x15e0 ||
 131                  pdev->device == 0x15e1 ||
 132                  pdev->device == 0x43bb))
 133                 xhci->quirks |= XHCI_SUSPEND_DELAY;
 134
 135         if (pdev->vendor == PCI_VENDOR_ID_AMD)
 136                 xhci->quirks |= XHCI_TRUST_TX_LENGTH;
 137
 138         if ((pdev->vendor == PCI_VENDOR_ID_AMD) &&
 139                 ((pdev->device == PCI_DEVICE_ID_AMD_PROMONTORYA_4) ||
 140                 (pdev->device == PCI_DEVICE_ID_AMD_PROMONTORYA_3) ||
 141                 (pdev->device == PCI_DEVICE_ID_AMD_PROMONTORYA_2) ||
 142                 (pdev->device == PCI_DEVICE_ID_AMD_PROMONTORYA_1)))
 143                 xhci->quirks |= XHCI_U2_DISABLE_WAKE;
 144
 145         if (pdev->vendor == PCI_VENDOR_ID_INTEL) {
 146                 xhci->quirks |= XHCI_LPM_SUPPORT;
 147                 xhci->quirks |= XHCI_INTEL_HOST;
 148                 xhci->quirks |= XHCI_AVOID_BEI;
 149         }
 150         if (pdev->vendor == PCI_VENDOR_ID_INTEL &&
 151                         pdev->device == PCI_DEVICE_ID_INTEL_PANTHERPOINT_XHCI) {
 152                 xhci->quirks |= XHCI_EP_LIMIT_QUIRK;
 153                 xhci->limit_active_eps = 64;
 154                 xhci->quirks |= XHCI_SW_BW_CHECKING;
 155                 /*
 156                  * PPT desktop boards DH77EB and DH77DF will power back on after
 157                  * a few seconds of being shutdown.  The fix for this is to
 158                  * switch the ports from xHCI to EHCI on shutdown.  We can't use
 159                  * DMI information to find those particular boards (since each
 160                  * vendor will change the board name), so we have to key off all
 161                  * PPT chipsets.
 162                  */
 163                 xhci->quirks |= XHCI_SPURIOUS_REBOOT;
 164         }
 165         if (pdev->vendor == PCI_VENDOR_ID_INTEL &&
 166                 (pdev->device == PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_XHCI ||
 167                  pdev->device == PCI_DEVICE_ID_INTEL_WILDCATPOINT_LP_XHCI)) {
 168                 xhci->quirks |= XHCI_SPURIOUS_REBOOT;
 169                 xhci->quirks |= XHCI_SPURIOUS_WAKEUP;
 170         }
 171         if (pdev->vendor == PCI_VENDOR_ID_INTEL &&
 172                 (pdev->device == PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_XHCI ||
 173                  pdev->device == PCI_DEVICE_ID_INTEL_SUNRISEPOINT_H_XHCI ||
 174                  pdev->device == PCI_DEVICE_ID_INTEL_CHERRYVIEW_XHCI ||
 175                  pdev->device == PCI_DEVICE_ID_INTEL_BROXTON_M_XHCI ||
 176                  pdev->device == PCI_DEVICE_ID_INTEL_BROXTON_B_XHCI ||
 177                  pdev->device == PCI_DEVICE_ID_INTEL_APL_XHCI ||
 178                  pdev->device == PCI_DEVICE_ID_INTEL_DNV_XHCI)) {
 179                 xhci->quirks |= XHCI_PME_STUCK_QUIRK;
 180         }
 181         if (pdev->vendor == PCI_VENDOR_ID_INTEL &&
 182                  pdev->device == PCI_DEVICE_ID_INTEL_CHERRYVIEW_XHCI) {
 183                 xhci->quirks |= XHCI_SSIC_PORT_UNUSED;
 184                 xhci->quirks |= XHCI_INTEL_USB_ROLE_SW;
 185         }
 186         if (pdev->vendor == PCI_VENDOR_ID_INTEL &&
 187             (pdev->device == PCI_DEVICE_ID_INTEL_CHERRYVIEW_XHCI ||
 188              pdev->device == PCI_DEVICE_ID_INTEL_APL_XHCI ||
 189              pdev->device == PCI_DEVICE_ID_INTEL_DNV_XHCI))
 190                 xhci->quirks |= XHCI_MISSING_CAS;
 191
 192         if (pdev->vendor == PCI_VENDOR_ID_ETRON &&
 193                         pdev->device == PCI_DEVICE_ID_EJ168) {
 194                 xhci->quirks |= XHCI_RESET_ON_RESUME;
 195                 xhci->quirks |= XHCI_TRUST_TX_LENGTH;
 196                 xhci->quirks |= XHCI_BROKEN_STREAMS;
 197         }
 198         if (pdev->vendor == PCI_VENDOR_ID_RENESAS &&
 199             pdev->device == 0x0014) {
 200                 xhci->quirks |= XHCI_TRUST_TX_LENGTH;
 201                 xhci->quirks |= XHCI_ZERO_64B_REGS;
 202         }
 203         if (pdev->vendor == PCI_VENDOR_ID_RENESAS &&
 204             pdev->device == 0x0015) {
 205                 xhci->quirks |= XHCI_RESET_ON_RESUME;
 206                 xhci->quirks |= XHCI_ZERO_64B_REGS;
 207         }
 208         if (pdev->vendor == PCI_VENDOR_ID_VIA)
 209                 xhci->quirks |= XHCI_RESET_ON_RESUME;
 210
 211         /* See https://bugzilla.kernel.org/show_bug.cgi?id=79511 */
 212         if (pdev->vendor == PCI_VENDOR_ID_VIA &&
 213                         pdev->device == 0x3432)
 214                 xhci->quirks |= XHCI_BROKEN_STREAMS;
 215
 216         if (pdev->vendor == PCI_VENDOR_ID_ASMEDIA &&
 217                         pdev->device == 0x1042)
 218                 xhci->quirks |= XHCI_BROKEN_STREAMS;
 219         if (pdev->vendor == PCI_VENDOR_ID_ASMEDIA &&
 220                         pdev->device == 0x1142)
 221                 xhci->quirks |= XHCI_TRUST_TX_LENGTH;
 222
 223         if (pdev->vendor == PCI_VENDOR_ID_ASMEDIA &&
 224                 pdev->device == PCI_DEVICE_ID_ASMEDIA_1042A_XHCI)
 225                 xhci->quirks |= XHCI_ASMEDIA_MODIFY_FLOWCONTROL;
 226
 227         if (pdev->vendor == PCI_VENDOR_ID_TI && pdev->device == 0x8241)
 228                 xhci->quirks |= XHCI_LIMIT_ENDPOINT_INTERVAL_7;
 229
 230         if (xhci->quirks & XHCI_RESET_ON_RESUME)
 231                 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
 232                                 "QUIRK: Resetting on resume");
 233 }
 234
 235 #ifdef CONFIG_ACPI
 236 static void xhci_pme_acpi_rtd3_enable(struct pci_dev *dev)
 237 {
 238         static const guid_t intel_dsm_guid =
 239                 GUID_INIT(0xac340cb7, 0xe901, 0x45bf,
 240                           0xb7, 0xe6, 0x2b, 0x34, 0xec, 0x93, 0x1e, 0x23);
 241         union acpi_object *obj;
 242
 243         obj = acpi_evaluate_dsm(ACPI_HANDLE(&dev->dev), &intel_dsm_guid, 3, 1,
 244                                 NULL);
 245         ACPI_FREE(obj);
 246 }
 247 #else
 248 static void xhci_pme_acpi_rtd3_enable(struct pci_dev *dev) { }
 249 #endif /* CONFIG_ACPI */
 250
 251 /* called during probe() after chip reset completes */
 252 static int xhci_pci_setup(struct usb_hcd *hcd)
 253 {
 254         struct xhci_hcd         *xhci;
 255         struct pci_dev          *pdev = to_pci_dev(hcd->self.controller);
 256         int                     retval;
 257
 258         xhci = hcd_to_xhci(hcd);
 259         if (!xhci->sbrn)
 260                 pci_read_config_byte(pdev, XHCI_SBRN_OFFSET, &xhci->sbrn);
 261
 262         /* imod_interval is the interrupt moderation value in nanoseconds. */
 263         xhci->imod_interval = 40000;
 264
 265         retval = xhci_gen_setup(hcd, xhci_pci_quirks);
 266         if (retval)
 267                 return retval;
 268
 269         if (!usb_hcd_is_primary_hcd(hcd))
 270                 return 0;
 271
 272         xhci_dbg(xhci, "Got SBRN %u\n", (unsigned int) xhci->sbrn);
 273
 274         /* Find any debug ports */
 275         return xhci_pci_reinit(xhci, pdev);
 276 }
 277
 278 /*
 279  * We need to register our own PCI probe function (instead of the USB core's
 280  * function) in order to create a second roothub under xHCI.
 281  */
 282 static int xhci_pci_probe(struct pci_dev *dev, const struct pci_device_id *id)
 283 {
 284         int retval;
 285         struct xhci_hcd *xhci;
 286         struct hc_driver *driver;
 287         struct usb_hcd *hcd;
 288
 289         driver = (struct hc_driver *)id->driver_data;
 290
 291         /* Prevent runtime suspending between USB-2 and USB-3 initialization */
 292         pm_runtime_get_noresume(&dev->dev);
 293
 294         /* Register the USB 2.0 roothub.
 295          * FIXME: USB core must know to register the USB 2.0 roothub first.
 296          * This is sort of silly, because we could just set the HCD driver flags
 297          * to say USB 2.0, but I'm not sure what the implications would be in
 298          * the other parts of the HCD code.
 299          */
 300         retval = usb_hcd_pci_probe(dev, id);
 301
 302         if (retval)
 303                 goto put_runtime_pm;
 304
 305         /* USB 2.0 roothub is stored in the PCI device now. */
 306         hcd = dev_get_drvdata(&dev->dev);
 307         xhci = hcd_to_xhci(hcd);
 308         xhci->shared_hcd = usb_create_shared_hcd(driver, &dev->dev,
 309                                 pci_name(dev), hcd);
 310         if (!xhci->shared_hcd) {
 311                 retval = -ENOMEM;
 312                 goto dealloc_usb2_hcd;
 313         }
 314
 315         retval = xhci_ext_cap_init(xhci);
 316         if (retval)
 317                 goto put_usb3_hcd;
 318
 319         retval = usb_add_hcd(xhci->shared_hcd, dev->irq,
 320                         IRQF_SHARED);
 321         if (retval)
 322                 goto put_usb3_hcd;
 323         /* Roothub already marked as USB 3.0 speed */
 324
 325         if (!(xhci->quirks & XHCI_BROKEN_STREAMS) &&
 326                         HCC_MAX_PSA(xhci->hcc_params) >= 4)
 327                 xhci->shared_hcd->can_do_streams = 1;
 328
 329         if (xhci->quirks & XHCI_PME_STUCK_QUIRK)
 330                 xhci_pme_acpi_rtd3_enable(dev);
 331
 332         /* USB-2 and USB-3 roothubs initialized, allow runtime pm suspend */
 333         pm_runtime_put_noidle(&dev->dev);
 334
 335         return 0;
 336
 337 put_usb3_hcd:
 338         usb_put_hcd(xhci->shared_hcd);
 339 dealloc_usb2_hcd:
 340         usb_hcd_pci_remove(dev);
 341 put_runtime_pm:
 342         pm_runtime_put_noidle(&dev->dev);
 343         return retval;
 344 }
 345
 346 static void xhci_pci_remove(struct pci_dev *dev)
 347 {
 348         struct xhci_hcd *xhci;
 349
 350         xhci = hcd_to_xhci(pci_get_drvdata(dev));
 351         xhci->xhc_state |= XHCI_STATE_REMOVING;
 352         if (xhci->shared_hcd) {
 353                 usb_remove_hcd(xhci->shared_hcd);
 354                 usb_put_hcd(xhci->shared_hcd);
 355         }
 356
 357         /* Workaround for spurious wakeups at shutdown with HSW */
 358         if (xhci->quirks & XHCI_SPURIOUS_WAKEUP)
 359                 pci_set_power_state(dev, PCI_D3hot);
 360
 361         usb_hcd_pci_remove(dev);
 362 }
 363
 364 #ifdef CONFIG_PM
 365 /*
 366  * In some Intel xHCI controllers, in order to get D3 working,
 367  * through a vendor specific SSIC CONFIG register at offset 0x883c,
 368  * SSIC PORT need to be marked as "unused" before putting xHCI
 369  * into D3. After D3 exit, the SSIC port need to be marked as "used".
 370  * Without this change, xHCI might not enter D3 state.
 371  */
 372 static void xhci_ssic_port_unused_quirk(struct usb_hcd *hcd, bool suspend)
 373 {
 374         struct xhci_hcd *xhci = hcd_to_xhci(hcd);
 375         u32 val;
 376         void __iomem *reg;
 377         int i;
 378
 379         for (i = 0; i < SSIC_PORT_NUM; i++) {
 380                 reg = (void __iomem *) xhci->cap_regs +
 381                                 SSIC_PORT_CFG2 +
 382                                 i * SSIC_PORT_CFG2_OFFSET;
 383
 384                 /* Notify SSIC that SSIC profile programming is not done. */
 385                 val = readl(reg) & ~PROG_DONE;
 386                 writel(val, reg);
 387
 388                 /* Mark SSIC port as unused(suspend) or used(resume) */
 389                 val = readl(reg);
 390                 if (suspend)
 391                         val |= SSIC_PORT_UNUSED;
 392                 else
 393                         val &= ~SSIC_PORT_UNUSED;
 394                 writel(val, reg);
 395
 396                 /* Notify SSIC that SSIC profile programming is done */
 397                 val = readl(reg) | PROG_DONE;
 398                 writel(val, reg);
 399                 readl(reg);
 400         }
 401 }
 402
 403 /*
 404  * Make sure PME works on some Intel xHCI controllers by writing 1 to clear
 405  * the Internal PME flag bit in vendor specific PMCTRL register at offset 0x80a4
 406  */
 407 static void xhci_pme_quirk(struct usb_hcd *hcd)
 408 {
 409         struct xhci_hcd *xhci = hcd_to_xhci(hcd);
 410         void __iomem *reg;
 411         u32 val;
 412
 413         reg = (void __iomem *) xhci->cap_regs + 0x80a4;
 414         val = readl(reg);
 415         writel(val | BIT(28), reg);
 416         readl(reg);
 417 }
 418
 419 static int xhci_pci_suspend(struct usb_hcd *hcd, bool do_wakeup)
 420 {
 421         struct xhci_hcd *xhci = hcd_to_xhci(hcd);
 422         struct pci_dev          *pdev = to_pci_dev(hcd->self.controller);
 423         int                     ret;
 424
 425         /*
 426          * Systems with the TI redriver that loses port status change events
 427          * need to have the registers polled during D3, so avoid D3cold.
 428          */
 429         if (xhci->quirks & XHCI_COMP_MODE_QUIRK)
 430                 pci_d3cold_disable(pdev);
 431
 432         if (xhci->quirks & XHCI_PME_STUCK_QUIRK)
 433                 xhci_pme_quirk(hcd);
 434
 435         if (xhci->quirks & XHCI_SSIC_PORT_UNUSED)
 436                 xhci_ssic_port_unused_quirk(hcd, true);
 437
 438         ret = xhci_suspend(xhci, do_wakeup);
 439         if (ret && (xhci->quirks & XHCI_SSIC_PORT_UNUSED))
 440                 xhci_ssic_port_unused_quirk(hcd, false);
 441
 442         return ret;
 443 }
 444
 445 static int xhci_pci_resume(struct usb_hcd *hcd, bool hibernated)
 446 {
 447         struct xhci_hcd         *xhci = hcd_to_xhci(hcd);
 448         struct pci_dev          *pdev = to_pci_dev(hcd->self.controller);
 449         int                     retval = 0;
 450
 451         /* The BIOS on systems with the Intel Panther Point chipset may or may
 452          * not support xHCI natively.  That means that during system resume, it
 453          * may switch the ports back to EHCI so that users can use their
 454          * keyboard to select a kernel from GRUB after resume from hibernate.
 455          *
 456          * The BIOS is supposed to remember whether the OS had xHCI ports
 457          * enabled before resume, and switch the ports back to xHCI when the
 458          * BIOS/OS semaphore is written, but we all know we can't trust BIOS
 459          * writers.
 460          *
 461          * Unconditionally switch the ports back to xHCI after a system resume.
 462          * It should not matter whether the EHCI or xHCI controller is
 463          * resumed first. It's enough to do the switchover in xHCI because
 464          * USB core won't notice anything as the hub driver doesn't start
 465          * running again until after all the devices (including both EHCI and
 466          * xHCI host controllers) have been resumed.
 467          */
 468
 469         if (pdev->vendor == PCI_VENDOR_ID_INTEL)
 470                 usb_enable_intel_xhci_ports(pdev);
 471
 472         if (xhci->quirks & XHCI_SSIC_PORT_UNUSED)
 473                 xhci_ssic_port_unused_quirk(hcd, false);
 474
 475         if (xhci->quirks & XHCI_PME_STUCK_QUIRK)
 476                 xhci_pme_quirk(hcd);
 477
 478         retval = xhci_resume(xhci, hibernated);
 479         return retval;
 480 }
 481 #endif /* CONFIG_PM */
 482
 483 /*-------------------------------------------------------------------------*/
 484
 485 /* PCI driver selection metadata; PCI hotplugging uses this */
 486 static const struct pci_device_id pci_ids[] = { {
 487         /* handle any USB 3.0 xHCI controller */
 488         PCI_DEVICE_CLASS(PCI_CLASS_SERIAL_USB_XHCI, ~0),
 489         .driver_data =  (unsigned long) &xhci_pci_hc_driver,
 490         },
 491         { /* end: all zeroes */ }
 492 };
 493 MODULE_DEVICE_TABLE(pci, pci_ids);
 494
 495 /* pci driver glue; this is a "new style" PCI driver module */
 496 static struct pci_driver xhci_pci_driver = {
 497         .name =         (char *) hcd_name,
 498         .id_table =     pci_ids,
 499
 500         .probe =        xhci_pci_probe,
 501         .remove =       xhci_pci_remove,
 502         /* suspend and resume implemented later */
 503
 504         .shutdown =     usb_hcd_pci_shutdown,
 505 #ifdef CONFIG_PM
 506         .driver = {
 507                 .pm = &usb_hcd_pci_pm_ops
 508         },
 509 #endif
 510 };
 511
 512 static int __init xhci_pci_init(void)
 513 {
 514         xhci_init_driver(&xhci_pci_hc_driver, &xhci_pci_overrides);
 515 #ifdef CONFIG_PM
 516         xhci_pci_hc_driver.pci_suspend = xhci_pci_suspend;
 517         xhci_pci_hc_driver.pci_resume = xhci_pci_resume;
 518 #endif
 519         return pci_register_driver(&xhci_pci_driver);
 520 }
 521 module_init(xhci_pci_init);
 522
 523 static void __exit xhci_pci_exit(void)
 524 {
 525         pci_unregister_driver(&xhci_pci_driver);
 526 }
 527 module_exit(xhci_pci_exit);
 528
 529 MODULE_DESCRIPTION("xHCI PCI Host Controller Driver");
 530 MODULE_LICENSE("GPL");