drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c

   1 /*
   2  * Copyright 2017 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: Rafał Miłecki <[email protected]>
  23  *          Alex Deucher <[email protected]>
  24  */
  25
  26 #include <drm/drm_debugfs.h>
  27
  28 #include "amdgpu.h"
  29 #include "amdgpu_drv.h"
  30 #include "amdgpu_pm.h"
  31 #include "amdgpu_dpm.h"
  32 #include "amdgpu_display.h"
  33 #include "amdgpu_smu.h"
  34 #include "atom.h"
  35 #include <linux/power_supply.h>
  36 #include <linux/pci.h>
  37 #include <linux/hwmon.h>
  38 #include <linux/hwmon-sysfs.h>
  39 #include <linux/nospec.h>
  40 #include <linux/pm_runtime.h>
  41 #include "hwmgr.h"
  42 #define WIDTH_4K 3840
  43
  44 static const struct cg_flag_name clocks[] = {
  45         {AMD_CG_SUPPORT_GFX_MGCG, "Graphics Medium Grain Clock Gating"},
  46         {AMD_CG_SUPPORT_GFX_MGLS, "Graphics Medium Grain memory Light Sleep"},
  47         {AMD_CG_SUPPORT_GFX_CGCG, "Graphics Coarse Grain Clock Gating"},
  48         {AMD_CG_SUPPORT_GFX_CGLS, "Graphics Coarse Grain memory Light Sleep"},
  49         {AMD_CG_SUPPORT_GFX_CGTS, "Graphics Coarse Grain Tree Shader Clock Gating"},
  50         {AMD_CG_SUPPORT_GFX_CGTS_LS, "Graphics Coarse Grain Tree Shader Light Sleep"},
  51         {AMD_CG_SUPPORT_GFX_CP_LS, "Graphics Command Processor Light Sleep"},
  52         {AMD_CG_SUPPORT_GFX_RLC_LS, "Graphics Run List Controller Light Sleep"},
  53         {AMD_CG_SUPPORT_GFX_3D_CGCG, "Graphics 3D Coarse Grain Clock Gating"},
  54         {AMD_CG_SUPPORT_GFX_3D_CGLS, "Graphics 3D Coarse Grain memory Light Sleep"},
  55         {AMD_CG_SUPPORT_MC_LS, "Memory Controller Light Sleep"},
  56         {AMD_CG_SUPPORT_MC_MGCG, "Memory Controller Medium Grain Clock Gating"},
  57         {AMD_CG_SUPPORT_SDMA_LS, "System Direct Memory Access Light Sleep"},
  58         {AMD_CG_SUPPORT_SDMA_MGCG, "System Direct Memory Access Medium Grain Clock Gating"},
  59         {AMD_CG_SUPPORT_BIF_MGCG, "Bus Interface Medium Grain Clock Gating"},
  60         {AMD_CG_SUPPORT_BIF_LS, "Bus Interface Light Sleep"},
  61         {AMD_CG_SUPPORT_UVD_MGCG, "Unified Video Decoder Medium Grain Clock Gating"},
  62         {AMD_CG_SUPPORT_VCE_MGCG, "Video Compression Engine Medium Grain Clock Gating"},
  63         {AMD_CG_SUPPORT_HDP_LS, "Host Data Path Light Sleep"},
  64         {AMD_CG_SUPPORT_HDP_MGCG, "Host Data Path Medium Grain Clock Gating"},
  65         {AMD_CG_SUPPORT_DRM_MGCG, "Digital Right Management Medium Grain Clock Gating"},
  66         {AMD_CG_SUPPORT_DRM_LS, "Digital Right Management Light Sleep"},
  67         {AMD_CG_SUPPORT_ROM_MGCG, "Rom Medium Grain Clock Gating"},
  68         {AMD_CG_SUPPORT_DF_MGCG, "Data Fabric Medium Grain Clock Gating"},
  69
  70         {AMD_CG_SUPPORT_ATHUB_MGCG, "Address Translation Hub Medium Grain Clock Gating"},
  71         {AMD_CG_SUPPORT_ATHUB_LS, "Address Translation Hub Light Sleep"},
  72         {0, NULL},
  73 };
  74
  75 static const struct hwmon_temp_label {
  76         enum PP_HWMON_TEMP channel;
  77         const char *label;
  78 } temp_label[] = {
  79         {PP_TEMP_EDGE, "edge"},
  80         {PP_TEMP_JUNCTION, "junction"},
  81         {PP_TEMP_MEM, "mem"},
  82 };
  83
  84 void amdgpu_pm_acpi_event_handler(struct amdgpu_device *adev)
  85 {
  86         if (adev->pm.dpm_enabled) {
  87                 mutex_lock(&adev->pm.mutex);
  88                 if (power_supply_is_system_supplied() > 0)
  89                         adev->pm.ac_power = true;
  90                 else
  91                         adev->pm.ac_power = false;
  92                 if (adev->powerplay.pp_funcs->enable_bapm)
  93                         amdgpu_dpm_enable_bapm(adev, adev->pm.ac_power);
  94                 mutex_unlock(&adev->pm.mutex);
  95
  96                 if (is_support_sw_smu(adev))
  97                         smu_set_ac_dc(&adev->smu);
  98         }
  99 }
 100
 101 int amdgpu_dpm_read_sensor(struct amdgpu_device *adev, enum amd_pp_sensors sensor,
 102                            void *data, uint32_t *size)
 103 {
 104         int ret = 0;
 105
 106         if (!data || !size)
 107                 return -EINVAL;
 108
 109         if (is_support_sw_smu(adev))
 110                 ret = smu_read_sensor(&adev->smu, sensor, data, size);
 111         else {
 112                 if (adev->powerplay.pp_funcs && adev->powerplay.pp_funcs->read_sensor)
 113                         ret = adev->powerplay.pp_funcs->read_sensor((adev)->powerplay.pp_handle,
 114                                                                     sensor, data, size);
 115                 else
 116                         ret = -EINVAL;
 117         }
 118
 119         return ret;
 120 }
 121
 122 /**
 123  * DOC: power_dpm_state
 124  *
 125  * The power_dpm_state file is a legacy interface and is only provided for
 126  * backwards compatibility. The amdgpu driver provides a sysfs API for adjusting
 127  * certain power related parameters.  The file power_dpm_state is used for this.
 128  * It accepts the following arguments:
 129  *
 130  * - battery
 131  *
 132  * - balanced
 133  *
 134  * - performance
 135  *
 136  * battery
 137  *
 138  * On older GPUs, the vbios provided a special power state for battery
 139  * operation.  Selecting battery switched to this state.  This is no
 140  * longer provided on newer GPUs so the option does nothing in that case.
 141  *
 142  * balanced
 143  *
 144  * On older GPUs, the vbios provided a special power state for balanced
 145  * operation.  Selecting balanced switched to this state.  This is no
 146  * longer provided on newer GPUs so the option does nothing in that case.
 147  *
 148  * performance
 149  *
 150  * On older GPUs, the vbios provided a special power state for performance
 151  * operation.  Selecting performance switched to this state.  This is no
 152  * longer provided on newer GPUs so the option does nothing in that case.
 153  *
 154  */
 155
 156 static ssize_t amdgpu_get_dpm_state(struct device *dev,
 157                                     struct device_attribute *attr,
 158                                     char *buf)
 159 {
 160         struct drm_device *ddev = dev_get_drvdata(dev);
 161         struct amdgpu_device *adev = ddev->dev_private;
 162         enum amd_pm_state_type pm;
 163         int ret;
 164
 165         if (amdgpu_sriov_vf(adev) && !amdgpu_sriov_is_pp_one_vf(adev))
 166                 return 0;
 167
 168         ret = pm_runtime_get_sync(ddev->dev);
 169         if (ret < 0)
 170                 return ret;
 171
 172         if (is_support_sw_smu(adev)) {
 173                 if (adev->smu.ppt_funcs->get_current_power_state)
 174                         pm = smu_get_current_power_state(&adev->smu);
 175                 else
 176                         pm = adev->pm.dpm.user_state;
 177         } else if (adev->powerplay.pp_funcs->get_current_power_state) {
 178                 pm = amdgpu_dpm_get_current_power_state(adev);
 179         } else {
 180                 pm = adev->pm.dpm.user_state;
 181         }
 182
 183         pm_runtime_mark_last_busy(ddev->dev);
 184         pm_runtime_put_autosuspend(ddev->dev);
 185
 186         return snprintf(buf, PAGE_SIZE, "%s\n",
 187                         (pm == POWER_STATE_TYPE_BATTERY) ? "battery" :
 188                         (pm == POWER_STATE_TYPE_BALANCED) ? "balanced" : "performance");
 189 }
 190
 191 static ssize_t amdgpu_set_dpm_state(struct device *dev,
 192                                     struct device_attribute *attr,
 193                                     const char *buf,
 194                                     size_t count)
 195 {
 196         struct drm_device *ddev = dev_get_drvdata(dev);
 197         struct amdgpu_device *adev = ddev->dev_private;
 198         enum amd_pm_state_type  state;
 199         int ret;
 200
 201         if (amdgpu_sriov_vf(adev) && !amdgpu_sriov_is_pp_one_vf(adev))
 202                 return -EINVAL;
 203
 204         if (strncmp("battery", buf, strlen("battery")) == 0)
 205                 state = POWER_STATE_TYPE_BATTERY;
 206         else if (strncmp("balanced", buf, strlen("balanced")) == 0)
 207                 state = POWER_STATE_TYPE_BALANCED;
 208         else if (strncmp("performance", buf, strlen("performance")) == 0)
 209                 state = POWER_STATE_TYPE_PERFORMANCE;
 210         else
 211                 return -EINVAL;
 212
 213         ret = pm_runtime_get_sync(ddev->dev);
 214         if (ret < 0)
 215                 return ret;
 216
 217         if (is_support_sw_smu(adev)) {
 218                 mutex_lock(&adev->pm.mutex);
 219                 adev->pm.dpm.user_state = state;
 220                 mutex_unlock(&adev->pm.mutex);
 221         } else if (adev->powerplay.pp_funcs->dispatch_tasks) {
 222                 amdgpu_dpm_dispatch_task(adev, AMD_PP_TASK_ENABLE_USER_STATE, &state);
 223         } else {
 224                 mutex_lock(&adev->pm.mutex);
 225                 adev->pm.dpm.user_state = state;
 226                 mutex_unlock(&adev->pm.mutex);
 227
 228                 amdgpu_pm_compute_clocks(adev);
 229         }
 230         pm_runtime_mark_last_busy(ddev->dev);
 231         pm_runtime_put_autosuspend(ddev->dev);
 232
 233         return count;
 234 }
 235
 236
 237 /**
 238  * DOC: power_dpm_force_performance_level
 239  *
 240  * The amdgpu driver provides a sysfs API for adjusting certain power
 241  * related parameters.  The file power_dpm_force_performance_level is
 242  * used for this.  It accepts the following arguments:
 243  *
 244  * - auto
 245  *
 246  * - low
 247  *
 248  * - high
 249  *
 250  * - manual
 251  *
 252  * - profile_standard
 253  *
 254  * - profile_min_sclk
 255  *
 256  * - profile_min_mclk
 257  *
 258  * - profile_peak
 259  *
 260  * auto
 261  *
 262  * When auto is selected, the driver will attempt to dynamically select
 263  * the optimal power profile for current conditions in the driver.
 264  *
 265  * low
 266  *
 267  * When low is selected, the clocks are forced to the lowest power state.
 268  *
 269  * high
 270  *
 271  * When high is selected, the clocks are forced to the highest power state.
 272  *
 273  * manual
 274  *
 275  * When manual is selected, the user can manually adjust which power states
 276  * are enabled for each clock domain via the sysfs pp_dpm_mclk, pp_dpm_sclk,
 277  * and pp_dpm_pcie files and adjust the power state transition heuristics
 278  * via the pp_power_profile_mode sysfs file.
 279  *
 280  * profile_standard
 281  * profile_min_sclk
 282  * profile_min_mclk
 283  * profile_peak
 284  *
 285  * When the profiling modes are selected, clock and power gating are
 286  * disabled and the clocks are set for different profiling cases. This
 287  * mode is recommended for profiling specific work loads where you do
 288  * not want clock or power gating for clock fluctuation to interfere
 289  * with your results. profile_standard sets the clocks to a fixed clock
 290  * level which varies from asic to asic.  profile_min_sclk forces the sclk
 291  * to the lowest level.  profile_min_mclk forces the mclk to the lowest level.
 292  * profile_peak sets all clocks (mclk, sclk, pcie) to the highest levels.
 293  *
 294  */
 295
 296 static ssize_t amdgpu_get_dpm_forced_performance_level(struct device *dev,
 297                                                 struct device_attribute *attr,
 298                                                                 char *buf)
 299 {
 300         struct drm_device *ddev = dev_get_drvdata(dev);
 301         struct amdgpu_device *adev = ddev->dev_private;
 302         enum amd_dpm_forced_level level = 0xff;
 303         int ret;
 304
 305         if (amdgpu_sriov_vf(adev) && !amdgpu_sriov_is_pp_one_vf(adev))
 306                 return 0;
 307
 308         ret = pm_runtime_get_sync(ddev->dev);
 309         if (ret < 0)
 310                 return ret;
 311
 312         if (is_support_sw_smu(adev))
 313                 level = smu_get_performance_level(&adev->smu);
 314         else if (adev->powerplay.pp_funcs->get_performance_level)
 315                 level = amdgpu_dpm_get_performance_level(adev);
 316         else
 317                 level = adev->pm.dpm.forced_level;
 318
 319         pm_runtime_mark_last_busy(ddev->dev);
 320         pm_runtime_put_autosuspend(ddev->dev);
 321
 322         return snprintf(buf, PAGE_SIZE, "%s\n",
 323                         (level == AMD_DPM_FORCED_LEVEL_AUTO) ? "auto" :
 324                         (level == AMD_DPM_FORCED_LEVEL_LOW) ? "low" :
 325                         (level == AMD_DPM_FORCED_LEVEL_HIGH) ? "high" :
 326                         (level == AMD_DPM_FORCED_LEVEL_MANUAL) ? "manual" :
 327                         (level == AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD) ? "profile_standard" :
 328                         (level == AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK) ? "profile_min_sclk" :
 329                         (level == AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK) ? "profile_min_mclk" :
 330                         (level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK) ? "profile_peak" :
 331                         "unknown");
 332 }
 333
 334 static ssize_t amdgpu_set_dpm_forced_performance_level(struct device *dev,
 335                                                        struct device_attribute *attr,
 336                                                        const char *buf,
 337                                                        size_t count)
 338 {
 339         struct drm_device *ddev = dev_get_drvdata(dev);
 340         struct amdgpu_device *adev = ddev->dev_private;
 341         enum amd_dpm_forced_level level;
 342         enum amd_dpm_forced_level current_level = 0xff;
 343         int ret = 0;
 344
 345         if (amdgpu_sriov_vf(adev) && !amdgpu_sriov_is_pp_one_vf(adev))
 346                 return -EINVAL;
 347
 348         if (strncmp("low", buf, strlen("low")) == 0) {
 349                 level = AMD_DPM_FORCED_LEVEL_LOW;
 350         } else if (strncmp("high", buf, strlen("high")) == 0) {
 351                 level = AMD_DPM_FORCED_LEVEL_HIGH;
 352         } else if (strncmp("auto", buf, strlen("auto")) == 0) {
 353                 level = AMD_DPM_FORCED_LEVEL_AUTO;
 354         } else if (strncmp("manual", buf, strlen("manual")) == 0) {
 355                 level = AMD_DPM_FORCED_LEVEL_MANUAL;
 356         } else if (strncmp("profile_exit", buf, strlen("profile_exit")) == 0) {
 357                 level = AMD_DPM_FORCED_LEVEL_PROFILE_EXIT;
 358         } else if (strncmp("profile_standard", buf, strlen("profile_standard")) == 0) {
 359                 level = AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD;
 360         } else if (strncmp("profile_min_sclk", buf, strlen("profile_min_sclk")) == 0) {
 361                 level = AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK;
 362         } else if (strncmp("profile_min_mclk", buf, strlen("profile_min_mclk")) == 0) {
 363                 level = AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK;
 364         } else if (strncmp("profile_peak", buf, strlen("profile_peak")) == 0) {
 365                 level = AMD_DPM_FORCED_LEVEL_PROFILE_PEAK;
 366         }  else {
 367                 return -EINVAL;
 368         }
 369
 370         ret = pm_runtime_get_sync(ddev->dev);
 371         if (ret < 0)
 372                 return ret;
 373
 374         if (is_support_sw_smu(adev))
 375                 current_level = smu_get_performance_level(&adev->smu);
 376         else if (adev->powerplay.pp_funcs->get_performance_level)
 377                 current_level = amdgpu_dpm_get_performance_level(adev);
 378
 379         if (current_level == level) {
 380                 pm_runtime_mark_last_busy(ddev->dev);
 381                 pm_runtime_put_autosuspend(ddev->dev);
 382                 return count;
 383         }
 384
 385         /* profile_exit setting is valid only when current mode is in profile mode */
 386         if (!(current_level & (AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD |
 387             AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK |
 388             AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK |
 389             AMD_DPM_FORCED_LEVEL_PROFILE_PEAK)) &&
 390             (level == AMD_DPM_FORCED_LEVEL_PROFILE_EXIT)) {
 391                 pr_err("Currently not in any profile mode!\n");
 392                 pm_runtime_mark_last_busy(ddev->dev);
 393                 pm_runtime_put_autosuspend(ddev->dev);
 394                 return -EINVAL;
 395         }
 396
 397         if (is_support_sw_smu(adev)) {
 398                 ret = smu_force_performance_level(&adev->smu, level);
 399                 if (ret) {
 400                         pm_runtime_mark_last_busy(ddev->dev);
 401                         pm_runtime_put_autosuspend(ddev->dev);
 402                         return -EINVAL;
 403                 }
 404         } else if (adev->powerplay.pp_funcs->force_performance_level) {
 405                 mutex_lock(&adev->pm.mutex);
 406                 if (adev->pm.dpm.thermal_active) {
 407                         mutex_unlock(&adev->pm.mutex);
 408                         pm_runtime_mark_last_busy(ddev->dev);
 409                         pm_runtime_put_autosuspend(ddev->dev);
 410                         return -EINVAL;
 411                 }
 412                 ret = amdgpu_dpm_force_performance_level(adev, level);
 413                 if (ret) {
 414                         mutex_unlock(&adev->pm.mutex);
 415                         pm_runtime_mark_last_busy(ddev->dev);
 416                         pm_runtime_put_autosuspend(ddev->dev);
 417                         return -EINVAL;
 418                 } else {
 419                         adev->pm.dpm.forced_level = level;
 420                 }
 421                 mutex_unlock(&adev->pm.mutex);
 422         }
 423         pm_runtime_mark_last_busy(ddev->dev);
 424         pm_runtime_put_autosuspend(ddev->dev);
 425
 426         return count;
 427 }
 428
 429 static ssize_t amdgpu_get_pp_num_states(struct device *dev,
 430                 struct device_attribute *attr,
 431                 char *buf)
 432 {
 433         struct drm_device *ddev = dev_get_drvdata(dev);
 434         struct amdgpu_device *adev = ddev->dev_private;
 435         struct pp_states_info data;
 436         int i, buf_len, ret;
 437
 438         ret = pm_runtime_get_sync(ddev->dev);
 439         if (ret < 0)
 440                 return ret;
 441
 442         if (is_support_sw_smu(adev)) {
 443                 ret = smu_get_power_num_states(&adev->smu, &data);
 444                 if (ret)
 445                         return ret;
 446         } else if (adev->powerplay.pp_funcs->get_pp_num_states)
 447                 amdgpu_dpm_get_pp_num_states(adev, &data);
 448
 449         pm_runtime_mark_last_busy(ddev->dev);
 450         pm_runtime_put_autosuspend(ddev->dev);
 451
 452         buf_len = snprintf(buf, PAGE_SIZE, "states: %d\n", data.nums);
 453         for (i = 0; i < data.nums; i++)
 454                 buf_len += snprintf(buf + buf_len, PAGE_SIZE, "%d %s\n", i,
 455                                 (data.states[i] == POWER_STATE_TYPE_INTERNAL_BOOT) ? "boot" :
 456                                 (data.states[i] == POWER_STATE_TYPE_BATTERY) ? "battery" :
 457                                 (data.states[i] == POWER_STATE_TYPE_BALANCED) ? "balanced" :
 458                                 (data.states[i] == POWER_STATE_TYPE_PERFORMANCE) ? "performance" : "default");
 459
 460         return buf_len;
 461 }
 462
 463 static ssize_t amdgpu_get_pp_cur_state(struct device *dev,
 464                 struct device_attribute *attr,
 465                 char *buf)
 466 {
 467         struct drm_device *ddev = dev_get_drvdata(dev);
 468         struct amdgpu_device *adev = ddev->dev_private;
 469         struct pp_states_info data;
 470         struct smu_context *smu = &adev->smu;
 471         enum amd_pm_state_type pm = 0;
 472         int i = 0, ret = 0;
 473
 474         if (amdgpu_sriov_vf(adev) && !amdgpu_sriov_is_pp_one_vf(adev))
 475                 return 0;
 476
 477         ret = pm_runtime_get_sync(ddev->dev);
 478         if (ret < 0)
 479                 return ret;
 480
 481         if (is_support_sw_smu(adev)) {
 482                 pm = smu_get_current_power_state(smu);
 483                 ret = smu_get_power_num_states(smu, &data);
 484                 if (ret)
 485                         return ret;
 486         } else if (adev->powerplay.pp_funcs->get_current_power_state
 487                  && adev->powerplay.pp_funcs->get_pp_num_states) {
 488                 pm = amdgpu_dpm_get_current_power_state(adev);
 489                 amdgpu_dpm_get_pp_num_states(adev, &data);
 490         }
 491
 492         pm_runtime_mark_last_busy(ddev->dev);
 493         pm_runtime_put_autosuspend(ddev->dev);
 494
 495         for (i = 0; i < data.nums; i++) {
 496                 if (pm == data.states[i])
 497                         break;
 498         }
 499
 500         if (i == data.nums)
 501                 i = -EINVAL;
 502
 503         return snprintf(buf, PAGE_SIZE, "%d\n", i);
 504 }
 505
 506 static ssize_t amdgpu_get_pp_force_state(struct device *dev,
 507                 struct device_attribute *attr,
 508                 char *buf)
 509 {
 510         struct drm_device *ddev = dev_get_drvdata(dev);
 511         struct amdgpu_device *adev = ddev->dev_private;
 512
 513         if (amdgpu_sriov_vf(adev) && !amdgpu_sriov_is_pp_one_vf(adev))
 514                 return 0;
 515
 516         if (adev->pp_force_state_enabled)
 517                 return amdgpu_get_pp_cur_state(dev, attr, buf);
 518         else
 519                 return snprintf(buf, PAGE_SIZE, "\n");
 520 }
 521
 522 static ssize_t amdgpu_set_pp_force_state(struct device *dev,
 523                 struct device_attribute *attr,
 524                 const char *buf,
 525                 size_t count)
 526 {
 527         struct drm_device *ddev = dev_get_drvdata(dev);
 528         struct amdgpu_device *adev = ddev->dev_private;
 529         enum amd_pm_state_type state = 0;
 530         unsigned long idx;
 531         int ret;
 532
 533         if (amdgpu_sriov_vf(adev) && !amdgpu_sriov_is_pp_one_vf(adev))
 534                 return -EINVAL;
 535
 536         if (strlen(buf) == 1)
 537                 adev->pp_force_state_enabled = false;
 538         else if (is_support_sw_smu(adev))
 539                 adev->pp_force_state_enabled = false;
 540         else if (adev->powerplay.pp_funcs->dispatch_tasks &&
 541                         adev->powerplay.pp_funcs->get_pp_num_states) {
 542                 struct pp_states_info data;
 543
 544                 ret = kstrtoul(buf, 0, &idx);
 545                 if (ret || idx >= ARRAY_SIZE(data.states))
 546                         return -EINVAL;
 547
 548                 idx = array_index_nospec(idx, ARRAY_SIZE(data.states));
 549
 550                 amdgpu_dpm_get_pp_num_states(adev, &data);
 551                 state = data.states[idx];
 552
 553                 ret = pm_runtime_get_sync(ddev->dev);
 554                 if (ret < 0)
 555                         return ret;
 556
 557                 /* only set user selected power states */
 558                 if (state != POWER_STATE_TYPE_INTERNAL_BOOT &&
 559                     state != POWER_STATE_TYPE_DEFAULT) {
 560                         amdgpu_dpm_dispatch_task(adev,
 561                                         AMD_PP_TASK_ENABLE_USER_STATE, &state);
 562                         adev->pp_force_state_enabled = true;
 563                 }
 564                 pm_runtime_mark_last_busy(ddev->dev);
 565                 pm_runtime_put_autosuspend(ddev->dev);
 566         }
 567
 568         return count;
 569 }
 570
 571 /**
 572  * DOC: pp_table
 573  *
 574  * The amdgpu driver provides a sysfs API for uploading new powerplay
 575  * tables.  The file pp_table is used for this.  Reading the file
 576  * will dump the current power play table.  Writing to the file
 577  * will attempt to upload a new powerplay table and re-initialize
 578  * powerplay using that new table.
 579  *
 580  */
 581
 582 static ssize_t amdgpu_get_pp_table(struct device *dev,
 583                 struct device_attribute *attr,
 584                 char *buf)
 585 {
 586         struct drm_device *ddev = dev_get_drvdata(dev);
 587         struct amdgpu_device *adev = ddev->dev_private;
 588         char *table = NULL;
 589         int size, ret;
 590
 591         if (amdgpu_sriov_vf(adev) && !amdgpu_sriov_is_pp_one_vf(adev))
 592                 return 0;
 593
 594         ret = pm_runtime_get_sync(ddev->dev);
 595         if (ret < 0)
 596                 return ret;
 597
 598         if (is_support_sw_smu(adev)) {
 599                 size = smu_sys_get_pp_table(&adev->smu, (void **)&table);
 600                 pm_runtime_mark_last_busy(ddev->dev);
 601                 pm_runtime_put_autosuspend(ddev->dev);
 602                 if (size < 0)
 603                         return size;
 604         } else if (adev->powerplay.pp_funcs->get_pp_table) {
 605                 size = amdgpu_dpm_get_pp_table(adev, &table);
 606                 pm_runtime_mark_last_busy(ddev->dev);
 607                 pm_runtime_put_autosuspend(ddev->dev);
 608                 if (size < 0)
 609                         return size;
 610         } else {
 611                 pm_runtime_mark_last_busy(ddev->dev);
 612                 pm_runtime_put_autosuspend(ddev->dev);
 613                 return 0;
 614         }
 615
 616         if (size >= PAGE_SIZE)
 617                 size = PAGE_SIZE - 1;
 618
 619         memcpy(buf, table, size);
 620
 621         return size;
 622 }
 623
 624 static ssize_t amdgpu_set_pp_table(struct device *dev,
 625                 struct device_attribute *attr,
 626                 const char *buf,
 627                 size_t count)
 628 {
 629         struct drm_device *ddev = dev_get_drvdata(dev);
 630         struct amdgpu_device *adev = ddev->dev_private;
 631         int ret = 0;
 632
 633         if (amdgpu_sriov_vf(adev) && !amdgpu_sriov_is_pp_one_vf(adev))
 634                 return -EINVAL;
 635
 636         ret = pm_runtime_get_sync(ddev->dev);
 637         if (ret < 0)
 638                 return ret;
 639
 640         if (is_support_sw_smu(adev)) {
 641                 ret = smu_sys_set_pp_table(&adev->smu, (void *)buf, count);
 642                 if (ret) {
 643                         pm_runtime_mark_last_busy(ddev->dev);
 644                         pm_runtime_put_autosuspend(ddev->dev);
 645                         return ret;
 646                 }
 647         } else if (adev->powerplay.pp_funcs->set_pp_table)
 648                 amdgpu_dpm_set_pp_table(adev, buf, count);
 649
 650         pm_runtime_mark_last_busy(ddev->dev);
 651         pm_runtime_put_autosuspend(ddev->dev);
 652
 653         return count;
 654 }
 655
 656 /**
 657  * DOC: pp_od_clk_voltage
 658  *
 659  * The amdgpu driver provides a sysfs API for adjusting the clocks and voltages
 660  * in each power level within a power state.  The pp_od_clk_voltage is used for
 661  * this.
 662  *
 663  * < For Vega10 and previous ASICs >
 664  *
 665  * Reading the file will display:
 666  *
 667  * - a list of engine clock levels and voltages labeled OD_SCLK
 668  *
 669  * - a list of memory clock levels and voltages labeled OD_MCLK
 670  *
 671  * - a list of valid ranges for sclk, mclk, and voltage labeled OD_RANGE
 672  *
 673  * To manually adjust these settings, first select manual using
 674  * power_dpm_force_performance_level. Enter a new value for each
 675  * level by writing a string that contains "s/m level clock voltage" to
 676  * the file.  E.g., "s 1 500 820" will update sclk level 1 to be 500 MHz
 677  * at 820 mV; "m 0 350 810" will update mclk level 0 to be 350 MHz at
 678  * 810 mV.  When you have edited all of the states as needed, write
 679  * "c" (commit) to the file to commit your changes.  If you want to reset to the
 680  * default power levels, write "r" (reset) to the file to reset them.
 681  *
 682  *
 683  * < For Vega20 >
 684  *
 685  * Reading the file will display:
 686  *
 687  * - minimum and maximum engine clock labeled OD_SCLK
 688  *
 689  * - maximum memory clock labeled OD_MCLK
 690  *
 691  * - three <frequency, voltage> points labeled OD_VDDC_CURVE.
 692  *   They can be used to calibrate the sclk voltage curve.
 693  *
 694  * - a list of valid ranges for sclk, mclk, and voltage curve points
 695  *   labeled OD_RANGE
 696  *
 697  * To manually adjust these settings:
 698  *
 699  * - First select manual using power_dpm_force_performance_level
 700  *
 701  * - For clock frequency setting, enter a new value by writing a
 702  *   string that contains "s/m index clock" to the file. The index
 703  *   should be 0 if to set minimum clock. And 1 if to set maximum
 704  *   clock. E.g., "s 0 500" will update minimum sclk to be 500 MHz.
 705  *   "m 1 800" will update maximum mclk to be 800Mhz.
 706  *
 707  *   For sclk voltage curve, enter the new values by writing a
 708  *   string that contains "vc point clock voltage" to the file. The
 709  *   points are indexed by 0, 1 and 2. E.g., "vc 0 300 600" will
 710  *   update point1 with clock set as 300Mhz and voltage as
 711  *   600mV. "vc 2 1000 1000" will update point3 with clock set
 712  *   as 1000Mhz and voltage 1000mV.
 713  *
 714  * - When you have edited all of the states as needed, write "c" (commit)
 715  *   to the file to commit your changes
 716  *
 717  * - If you want to reset to the default power levels, write "r" (reset)
 718  *   to the file to reset them
 719  *
 720  */
 721
 722 static ssize_t amdgpu_set_pp_od_clk_voltage(struct device *dev,
 723                 struct device_attribute *attr,
 724                 const char *buf,
 725                 size_t count)
 726 {
 727         struct drm_device *ddev = dev_get_drvdata(dev);
 728         struct amdgpu_device *adev = ddev->dev_private;
 729         int ret;
 730         uint32_t parameter_size = 0;
 731         long parameter[64];
 732         char buf_cpy[128];
 733         char *tmp_str;
 734         char *sub_str;
 735         const char delimiter[3] = {' ', '\n', '\0'};
 736         uint32_t type;
 737
 738         if (amdgpu_sriov_vf(adev))
 739                 return -EINVAL;
 740
 741         if (count > 127)
 742                 return -EINVAL;
 743
 744         if (*buf == 's')
 745                 type = PP_OD_EDIT_SCLK_VDDC_TABLE;
 746         else if (*buf == 'm')
 747                 type = PP_OD_EDIT_MCLK_VDDC_TABLE;
 748         else if(*buf == 'r')
 749                 type = PP_OD_RESTORE_DEFAULT_TABLE;
 750         else if (*buf == 'c')
 751                 type = PP_OD_COMMIT_DPM_TABLE;
 752         else if (!strncmp(buf, "vc", 2))
 753                 type = PP_OD_EDIT_VDDC_CURVE;
 754         else
 755                 return -EINVAL;
 756
 757         memcpy(buf_cpy, buf, count+1);
 758
 759         tmp_str = buf_cpy;
 760
 761         if (type == PP_OD_EDIT_VDDC_CURVE)
 762                 tmp_str++;
 763         while (isspace(*++tmp_str));
 764
 765         while (tmp_str[0]) {
 766                 sub_str = strsep(&tmp_str, delimiter);
 767                 ret = kstrtol(sub_str, 0, &parameter[parameter_size]);
 768                 if (ret)
 769                         return -EINVAL;
 770                 parameter_size++;
 771
 772                 while (isspace(*tmp_str))
 773                         tmp_str++;
 774         }
 775
 776         ret = pm_runtime_get_sync(ddev->dev);
 777         if (ret < 0)
 778                 return ret;
 779
 780         if (is_support_sw_smu(adev)) {
 781                 ret = smu_od_edit_dpm_table(&adev->smu, type,
 782                                             parameter, parameter_size);
 783
 784                 if (ret) {
 785                         pm_runtime_mark_last_busy(ddev->dev);
 786                         pm_runtime_put_autosuspend(ddev->dev);
 787                         return -EINVAL;
 788                 }
 789         } else {
 790                 if (adev->powerplay.pp_funcs->odn_edit_dpm_table) {
 791                         ret = amdgpu_dpm_odn_edit_dpm_table(adev, type,
 792                                                 parameter, parameter_size);
 793                         if (ret) {
 794                                 pm_runtime_mark_last_busy(ddev->dev);
 795                                 pm_runtime_put_autosuspend(ddev->dev);
 796                                 return -EINVAL;
 797                         }
 798                 }
 799
 800                 if (type == PP_OD_COMMIT_DPM_TABLE) {
 801                         if (adev->powerplay.pp_funcs->dispatch_tasks) {
 802                                 amdgpu_dpm_dispatch_task(adev,
 803                                                 AMD_PP_TASK_READJUST_POWER_STATE,
 804                                                 NULL);
 805                                 pm_runtime_mark_last_busy(ddev->dev);
 806                                 pm_runtime_put_autosuspend(ddev->dev);
 807                                 return count;
 808                         } else {
 809                                 pm_runtime_mark_last_busy(ddev->dev);
 810                                 pm_runtime_put_autosuspend(ddev->dev);
 811                                 return -EINVAL;
 812                         }
 813                 }
 814         }
 815         pm_runtime_mark_last_busy(ddev->dev);
 816         pm_runtime_put_autosuspend(ddev->dev);
 817
 818         return count;
 819 }
 820
 821 static ssize_t amdgpu_get_pp_od_clk_voltage(struct device *dev,
 822                 struct device_attribute *attr,
 823                 char *buf)
 824 {
 825         struct drm_device *ddev = dev_get_drvdata(dev);
 826         struct amdgpu_device *adev = ddev->dev_private;
 827         ssize_t size;
 828         int ret;
 829
 830         if (amdgpu_sriov_vf(adev))
 831                 return 0;
 832
 833         ret = pm_runtime_get_sync(ddev->dev);
 834         if (ret < 0)
 835                 return ret;
 836
 837         if (is_support_sw_smu(adev)) {
 838                 size = smu_print_clk_levels(&adev->smu, SMU_OD_SCLK, buf);
 839                 size += smu_print_clk_levels(&adev->smu, SMU_OD_MCLK, buf+size);
 840                 size += smu_print_clk_levels(&adev->smu, SMU_OD_VDDC_CURVE, buf+size);
 841                 size += smu_print_clk_levels(&adev->smu, SMU_OD_RANGE, buf+size);
 842         } else if (adev->powerplay.pp_funcs->print_clock_levels) {
 843                 size = amdgpu_dpm_print_clock_levels(adev, OD_SCLK, buf);
 844                 size += amdgpu_dpm_print_clock_levels(adev, OD_MCLK, buf+size);
 845                 size += amdgpu_dpm_print_clock_levels(adev, OD_VDDC_CURVE, buf+size);
 846                 size += amdgpu_dpm_print_clock_levels(adev, OD_RANGE, buf+size);
 847         } else {
 848                 size = snprintf(buf, PAGE_SIZE, "\n");
 849         }
 850         pm_runtime_mark_last_busy(ddev->dev);
 851         pm_runtime_put_autosuspend(ddev->dev);
 852
 853         return size;
 854 }
 855
 856 /**
 857  * DOC: pp_features
 858  *
 859  * The amdgpu driver provides a sysfs API for adjusting what powerplay
 860  * features to be enabled. The file pp_features is used for this. And
 861  * this is only available for Vega10 and later dGPUs.
 862  *
 863  * Reading back the file will show you the followings:
 864  * - Current ppfeature masks
 865  * - List of the all supported powerplay features with their naming,
 866  *   bitmasks and enablement status('Y'/'N' means "enabled"/"disabled").
 867  *
 868  * To manually enable or disable a specific feature, just set or clear
 869  * the corresponding bit from original ppfeature masks and input the
 870  * new ppfeature masks.
 871  */
 872 static ssize_t amdgpu_set_pp_feature_status(struct device *dev,
 873                 struct device_attribute *attr,
 874                 const char *buf,
 875                 size_t count)
 876 {
 877         struct drm_device *ddev = dev_get_drvdata(dev);
 878         struct amdgpu_device *adev = ddev->dev_private;
 879         uint64_t featuremask;
 880         int ret;
 881
 882         if (amdgpu_sriov_vf(adev))
 883                 return -EINVAL;
 884
 885         ret = kstrtou64(buf, 0, &featuremask);
 886         if (ret)
 887                 return -EINVAL;
 888
 889         pr_debug("featuremask = 0x%llx\n", featuremask);
 890
 891         ret = pm_runtime_get_sync(ddev->dev);
 892         if (ret < 0)
 893                 return ret;
 894
 895         if (is_support_sw_smu(adev)) {
 896                 ret = smu_sys_set_pp_feature_mask(&adev->smu, featuremask);
 897                 if (ret) {
 898                         pm_runtime_mark_last_busy(ddev->dev);
 899                         pm_runtime_put_autosuspend(ddev->dev);
 900                         return -EINVAL;
 901                 }
 902         } else if (adev->powerplay.pp_funcs->set_ppfeature_status) {
 903                 ret = amdgpu_dpm_set_ppfeature_status(adev, featuremask);
 904                 if (ret) {
 905                         pm_runtime_mark_last_busy(ddev->dev);
 906                         pm_runtime_put_autosuspend(ddev->dev);
 907                         return -EINVAL;
 908                 }
 909         }
 910         pm_runtime_mark_last_busy(ddev->dev);
 911         pm_runtime_put_autosuspend(ddev->dev);
 912
 913         return count;
 914 }
 915
 916 static ssize_t amdgpu_get_pp_feature_status(struct device *dev,
 917                 struct device_attribute *attr,
 918                 char *buf)
 919 {
 920         struct drm_device *ddev = dev_get_drvdata(dev);
 921         struct amdgpu_device *adev = ddev->dev_private;
 922         ssize_t size;
 923         int ret;
 924
 925         if (amdgpu_sriov_vf(adev))
 926                 return 0;
 927
 928         ret = pm_runtime_get_sync(ddev->dev);
 929         if (ret < 0)
 930                 return ret;
 931
 932         if (is_support_sw_smu(adev))
 933                 size = smu_sys_get_pp_feature_mask(&adev->smu, buf);
 934         else if (adev->powerplay.pp_funcs->get_ppfeature_status)
 935                 size = amdgpu_dpm_get_ppfeature_status(adev, buf);
 936         else
 937                 size = snprintf(buf, PAGE_SIZE, "\n");
 938
 939         pm_runtime_mark_last_busy(ddev->dev);
 940         pm_runtime_put_autosuspend(ddev->dev);
 941
 942         return size;
 943 }
 944
 945 /**
 946  * DOC: pp_dpm_sclk pp_dpm_mclk pp_dpm_socclk pp_dpm_fclk pp_dpm_dcefclk pp_dpm_pcie
 947  *
 948  * The amdgpu driver provides a sysfs API for adjusting what power levels
 949  * are enabled for a given power state.  The files pp_dpm_sclk, pp_dpm_mclk,
 950  * pp_dpm_socclk, pp_dpm_fclk, pp_dpm_dcefclk and pp_dpm_pcie are used for
 951  * this.
 952  *
 953  * pp_dpm_socclk and pp_dpm_dcefclk interfaces are only available for
 954  * Vega10 and later ASICs.
 955  * pp_dpm_fclk interface is only available for Vega20 and later ASICs.
 956  *
 957  * Reading back the files will show you the available power levels within
 958  * the power state and the clock information for those levels.
 959  *
 960  * To manually adjust these states, first select manual using
 961  * power_dpm_force_performance_level.
 962  * Secondly, enter a new value for each level by inputing a string that
 963  * contains " echo xx xx xx > pp_dpm_sclk/mclk/pcie"
 964  * E.g.,
 965  *
 966  * .. code-block:: bash
 967  *
 968  *      echo "4 5 6" > pp_dpm_sclk
 969  *
 970  * will enable sclk levels 4, 5, and 6.
 971  *
 972  * NOTE: change to the dcefclk max dpm level is not supported now
 973  */
 974
 975 static ssize_t amdgpu_get_pp_dpm_sclk(struct device *dev,
 976                 struct device_attribute *attr,
 977                 char *buf)
 978 {
 979         struct drm_device *ddev = dev_get_drvdata(dev);
 980         struct amdgpu_device *adev = ddev->dev_private;
 981         ssize_t size;
 982         int ret;
 983
 984         if (amdgpu_sriov_vf(adev) && !amdgpu_sriov_is_pp_one_vf(adev))
 985                 return 0;
 986
 987         ret = pm_runtime_get_sync(ddev->dev);
 988         if (ret < 0)
 989                 return ret;
 990
 991         if (is_support_sw_smu(adev))
 992                 size = smu_print_clk_levels(&adev->smu, SMU_SCLK, buf);
 993         else if (adev->powerplay.pp_funcs->print_clock_levels)
 994                 size = amdgpu_dpm_print_clock_levels(adev, PP_SCLK, buf);
 995         else
 996                 size = snprintf(buf, PAGE_SIZE, "\n");
 997
 998         pm_runtime_mark_last_busy(ddev->dev);
 999         pm_runtime_put_autosuspend(ddev->dev);
1000
1001         return size;
1002 }
1003
1004 /*
1005  * Worst case: 32 bits individually specified, in octal at 12 characters
1006  * per line (+1 for \n).
1007  */
1008 #define AMDGPU_MASK_BUF_MAX     (32 * 13)
1009
1010 static ssize_t amdgpu_read_mask(const char *buf, size_t count, uint32_t *mask)
1011 {
1012         int ret;
1013         long level;
1014         char *sub_str = NULL;
1015         char *tmp;
1016         char buf_cpy[AMDGPU_MASK_BUF_MAX + 1];
1017         const char delimiter[3] = {' ', '\n', '\0'};
1018         size_t bytes;
1019
1020         *mask = 0;
1021
1022         bytes = min(count, sizeof(buf_cpy) - 1);
1023         memcpy(buf_cpy, buf, bytes);
1024         buf_cpy[bytes] = '\0';
1025         tmp = buf_cpy;
1026         while (tmp[0]) {
1027                 sub_str = strsep(&tmp, delimiter);
1028                 if (strlen(sub_str)) {
1029                         ret = kstrtol(sub_str, 0, &level);
1030                         if (ret)
1031                                 return -EINVAL;
1032                         *mask |= 1 << level;
1033                 } else
1034                         break;
1035         }
1036
1037         return 0;
1038 }
1039
1040 static ssize_t amdgpu_set_pp_dpm_sclk(struct device *dev,
1041                 struct device_attribute *attr,
1042                 const char *buf,
1043                 size_t count)
1044 {
1045         struct drm_device *ddev = dev_get_drvdata(dev);
1046         struct amdgpu_device *adev = ddev->dev_private;
1047         int ret;
1048         uint32_t mask = 0;
1049
1050         if (amdgpu_sriov_vf(adev) && !amdgpu_sriov_is_pp_one_vf(adev))
1051                 return -EINVAL;
1052
1053         ret = amdgpu_read_mask(buf, count, &mask);
1054         if (ret)
1055                 return ret;
1056
1057         ret = pm_runtime_get_sync(ddev->dev);
1058         if (ret < 0)
1059                 return ret;
1060
1061         if (is_support_sw_smu(adev))
1062                 ret = smu_force_clk_levels(&adev->smu, SMU_SCLK, mask, true);
1063         else if (adev->powerplay.pp_funcs->force_clock_level)
1064                 ret = amdgpu_dpm_force_clock_level(adev, PP_SCLK, mask);
1065
1066         pm_runtime_mark_last_busy(ddev->dev);
1067         pm_runtime_put_autosuspend(ddev->dev);
1068
1069         if (ret)
1070                 return -EINVAL;
1071
1072         return count;
1073 }
1074
1075 static ssize_t amdgpu_get_pp_dpm_mclk(struct device *dev,
1076                 struct device_attribute *attr,
1077                 char *buf)
1078 {
1079         struct drm_device *ddev = dev_get_drvdata(dev);
1080         struct amdgpu_device *adev = ddev->dev_private;
1081         ssize_t size;
1082         int ret;
1083
1084         if (amdgpu_sriov_vf(adev) && !amdgpu_sriov_is_pp_one_vf(adev))
1085                 return 0;
1086
1087         ret = pm_runtime_get_sync(ddev->dev);
1088         if (ret < 0)
1089                 return ret;
1090
1091         if (is_support_sw_smu(adev))
1092                 size = smu_print_clk_levels(&adev->smu, SMU_MCLK, buf);
1093         else if (adev->powerplay.pp_funcs->print_clock_levels)
1094                 size = amdgpu_dpm_print_clock_levels(adev, PP_MCLK, buf);
1095         else
1096                 size = snprintf(buf, PAGE_SIZE, "\n");
1097
1098         pm_runtime_mark_last_busy(ddev->dev);
1099         pm_runtime_put_autosuspend(ddev->dev);
1100
1101         return size;
1102 }
1103
1104 static ssize_t amdgpu_set_pp_dpm_mclk(struct device *dev,
1105                 struct device_attribute *attr,
1106                 const char *buf,
1107                 size_t count)
1108 {
1109         struct drm_device *ddev = dev_get_drvdata(dev);
1110         struct amdgpu_device *adev = ddev->dev_private;
1111         uint32_t mask = 0;
1112         int ret;
1113
1114         if (amdgpu_sriov_vf(adev) && !amdgpu_sriov_is_pp_one_vf(adev))
1115                         return -EINVAL;
1116
1117         ret = amdgpu_read_mask(buf, count, &mask);
1118         if (ret)
1119                 return ret;
1120
1121         ret = pm_runtime_get_sync(ddev->dev);
1122         if (ret < 0)
1123                 return ret;
1124
1125         if (is_support_sw_smu(adev))
1126                 ret = smu_force_clk_levels(&adev->smu, SMU_MCLK, mask, true);
1127         else if (adev->powerplay.pp_funcs->force_clock_level)
1128                 ret = amdgpu_dpm_force_clock_level(adev, PP_MCLK, mask);
1129
1130         pm_runtime_mark_last_busy(ddev->dev);
1131         pm_runtime_put_autosuspend(ddev->dev);
1132
1133         if (ret)
1134                 return -EINVAL;
1135
1136         return count;
1137 }
1138
1139 static ssize_t amdgpu_get_pp_dpm_socclk(struct device *dev,
1140                 struct device_attribute *attr,
1141                 char *buf)
1142 {
1143         struct drm_device *ddev = dev_get_drvdata(dev);
1144         struct amdgpu_device *adev = ddev->dev_private;
1145         ssize_t size;
1146         int ret;
1147
1148         if (amdgpu_sriov_vf(adev) && !amdgpu_sriov_is_pp_one_vf(adev))
1149                 return 0;
1150
1151         ret = pm_runtime_get_sync(ddev->dev);
1152         if (ret < 0)
1153                 return ret;
1154
1155         if (is_support_sw_smu(adev))
1156                 size = smu_print_clk_levels(&adev->smu, SMU_SOCCLK, buf);
1157         else if (adev->powerplay.pp_funcs->print_clock_levels)
1158                 size = amdgpu_dpm_print_clock_levels(adev, PP_SOCCLK, buf);
1159         else
1160                 size = snprintf(buf, PAGE_SIZE, "\n");
1161
1162         pm_runtime_mark_last_busy(ddev->dev);
1163         pm_runtime_put_autosuspend(ddev->dev);
1164
1165         return size;
1166 }
1167
1168 static ssize_t amdgpu_set_pp_dpm_socclk(struct device *dev,
1169                 struct device_attribute *attr,
1170                 const char *buf,
1171                 size_t count)
1172 {
1173         struct drm_device *ddev = dev_get_drvdata(dev);
1174         struct amdgpu_device *adev = ddev->dev_private;
1175         int ret;
1176         uint32_t mask = 0;
1177
1178         if (amdgpu_sriov_vf(adev) && !amdgpu_sriov_is_pp_one_vf(adev))
1179                 return -EINVAL;
1180
1181         ret = amdgpu_read_mask(buf, count, &mask);
1182         if (ret)
1183                 return ret;
1184
1185         ret = pm_runtime_get_sync(ddev->dev);
1186         if (ret < 0)
1187                 return ret;
1188
1189         if (is_support_sw_smu(adev))
1190                 ret = smu_force_clk_levels(&adev->smu, SMU_SOCCLK, mask, true);
1191         else if (adev->powerplay.pp_funcs->force_clock_level)
1192                 ret = amdgpu_dpm_force_clock_level(adev, PP_SOCCLK, mask);
1193         else
1194                 ret = 0;
1195
1196         pm_runtime_mark_last_busy(ddev->dev);
1197         pm_runtime_put_autosuspend(ddev->dev);
1198
1199         if (ret)
1200                 return -EINVAL;
1201
1202         return count;
1203 }
1204
1205 static ssize_t amdgpu_get_pp_dpm_fclk(struct device *dev,
1206                 struct device_attribute *attr,
1207                 char *buf)
1208 {
1209         struct drm_device *ddev = dev_get_drvdata(dev);
1210         struct amdgpu_device *adev = ddev->dev_private;
1211         ssize_t size;
1212         int ret;
1213
1214         if (amdgpu_sriov_vf(adev) && !amdgpu_sriov_is_pp_one_vf(adev))
1215                 return 0;
1216
1217         ret = pm_runtime_get_sync(ddev->dev);
1218         if (ret < 0)
1219                 return ret;
1220
1221         if (is_support_sw_smu(adev))
1222                 size = smu_print_clk_levels(&adev->smu, SMU_FCLK, buf);
1223         else if (adev->powerplay.pp_funcs->print_clock_levels)
1224                 size = amdgpu_dpm_print_clock_levels(adev, PP_FCLK, buf);
1225         else
1226                 size = snprintf(buf, PAGE_SIZE, "\n");
1227
1228         pm_runtime_mark_last_busy(ddev->dev);
1229         pm_runtime_put_autosuspend(ddev->dev);
1230
1231         return size;
1232 }
1233
1234 static ssize_t amdgpu_set_pp_dpm_fclk(struct device *dev,
1235                 struct device_attribute *attr,
1236                 const char *buf,
1237                 size_t count)
1238 {
1239         struct drm_device *ddev = dev_get_drvdata(dev);
1240         struct amdgpu_device *adev = ddev->dev_private;
1241         int ret;
1242         uint32_t mask = 0;
1243
1244         if (amdgpu_sriov_vf(adev) && !amdgpu_sriov_is_pp_one_vf(adev))
1245                 return -EINVAL;
1246
1247         ret = amdgpu_read_mask(buf, count, &mask);
1248         if (ret)
1249                 return ret;
1250
1251         ret = pm_runtime_get_sync(ddev->dev);
1252         if (ret < 0)
1253                 return ret;
1254
1255         if (is_support_sw_smu(adev))
1256                 ret = smu_force_clk_levels(&adev->smu, SMU_FCLK, mask, true);
1257         else if (adev->powerplay.pp_funcs->force_clock_level)
1258                 ret = amdgpu_dpm_force_clock_level(adev, PP_FCLK, mask);
1259         else
1260                 ret = 0;
1261
1262         pm_runtime_mark_last_busy(ddev->dev);
1263         pm_runtime_put_autosuspend(ddev->dev);
1264
1265         if (ret)
1266                 return -EINVAL;
1267
1268         return count;
1269 }
1270
1271 static ssize_t amdgpu_get_pp_dpm_dcefclk(struct device *dev,
1272                 struct device_attribute *attr,
1273                 char *buf)
1274 {
1275         struct drm_device *ddev = dev_get_drvdata(dev);
1276         struct amdgpu_device *adev = ddev->dev_private;
1277         ssize_t size;
1278         int ret;
1279
1280         if (amdgpu_sriov_vf(adev))
1281                 return 0;
1282
1283         ret = pm_runtime_get_sync(ddev->dev);
1284         if (ret < 0)
1285                 return ret;
1286
1287         if (is_support_sw_smu(adev))
1288                 size = smu_print_clk_levels(&adev->smu, SMU_DCEFCLK, buf);
1289         else if (adev->powerplay.pp_funcs->print_clock_levels)
1290                 size = amdgpu_dpm_print_clock_levels(adev, PP_DCEFCLK, buf);
1291         else
1292                 size = snprintf(buf, PAGE_SIZE, "\n");
1293
1294         pm_runtime_mark_last_busy(ddev->dev);
1295         pm_runtime_put_autosuspend(ddev->dev);
1296
1297         return size;
1298 }
1299
1300 static ssize_t amdgpu_set_pp_dpm_dcefclk(struct device *dev,
1301                 struct device_attribute *attr,
1302                 const char *buf,
1303                 size_t count)
1304 {
1305         struct drm_device *ddev = dev_get_drvdata(dev);
1306         struct amdgpu_device *adev = ddev->dev_private;
1307         int ret;
1308         uint32_t mask = 0;
1309
1310         if (amdgpu_sriov_vf(adev))
1311                 return -EINVAL;
1312
1313         ret = amdgpu_read_mask(buf, count, &mask);
1314         if (ret)
1315                 return ret;
1316
1317         ret = pm_runtime_get_sync(ddev->dev);
1318         if (ret < 0)
1319                 return ret;
1320
1321         if (is_support_sw_smu(adev))
1322                 ret = smu_force_clk_levels(&adev->smu, SMU_DCEFCLK, mask, true);
1323         else if (adev->powerplay.pp_funcs->force_clock_level)
1324                 ret = amdgpu_dpm_force_clock_level(adev, PP_DCEFCLK, mask);
1325         else
1326                 ret = 0;
1327
1328         pm_runtime_mark_last_busy(ddev->dev);
1329         pm_runtime_put_autosuspend(ddev->dev);
1330
1331         if (ret)
1332                 return -EINVAL;
1333
1334         return count;
1335 }
1336
1337 static ssize_t amdgpu_get_pp_dpm_pcie(struct device *dev,
1338                 struct device_attribute *attr,
1339                 char *buf)
1340 {
1341         struct drm_device *ddev = dev_get_drvdata(dev);
1342         struct amdgpu_device *adev = ddev->dev_private;
1343         ssize_t size;
1344         int ret;
1345
1346         if (amdgpu_sriov_vf(adev) && !amdgpu_sriov_is_pp_one_vf(adev))
1347                 return 0;
1348
1349         ret = pm_runtime_get_sync(ddev->dev);
1350         if (ret < 0)
1351                 return ret;
1352
1353         if (is_support_sw_smu(adev))
1354                 size = smu_print_clk_levels(&adev->smu, SMU_PCIE, buf);
1355         else if (adev->powerplay.pp_funcs->print_clock_levels)
1356                 size = amdgpu_dpm_print_clock_levels(adev, PP_PCIE, buf);
1357         else
1358                 size = snprintf(buf, PAGE_SIZE, "\n");
1359
1360         pm_runtime_mark_last_busy(ddev->dev);
1361         pm_runtime_put_autosuspend(ddev->dev);
1362
1363         return size;
1364 }
1365
1366 static ssize_t amdgpu_set_pp_dpm_pcie(struct device *dev,
1367                 struct device_attribute *attr,
1368                 const char *buf,
1369                 size_t count)
1370 {
1371         struct drm_device *ddev = dev_get_drvdata(dev);
1372         struct amdgpu_device *adev = ddev->dev_private;
1373         int ret;
1374         uint32_t mask = 0;
1375
1376         if (amdgpu_sriov_vf(adev) && !amdgpu_sriov_is_pp_one_vf(adev))
1377                 return -EINVAL;
1378
1379         ret = amdgpu_read_mask(buf, count, &mask);
1380         if (ret)
1381                 return ret;
1382
1383         ret = pm_runtime_get_sync(ddev->dev);
1384         if (ret < 0)
1385                 return ret;
1386
1387         if (is_support_sw_smu(adev))
1388                 ret = smu_force_clk_levels(&adev->smu, SMU_PCIE, mask, true);
1389         else if (adev->powerplay.pp_funcs->force_clock_level)
1390                 ret = amdgpu_dpm_force_clock_level(adev, PP_PCIE, mask);
1391         else
1392                 ret = 0;
1393
1394         pm_runtime_mark_last_busy(ddev->dev);
1395         pm_runtime_put_autosuspend(ddev->dev);
1396
1397         if (ret)
1398                 return -EINVAL;
1399
1400         return count;
1401 }
1402
1403 static ssize_t amdgpu_get_pp_sclk_od(struct device *dev,
1404                 struct device_attribute *attr,
1405                 char *buf)
1406 {
1407         struct drm_device *ddev = dev_get_drvdata(dev);
1408         struct amdgpu_device *adev = ddev->dev_private;
1409         uint32_t value = 0;
1410         int ret;
1411
1412         if (amdgpu_sriov_vf(adev))
1413                 return 0;
1414
1415         ret = pm_runtime_get_sync(ddev->dev);
1416         if (ret < 0)
1417                 return ret;
1418
1419         if (is_support_sw_smu(adev))
1420                 value = smu_get_od_percentage(&(adev->smu), SMU_OD_SCLK);
1421         else if (adev->powerplay.pp_funcs->get_sclk_od)
1422                 value = amdgpu_dpm_get_sclk_od(adev);
1423
1424         pm_runtime_mark_last_busy(ddev->dev);
1425         pm_runtime_put_autosuspend(ddev->dev);
1426
1427         return snprintf(buf, PAGE_SIZE, "%d\n", value);
1428 }
1429
1430 static ssize_t amdgpu_set_pp_sclk_od(struct device *dev,
1431                 struct device_attribute *attr,
1432                 const char *buf,
1433                 size_t count)
1434 {
1435         struct drm_device *ddev = dev_get_drvdata(dev);
1436         struct amdgpu_device *adev = ddev->dev_private;
1437         int ret;
1438         long int value;
1439
1440         if (amdgpu_sriov_vf(adev))
1441                 return -EINVAL;
1442
1443         ret = kstrtol(buf, 0, &value);
1444
1445         if (ret)
1446                 return -EINVAL;
1447
1448         ret = pm_runtime_get_sync(ddev->dev);
1449         if (ret < 0)
1450                 return ret;
1451
1452         if (is_support_sw_smu(adev)) {
1453                 value = smu_set_od_percentage(&(adev->smu), SMU_OD_SCLK, (uint32_t)value);
1454         } else {
1455                 if (adev->powerplay.pp_funcs->set_sclk_od)
1456                         amdgpu_dpm_set_sclk_od(adev, (uint32_t)value);
1457
1458                 if (adev->powerplay.pp_funcs->dispatch_tasks) {
1459                         amdgpu_dpm_dispatch_task(adev, AMD_PP_TASK_READJUST_POWER_STATE, NULL);
1460                 } else {
1461                         adev->pm.dpm.current_ps = adev->pm.dpm.boot_ps;
1462                         amdgpu_pm_compute_clocks(adev);
1463                 }
1464         }
1465
1466         pm_runtime_mark_last_busy(ddev->dev);
1467         pm_runtime_put_autosuspend(ddev->dev);
1468
1469         return count;
1470 }
1471
1472 static ssize_t amdgpu_get_pp_mclk_od(struct device *dev,
1473                 struct device_attribute *attr,
1474                 char *buf)
1475 {
1476         struct drm_device *ddev = dev_get_drvdata(dev);
1477         struct amdgpu_device *adev = ddev->dev_private;
1478         uint32_t value = 0;
1479         int ret;
1480
1481         if (amdgpu_sriov_vf(adev))
1482                 return 0;
1483
1484         ret = pm_runtime_get_sync(ddev->dev);
1485         if (ret < 0)
1486                 return ret;
1487
1488         if (is_support_sw_smu(adev))
1489                 value = smu_get_od_percentage(&(adev->smu), SMU_OD_MCLK);
1490         else if (adev->powerplay.pp_funcs->get_mclk_od)
1491                 value = amdgpu_dpm_get_mclk_od(adev);
1492
1493         pm_runtime_mark_last_busy(ddev->dev);
1494         pm_runtime_put_autosuspend(ddev->dev);
1495
1496         return snprintf(buf, PAGE_SIZE, "%d\n", value);
1497 }
1498
1499 static ssize_t amdgpu_set_pp_mclk_od(struct device *dev,
1500                 struct device_attribute *attr,
1501                 const char *buf,
1502                 size_t count)
1503 {
1504         struct drm_device *ddev = dev_get_drvdata(dev);
1505         struct amdgpu_device *adev = ddev->dev_private;
1506         int ret;
1507         long int value;
1508
1509         if (amdgpu_sriov_vf(adev))
1510                 return 0;
1511
1512         ret = kstrtol(buf, 0, &value);
1513
1514         if (ret)
1515                 return -EINVAL;
1516
1517         ret = pm_runtime_get_sync(ddev->dev);
1518         if (ret < 0)
1519                 return ret;
1520
1521         if (is_support_sw_smu(adev)) {
1522                 value = smu_set_od_percentage(&(adev->smu), SMU_OD_MCLK, (uint32_t)value);
1523         } else {
1524                 if (adev->powerplay.pp_funcs->set_mclk_od)
1525                         amdgpu_dpm_set_mclk_od(adev, (uint32_t)value);
1526
1527                 if (adev->powerplay.pp_funcs->dispatch_tasks) {
1528                         amdgpu_dpm_dispatch_task(adev, AMD_PP_TASK_READJUST_POWER_STATE, NULL);
1529                 } else {
1530                         adev->pm.dpm.current_ps = adev->pm.dpm.boot_ps;
1531                         amdgpu_pm_compute_clocks(adev);
1532                 }
1533         }
1534
1535         pm_runtime_mark_last_busy(ddev->dev);
1536         pm_runtime_put_autosuspend(ddev->dev);
1537
1538         return count;
1539 }
1540
1541 /**
1542  * DOC: pp_power_profile_mode
1543  *
1544  * The amdgpu driver provides a sysfs API for adjusting the heuristics
1545  * related to switching between power levels in a power state.  The file
1546  * pp_power_profile_mode is used for this.
1547  *
1548  * Reading this file outputs a list of all of the predefined power profiles
1549  * and the relevant heuristics settings for that profile.
1550  *
1551  * To select a profile or create a custom profile, first select manual using
1552  * power_dpm_force_performance_level.  Writing the number of a predefined
1553  * profile to pp_power_profile_mode will enable those heuristics.  To
1554  * create a custom set of heuristics, write a string of numbers to the file
1555  * starting with the number of the custom profile along with a setting
1556  * for each heuristic parameter.  Due to differences across asic families
1557  * the heuristic parameters vary from family to family.
1558  *
1559  */
1560
1561 static ssize_t amdgpu_get_pp_power_profile_mode(struct device *dev,
1562                 struct device_attribute *attr,
1563                 char *buf)
1564 {
1565         struct drm_device *ddev = dev_get_drvdata(dev);
1566         struct amdgpu_device *adev = ddev->dev_private;
1567         ssize_t size;
1568         int ret;
1569
1570         if (amdgpu_sriov_vf(adev) && !amdgpu_sriov_is_pp_one_vf(adev))
1571                 return 0;
1572
1573         ret = pm_runtime_get_sync(ddev->dev);
1574         if (ret < 0)
1575                 return ret;
1576
1577         if (is_support_sw_smu(adev))
1578                 size = smu_get_power_profile_mode(&adev->smu, buf);
1579         else if (adev->powerplay.pp_funcs->get_power_profile_mode)
1580                 size = amdgpu_dpm_get_power_profile_mode(adev, buf);
1581         else
1582                 size = snprintf(buf, PAGE_SIZE, "\n");
1583
1584         pm_runtime_mark_last_busy(ddev->dev);
1585         pm_runtime_put_autosuspend(ddev->dev);
1586
1587         return size;
1588 }
1589
1590
1591 static ssize_t amdgpu_set_pp_power_profile_mode(struct device *dev,
1592                 struct device_attribute *attr,
1593                 const char *buf,
1594                 size_t count)
1595 {
1596         int ret = 0xff;
1597         struct drm_device *ddev = dev_get_drvdata(dev);
1598         struct amdgpu_device *adev = ddev->dev_private;
1599         uint32_t parameter_size = 0;
1600         long parameter[64];
1601         char *sub_str, buf_cpy[128];
1602         char *tmp_str;
1603         uint32_t i = 0;
1604         char tmp[2];
1605         long int profile_mode = 0;
1606         const char delimiter[3] = {' ', '\n', '\0'};
1607
1608         tmp[0] = *(buf);
1609         tmp[1] = '\0';
1610         ret = kstrtol(tmp, 0, &profile_mode);
1611         if (ret)
1612                 return -EINVAL;
1613
1614         if (amdgpu_sriov_vf(adev) && !amdgpu_sriov_is_pp_one_vf(adev))
1615                 return -EINVAL;
1616
1617         if (profile_mode == PP_SMC_POWER_PROFILE_CUSTOM) {
1618                 if (count < 2 || count > 127)
1619                         return -EINVAL;
1620                 while (isspace(*++buf))
1621                         i++;
1622                 memcpy(buf_cpy, buf, count-i);
1623                 tmp_str = buf_cpy;
1624                 while (tmp_str[0]) {
1625                         sub_str = strsep(&tmp_str, delimiter);
1626                         ret = kstrtol(sub_str, 0, &parameter[parameter_size]);
1627                         if (ret)
1628                                 return -EINVAL;
1629                         parameter_size++;
1630                         while (isspace(*tmp_str))
1631                                 tmp_str++;
1632                 }
1633         }
1634         parameter[parameter_size] = profile_mode;
1635
1636         ret = pm_runtime_get_sync(ddev->dev);
1637         if (ret < 0)
1638                 return ret;
1639
1640         if (is_support_sw_smu(adev))
1641                 ret = smu_set_power_profile_mode(&adev->smu, parameter, parameter_size, true);
1642         else if (adev->powerplay.pp_funcs->set_power_profile_mode)
1643                 ret = amdgpu_dpm_set_power_profile_mode(adev, parameter, parameter_size);
1644
1645         pm_runtime_mark_last_busy(ddev->dev);
1646         pm_runtime_put_autosuspend(ddev->dev);
1647
1648         if (!ret)
1649                 return count;
1650
1651         return -EINVAL;
1652 }
1653
1654 /**
1655  * DOC: busy_percent
1656  *
1657  * The amdgpu driver provides a sysfs API for reading how busy the GPU
1658  * is as a percentage.  The file gpu_busy_percent is used for this.
1659  * The SMU firmware computes a percentage of load based on the
1660  * aggregate activity level in the IP cores.
1661  */
1662 static ssize_t amdgpu_get_busy_percent(struct device *dev,
1663                 struct device_attribute *attr,
1664                 char *buf)
1665 {
1666         struct drm_device *ddev = dev_get_drvdata(dev);
1667         struct amdgpu_device *adev = ddev->dev_private;
1668         int r, value, size = sizeof(value);
1669
1670         if (amdgpu_sriov_vf(adev) && !amdgpu_sriov_is_pp_one_vf(adev))
1671                 return 0;
1672
1673         r = pm_runtime_get_sync(ddev->dev);
1674         if (r < 0)
1675                 return r;
1676
1677         /* read the IP busy sensor */
1678         r = amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_GPU_LOAD,
1679                                    (void *)&value, &size);
1680
1681         pm_runtime_mark_last_busy(ddev->dev);
1682         pm_runtime_put_autosuspend(ddev->dev);
1683
1684         if (r)
1685                 return r;
1686
1687         return snprintf(buf, PAGE_SIZE, "%d\n", value);
1688 }
1689
1690 /**
1691  * DOC: mem_busy_percent
1692  *
1693  * The amdgpu driver provides a sysfs API for reading how busy the VRAM
1694  * is as a percentage.  The file mem_busy_percent is used for this.
1695  * The SMU firmware computes a percentage of load based on the
1696  * aggregate activity level in the IP cores.
1697  */
1698 static ssize_t amdgpu_get_memory_busy_percent(struct device *dev,
1699                 struct device_attribute *attr,
1700                 char *buf)
1701 {
1702         struct drm_device *ddev = dev_get_drvdata(dev);
1703         struct amdgpu_device *adev = ddev->dev_private;
1704         int r, value, size = sizeof(value);
1705
1706         if (amdgpu_sriov_vf(adev) && !amdgpu_sriov_is_pp_one_vf(adev))
1707                 return 0;
1708
1709         r = pm_runtime_get_sync(ddev->dev);
1710         if (r < 0)
1711                 return r;
1712
1713         /* read the IP busy sensor */
1714         r = amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_MEM_LOAD,
1715                                    (void *)&value, &size);
1716
1717         pm_runtime_mark_last_busy(ddev->dev);
1718         pm_runtime_put_autosuspend(ddev->dev);
1719
1720         if (r)
1721                 return r;
1722
1723         return snprintf(buf, PAGE_SIZE, "%d\n", value);
1724 }
1725
1726 /**
1727  * DOC: pcie_bw
1728  *
1729  * The amdgpu driver provides a sysfs API for estimating how much data
1730  * has been received and sent by the GPU in the last second through PCIe.
1731  * The file pcie_bw is used for this.
1732  * The Perf counters count the number of received and sent messages and return
1733  * those values, as well as the maximum payload size of a PCIe packet (mps).
1734  * Note that it is not possible to easily and quickly obtain the size of each
1735  * packet transmitted, so we output the max payload size (mps) to allow for
1736  * quick estimation of the PCIe bandwidth usage
1737  */
1738 static ssize_t amdgpu_get_pcie_bw(struct device *dev,
1739                 struct device_attribute *attr,
1740                 char *buf)
1741 {
1742         struct drm_device *ddev = dev_get_drvdata(dev);
1743         struct amdgpu_device *adev = ddev->dev_private;
1744         uint64_t count0, count1;
1745         int ret;
1746
1747         if (amdgpu_sriov_vf(adev) && !amdgpu_sriov_is_pp_one_vf(adev))
1748                 return 0;
1749
1750         ret = pm_runtime_get_sync(ddev->dev);
1751         if (ret < 0)
1752                 return ret;
1753
1754         amdgpu_asic_get_pcie_usage(adev, &count0, &count1);
1755
1756         pm_runtime_mark_last_busy(ddev->dev);
1757         pm_runtime_put_autosuspend(ddev->dev);
1758
1759         return snprintf(buf, PAGE_SIZE, "%llu %llu %i\n",
1760                         count0, count1, pcie_get_mps(adev->pdev));
1761 }
1762
1763 /**
1764  * DOC: unique_id
1765  *
1766  * The amdgpu driver provides a sysfs API for providing a unique ID for the GPU
1767  * The file unique_id is used for this.
1768  * This will provide a Unique ID that will persist from machine to machine
1769  *
1770  * NOTE: This will only work for GFX9 and newer. This file will be absent
1771  * on unsupported ASICs (GFX8 and older)
1772  */
1773 static ssize_t amdgpu_get_unique_id(struct device *dev,
1774                 struct device_attribute *attr,
1775                 char *buf)
1776 {
1777         struct drm_device *ddev = dev_get_drvdata(dev);
1778         struct amdgpu_device *adev = ddev->dev_private;
1779
1780         if (amdgpu_sriov_vf(adev) && !amdgpu_sriov_is_pp_one_vf(adev))
1781                 return 0;
1782
1783         if (adev->unique_id)
1784                 return snprintf(buf, PAGE_SIZE, "%016llx\n", adev->unique_id);
1785
1786         return 0;
1787 }
1788
1789 static DEVICE_ATTR(power_dpm_state, S_IRUGO | S_IWUSR, amdgpu_get_dpm_state, amdgpu_set_dpm_state);
1790 static DEVICE_ATTR(power_dpm_force_performance_level, S_IRUGO | S_IWUSR,
1791                    amdgpu_get_dpm_forced_performance_level,
1792                    amdgpu_set_dpm_forced_performance_level);
1793 static DEVICE_ATTR(pp_num_states, S_IRUGO, amdgpu_get_pp_num_states, NULL);
1794 static DEVICE_ATTR(pp_cur_state, S_IRUGO, amdgpu_get_pp_cur_state, NULL);
1795 static DEVICE_ATTR(pp_force_state, S_IRUGO | S_IWUSR,
1796                 amdgpu_get_pp_force_state,
1797                 amdgpu_set_pp_force_state);
1798 static DEVICE_ATTR(pp_table, S_IRUGO | S_IWUSR,
1799                 amdgpu_get_pp_table,
1800                 amdgpu_set_pp_table);
1801 static DEVICE_ATTR(pp_dpm_sclk, S_IRUGO | S_IWUSR,
1802                 amdgpu_get_pp_dpm_sclk,
1803                 amdgpu_set_pp_dpm_sclk);
1804 static DEVICE_ATTR(pp_dpm_mclk, S_IRUGO | S_IWUSR,
1805                 amdgpu_get_pp_dpm_mclk,
1806                 amdgpu_set_pp_dpm_mclk);
1807 static DEVICE_ATTR(pp_dpm_socclk, S_IRUGO | S_IWUSR,
1808                 amdgpu_get_pp_dpm_socclk,
1809                 amdgpu_set_pp_dpm_socclk);
1810 static DEVICE_ATTR(pp_dpm_fclk, S_IRUGO | S_IWUSR,
1811                 amdgpu_get_pp_dpm_fclk,
1812                 amdgpu_set_pp_dpm_fclk);
1813 static DEVICE_ATTR(pp_dpm_dcefclk, S_IRUGO | S_IWUSR,
1814                 amdgpu_get_pp_dpm_dcefclk,
1815                 amdgpu_set_pp_dpm_dcefclk);
1816 static DEVICE_ATTR(pp_dpm_pcie, S_IRUGO | S_IWUSR,
1817                 amdgpu_get_pp_dpm_pcie,
1818                 amdgpu_set_pp_dpm_pcie);
1819 static DEVICE_ATTR(pp_sclk_od, S_IRUGO | S_IWUSR,
1820                 amdgpu_get_pp_sclk_od,
1821                 amdgpu_set_pp_sclk_od);
1822 static DEVICE_ATTR(pp_mclk_od, S_IRUGO | S_IWUSR,
1823                 amdgpu_get_pp_mclk_od,
1824                 amdgpu_set_pp_mclk_od);
1825 static DEVICE_ATTR(pp_power_profile_mode, S_IRUGO | S_IWUSR,
1826                 amdgpu_get_pp_power_profile_mode,
1827                 amdgpu_set_pp_power_profile_mode);
1828 static DEVICE_ATTR(pp_od_clk_voltage, S_IRUGO | S_IWUSR,
1829                 amdgpu_get_pp_od_clk_voltage,
1830                 amdgpu_set_pp_od_clk_voltage);
1831 static DEVICE_ATTR(gpu_busy_percent, S_IRUGO,
1832                 amdgpu_get_busy_percent, NULL);
1833 static DEVICE_ATTR(mem_busy_percent, S_IRUGO,
1834                 amdgpu_get_memory_busy_percent, NULL);
1835 static DEVICE_ATTR(pcie_bw, S_IRUGO, amdgpu_get_pcie_bw, NULL);
1836 static DEVICE_ATTR(pp_features, S_IRUGO | S_IWUSR,
1837                 amdgpu_get_pp_feature_status,
1838                 amdgpu_set_pp_feature_status);
1839 static DEVICE_ATTR(unique_id, S_IRUGO, amdgpu_get_unique_id, NULL);
1840
1841 static ssize_t amdgpu_hwmon_show_temp(struct device *dev,
1842                                       struct device_attribute *attr,
1843                                       char *buf)
1844 {
1845         struct amdgpu_device *adev = dev_get_drvdata(dev);
1846         int channel = to_sensor_dev_attr(attr)->index;
1847         int r, temp = 0, size = sizeof(temp);
1848
1849         if (channel >= PP_TEMP_MAX)
1850                 return -EINVAL;
1851
1852         r = pm_runtime_get_sync(adev->ddev->dev);
1853         if (r < 0)
1854                 return r;
1855
1856         switch (channel) {
1857         case PP_TEMP_JUNCTION:
1858                 /* get current junction temperature */
1859                 r = amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_HOTSPOT_TEMP,
1860                                            (void *)&temp, &size);
1861                 break;
1862         case PP_TEMP_EDGE:
1863                 /* get current edge temperature */
1864                 r = amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_EDGE_TEMP,
1865                                            (void *)&temp, &size);
1866                 break;
1867         case PP_TEMP_MEM:
1868                 /* get current memory temperature */
1869                 r = amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_MEM_TEMP,
1870                                            (void *)&temp, &size);
1871                 break;
1872         default:
1873                 r = -EINVAL;
1874                 break;
1875         }
1876
1877         pm_runtime_mark_last_busy(adev->ddev->dev);
1878         pm_runtime_put_autosuspend(adev->ddev->dev);
1879
1880         if (r)
1881                 return r;
1882
1883         return snprintf(buf, PAGE_SIZE, "%d\n", temp);
1884 }
1885
1886 static ssize_t amdgpu_hwmon_show_temp_thresh(struct device *dev,
1887                                              struct device_attribute *attr,
1888                                              char *buf)
1889 {
1890         struct amdgpu_device *adev = dev_get_drvdata(dev);
1891         int hyst = to_sensor_dev_attr(attr)->index;
1892         int temp;
1893
1894         if (hyst)
1895                 temp = adev->pm.dpm.thermal.min_temp;
1896         else
1897                 temp = adev->pm.dpm.thermal.max_temp;
1898
1899         return snprintf(buf, PAGE_SIZE, "%d\n", temp);
1900 }
1901
1902 static ssize_t amdgpu_hwmon_show_hotspot_temp_thresh(struct device *dev,
1903                                              struct device_attribute *attr,
1904                                              char *buf)
1905 {
1906         struct amdgpu_device *adev = dev_get_drvdata(dev);
1907         int hyst = to_sensor_dev_attr(attr)->index;
1908         int temp;
1909
1910         if (hyst)
1911                 temp = adev->pm.dpm.thermal.min_hotspot_temp;
1912         else
1913                 temp = adev->pm.dpm.thermal.max_hotspot_crit_temp;
1914
1915         return snprintf(buf, PAGE_SIZE, "%d\n", temp);
1916 }
1917
1918 static ssize_t amdgpu_hwmon_show_mem_temp_thresh(struct device *dev,
1919                                              struct device_attribute *attr,
1920                                              char *buf)
1921 {
1922         struct amdgpu_device *adev = dev_get_drvdata(dev);
1923         int hyst = to_sensor_dev_attr(attr)->index;
1924         int temp;
1925
1926         if (hyst)
1927                 temp = adev->pm.dpm.thermal.min_mem_temp;
1928         else
1929                 temp = adev->pm.dpm.thermal.max_mem_crit_temp;
1930
1931         return snprintf(buf, PAGE_SIZE, "%d\n", temp);
1932 }
1933
1934 static ssize_t amdgpu_hwmon_show_temp_label(struct device *dev,
1935                                              struct device_attribute *attr,
1936                                              char *buf)
1937 {
1938         int channel = to_sensor_dev_attr(attr)->index;
1939
1940         if (channel >= PP_TEMP_MAX)
1941                 return -EINVAL;
1942
1943         return snprintf(buf, PAGE_SIZE, "%s\n", temp_label[channel].label);
1944 }
1945
1946 static ssize_t amdgpu_hwmon_show_temp_emergency(struct device *dev,
1947                                              struct device_attribute *attr,
1948                                              char *buf)
1949 {
1950         struct amdgpu_device *adev = dev_get_drvdata(dev);
1951         int channel = to_sensor_dev_attr(attr)->index;
1952         int temp = 0;
1953
1954         if (channel >= PP_TEMP_MAX)
1955                 return -EINVAL;
1956
1957         switch (channel) {
1958         case PP_TEMP_JUNCTION:
1959                 temp = adev->pm.dpm.thermal.max_hotspot_emergency_temp;
1960                 break;
1961         case PP_TEMP_EDGE:
1962                 temp = adev->pm.dpm.thermal.max_edge_emergency_temp;
1963                 break;
1964         case PP_TEMP_MEM:
1965                 temp = adev->pm.dpm.thermal.max_mem_emergency_temp;
1966                 break;
1967         }
1968
1969         return snprintf(buf, PAGE_SIZE, "%d\n", temp);
1970 }
1971
1972 static ssize_t amdgpu_hwmon_get_pwm1_enable(struct device *dev,
1973                                             struct device_attribute *attr,
1974                                             char *buf)
1975 {
1976         struct amdgpu_device *adev = dev_get_drvdata(dev);
1977         u32 pwm_mode = 0;
1978         int ret;
1979
1980         ret = pm_runtime_get_sync(adev->ddev->dev);
1981         if (ret < 0)
1982                 return ret;
1983
1984         if (is_support_sw_smu(adev)) {
1985                 pwm_mode = smu_get_fan_control_mode(&adev->smu);
1986         } else {
1987                 if (!adev->powerplay.pp_funcs->get_fan_control_mode) {
1988                         pm_runtime_mark_last_busy(adev->ddev->dev);
1989                         pm_runtime_put_autosuspend(adev->ddev->dev);
1990                         return -EINVAL;
1991                 }
1992
1993                 pwm_mode = amdgpu_dpm_get_fan_control_mode(adev);
1994         }
1995
1996         pm_runtime_mark_last_busy(adev->ddev->dev);
1997         pm_runtime_put_autosuspend(adev->ddev->dev);
1998
1999         return sprintf(buf, "%i\n", pwm_mode);
2000 }
2001
2002 static ssize_t amdgpu_hwmon_set_pwm1_enable(struct device *dev,
2003                                             struct device_attribute *attr,
2004                                             const char *buf,
2005                                             size_t count)
2006 {
2007         struct amdgpu_device *adev = dev_get_drvdata(dev);
2008         int err, ret;
2009         int value;
2010
2011         err = kstrtoint(buf, 10, &value);
2012         if (err)
2013                 return err;
2014
2015         ret = pm_runtime_get_sync(adev->ddev->dev);
2016         if (ret < 0)
2017                 return ret;
2018
2019         if (is_support_sw_smu(adev)) {
2020                 smu_set_fan_control_mode(&adev->smu, value);
2021         } else {
2022                 if (!adev->powerplay.pp_funcs->set_fan_control_mode) {
2023                         pm_runtime_mark_last_busy(adev->ddev->dev);
2024                         pm_runtime_put_autosuspend(adev->ddev->dev);
2025                         return -EINVAL;
2026                 }
2027
2028                 amdgpu_dpm_set_fan_control_mode(adev, value);
2029         }
2030
2031         pm_runtime_mark_last_busy(adev->ddev->dev);
2032         pm_runtime_put_autosuspend(adev->ddev->dev);
2033
2034         return count;
2035 }
2036
2037 static ssize_t amdgpu_hwmon_get_pwm1_min(struct device *dev,
2038                                          struct device_attribute *attr,
2039                                          char *buf)
2040 {
2041         return sprintf(buf, "%i\n", 0);
2042 }
2043
2044 static ssize_t amdgpu_hwmon_get_pwm1_max(struct device *dev,
2045                                          struct device_attribute *attr,
2046                                          char *buf)
2047 {
2048         return sprintf(buf, "%i\n", 255);
2049 }
2050
2051 static ssize_t amdgpu_hwmon_set_pwm1(struct device *dev,
2052                                      struct device_attribute *attr,
2053                                      const char *buf, size_t count)
2054 {
2055         struct amdgpu_device *adev = dev_get_drvdata(dev);
2056         int err;
2057         u32 value;
2058         u32 pwm_mode;
2059
2060         err = pm_runtime_get_sync(adev->ddev->dev);
2061         if (err < 0)
2062                 return err;
2063
2064         if (is_support_sw_smu(adev))
2065                 pwm_mode = smu_get_fan_control_mode(&adev->smu);
2066         else
2067                 pwm_mode = amdgpu_dpm_get_fan_control_mode(adev);
2068
2069         if (pwm_mode != AMD_FAN_CTRL_MANUAL) {
2070                 pr_info("manual fan speed control should be enabled first\n");
2071                 pm_runtime_mark_last_busy(adev->ddev->dev);
2072                 pm_runtime_put_autosuspend(adev->ddev->dev);
2073                 return -EINVAL;
2074         }
2075
2076         err = kstrtou32(buf, 10, &value);
2077         if (err) {
2078                 pm_runtime_mark_last_busy(adev->ddev->dev);
2079                 pm_runtime_put_autosuspend(adev->ddev->dev);
2080                 return err;
2081         }
2082
2083         value = (value * 100) / 255;
2084
2085         if (is_support_sw_smu(adev))
2086                 err = smu_set_fan_speed_percent(&adev->smu, value);
2087         else if (adev->powerplay.pp_funcs->set_fan_speed_percent)
2088                 err = amdgpu_dpm_set_fan_speed_percent(adev, value);
2089         else
2090                 err = -EINVAL;
2091
2092         pm_runtime_mark_last_busy(adev->ddev->dev);
2093         pm_runtime_put_autosuspend(adev->ddev->dev);
2094
2095         if (err)
2096                 return err;
2097
2098         return count;
2099 }
2100
2101 static ssize_t amdgpu_hwmon_get_pwm1(struct device *dev,
2102                                      struct device_attribute *attr,
2103                                      char *buf)
2104 {
2105         struct amdgpu_device *adev = dev_get_drvdata(dev);
2106         int err;
2107         u32 speed = 0;
2108
2109         err = pm_runtime_get_sync(adev->ddev->dev);
2110         if (err < 0)
2111                 return err;
2112
2113         if (is_support_sw_smu(adev))
2114                 err = smu_get_fan_speed_percent(&adev->smu, &speed);
2115         else if (adev->powerplay.pp_funcs->get_fan_speed_percent)
2116                 err = amdgpu_dpm_get_fan_speed_percent(adev, &speed);
2117         else
2118                 err = -EINVAL;
2119
2120         pm_runtime_mark_last_busy(adev->ddev->dev);
2121         pm_runtime_put_autosuspend(adev->ddev->dev);
2122
2123         if (err)
2124                 return err;
2125
2126         speed = (speed * 255) / 100;
2127
2128         return sprintf(buf, "%i\n", speed);
2129 }
2130
2131 static ssize_t amdgpu_hwmon_get_fan1_input(struct device *dev,
2132                                            struct device_attribute *attr,
2133                                            char *buf)
2134 {
2135         struct amdgpu_device *adev = dev_get_drvdata(dev);
2136         int err;
2137         u32 speed = 0;
2138
2139         err = pm_runtime_get_sync(adev->ddev->dev);
2140         if (err < 0)
2141                 return err;
2142
2143         if (is_support_sw_smu(adev))
2144                 err = smu_get_fan_speed_rpm(&adev->smu, &speed);
2145         else if (adev->powerplay.pp_funcs->get_fan_speed_rpm)
2146                 err = amdgpu_dpm_get_fan_speed_rpm(adev, &speed);
2147         else
2148                 err = -EINVAL;
2149
2150         pm_runtime_mark_last_busy(adev->ddev->dev);
2151         pm_runtime_put_autosuspend(adev->ddev->dev);
2152
2153         if (err)
2154                 return err;
2155
2156         return sprintf(buf, "%i\n", speed);
2157 }
2158
2159 static ssize_t amdgpu_hwmon_get_fan1_min(struct device *dev,
2160                                          struct device_attribute *attr,
2161                                          char *buf)
2162 {
2163         struct amdgpu_device *adev = dev_get_drvdata(dev);
2164         u32 min_rpm = 0;
2165         u32 size = sizeof(min_rpm);
2166         int r;
2167
2168         r = pm_runtime_get_sync(adev->ddev->dev);
2169         if (r < 0)
2170                 return r;
2171
2172         r = amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_MIN_FAN_RPM,
2173                                    (void *)&min_rpm, &size);
2174
2175         pm_runtime_mark_last_busy(adev->ddev->dev);
2176         pm_runtime_put_autosuspend(adev->ddev->dev);
2177
2178         if (r)
2179                 return r;
2180
2181         return snprintf(buf, PAGE_SIZE, "%d\n", min_rpm);
2182 }
2183
2184 static ssize_t amdgpu_hwmon_get_fan1_max(struct device *dev,
2185                                          struct device_attribute *attr,
2186                                          char *buf)
2187 {
2188         struct amdgpu_device *adev = dev_get_drvdata(dev);
2189         u32 max_rpm = 0;
2190         u32 size = sizeof(max_rpm);
2191         int r;
2192
2193         r = pm_runtime_get_sync(adev->ddev->dev);
2194         if (r < 0)
2195                 return r;
2196
2197         r = amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_MAX_FAN_RPM,
2198                                    (void *)&max_rpm, &size);
2199
2200         pm_runtime_mark_last_busy(adev->ddev->dev);
2201         pm_runtime_put_autosuspend(adev->ddev->dev);
2202
2203         if (r)
2204                 return r;
2205
2206         return snprintf(buf, PAGE_SIZE, "%d\n", max_rpm);
2207 }
2208
2209 static ssize_t amdgpu_hwmon_get_fan1_target(struct device *dev,
2210                                            struct device_attribute *attr,
2211                                            char *buf)
2212 {
2213         struct amdgpu_device *adev = dev_get_drvdata(dev);
2214         int err;
2215         u32 rpm = 0;
2216
2217         err = pm_runtime_get_sync(adev->ddev->dev);
2218         if (err < 0)
2219                 return err;
2220
2221         if (is_support_sw_smu(adev))
2222                 err = smu_get_fan_speed_rpm(&adev->smu, &rpm);
2223         else if (adev->powerplay.pp_funcs->get_fan_speed_rpm)
2224                 err = amdgpu_dpm_get_fan_speed_rpm(adev, &rpm);
2225         else
2226                 err = -EINVAL;
2227
2228         pm_runtime_mark_last_busy(adev->ddev->dev);
2229         pm_runtime_put_autosuspend(adev->ddev->dev);
2230
2231         if (err)
2232                 return err;
2233
2234         return sprintf(buf, "%i\n", rpm);
2235 }
2236
2237 static ssize_t amdgpu_hwmon_set_fan1_target(struct device *dev,
2238                                      struct device_attribute *attr,
2239                                      const char *buf, size_t count)
2240 {
2241         struct amdgpu_device *adev = dev_get_drvdata(dev);
2242         int err;
2243         u32 value;
2244         u32 pwm_mode;
2245
2246         err = pm_runtime_get_sync(adev->ddev->dev);
2247         if (err < 0)
2248                 return err;
2249
2250         if (is_support_sw_smu(adev))
2251                 pwm_mode = smu_get_fan_control_mode(&adev->smu);
2252         else
2253                 pwm_mode = amdgpu_dpm_get_fan_control_mode(adev);
2254
2255         if (pwm_mode != AMD_FAN_CTRL_MANUAL) {
2256                 pm_runtime_mark_last_busy(adev->ddev->dev);
2257                 pm_runtime_put_autosuspend(adev->ddev->dev);
2258                 return -ENODATA;
2259         }
2260
2261         err = kstrtou32(buf, 10, &value);
2262         if (err) {
2263                 pm_runtime_mark_last_busy(adev->ddev->dev);
2264                 pm_runtime_put_autosuspend(adev->ddev->dev);
2265                 return err;
2266         }
2267
2268         if (is_support_sw_smu(adev))
2269                 err = smu_set_fan_speed_rpm(&adev->smu, value);
2270         else if (adev->powerplay.pp_funcs->set_fan_speed_rpm)
2271                 err = amdgpu_dpm_set_fan_speed_rpm(adev, value);
2272         else
2273                 err = -EINVAL;
2274
2275         pm_runtime_mark_last_busy(adev->ddev->dev);
2276         pm_runtime_put_autosuspend(adev->ddev->dev);
2277
2278         if (err)
2279                 return err;
2280
2281         return count;
2282 }
2283
2284 static ssize_t amdgpu_hwmon_get_fan1_enable(struct device *dev,
2285                                             struct device_attribute *attr,
2286                                             char *buf)
2287 {
2288         struct amdgpu_device *adev = dev_get_drvdata(dev);
2289         u32 pwm_mode = 0;
2290         int ret;
2291
2292         ret = pm_runtime_get_sync(adev->ddev->dev);
2293         if (ret < 0)
2294                 return ret;
2295
2296         if (is_support_sw_smu(adev)) {
2297                 pwm_mode = smu_get_fan_control_mode(&adev->smu);
2298         } else {
2299                 if (!adev->powerplay.pp_funcs->get_fan_control_mode) {
2300                         pm_runtime_mark_last_busy(adev->ddev->dev);
2301                         pm_runtime_put_autosuspend(adev->ddev->dev);
2302                         return -EINVAL;
2303                 }
2304
2305                 pwm_mode = amdgpu_dpm_get_fan_control_mode(adev);
2306         }
2307
2308         pm_runtime_mark_last_busy(adev->ddev->dev);
2309         pm_runtime_put_autosuspend(adev->ddev->dev);
2310
2311         return sprintf(buf, "%i\n", pwm_mode == AMD_FAN_CTRL_AUTO ? 0 : 1);
2312 }
2313
2314 static ssize_t amdgpu_hwmon_set_fan1_enable(struct device *dev,
2315                                             struct device_attribute *attr,
2316                                             const char *buf,
2317                                             size_t count)
2318 {
2319         struct amdgpu_device *adev = dev_get_drvdata(dev);
2320         int err;
2321         int value;
2322         u32 pwm_mode;
2323
2324         err = kstrtoint(buf, 10, &value);
2325         if (err)
2326                 return err;
2327
2328         if (value == 0)
2329                 pwm_mode = AMD_FAN_CTRL_AUTO;
2330         else if (value == 1)
2331                 pwm_mode = AMD_FAN_CTRL_MANUAL;
2332         else
2333                 return -EINVAL;
2334
2335         err = pm_runtime_get_sync(adev->ddev->dev);
2336         if (err < 0)
2337                 return err;
2338
2339         if (is_support_sw_smu(adev)) {
2340                 smu_set_fan_control_mode(&adev->smu, pwm_mode);
2341         } else {
2342                 if (!adev->powerplay.pp_funcs->set_fan_control_mode) {
2343                         pm_runtime_mark_last_busy(adev->ddev->dev);
2344                         pm_runtime_put_autosuspend(adev->ddev->dev);
2345                         return -EINVAL;
2346                 }
2347                 amdgpu_dpm_set_fan_control_mode(adev, pwm_mode);
2348         }
2349
2350         pm_runtime_mark_last_busy(adev->ddev->dev);
2351         pm_runtime_put_autosuspend(adev->ddev->dev);
2352
2353         return count;
2354 }
2355
2356 static ssize_t amdgpu_hwmon_show_vddgfx(struct device *dev,
2357                                         struct device_attribute *attr,
2358                                         char *buf)
2359 {
2360         struct amdgpu_device *adev = dev_get_drvdata(dev);
2361         u32 vddgfx;
2362         int r, size = sizeof(vddgfx);
2363
2364         r = pm_runtime_get_sync(adev->ddev->dev);
2365         if (r < 0)
2366                 return r;
2367
2368         /* get the voltage */
2369         r = amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_VDDGFX,
2370                                    (void *)&vddgfx, &size);
2371
2372         pm_runtime_mark_last_busy(adev->ddev->dev);
2373         pm_runtime_put_autosuspend(adev->ddev->dev);
2374
2375         if (r)
2376                 return r;
2377
2378         return snprintf(buf, PAGE_SIZE, "%d\n", vddgfx);
2379 }
2380
2381 static ssize_t amdgpu_hwmon_show_vddgfx_label(struct device *dev,
2382                                               struct device_attribute *attr,
2383                                               char *buf)
2384 {
2385         return snprintf(buf, PAGE_SIZE, "vddgfx\n");
2386 }
2387
2388 static ssize_t amdgpu_hwmon_show_vddnb(struct device *dev,
2389                                        struct device_attribute *attr,
2390                                        char *buf)
2391 {
2392         struct amdgpu_device *adev = dev_get_drvdata(dev);
2393         u32 vddnb;
2394         int r, size = sizeof(vddnb);
2395
2396         /* only APUs have vddnb */
2397         if  (!(adev->flags & AMD_IS_APU))
2398                 return -EINVAL;
2399
2400         r = pm_runtime_get_sync(adev->ddev->dev);
2401         if (r < 0)
2402                 return r;
2403
2404         /* get the voltage */
2405         r = amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_VDDNB,
2406                                    (void *)&vddnb, &size);
2407
2408         pm_runtime_mark_last_busy(adev->ddev->dev);
2409         pm_runtime_put_autosuspend(adev->ddev->dev);
2410
2411         if (r)
2412                 return r;
2413
2414         return snprintf(buf, PAGE_SIZE, "%d\n", vddnb);
2415 }
2416
2417 static ssize_t amdgpu_hwmon_show_vddnb_label(struct device *dev,
2418                                               struct device_attribute *attr,
2419                                               char *buf)
2420 {
2421         return snprintf(buf, PAGE_SIZE, "vddnb\n");
2422 }
2423
2424 static ssize_t amdgpu_hwmon_show_power_avg(struct device *dev,
2425                                            struct device_attribute *attr,
2426                                            char *buf)
2427 {
2428         struct amdgpu_device *adev = dev_get_drvdata(dev);
2429         u32 query = 0;
2430         int r, size = sizeof(u32);
2431         unsigned uw;
2432
2433         r = pm_runtime_get_sync(adev->ddev->dev);
2434         if (r < 0)
2435                 return r;
2436
2437         /* get the voltage */
2438         r = amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_GPU_POWER,
2439                                    (void *)&query, &size);
2440
2441         pm_runtime_mark_last_busy(adev->ddev->dev);
2442         pm_runtime_put_autosuspend(adev->ddev->dev);
2443
2444         if (r)
2445                 return r;
2446
2447         /* convert to microwatts */
2448         uw = (query >> 8) * 1000000 + (query & 0xff) * 1000;
2449
2450         return snprintf(buf, PAGE_SIZE, "%u\n", uw);
2451 }
2452
2453 static ssize_t amdgpu_hwmon_show_power_cap_min(struct device *dev,
2454                                          struct device_attribute *attr,
2455                                          char *buf)
2456 {
2457         return sprintf(buf, "%i\n", 0);
2458 }
2459
2460 static ssize_t amdgpu_hwmon_show_power_cap_max(struct device *dev,
2461                                          struct device_attribute *attr,
2462                                          char *buf)
2463 {
2464         struct amdgpu_device *adev = dev_get_drvdata(dev);
2465         uint32_t limit = 0;
2466         ssize_t size;
2467         int r;
2468
2469         r = pm_runtime_get_sync(adev->ddev->dev);
2470         if (r < 0)
2471                 return r;
2472
2473         if (is_support_sw_smu(adev)) {
2474                 smu_get_power_limit(&adev->smu, &limit, true, true);
2475                 size = snprintf(buf, PAGE_SIZE, "%u\n", limit * 1000000);
2476         } else if (adev->powerplay.pp_funcs && adev->powerplay.pp_funcs->get_power_limit) {
2477                 adev->powerplay.pp_funcs->get_power_limit(adev->powerplay.pp_handle, &limit, true);
2478                 size = snprintf(buf, PAGE_SIZE, "%u\n", limit * 1000000);
2479         } else {
2480                 size = snprintf(buf, PAGE_SIZE, "\n");
2481         }
2482
2483         pm_runtime_mark_last_busy(adev->ddev->dev);
2484         pm_runtime_put_autosuspend(adev->ddev->dev);
2485
2486         return size;
2487 }
2488
2489 static ssize_t amdgpu_hwmon_show_power_cap(struct device *dev,
2490                                          struct device_attribute *attr,
2491                                          char *buf)
2492 {
2493         struct amdgpu_device *adev = dev_get_drvdata(dev);
2494         uint32_t limit = 0;
2495         ssize_t size;
2496         int r;
2497
2498         r = pm_runtime_get_sync(adev->ddev->dev);
2499         if (r < 0)
2500                 return r;
2501
2502         if (is_support_sw_smu(adev)) {
2503                 smu_get_power_limit(&adev->smu, &limit, false,  true);
2504                 size = snprintf(buf, PAGE_SIZE, "%u\n", limit * 1000000);
2505         } else if (adev->powerplay.pp_funcs && adev->powerplay.pp_funcs->get_power_limit) {
2506                 adev->powerplay.pp_funcs->get_power_limit(adev->powerplay.pp_handle, &limit, false);
2507                 size = snprintf(buf, PAGE_SIZE, "%u\n", limit * 1000000);
2508         } else {
2509                 size = snprintf(buf, PAGE_SIZE, "\n");
2510         }
2511
2512         pm_runtime_mark_last_busy(adev->ddev->dev);
2513         pm_runtime_put_autosuspend(adev->ddev->dev);
2514
2515         return size;
2516 }
2517
2518
2519 static ssize_t amdgpu_hwmon_set_power_cap(struct device *dev,
2520                 struct device_attribute *attr,
2521                 const char *buf,
2522                 size_t count)
2523 {
2524         struct amdgpu_device *adev = dev_get_drvdata(dev);
2525         int err;
2526         u32 value;
2527
2528         if (amdgpu_sriov_vf(adev))
2529                 return -EINVAL;
2530
2531         err = kstrtou32(buf, 10, &value);
2532         if (err)
2533                 return err;
2534
2535         value = value / 1000000; /* convert to Watt */
2536
2537
2538         err = pm_runtime_get_sync(adev->ddev->dev);
2539         if (err < 0)
2540                 return err;
2541
2542         if (is_support_sw_smu(adev))
2543                 err = smu_set_power_limit(&adev->smu, value);
2544         else if (adev->powerplay.pp_funcs && adev->powerplay.pp_funcs->set_power_limit)
2545                 err = adev->powerplay.pp_funcs->set_power_limit(adev->powerplay.pp_handle, value);
2546         else
2547                 err = -EINVAL;
2548
2549         pm_runtime_mark_last_busy(adev->ddev->dev);
2550         pm_runtime_put_autosuspend(adev->ddev->dev);
2551
2552         if (err)
2553                 return err;
2554
2555         return count;
2556 }
2557
2558 static ssize_t amdgpu_hwmon_show_sclk(struct device *dev,
2559                                       struct device_attribute *attr,
2560                                       char *buf)
2561 {
2562         struct amdgpu_device *adev = dev_get_drvdata(dev);
2563         uint32_t sclk;
2564         int r, size = sizeof(sclk);
2565
2566         r = pm_runtime_get_sync(adev->ddev->dev);
2567         if (r < 0)
2568                 return r;
2569
2570         /* get the sclk */
2571         r = amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_GFX_SCLK,
2572                                    (void *)&sclk, &size);
2573
2574         pm_runtime_mark_last_busy(adev->ddev->dev);
2575         pm_runtime_put_autosuspend(adev->ddev->dev);
2576
2577         if (r)
2578                 return r;
2579
2580         return snprintf(buf, PAGE_SIZE, "%d\n", sclk * 10 * 1000);
2581 }
2582
2583 static ssize_t amdgpu_hwmon_show_sclk_label(struct device *dev,
2584                                             struct device_attribute *attr,
2585                                             char *buf)
2586 {
2587         return snprintf(buf, PAGE_SIZE, "sclk\n");
2588 }
2589
2590 static ssize_t amdgpu_hwmon_show_mclk(struct device *dev,
2591                                       struct device_attribute *attr,
2592                                       char *buf)
2593 {
2594         struct amdgpu_device *adev = dev_get_drvdata(dev);
2595         uint32_t mclk;
2596         int r, size = sizeof(mclk);
2597
2598         r = pm_runtime_get_sync(adev->ddev->dev);
2599         if (r < 0)
2600                 return r;
2601
2602         /* get the sclk */
2603         r = amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_GFX_MCLK,
2604                                    (void *)&mclk, &size);
2605
2606         pm_runtime_mark_last_busy(adev->ddev->dev);
2607         pm_runtime_put_autosuspend(adev->ddev->dev);
2608
2609         if (r)
2610                 return r;
2611
2612         return snprintf(buf, PAGE_SIZE, "%d\n", mclk * 10 * 1000);
2613 }
2614
2615 static ssize_t amdgpu_hwmon_show_mclk_label(struct device *dev,
2616                                             struct device_attribute *attr,
2617                                             char *buf)
2618 {
2619         return snprintf(buf, PAGE_SIZE, "mclk\n");
2620 }
2621
2622 /**
2623  * DOC: hwmon
2624  *
2625  * The amdgpu driver exposes the following sensor interfaces:
2626  *
2627  * - GPU temperature (via the on-die sensor)
2628  *
2629  * - GPU voltage
2630  *
2631  * - Northbridge voltage (APUs only)
2632  *
2633  * - GPU power
2634  *
2635  * - GPU fan
2636  *
2637  * - GPU gfx/compute engine clock
2638  *
2639  * - GPU memory clock (dGPU only)
2640  *
2641  * hwmon interfaces for GPU temperature:
2642  *
2643  * - temp[1-3]_input: the on die GPU temperature in millidegrees Celsius
2644  *   - temp2_input and temp3_input are supported on SOC15 dGPUs only
2645  *
2646  * - temp[1-3]_label: temperature channel label
2647  *   - temp2_label and temp3_label are supported on SOC15 dGPUs only
2648  *
2649  * - temp[1-3]_crit: temperature critical max value in millidegrees Celsius
2650  *   - temp2_crit and temp3_crit are supported on SOC15 dGPUs only
2651  *
2652  * - temp[1-3]_crit_hyst: temperature hysteresis for critical limit in millidegrees Celsius
2653  *   - temp2_crit_hyst and temp3_crit_hyst are supported on SOC15 dGPUs only
2654  *
2655  * - temp[1-3]_emergency: temperature emergency max value(asic shutdown) in millidegrees Celsius
2656  *   - these are supported on SOC15 dGPUs only
2657  *
2658  * hwmon interfaces for GPU voltage:
2659  *
2660  * - in0_input: the voltage on the GPU in millivolts
2661  *
2662  * - in1_input: the voltage on the Northbridge in millivolts
2663  *
2664  * hwmon interfaces for GPU power:
2665  *
2666  * - power1_average: average power used by the GPU in microWatts
2667  *
2668  * - power1_cap_min: minimum cap supported in microWatts
2669  *
2670  * - power1_cap_max: maximum cap supported in microWatts
2671  *
2672  * - power1_cap: selected power cap in microWatts
2673  *
2674  * hwmon interfaces for GPU fan:
2675  *
2676  * - pwm1: pulse width modulation fan level (0-255)
2677  *
2678  * - pwm1_enable: pulse width modulation fan control method (0: no fan speed control, 1: manual fan speed control using pwm interface, 2: automatic fan speed control)
2679  *
2680  * - pwm1_min: pulse width modulation fan control minimum level (0)
2681  *
2682  * - pwm1_max: pulse width modulation fan control maximum level (255)
2683  *
2684  * - fan1_min: an minimum value Unit: revolution/min (RPM)
2685  *
2686  * - fan1_max: an maxmum value Unit: revolution/max (RPM)
2687  *
2688  * - fan1_input: fan speed in RPM
2689  *
2690  * - fan[1-\*]_target: Desired fan speed Unit: revolution/min (RPM)
2691  *
2692  * - fan[1-\*]_enable: Enable or disable the sensors.1: Enable 0: Disable
2693  *
2694  * hwmon interfaces for GPU clocks:
2695  *
2696  * - freq1_input: the gfx/compute clock in hertz
2697  *
2698  * - freq2_input: the memory clock in hertz
2699  *
2700  * You can use hwmon tools like sensors to view this information on your system.
2701  *
2702  */
2703
2704 static SENSOR_DEVICE_ATTR(temp1_input, S_IRUGO, amdgpu_hwmon_show_temp, NULL, PP_TEMP_EDGE);
2705 static SENSOR_DEVICE_ATTR(temp1_crit, S_IRUGO, amdgpu_hwmon_show_temp_thresh, NULL, 0);
2706 static SENSOR_DEVICE_ATTR(temp1_crit_hyst, S_IRUGO, amdgpu_hwmon_show_temp_thresh, NULL, 1);
2707 static SENSOR_DEVICE_ATTR(temp1_emergency, S_IRUGO, amdgpu_hwmon_show_temp_emergency, NULL, PP_TEMP_EDGE);
2708 static SENSOR_DEVICE_ATTR(temp2_input, S_IRUGO, amdgpu_hwmon_show_temp, NULL, PP_TEMP_JUNCTION);
2709 static SENSOR_DEVICE_ATTR(temp2_crit, S_IRUGO, amdgpu_hwmon_show_hotspot_temp_thresh, NULL, 0);
2710 static SENSOR_DEVICE_ATTR(temp2_crit_hyst, S_IRUGO, amdgpu_hwmon_show_hotspot_temp_thresh, NULL, 1);
2711 static SENSOR_DEVICE_ATTR(temp2_emergency, S_IRUGO, amdgpu_hwmon_show_temp_emergency, NULL, PP_TEMP_JUNCTION);
2712 static SENSOR_DEVICE_ATTR(temp3_input, S_IRUGO, amdgpu_hwmon_show_temp, NULL, PP_TEMP_MEM);
2713 static SENSOR_DEVICE_ATTR(temp3_crit, S_IRUGO, amdgpu_hwmon_show_mem_temp_thresh, NULL, 0);
2714 static SENSOR_DEVICE_ATTR(temp3_crit_hyst, S_IRUGO, amdgpu_hwmon_show_mem_temp_thresh, NULL, 1);
2715 static SENSOR_DEVICE_ATTR(temp3_emergency, S_IRUGO, amdgpu_hwmon_show_temp_emergency, NULL, PP_TEMP_MEM);
2716 static SENSOR_DEVICE_ATTR(temp1_label, S_IRUGO, amdgpu_hwmon_show_temp_label, NULL, PP_TEMP_EDGE);
2717 static SENSOR_DEVICE_ATTR(temp2_label, S_IRUGO, amdgpu_hwmon_show_temp_label, NULL, PP_TEMP_JUNCTION);
2718 static SENSOR_DEVICE_ATTR(temp3_label, S_IRUGO, amdgpu_hwmon_show_temp_label, NULL, PP_TEMP_MEM);
2719 static SENSOR_DEVICE_ATTR(pwm1, S_IRUGO | S_IWUSR, amdgpu_hwmon_get_pwm1, amdgpu_hwmon_set_pwm1, 0);
2720 static SENSOR_DEVICE_ATTR(pwm1_enable, S_IRUGO | S_IWUSR, amdgpu_hwmon_get_pwm1_enable, amdgpu_hwmon_set_pwm1_enable, 0);
2721 static SENSOR_DEVICE_ATTR(pwm1_min, S_IRUGO, amdgpu_hwmon_get_pwm1_min, NULL, 0);
2722 static SENSOR_DEVICE_ATTR(pwm1_max, S_IRUGO, amdgpu_hwmon_get_pwm1_max, NULL, 0);
2723 static SENSOR_DEVICE_ATTR(fan1_input, S_IRUGO, amdgpu_hwmon_get_fan1_input, NULL, 0);
2724 static SENSOR_DEVICE_ATTR(fan1_min, S_IRUGO, amdgpu_hwmon_get_fan1_min, NULL, 0);
2725 static SENSOR_DEVICE_ATTR(fan1_max, S_IRUGO, amdgpu_hwmon_get_fan1_max, NULL, 0);
2726 static SENSOR_DEVICE_ATTR(fan1_target, S_IRUGO | S_IWUSR, amdgpu_hwmon_get_fan1_target, amdgpu_hwmon_set_fan1_target, 0);
2727 static SENSOR_DEVICE_ATTR(fan1_enable, S_IRUGO | S_IWUSR, amdgpu_hwmon_get_fan1_enable, amdgpu_hwmon_set_fan1_enable, 0);
2728 static SENSOR_DEVICE_ATTR(in0_input, S_IRUGO, amdgpu_hwmon_show_vddgfx, NULL, 0);
2729 static SENSOR_DEVICE_ATTR(in0_label, S_IRUGO, amdgpu_hwmon_show_vddgfx_label, NULL, 0);
2730 static SENSOR_DEVICE_ATTR(in1_input, S_IRUGO, amdgpu_hwmon_show_vddnb, NULL, 0);
2731 static SENSOR_DEVICE_ATTR(in1_label, S_IRUGO, amdgpu_hwmon_show_vddnb_label, NULL, 0);
2732 static SENSOR_DEVICE_ATTR(power1_average, S_IRUGO, amdgpu_hwmon_show_power_avg, NULL, 0);
2733 static SENSOR_DEVICE_ATTR(power1_cap_max, S_IRUGO, amdgpu_hwmon_show_power_cap_max, NULL, 0);
2734 static SENSOR_DEVICE_ATTR(power1_cap_min, S_IRUGO, amdgpu_hwmon_show_power_cap_min, NULL, 0);
2735 static SENSOR_DEVICE_ATTR(power1_cap, S_IRUGO | S_IWUSR, amdgpu_hwmon_show_power_cap, amdgpu_hwmon_set_power_cap, 0);
2736 static SENSOR_DEVICE_ATTR(freq1_input, S_IRUGO, amdgpu_hwmon_show_sclk, NULL, 0);
2737 static SENSOR_DEVICE_ATTR(freq1_label, S_IRUGO, amdgpu_hwmon_show_sclk_label, NULL, 0);
2738 static SENSOR_DEVICE_ATTR(freq2_input, S_IRUGO, amdgpu_hwmon_show_mclk, NULL, 0);
2739 static SENSOR_DEVICE_ATTR(freq2_label, S_IRUGO, amdgpu_hwmon_show_mclk_label, NULL, 0);
2740
2741 static struct attribute *hwmon_attributes[] = {
2742         &sensor_dev_attr_temp1_input.dev_attr.attr,
2743         &sensor_dev_attr_temp1_crit.dev_attr.attr,
2744         &sensor_dev_attr_temp1_crit_hyst.dev_attr.attr,
2745         &sensor_dev_attr_temp2_input.dev_attr.attr,
2746         &sensor_dev_attr_temp2_crit.dev_attr.attr,
2747         &sensor_dev_attr_temp2_crit_hyst.dev_attr.attr,
2748         &sensor_dev_attr_temp3_input.dev_attr.attr,
2749         &sensor_dev_attr_temp3_crit.dev_attr.attr,
2750         &sensor_dev_attr_temp3_crit_hyst.dev_attr.attr,
2751         &sensor_dev_attr_temp1_emergency.dev_attr.attr,
2752         &sensor_dev_attr_temp2_emergency.dev_attr.attr,
2753         &sensor_dev_attr_temp3_emergency.dev_attr.attr,
2754         &sensor_dev_attr_temp1_label.dev_attr.attr,
2755         &sensor_dev_attr_temp2_label.dev_attr.attr,
2756         &sensor_dev_attr_temp3_label.dev_attr.attr,
2757         &sensor_dev_attr_pwm1.dev_attr.attr,
2758         &sensor_dev_attr_pwm1_enable.dev_attr.attr,
2759         &sensor_dev_attr_pwm1_min.dev_attr.attr,
2760         &sensor_dev_attr_pwm1_max.dev_attr.attr,
2761         &sensor_dev_attr_fan1_input.dev_attr.attr,
2762         &sensor_dev_attr_fan1_min.dev_attr.attr,
2763         &sensor_dev_attr_fan1_max.dev_attr.attr,
2764         &sensor_dev_attr_fan1_target.dev_attr.attr,
2765         &sensor_dev_attr_fan1_enable.dev_attr.attr,
2766         &sensor_dev_attr_in0_input.dev_attr.attr,
2767         &sensor_dev_attr_in0_label.dev_attr.attr,
2768         &sensor_dev_attr_in1_input.dev_attr.attr,
2769         &sensor_dev_attr_in1_label.dev_attr.attr,
2770         &sensor_dev_attr_power1_average.dev_attr.attr,
2771         &sensor_dev_attr_power1_cap_max.dev_attr.attr,
2772         &sensor_dev_attr_power1_cap_min.dev_attr.attr,
2773         &sensor_dev_attr_power1_cap.dev_attr.attr,
2774         &sensor_dev_attr_freq1_input.dev_attr.attr,
2775         &sensor_dev_attr_freq1_label.dev_attr.attr,
2776         &sensor_dev_attr_freq2_input.dev_attr.attr,
2777         &sensor_dev_attr_freq2_label.dev_attr.attr,
2778         NULL
2779 };
2780
2781 static umode_t hwmon_attributes_visible(struct kobject *kobj,
2782                                         struct attribute *attr, int index)
2783 {
2784         struct device *dev = kobj_to_dev(kobj);
2785         struct amdgpu_device *adev = dev_get_drvdata(dev);
2786         umode_t effective_mode = attr->mode;
2787
2788         /* under multi-vf mode, the hwmon attributes are all not supported */
2789         if (amdgpu_sriov_vf(adev) && !amdgpu_sriov_is_pp_one_vf(adev))
2790                 return 0;
2791
2792         /* there is no fan under pp one vf mode */
2793         if (amdgpu_sriov_is_pp_one_vf(adev) &&
2794             (attr == &sensor_dev_attr_pwm1.dev_attr.attr ||
2795              attr == &sensor_dev_attr_pwm1_enable.dev_attr.attr ||
2796              attr == &sensor_dev_attr_pwm1_max.dev_attr.attr ||
2797              attr == &sensor_dev_attr_pwm1_min.dev_attr.attr ||
2798              attr == &sensor_dev_attr_fan1_input.dev_attr.attr ||
2799              attr == &sensor_dev_attr_fan1_min.dev_attr.attr ||
2800              attr == &sensor_dev_attr_fan1_max.dev_attr.attr ||
2801              attr == &sensor_dev_attr_fan1_target.dev_attr.attr ||
2802              attr == &sensor_dev_attr_fan1_enable.dev_attr.attr))
2803                 return 0;
2804
2805         /* Skip fan attributes if fan is not present */
2806         if (adev->pm.no_fan && (attr == &sensor_dev_attr_pwm1.dev_attr.attr ||
2807             attr == &sensor_dev_attr_pwm1_enable.dev_attr.attr ||
2808             attr == &sensor_dev_attr_pwm1_max.dev_attr.attr ||
2809             attr == &sensor_dev_attr_pwm1_min.dev_attr.attr ||
2810             attr == &sensor_dev_attr_fan1_input.dev_attr.attr ||
2811             attr == &sensor_dev_attr_fan1_min.dev_attr.attr ||
2812             attr == &sensor_dev_attr_fan1_max.dev_attr.attr ||
2813             attr == &sensor_dev_attr_fan1_target.dev_attr.attr ||
2814             attr == &sensor_dev_attr_fan1_enable.dev_attr.attr))
2815                 return 0;
2816
2817         /* Skip fan attributes on APU */
2818         if ((adev->flags & AMD_IS_APU) &&
2819             (attr == &sensor_dev_attr_pwm1.dev_attr.attr ||
2820              attr == &sensor_dev_attr_pwm1_enable.dev_attr.attr ||
2821              attr == &sensor_dev_attr_pwm1_max.dev_attr.attr ||
2822              attr == &sensor_dev_attr_pwm1_min.dev_attr.attr ||
2823              attr == &sensor_dev_attr_fan1_input.dev_attr.attr ||
2824              attr == &sensor_dev_attr_fan1_min.dev_attr.attr ||
2825              attr == &sensor_dev_attr_fan1_max.dev_attr.attr ||
2826              attr == &sensor_dev_attr_fan1_target.dev_attr.attr ||
2827              attr == &sensor_dev_attr_fan1_enable.dev_attr.attr))
2828                 return 0;
2829
2830         /* Skip limit attributes if DPM is not enabled */
2831         if (!adev->pm.dpm_enabled &&
2832             (attr == &sensor_dev_attr_temp1_crit.dev_attr.attr ||
2833              attr == &sensor_dev_attr_temp1_crit_hyst.dev_attr.attr ||
2834              attr == &sensor_dev_attr_pwm1.dev_attr.attr ||
2835              attr == &sensor_dev_attr_pwm1_enable.dev_attr.attr ||
2836              attr == &sensor_dev_attr_pwm1_max.dev_attr.attr ||
2837              attr == &sensor_dev_attr_pwm1_min.dev_attr.attr ||
2838              attr == &sensor_dev_attr_fan1_input.dev_attr.attr ||
2839              attr == &sensor_dev_attr_fan1_min.dev_attr.attr ||
2840              attr == &sensor_dev_attr_fan1_max.dev_attr.attr ||
2841              attr == &sensor_dev_attr_fan1_target.dev_attr.attr ||
2842              attr == &sensor_dev_attr_fan1_enable.dev_attr.attr))
2843                 return 0;
2844
2845         if (!is_support_sw_smu(adev)) {
2846                 /* mask fan attributes if we have no bindings for this asic to expose */
2847                 if ((!adev->powerplay.pp_funcs->get_fan_speed_percent &&
2848                      attr == &sensor_dev_attr_pwm1.dev_attr.attr) || /* can't query fan */
2849                     (!adev->powerplay.pp_funcs->get_fan_control_mode &&
2850                      attr == &sensor_dev_attr_pwm1_enable.dev_attr.attr)) /* can't query state */
2851                         effective_mode &= ~S_IRUGO;
2852
2853                 if ((!adev->powerplay.pp_funcs->set_fan_speed_percent &&
2854                      attr == &sensor_dev_attr_pwm1.dev_attr.attr) || /* can't manage fan */
2855                     (!adev->powerplay.pp_funcs->set_fan_control_mode &&
2856                      attr == &sensor_dev_attr_pwm1_enable.dev_attr.attr)) /* can't manage state */
2857                         effective_mode &= ~S_IWUSR;
2858         }
2859
2860         if (((adev->flags & AMD_IS_APU) ||
2861              adev->family == AMDGPU_FAMILY_SI ||        /* not implemented yet */
2862              adev->family == AMDGPU_FAMILY_KV) &&       /* not implemented yet */
2863             (attr == &sensor_dev_attr_power1_average.dev_attr.attr ||
2864              attr == &sensor_dev_attr_power1_cap_max.dev_attr.attr ||
2865              attr == &sensor_dev_attr_power1_cap_min.dev_attr.attr||
2866              attr == &sensor_dev_attr_power1_cap.dev_attr.attr))
2867                 return 0;
2868
2869         if (!is_support_sw_smu(adev)) {
2870                 /* hide max/min values if we can't both query and manage the fan */
2871                 if ((!adev->powerplay.pp_funcs->set_fan_speed_percent &&
2872                      !adev->powerplay.pp_funcs->get_fan_speed_percent) &&
2873                      (!adev->powerplay.pp_funcs->set_fan_speed_rpm &&
2874                      !adev->powerplay.pp_funcs->get_fan_speed_rpm) &&
2875                     (attr == &sensor_dev_attr_pwm1_max.dev_attr.attr ||
2876                      attr == &sensor_dev_attr_pwm1_min.dev_attr.attr))
2877                         return 0;
2878
2879                 if ((!adev->powerplay.pp_funcs->set_fan_speed_rpm &&
2880                      !adev->powerplay.pp_funcs->get_fan_speed_rpm) &&
2881                     (attr == &sensor_dev_attr_fan1_max.dev_attr.attr ||
2882                      attr == &sensor_dev_attr_fan1_min.dev_attr.attr))
2883                         return 0;
2884         }
2885
2886         if ((adev->family == AMDGPU_FAMILY_SI ||        /* not implemented yet */
2887              adev->family == AMDGPU_FAMILY_KV) &&       /* not implemented yet */
2888             (attr == &sensor_dev_attr_in0_input.dev_attr.attr ||
2889              attr == &sensor_dev_attr_in0_label.dev_attr.attr))
2890                 return 0;
2891
2892         /* only APUs have vddnb */
2893         if (!(adev->flags & AMD_IS_APU) &&
2894             (attr == &sensor_dev_attr_in1_input.dev_attr.attr ||
2895              attr == &sensor_dev_attr_in1_label.dev_attr.attr))
2896                 return 0;
2897
2898         /* no mclk on APUs */
2899         if ((adev->flags & AMD_IS_APU) &&
2900             (attr == &sensor_dev_attr_freq2_input.dev_attr.attr ||
2901              attr == &sensor_dev_attr_freq2_label.dev_attr.attr))
2902                 return 0;
2903
2904         /* only SOC15 dGPUs support hotspot and mem temperatures */
2905         if (((adev->flags & AMD_IS_APU) ||
2906              adev->asic_type < CHIP_VEGA10) &&
2907             (attr == &sensor_dev_attr_temp2_crit.dev_attr.attr ||
2908              attr == &sensor_dev_attr_temp2_crit_hyst.dev_attr.attr ||
2909              attr == &sensor_dev_attr_temp3_crit.dev_attr.attr ||
2910              attr == &sensor_dev_attr_temp3_crit_hyst.dev_attr.attr ||
2911              attr == &sensor_dev_attr_temp1_emergency.dev_attr.attr ||
2912              attr == &sensor_dev_attr_temp2_emergency.dev_attr.attr ||
2913              attr == &sensor_dev_attr_temp3_emergency.dev_attr.attr ||
2914              attr == &sensor_dev_attr_temp2_input.dev_attr.attr ||
2915              attr == &sensor_dev_attr_temp3_input.dev_attr.attr ||
2916              attr == &sensor_dev_attr_temp2_label.dev_attr.attr ||
2917              attr == &sensor_dev_attr_temp3_label.dev_attr.attr))
2918                 return 0;
2919
2920         return effective_mode;
2921 }
2922
2923 static const struct attribute_group hwmon_attrgroup = {
2924         .attrs = hwmon_attributes,
2925         .is_visible = hwmon_attributes_visible,
2926 };
2927
2928 static const struct attribute_group *hwmon_groups[] = {
2929         &hwmon_attrgroup,
2930         NULL
2931 };
2932
2933 void amdgpu_dpm_thermal_work_handler(struct work_struct *work)
2934 {
2935         struct amdgpu_device *adev =
2936                 container_of(work, struct amdgpu_device,
2937                              pm.dpm.thermal.work);
2938         /* switch to the thermal state */
2939         enum amd_pm_state_type dpm_state = POWER_STATE_TYPE_INTERNAL_THERMAL;
2940         int temp, size = sizeof(temp);
2941
2942         if (!adev->pm.dpm_enabled)
2943                 return;
2944
2945         if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_GPU_TEMP,
2946                                     (void *)&temp, &size)) {
2947                 if (temp < adev->pm.dpm.thermal.min_temp)
2948                         /* switch back the user state */
2949                         dpm_state = adev->pm.dpm.user_state;
2950         } else {
2951                 if (adev->pm.dpm.thermal.high_to_low)
2952                         /* switch back the user state */
2953                         dpm_state = adev->pm.dpm.user_state;
2954         }
2955         mutex_lock(&adev->pm.mutex);
2956         if (dpm_state == POWER_STATE_TYPE_INTERNAL_THERMAL)
2957                 adev->pm.dpm.thermal_active = true;
2958         else
2959                 adev->pm.dpm.thermal_active = false;
2960         adev->pm.dpm.state = dpm_state;
2961         mutex_unlock(&adev->pm.mutex);
2962
2963         amdgpu_pm_compute_clocks(adev);
2964 }
2965
2966 static struct amdgpu_ps *amdgpu_dpm_pick_power_state(struct amdgpu_device *adev,
2967                                                      enum amd_pm_state_type dpm_state)
2968 {
2969         int i;
2970         struct amdgpu_ps *ps;
2971         u32 ui_class;
2972         bool single_display = (adev->pm.dpm.new_active_crtc_count < 2) ?
2973                 true : false;
2974
2975         /* check if the vblank period is too short to adjust the mclk */
2976         if (single_display && adev->powerplay.pp_funcs->vblank_too_short) {
2977                 if (amdgpu_dpm_vblank_too_short(adev))
2978                         single_display = false;
2979         }
2980
2981         /* certain older asics have a separare 3D performance state,
2982          * so try that first if the user selected performance
2983          */
2984         if (dpm_state == POWER_STATE_TYPE_PERFORMANCE)
2985                 dpm_state = POWER_STATE_TYPE_INTERNAL_3DPERF;
2986         /* balanced states don't exist at the moment */
2987         if (dpm_state == POWER_STATE_TYPE_BALANCED)
2988                 dpm_state = POWER_STATE_TYPE_PERFORMANCE;
2989
2990 restart_search:
2991         /* Pick the best power state based on current conditions */
2992         for (i = 0; i < adev->pm.dpm.num_ps; i++) {
2993                 ps = &adev->pm.dpm.ps[i];
2994                 ui_class = ps->class & ATOM_PPLIB_CLASSIFICATION_UI_MASK;
2995                 switch (dpm_state) {
2996                 /* user states */
2997                 case POWER_STATE_TYPE_BATTERY:
2998                         if (ui_class == ATOM_PPLIB_CLASSIFICATION_UI_BATTERY) {
2999                                 if (ps->caps & ATOM_PPLIB_SINGLE_DISPLAY_ONLY) {
3000                                         if (single_display)
3001                                                 return ps;
3002                                 } else
3003                                         return ps;
3004                         }
3005                         break;
3006                 case POWER_STATE_TYPE_BALANCED:
3007                         if (ui_class == ATOM_PPLIB_CLASSIFICATION_UI_BALANCED) {
3008                                 if (ps->caps & ATOM_PPLIB_SINGLE_DISPLAY_ONLY) {
3009                                         if (single_display)
3010                                                 return ps;
3011                                 } else
3012                                         return ps;
3013                         }
3014                         break;
3015                 case POWER_STATE_TYPE_PERFORMANCE:
3016                         if (ui_class == ATOM_PPLIB_CLASSIFICATION_UI_PERFORMANCE) {
3017                                 if (ps->caps & ATOM_PPLIB_SINGLE_DISPLAY_ONLY) {
3018                                         if (single_display)
3019                                                 return ps;
3020                                 } else
3021                                         return ps;
3022                         }
3023                         break;
3024                 /* internal states */
3025                 case POWER_STATE_TYPE_INTERNAL_UVD:
3026                         if (adev->pm.dpm.uvd_ps)
3027                                 return adev->pm.dpm.uvd_ps;
3028                         else
3029                                 break;
3030                 case POWER_STATE_TYPE_INTERNAL_UVD_SD:
3031                         if (ps->class & ATOM_PPLIB_CLASSIFICATION_SDSTATE)
3032                                 return ps;
3033                         break;
3034                 case POWER_STATE_TYPE_INTERNAL_UVD_HD:
3035                         if (ps->class & ATOM_PPLIB_CLASSIFICATION_HDSTATE)
3036                                 return ps;
3037                         break;
3038                 case POWER_STATE_TYPE_INTERNAL_UVD_HD2:
3039                         if (ps->class & ATOM_PPLIB_CLASSIFICATION_HD2STATE)
3040                                 return ps;
3041                         break;
3042                 case POWER_STATE_TYPE_INTERNAL_UVD_MVC:
3043                         if (ps->class2 & ATOM_PPLIB_CLASSIFICATION2_MVC)
3044                                 return ps;
3045                         break;
3046                 case POWER_STATE_TYPE_INTERNAL_BOOT:
3047                         return adev->pm.dpm.boot_ps;
3048                 case POWER_STATE_TYPE_INTERNAL_THERMAL:
3049                         if (ps->class & ATOM_PPLIB_CLASSIFICATION_THERMAL)
3050                                 return ps;
3051                         break;
3052                 case POWER_STATE_TYPE_INTERNAL_ACPI:
3053                         if (ps->class & ATOM_PPLIB_CLASSIFICATION_ACPI)
3054                                 return ps;
3055                         break;
3056                 case POWER_STATE_TYPE_INTERNAL_ULV:
3057                         if (ps->class2 & ATOM_PPLIB_CLASSIFICATION2_ULV)
3058                                 return ps;
3059                         break;
3060                 case POWER_STATE_TYPE_INTERNAL_3DPERF:
3061                         if (ps->class & ATOM_PPLIB_CLASSIFICATION_3DPERFORMANCE)
3062                                 return ps;
3063                         break;
3064                 default:
3065                         break;
3066                 }
3067         }
3068         /* use a fallback state if we didn't match */
3069         switch (dpm_state) {
3070         case POWER_STATE_TYPE_INTERNAL_UVD_SD:
3071                 dpm_state = POWER_STATE_TYPE_INTERNAL_UVD_HD;
3072                 goto restart_search;
3073         case POWER_STATE_TYPE_INTERNAL_UVD_HD:
3074         case POWER_STATE_TYPE_INTERNAL_UVD_HD2:
3075         case POWER_STATE_TYPE_INTERNAL_UVD_MVC:
3076                 if (adev->pm.dpm.uvd_ps) {
3077                         return adev->pm.dpm.uvd_ps;
3078                 } else {
3079                         dpm_state = POWER_STATE_TYPE_PERFORMANCE;
3080                         goto restart_search;
3081                 }
3082         case POWER_STATE_TYPE_INTERNAL_THERMAL:
3083                 dpm_state = POWER_STATE_TYPE_INTERNAL_ACPI;
3084                 goto restart_search;
3085         case POWER_STATE_TYPE_INTERNAL_ACPI:
3086                 dpm_state = POWER_STATE_TYPE_BATTERY;
3087                 goto restart_search;
3088         case POWER_STATE_TYPE_BATTERY:
3089         case POWER_STATE_TYPE_BALANCED:
3090         case POWER_STATE_TYPE_INTERNAL_3DPERF:
3091                 dpm_state = POWER_STATE_TYPE_PERFORMANCE;
3092                 goto restart_search;
3093         default:
3094                 break;
3095         }
3096
3097         return NULL;
3098 }
3099
3100 static void amdgpu_dpm_change_power_state_locked(struct amdgpu_device *adev)
3101 {
3102         struct amdgpu_ps *ps;
3103         enum amd_pm_state_type dpm_state;
3104         int ret;
3105         bool equal = false;
3106
3107         /* if dpm init failed */
3108         if (!adev->pm.dpm_enabled)
3109                 return;
3110
3111         if (adev->pm.dpm.user_state != adev->pm.dpm.state) {
3112                 /* add other state override checks here */
3113                 if ((!adev->pm.dpm.thermal_active) &&
3114                     (!adev->pm.dpm.uvd_active))
3115                         adev->pm.dpm.state = adev->pm.dpm.user_state;
3116         }
3117         dpm_state = adev->pm.dpm.state;
3118
3119         ps = amdgpu_dpm_pick_power_state(adev, dpm_state);
3120         if (ps)
3121                 adev->pm.dpm.requested_ps = ps;
3122         else
3123                 return;
3124
3125         if (amdgpu_dpm == 1 && adev->powerplay.pp_funcs->print_power_state) {
3126                 printk("switching from power state:\n");
3127                 amdgpu_dpm_print_power_state(adev, adev->pm.dpm.current_ps);
3128                 printk("switching to power state:\n");
3129                 amdgpu_dpm_print_power_state(adev, adev->pm.dpm.requested_ps);
3130         }
3131
3132         /* update whether vce is active */
3133         ps->vce_active = adev->pm.dpm.vce_active;
3134         if (adev->powerplay.pp_funcs->display_configuration_changed)
3135                 amdgpu_dpm_display_configuration_changed(adev);
3136
3137         ret = amdgpu_dpm_pre_set_power_state(adev);
3138         if (ret)
3139                 return;
3140
3141         if (adev->powerplay.pp_funcs->check_state_equal) {
3142                 if (0 != amdgpu_dpm_check_state_equal(adev, adev->pm.dpm.current_ps, adev->pm.dpm.requested_ps, &equal))
3143                         equal = false;
3144         }
3145
3146         if (equal)
3147                 return;
3148
3149         amdgpu_dpm_set_power_state(adev);
3150         amdgpu_dpm_post_set_power_state(adev);
3151
3152         adev->pm.dpm.current_active_crtcs = adev->pm.dpm.new_active_crtcs;
3153         adev->pm.dpm.current_active_crtc_count = adev->pm.dpm.new_active_crtc_count;
3154
3155         if (adev->powerplay.pp_funcs->force_performance_level) {
3156                 if (adev->pm.dpm.thermal_active) {
3157                         enum amd_dpm_forced_level level = adev->pm.dpm.forced_level;
3158                         /* force low perf level for thermal */
3159                         amdgpu_dpm_force_performance_level(adev, AMD_DPM_FORCED_LEVEL_LOW);
3160                         /* save the user's level */
3161                         adev->pm.dpm.forced_level = level;
3162                 } else {
3163                         /* otherwise, user selected level */
3164                         amdgpu_dpm_force_performance_level(adev, adev->pm.dpm.forced_level);
3165                 }
3166         }
3167 }
3168
3169 void amdgpu_dpm_enable_uvd(struct amdgpu_device *adev, bool enable)
3170 {
3171         int ret = 0;
3172
3173         ret = amdgpu_dpm_set_powergating_by_smu(adev, AMD_IP_BLOCK_TYPE_UVD, !enable);
3174         if (ret)
3175                 DRM_ERROR("Dpm %s uvd failed, ret = %d. \n",
3176                           enable ? "enable" : "disable", ret);
3177
3178         /* enable/disable Low Memory PState for UVD (4k videos) */
3179         if (adev->asic_type == CHIP_STONEY &&
3180                 adev->uvd.decode_image_width >= WIDTH_4K) {
3181                 struct pp_hwmgr *hwmgr = adev->powerplay.pp_handle;
3182
3183                 if (hwmgr && hwmgr->hwmgr_func &&
3184                     hwmgr->hwmgr_func->update_nbdpm_pstate)
3185                         hwmgr->hwmgr_func->update_nbdpm_pstate(hwmgr,
3186                                                                !enable,
3187                                                                true);
3188         }
3189 }
3190
3191 void amdgpu_dpm_enable_vce(struct amdgpu_device *adev, bool enable)
3192 {
3193         int ret = 0;
3194
3195         ret = amdgpu_dpm_set_powergating_by_smu(adev, AMD_IP_BLOCK_TYPE_VCE, !enable);
3196         if (ret)
3197                 DRM_ERROR("Dpm %s vce failed, ret = %d. \n",
3198                           enable ? "enable" : "disable", ret);
3199 }
3200
3201 void amdgpu_pm_print_power_states(struct amdgpu_device *adev)
3202 {
3203         int i;
3204
3205         if (adev->powerplay.pp_funcs->print_power_state == NULL)
3206                 return;
3207
3208         for (i = 0; i < adev->pm.dpm.num_ps; i++)
3209                 amdgpu_dpm_print_power_state(adev, &adev->pm.dpm.ps[i]);
3210
3211 }
3212
3213 void amdgpu_dpm_enable_jpeg(struct amdgpu_device *adev, bool enable)
3214 {
3215         int ret = 0;
3216
3217         ret = amdgpu_dpm_set_powergating_by_smu(adev, AMD_IP_BLOCK_TYPE_JPEG, !enable);
3218         if (ret)
3219                 DRM_ERROR("Dpm %s jpeg failed, ret = %d. \n",
3220                           enable ? "enable" : "disable", ret);
3221 }
3222
3223 int amdgpu_pm_load_smu_firmware(struct amdgpu_device *adev, uint32_t *smu_version)
3224 {
3225         int r;
3226
3227         if (adev->powerplay.pp_funcs && adev->powerplay.pp_funcs->load_firmware) {
3228                 r = adev->powerplay.pp_funcs->load_firmware(adev->powerplay.pp_handle);
3229                 if (r) {
3230                         pr_err("smu firmware loading failed\n");
3231                         return r;
3232                 }
3233                 *smu_version = adev->pm.fw_version;
3234         }
3235         return 0;
3236 }
3237
3238 int amdgpu_pm_sysfs_init(struct amdgpu_device *adev)
3239 {
3240         struct pp_hwmgr *hwmgr = adev->powerplay.pp_handle;
3241         int ret;
3242
3243         if (adev->pm.sysfs_initialized)
3244                 return 0;
3245
3246         if (adev->pm.dpm_enabled == 0)
3247                 return 0;
3248
3249         adev->pm.int_hwmon_dev = hwmon_device_register_with_groups(adev->dev,
3250                                                                    DRIVER_NAME, adev,
3251                                                                    hwmon_groups);
3252         if (IS_ERR(adev->pm.int_hwmon_dev)) {
3253                 ret = PTR_ERR(adev->pm.int_hwmon_dev);
3254                 dev_err(adev->dev,
3255                         "Unable to register hwmon device: %d\n", ret);
3256                 return ret;
3257         }
3258
3259         ret = device_create_file(adev->dev, &dev_attr_power_dpm_state);
3260         if (ret) {
3261                 DRM_ERROR("failed to create device file for dpm state\n");
3262                 return ret;
3263         }
3264         ret = device_create_file(adev->dev, &dev_attr_power_dpm_force_performance_level);
3265         if (ret) {
3266                 DRM_ERROR("failed to create device file for dpm state\n");
3267                 return ret;
3268         }
3269
3270
3271         ret = device_create_file(adev->dev, &dev_attr_pp_num_states);
3272         if (ret) {
3273                 DRM_ERROR("failed to create device file pp_num_states\n");
3274                 return ret;
3275         }
3276         ret = device_create_file(adev->dev, &dev_attr_pp_cur_state);
3277         if (ret) {
3278                 DRM_ERROR("failed to create device file pp_cur_state\n");
3279                 return ret;
3280         }
3281         ret = device_create_file(adev->dev, &dev_attr_pp_force_state);
3282         if (ret) {
3283                 DRM_ERROR("failed to create device file pp_force_state\n");
3284                 return ret;
3285         }
3286         ret = device_create_file(adev->dev, &dev_attr_pp_table);
3287         if (ret) {
3288                 DRM_ERROR("failed to create device file pp_table\n");
3289                 return ret;
3290         }
3291
3292         ret = device_create_file(adev->dev, &dev_attr_pp_dpm_sclk);
3293         if (ret) {
3294                 DRM_ERROR("failed to create device file pp_dpm_sclk\n");
3295                 return ret;
3296         }
3297
3298         /* Arcturus does not support standalone mclk/socclk/fclk level setting */
3299         if (adev->asic_type == CHIP_ARCTURUS) {
3300                 dev_attr_pp_dpm_mclk.attr.mode &= ~S_IWUGO;
3301                 dev_attr_pp_dpm_mclk.store = NULL;
3302
3303                 dev_attr_pp_dpm_socclk.attr.mode &= ~S_IWUGO;
3304                 dev_attr_pp_dpm_socclk.store = NULL;
3305
3306                 dev_attr_pp_dpm_fclk.attr.mode &= ~S_IWUGO;
3307                 dev_attr_pp_dpm_fclk.store = NULL;
3308         }
3309
3310         ret = device_create_file(adev->dev, &dev_attr_pp_dpm_mclk);
3311         if (ret) {
3312                 DRM_ERROR("failed to create device file pp_dpm_mclk\n");
3313                 return ret;
3314         }
3315         if (adev->asic_type >= CHIP_VEGA10) {
3316                 ret = device_create_file(adev->dev, &dev_attr_pp_dpm_socclk);
3317                 if (ret) {
3318                         DRM_ERROR("failed to create device file pp_dpm_socclk\n");
3319                         return ret;
3320                 }
3321                 if (adev->asic_type != CHIP_ARCTURUS) {
3322                         ret = device_create_file(adev->dev, &dev_attr_pp_dpm_dcefclk);
3323                         if (ret) {
3324                                 DRM_ERROR("failed to create device file pp_dpm_dcefclk\n");
3325                                 return ret;
3326                         }
3327                 }
3328         }
3329         if (adev->asic_type >= CHIP_VEGA20) {
3330                 ret = device_create_file(adev->dev, &dev_attr_pp_dpm_fclk);
3331                 if (ret) {
3332                         DRM_ERROR("failed to create device file pp_dpm_fclk\n");
3333                         return ret;
3334                 }
3335         }
3336         if (adev->asic_type != CHIP_ARCTURUS) {
3337                 ret = device_create_file(adev->dev, &dev_attr_pp_dpm_pcie);
3338                 if (ret) {
3339                         DRM_ERROR("failed to create device file pp_dpm_pcie\n");
3340                         return ret;
3341                 }
3342         }
3343         ret = device_create_file(adev->dev, &dev_attr_pp_sclk_od);
3344         if (ret) {
3345                 DRM_ERROR("failed to create device file pp_sclk_od\n");
3346                 return ret;
3347         }
3348         ret = device_create_file(adev->dev, &dev_attr_pp_mclk_od);
3349         if (ret) {
3350                 DRM_ERROR("failed to create device file pp_mclk_od\n");
3351                 return ret;
3352         }
3353         ret = device_create_file(adev->dev,
3354                         &dev_attr_pp_power_profile_mode);
3355         if (ret) {
3356                 DRM_ERROR("failed to create device file "
3357                                 "pp_power_profile_mode\n");
3358                 return ret;
3359         }
3360         if ((is_support_sw_smu(adev) && adev->smu.od_enabled) ||
3361             (!is_support_sw_smu(adev) && hwmgr->od_enabled)) {
3362                 ret = device_create_file(adev->dev,
3363                                 &dev_attr_pp_od_clk_voltage);
3364                 if (ret) {
3365                         DRM_ERROR("failed to create device file "
3366                                         "pp_od_clk_voltage\n");
3367                         return ret;
3368                 }
3369         }
3370         ret = device_create_file(adev->dev,
3371                         &dev_attr_gpu_busy_percent);
3372         if (ret) {
3373                 DRM_ERROR("failed to create device file "
3374                                 "gpu_busy_level\n");
3375                 return ret;
3376         }
3377         /* APU does not have its own dedicated memory */
3378         if (!(adev->flags & AMD_IS_APU) &&
3379              (adev->asic_type != CHIP_VEGA10)) {
3380                 ret = device_create_file(adev->dev,
3381                                 &dev_attr_mem_busy_percent);
3382                 if (ret) {
3383                         DRM_ERROR("failed to create device file "
3384                                         "mem_busy_percent\n");
3385                         return ret;
3386                 }
3387         }
3388         /* PCIe Perf counters won't work on APU nodes */
3389         if (!(adev->flags & AMD_IS_APU)) {
3390                 ret = device_create_file(adev->dev, &dev_attr_pcie_bw);
3391                 if (ret) {
3392                         DRM_ERROR("failed to create device file pcie_bw\n");
3393                         return ret;
3394                 }
3395         }
3396         if (adev->unique_id)
3397                 ret = device_create_file(adev->dev, &dev_attr_unique_id);
3398         if (ret) {
3399                 DRM_ERROR("failed to create device file unique_id\n");
3400                 return ret;
3401         }
3402
3403         if ((adev->asic_type >= CHIP_VEGA10) &&
3404             !(adev->flags & AMD_IS_APU)) {
3405                 ret = device_create_file(adev->dev,
3406                                 &dev_attr_pp_features);
3407                 if (ret) {
3408                         DRM_ERROR("failed to create device file "
3409                                         "pp_features\n");
3410                         return ret;
3411                 }
3412         }
3413
3414         adev->pm.sysfs_initialized = true;
3415
3416         return 0;
3417 }
3418
3419 void amdgpu_pm_sysfs_fini(struct amdgpu_device *adev)
3420 {
3421         struct pp_hwmgr *hwmgr = adev->powerplay.pp_handle;
3422
3423         if (adev->pm.dpm_enabled == 0)
3424                 return;
3425
3426         if (adev->pm.int_hwmon_dev)
3427                 hwmon_device_unregister(adev->pm.int_hwmon_dev);
3428         device_remove_file(adev->dev, &dev_attr_power_dpm_state);
3429         device_remove_file(adev->dev, &dev_attr_power_dpm_force_performance_level);
3430
3431         device_remove_file(adev->dev, &dev_attr_pp_num_states);
3432         device_remove_file(adev->dev, &dev_attr_pp_cur_state);
3433         device_remove_file(adev->dev, &dev_attr_pp_force_state);
3434         device_remove_file(adev->dev, &dev_attr_pp_table);
3435
3436         device_remove_file(adev->dev, &dev_attr_pp_dpm_sclk);
3437         device_remove_file(adev->dev, &dev_attr_pp_dpm_mclk);
3438         if (adev->asic_type >= CHIP_VEGA10) {
3439                 device_remove_file(adev->dev, &dev_attr_pp_dpm_socclk);
3440                 if (adev->asic_type != CHIP_ARCTURUS)
3441                         device_remove_file(adev->dev, &dev_attr_pp_dpm_dcefclk);
3442         }
3443         if (adev->asic_type != CHIP_ARCTURUS)
3444                 device_remove_file(adev->dev, &dev_attr_pp_dpm_pcie);
3445         if (adev->asic_type >= CHIP_VEGA20)
3446                 device_remove_file(adev->dev, &dev_attr_pp_dpm_fclk);
3447         device_remove_file(adev->dev, &dev_attr_pp_sclk_od);
3448         device_remove_file(adev->dev, &dev_attr_pp_mclk_od);
3449         device_remove_file(adev->dev,
3450                         &dev_attr_pp_power_profile_mode);
3451         if ((is_support_sw_smu(adev) && adev->smu.od_enabled) ||
3452             (!is_support_sw_smu(adev) && hwmgr->od_enabled))
3453                 device_remove_file(adev->dev,
3454                                 &dev_attr_pp_od_clk_voltage);
3455         device_remove_file(adev->dev, &dev_attr_gpu_busy_percent);
3456         if (!(adev->flags & AMD_IS_APU) &&
3457              (adev->asic_type != CHIP_VEGA10))
3458                 device_remove_file(adev->dev, &dev_attr_mem_busy_percent);
3459         if (!(adev->flags & AMD_IS_APU))
3460                 device_remove_file(adev->dev, &dev_attr_pcie_bw);
3461         if (adev->unique_id)
3462                 device_remove_file(adev->dev, &dev_attr_unique_id);
3463         if ((adev->asic_type >= CHIP_VEGA10) &&
3464             !(adev->flags & AMD_IS_APU))
3465                 device_remove_file(adev->dev, &dev_attr_pp_features);
3466 }
3467
3468 void amdgpu_pm_compute_clocks(struct amdgpu_device *adev)
3469 {
3470         int i = 0;
3471
3472         if (!adev->pm.dpm_enabled)
3473                 return;
3474
3475         if (adev->mode_info.num_crtc)
3476                 amdgpu_display_bandwidth_update(adev);
3477
3478         for (i = 0; i < AMDGPU_MAX_RINGS; i++) {
3479                 struct amdgpu_ring *ring = adev->rings[i];
3480                 if (ring && ring->sched.ready)
3481                         amdgpu_fence_wait_empty(ring);
3482         }
3483
3484         if (is_support_sw_smu(adev)) {
3485                 struct smu_dpm_context *smu_dpm = &adev->smu.smu_dpm;
3486                 smu_handle_task(&adev->smu,
3487                                 smu_dpm->dpm_level,
3488                                 AMD_PP_TASK_DISPLAY_CONFIG_CHANGE,
3489                                 true);
3490         } else {
3491                 if (adev->powerplay.pp_funcs->dispatch_tasks) {
3492                         if (!amdgpu_device_has_dc_support(adev)) {
3493                                 mutex_lock(&adev->pm.mutex);
3494                                 amdgpu_dpm_get_active_displays(adev);
3495                                 adev->pm.pm_display_cfg.num_display = adev->pm.dpm.new_active_crtc_count;
3496                                 adev->pm.pm_display_cfg.vrefresh = amdgpu_dpm_get_vrefresh(adev);
3497                                 adev->pm.pm_display_cfg.min_vblank_time = amdgpu_dpm_get_vblank_time(adev);
3498                                 /* we have issues with mclk switching with refresh rates over 120 hz on the non-DC code. */
3499                                 if (adev->pm.pm_display_cfg.vrefresh > 120)
3500                                         adev->pm.pm_display_cfg.min_vblank_time = 0;
3501                                 if (adev->powerplay.pp_funcs->display_configuration_change)
3502                                         adev->powerplay.pp_funcs->display_configuration_change(
3503                                                                         adev->powerplay.pp_handle,
3504                                                                         &adev->pm.pm_display_cfg);
3505                                 mutex_unlock(&adev->pm.mutex);
3506                         }
3507                         amdgpu_dpm_dispatch_task(adev, AMD_PP_TASK_DISPLAY_CONFIG_CHANGE, NULL);
3508                 } else {
3509                         mutex_lock(&adev->pm.mutex);
3510                         amdgpu_dpm_get_active_displays(adev);
3511                         amdgpu_dpm_change_power_state_locked(adev);
3512                         mutex_unlock(&adev->pm.mutex);
3513                 }
3514         }
3515 }
3516
3517 /*
3518  * Debugfs info
3519  */
3520 #if defined(CONFIG_DEBUG_FS)
3521
3522 static int amdgpu_debugfs_pm_info_pp(struct seq_file *m, struct amdgpu_device *adev)
3523 {
3524         uint32_t value;
3525         uint64_t value64;
3526         uint32_t query = 0;
3527         int size;
3528
3529         /* GPU Clocks */
3530         size = sizeof(value);
3531         seq_printf(m, "GFX Clocks and Power:\n");
3532         if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_GFX_MCLK, (void *)&value, &size))
3533                 seq_printf(m, "\t%u MHz (MCLK)\n", value/100);
3534         if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_GFX_SCLK, (void *)&value, &size))
3535                 seq_printf(m, "\t%u MHz (SCLK)\n", value/100);
3536         if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_STABLE_PSTATE_SCLK, (void *)&value, &size))
3537                 seq_printf(m, "\t%u MHz (PSTATE_SCLK)\n", value/100);
3538         if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_STABLE_PSTATE_MCLK, (void *)&value, &size))
3539                 seq_printf(m, "\t%u MHz (PSTATE_MCLK)\n", value/100);
3540         if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_VDDGFX, (void *)&value, &size))
3541                 seq_printf(m, "\t%u mV (VDDGFX)\n", value);
3542         if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_VDDNB, (void *)&value, &size))
3543                 seq_printf(m, "\t%u mV (VDDNB)\n", value);
3544         size = sizeof(uint32_t);
3545         if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_GPU_POWER, (void *)&query, &size))
3546                 seq_printf(m, "\t%u.%u W (average GPU)\n", query >> 8, query & 0xff);
3547         size = sizeof(value);
3548         seq_printf(m, "\n");
3549
3550         /* GPU Temp */
3551         if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_GPU_TEMP, (void *)&value, &size))
3552                 seq_printf(m, "GPU Temperature: %u C\n", value/1000);
3553
3554         /* GPU Load */
3555         if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_GPU_LOAD, (void *)&value, &size))
3556                 seq_printf(m, "GPU Load: %u %%\n", value);
3557         /* MEM Load */
3558         if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_MEM_LOAD, (void *)&value, &size))
3559                 seq_printf(m, "MEM Load: %u %%\n", value);
3560
3561         seq_printf(m, "\n");
3562
3563         /* SMC feature mask */
3564         if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_ENABLED_SMC_FEATURES_MASK, (void *)&value64, &size))
3565                 seq_printf(m, "SMC Feature Mask: 0x%016llx\n", value64);
3566
3567         if (adev->asic_type > CHIP_VEGA20) {
3568                 /* VCN clocks */
3569                 if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_VCN_POWER_STATE, (void *)&value, &size)) {
3570                         if (!value) {
3571                                 seq_printf(m, "VCN: Disabled\n");
3572                         } else {
3573                                 seq_printf(m, "VCN: Enabled\n");
3574                                 if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_UVD_DCLK, (void *)&value, &size))
3575                                         seq_printf(m, "\t%u MHz (DCLK)\n", value/100);
3576                                 if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_UVD_VCLK, (void *)&value, &size))
3577                                         seq_printf(m, "\t%u MHz (VCLK)\n", value/100);
3578                         }
3579                 }
3580                 seq_printf(m, "\n");
3581         } else {
3582                 /* UVD clocks */
3583                 if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_UVD_POWER, (void *)&value, &size)) {
3584                         if (!value) {
3585                                 seq_printf(m, "UVD: Disabled\n");
3586                         } else {
3587                                 seq_printf(m, "UVD: Enabled\n");
3588                                 if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_UVD_DCLK, (void *)&value, &size))
3589                                         seq_printf(m, "\t%u MHz (DCLK)\n", value/100);
3590                                 if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_UVD_VCLK, (void *)&value, &size))
3591                                         seq_printf(m, "\t%u MHz (VCLK)\n", value/100);
3592                         }
3593                 }
3594                 seq_printf(m, "\n");
3595
3596                 /* VCE clocks */
3597                 if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_VCE_POWER, (void *)&value, &size)) {
3598                         if (!value) {
3599                                 seq_printf(m, "VCE: Disabled\n");
3600                         } else {
3601                                 seq_printf(m, "VCE: Enabled\n");
3602                                 if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_VCE_ECCLK, (void *)&value, &size))
3603                                         seq_printf(m, "\t%u MHz (ECCLK)\n", value/100);
3604                         }
3605                 }
3606         }
3607
3608         return 0;
3609 }
3610
3611 static void amdgpu_parse_cg_state(struct seq_file *m, u32 flags)
3612 {
3613         int i;
3614
3615         for (i = 0; clocks[i].flag; i++)
3616                 seq_printf(m, "\t%s: %s\n", clocks[i].name,
3617                            (flags & clocks[i].flag) ? "On" : "Off");
3618 }
3619
3620 static int amdgpu_debugfs_pm_info(struct seq_file *m, void *data)
3621 {
3622         struct drm_info_node *node = (struct drm_info_node *) m->private;
3623         struct drm_device *dev = node->minor->dev;
3624         struct amdgpu_device *adev = dev->dev_private;
3625         u32 flags = 0;
3626         int r;
3627
3628         r = pm_runtime_get_sync(dev->dev);
3629         if (r < 0)
3630                 return r;
3631
3632         amdgpu_device_ip_get_clockgating_state(adev, &flags);
3633         seq_printf(m, "Clock Gating Flags Mask: 0x%x\n", flags);
3634         amdgpu_parse_cg_state(m, flags);
3635         seq_printf(m, "\n");
3636
3637         if (!adev->pm.dpm_enabled) {
3638                 seq_printf(m, "dpm not enabled\n");
3639                 pm_runtime_mark_last_busy(dev->dev);
3640                 pm_runtime_put_autosuspend(dev->dev);
3641                 return 0;
3642         }
3643
3644         if (!is_support_sw_smu(adev) &&
3645             adev->powerplay.pp_funcs->debugfs_print_current_performance_level) {
3646                 mutex_lock(&adev->pm.mutex);
3647                 if (adev->powerplay.pp_funcs->debugfs_print_current_performance_level)
3648                         adev->powerplay.pp_funcs->debugfs_print_current_performance_level(adev, m);
3649                 else
3650                         seq_printf(m, "Debugfs support not implemented for this asic\n");
3651                 mutex_unlock(&adev->pm.mutex);
3652                 r = 0;
3653         } else {
3654                 r = amdgpu_debugfs_pm_info_pp(m, adev);
3655         }
3656
3657         pm_runtime_mark_last_busy(dev->dev);
3658         pm_runtime_put_autosuspend(dev->dev);
3659
3660         return r;
3661 }
3662
3663 static const struct drm_info_list amdgpu_pm_info_list[] = {
3664         {"amdgpu_pm_info", amdgpu_debugfs_pm_info, 0, NULL},
3665 };
3666 #endif
3667
3668 int amdgpu_debugfs_pm_init(struct amdgpu_device *adev)
3669 {
3670 #if defined(CONFIG_DEBUG_FS)
3671         return amdgpu_debugfs_add_files(adev, amdgpu_pm_info_list, ARRAY_SIZE(amdgpu_pm_info_list));
3672 #else
3673         return 0;
3674 #endif
3675 }