drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c

   1 /*
   2  * Copyright 2009 Jerome Glisse.
   3  * All Rights Reserved.
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the
   7  * "Software"), to deal in the Software without restriction, including
   8  * without limitation the rights to use, copy, modify, merge, publish,
   9  * distribute, sub license, and/or sell copies of the Software, and to
  10  * permit persons to whom the Software is furnished to do so, subject to
  11  * the following conditions:
  12  *
  13  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  14  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  15  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  16  * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
  17  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  18  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  19  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  20  *
  21  * The above copyright notice and this permission notice (including the
  22  * next paragraph) shall be included in all copies or substantial portions
  23  * of the Software.
  24  *
  25  */
  26 /*
  27  * Authors:
  28  *    Jerome Glisse <[email protected]>
  29  *    Thomas Hellstrom <thomas-at-tungstengraphics-dot-com>
  30  *    Dave Airlie
  31  */
  32 #include <drm/ttm/ttm_bo_api.h>
  33 #include <drm/ttm/ttm_bo_driver.h>
  34 #include <drm/ttm/ttm_placement.h>
  35 #include <drm/ttm/ttm_module.h>
  36 #include <drm/ttm/ttm_page_alloc.h>
  37 #include <drm/drmP.h>
  38 #include <drm/amdgpu_drm.h>
  39 #include <linux/seq_file.h>
  40 #include <linux/slab.h>
  41 #include <linux/swiotlb.h>
  42 #include <linux/swap.h>
  43 #include <linux/pagemap.h>
  44 #include <linux/debugfs.h>
  45 #include <linux/iommu.h>
  46 #include "amdgpu.h"
  47 #include "amdgpu_object.h"
  48 #include "amdgpu_trace.h"
  49 #include "amdgpu_amdkfd.h"
  50 #include "amdgpu_sdma.h"
  51 #include "bif/bif_4_1_d.h"
  52
  53 #define DRM_FILE_PAGE_OFFSET (0x100000000ULL >> PAGE_SHIFT)
  54
  55 static int amdgpu_map_buffer(struct ttm_buffer_object *bo,
  56                              struct ttm_mem_reg *mem, unsigned num_pages,
  57                              uint64_t offset, unsigned window,
  58                              struct amdgpu_ring *ring,
  59                              uint64_t *addr);
  60
  61 static int amdgpu_ttm_debugfs_init(struct amdgpu_device *adev);
  62 static void amdgpu_ttm_debugfs_fini(struct amdgpu_device *adev);
  63
  64 /*
  65  * Global memory.
  66  */
  67
  68 /**
  69  * amdgpu_ttm_mem_global_init - Initialize and acquire reference to
  70  * memory object
  71  *
  72  * @ref: Object for initialization.
  73  *
  74  * This is called by drm_global_item_ref() when an object is being
  75  * initialized.
  76  */
  77 static int amdgpu_ttm_mem_global_init(struct drm_global_reference *ref)
  78 {
  79         return ttm_mem_global_init(ref->object);
  80 }
  81
  82 /**
  83  * amdgpu_ttm_mem_global_release - Drop reference to a memory object
  84  *
  85  * @ref: Object being removed
  86  *
  87  * This is called by drm_global_item_unref() when an object is being
  88  * released.
  89  */
  90 static void amdgpu_ttm_mem_global_release(struct drm_global_reference *ref)
  91 {
  92         ttm_mem_global_release(ref->object);
  93 }
  94
  95 /**
  96  * amdgpu_ttm_global_init - Initialize global TTM memory reference structures.
  97  *
  98  * @adev: AMDGPU device for which the global structures need to be registered.
  99  *
 100  * This is called as part of the AMDGPU ttm init from amdgpu_ttm_init()
 101  * during bring up.
 102  */
 103 static int amdgpu_ttm_global_init(struct amdgpu_device *adev)
 104 {
 105         struct drm_global_reference *global_ref;
 106         int r;
 107
 108         /* ensure reference is false in case init fails */
 109         adev->mman.mem_global_referenced = false;
 110
 111         global_ref = &adev->mman.mem_global_ref;
 112         global_ref->global_type = DRM_GLOBAL_TTM_MEM;
 113         global_ref->size = sizeof(struct ttm_mem_global);
 114         global_ref->init = &amdgpu_ttm_mem_global_init;
 115         global_ref->release = &amdgpu_ttm_mem_global_release;
 116         r = drm_global_item_ref(global_ref);
 117         if (r) {
 118                 DRM_ERROR("Failed setting up TTM memory accounting "
 119                           "subsystem.\n");
 120                 goto error_mem;
 121         }
 122
 123         adev->mman.bo_global_ref.mem_glob =
 124                 adev->mman.mem_global_ref.object;
 125         global_ref = &adev->mman.bo_global_ref.ref;
 126         global_ref->global_type = DRM_GLOBAL_TTM_BO;
 127         global_ref->size = sizeof(struct ttm_bo_global);
 128         global_ref->init = &ttm_bo_global_init;
 129         global_ref->release = &ttm_bo_global_release;
 130         r = drm_global_item_ref(global_ref);
 131         if (r) {
 132                 DRM_ERROR("Failed setting up TTM BO subsystem.\n");
 133                 goto error_bo;
 134         }
 135
 136         mutex_init(&adev->mman.gtt_window_lock);
 137
 138         adev->mman.mem_global_referenced = true;
 139
 140         return 0;
 141
 142 error_bo:
 143         drm_global_item_unref(&adev->mman.mem_global_ref);
 144 error_mem:
 145         return r;
 146 }
 147
 148 static void amdgpu_ttm_global_fini(struct amdgpu_device *adev)
 149 {
 150         if (adev->mman.mem_global_referenced) {
 151                 mutex_destroy(&adev->mman.gtt_window_lock);
 152                 drm_global_item_unref(&adev->mman.bo_global_ref.ref);
 153                 drm_global_item_unref(&adev->mman.mem_global_ref);
 154                 adev->mman.mem_global_referenced = false;
 155         }
 156 }
 157
 158 static int amdgpu_invalidate_caches(struct ttm_bo_device *bdev, uint32_t flags)
 159 {
 160         return 0;
 161 }
 162
 163 /**
 164  * amdgpu_init_mem_type - Initialize a memory manager for a specific type of
 165  * memory request.
 166  *
 167  * @bdev: The TTM BO device object (contains a reference to amdgpu_device)
 168  * @type: The type of memory requested
 169  * @man: The memory type manager for each domain
 170  *
 171  * This is called by ttm_bo_init_mm() when a buffer object is being
 172  * initialized.
 173  */
 174 static int amdgpu_init_mem_type(struct ttm_bo_device *bdev, uint32_t type,
 175                                 struct ttm_mem_type_manager *man)
 176 {
 177         struct amdgpu_device *adev;
 178
 179         adev = amdgpu_ttm_adev(bdev);
 180
 181         switch (type) {
 182         case TTM_PL_SYSTEM:
 183                 /* System memory */
 184                 man->flags = TTM_MEMTYPE_FLAG_MAPPABLE;
 185                 man->available_caching = TTM_PL_MASK_CACHING;
 186                 man->default_caching = TTM_PL_FLAG_CACHED;
 187                 break;
 188         case TTM_PL_TT:
 189                 /* GTT memory  */
 190                 man->func = &amdgpu_gtt_mgr_func;
 191                 man->gpu_offset = 0;
 192                 man->available_caching = TTM_PL_MASK_CACHING;
 193                 man->default_caching = TTM_PL_FLAG_CACHED;
 194                 man->flags = TTM_MEMTYPE_FLAG_MAPPABLE | TTM_MEMTYPE_FLAG_CMA;
 195                 break;
 196         case TTM_PL_VRAM:
 197                 /* "On-card" video ram */
 198                 man->func = &amdgpu_vram_mgr_func;
 199                 man->gpu_offset = adev->gmc.vram_start;
 200                 man->flags = TTM_MEMTYPE_FLAG_FIXED |
 201                              TTM_MEMTYPE_FLAG_MAPPABLE;
 202                 man->available_caching = TTM_PL_FLAG_UNCACHED | TTM_PL_FLAG_WC;
 203                 man->default_caching = TTM_PL_FLAG_WC;
 204                 break;
 205         case AMDGPU_PL_GDS:
 206         case AMDGPU_PL_GWS:
 207         case AMDGPU_PL_OA:
 208                 /* On-chip GDS memory*/
 209                 man->func = &ttm_bo_manager_func;
 210                 man->gpu_offset = 0;
 211                 man->flags = TTM_MEMTYPE_FLAG_FIXED | TTM_MEMTYPE_FLAG_CMA;
 212                 man->available_caching = TTM_PL_FLAG_UNCACHED;
 213                 man->default_caching = TTM_PL_FLAG_UNCACHED;
 214                 break;
 215         default:
 216                 DRM_ERROR("Unsupported memory type %u\n", (unsigned)type);
 217                 return -EINVAL;
 218         }
 219         return 0;
 220 }
 221
 222 /**
 223  * amdgpu_evict_flags - Compute placement flags
 224  *
 225  * @bo: The buffer object to evict
 226  * @placement: Possible destination(s) for evicted BO
 227  *
 228  * Fill in placement data when ttm_bo_evict() is called
 229  */
 230 static void amdgpu_evict_flags(struct ttm_buffer_object *bo,
 231                                 struct ttm_placement *placement)
 232 {
 233         struct amdgpu_device *adev = amdgpu_ttm_adev(bo->bdev);
 234         struct amdgpu_bo *abo;
 235         static const struct ttm_place placements = {
 236                 .fpfn = 0,
 237                 .lpfn = 0,
 238                 .flags = TTM_PL_MASK_CACHING | TTM_PL_FLAG_SYSTEM
 239         };
 240
 241         /* Don't handle scatter gather BOs */
 242         if (bo->type == ttm_bo_type_sg) {
 243                 placement->num_placement = 0;
 244                 placement->num_busy_placement = 0;
 245                 return;
 246         }
 247
 248         /* Object isn't an AMDGPU object so ignore */
 249         if (!amdgpu_bo_is_amdgpu_bo(bo)) {
 250                 placement->placement = &placements;
 251                 placement->busy_placement = &placements;
 252                 placement->num_placement = 1;
 253                 placement->num_busy_placement = 1;
 254                 return;
 255         }
 256
 257         abo = ttm_to_amdgpu_bo(bo);
 258         switch (bo->mem.mem_type) {
 259         case TTM_PL_VRAM:
 260                 if (!adev->mman.buffer_funcs_enabled) {
 261                         /* Move to system memory */
 262                         amdgpu_bo_placement_from_domain(abo, AMDGPU_GEM_DOMAIN_CPU);
 263                 } else if (!amdgpu_gmc_vram_full_visible(&adev->gmc) &&
 264                            !(abo->flags & AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED) &&
 265                            amdgpu_bo_in_cpu_visible_vram(abo)) {
 266
 267                         /* Try evicting to the CPU inaccessible part of VRAM
 268                          * first, but only set GTT as busy placement, so this
 269                          * BO will be evicted to GTT rather than causing other
 270                          * BOs to be evicted from VRAM
 271                          */
 272                         amdgpu_bo_placement_from_domain(abo, AMDGPU_GEM_DOMAIN_VRAM |
 273                                                          AMDGPU_GEM_DOMAIN_GTT);
 274                         abo->placements[0].fpfn = adev->gmc.visible_vram_size >> PAGE_SHIFT;
 275                         abo->placements[0].lpfn = 0;
 276                         abo->placement.busy_placement = &abo->placements[1];
 277                         abo->placement.num_busy_placement = 1;
 278                 } else {
 279                         /* Move to GTT memory */
 280                         amdgpu_bo_placement_from_domain(abo, AMDGPU_GEM_DOMAIN_GTT);
 281                 }
 282                 break;
 283         case TTM_PL_TT:
 284         default:
 285                 amdgpu_bo_placement_from_domain(abo, AMDGPU_GEM_DOMAIN_CPU);
 286         }
 287         *placement = abo->placement;
 288 }
 289
 290 /**
 291  * amdgpu_verify_access - Verify access for a mmap call
 292  *
 293  * @bo: The buffer object to map
 294  * @filp: The file pointer from the process performing the mmap
 295  *
 296  * This is called by ttm_bo_mmap() to verify whether a process
 297  * has the right to mmap a BO to their process space.
 298  */
 299 static int amdgpu_verify_access(struct ttm_buffer_object *bo, struct file *filp)
 300 {
 301         struct amdgpu_bo *abo = ttm_to_amdgpu_bo(bo);
 302
 303         /*
 304          * Don't verify access for KFD BOs. They don't have a GEM
 305          * object associated with them.
 306          */
 307         if (abo->kfd_bo)
 308                 return 0;
 309
 310         if (amdgpu_ttm_tt_get_usermm(bo->ttm))
 311                 return -EPERM;
 312         return drm_vma_node_verify_access(&abo->gem_base.vma_node,
 313                                           filp->private_data);
 314 }
 315
 316 /**
 317  * amdgpu_move_null - Register memory for a buffer object
 318  *
 319  * @bo: The bo to assign the memory to
 320  * @new_mem: The memory to be assigned.
 321  *
 322  * Assign the memory from new_mem to the memory of the buffer object bo.
 323  */
 324 static void amdgpu_move_null(struct ttm_buffer_object *bo,
 325                              struct ttm_mem_reg *new_mem)
 326 {
 327         struct ttm_mem_reg *old_mem = &bo->mem;
 328
 329         BUG_ON(old_mem->mm_node != NULL);
 330         *old_mem = *new_mem;
 331         new_mem->mm_node = NULL;
 332 }
 333
 334 /**
 335  * amdgpu_mm_node_addr - Compute the GPU relative offset of a GTT buffer.
 336  *
 337  * @bo: The bo to assign the memory to.
 338  * @mm_node: Memory manager node for drm allocator.
 339  * @mem: The region where the bo resides.
 340  *
 341  */
 342 static uint64_t amdgpu_mm_node_addr(struct ttm_buffer_object *bo,
 343                                     struct drm_mm_node *mm_node,
 344                                     struct ttm_mem_reg *mem)
 345 {
 346         uint64_t addr = 0;
 347
 348         if (mm_node->start != AMDGPU_BO_INVALID_OFFSET) {
 349                 addr = mm_node->start << PAGE_SHIFT;
 350                 addr += bo->bdev->man[mem->mem_type].gpu_offset;
 351         }
 352         return addr;
 353 }
 354
 355 /**
 356  * amdgpu_find_mm_node - Helper function finds the drm_mm_node corresponding to
 357  * @offset. It also modifies the offset to be within the drm_mm_node returned
 358  *
 359  * @mem: The region where the bo resides.
 360  * @offset: The offset that drm_mm_node is used for finding.
 361  *
 362  */
 363 static struct drm_mm_node *amdgpu_find_mm_node(struct ttm_mem_reg *mem,
 364                                                unsigned long *offset)
 365 {
 366         struct drm_mm_node *mm_node = mem->mm_node;
 367
 368         while (*offset >= (mm_node->size << PAGE_SHIFT)) {
 369                 *offset -= (mm_node->size << PAGE_SHIFT);
 370                 ++mm_node;
 371         }
 372         return mm_node;
 373 }
 374
 375 /**
 376  * amdgpu_copy_ttm_mem_to_mem - Helper function for copy
 377  *
 378  * The function copies @size bytes from {src->mem + src->offset} to
 379  * {dst->mem + dst->offset}. src->bo and dst->bo could be same BO for a
 380  * move and different for a BO to BO copy.
 381  *
 382  * @f: Returns the last fence if multiple jobs are submitted.
 383  */
 384 int amdgpu_ttm_copy_mem_to_mem(struct amdgpu_device *adev,
 385                                struct amdgpu_copy_mem *src,
 386                                struct amdgpu_copy_mem *dst,
 387                                uint64_t size,
 388                                struct reservation_object *resv,
 389                                struct dma_fence **f)
 390 {
 391         struct amdgpu_ring *ring = adev->mman.buffer_funcs_ring;
 392         struct drm_mm_node *src_mm, *dst_mm;
 393         uint64_t src_node_start, dst_node_start, src_node_size,
 394                  dst_node_size, src_page_offset, dst_page_offset;
 395         struct dma_fence *fence = NULL;
 396         int r = 0;
 397         const uint64_t GTT_MAX_BYTES = (AMDGPU_GTT_MAX_TRANSFER_SIZE *
 398                                         AMDGPU_GPU_PAGE_SIZE);
 399
 400         if (!adev->mman.buffer_funcs_enabled) {
 401                 DRM_ERROR("Trying to move memory with ring turned off.\n");
 402                 return -EINVAL;
 403         }
 404
 405         src_mm = amdgpu_find_mm_node(src->mem, &src->offset);
 406         src_node_start = amdgpu_mm_node_addr(src->bo, src_mm, src->mem) +
 407                                              src->offset;
 408         src_node_size = (src_mm->size << PAGE_SHIFT) - src->offset;
 409         src_page_offset = src_node_start & (PAGE_SIZE - 1);
 410
 411         dst_mm = amdgpu_find_mm_node(dst->mem, &dst->offset);
 412         dst_node_start = amdgpu_mm_node_addr(dst->bo, dst_mm, dst->mem) +
 413                                              dst->offset;
 414         dst_node_size = (dst_mm->size << PAGE_SHIFT) - dst->offset;
 415         dst_page_offset = dst_node_start & (PAGE_SIZE - 1);
 416
 417         mutex_lock(&adev->mman.gtt_window_lock);
 418
 419         while (size) {
 420                 unsigned long cur_size;
 421                 uint64_t from = src_node_start, to = dst_node_start;
 422                 struct dma_fence *next;
 423
 424                 /* Copy size cannot exceed GTT_MAX_BYTES. So if src or dst
 425                  * begins at an offset, then adjust the size accordingly
 426                  */
 427                 cur_size = min3(min(src_node_size, dst_node_size), size,
 428                                 GTT_MAX_BYTES);
 429                 if (cur_size + src_page_offset > GTT_MAX_BYTES ||
 430                     cur_size + dst_page_offset > GTT_MAX_BYTES)
 431                         cur_size -= max(src_page_offset, dst_page_offset);
 432
 433                 /* Map only what needs to be accessed. Map src to window 0 and
 434                  * dst to window 1
 435                  */
 436                 if (src->mem->start == AMDGPU_BO_INVALID_OFFSET) {
 437                         r = amdgpu_map_buffer(src->bo, src->mem,
 438                                         PFN_UP(cur_size + src_page_offset),
 439                                         src_node_start, 0, ring,
 440                                         &from);
 441                         if (r)
 442                                 goto error;
 443                         /* Adjust the offset because amdgpu_map_buffer returns
 444                          * start of mapped page
 445                          */
 446                         from += src_page_offset;
 447                 }
 448
 449                 if (dst->mem->start == AMDGPU_BO_INVALID_OFFSET) {
 450                         r = amdgpu_map_buffer(dst->bo, dst->mem,
 451                                         PFN_UP(cur_size + dst_page_offset),
 452                                         dst_node_start, 1, ring,
 453                                         &to);
 454                         if (r)
 455                                 goto error;
 456                         to += dst_page_offset;
 457                 }
 458
 459                 r = amdgpu_copy_buffer(ring, from, to, cur_size,
 460                                        resv, &next, false, true);
 461                 if (r)
 462                         goto error;
 463
 464                 dma_fence_put(fence);
 465                 fence = next;
 466
 467                 size -= cur_size;
 468                 if (!size)
 469                         break;
 470
 471                 src_node_size -= cur_size;
 472                 if (!src_node_size) {
 473                         src_node_start = amdgpu_mm_node_addr(src->bo, ++src_mm,
 474                                                              src->mem);
 475                         src_node_size = (src_mm->size << PAGE_SHIFT);
 476                 } else {
 477                         src_node_start += cur_size;
 478                         src_page_offset = src_node_start & (PAGE_SIZE - 1);
 479                 }
 480                 dst_node_size -= cur_size;
 481                 if (!dst_node_size) {
 482                         dst_node_start = amdgpu_mm_node_addr(dst->bo, ++dst_mm,
 483                                                              dst->mem);
 484                         dst_node_size = (dst_mm->size << PAGE_SHIFT);
 485                 } else {
 486                         dst_node_start += cur_size;
 487                         dst_page_offset = dst_node_start & (PAGE_SIZE - 1);
 488                 }
 489         }
 490 error:
 491         mutex_unlock(&adev->mman.gtt_window_lock);
 492         if (f)
 493                 *f = dma_fence_get(fence);
 494         dma_fence_put(fence);
 495         return r;
 496 }
 497
 498 /**
 499  * amdgpu_move_blit - Copy an entire buffer to another buffer
 500  *
 501  * This is a helper called by amdgpu_bo_move() and amdgpu_move_vram_ram() to
 502  * help move buffers to and from VRAM.
 503  */
 504 static int amdgpu_move_blit(struct ttm_buffer_object *bo,
 505                             bool evict, bool no_wait_gpu,
 506                             struct ttm_mem_reg *new_mem,
 507                             struct ttm_mem_reg *old_mem)
 508 {
 509         struct amdgpu_device *adev = amdgpu_ttm_adev(bo->bdev);
 510         struct amdgpu_copy_mem src, dst;
 511         struct dma_fence *fence = NULL;
 512         int r;
 513
 514         src.bo = bo;
 515         dst.bo = bo;
 516         src.mem = old_mem;
 517         dst.mem = new_mem;
 518         src.offset = 0;
 519         dst.offset = 0;
 520
 521         r = amdgpu_ttm_copy_mem_to_mem(adev, &src, &dst,
 522                                        new_mem->num_pages << PAGE_SHIFT,
 523                                        bo->resv, &fence);
 524         if (r)
 525                 goto error;
 526
 527         r = ttm_bo_pipeline_move(bo, fence, evict, new_mem);
 528         dma_fence_put(fence);
 529         return r;
 530
 531 error:
 532         if (fence)
 533                 dma_fence_wait(fence, false);
 534         dma_fence_put(fence);
 535         return r;
 536 }
 537
 538 /**
 539  * amdgpu_move_vram_ram - Copy VRAM buffer to RAM buffer
 540  *
 541  * Called by amdgpu_bo_move().
 542  */
 543 static int amdgpu_move_vram_ram(struct ttm_buffer_object *bo, bool evict,
 544                                 struct ttm_operation_ctx *ctx,
 545                                 struct ttm_mem_reg *new_mem)
 546 {
 547         struct amdgpu_device *adev;
 548         struct ttm_mem_reg *old_mem = &bo->mem;
 549         struct ttm_mem_reg tmp_mem;
 550         struct ttm_place placements;
 551         struct ttm_placement placement;
 552         int r;
 553
 554         adev = amdgpu_ttm_adev(bo->bdev);
 555
 556         /* create space/pages for new_mem in GTT space */
 557         tmp_mem = *new_mem;
 558         tmp_mem.mm_node = NULL;
 559         placement.num_placement = 1;
 560         placement.placement = &placements;
 561         placement.num_busy_placement = 1;
 562         placement.busy_placement = &placements;
 563         placements.fpfn = 0;
 564         placements.lpfn = 0;
 565         placements.flags = TTM_PL_MASK_CACHING | TTM_PL_FLAG_TT;
 566         r = ttm_bo_mem_space(bo, &placement, &tmp_mem, ctx);
 567         if (unlikely(r)) {
 568                 return r;
 569         }
 570
 571         /* set caching flags */
 572         r = ttm_tt_set_placement_caching(bo->ttm, tmp_mem.placement);
 573         if (unlikely(r)) {
 574                 goto out_cleanup;
 575         }
 576
 577         /* Bind the memory to the GTT space */
 578         r = ttm_tt_bind(bo->ttm, &tmp_mem, ctx);
 579         if (unlikely(r)) {
 580                 goto out_cleanup;
 581         }
 582
 583         /* blit VRAM to GTT */
 584         r = amdgpu_move_blit(bo, evict, ctx->no_wait_gpu, &tmp_mem, old_mem);
 585         if (unlikely(r)) {
 586                 goto out_cleanup;
 587         }
 588
 589         /* move BO (in tmp_mem) to new_mem */
 590         r = ttm_bo_move_ttm(bo, ctx, new_mem);
 591 out_cleanup:
 592         ttm_bo_mem_put(bo, &tmp_mem);
 593         return r;
 594 }
 595
 596 /**
 597  * amdgpu_move_ram_vram - Copy buffer from RAM to VRAM
 598  *
 599  * Called by amdgpu_bo_move().
 600  */
 601 static int amdgpu_move_ram_vram(struct ttm_buffer_object *bo, bool evict,
 602                                 struct ttm_operation_ctx *ctx,
 603                                 struct ttm_mem_reg *new_mem)
 604 {
 605         struct amdgpu_device *adev;
 606         struct ttm_mem_reg *old_mem = &bo->mem;
 607         struct ttm_mem_reg tmp_mem;
 608         struct ttm_placement placement;
 609         struct ttm_place placements;
 610         int r;
 611
 612         adev = amdgpu_ttm_adev(bo->bdev);
 613
 614         /* make space in GTT for old_mem buffer */
 615         tmp_mem = *new_mem;
 616         tmp_mem.mm_node = NULL;
 617         placement.num_placement = 1;
 618         placement.placement = &placements;
 619         placement.num_busy_placement = 1;
 620         placement.busy_placement = &placements;
 621         placements.fpfn = 0;
 622         placements.lpfn = 0;
 623         placements.flags = TTM_PL_MASK_CACHING | TTM_PL_FLAG_TT;
 624         r = ttm_bo_mem_space(bo, &placement, &tmp_mem, ctx);
 625         if (unlikely(r)) {
 626                 return r;
 627         }
 628
 629         /* move/bind old memory to GTT space */
 630         r = ttm_bo_move_ttm(bo, ctx, &tmp_mem);
 631         if (unlikely(r)) {
 632                 goto out_cleanup;
 633         }
 634
 635         /* copy to VRAM */
 636         r = amdgpu_move_blit(bo, evict, ctx->no_wait_gpu, new_mem, old_mem);
 637         if (unlikely(r)) {
 638                 goto out_cleanup;
 639         }
 640 out_cleanup:
 641         ttm_bo_mem_put(bo, &tmp_mem);
 642         return r;
 643 }
 644
 645 /**
 646  * amdgpu_bo_move - Move a buffer object to a new memory location
 647  *
 648  * Called by ttm_bo_handle_move_mem()
 649  */
 650 static int amdgpu_bo_move(struct ttm_buffer_object *bo, bool evict,
 651                           struct ttm_operation_ctx *ctx,
 652                           struct ttm_mem_reg *new_mem)
 653 {
 654         struct amdgpu_device *adev;
 655         struct amdgpu_bo *abo;
 656         struct ttm_mem_reg *old_mem = &bo->mem;
 657         int r;
 658
 659         /* Can't move a pinned BO */
 660         abo = ttm_to_amdgpu_bo(bo);
 661         if (WARN_ON_ONCE(abo->pin_count > 0))
 662                 return -EINVAL;
 663
 664         adev = amdgpu_ttm_adev(bo->bdev);
 665
 666         if (old_mem->mem_type == TTM_PL_SYSTEM && bo->ttm == NULL) {
 667                 amdgpu_move_null(bo, new_mem);
 668                 return 0;
 669         }
 670         if ((old_mem->mem_type == TTM_PL_TT &&
 671              new_mem->mem_type == TTM_PL_SYSTEM) ||
 672             (old_mem->mem_type == TTM_PL_SYSTEM &&
 673              new_mem->mem_type == TTM_PL_TT)) {
 674                 /* bind is enough */
 675                 amdgpu_move_null(bo, new_mem);
 676                 return 0;
 677         }
 678
 679         if (!adev->mman.buffer_funcs_enabled)
 680                 goto memcpy;
 681
 682         if (old_mem->mem_type == TTM_PL_VRAM &&
 683             new_mem->mem_type == TTM_PL_SYSTEM) {
 684                 r = amdgpu_move_vram_ram(bo, evict, ctx, new_mem);
 685         } else if (old_mem->mem_type == TTM_PL_SYSTEM &&
 686                    new_mem->mem_type == TTM_PL_VRAM) {
 687                 r = amdgpu_move_ram_vram(bo, evict, ctx, new_mem);
 688         } else {
 689                 r = amdgpu_move_blit(bo, evict, ctx->no_wait_gpu,
 690                                      new_mem, old_mem);
 691         }
 692
 693         if (r) {
 694 memcpy:
 695                 r = ttm_bo_move_memcpy(bo, ctx, new_mem);
 696                 if (r) {
 697                         return r;
 698                 }
 699         }
 700
 701         if (bo->type == ttm_bo_type_device &&
 702             new_mem->mem_type == TTM_PL_VRAM &&
 703             old_mem->mem_type != TTM_PL_VRAM) {
 704                 /* amdgpu_bo_fault_reserve_notify will re-set this if the CPU
 705                  * accesses the BO after it's moved.
 706                  */
 707                 abo->flags &= ~AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED;
 708         }
 709
 710         /* update statistics */
 711         atomic64_add((u64)bo->num_pages << PAGE_SHIFT, &adev->num_bytes_moved);
 712         return 0;
 713 }
 714
 715 /**
 716  * amdgpu_ttm_io_mem_reserve - Reserve a block of memory during a fault
 717  *
 718  * Called by ttm_mem_io_reserve() ultimately via ttm_bo_vm_fault()
 719  */
 720 static int amdgpu_ttm_io_mem_reserve(struct ttm_bo_device *bdev, struct ttm_mem_reg *mem)
 721 {
 722         struct ttm_mem_type_manager *man = &bdev->man[mem->mem_type];
 723         struct amdgpu_device *adev = amdgpu_ttm_adev(bdev);
 724         struct drm_mm_node *mm_node = mem->mm_node;
 725
 726         mem->bus.addr = NULL;
 727         mem->bus.offset = 0;
 728         mem->bus.size = mem->num_pages << PAGE_SHIFT;
 729         mem->bus.base = 0;
 730         mem->bus.is_iomem = false;
 731         if (!(man->flags & TTM_MEMTYPE_FLAG_MAPPABLE))
 732                 return -EINVAL;
 733         switch (mem->mem_type) {
 734         case TTM_PL_SYSTEM:
 735                 /* system memory */
 736                 return 0;
 737         case TTM_PL_TT:
 738                 break;
 739         case TTM_PL_VRAM:
 740                 mem->bus.offset = mem->start << PAGE_SHIFT;
 741                 /* check if it's visible */
 742                 if ((mem->bus.offset + mem->bus.size) > adev->gmc.visible_vram_size)
 743                         return -EINVAL;
 744                 /* Only physically contiguous buffers apply. In a contiguous
 745                  * buffer, size of the first mm_node would match the number of
 746                  * pages in ttm_mem_reg.
 747                  */
 748                 if (adev->mman.aper_base_kaddr &&
 749                     (mm_node->size == mem->num_pages))
 750                         mem->bus.addr = (u8 *)adev->mman.aper_base_kaddr +
 751                                         mem->bus.offset;
 752
 753                 mem->bus.base = adev->gmc.aper_base;
 754                 mem->bus.is_iomem = true;
 755                 break;
 756         default:
 757                 return -EINVAL;
 758         }
 759         return 0;
 760 }
 761
 762 static void amdgpu_ttm_io_mem_free(struct ttm_bo_device *bdev, struct ttm_mem_reg *mem)
 763 {
 764 }
 765
 766 static unsigned long amdgpu_ttm_io_mem_pfn(struct ttm_buffer_object *bo,
 767                                            unsigned long page_offset)
 768 {
 769         struct drm_mm_node *mm;
 770         unsigned long offset = (page_offset << PAGE_SHIFT);
 771
 772         mm = amdgpu_find_mm_node(&bo->mem, &offset);
 773         return (bo->mem.bus.base >> PAGE_SHIFT) + mm->start +
 774                 (offset >> PAGE_SHIFT);
 775 }
 776
 777 /*
 778  * TTM backend functions.
 779  */
 780 struct amdgpu_ttm_gup_task_list {
 781         struct list_head        list;
 782         struct task_struct      *task;
 783 };
 784
 785 struct amdgpu_ttm_tt {
 786         struct ttm_dma_tt       ttm;
 787         u64                     offset;
 788         uint64_t                userptr;
 789         struct task_struct      *usertask;
 790         uint32_t                userflags;
 791         spinlock_t              guptasklock;
 792         struct list_head        guptasks;
 793         atomic_t                mmu_invalidations;
 794         uint32_t                last_set_pages;
 795 };
 796
 797 /**
 798  * amdgpu_ttm_tt_get_user_pages - Pin pages of memory pointed to by a USERPTR
 799  * pointer to memory
 800  *
 801  * Called by amdgpu_gem_userptr_ioctl() and amdgpu_cs_parser_bos().
 802  * This provides a wrapper around the get_user_pages() call to provide
 803  * device accessible pages that back user memory.
 804  */
 805 int amdgpu_ttm_tt_get_user_pages(struct ttm_tt *ttm, struct page **pages)
 806 {
 807         struct amdgpu_ttm_tt *gtt = (void *)ttm;
 808         struct mm_struct *mm = gtt->usertask->mm;
 809         unsigned int flags = 0;
 810         unsigned pinned = 0;
 811         int r;
 812
 813         if (!mm) /* Happens during process shutdown */
 814                 return -ESRCH;
 815
 816         if (!(gtt->userflags & AMDGPU_GEM_USERPTR_READONLY))
 817                 flags |= FOLL_WRITE;
 818
 819         down_read(&mm->mmap_sem);
 820
 821         if (gtt->userflags & AMDGPU_GEM_USERPTR_ANONONLY) {
 822                 /*
 823                  * check that we only use anonymous memory to prevent problems
 824                  * with writeback
 825                  */
 826                 unsigned long end = gtt->userptr + ttm->num_pages * PAGE_SIZE;
 827                 struct vm_area_struct *vma;
 828
 829                 vma = find_vma(mm, gtt->userptr);
 830                 if (!vma || vma->vm_file || vma->vm_end < end) {
 831                         up_read(&mm->mmap_sem);
 832                         return -EPERM;
 833                 }
 834         }
 835
 836         /* loop enough times using contiguous pages of memory */
 837         do {
 838                 unsigned num_pages = ttm->num_pages - pinned;
 839                 uint64_t userptr = gtt->userptr + pinned * PAGE_SIZE;
 840                 struct page **p = pages + pinned;
 841                 struct amdgpu_ttm_gup_task_list guptask;
 842
 843                 guptask.task = current;
 844                 spin_lock(&gtt->guptasklock);
 845                 list_add(&guptask.list, &gtt->guptasks);
 846                 spin_unlock(&gtt->guptasklock);
 847
 848                 if (mm == current->mm)
 849                         r = get_user_pages(userptr, num_pages, flags, p, NULL);
 850                 else
 851                         r = get_user_pages_remote(gtt->usertask,
 852                                         mm, userptr, num_pages,
 853                                         flags, p, NULL, NULL);
 854
 855                 spin_lock(&gtt->guptasklock);
 856                 list_del(&guptask.list);
 857                 spin_unlock(&gtt->guptasklock);
 858
 859                 if (r < 0)
 860                         goto release_pages;
 861
 862                 pinned += r;
 863
 864         } while (pinned < ttm->num_pages);
 865
 866         up_read(&mm->mmap_sem);
 867         return 0;
 868
 869 release_pages:
 870         release_pages(pages, pinned);
 871         up_read(&mm->mmap_sem);
 872         return r;
 873 }
 874
 875 /**
 876  * amdgpu_ttm_tt_set_user_pages - Copy pages in, putting old pages as necessary.
 877  *
 878  * Called by amdgpu_cs_list_validate(). This creates the page list
 879  * that backs user memory and will ultimately be mapped into the device
 880  * address space.
 881  */
 882 void amdgpu_ttm_tt_set_user_pages(struct ttm_tt *ttm, struct page **pages)
 883 {
 884         struct amdgpu_ttm_tt *gtt = (void *)ttm;
 885         unsigned i;
 886
 887         gtt->last_set_pages = atomic_read(&gtt->mmu_invalidations);
 888         for (i = 0; i < ttm->num_pages; ++i) {
 889                 if (ttm->pages[i])
 890                         put_page(ttm->pages[i]);
 891
 892                 ttm->pages[i] = pages ? pages[i] : NULL;
 893         }
 894 }
 895
 896 /**
 897  * amdgpu_ttm_tt_mark_user_page - Mark pages as dirty
 898  *
 899  * Called while unpinning userptr pages
 900  */
 901 void amdgpu_ttm_tt_mark_user_pages(struct ttm_tt *ttm)
 902 {
 903         struct amdgpu_ttm_tt *gtt = (void *)ttm;
 904         unsigned i;
 905
 906         for (i = 0; i < ttm->num_pages; ++i) {
 907                 struct page *page = ttm->pages[i];
 908
 909                 if (!page)
 910                         continue;
 911
 912                 if (!(gtt->userflags & AMDGPU_GEM_USERPTR_READONLY))
 913                         set_page_dirty(page);
 914
 915                 mark_page_accessed(page);
 916         }
 917 }
 918
 919 /**
 920  * amdgpu_ttm_tt_pin_userptr -  prepare the sg table with the user pages
 921  *
 922  * Called by amdgpu_ttm_backend_bind()
 923  **/
 924 static int amdgpu_ttm_tt_pin_userptr(struct ttm_tt *ttm)
 925 {
 926         struct amdgpu_device *adev = amdgpu_ttm_adev(ttm->bdev);
 927         struct amdgpu_ttm_tt *gtt = (void *)ttm;
 928         unsigned nents;
 929         int r;
 930
 931         int write = !(gtt->userflags & AMDGPU_GEM_USERPTR_READONLY);
 932         enum dma_data_direction direction = write ?
 933                 DMA_BIDIRECTIONAL : DMA_TO_DEVICE;
 934
 935         /* Allocate an SG array and squash pages into it */
 936         r = sg_alloc_table_from_pages(ttm->sg, ttm->pages, ttm->num_pages, 0,
 937                                       ttm->num_pages << PAGE_SHIFT,
 938                                       GFP_KERNEL);
 939         if (r)
 940                 goto release_sg;
 941
 942         /* Map SG to device */
 943         r = -ENOMEM;
 944         nents = dma_map_sg(adev->dev, ttm->sg->sgl, ttm->sg->nents, direction);
 945         if (nents != ttm->sg->nents)
 946                 goto release_sg;
 947
 948         /* convert SG to linear array of pages and dma addresses */
 949         drm_prime_sg_to_page_addr_arrays(ttm->sg, ttm->pages,
 950                                          gtt->ttm.dma_address, ttm->num_pages);
 951
 952         return 0;
 953
 954 release_sg:
 955         kfree(ttm->sg);
 956         return r;
 957 }
 958
 959 /**
 960  * amdgpu_ttm_tt_unpin_userptr - Unpin and unmap userptr pages
 961  */
 962 static void amdgpu_ttm_tt_unpin_userptr(struct ttm_tt *ttm)
 963 {
 964         struct amdgpu_device *adev = amdgpu_ttm_adev(ttm->bdev);
 965         struct amdgpu_ttm_tt *gtt = (void *)ttm;
 966
 967         int write = !(gtt->userflags & AMDGPU_GEM_USERPTR_READONLY);
 968         enum dma_data_direction direction = write ?
 969                 DMA_BIDIRECTIONAL : DMA_TO_DEVICE;
 970
 971         /* double check that we don't free the table twice */
 972         if (!ttm->sg->sgl)
 973                 return;
 974
 975         /* unmap the pages mapped to the device */
 976         dma_unmap_sg(adev->dev, ttm->sg->sgl, ttm->sg->nents, direction);
 977
 978         /* mark the pages as dirty */
 979         amdgpu_ttm_tt_mark_user_pages(ttm);
 980
 981         sg_free_table(ttm->sg);
 982 }
 983
 984 int amdgpu_ttm_gart_bind(struct amdgpu_device *adev,
 985                                 struct ttm_buffer_object *tbo,
 986                                 uint64_t flags)
 987 {
 988         struct amdgpu_bo *abo = ttm_to_amdgpu_bo(tbo);
 989         struct ttm_tt *ttm = tbo->ttm;
 990         struct amdgpu_ttm_tt *gtt = (void *)ttm;
 991         int r;
 992
 993         if (abo->flags & AMDGPU_GEM_CREATE_MQD_GFX9) {
 994                 uint64_t page_idx = 1;
 995
 996                 r = amdgpu_gart_bind(adev, gtt->offset, page_idx,
 997                                 ttm->pages, gtt->ttm.dma_address, flags);
 998                 if (r)
 999                         goto gart_bind_fail;
1000
1001                 /* Patch mtype of the second part BO */
1002                 flags &=  ~AMDGPU_PTE_MTYPE_MASK;
1003                 flags |= AMDGPU_PTE_MTYPE(AMDGPU_MTYPE_NC);
1004
1005                 r = amdgpu_gart_bind(adev,
1006                                 gtt->offset + (page_idx << PAGE_SHIFT),
1007                                 ttm->num_pages - page_idx,
1008                                 &ttm->pages[page_idx],
1009                                 &(gtt->ttm.dma_address[page_idx]), flags);
1010         } else {
1011                 r = amdgpu_gart_bind(adev, gtt->offset, ttm->num_pages,
1012                                      ttm->pages, gtt->ttm.dma_address, flags);
1013         }
1014
1015 gart_bind_fail:
1016         if (r)
1017                 DRM_ERROR("failed to bind %lu pages at 0x%08llX\n",
1018                           ttm->num_pages, gtt->offset);
1019
1020         return r;
1021 }
1022
1023 /**
1024  * amdgpu_ttm_backend_bind - Bind GTT memory
1025  *
1026  * Called by ttm_tt_bind() on behalf of ttm_bo_handle_move_mem().
1027  * This handles binding GTT memory to the device address space.
1028  */
1029 static int amdgpu_ttm_backend_bind(struct ttm_tt *ttm,
1030                                    struct ttm_mem_reg *bo_mem)
1031 {
1032         struct amdgpu_device *adev = amdgpu_ttm_adev(ttm->bdev);
1033         struct amdgpu_ttm_tt *gtt = (void*)ttm;
1034         uint64_t flags;
1035         int r = 0;
1036
1037         if (gtt->userptr) {
1038                 r = amdgpu_ttm_tt_pin_userptr(ttm);
1039                 if (r) {
1040                         DRM_ERROR("failed to pin userptr\n");
1041                         return r;
1042                 }
1043         }
1044         if (!ttm->num_pages) {
1045                 WARN(1, "nothing to bind %lu pages for mreg %p back %p!\n",
1046                      ttm->num_pages, bo_mem, ttm);
1047         }
1048
1049         if (bo_mem->mem_type == AMDGPU_PL_GDS ||
1050             bo_mem->mem_type == AMDGPU_PL_GWS ||
1051             bo_mem->mem_type == AMDGPU_PL_OA)
1052                 return -EINVAL;
1053
1054         if (!amdgpu_gtt_mgr_has_gart_addr(bo_mem)) {
1055                 gtt->offset = AMDGPU_BO_INVALID_OFFSET;
1056                 return 0;
1057         }
1058
1059         /* compute PTE flags relevant to this BO memory */
1060         flags = amdgpu_ttm_tt_pte_flags(adev, ttm, bo_mem);
1061
1062         /* bind pages into GART page tables */
1063         gtt->offset = ((u64)bo_mem->start << PAGE_SHIFT) - adev->gmc.gart_start;
1064         r = amdgpu_gart_bind(adev, gtt->offset, ttm->num_pages,
1065                 ttm->pages, gtt->ttm.dma_address, flags);
1066
1067         if (r)
1068                 DRM_ERROR("failed to bind %lu pages at 0x%08llX\n",
1069                           ttm->num_pages, gtt->offset);
1070         return r;
1071 }
1072
1073 /**
1074  * amdgpu_ttm_alloc_gart - Allocate GART memory for buffer object
1075  */
1076 int amdgpu_ttm_alloc_gart(struct ttm_buffer_object *bo)
1077 {
1078         struct amdgpu_device *adev = amdgpu_ttm_adev(bo->bdev);
1079         struct ttm_operation_ctx ctx = { false, false };
1080         struct amdgpu_ttm_tt *gtt = (void*)bo->ttm;
1081         struct ttm_mem_reg tmp;
1082         struct ttm_placement placement;
1083         struct ttm_place placements;
1084         uint64_t flags;
1085         int r;
1086
1087         if (bo->mem.start != AMDGPU_BO_INVALID_OFFSET)
1088                 return 0;
1089
1090         /* allocate GART space */
1091         tmp = bo->mem;
1092         tmp.mm_node = NULL;
1093         placement.num_placement = 1;
1094         placement.placement = &placements;
1095         placement.num_busy_placement = 1;
1096         placement.busy_placement = &placements;
1097         placements.fpfn = 0;
1098         placements.lpfn = adev->gmc.gart_size >> PAGE_SHIFT;
1099         placements.flags = (bo->mem.placement & ~TTM_PL_MASK_MEM) |
1100                 TTM_PL_FLAG_TT;
1101
1102         r = ttm_bo_mem_space(bo, &placement, &tmp, &ctx);
1103         if (unlikely(r))
1104                 return r;
1105
1106         /* compute PTE flags for this buffer object */
1107         flags = amdgpu_ttm_tt_pte_flags(adev, bo->ttm, &tmp);
1108
1109         /* Bind pages */
1110         gtt->offset = ((u64)tmp.start << PAGE_SHIFT) - adev->gmc.gart_start;
1111         r = amdgpu_ttm_gart_bind(adev, bo, flags);
1112         if (unlikely(r)) {
1113                 ttm_bo_mem_put(bo, &tmp);
1114                 return r;
1115         }
1116
1117         ttm_bo_mem_put(bo, &bo->mem);
1118         bo->mem = tmp;
1119         bo->offset = (bo->mem.start << PAGE_SHIFT) +
1120                 bo->bdev->man[bo->mem.mem_type].gpu_offset;
1121
1122         return 0;
1123 }
1124
1125 /**
1126  * amdgpu_ttm_recover_gart - Rebind GTT pages
1127  *
1128  * Called by amdgpu_gtt_mgr_recover() from amdgpu_device_reset() to
1129  * rebind GTT pages during a GPU reset.
1130  */
1131 int amdgpu_ttm_recover_gart(struct ttm_buffer_object *tbo)
1132 {
1133         struct amdgpu_device *adev = amdgpu_ttm_adev(tbo->bdev);
1134         uint64_t flags;
1135         int r;
1136
1137         if (!tbo->ttm)
1138                 return 0;
1139
1140         flags = amdgpu_ttm_tt_pte_flags(adev, tbo->ttm, &tbo->mem);
1141         r = amdgpu_ttm_gart_bind(adev, tbo, flags);
1142
1143         return r;
1144 }
1145
1146 /**
1147  * amdgpu_ttm_backend_unbind - Unbind GTT mapped pages
1148  *
1149  * Called by ttm_tt_unbind() on behalf of ttm_bo_move_ttm() and
1150  * ttm_tt_destroy().
1151  */
1152 static int amdgpu_ttm_backend_unbind(struct ttm_tt *ttm)
1153 {
1154         struct amdgpu_device *adev = amdgpu_ttm_adev(ttm->bdev);
1155         struct amdgpu_ttm_tt *gtt = (void *)ttm;
1156         int r;
1157
1158         /* if the pages have userptr pinning then clear that first */
1159         if (gtt->userptr)
1160                 amdgpu_ttm_tt_unpin_userptr(ttm);
1161
1162         if (gtt->offset == AMDGPU_BO_INVALID_OFFSET)
1163                 return 0;
1164
1165         /* unbind shouldn't be done for GDS/GWS/OA in ttm_bo_clean_mm */
1166         r = amdgpu_gart_unbind(adev, gtt->offset, ttm->num_pages);
1167         if (r)
1168                 DRM_ERROR("failed to unbind %lu pages at 0x%08llX\n",
1169                           gtt->ttm.ttm.num_pages, gtt->offset);
1170         return r;
1171 }
1172
1173 static void amdgpu_ttm_backend_destroy(struct ttm_tt *ttm)
1174 {
1175         struct amdgpu_ttm_tt *gtt = (void *)ttm;
1176
1177         if (gtt->usertask)
1178                 put_task_struct(gtt->usertask);
1179
1180         ttm_dma_tt_fini(&gtt->ttm);
1181         kfree(gtt);
1182 }
1183
1184 static struct ttm_backend_func amdgpu_backend_func = {
1185         .bind = &amdgpu_ttm_backend_bind,
1186         .unbind = &amdgpu_ttm_backend_unbind,
1187         .destroy = &amdgpu_ttm_backend_destroy,
1188 };
1189
1190 /**
1191  * amdgpu_ttm_tt_create - Create a ttm_tt object for a given BO
1192  *
1193  * @bo: The buffer object to create a GTT ttm_tt object around
1194  *
1195  * Called by ttm_tt_create().
1196  */
1197 static struct ttm_tt *amdgpu_ttm_tt_create(struct ttm_buffer_object *bo,
1198                                            uint32_t page_flags)
1199 {
1200         struct amdgpu_device *adev;
1201         struct amdgpu_ttm_tt *gtt;
1202
1203         adev = amdgpu_ttm_adev(bo->bdev);
1204
1205         gtt = kzalloc(sizeof(struct amdgpu_ttm_tt), GFP_KERNEL);
1206         if (gtt == NULL) {
1207                 return NULL;
1208         }
1209         gtt->ttm.ttm.func = &amdgpu_backend_func;
1210
1211         /* allocate space for the uninitialized page entries */
1212         if (ttm_sg_tt_init(&gtt->ttm, bo, page_flags)) {
1213                 kfree(gtt);
1214                 return NULL;
1215         }
1216         return &gtt->ttm.ttm;
1217 }
1218
1219 /**
1220  * amdgpu_ttm_tt_populate - Map GTT pages visible to the device
1221  *
1222  * Map the pages of a ttm_tt object to an address space visible
1223  * to the underlying device.
1224  */
1225 static int amdgpu_ttm_tt_populate(struct ttm_tt *ttm,
1226                         struct ttm_operation_ctx *ctx)
1227 {
1228         struct amdgpu_device *adev = amdgpu_ttm_adev(ttm->bdev);
1229         struct amdgpu_ttm_tt *gtt = (void *)ttm;
1230         bool slave = !!(ttm->page_flags & TTM_PAGE_FLAG_SG);
1231
1232         /* user pages are bound by amdgpu_ttm_tt_pin_userptr() */
1233         if (gtt && gtt->userptr) {
1234                 ttm->sg = kzalloc(sizeof(struct sg_table), GFP_KERNEL);
1235                 if (!ttm->sg)
1236                         return -ENOMEM;
1237
1238                 ttm->page_flags |= TTM_PAGE_FLAG_SG;
1239                 ttm->state = tt_unbound;
1240                 return 0;
1241         }
1242
1243         if (slave && ttm->sg) {
1244                 drm_prime_sg_to_page_addr_arrays(ttm->sg, ttm->pages,
1245                                                  gtt->ttm.dma_address,
1246                                                  ttm->num_pages);
1247                 ttm->state = tt_unbound;
1248                 return 0;
1249         }
1250
1251 #ifdef CONFIG_SWIOTLB
1252         if (adev->need_swiotlb && swiotlb_nr_tbl()) {
1253                 return ttm_dma_populate(&gtt->ttm, adev->dev, ctx);
1254         }
1255 #endif
1256
1257         /* fall back to generic helper to populate the page array
1258          * and map them to the device */
1259         return ttm_populate_and_map_pages(adev->dev, &gtt->ttm, ctx);
1260 }
1261
1262 /**
1263  * amdgpu_ttm_tt_unpopulate - unmap GTT pages and unpopulate page arrays
1264  *
1265  * Unmaps pages of a ttm_tt object from the device address space and
1266  * unpopulates the page array backing it.
1267  */
1268 static void amdgpu_ttm_tt_unpopulate(struct ttm_tt *ttm)
1269 {
1270         struct amdgpu_device *adev;
1271         struct amdgpu_ttm_tt *gtt = (void *)ttm;
1272         bool slave = !!(ttm->page_flags & TTM_PAGE_FLAG_SG);
1273
1274         if (gtt && gtt->userptr) {
1275                 amdgpu_ttm_tt_set_user_pages(ttm, NULL);
1276                 kfree(ttm->sg);
1277                 ttm->page_flags &= ~TTM_PAGE_FLAG_SG;
1278                 return;
1279         }
1280
1281         if (slave)
1282                 return;
1283
1284         adev = amdgpu_ttm_adev(ttm->bdev);
1285
1286 #ifdef CONFIG_SWIOTLB
1287         if (adev->need_swiotlb && swiotlb_nr_tbl()) {
1288                 ttm_dma_unpopulate(&gtt->ttm, adev->dev);
1289                 return;
1290         }
1291 #endif
1292
1293         /* fall back to generic helper to unmap and unpopulate array */
1294         ttm_unmap_and_unpopulate_pages(adev->dev, &gtt->ttm);
1295 }
1296
1297 /**
1298  * amdgpu_ttm_tt_set_userptr - Initialize userptr GTT ttm_tt for the current
1299  * task
1300  *
1301  * @ttm: The ttm_tt object to bind this userptr object to
1302  * @addr:  The address in the current tasks VM space to use
1303  * @flags: Requirements of userptr object.
1304  *
1305  * Called by amdgpu_gem_userptr_ioctl() to bind userptr pages
1306  * to current task
1307  */
1308 int amdgpu_ttm_tt_set_userptr(struct ttm_tt *ttm, uint64_t addr,
1309                               uint32_t flags)
1310 {
1311         struct amdgpu_ttm_tt *gtt = (void *)ttm;
1312
1313         if (gtt == NULL)
1314                 return -EINVAL;
1315
1316         gtt->userptr = addr;
1317         gtt->userflags = flags;
1318
1319         if (gtt->usertask)
1320                 put_task_struct(gtt->usertask);
1321         gtt->usertask = current->group_leader;
1322         get_task_struct(gtt->usertask);
1323
1324         spin_lock_init(&gtt->guptasklock);
1325         INIT_LIST_HEAD(&gtt->guptasks);
1326         atomic_set(&gtt->mmu_invalidations, 0);
1327         gtt->last_set_pages = 0;
1328
1329         return 0;
1330 }
1331
1332 /**
1333  * amdgpu_ttm_tt_get_usermm - Return memory manager for ttm_tt object
1334  */
1335 struct mm_struct *amdgpu_ttm_tt_get_usermm(struct ttm_tt *ttm)
1336 {
1337         struct amdgpu_ttm_tt *gtt = (void *)ttm;
1338
1339         if (gtt == NULL)
1340                 return NULL;
1341
1342         if (gtt->usertask == NULL)
1343                 return NULL;
1344
1345         return gtt->usertask->mm;
1346 }
1347
1348 /**
1349  * amdgpu_ttm_tt_affect_userptr - Determine if a ttm_tt object lays inside an
1350  * address range for the current task.
1351  *
1352  */
1353 bool amdgpu_ttm_tt_affect_userptr(struct ttm_tt *ttm, unsigned long start,
1354                                   unsigned long end)
1355 {
1356         struct amdgpu_ttm_tt *gtt = (void *)ttm;
1357         struct amdgpu_ttm_gup_task_list *entry;
1358         unsigned long size;
1359
1360         if (gtt == NULL || !gtt->userptr)
1361                 return false;
1362
1363         /* Return false if no part of the ttm_tt object lies within
1364          * the range
1365          */
1366         size = (unsigned long)gtt->ttm.ttm.num_pages * PAGE_SIZE;
1367         if (gtt->userptr > end || gtt->userptr + size <= start)
1368                 return false;
1369
1370         /* Search the lists of tasks that hold this mapping and see
1371          * if current is one of them.  If it is return false.
1372          */
1373         spin_lock(&gtt->guptasklock);
1374         list_for_each_entry(entry, &gtt->guptasks, list) {
1375                 if (entry->task == current) {
1376                         spin_unlock(&gtt->guptasklock);
1377                         return false;
1378                 }
1379         }
1380         spin_unlock(&gtt->guptasklock);
1381
1382         atomic_inc(&gtt->mmu_invalidations);
1383
1384         return true;
1385 }
1386
1387 /**
1388  * amdgpu_ttm_tt_userptr_invalidated - Has the ttm_tt object been invalidated?
1389  */
1390 bool amdgpu_ttm_tt_userptr_invalidated(struct ttm_tt *ttm,
1391                                        int *last_invalidated)
1392 {
1393         struct amdgpu_ttm_tt *gtt = (void *)ttm;
1394         int prev_invalidated = *last_invalidated;
1395
1396         *last_invalidated = atomic_read(&gtt->mmu_invalidations);
1397         return prev_invalidated != *last_invalidated;
1398 }
1399
1400 /**
1401  * amdgpu_ttm_tt_userptr_needs_pages - Have the pages backing this ttm_tt object
1402  * been invalidated since the last time they've been set?
1403  */
1404 bool amdgpu_ttm_tt_userptr_needs_pages(struct ttm_tt *ttm)
1405 {
1406         struct amdgpu_ttm_tt *gtt = (void *)ttm;
1407
1408         if (gtt == NULL || !gtt->userptr)
1409                 return false;
1410
1411         return atomic_read(&gtt->mmu_invalidations) != gtt->last_set_pages;
1412 }
1413
1414 /**
1415  * amdgpu_ttm_tt_is_readonly - Is the ttm_tt object read only?
1416  */
1417 bool amdgpu_ttm_tt_is_readonly(struct ttm_tt *ttm)
1418 {
1419         struct amdgpu_ttm_tt *gtt = (void *)ttm;
1420
1421         if (gtt == NULL)
1422                 return false;
1423
1424         return !!(gtt->userflags & AMDGPU_GEM_USERPTR_READONLY);
1425 }
1426
1427 /**
1428  * amdgpu_ttm_tt_pde_flags - Compute PDE flags for ttm_tt object
1429  *
1430  * @ttm: The ttm_tt object to compute the flags for
1431  * @mem: The memory registry backing this ttm_tt object
1432  *
1433  * Figure out the flags to use for a VM PDE (Page Directory Entry).
1434  */
1435 uint64_t amdgpu_ttm_tt_pde_flags(struct ttm_tt *ttm, struct ttm_mem_reg *mem)
1436 {
1437         uint64_t flags = 0;
1438
1439         if (mem && mem->mem_type != TTM_PL_SYSTEM)
1440                 flags |= AMDGPU_PTE_VALID;
1441
1442         if (mem && mem->mem_type == TTM_PL_TT) {
1443                 flags |= AMDGPU_PTE_SYSTEM;
1444
1445                 if (ttm->caching_state == tt_cached)
1446                         flags |= AMDGPU_PTE_SNOOPED;
1447         }
1448
1449         return flags;
1450 }
1451
1452 /**
1453  * amdgpu_ttm_tt_pte_flags - Compute PTE flags for ttm_tt object
1454  *
1455  * @ttm: The ttm_tt object to compute the flags for
1456  * @mem: The memory registry backing this ttm_tt object
1457
1458  * Figure out the flags to use for a VM PTE (Page Table Entry).
1459  */
1460 uint64_t amdgpu_ttm_tt_pte_flags(struct amdgpu_device *adev, struct ttm_tt *ttm,
1461                                  struct ttm_mem_reg *mem)
1462 {
1463         uint64_t flags = amdgpu_ttm_tt_pde_flags(ttm, mem);
1464
1465         flags |= adev->gart.gart_pte_flags;
1466         flags |= AMDGPU_PTE_READABLE;
1467
1468         if (!amdgpu_ttm_tt_is_readonly(ttm))
1469                 flags |= AMDGPU_PTE_WRITEABLE;
1470
1471         return flags;
1472 }
1473
1474 /**
1475  * amdgpu_ttm_bo_eviction_valuable - Check to see if we can evict a buffer
1476  * object.
1477  *
1478  * Return true if eviction is sensible. Called by ttm_mem_evict_first() on
1479  * behalf of ttm_bo_mem_force_space() which tries to evict buffer objects until
1480  * it can find space for a new object and by ttm_bo_force_list_clean() which is
1481  * used to clean out a memory space.
1482  */
1483 static bool amdgpu_ttm_bo_eviction_valuable(struct ttm_buffer_object *bo,
1484                                             const struct ttm_place *place)
1485 {
1486         unsigned long num_pages = bo->mem.num_pages;
1487         struct drm_mm_node *node = bo->mem.mm_node;
1488         struct reservation_object_list *flist;
1489         struct dma_fence *f;
1490         int i;
1491
1492         /* If bo is a KFD BO, check if the bo belongs to the current process.
1493          * If true, then return false as any KFD process needs all its BOs to
1494          * be resident to run successfully
1495          */
1496         flist = reservation_object_get_list(bo->resv);
1497         if (flist) {
1498                 for (i = 0; i < flist->shared_count; ++i) {
1499                         f = rcu_dereference_protected(flist->shared[i],
1500                                 reservation_object_held(bo->resv));
1501                         if (amdkfd_fence_check_mm(f, current->mm))
1502                                 return false;
1503                 }
1504         }
1505
1506         switch (bo->mem.mem_type) {
1507         case TTM_PL_TT:
1508                 return true;
1509
1510         case TTM_PL_VRAM:
1511                 /* Check each drm MM node individually */
1512                 while (num_pages) {
1513                         if (place->fpfn < (node->start + node->size) &&
1514                             !(place->lpfn && place->lpfn <= node->start))
1515                                 return true;
1516
1517                         num_pages -= node->size;
1518                         ++node;
1519                 }
1520                 return false;
1521
1522         default:
1523                 break;
1524         }
1525
1526         return ttm_bo_eviction_valuable(bo, place);
1527 }
1528
1529 /**
1530  * amdgpu_ttm_access_memory - Read or Write memory that backs a buffer object.
1531  *
1532  * @bo:  The buffer object to read/write
1533  * @offset:  Offset into buffer object
1534  * @buf:  Secondary buffer to write/read from
1535  * @len: Length in bytes of access
1536  * @write:  true if writing
1537  *
1538  * This is used to access VRAM that backs a buffer object via MMIO
1539  * access for debugging purposes.
1540  */
1541 static int amdgpu_ttm_access_memory(struct ttm_buffer_object *bo,
1542                                     unsigned long offset,
1543                                     void *buf, int len, int write)
1544 {
1545         struct amdgpu_bo *abo = ttm_to_amdgpu_bo(bo);
1546         struct amdgpu_device *adev = amdgpu_ttm_adev(abo->tbo.bdev);
1547         struct drm_mm_node *nodes;
1548         uint32_t value = 0;
1549         int ret = 0;
1550         uint64_t pos;
1551         unsigned long flags;
1552
1553         if (bo->mem.mem_type != TTM_PL_VRAM)
1554                 return -EIO;
1555
1556         nodes = amdgpu_find_mm_node(&abo->tbo.mem, &offset);
1557         pos = (nodes->start << PAGE_SHIFT) + offset;
1558
1559         while (len && pos < adev->gmc.mc_vram_size) {
1560                 uint64_t aligned_pos = pos & ~(uint64_t)3;
1561                 uint32_t bytes = 4 - (pos & 3);
1562                 uint32_t shift = (pos & 3) * 8;
1563                 uint32_t mask = 0xffffffff << shift;
1564
1565                 if (len < bytes) {
1566                         mask &= 0xffffffff >> (bytes - len) * 8;
1567                         bytes = len;
1568                 }
1569
1570                 spin_lock_irqsave(&adev->mmio_idx_lock, flags);
1571                 WREG32_NO_KIQ(mmMM_INDEX, ((uint32_t)aligned_pos) | 0x80000000);
1572                 WREG32_NO_KIQ(mmMM_INDEX_HI, aligned_pos >> 31);
1573                 if (!write || mask != 0xffffffff)
1574                         value = RREG32_NO_KIQ(mmMM_DATA);
1575                 if (write) {
1576                         value &= ~mask;
1577                         value |= (*(uint32_t *)buf << shift) & mask;
1578                         WREG32_NO_KIQ(mmMM_DATA, value);
1579                 }
1580                 spin_unlock_irqrestore(&adev->mmio_idx_lock, flags);
1581                 if (!write) {
1582                         value = (value & mask) >> shift;
1583                         memcpy(buf, &value, bytes);
1584                 }
1585
1586                 ret += bytes;
1587                 buf = (uint8_t *)buf + bytes;
1588                 pos += bytes;
1589                 len -= bytes;
1590                 if (pos >= (nodes->start + nodes->size) << PAGE_SHIFT) {
1591                         ++nodes;
1592                         pos = (nodes->start << PAGE_SHIFT);
1593                 }
1594         }
1595
1596         return ret;
1597 }
1598
1599 static struct ttm_bo_driver amdgpu_bo_driver = {
1600         .ttm_tt_create = &amdgpu_ttm_tt_create,
1601         .ttm_tt_populate = &amdgpu_ttm_tt_populate,
1602         .ttm_tt_unpopulate = &amdgpu_ttm_tt_unpopulate,
1603         .invalidate_caches = &amdgpu_invalidate_caches,
1604         .init_mem_type = &amdgpu_init_mem_type,
1605         .eviction_valuable = amdgpu_ttm_bo_eviction_valuable,
1606         .evict_flags = &amdgpu_evict_flags,
1607         .move = &amdgpu_bo_move,
1608         .verify_access = &amdgpu_verify_access,
1609         .move_notify = &amdgpu_bo_move_notify,
1610         .fault_reserve_notify = &amdgpu_bo_fault_reserve_notify,
1611         .io_mem_reserve = &amdgpu_ttm_io_mem_reserve,
1612         .io_mem_free = &amdgpu_ttm_io_mem_free,
1613         .io_mem_pfn = amdgpu_ttm_io_mem_pfn,
1614         .access_memory = &amdgpu_ttm_access_memory
1615 };
1616
1617 /*
1618  * Firmware Reservation functions
1619  */
1620 /**
1621  * amdgpu_ttm_fw_reserve_vram_fini - free fw reserved vram
1622  *
1623  * @adev: amdgpu_device pointer
1624  *
1625  * free fw reserved vram if it has been reserved.
1626  */
1627 static void amdgpu_ttm_fw_reserve_vram_fini(struct amdgpu_device *adev)
1628 {
1629         amdgpu_bo_free_kernel(&adev->fw_vram_usage.reserved_bo,
1630                 NULL, &adev->fw_vram_usage.va);
1631 }
1632
1633 /**
1634  * amdgpu_ttm_fw_reserve_vram_init - create bo vram reservation from fw
1635  *
1636  * @adev: amdgpu_device pointer
1637  *
1638  * create bo vram reservation from fw.
1639  */
1640 static int amdgpu_ttm_fw_reserve_vram_init(struct amdgpu_device *adev)
1641 {
1642         struct ttm_operation_ctx ctx = { false, false };
1643         struct amdgpu_bo_param bp;
1644         int r = 0;
1645         int i;
1646         u64 vram_size = adev->gmc.visible_vram_size;
1647         u64 offset = adev->fw_vram_usage.start_offset;
1648         u64 size = adev->fw_vram_usage.size;
1649         struct amdgpu_bo *bo;
1650
1651         memset(&bp, 0, sizeof(bp));
1652         bp.size = adev->fw_vram_usage.size;
1653         bp.byte_align = PAGE_SIZE;
1654         bp.domain = AMDGPU_GEM_DOMAIN_VRAM;
1655         bp.flags = AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED |
1656                 AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS;
1657         bp.type = ttm_bo_type_kernel;
1658         bp.resv = NULL;
1659         adev->fw_vram_usage.va = NULL;
1660         adev->fw_vram_usage.reserved_bo = NULL;
1661
1662         if (adev->fw_vram_usage.size > 0 &&
1663                 adev->fw_vram_usage.size <= vram_size) {
1664
1665                 r = amdgpu_bo_create(adev, &bp,
1666                                      &adev->fw_vram_usage.reserved_bo);
1667                 if (r)
1668                         goto error_create;
1669
1670                 r = amdgpu_bo_reserve(adev->fw_vram_usage.reserved_bo, false);
1671                 if (r)
1672                         goto error_reserve;
1673
1674                 /* remove the original mem node and create a new one at the
1675                  * request position
1676                  */
1677                 bo = adev->fw_vram_usage.reserved_bo;
1678                 offset = ALIGN(offset, PAGE_SIZE);
1679                 for (i = 0; i < bo->placement.num_placement; ++i) {
1680                         bo->placements[i].fpfn = offset >> PAGE_SHIFT;
1681                         bo->placements[i].lpfn = (offset + size) >> PAGE_SHIFT;
1682                 }
1683
1684                 ttm_bo_mem_put(&bo->tbo, &bo->tbo.mem);
1685                 r = ttm_bo_mem_space(&bo->tbo, &bo->placement,
1686                                      &bo->tbo.mem, &ctx);
1687                 if (r)
1688                         goto error_pin;
1689
1690                 r = amdgpu_bo_pin_restricted(adev->fw_vram_usage.reserved_bo,
1691                         AMDGPU_GEM_DOMAIN_VRAM,
1692                         adev->fw_vram_usage.start_offset,
1693                         (adev->fw_vram_usage.start_offset +
1694                         adev->fw_vram_usage.size));
1695                 if (r)
1696                         goto error_pin;
1697                 r = amdgpu_bo_kmap(adev->fw_vram_usage.reserved_bo,
1698                         &adev->fw_vram_usage.va);
1699                 if (r)
1700                         goto error_kmap;
1701
1702                 amdgpu_bo_unreserve(adev->fw_vram_usage.reserved_bo);
1703         }
1704         return r;
1705
1706 error_kmap:
1707         amdgpu_bo_unpin(adev->fw_vram_usage.reserved_bo);
1708 error_pin:
1709         amdgpu_bo_unreserve(adev->fw_vram_usage.reserved_bo);
1710 error_reserve:
1711         amdgpu_bo_unref(&adev->fw_vram_usage.reserved_bo);
1712 error_create:
1713         adev->fw_vram_usage.va = NULL;
1714         adev->fw_vram_usage.reserved_bo = NULL;
1715         return r;
1716 }
1717 /**
1718  * amdgpu_ttm_init - Init the memory management (ttm) as well as various
1719  * gtt/vram related fields.
1720  *
1721  * This initializes all of the memory space pools that the TTM layer
1722  * will need such as the GTT space (system memory mapped to the device),
1723  * VRAM (on-board memory), and on-chip memories (GDS, GWS, OA) which
1724  * can be mapped per VMID.
1725  */
1726 int amdgpu_ttm_init(struct amdgpu_device *adev)
1727 {
1728         uint64_t gtt_size;
1729         int r;
1730         u64 vis_vram_limit;
1731
1732         /* initialize global references for vram/gtt */
1733         r = amdgpu_ttm_global_init(adev);
1734         if (r) {
1735                 return r;
1736         }
1737         /* No others user of address space so set it to 0 */
1738         r = ttm_bo_device_init(&adev->mman.bdev,
1739                                adev->mman.bo_global_ref.ref.object,
1740                                &amdgpu_bo_driver,
1741                                adev->ddev->anon_inode->i_mapping,
1742                                DRM_FILE_PAGE_OFFSET,
1743                                adev->need_dma32);
1744         if (r) {
1745                 DRM_ERROR("failed initializing buffer object driver(%d).\n", r);
1746                 return r;
1747         }
1748         adev->mman.initialized = true;
1749
1750         /* We opt to avoid OOM on system pages allocations */
1751         adev->mman.bdev.no_retry = true;
1752
1753         /* Initialize VRAM pool with all of VRAM divided into pages */
1754         r = ttm_bo_init_mm(&adev->mman.bdev, TTM_PL_VRAM,
1755                                 adev->gmc.real_vram_size >> PAGE_SHIFT);
1756         if (r) {
1757                 DRM_ERROR("Failed initializing VRAM heap.\n");
1758                 return r;
1759         }
1760
1761         /* Reduce size of CPU-visible VRAM if requested */
1762         vis_vram_limit = (u64)amdgpu_vis_vram_limit * 1024 * 1024;
1763         if (amdgpu_vis_vram_limit > 0 &&
1764             vis_vram_limit <= adev->gmc.visible_vram_size)
1765                 adev->gmc.visible_vram_size = vis_vram_limit;
1766
1767         /* Change the size here instead of the init above so only lpfn is affected */
1768         amdgpu_ttm_set_buffer_funcs_status(adev, false);
1769 #ifdef CONFIG_64BIT
1770         adev->mman.aper_base_kaddr = ioremap_wc(adev->gmc.aper_base,
1771                                                 adev->gmc.visible_vram_size);
1772 #endif
1773
1774         /*
1775          *The reserved vram for firmware must be pinned to the specified
1776          *place on the VRAM, so reserve it early.
1777          */
1778         r = amdgpu_ttm_fw_reserve_vram_init(adev);
1779         if (r) {
1780                 return r;
1781         }
1782
1783         /* allocate memory as required for VGA
1784          * This is used for VGA emulation and pre-OS scanout buffers to
1785          * avoid display artifacts while transitioning between pre-OS
1786          * and driver.  */
1787         if (adev->gmc.stolen_size) {
1788                 r = amdgpu_bo_create_kernel(adev, adev->gmc.stolen_size, PAGE_SIZE,
1789                                             AMDGPU_GEM_DOMAIN_VRAM,
1790                                             &adev->stolen_vga_memory,
1791                                             NULL, NULL);
1792                 if (r)
1793                         return r;
1794         }
1795         DRM_INFO("amdgpu: %uM of VRAM memory ready\n",
1796                  (unsigned) (adev->gmc.real_vram_size / (1024 * 1024)));
1797
1798         /* Compute GTT size, either bsaed on 3/4th the size of RAM size
1799          * or whatever the user passed on module init */
1800         if (amdgpu_gtt_size == -1) {
1801                 struct sysinfo si;
1802
1803                 si_meminfo(&si);
1804                 gtt_size = min(max((AMDGPU_DEFAULT_GTT_SIZE_MB << 20),
1805                                adev->gmc.mc_vram_size),
1806                                ((uint64_t)si.totalram * si.mem_unit * 3/4));
1807         }
1808         else
1809                 gtt_size = (uint64_t)amdgpu_gtt_size << 20;
1810
1811         /* Initialize GTT memory pool */
1812         r = ttm_bo_init_mm(&adev->mman.bdev, TTM_PL_TT, gtt_size >> PAGE_SHIFT);
1813         if (r) {
1814                 DRM_ERROR("Failed initializing GTT heap.\n");
1815                 return r;
1816         }
1817         DRM_INFO("amdgpu: %uM of GTT memory ready.\n",
1818                  (unsigned)(gtt_size / (1024 * 1024)));
1819
1820         /* Initialize various on-chip memory pools */
1821         adev->gds.mem.total_size = adev->gds.mem.total_size << AMDGPU_GDS_SHIFT;
1822         adev->gds.mem.gfx_partition_size = adev->gds.mem.gfx_partition_size << AMDGPU_GDS_SHIFT;
1823         adev->gds.mem.cs_partition_size = adev->gds.mem.cs_partition_size << AMDGPU_GDS_SHIFT;
1824         adev->gds.gws.total_size = adev->gds.gws.total_size << AMDGPU_GWS_SHIFT;
1825         adev->gds.gws.gfx_partition_size = adev->gds.gws.gfx_partition_size << AMDGPU_GWS_SHIFT;
1826         adev->gds.gws.cs_partition_size = adev->gds.gws.cs_partition_size << AMDGPU_GWS_SHIFT;
1827         adev->gds.oa.total_size = adev->gds.oa.total_size << AMDGPU_OA_SHIFT;
1828         adev->gds.oa.gfx_partition_size = adev->gds.oa.gfx_partition_size << AMDGPU_OA_SHIFT;
1829         adev->gds.oa.cs_partition_size = adev->gds.oa.cs_partition_size << AMDGPU_OA_SHIFT;
1830         /* GDS Memory */
1831         if (adev->gds.mem.total_size) {
1832                 r = ttm_bo_init_mm(&adev->mman.bdev, AMDGPU_PL_GDS,
1833                                    adev->gds.mem.total_size >> PAGE_SHIFT);
1834                 if (r) {
1835                         DRM_ERROR("Failed initializing GDS heap.\n");
1836                         return r;
1837                 }
1838         }
1839
1840         /* GWS */
1841         if (adev->gds.gws.total_size) {
1842                 r = ttm_bo_init_mm(&adev->mman.bdev, AMDGPU_PL_GWS,
1843                                    adev->gds.gws.total_size >> PAGE_SHIFT);
1844                 if (r) {
1845                         DRM_ERROR("Failed initializing gws heap.\n");
1846                         return r;
1847                 }
1848         }
1849
1850         /* OA */
1851         if (adev->gds.oa.total_size) {
1852                 r = ttm_bo_init_mm(&adev->mman.bdev, AMDGPU_PL_OA,
1853                                    adev->gds.oa.total_size >> PAGE_SHIFT);
1854                 if (r) {
1855                         DRM_ERROR("Failed initializing oa heap.\n");
1856                         return r;
1857                 }
1858         }
1859
1860         /* Register debugfs entries for amdgpu_ttm */
1861         r = amdgpu_ttm_debugfs_init(adev);
1862         if (r) {
1863                 DRM_ERROR("Failed to init debugfs\n");
1864                 return r;
1865         }
1866         return 0;
1867 }
1868
1869 /**
1870  * amdgpu_ttm_late_init - Handle any late initialization for amdgpu_ttm
1871  */
1872 void amdgpu_ttm_late_init(struct amdgpu_device *adev)
1873 {
1874         /* return the VGA stolen memory (if any) back to VRAM */
1875         amdgpu_bo_free_kernel(&adev->stolen_vga_memory, NULL, NULL);
1876 }
1877
1878 /**
1879  * amdgpu_ttm_fini - De-initialize the TTM memory pools
1880  */
1881 void amdgpu_ttm_fini(struct amdgpu_device *adev)
1882 {
1883         if (!adev->mman.initialized)
1884                 return;
1885
1886         amdgpu_ttm_debugfs_fini(adev);
1887         amdgpu_ttm_fw_reserve_vram_fini(adev);
1888         if (adev->mman.aper_base_kaddr)
1889                 iounmap(adev->mman.aper_base_kaddr);
1890         adev->mman.aper_base_kaddr = NULL;
1891
1892         ttm_bo_clean_mm(&adev->mman.bdev, TTM_PL_VRAM);
1893         ttm_bo_clean_mm(&adev->mman.bdev, TTM_PL_TT);
1894         if (adev->gds.mem.total_size)
1895                 ttm_bo_clean_mm(&adev->mman.bdev, AMDGPU_PL_GDS);
1896         if (adev->gds.gws.total_size)
1897                 ttm_bo_clean_mm(&adev->mman.bdev, AMDGPU_PL_GWS);
1898         if (adev->gds.oa.total_size)
1899                 ttm_bo_clean_mm(&adev->mman.bdev, AMDGPU_PL_OA);
1900         ttm_bo_device_release(&adev->mman.bdev);
1901         amdgpu_ttm_global_fini(adev);
1902         adev->mman.initialized = false;
1903         DRM_INFO("amdgpu: ttm finalized\n");
1904 }
1905
1906 /**
1907  * amdgpu_ttm_set_buffer_funcs_status - enable/disable use of buffer functions
1908  *
1909  * @adev: amdgpu_device pointer
1910  * @enable: true when we can use buffer functions.
1911  *
1912  * Enable/disable use of buffer functions during suspend/resume. This should
1913  * only be called at bootup or when userspace isn't running.
1914  */
1915 void amdgpu_ttm_set_buffer_funcs_status(struct amdgpu_device *adev, bool enable)
1916 {
1917         struct ttm_mem_type_manager *man = &adev->mman.bdev.man[TTM_PL_VRAM];
1918         uint64_t size;
1919         int r;
1920
1921         if (!adev->mman.initialized || adev->in_gpu_reset ||
1922             adev->mman.buffer_funcs_enabled == enable)
1923                 return;
1924
1925         if (enable) {
1926                 struct amdgpu_ring *ring;
1927                 struct drm_sched_rq *rq;
1928
1929                 ring = adev->mman.buffer_funcs_ring;
1930                 rq = &ring->sched.sched_rq[DRM_SCHED_PRIORITY_KERNEL];
1931                 r = drm_sched_entity_init(&adev->mman.entity, &rq, 1, NULL);
1932                 if (r) {
1933                         DRM_ERROR("Failed setting up TTM BO move entity (%d)\n",
1934                                   r);
1935                         return;
1936                 }
1937         } else {
1938                 drm_sched_entity_destroy(&adev->mman.entity);
1939                 dma_fence_put(man->move);
1940                 man->move = NULL;
1941         }
1942
1943         /* this just adjusts TTM size idea, which sets lpfn to the correct value */
1944         if (enable)
1945                 size = adev->gmc.real_vram_size;
1946         else
1947                 size = adev->gmc.visible_vram_size;
1948         man->size = size >> PAGE_SHIFT;
1949         adev->mman.buffer_funcs_enabled = enable;
1950 }
1951
1952 int amdgpu_mmap(struct file *filp, struct vm_area_struct *vma)
1953 {
1954         struct drm_file *file_priv;
1955         struct amdgpu_device *adev;
1956
1957         if (unlikely(vma->vm_pgoff < DRM_FILE_PAGE_OFFSET))
1958                 return -EINVAL;
1959
1960         file_priv = filp->private_data;
1961         adev = file_priv->minor->dev->dev_private;
1962         if (adev == NULL)
1963                 return -EINVAL;
1964
1965         return ttm_bo_mmap(filp, vma, &adev->mman.bdev);
1966 }
1967
1968 static int amdgpu_map_buffer(struct ttm_buffer_object *bo,
1969                              struct ttm_mem_reg *mem, unsigned num_pages,
1970                              uint64_t offset, unsigned window,
1971                              struct amdgpu_ring *ring,
1972                              uint64_t *addr)
1973 {
1974         struct amdgpu_ttm_tt *gtt = (void *)bo->ttm;
1975         struct amdgpu_device *adev = ring->adev;
1976         struct ttm_tt *ttm = bo->ttm;
1977         struct amdgpu_job *job;
1978         unsigned num_dw, num_bytes;
1979         dma_addr_t *dma_address;
1980         struct dma_fence *fence;
1981         uint64_t src_addr, dst_addr;
1982         uint64_t flags;
1983         int r;
1984
1985         BUG_ON(adev->mman.buffer_funcs->copy_max_bytes <
1986                AMDGPU_GTT_MAX_TRANSFER_SIZE * 8);
1987
1988         *addr = adev->gmc.gart_start;
1989         *addr += (u64)window * AMDGPU_GTT_MAX_TRANSFER_SIZE *
1990                 AMDGPU_GPU_PAGE_SIZE;
1991
1992         num_dw = adev->mman.buffer_funcs->copy_num_dw;
1993         while (num_dw & 0x7)
1994                 num_dw++;
1995
1996         num_bytes = num_pages * 8;
1997
1998         r = amdgpu_job_alloc_with_ib(adev, num_dw * 4 + num_bytes, &job);
1999         if (r)
2000                 return r;
2001
2002         src_addr = num_dw * 4;
2003         src_addr += job->ibs[0].gpu_addr;
2004
2005         dst_addr = amdgpu_bo_gpu_offset(adev->gart.bo);
2006         dst_addr += window * AMDGPU_GTT_MAX_TRANSFER_SIZE * 8;
2007         amdgpu_emit_copy_buffer(adev, &job->ibs[0], src_addr,
2008                                 dst_addr, num_bytes);
2009
2010         amdgpu_ring_pad_ib(ring, &job->ibs[0]);
2011         WARN_ON(job->ibs[0].length_dw > num_dw);
2012
2013         dma_address = &gtt->ttm.dma_address[offset >> PAGE_SHIFT];
2014         flags = amdgpu_ttm_tt_pte_flags(adev, ttm, mem);
2015         r = amdgpu_gart_map(adev, 0, num_pages, dma_address, flags,
2016                             &job->ibs[0].ptr[num_dw]);
2017         if (r)
2018                 goto error_free;
2019
2020         r = amdgpu_job_submit(job, &adev->mman.entity,
2021                               AMDGPU_FENCE_OWNER_UNDEFINED, &fence);
2022         if (r)
2023                 goto error_free;
2024
2025         dma_fence_put(fence);
2026
2027         return r;
2028
2029 error_free:
2030         amdgpu_job_free(job);
2031         return r;
2032 }
2033
2034 int amdgpu_copy_buffer(struct amdgpu_ring *ring, uint64_t src_offset,
2035                        uint64_t dst_offset, uint32_t byte_count,
2036                        struct reservation_object *resv,
2037                        struct dma_fence **fence, bool direct_submit,
2038                        bool vm_needs_flush)
2039 {
2040         struct amdgpu_device *adev = ring->adev;
2041         struct amdgpu_job *job;
2042
2043         uint32_t max_bytes;
2044         unsigned num_loops, num_dw;
2045         unsigned i;
2046         int r;
2047
2048         if (direct_submit && !ring->ready) {
2049                 DRM_ERROR("Trying to move memory with ring turned off.\n");
2050                 return -EINVAL;
2051         }
2052
2053         max_bytes = adev->mman.buffer_funcs->copy_max_bytes;
2054         num_loops = DIV_ROUND_UP(byte_count, max_bytes);
2055         num_dw = num_loops * adev->mman.buffer_funcs->copy_num_dw;
2056
2057         /* for IB padding */
2058         while (num_dw & 0x7)
2059                 num_dw++;
2060
2061         r = amdgpu_job_alloc_with_ib(adev, num_dw * 4, &job);
2062         if (r)
2063                 return r;
2064
2065         if (vm_needs_flush) {
2066                 job->vm_pd_addr = amdgpu_gmc_pd_addr(adev->gart.bo);
2067                 job->vm_needs_flush = true;
2068         }
2069         if (resv) {
2070                 r = amdgpu_sync_resv(adev, &job->sync, resv,
2071                                      AMDGPU_FENCE_OWNER_UNDEFINED,
2072                                      false);
2073                 if (r) {
2074                         DRM_ERROR("sync failed (%d).\n", r);
2075                         goto error_free;
2076                 }
2077         }
2078
2079         for (i = 0; i < num_loops; i++) {
2080                 uint32_t cur_size_in_bytes = min(byte_count, max_bytes);
2081
2082                 amdgpu_emit_copy_buffer(adev, &job->ibs[0], src_offset,
2083                                         dst_offset, cur_size_in_bytes);
2084
2085                 src_offset += cur_size_in_bytes;
2086                 dst_offset += cur_size_in_bytes;
2087                 byte_count -= cur_size_in_bytes;
2088         }
2089
2090         amdgpu_ring_pad_ib(ring, &job->ibs[0]);
2091         WARN_ON(job->ibs[0].length_dw > num_dw);
2092         if (direct_submit)
2093                 r = amdgpu_job_submit_direct(job, ring, fence);
2094         else
2095                 r = amdgpu_job_submit(job, &adev->mman.entity,
2096                                       AMDGPU_FENCE_OWNER_UNDEFINED, fence);
2097         if (r)
2098                 goto error_free;
2099
2100         return r;
2101
2102 error_free:
2103         amdgpu_job_free(job);
2104         DRM_ERROR("Error scheduling IBs (%d)\n", r);
2105         return r;
2106 }
2107
2108 int amdgpu_fill_buffer(struct amdgpu_bo *bo,
2109                        uint32_t src_data,
2110                        struct reservation_object *resv,
2111                        struct dma_fence **fence)
2112 {
2113         struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev);
2114         uint32_t max_bytes = adev->mman.buffer_funcs->fill_max_bytes;
2115         struct amdgpu_ring *ring = adev->mman.buffer_funcs_ring;
2116
2117         struct drm_mm_node *mm_node;
2118         unsigned long num_pages;
2119         unsigned int num_loops, num_dw;
2120
2121         struct amdgpu_job *job;
2122         int r;
2123
2124         if (!adev->mman.buffer_funcs_enabled) {
2125                 DRM_ERROR("Trying to clear memory with ring turned off.\n");
2126                 return -EINVAL;
2127         }
2128
2129         if (bo->tbo.mem.mem_type == TTM_PL_TT) {
2130                 r = amdgpu_ttm_alloc_gart(&bo->tbo);
2131                 if (r)
2132                         return r;
2133         }
2134
2135         num_pages = bo->tbo.num_pages;
2136         mm_node = bo->tbo.mem.mm_node;
2137         num_loops = 0;
2138         while (num_pages) {
2139                 uint32_t byte_count = mm_node->size << PAGE_SHIFT;
2140
2141                 num_loops += DIV_ROUND_UP(byte_count, max_bytes);
2142                 num_pages -= mm_node->size;
2143                 ++mm_node;
2144         }
2145         num_dw = num_loops * adev->mman.buffer_funcs->fill_num_dw;
2146
2147         /* for IB padding */
2148         num_dw += 64;
2149
2150         r = amdgpu_job_alloc_with_ib(adev, num_dw * 4, &job);
2151         if (r)
2152                 return r;
2153
2154         if (resv) {
2155                 r = amdgpu_sync_resv(adev, &job->sync, resv,
2156                                      AMDGPU_FENCE_OWNER_UNDEFINED, false);
2157                 if (r) {
2158                         DRM_ERROR("sync failed (%d).\n", r);
2159                         goto error_free;
2160                 }
2161         }
2162
2163         num_pages = bo->tbo.num_pages;
2164         mm_node = bo->tbo.mem.mm_node;
2165
2166         while (num_pages) {
2167                 uint32_t byte_count = mm_node->size << PAGE_SHIFT;
2168                 uint64_t dst_addr;
2169
2170                 dst_addr = amdgpu_mm_node_addr(&bo->tbo, mm_node, &bo->tbo.mem);
2171                 while (byte_count) {
2172                         uint32_t cur_size_in_bytes = min(byte_count, max_bytes);
2173
2174                         amdgpu_emit_fill_buffer(adev, &job->ibs[0], src_data,
2175                                                 dst_addr, cur_size_in_bytes);
2176
2177                         dst_addr += cur_size_in_bytes;
2178                         byte_count -= cur_size_in_bytes;
2179                 }
2180
2181                 num_pages -= mm_node->size;
2182                 ++mm_node;
2183         }
2184
2185         amdgpu_ring_pad_ib(ring, &job->ibs[0]);
2186         WARN_ON(job->ibs[0].length_dw > num_dw);
2187         r = amdgpu_job_submit(job, &adev->mman.entity,
2188                               AMDGPU_FENCE_OWNER_UNDEFINED, fence);
2189         if (r)
2190                 goto error_free;
2191
2192         return 0;
2193
2194 error_free:
2195         amdgpu_job_free(job);
2196         return r;
2197 }
2198
2199 #if defined(CONFIG_DEBUG_FS)
2200
2201 static int amdgpu_mm_dump_table(struct seq_file *m, void *data)
2202 {
2203         struct drm_info_node *node = (struct drm_info_node *)m->private;
2204         unsigned ttm_pl = *(int *)node->info_ent->data;
2205         struct drm_device *dev = node->minor->dev;
2206         struct amdgpu_device *adev = dev->dev_private;
2207         struct ttm_mem_type_manager *man = &adev->mman.bdev.man[ttm_pl];
2208         struct drm_printer p = drm_seq_file_printer(m);
2209
2210         man->func->debug(man, &p);
2211         return 0;
2212 }
2213
2214 static int ttm_pl_vram = TTM_PL_VRAM;
2215 static int ttm_pl_tt = TTM_PL_TT;
2216
2217 static const struct drm_info_list amdgpu_ttm_debugfs_list[] = {
2218         {"amdgpu_vram_mm", amdgpu_mm_dump_table, 0, &ttm_pl_vram},
2219         {"amdgpu_gtt_mm", amdgpu_mm_dump_table, 0, &ttm_pl_tt},
2220         {"ttm_page_pool", ttm_page_alloc_debugfs, 0, NULL},
2221 #ifdef CONFIG_SWIOTLB
2222         {"ttm_dma_page_pool", ttm_dma_page_alloc_debugfs, 0, NULL}
2223 #endif
2224 };
2225
2226 /**
2227  * amdgpu_ttm_vram_read - Linear read access to VRAM
2228  *
2229  * Accesses VRAM via MMIO for debugging purposes.
2230  */
2231 static ssize_t amdgpu_ttm_vram_read(struct file *f, char __user *buf,
2232                                     size_t size, loff_t *pos)
2233 {
2234         struct amdgpu_device *adev = file_inode(f)->i_private;
2235         ssize_t result = 0;
2236         int r;
2237
2238         if (size & 0x3 || *pos & 0x3)
2239                 return -EINVAL;
2240
2241         if (*pos >= adev->gmc.mc_vram_size)
2242                 return -ENXIO;
2243
2244         while (size) {
2245                 unsigned long flags;
2246                 uint32_t value;
2247
2248                 if (*pos >= adev->gmc.mc_vram_size)
2249                         return result;
2250
2251                 spin_lock_irqsave(&adev->mmio_idx_lock, flags);
2252                 WREG32_NO_KIQ(mmMM_INDEX, ((uint32_t)*pos) | 0x80000000);
2253                 WREG32_NO_KIQ(mmMM_INDEX_HI, *pos >> 31);
2254                 value = RREG32_NO_KIQ(mmMM_DATA);
2255                 spin_unlock_irqrestore(&adev->mmio_idx_lock, flags);
2256
2257                 r = put_user(value, (uint32_t *)buf);
2258                 if (r)
2259                         return r;
2260
2261                 result += 4;
2262                 buf += 4;
2263                 *pos += 4;
2264                 size -= 4;
2265         }
2266
2267         return result;
2268 }
2269
2270 /**
2271  * amdgpu_ttm_vram_write - Linear write access to VRAM
2272  *
2273  * Accesses VRAM via MMIO for debugging purposes.
2274  */
2275 static ssize_t amdgpu_ttm_vram_write(struct file *f, const char __user *buf,
2276                                     size_t size, loff_t *pos)
2277 {
2278         struct amdgpu_device *adev = file_inode(f)->i_private;
2279         ssize_t result = 0;
2280         int r;
2281
2282         if (size & 0x3 || *pos & 0x3)
2283                 return -EINVAL;
2284
2285         if (*pos >= adev->gmc.mc_vram_size)
2286                 return -ENXIO;
2287
2288         while (size) {
2289                 unsigned long flags;
2290                 uint32_t value;
2291
2292                 if (*pos >= adev->gmc.mc_vram_size)
2293                         return result;
2294
2295                 r = get_user(value, (uint32_t *)buf);
2296                 if (r)
2297                         return r;
2298
2299                 spin_lock_irqsave(&adev->mmio_idx_lock, flags);
2300                 WREG32_NO_KIQ(mmMM_INDEX, ((uint32_t)*pos) | 0x80000000);
2301                 WREG32_NO_KIQ(mmMM_INDEX_HI, *pos >> 31);
2302                 WREG32_NO_KIQ(mmMM_DATA, value);
2303                 spin_unlock_irqrestore(&adev->mmio_idx_lock, flags);
2304
2305                 result += 4;
2306                 buf += 4;
2307                 *pos += 4;
2308                 size -= 4;
2309         }
2310
2311         return result;
2312 }
2313
2314 static const struct file_operations amdgpu_ttm_vram_fops = {
2315         .owner = THIS_MODULE,
2316         .read = amdgpu_ttm_vram_read,
2317         .write = amdgpu_ttm_vram_write,
2318         .llseek = default_llseek,
2319 };
2320
2321 #ifdef CONFIG_DRM_AMDGPU_GART_DEBUGFS
2322
2323 /**
2324  * amdgpu_ttm_gtt_read - Linear read access to GTT memory
2325  */
2326 static ssize_t amdgpu_ttm_gtt_read(struct file *f, char __user *buf,
2327                                    size_t size, loff_t *pos)
2328 {
2329         struct amdgpu_device *adev = file_inode(f)->i_private;
2330         ssize_t result = 0;
2331         int r;
2332
2333         while (size) {
2334                 loff_t p = *pos / PAGE_SIZE;
2335                 unsigned off = *pos & ~PAGE_MASK;
2336                 size_t cur_size = min_t(size_t, size, PAGE_SIZE - off);
2337                 struct page *page;
2338                 void *ptr;
2339
2340                 if (p >= adev->gart.num_cpu_pages)
2341                         return result;
2342
2343                 page = adev->gart.pages[p];
2344                 if (page) {
2345                         ptr = kmap(page);
2346                         ptr += off;
2347
2348                         r = copy_to_user(buf, ptr, cur_size);
2349                         kunmap(adev->gart.pages[p]);
2350                 } else
2351                         r = clear_user(buf, cur_size);
2352
2353                 if (r)
2354                         return -EFAULT;
2355
2356                 result += cur_size;
2357                 buf += cur_size;
2358                 *pos += cur_size;
2359                 size -= cur_size;
2360         }
2361
2362         return result;
2363 }
2364
2365 static const struct file_operations amdgpu_ttm_gtt_fops = {
2366         .owner = THIS_MODULE,
2367         .read = amdgpu_ttm_gtt_read,
2368         .llseek = default_llseek
2369 };
2370
2371 #endif
2372
2373 /**
2374  * amdgpu_iomem_read - Virtual read access to GPU mapped memory
2375  *
2376  * This function is used to read memory that has been mapped to the
2377  * GPU and the known addresses are not physical addresses but instead
2378  * bus addresses (e.g., what you'd put in an IB or ring buffer).
2379  */
2380 static ssize_t amdgpu_iomem_read(struct file *f, char __user *buf,
2381                                  size_t size, loff_t *pos)
2382 {
2383         struct amdgpu_device *adev = file_inode(f)->i_private;
2384         struct iommu_domain *dom;
2385         ssize_t result = 0;
2386         int r;
2387
2388         /* retrieve the IOMMU domain if any for this device */
2389         dom = iommu_get_domain_for_dev(adev->dev);
2390
2391         while (size) {
2392                 phys_addr_t addr = *pos & PAGE_MASK;
2393                 loff_t off = *pos & ~PAGE_MASK;
2394                 size_t bytes = PAGE_SIZE - off;
2395                 unsigned long pfn;
2396                 struct page *p;
2397                 void *ptr;
2398
2399                 bytes = bytes < size ? bytes : size;
2400
2401                 /* Translate the bus address to a physical address.  If
2402                  * the domain is NULL it means there is no IOMMU active
2403                  * and the address translation is the identity
2404                  */
2405                 addr = dom ? iommu_iova_to_phys(dom, addr) : addr;
2406
2407                 pfn = addr >> PAGE_SHIFT;
2408                 if (!pfn_valid(pfn))
2409                         return -EPERM;
2410
2411                 p = pfn_to_page(pfn);
2412                 if (p->mapping != adev->mman.bdev.dev_mapping)
2413                         return -EPERM;
2414
2415                 ptr = kmap(p);
2416                 r = copy_to_user(buf, ptr + off, bytes);
2417                 kunmap(p);
2418                 if (r)
2419                         return -EFAULT;
2420
2421                 size -= bytes;
2422                 *pos += bytes;
2423                 result += bytes;
2424         }
2425
2426         return result;
2427 }
2428
2429 /**
2430  * amdgpu_iomem_write - Virtual write access to GPU mapped memory
2431  *
2432  * This function is used to write memory that has been mapped to the
2433  * GPU and the known addresses are not physical addresses but instead
2434  * bus addresses (e.g., what you'd put in an IB or ring buffer).
2435  */
2436 static ssize_t amdgpu_iomem_write(struct file *f, const char __user *buf,
2437                                  size_t size, loff_t *pos)
2438 {
2439         struct amdgpu_device *adev = file_inode(f)->i_private;
2440         struct iommu_domain *dom;
2441         ssize_t result = 0;
2442         int r;
2443
2444         dom = iommu_get_domain_for_dev(adev->dev);
2445
2446         while (size) {
2447                 phys_addr_t addr = *pos & PAGE_MASK;
2448                 loff_t off = *pos & ~PAGE_MASK;
2449                 size_t bytes = PAGE_SIZE - off;
2450                 unsigned long pfn;
2451                 struct page *p;
2452                 void *ptr;
2453
2454                 bytes = bytes < size ? bytes : size;
2455
2456                 addr = dom ? iommu_iova_to_phys(dom, addr) : addr;
2457
2458                 pfn = addr >> PAGE_SHIFT;
2459                 if (!pfn_valid(pfn))
2460                         return -EPERM;
2461
2462                 p = pfn_to_page(pfn);
2463                 if (p->mapping != adev->mman.bdev.dev_mapping)
2464                         return -EPERM;
2465
2466                 ptr = kmap(p);
2467                 r = copy_from_user(ptr + off, buf, bytes);
2468                 kunmap(p);
2469                 if (r)
2470                         return -EFAULT;
2471
2472                 size -= bytes;
2473                 *pos += bytes;
2474                 result += bytes;
2475         }
2476
2477         return result;
2478 }
2479
2480 static const struct file_operations amdgpu_ttm_iomem_fops = {
2481         .owner = THIS_MODULE,
2482         .read = amdgpu_iomem_read,
2483         .write = amdgpu_iomem_write,
2484         .llseek = default_llseek
2485 };
2486
2487 static const struct {
2488         char *name;
2489         const struct file_operations *fops;
2490         int domain;
2491 } ttm_debugfs_entries[] = {
2492         { "amdgpu_vram", &amdgpu_ttm_vram_fops, TTM_PL_VRAM },
2493 #ifdef CONFIG_DRM_AMDGPU_GART_DEBUGFS
2494         { "amdgpu_gtt", &amdgpu_ttm_gtt_fops, TTM_PL_TT },
2495 #endif
2496         { "amdgpu_iomem", &amdgpu_ttm_iomem_fops, TTM_PL_SYSTEM },
2497 };
2498
2499 #endif
2500
2501 static int amdgpu_ttm_debugfs_init(struct amdgpu_device *adev)
2502 {
2503 #if defined(CONFIG_DEBUG_FS)
2504         unsigned count;
2505
2506         struct drm_minor *minor = adev->ddev->primary;
2507         struct dentry *ent, *root = minor->debugfs_root;
2508
2509         for (count = 0; count < ARRAY_SIZE(ttm_debugfs_entries); count++) {
2510                 ent = debugfs_create_file(
2511                                 ttm_debugfs_entries[count].name,
2512                                 S_IFREG | S_IRUGO, root,
2513                                 adev,
2514                                 ttm_debugfs_entries[count].fops);
2515                 if (IS_ERR(ent))
2516                         return PTR_ERR(ent);
2517                 if (ttm_debugfs_entries[count].domain == TTM_PL_VRAM)
2518                         i_size_write(ent->d_inode, adev->gmc.mc_vram_size);
2519                 else if (ttm_debugfs_entries[count].domain == TTM_PL_TT)
2520                         i_size_write(ent->d_inode, adev->gmc.gart_size);
2521                 adev->mman.debugfs_entries[count] = ent;
2522         }
2523
2524         count = ARRAY_SIZE(amdgpu_ttm_debugfs_list);
2525
2526 #ifdef CONFIG_SWIOTLB
2527         if (!(adev->need_swiotlb && swiotlb_nr_tbl()))
2528                 --count;
2529 #endif
2530
2531         return amdgpu_debugfs_add_files(adev, amdgpu_ttm_debugfs_list, count);
2532 #else
2533         return 0;
2534 #endif
2535 }
2536
2537 static void amdgpu_ttm_debugfs_fini(struct amdgpu_device *adev)
2538 {
2539 #if defined(CONFIG_DEBUG_FS)
2540         unsigned i;
2541
2542         for (i = 0; i < ARRAY_SIZE(ttm_debugfs_entries); i++)
2543                 debugfs_remove(adev->mman.debugfs_entries[i]);
2544 #endif
2545 }