drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c

   1 /*
   2  * Copyright 2019 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23 #include <linux/firmware.h>
  24 #include <linux/pci.h>
  25 #include "amdgpu.h"
  26 #include "amdgpu_atomfirmware.h"
  27 #include "gmc_v10_0.h"
  28 #include "umc_v8_7.h"
  29
  30 #include "athub/athub_2_0_0_sh_mask.h"
  31 #include "athub/athub_2_0_0_offset.h"
  32 #include "dcn/dcn_2_0_0_offset.h"
  33 #include "dcn/dcn_2_0_0_sh_mask.h"
  34 #include "oss/osssys_5_0_0_offset.h"
  35 #include "ivsrcid/vmc/irqsrcs_vmc_1_0.h"
  36 #include "navi10_enum.h"
  37
  38 #include "soc15.h"
  39 #include "soc15d.h"
  40 #include "soc15_common.h"
  41
  42 #include "nbio_v2_3.h"
  43
  44 #include "gfxhub_v2_0.h"
  45 #include "gfxhub_v2_1.h"
  46 #include "mmhub_v2_0.h"
  47 #include "mmhub_v2_3.h"
  48 #include "athub_v2_0.h"
  49 #include "athub_v2_1.h"
  50
  51 #if 0
  52 static const struct soc15_reg_golden golden_settings_navi10_hdp[] =
  53 {
  54         /* TODO add golden setting for hdp */
  55 };
  56 #endif
  57
  58 static int gmc_v10_0_ecc_interrupt_state(struct amdgpu_device *adev,
  59                                          struct amdgpu_irq_src *src,
  60                                          unsigned type,
  61                                          enum amdgpu_interrupt_state state)
  62 {
  63         return 0;
  64 }
  65
  66 static int
  67 gmc_v10_0_vm_fault_interrupt_state(struct amdgpu_device *adev,
  68                                    struct amdgpu_irq_src *src, unsigned type,
  69                                    enum amdgpu_interrupt_state state)
  70 {
  71         switch (state) {
  72         case AMDGPU_IRQ_STATE_DISABLE:
  73                 /* MM HUB */
  74                 amdgpu_gmc_set_vm_fault_masks(adev, AMDGPU_MMHUB_0, false);
  75                 /* GFX HUB */
  76                 amdgpu_gmc_set_vm_fault_masks(adev, AMDGPU_GFXHUB_0, false);
  77                 break;
  78         case AMDGPU_IRQ_STATE_ENABLE:
  79                 /* MM HUB */
  80                 amdgpu_gmc_set_vm_fault_masks(adev, AMDGPU_MMHUB_0, true);
  81                 /* GFX HUB */
  82                 amdgpu_gmc_set_vm_fault_masks(adev, AMDGPU_GFXHUB_0, true);
  83                 break;
  84         default:
  85                 break;
  86         }
  87
  88         return 0;
  89 }
  90
  91 static int gmc_v10_0_process_interrupt(struct amdgpu_device *adev,
  92                                        struct amdgpu_irq_src *source,
  93                                        struct amdgpu_iv_entry *entry)
  94 {
  95         bool retry_fault = !!(entry->src_data[1] & 0x80);
  96         struct amdgpu_vmhub *hub = &adev->vmhub[entry->vmid_src];
  97         struct amdgpu_task_info task_info;
  98         uint32_t status = 0;
  99         u64 addr;
 100
 101         addr = (u64)entry->src_data[0] << 12;
 102         addr |= ((u64)entry->src_data[1] & 0xf) << 44;
 103
 104         if (retry_fault) {
 105                 /* Returning 1 here also prevents sending the IV to the KFD */
 106
 107                 /* Process it onyl if it's the first fault for this address */
 108                 if (entry->ih != &adev->irq.ih_soft &&
 109                     amdgpu_gmc_filter_faults(adev, addr, entry->pasid,
 110                                              entry->timestamp))
 111                         return 1;
 112
 113                 /* Delegate it to a different ring if the hardware hasn't
 114                  * already done it.
 115                  */
 116                 if (entry->ih == &adev->irq.ih) {
 117                         amdgpu_irq_delegate(adev, entry, 8);
 118                         return 1;
 119                 }
 120
 121                 /* Try to handle the recoverable page faults by filling page
 122                  * tables
 123                  */
 124                 if (amdgpu_vm_handle_fault(adev, entry->pasid, addr))
 125                         return 1;
 126         }
 127
 128         if (!amdgpu_sriov_vf(adev)) {
 129                 /*
 130                  * Issue a dummy read to wait for the status register to
 131                  * be updated to avoid reading an incorrect value due to
 132                  * the new fast GRBM interface.
 133                  */
 134                 if ((entry->vmid_src == AMDGPU_GFXHUB_0) &&
 135                     (adev->asic_type < CHIP_SIENNA_CICHLID))
 136                         RREG32(hub->vm_l2_pro_fault_status);
 137
 138                 status = RREG32(hub->vm_l2_pro_fault_status);
 139                 WREG32_P(hub->vm_l2_pro_fault_cntl, 1, ~1);
 140         }
 141
 142         if (!printk_ratelimit())
 143                 return 0;
 144
 145         memset(&task_info, 0, sizeof(struct amdgpu_task_info));
 146         amdgpu_vm_get_task_info(adev, entry->pasid, &task_info);
 147
 148         dev_err(adev->dev,
 149                 "[%s] page fault (src_id:%u ring:%u vmid:%u pasid:%u, "
 150                 "for process %s pid %d thread %s pid %d)\n",
 151                 entry->vmid_src ? "mmhub" : "gfxhub",
 152                 entry->src_id, entry->ring_id, entry->vmid,
 153                 entry->pasid, task_info.process_name, task_info.tgid,
 154                 task_info.task_name, task_info.pid);
 155         dev_err(adev->dev, "  in page starting at address 0x%016llx from client 0x%x (%s)\n",
 156                 addr, entry->client_id,
 157                 soc15_ih_clientid_name[entry->client_id]);
 158
 159         if (!amdgpu_sriov_vf(adev))
 160                 hub->vmhub_funcs->print_l2_protection_fault_status(adev,
 161                                                                    status);
 162
 163         return 0;
 164 }
 165
 166 static const struct amdgpu_irq_src_funcs gmc_v10_0_irq_funcs = {
 167         .set = gmc_v10_0_vm_fault_interrupt_state,
 168         .process = gmc_v10_0_process_interrupt,
 169 };
 170
 171 static const struct amdgpu_irq_src_funcs gmc_v10_0_ecc_funcs = {
 172         .set = gmc_v10_0_ecc_interrupt_state,
 173         .process = amdgpu_umc_process_ecc_irq,
 174 };
 175
 176 static void gmc_v10_0_set_irq_funcs(struct amdgpu_device *adev)
 177 {
 178         adev->gmc.vm_fault.num_types = 1;
 179         adev->gmc.vm_fault.funcs = &gmc_v10_0_irq_funcs;
 180
 181         if (!amdgpu_sriov_vf(adev)) {
 182                 adev->gmc.ecc_irq.num_types = 1;
 183                 adev->gmc.ecc_irq.funcs = &gmc_v10_0_ecc_funcs;
 184         }
 185 }
 186
 187 /**
 188  * gmc_v10_0_use_invalidate_semaphore - judge whether to use semaphore
 189  *
 190  * @adev: amdgpu_device pointer
 191  * @vmhub: vmhub type
 192  *
 193  */
 194 static bool gmc_v10_0_use_invalidate_semaphore(struct amdgpu_device *adev,
 195                                        uint32_t vmhub)
 196 {
 197         return ((vmhub == AMDGPU_MMHUB_0 ||
 198                  vmhub == AMDGPU_MMHUB_1) &&
 199                 (!amdgpu_sriov_vf(adev)));
 200 }
 201
 202 static bool gmc_v10_0_get_atc_vmid_pasid_mapping_info(
 203                                         struct amdgpu_device *adev,
 204                                         uint8_t vmid, uint16_t *p_pasid)
 205 {
 206         uint32_t value;
 207
 208         value = RREG32(SOC15_REG_OFFSET(ATHUB, 0, mmATC_VMID0_PASID_MAPPING)
 209                      + vmid);
 210         *p_pasid = value & ATC_VMID0_PASID_MAPPING__PASID_MASK;
 211
 212         return !!(value & ATC_VMID0_PASID_MAPPING__VALID_MASK);
 213 }
 214
 215 /*
 216  * GART
 217  * VMID 0 is the physical GPU addresses as used by the kernel.
 218  * VMIDs 1-15 are used for userspace clients and are handled
 219  * by the amdgpu vm/hsa code.
 220  */
 221
 222 static void gmc_v10_0_flush_vm_hub(struct amdgpu_device *adev, uint32_t vmid,
 223                                    unsigned int vmhub, uint32_t flush_type)
 224 {
 225         bool use_semaphore = gmc_v10_0_use_invalidate_semaphore(adev, vmhub);
 226         struct amdgpu_vmhub *hub = &adev->vmhub[vmhub];
 227         u32 inv_req = hub->vmhub_funcs->get_invalidate_req(vmid, flush_type);
 228         u32 tmp;
 229         /* Use register 17 for GART */
 230         const unsigned eng = 17;
 231         unsigned int i;
 232         unsigned char hub_ip = 0;
 233
 234         hub_ip = (vmhub == AMDGPU_GFXHUB_0) ?
 235                    GC_HWIP : MMHUB_HWIP;
 236
 237         spin_lock(&adev->gmc.invalidate_lock);
 238         /*
 239          * It may lose gpuvm invalidate acknowldege state across power-gating
 240          * off cycle, add semaphore acquire before invalidation and semaphore
 241          * release after invalidation to avoid entering power gated state
 242          * to WA the Issue
 243          */
 244
 245         /* TODO: It needs to continue working on debugging with semaphore for GFXHUB as well. */
 246         if (use_semaphore) {
 247                 for (i = 0; i < adev->usec_timeout; i++) {
 248                         /* a read return value of 1 means semaphore acuqire */
 249                         tmp = RREG32_RLC_NO_KIQ(hub->vm_inv_eng0_sem +
 250                                          hub->eng_distance * eng, hub_ip);
 251
 252                         if (tmp & 0x1)
 253                                 break;
 254                         udelay(1);
 255                 }
 256
 257                 if (i >= adev->usec_timeout)
 258                         DRM_ERROR("Timeout waiting for sem acquire in VM flush!\n");
 259         }
 260
 261         WREG32_RLC_NO_KIQ(hub->vm_inv_eng0_req +
 262                           hub->eng_distance * eng,
 263                           inv_req, hub_ip);
 264
 265         /*
 266          * Issue a dummy read to wait for the ACK register to be cleared
 267          * to avoid a false ACK due to the new fast GRBM interface.
 268          */
 269         if ((vmhub == AMDGPU_GFXHUB_0) &&
 270             (adev->asic_type < CHIP_SIENNA_CICHLID))
 271                 RREG32_RLC_NO_KIQ(hub->vm_inv_eng0_req +
 272                                   hub->eng_distance * eng, hub_ip);
 273
 274         /* Wait for ACK with a delay.*/
 275         for (i = 0; i < adev->usec_timeout; i++) {
 276                 tmp = RREG32_RLC_NO_KIQ(hub->vm_inv_eng0_ack +
 277                                   hub->eng_distance * eng, hub_ip);
 278
 279                 tmp &= 1 << vmid;
 280                 if (tmp)
 281                         break;
 282
 283                 udelay(1);
 284         }
 285
 286         /* TODO: It needs to continue working on debugging with semaphore for GFXHUB as well. */
 287         if (use_semaphore)
 288                 /*
 289                  * add semaphore release after invalidation,
 290                  * write with 0 means semaphore release
 291                  */
 292                 WREG32_RLC_NO_KIQ(hub->vm_inv_eng0_sem +
 293                                   hub->eng_distance * eng, 0, hub_ip);
 294
 295         spin_unlock(&adev->gmc.invalidate_lock);
 296
 297         if (i < adev->usec_timeout)
 298                 return;
 299
 300         DRM_ERROR("Timeout waiting for VM flush hub: %d!\n", vmhub);
 301 }
 302
 303 /**
 304  * gmc_v10_0_flush_gpu_tlb - gart tlb flush callback
 305  *
 306  * @adev: amdgpu_device pointer
 307  * @vmid: vm instance to flush
 308  * @vmhub: vmhub type
 309  * @flush_type: the flush type
 310  *
 311  * Flush the TLB for the requested page table.
 312  */
 313 static void gmc_v10_0_flush_gpu_tlb(struct amdgpu_device *adev, uint32_t vmid,
 314                                         uint32_t vmhub, uint32_t flush_type)
 315 {
 316         struct amdgpu_ring *ring = adev->mman.buffer_funcs_ring;
 317         struct dma_fence *fence;
 318         struct amdgpu_job *job;
 319
 320         int r;
 321
 322         /* flush hdp cache */
 323         adev->hdp.funcs->flush_hdp(adev, NULL);
 324
 325         /* For SRIOV run time, driver shouldn't access the register through MMIO
 326          * Directly use kiq to do the vm invalidation instead
 327          */
 328         if (adev->gfx.kiq.ring.sched.ready &&
 329             (amdgpu_sriov_runtime(adev) || !amdgpu_sriov_vf(adev)) &&
 330             down_read_trylock(&adev->reset_sem)) {
 331                 struct amdgpu_vmhub *hub = &adev->vmhub[vmhub];
 332                 const unsigned eng = 17;
 333                 u32 inv_req = hub->vmhub_funcs->get_invalidate_req(vmid, flush_type);
 334                 u32 req = hub->vm_inv_eng0_req + hub->eng_distance * eng;
 335                 u32 ack = hub->vm_inv_eng0_ack + hub->eng_distance * eng;
 336
 337                 amdgpu_virt_kiq_reg_write_reg_wait(adev, req, ack, inv_req,
 338                                 1 << vmid);
 339
 340                 up_read(&adev->reset_sem);
 341                 return;
 342         }
 343
 344         mutex_lock(&adev->mman.gtt_window_lock);
 345
 346         if (vmhub == AMDGPU_MMHUB_0) {
 347                 gmc_v10_0_flush_vm_hub(adev, vmid, AMDGPU_MMHUB_0, 0);
 348                 mutex_unlock(&adev->mman.gtt_window_lock);
 349                 return;
 350         }
 351
 352         BUG_ON(vmhub != AMDGPU_GFXHUB_0);
 353
 354         if (!adev->mman.buffer_funcs_enabled ||
 355             !adev->ib_pool_ready ||
 356             amdgpu_in_reset(adev) ||
 357             ring->sched.ready == false) {
 358                 gmc_v10_0_flush_vm_hub(adev, vmid, AMDGPU_GFXHUB_0, 0);
 359                 mutex_unlock(&adev->mman.gtt_window_lock);
 360                 return;
 361         }
 362
 363         /* The SDMA on Navi has a bug which can theoretically result in memory
 364          * corruption if an invalidation happens at the same time as an VA
 365          * translation. Avoid this by doing the invalidation from the SDMA
 366          * itself.
 367          */
 368         r = amdgpu_job_alloc_with_ib(adev, 16 * 4, AMDGPU_IB_POOL_IMMEDIATE,
 369                                      &job);
 370         if (r)
 371                 goto error_alloc;
 372
 373         job->vm_pd_addr = amdgpu_gmc_pd_addr(adev->gart.bo);
 374         job->vm_needs_flush = true;
 375         job->ibs->ptr[job->ibs->length_dw++] = ring->funcs->nop;
 376         amdgpu_ring_pad_ib(ring, &job->ibs[0]);
 377         r = amdgpu_job_submit(job, &adev->mman.entity,
 378                               AMDGPU_FENCE_OWNER_UNDEFINED, &fence);
 379         if (r)
 380                 goto error_submit;
 381
 382         mutex_unlock(&adev->mman.gtt_window_lock);
 383
 384         dma_fence_wait(fence, false);
 385         dma_fence_put(fence);
 386
 387         return;
 388
 389 error_submit:
 390         amdgpu_job_free(job);
 391
 392 error_alloc:
 393         mutex_unlock(&adev->mman.gtt_window_lock);
 394         DRM_ERROR("Error flushing GPU TLB using the SDMA (%d)!\n", r);
 395 }
 396
 397 /**
 398  * gmc_v10_0_flush_gpu_tlb_pasid - tlb flush via pasid
 399  *
 400  * @adev: amdgpu_device pointer
 401  * @pasid: pasid to be flush
 402  * @flush_type: the flush type
 403  * @all_hub: Used with PACKET3_INVALIDATE_TLBS_ALL_HUB()
 404  *
 405  * Flush the TLB for the requested pasid.
 406  */
 407 static int gmc_v10_0_flush_gpu_tlb_pasid(struct amdgpu_device *adev,
 408                                         uint16_t pasid, uint32_t flush_type,
 409                                         bool all_hub)
 410 {
 411         int vmid, i;
 412         signed long r;
 413         uint32_t seq;
 414         uint16_t queried_pasid;
 415         bool ret;
 416         struct amdgpu_ring *ring = &adev->gfx.kiq.ring;
 417         struct amdgpu_kiq *kiq = &adev->gfx.kiq;
 418
 419         if (amdgpu_emu_mode == 0 && ring->sched.ready) {
 420                 spin_lock(&adev->gfx.kiq.ring_lock);
 421                 /* 2 dwords flush + 8 dwords fence */
 422                 amdgpu_ring_alloc(ring, kiq->pmf->invalidate_tlbs_size + 8);
 423                 kiq->pmf->kiq_invalidate_tlbs(ring,
 424                                         pasid, flush_type, all_hub);
 425                 r = amdgpu_fence_emit_polling(ring, &seq, MAX_KIQ_REG_WAIT);
 426                 if (r) {
 427                         amdgpu_ring_undo(ring);
 428                         spin_unlock(&adev->gfx.kiq.ring_lock);
 429                         return -ETIME;
 430                 }
 431
 432                 amdgpu_ring_commit(ring);
 433                 spin_unlock(&adev->gfx.kiq.ring_lock);
 434                 r = amdgpu_fence_wait_polling(ring, seq, adev->usec_timeout);
 435                 if (r < 1) {
 436                         dev_err(adev->dev, "wait for kiq fence error: %ld.\n", r);
 437                         return -ETIME;
 438                 }
 439
 440                 return 0;
 441         }
 442
 443         for (vmid = 1; vmid < AMDGPU_NUM_VMID; vmid++) {
 444
 445                 ret = gmc_v10_0_get_atc_vmid_pasid_mapping_info(adev, vmid,
 446                                 &queried_pasid);
 447                 if (ret && queried_pasid == pasid) {
 448                         if (all_hub) {
 449                                 for (i = 0; i < adev->num_vmhubs; i++)
 450                                         gmc_v10_0_flush_gpu_tlb(adev, vmid,
 451                                                         i, flush_type);
 452                         } else {
 453                                 gmc_v10_0_flush_gpu_tlb(adev, vmid,
 454                                                 AMDGPU_GFXHUB_0, flush_type);
 455                         }
 456                         break;
 457                 }
 458         }
 459
 460         return 0;
 461 }
 462
 463 static uint64_t gmc_v10_0_emit_flush_gpu_tlb(struct amdgpu_ring *ring,
 464                                              unsigned vmid, uint64_t pd_addr)
 465 {
 466         bool use_semaphore = gmc_v10_0_use_invalidate_semaphore(ring->adev, ring->funcs->vmhub);
 467         struct amdgpu_vmhub *hub = &ring->adev->vmhub[ring->funcs->vmhub];
 468         uint32_t req = hub->vmhub_funcs->get_invalidate_req(vmid, 0);
 469         unsigned eng = ring->vm_inv_eng;
 470
 471         /*
 472          * It may lose gpuvm invalidate acknowldege state across power-gating
 473          * off cycle, add semaphore acquire before invalidation and semaphore
 474          * release after invalidation to avoid entering power gated state
 475          * to WA the Issue
 476          */
 477
 478         /* TODO: It needs to continue working on debugging with semaphore for GFXHUB as well. */
 479         if (use_semaphore)
 480                 /* a read return value of 1 means semaphore acuqire */
 481                 amdgpu_ring_emit_reg_wait(ring,
 482                                           hub->vm_inv_eng0_sem +
 483                                           hub->eng_distance * eng, 0x1, 0x1);
 484
 485         amdgpu_ring_emit_wreg(ring, hub->ctx0_ptb_addr_lo32 +
 486                               (hub->ctx_addr_distance * vmid),
 487                               lower_32_bits(pd_addr));
 488
 489         amdgpu_ring_emit_wreg(ring, hub->ctx0_ptb_addr_hi32 +
 490                               (hub->ctx_addr_distance * vmid),
 491                               upper_32_bits(pd_addr));
 492
 493         amdgpu_ring_emit_reg_write_reg_wait(ring, hub->vm_inv_eng0_req +
 494                                             hub->eng_distance * eng,
 495                                             hub->vm_inv_eng0_ack +
 496                                             hub->eng_distance * eng,
 497                                             req, 1 << vmid);
 498
 499         /* TODO: It needs to continue working on debugging with semaphore for GFXHUB as well. */
 500         if (use_semaphore)
 501                 /*
 502                  * add semaphore release after invalidation,
 503                  * write with 0 means semaphore release
 504                  */
 505                 amdgpu_ring_emit_wreg(ring, hub->vm_inv_eng0_sem +
 506                                       hub->eng_distance * eng, 0);
 507
 508         return pd_addr;
 509 }
 510
 511 static void gmc_v10_0_emit_pasid_mapping(struct amdgpu_ring *ring, unsigned vmid,
 512                                          unsigned pasid)
 513 {
 514         struct amdgpu_device *adev = ring->adev;
 515         uint32_t reg;
 516
 517         if (ring->funcs->vmhub == AMDGPU_GFXHUB_0)
 518                 reg = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_VMID_0_LUT) + vmid;
 519         else
 520                 reg = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_VMID_0_LUT_MM) + vmid;
 521
 522         amdgpu_ring_emit_wreg(ring, reg, pasid);
 523 }
 524
 525 /*
 526  * PTE format on NAVI 10:
 527  * 63:59 reserved
 528  * 58 reserved and for sienna_cichlid is used for MALL noalloc
 529  * 57 reserved
 530  * 56 F
 531  * 55 L
 532  * 54 reserved
 533  * 53:52 SW
 534  * 51 T
 535  * 50:48 mtype
 536  * 47:12 4k physical page base address
 537  * 11:7 fragment
 538  * 6 write
 539  * 5 read
 540  * 4 exe
 541  * 3 Z
 542  * 2 snooped
 543  * 1 system
 544  * 0 valid
 545  *
 546  * PDE format on NAVI 10:
 547  * 63:59 block fragment size
 548  * 58:55 reserved
 549  * 54 P
 550  * 53:48 reserved
 551  * 47:6 physical base address of PD or PTE
 552  * 5:3 reserved
 553  * 2 C
 554  * 1 system
 555  * 0 valid
 556  */
 557
 558 static uint64_t gmc_v10_0_map_mtype(struct amdgpu_device *adev, uint32_t flags)
 559 {
 560         switch (flags) {
 561         case AMDGPU_VM_MTYPE_DEFAULT:
 562                 return AMDGPU_PTE_MTYPE_NV10(MTYPE_NC);
 563         case AMDGPU_VM_MTYPE_NC:
 564                 return AMDGPU_PTE_MTYPE_NV10(MTYPE_NC);
 565         case AMDGPU_VM_MTYPE_WC:
 566                 return AMDGPU_PTE_MTYPE_NV10(MTYPE_WC);
 567         case AMDGPU_VM_MTYPE_CC:
 568                 return AMDGPU_PTE_MTYPE_NV10(MTYPE_CC);
 569         case AMDGPU_VM_MTYPE_UC:
 570                 return AMDGPU_PTE_MTYPE_NV10(MTYPE_UC);
 571         default:
 572                 return AMDGPU_PTE_MTYPE_NV10(MTYPE_NC);
 573         }
 574 }
 575
 576 static void gmc_v10_0_get_vm_pde(struct amdgpu_device *adev, int level,
 577                                  uint64_t *addr, uint64_t *flags)
 578 {
 579         if (!(*flags & AMDGPU_PDE_PTE) && !(*flags & AMDGPU_PTE_SYSTEM))
 580                 *addr = amdgpu_gmc_vram_mc2pa(adev, *addr);
 581         BUG_ON(*addr & 0xFFFF00000000003FULL);
 582
 583         if (!adev->gmc.translate_further)
 584                 return;
 585
 586         if (level == AMDGPU_VM_PDB1) {
 587                 /* Set the block fragment size */
 588                 if (!(*flags & AMDGPU_PDE_PTE))
 589                         *flags |= AMDGPU_PDE_BFS(0x9);
 590
 591         } else if (level == AMDGPU_VM_PDB0) {
 592                 if (*flags & AMDGPU_PDE_PTE)
 593                         *flags &= ~AMDGPU_PDE_PTE;
 594                 else
 595                         *flags |= AMDGPU_PTE_TF;
 596         }
 597 }
 598
 599 static void gmc_v10_0_get_vm_pte(struct amdgpu_device *adev,
 600                                  struct amdgpu_bo_va_mapping *mapping,
 601                                  uint64_t *flags)
 602 {
 603         *flags &= ~AMDGPU_PTE_EXECUTABLE;
 604         *flags |= mapping->flags & AMDGPU_PTE_EXECUTABLE;
 605
 606         *flags &= ~AMDGPU_PTE_MTYPE_NV10_MASK;
 607         *flags |= (mapping->flags & AMDGPU_PTE_MTYPE_NV10_MASK);
 608
 609         if (mapping->flags & AMDGPU_PTE_PRT) {
 610                 *flags |= AMDGPU_PTE_PRT;
 611                 *flags |= AMDGPU_PTE_SNOOPED;
 612                 *flags |= AMDGPU_PTE_LOG;
 613                 *flags |= AMDGPU_PTE_SYSTEM;
 614                 *flags &= ~AMDGPU_PTE_VALID;
 615         }
 616 }
 617
 618 static unsigned gmc_v10_0_get_vbios_fb_size(struct amdgpu_device *adev)
 619 {
 620         u32 d1vga_control = RREG32_SOC15(DCE, 0, mmD1VGA_CONTROL);
 621         unsigned size;
 622
 623         if (REG_GET_FIELD(d1vga_control, D1VGA_CONTROL, D1VGA_MODE_ENABLE)) {
 624                 size = AMDGPU_VBIOS_VGA_ALLOCATION;
 625         } else {
 626                 u32 viewport;
 627                 u32 pitch;
 628
 629                 viewport = RREG32_SOC15(DCE, 0, mmHUBP0_DCSURF_PRI_VIEWPORT_DIMENSION);
 630                 pitch = RREG32_SOC15(DCE, 0, mmHUBPREQ0_DCSURF_SURFACE_PITCH);
 631                 size = (REG_GET_FIELD(viewport,
 632                                         HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION, PRI_VIEWPORT_HEIGHT) *
 633                                 REG_GET_FIELD(pitch, HUBPREQ0_DCSURF_SURFACE_PITCH, PITCH) *
 634                                 4);
 635         }
 636
 637         return size;
 638 }
 639
 640 static const struct amdgpu_gmc_funcs gmc_v10_0_gmc_funcs = {
 641         .flush_gpu_tlb = gmc_v10_0_flush_gpu_tlb,
 642         .flush_gpu_tlb_pasid = gmc_v10_0_flush_gpu_tlb_pasid,
 643         .emit_flush_gpu_tlb = gmc_v10_0_emit_flush_gpu_tlb,
 644         .emit_pasid_mapping = gmc_v10_0_emit_pasid_mapping,
 645         .map_mtype = gmc_v10_0_map_mtype,
 646         .get_vm_pde = gmc_v10_0_get_vm_pde,
 647         .get_vm_pte = gmc_v10_0_get_vm_pte,
 648         .get_vbios_fb_size = gmc_v10_0_get_vbios_fb_size,
 649 };
 650
 651 static void gmc_v10_0_set_gmc_funcs(struct amdgpu_device *adev)
 652 {
 653         if (adev->gmc.gmc_funcs == NULL)
 654                 adev->gmc.gmc_funcs = &gmc_v10_0_gmc_funcs;
 655 }
 656
 657 static void gmc_v10_0_set_umc_funcs(struct amdgpu_device *adev)
 658 {
 659         switch (adev->asic_type) {
 660         case CHIP_SIENNA_CICHLID:
 661                 adev->umc.max_ras_err_cnt_per_query = UMC_V8_7_TOTAL_CHANNEL_NUM;
 662                 adev->umc.channel_inst_num = UMC_V8_7_CHANNEL_INSTANCE_NUM;
 663                 adev->umc.umc_inst_num = UMC_V8_7_UMC_INSTANCE_NUM;
 664                 adev->umc.channel_offs = UMC_V8_7_PER_CHANNEL_OFFSET_SIENNA;
 665                 adev->umc.channel_idx_tbl = &umc_v8_7_channel_idx_tbl[0][0];
 666                 adev->umc.ras_funcs = &umc_v8_7_ras_funcs;
 667                 break;
 668         default:
 669                 break;
 670         }
 671 }
 672
 673
 674 static void gmc_v10_0_set_mmhub_funcs(struct amdgpu_device *adev)
 675 {
 676         switch (adev->asic_type) {
 677         case CHIP_VANGOGH:
 678         case CHIP_YELLOW_CARP:
 679                 adev->mmhub.funcs = &mmhub_v2_3_funcs;
 680                 break;
 681         default:
 682                 adev->mmhub.funcs = &mmhub_v2_0_funcs;
 683                 break;
 684         }
 685 }
 686
 687 static void gmc_v10_0_set_gfxhub_funcs(struct amdgpu_device *adev)
 688 {
 689         switch (adev->asic_type) {
 690         case CHIP_SIENNA_CICHLID:
 691         case CHIP_NAVY_FLOUNDER:
 692         case CHIP_VANGOGH:
 693         case CHIP_DIMGREY_CAVEFISH:
 694         case CHIP_BEIGE_GOBY:
 695         case CHIP_YELLOW_CARP:
 696                 adev->gfxhub.funcs = &gfxhub_v2_1_funcs;
 697                 break;
 698         default:
 699                 adev->gfxhub.funcs = &gfxhub_v2_0_funcs;
 700                 break;
 701         }
 702 }
 703
 704
 705 static int gmc_v10_0_early_init(void *handle)
 706 {
 707         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 708
 709         gmc_v10_0_set_mmhub_funcs(adev);
 710         gmc_v10_0_set_gfxhub_funcs(adev);
 711         gmc_v10_0_set_gmc_funcs(adev);
 712         gmc_v10_0_set_irq_funcs(adev);
 713         gmc_v10_0_set_umc_funcs(adev);
 714
 715         adev->gmc.shared_aperture_start = 0x2000000000000000ULL;
 716         adev->gmc.shared_aperture_end =
 717                 adev->gmc.shared_aperture_start + (4ULL << 30) - 1;
 718         adev->gmc.private_aperture_start = 0x1000000000000000ULL;
 719         adev->gmc.private_aperture_end =
 720                 adev->gmc.private_aperture_start + (4ULL << 30) - 1;
 721
 722         return 0;
 723 }
 724
 725 static int gmc_v10_0_late_init(void *handle)
 726 {
 727         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 728         int r;
 729
 730         r = amdgpu_gmc_allocate_vm_inv_eng(adev);
 731         if (r)
 732                 return r;
 733
 734         r = amdgpu_gmc_ras_late_init(adev);
 735         if (r)
 736                 return r;
 737
 738         return amdgpu_irq_get(adev, &adev->gmc.vm_fault, 0);
 739 }
 740
 741 static void gmc_v10_0_vram_gtt_location(struct amdgpu_device *adev,
 742                                         struct amdgpu_gmc *mc)
 743 {
 744         u64 base = 0;
 745
 746         base = adev->gfxhub.funcs->get_fb_location(adev);
 747
 748         /* add the xgmi offset of the physical node */
 749         base += adev->gmc.xgmi.physical_node_id * adev->gmc.xgmi.node_segment_size;
 750
 751         amdgpu_gmc_vram_location(adev, &adev->gmc, base);
 752         amdgpu_gmc_gart_location(adev, mc);
 753         amdgpu_gmc_agp_location(adev, mc);
 754
 755         /* base offset of vram pages */
 756         adev->vm_manager.vram_base_offset = adev->gfxhub.funcs->get_mc_fb_offset(adev);
 757
 758         /* add the xgmi offset of the physical node */
 759         adev->vm_manager.vram_base_offset +=
 760                 adev->gmc.xgmi.physical_node_id * adev->gmc.xgmi.node_segment_size;
 761 }
 762
 763 /**
 764  * gmc_v10_0_mc_init - initialize the memory controller driver params
 765  *
 766  * @adev: amdgpu_device pointer
 767  *
 768  * Look up the amount of vram, vram width, and decide how to place
 769  * vram and gart within the GPU's physical address space.
 770  * Returns 0 for success.
 771  */
 772 static int gmc_v10_0_mc_init(struct amdgpu_device *adev)
 773 {
 774         int r;
 775
 776         /* size in MB on si */
 777         adev->gmc.mc_vram_size =
 778                 adev->nbio.funcs->get_memsize(adev) * 1024ULL * 1024ULL;
 779         adev->gmc.real_vram_size = adev->gmc.mc_vram_size;
 780
 781         if (!(adev->flags & AMD_IS_APU)) {
 782                 r = amdgpu_device_resize_fb_bar(adev);
 783                 if (r)
 784                         return r;
 785         }
 786         adev->gmc.aper_base = pci_resource_start(adev->pdev, 0);
 787         adev->gmc.aper_size = pci_resource_len(adev->pdev, 0);
 788
 789 #ifdef CONFIG_X86_64
 790         if (adev->flags & AMD_IS_APU) {
 791                 adev->gmc.aper_base = adev->gfxhub.funcs->get_mc_fb_offset(adev);
 792                 adev->gmc.aper_size = adev->gmc.real_vram_size;
 793         }
 794 #endif
 795
 796         /* In case the PCI BAR is larger than the actual amount of vram */
 797         adev->gmc.visible_vram_size = adev->gmc.aper_size;
 798         if (adev->gmc.visible_vram_size > adev->gmc.real_vram_size)
 799                 adev->gmc.visible_vram_size = adev->gmc.real_vram_size;
 800
 801         /* set the gart size */
 802         if (amdgpu_gart_size == -1) {
 803                 switch (adev->asic_type) {
 804                 case CHIP_NAVI10:
 805                 case CHIP_NAVI14:
 806                 case CHIP_NAVI12:
 807                 case CHIP_SIENNA_CICHLID:
 808                 case CHIP_NAVY_FLOUNDER:
 809                 case CHIP_VANGOGH:
 810                 case CHIP_DIMGREY_CAVEFISH:
 811                 case CHIP_BEIGE_GOBY:
 812                 case CHIP_YELLOW_CARP:
 813                 case CHIP_CYAN_SKILLFISH:
 814                 default:
 815                         adev->gmc.gart_size = 512ULL << 20;
 816                         break;
 817                 }
 818         } else
 819                 adev->gmc.gart_size = (u64)amdgpu_gart_size << 20;
 820
 821         gmc_v10_0_vram_gtt_location(adev, &adev->gmc);
 822
 823         return 0;
 824 }
 825
 826 static int gmc_v10_0_gart_init(struct amdgpu_device *adev)
 827 {
 828         int r;
 829
 830         if (adev->gart.bo) {
 831                 WARN(1, "NAVI10 PCIE GART already initialized\n");
 832                 return 0;
 833         }
 834
 835         /* Initialize common gart structure */
 836         r = amdgpu_gart_init(adev);
 837         if (r)
 838                 return r;
 839
 840         adev->gart.table_size = adev->gart.num_gpu_pages * 8;
 841         adev->gart.gart_pte_flags = AMDGPU_PTE_MTYPE_NV10(MTYPE_UC) |
 842                                  AMDGPU_PTE_EXECUTABLE;
 843
 844         return amdgpu_gart_table_vram_alloc(adev);
 845 }
 846
 847 static int gmc_v10_0_sw_init(void *handle)
 848 {
 849         int r, vram_width = 0, vram_type = 0, vram_vendor = 0;
 850         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 851
 852         adev->gfxhub.funcs->init(adev);
 853
 854         adev->mmhub.funcs->init(adev);
 855
 856         spin_lock_init(&adev->gmc.invalidate_lock);
 857
 858         if ((adev->flags & AMD_IS_APU) && amdgpu_emu_mode == 1) {
 859                 adev->gmc.vram_type = AMDGPU_VRAM_TYPE_DDR4;
 860                 adev->gmc.vram_width = 64;
 861         } else if (amdgpu_emu_mode == 1) {
 862                 adev->gmc.vram_type = AMDGPU_VRAM_TYPE_GDDR6;
 863                 adev->gmc.vram_width = 1 * 128; /* numchan * chansize */
 864         } else {
 865                 r = amdgpu_atomfirmware_get_vram_info(adev,
 866                                 &vram_width, &vram_type, &vram_vendor);
 867                 adev->gmc.vram_width = vram_width;
 868
 869                 adev->gmc.vram_type = vram_type;
 870                 adev->gmc.vram_vendor = vram_vendor;
 871         }
 872
 873         switch (adev->asic_type) {
 874         case CHIP_NAVI10:
 875         case CHIP_NAVI14:
 876         case CHIP_NAVI12:
 877         case CHIP_SIENNA_CICHLID:
 878         case CHIP_NAVY_FLOUNDER:
 879         case CHIP_VANGOGH:
 880         case CHIP_DIMGREY_CAVEFISH:
 881         case CHIP_BEIGE_GOBY:
 882         case CHIP_YELLOW_CARP:
 883         case CHIP_CYAN_SKILLFISH:
 884                 adev->num_vmhubs = 2;
 885                 /*
 886                  * To fulfill 4-level page support,
 887                  * vm size is 256TB (48bit), maximum size of Navi10/Navi14/Navi12,
 888                  * block size 512 (9bit)
 889                  */
 890                 amdgpu_vm_adjust_size(adev, 256 * 1024, 9, 3, 48);
 891                 break;
 892         default:
 893                 break;
 894         }
 895
 896         /* This interrupt is VMC page fault.*/
 897         r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_VMC,
 898                               VMC_1_0__SRCID__VM_FAULT,
 899                               &adev->gmc.vm_fault);
 900
 901         if (r)
 902                 return r;
 903
 904         r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_UTCL2,
 905                               UTCL2_1_0__SRCID__FAULT,
 906                               &adev->gmc.vm_fault);
 907         if (r)
 908                 return r;
 909
 910         if (!amdgpu_sriov_vf(adev)) {
 911                 /* interrupt sent to DF. */
 912                 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_DF, 0,
 913                                       &adev->gmc.ecc_irq);
 914                 if (r)
 915                         return r;
 916         }
 917
 918         /*
 919          * Set the internal MC address mask This is the max address of the GPU's
 920          * internal address space.
 921          */
 922         adev->gmc.mc_mask = 0xffffffffffffULL; /* 48 bit MC */
 923
 924         r = dma_set_mask_and_coherent(adev->dev, DMA_BIT_MASK(44));
 925         if (r) {
 926                 printk(KERN_WARNING "amdgpu: No suitable DMA available.\n");
 927                 return r;
 928         }
 929
 930         if (adev->gmc.xgmi.supported) {
 931                 r = adev->gfxhub.funcs->get_xgmi_info(adev);
 932                 if (r)
 933                         return r;
 934         }
 935
 936         r = gmc_v10_0_mc_init(adev);
 937         if (r)
 938                 return r;
 939
 940         amdgpu_gmc_get_vbios_allocations(adev);
 941         amdgpu_gmc_get_reserved_allocation(adev);
 942
 943         /* Memory manager */
 944         r = amdgpu_bo_init(adev);
 945         if (r)
 946                 return r;
 947
 948         r = gmc_v10_0_gart_init(adev);
 949         if (r)
 950                 return r;
 951
 952         /*
 953          * number of VMs
 954          * VMID 0 is reserved for System
 955          * amdgpu graphics/compute will use VMIDs 1-7
 956          * amdkfd will use VMIDs 8-15
 957          */
 958         adev->vm_manager.first_kfd_vmid = 8;
 959
 960         amdgpu_vm_manager_init(adev);
 961
 962         return 0;
 963 }
 964
 965 /**
 966  * gmc_v10_0_gart_fini - vm fini callback
 967  *
 968  * @adev: amdgpu_device pointer
 969  *
 970  * Tears down the driver GART/VM setup (CIK).
 971  */
 972 static void gmc_v10_0_gart_fini(struct amdgpu_device *adev)
 973 {
 974         amdgpu_gart_table_vram_free(adev);
 975 }
 976
 977 static int gmc_v10_0_sw_fini(void *handle)
 978 {
 979         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 980
 981         amdgpu_vm_manager_fini(adev);
 982         gmc_v10_0_gart_fini(adev);
 983         amdgpu_gem_force_release(adev);
 984         amdgpu_bo_fini(adev);
 985
 986         return 0;
 987 }
 988
 989 static void gmc_v10_0_init_golden_registers(struct amdgpu_device *adev)
 990 {
 991         switch (adev->asic_type) {
 992         case CHIP_NAVI10:
 993         case CHIP_NAVI14:
 994         case CHIP_NAVI12:
 995         case CHIP_SIENNA_CICHLID:
 996         case CHIP_NAVY_FLOUNDER:
 997         case CHIP_VANGOGH:
 998         case CHIP_DIMGREY_CAVEFISH:
 999         case CHIP_BEIGE_GOBY:
1000         case CHIP_YELLOW_CARP:
1001         case CHIP_CYAN_SKILLFISH:
1002                 break;
1003         default:
1004                 break;
1005         }
1006 }
1007
1008 /**
1009  * gmc_v10_0_gart_enable - gart enable
1010  *
1011  * @adev: amdgpu_device pointer
1012  */
1013 static int gmc_v10_0_gart_enable(struct amdgpu_device *adev)
1014 {
1015         int r;
1016         bool value;
1017
1018         if (adev->gart.bo == NULL) {
1019                 dev_err(adev->dev, "No VRAM object for PCIE GART.\n");
1020                 return -EINVAL;
1021         }
1022
1023         r = amdgpu_gart_table_vram_pin(adev);
1024         if (r)
1025                 return r;
1026
1027         r = adev->gfxhub.funcs->gart_enable(adev);
1028         if (r)
1029                 return r;
1030
1031         r = adev->mmhub.funcs->gart_enable(adev);
1032         if (r)
1033                 return r;
1034
1035         adev->hdp.funcs->init_registers(adev);
1036
1037         /* Flush HDP after it is initialized */
1038         adev->hdp.funcs->flush_hdp(adev, NULL);
1039
1040         value = (amdgpu_vm_fault_stop == AMDGPU_VM_FAULT_STOP_ALWAYS) ?
1041                 false : true;
1042
1043         adev->gfxhub.funcs->set_fault_enable_default(adev, value);
1044         adev->mmhub.funcs->set_fault_enable_default(adev, value);
1045         gmc_v10_0_flush_gpu_tlb(adev, 0, AMDGPU_MMHUB_0, 0);
1046         gmc_v10_0_flush_gpu_tlb(adev, 0, AMDGPU_GFXHUB_0, 0);
1047
1048         DRM_INFO("PCIE GART of %uM enabled (table at 0x%016llX).\n",
1049                  (unsigned)(adev->gmc.gart_size >> 20),
1050                  (unsigned long long)amdgpu_bo_gpu_offset(adev->gart.bo));
1051
1052         adev->gart.ready = true;
1053
1054         return 0;
1055 }
1056
1057 static int gmc_v10_0_hw_init(void *handle)
1058 {
1059         int r;
1060         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1061
1062         /* The sequence of these two function calls matters.*/
1063         gmc_v10_0_init_golden_registers(adev);
1064
1065         /*
1066          * harvestable groups in gc_utcl2 need to be programmed before any GFX block
1067          * register setup within GMC, or else system hang when harvesting SA.
1068          */
1069         if (adev->gfxhub.funcs && adev->gfxhub.funcs->utcl2_harvest)
1070                 adev->gfxhub.funcs->utcl2_harvest(adev);
1071
1072         r = gmc_v10_0_gart_enable(adev);
1073         if (r)
1074                 return r;
1075
1076         if (adev->umc.funcs && adev->umc.funcs->init_registers)
1077                 adev->umc.funcs->init_registers(adev);
1078
1079         return 0;
1080 }
1081
1082 /**
1083  * gmc_v10_0_gart_disable - gart disable
1084  *
1085  * @adev: amdgpu_device pointer
1086  *
1087  * This disables all VM page table.
1088  */
1089 static void gmc_v10_0_gart_disable(struct amdgpu_device *adev)
1090 {
1091         adev->gfxhub.funcs->gart_disable(adev);
1092         adev->mmhub.funcs->gart_disable(adev);
1093         amdgpu_gart_table_vram_unpin(adev);
1094 }
1095
1096 static int gmc_v10_0_hw_fini(void *handle)
1097 {
1098         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1099
1100         if (amdgpu_sriov_vf(adev)) {
1101                 /* full access mode, so don't touch any GMC register */
1102                 DRM_DEBUG("For SRIOV client, shouldn't do anything.\n");
1103                 return 0;
1104         }
1105
1106         amdgpu_irq_put(adev, &adev->gmc.ecc_irq, 0);
1107         amdgpu_irq_put(adev, &adev->gmc.vm_fault, 0);
1108         gmc_v10_0_gart_disable(adev);
1109
1110         return 0;
1111 }
1112
1113 static int gmc_v10_0_suspend(void *handle)
1114 {
1115         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1116
1117         gmc_v10_0_hw_fini(adev);
1118
1119         return 0;
1120 }
1121
1122 static int gmc_v10_0_resume(void *handle)
1123 {
1124         int r;
1125         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1126
1127         r = gmc_v10_0_hw_init(adev);
1128         if (r)
1129                 return r;
1130
1131         amdgpu_vmid_reset_all(adev);
1132
1133         return 0;
1134 }
1135
1136 static bool gmc_v10_0_is_idle(void *handle)
1137 {
1138         /* MC is always ready in GMC v10.*/
1139         return true;
1140 }
1141
1142 static int gmc_v10_0_wait_for_idle(void *handle)
1143 {
1144         /* There is no need to wait for MC idle in GMC v10.*/
1145         return 0;
1146 }
1147
1148 static int gmc_v10_0_soft_reset(void *handle)
1149 {
1150         return 0;
1151 }
1152
1153 static int gmc_v10_0_set_clockgating_state(void *handle,
1154                                            enum amd_clockgating_state state)
1155 {
1156         int r;
1157         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1158
1159         r = adev->mmhub.funcs->set_clockgating(adev, state);
1160         if (r)
1161                 return r;
1162
1163         if (adev->asic_type >= CHIP_SIENNA_CICHLID &&
1164             adev->asic_type <= CHIP_YELLOW_CARP)
1165                 return athub_v2_1_set_clockgating(adev, state);
1166         else
1167                 return athub_v2_0_set_clockgating(adev, state);
1168 }
1169
1170 static void gmc_v10_0_get_clockgating_state(void *handle, u32 *flags)
1171 {
1172         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1173
1174         adev->mmhub.funcs->get_clockgating(adev, flags);
1175
1176         if (adev->asic_type >= CHIP_SIENNA_CICHLID &&
1177             adev->asic_type <= CHIP_YELLOW_CARP)
1178                 athub_v2_1_get_clockgating(adev, flags);
1179         else
1180                 athub_v2_0_get_clockgating(adev, flags);
1181 }
1182
1183 static int gmc_v10_0_set_powergating_state(void *handle,
1184                                            enum amd_powergating_state state)
1185 {
1186         return 0;
1187 }
1188
1189 const struct amd_ip_funcs gmc_v10_0_ip_funcs = {
1190         .name = "gmc_v10_0",
1191         .early_init = gmc_v10_0_early_init,
1192         .late_init = gmc_v10_0_late_init,
1193         .sw_init = gmc_v10_0_sw_init,
1194         .sw_fini = gmc_v10_0_sw_fini,
1195         .hw_init = gmc_v10_0_hw_init,
1196         .hw_fini = gmc_v10_0_hw_fini,
1197         .suspend = gmc_v10_0_suspend,
1198         .resume = gmc_v10_0_resume,
1199         .is_idle = gmc_v10_0_is_idle,
1200         .wait_for_idle = gmc_v10_0_wait_for_idle,
1201         .soft_reset = gmc_v10_0_soft_reset,
1202         .set_clockgating_state = gmc_v10_0_set_clockgating_state,
1203         .set_powergating_state = gmc_v10_0_set_powergating_state,
1204         .get_clockgating_state = gmc_v10_0_get_clockgating_state,
1205 };
1206
1207 const struct amdgpu_ip_block_version gmc_v10_0_ip_block =
1208 {
1209         .type = AMD_IP_BLOCK_TYPE_GMC,
1210         .major = 10,
1211         .minor = 0,
1212         .rev = 0,
1213         .funcs = &gmc_v10_0_ip_funcs,
1214 };