arch/powerpc/net/bpf_jit.h

   1 /* SPDX-License-Identifier: GPL-2.0-only */
   2 /*
   3  * bpf_jit.h: BPF JIT compiler for PPC
   4  *
   5  * Copyright 2011 Matt Evans <[email protected]>, IBM Corporation
   6  *           2016 Naveen N. Rao <[email protected]>
   7  */
   8 #ifndef _BPF_JIT_H
   9 #define _BPF_JIT_H
  10
  11 #ifndef __ASSEMBLY__
  12
  13 #include <asm/types.h>
  14 #include <asm/ppc-opcode.h>
  15
  16 #ifdef CONFIG_PPC64_ELF_ABI_V1
  17 #define FUNCTION_DESCR_SIZE     24
  18 #else
  19 #define FUNCTION_DESCR_SIZE     0
  20 #endif
  21
  22 #define CTX_NIA(ctx) ((unsigned long)ctx->idx * 4)
  23
  24 #define PLANT_INSTR(d, idx, instr)                                            \
  25         do { if (d) { (d)[idx] = instr; } idx++; } while (0)
  26 #define EMIT(instr)             PLANT_INSTR(image, ctx->idx, instr)
  27
  28 /* Long jump; (unconditional 'branch') */
  29 #define PPC_JMP(dest)                                                         \
  30         do {                                                                  \
  31                 long offset = (long)(dest) - CTX_NIA(ctx);                    \
  32                 if ((dest) != 0 && !is_offset_in_branch_range(offset)) {                      \
  33                         pr_err_ratelimited("Branch offset 0x%lx (@%u) out of range\n", offset, ctx->idx);                       \
  34                         return -ERANGE;                                       \
  35                 }                                                             \
  36                 EMIT(PPC_RAW_BRANCH(offset));                                 \
  37         } while (0)
  38
  39 /* bl (unconditional 'branch' with link) */
  40 #define PPC_BL(dest)    EMIT(PPC_RAW_BL((dest) - (unsigned long)(image + ctx->idx)))
  41
  42 /* "cond" here covers BO:BI fields. */
  43 #define PPC_BCC_SHORT(cond, dest)                                             \
  44         do {                                                                  \
  45                 long offset = (long)(dest) - CTX_NIA(ctx);                    \
  46                 if ((dest) != 0 && !is_offset_in_cond_branch_range(offset)) {                 \
  47                         pr_err_ratelimited("Conditional branch offset 0x%lx (@%u) out of range\n", offset, ctx->idx);           \
  48                         return -ERANGE;                                       \
  49                 }                                                             \
  50                 EMIT(PPC_INST_BRANCH_COND | (((cond) & 0x3ff) << 16) | (offset & 0xfffc));                                      \
  51         } while (0)
  52
  53 /* Sign-extended 32-bit immediate load */
  54 #define PPC_LI32(d, i)          do {                                          \
  55                 if ((int)(uintptr_t)(i) >= -32768 &&                          \
  56                                 (int)(uintptr_t)(i) < 32768)                  \
  57                         EMIT(PPC_RAW_LI(d, i));                               \
  58                 else {                                                        \
  59                         EMIT(PPC_RAW_LIS(d, IMM_H(i)));                       \
  60                         if (IMM_L(i))                                         \
  61                                 EMIT(PPC_RAW_ORI(d, d, IMM_L(i)));            \
  62                 } } while(0)
  63
  64 #ifdef CONFIG_PPC64
  65 #define PPC_LI64(d, i)          do {                                          \
  66                 if ((long)(i) >= -2147483648 &&                               \
  67                                 (long)(i) < 2147483648)                       \
  68                         PPC_LI32(d, i);                                       \
  69                 else {                                                        \
  70                         if (!((uintptr_t)(i) & 0xffff800000000000ULL))        \
  71                                 EMIT(PPC_RAW_LI(d, ((uintptr_t)(i) >> 32) &   \
  72                                                 0xffff));                     \
  73                         else {                                                \
  74                                 EMIT(PPC_RAW_LIS(d, ((uintptr_t)(i) >> 48))); \
  75                                 if ((uintptr_t)(i) & 0x0000ffff00000000ULL)   \
  76                                         EMIT(PPC_RAW_ORI(d, d,                \
  77                                           ((uintptr_t)(i) >> 32) & 0xffff));  \
  78                         }                                                     \
  79                         EMIT(PPC_RAW_SLDI(d, d, 32));                         \
  80                         if ((uintptr_t)(i) & 0x00000000ffff0000ULL)           \
  81                                 EMIT(PPC_RAW_ORIS(d, d,                       \
  82                                          ((uintptr_t)(i) >> 16) & 0xffff));   \
  83                         if ((uintptr_t)(i) & 0x000000000000ffffULL)           \
  84                                 EMIT(PPC_RAW_ORI(d, d, (uintptr_t)(i) &       \
  85                                                         0xffff));             \
  86                 } } while (0)
  87 #endif
  88
  89 /*
  90  * The fly in the ointment of code size changing from pass to pass is
  91  * avoided by padding the short branch case with a NOP.  If code size differs
  92  * with different branch reaches we will have the issue of code moving from
  93  * one pass to the next and will need a few passes to converge on a stable
  94  * state.
  95  */
  96 #define PPC_BCC(cond, dest)     do {                                          \
  97                 if (is_offset_in_cond_branch_range((long)(dest) - CTX_NIA(ctx))) {      \
  98                         PPC_BCC_SHORT(cond, dest);                            \
  99                         EMIT(PPC_RAW_NOP());                                  \
 100                 } else {                                                      \
 101                         /* Flip the 'T or F' bit to invert comparison */      \
 102                         PPC_BCC_SHORT(cond ^ COND_CMP_TRUE, CTX_NIA(ctx) + 2*4);  \
 103                         PPC_JMP(dest);                                        \
 104                 } } while(0)
 105
 106 /* To create a branch condition, select a bit of cr0... */
 107 #define CR0_LT          0
 108 #define CR0_GT          1
 109 #define CR0_EQ          2
 110 /* ...and modify BO[3] */
 111 #define COND_CMP_TRUE   0x100
 112 #define COND_CMP_FALSE  0x000
 113 /* Together, they make all required comparisons: */
 114 #define COND_GT         (CR0_GT | COND_CMP_TRUE)
 115 #define COND_GE         (CR0_LT | COND_CMP_FALSE)
 116 #define COND_EQ         (CR0_EQ | COND_CMP_TRUE)
 117 #define COND_NE         (CR0_EQ | COND_CMP_FALSE)
 118 #define COND_LT         (CR0_LT | COND_CMP_TRUE)
 119 #define COND_LE         (CR0_GT | COND_CMP_FALSE)
 120
 121 #define SEEN_FUNC       0x20000000 /* might call external helpers */
 122 #define SEEN_TAILCALL   0x40000000 /* uses tail calls */
 123
 124 struct codegen_context {
 125         /*
 126          * This is used to track register usage as well
 127          * as calls to external helpers.
 128          * - register usage is tracked with corresponding
 129          *   bits (r3-r31)
 130          * - rest of the bits can be used to track other
 131          *   things -- for now, we use bits 0 to 2
 132          *   encoded in SEEN_* macros above
 133          */
 134         unsigned int seen;
 135         unsigned int idx;
 136         unsigned int stack_size;
 137         int b2p[MAX_BPF_JIT_REG + 2];
 138         unsigned int exentry_idx;
 139         unsigned int alt_exit_addr;
 140 };
 141
 142 #define bpf_to_ppc(r)   (ctx->b2p[r])
 143
 144 #ifdef CONFIG_PPC32
 145 #define BPF_FIXUP_LEN   3 /* Three instructions => 12 bytes */
 146 #else
 147 #define BPF_FIXUP_LEN   2 /* Two instructions => 8 bytes */
 148 #endif
 149
 150 static inline void bpf_flush_icache(void *start, void *end)
 151 {
 152         smp_wmb();      /* smp write barrier */
 153         flush_icache_range((unsigned long)start, (unsigned long)end);
 154 }
 155
 156 static inline bool bpf_is_seen_register(struct codegen_context *ctx, int i)
 157 {
 158         return ctx->seen & (1 << (31 - i));
 159 }
 160
 161 static inline void bpf_set_seen_register(struct codegen_context *ctx, int i)
 162 {
 163         ctx->seen |= 1 << (31 - i);
 164 }
 165
 166 static inline void bpf_clear_seen_register(struct codegen_context *ctx, int i)
 167 {
 168         ctx->seen &= ~(1 << (31 - i));
 169 }
 170
 171 void bpf_jit_init_reg_mapping(struct codegen_context *ctx);
 172 int bpf_jit_emit_func_call_rel(u32 *image, struct codegen_context *ctx, u64 func);
 173 int bpf_jit_build_body(struct bpf_prog *fp, u32 *image, struct codegen_context *ctx,
 174                        u32 *addrs, int pass, bool extra_pass);
 175 void bpf_jit_build_prologue(u32 *image, struct codegen_context *ctx);
 176 void bpf_jit_build_epilogue(u32 *image, struct codegen_context *ctx);
 177 void bpf_jit_realloc_regs(struct codegen_context *ctx);
 178 int bpf_jit_emit_exit_insn(u32 *image, struct codegen_context *ctx, int tmp_reg, long exit_addr);
 179
 180 int bpf_add_extable_entry(struct bpf_prog *fp, u32 *image, int pass, struct codegen_context *ctx,
 181                           int insn_idx, int jmp_off, int dst_reg);
 182
 183 #endif
 184
 185 #endif