drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c

   1 /*
   2  * Copyright 2016 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23 #include "amdgpu.h"
  24 #include "amdgpu_ras.h"
  25 #include "mmhub_v1_0.h"
  26
  27 #include "mmhub/mmhub_1_0_offset.h"
  28 #include "mmhub/mmhub_1_0_sh_mask.h"
  29 #include "mmhub/mmhub_1_0_default.h"
  30 #include "mmhub/mmhub_9_4_0_offset.h"
  31 #include "vega10_enum.h"
  32
  33 #include "soc15_common.h"
  34
  35 #define mmDAGB0_CNTL_MISC2_RV 0x008f
  36 #define mmDAGB0_CNTL_MISC2_RV_BASE_IDX 0
  37
  38 #define EA_EDC_CNT_MASK 0x3
  39 #define EA_EDC_CNT_SHIFT 0x2
  40
  41 u64 mmhub_v1_0_get_fb_location(struct amdgpu_device *adev)
  42 {
  43         u64 base = RREG32_SOC15(MMHUB, 0, mmMC_VM_FB_LOCATION_BASE);
  44         u64 top = RREG32_SOC15(MMHUB, 0, mmMC_VM_FB_LOCATION_TOP);
  45
  46         base &= MC_VM_FB_LOCATION_BASE__FB_BASE_MASK;
  47         base <<= 24;
  48
  49         top &= MC_VM_FB_LOCATION_TOP__FB_TOP_MASK;
  50         top <<= 24;
  51
  52         adev->gmc.fb_start = base;
  53         adev->gmc.fb_end = top;
  54
  55         return base;
  56 }
  57
  58 void mmhub_v1_0_setup_vm_pt_regs(struct amdgpu_device *adev, uint32_t vmid,
  59                                 uint64_t page_table_base)
  60 {
  61         /* two registers distance between mmVM_CONTEXT0_* to mmVM_CONTEXT1_* */
  62         int offset = mmVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32
  63                         - mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32;
  64
  65         WREG32_SOC15_OFFSET(MMHUB, 0, mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32,
  66                         offset * vmid, lower_32_bits(page_table_base));
  67
  68         WREG32_SOC15_OFFSET(MMHUB, 0, mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32,
  69                         offset * vmid, upper_32_bits(page_table_base));
  70 }
  71
  72 static void mmhub_v1_0_init_gart_aperture_regs(struct amdgpu_device *adev)
  73 {
  74         uint64_t pt_base = amdgpu_gmc_pd_addr(adev->gart.bo);
  75
  76         mmhub_v1_0_setup_vm_pt_regs(adev, 0, pt_base);
  77
  78         WREG32_SOC15(MMHUB, 0, mmVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32,
  79                      (u32)(adev->gmc.gart_start >> 12));
  80         WREG32_SOC15(MMHUB, 0, mmVM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32,
  81                      (u32)(adev->gmc.gart_start >> 44));
  82
  83         WREG32_SOC15(MMHUB, 0, mmVM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32,
  84                      (u32)(adev->gmc.gart_end >> 12));
  85         WREG32_SOC15(MMHUB, 0, mmVM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32,
  86                      (u32)(adev->gmc.gart_end >> 44));
  87 }
  88
  89 static void mmhub_v1_0_init_system_aperture_regs(struct amdgpu_device *adev)
  90 {
  91         uint64_t value;
  92         uint32_t tmp;
  93
  94         /* Program the AGP BAR */
  95         WREG32_SOC15(MMHUB, 0, mmMC_VM_AGP_BASE, 0);
  96         WREG32_SOC15(MMHUB, 0, mmMC_VM_AGP_BOT, adev->gmc.agp_start >> 24);
  97         WREG32_SOC15(MMHUB, 0, mmMC_VM_AGP_TOP, adev->gmc.agp_end >> 24);
  98
  99         /* Program the system aperture low logical page number. */
 100         WREG32_SOC15(MMHUB, 0, mmMC_VM_SYSTEM_APERTURE_LOW_ADDR,
 101                      min(adev->gmc.fb_start, adev->gmc.agp_start) >> 18);
 102
 103         if (adev->asic_type == CHIP_RAVEN && adev->rev_id >= 0x8)
 104                 /*
 105                  * Raven2 has a HW issue that it is unable to use the vram which
 106                  * is out of MC_VM_SYSTEM_APERTURE_HIGH_ADDR. So here is the
 107                  * workaround that increase system aperture high address (add 1)
 108                  * to get rid of the VM fault and hardware hang.
 109                  */
 110                 WREG32_SOC15(MMHUB, 0, mmMC_VM_SYSTEM_APERTURE_HIGH_ADDR,
 111                              max((adev->gmc.fb_end >> 18) + 0x1,
 112                                  adev->gmc.agp_end >> 18));
 113         else
 114                 WREG32_SOC15(MMHUB, 0, mmMC_VM_SYSTEM_APERTURE_HIGH_ADDR,
 115                              max(adev->gmc.fb_end, adev->gmc.agp_end) >> 18);
 116
 117         if (amdgpu_sriov_vf(adev))
 118                 return;
 119
 120         /* Set default page address. */
 121         value = adev->vram_scratch.gpu_addr - adev->gmc.vram_start +
 122                 adev->vm_manager.vram_base_offset;
 123         WREG32_SOC15(MMHUB, 0, mmMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB,
 124                      (u32)(value >> 12));
 125         WREG32_SOC15(MMHUB, 0, mmMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB,
 126                      (u32)(value >> 44));
 127
 128         /* Program "protection fault". */
 129         WREG32_SOC15(MMHUB, 0, mmVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32,
 130                      (u32)(adev->dummy_page_addr >> 12));
 131         WREG32_SOC15(MMHUB, 0, mmVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32,
 132                      (u32)((u64)adev->dummy_page_addr >> 44));
 133
 134         tmp = RREG32_SOC15(MMHUB, 0, mmVM_L2_PROTECTION_FAULT_CNTL2);
 135         tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL2,
 136                             ACTIVE_PAGE_MIGRATION_PTE_READ_RETRY, 1);
 137         WREG32_SOC15(MMHUB, 0, mmVM_L2_PROTECTION_FAULT_CNTL2, tmp);
 138 }
 139
 140 static void mmhub_v1_0_init_tlb_regs(struct amdgpu_device *adev)
 141 {
 142         uint32_t tmp;
 143
 144         /* Setup TLB control */
 145         tmp = RREG32_SOC15(MMHUB, 0, mmMC_VM_MX_L1_TLB_CNTL);
 146
 147         tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 1);
 148         tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, SYSTEM_ACCESS_MODE, 3);
 149         tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL,
 150                             ENABLE_ADVANCED_DRIVER_MODEL, 1);
 151         tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL,
 152                             SYSTEM_APERTURE_UNMAPPED_ACCESS, 0);
 153         tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ECO_BITS, 0);
 154         tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL,
 155                             MTYPE, MTYPE_UC);/* XXX for emulation. */
 156         tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ATC_EN, 1);
 157
 158         WREG32_SOC15(MMHUB, 0, mmMC_VM_MX_L1_TLB_CNTL, tmp);
 159 }
 160
 161 static void mmhub_v1_0_init_cache_regs(struct amdgpu_device *adev)
 162 {
 163         uint32_t tmp;
 164
 165         if (amdgpu_sriov_vf(adev))
 166                 return;
 167
 168         /* Setup L2 cache */
 169         tmp = RREG32_SOC15(MMHUB, 0, mmVM_L2_CNTL);
 170         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_CACHE, 1);
 171         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING, 1);
 172         /* XXX for emulation, Refer to closed source code.*/
 173         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, L2_PDE0_CACHE_TAG_GENERATION_MODE,
 174                             0);
 175         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, PDE_FAULT_CLASSIFICATION, 0);
 176         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, CONTEXT1_IDENTITY_ACCESS_MODE, 1);
 177         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, IDENTITY_MODE_FRAGMENT_SIZE, 0);
 178         WREG32_SOC15(MMHUB, 0, mmVM_L2_CNTL, tmp);
 179
 180         tmp = RREG32_SOC15(MMHUB, 0, mmVM_L2_CNTL2);
 181         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL2, INVALIDATE_ALL_L1_TLBS, 1);
 182         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL2, INVALIDATE_L2_CACHE, 1);
 183         WREG32_SOC15(MMHUB, 0, mmVM_L2_CNTL2, tmp);
 184
 185         if (adev->gmc.translate_further) {
 186                 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, BANK_SELECT, 12);
 187                 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3,
 188                                     L2_CACHE_BIGK_FRAGMENT_SIZE, 9);
 189         } else {
 190                 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, BANK_SELECT, 9);
 191                 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3,
 192                                     L2_CACHE_BIGK_FRAGMENT_SIZE, 6);
 193         }
 194         WREG32_SOC15(MMHUB, 0, mmVM_L2_CNTL3, tmp);
 195
 196         tmp = mmVM_L2_CNTL4_DEFAULT;
 197         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_PDE_REQUEST_PHYSICAL, 0);
 198         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_PTE_REQUEST_PHYSICAL, 0);
 199         WREG32_SOC15(MMHUB, 0, mmVM_L2_CNTL4, tmp);
 200 }
 201
 202 static void mmhub_v1_0_enable_system_domain(struct amdgpu_device *adev)
 203 {
 204         uint32_t tmp;
 205
 206         tmp = RREG32_SOC15(MMHUB, 0, mmVM_CONTEXT0_CNTL);
 207         tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, ENABLE_CONTEXT, 1);
 208         tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, PAGE_TABLE_DEPTH, 0);
 209         tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL,
 210                             RETRY_PERMISSION_OR_INVALID_PAGE_FAULT, 0);
 211         WREG32_SOC15(MMHUB, 0, mmVM_CONTEXT0_CNTL, tmp);
 212 }
 213
 214 static void mmhub_v1_0_disable_identity_aperture(struct amdgpu_device *adev)
 215 {
 216         if (amdgpu_sriov_vf(adev))
 217                 return;
 218
 219         WREG32_SOC15(MMHUB, 0, mmVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32,
 220                      0XFFFFFFFF);
 221         WREG32_SOC15(MMHUB, 0, mmVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32,
 222                      0x0000000F);
 223
 224         WREG32_SOC15(MMHUB, 0,
 225                      mmVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_LO32, 0);
 226         WREG32_SOC15(MMHUB, 0,
 227                      mmVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_HI32, 0);
 228
 229         WREG32_SOC15(MMHUB, 0, mmVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_LO32,
 230                      0);
 231         WREG32_SOC15(MMHUB, 0, mmVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_HI32,
 232                      0);
 233 }
 234
 235 static void mmhub_v1_0_setup_vmid_config(struct amdgpu_device *adev)
 236 {
 237         unsigned num_level, block_size;
 238         uint32_t tmp;
 239         int i;
 240
 241         num_level = adev->vm_manager.num_level;
 242         block_size = adev->vm_manager.block_size;
 243         if (adev->gmc.translate_further)
 244                 num_level -= 1;
 245         else
 246                 block_size -= 9;
 247
 248         for (i = 0; i <= 14; i++) {
 249                 tmp = RREG32_SOC15_OFFSET(MMHUB, 0, mmVM_CONTEXT1_CNTL, i);
 250                 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, ENABLE_CONTEXT, 1);
 251                 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, PAGE_TABLE_DEPTH,
 252                                     num_level);
 253                 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
 254                                     RANGE_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
 255                 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
 256                                     DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT,
 257                                     1);
 258                 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
 259                                     PDE0_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
 260                 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
 261                                     VALID_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
 262                 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
 263                                     READ_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
 264                 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
 265                                     WRITE_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
 266                 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
 267                                     EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
 268                 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
 269                                     PAGE_TABLE_BLOCK_SIZE,
 270                                     block_size);
 271                 /* Send no-retry XNACK on fault to suppress VM fault storm. */
 272                 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
 273                                     RETRY_PERMISSION_OR_INVALID_PAGE_FAULT,
 274                                     !amdgpu_noretry);
 275                 WREG32_SOC15_OFFSET(MMHUB, 0, mmVM_CONTEXT1_CNTL, i, tmp);
 276                 WREG32_SOC15_OFFSET(MMHUB, 0, mmVM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32, i*2, 0);
 277                 WREG32_SOC15_OFFSET(MMHUB, 0, mmVM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32, i*2, 0);
 278                 WREG32_SOC15_OFFSET(MMHUB, 0, mmVM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32, i*2,
 279                         lower_32_bits(adev->vm_manager.max_pfn - 1));
 280                 WREG32_SOC15_OFFSET(MMHUB, 0, mmVM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32, i*2,
 281                         upper_32_bits(adev->vm_manager.max_pfn - 1));
 282         }
 283 }
 284
 285 static void mmhub_v1_0_program_invalidation(struct amdgpu_device *adev)
 286 {
 287         unsigned i;
 288
 289         for (i = 0; i < 18; ++i) {
 290                 WREG32_SOC15_OFFSET(MMHUB, 0, mmVM_INVALIDATE_ENG0_ADDR_RANGE_LO32,
 291                                     2 * i, 0xffffffff);
 292                 WREG32_SOC15_OFFSET(MMHUB, 0, mmVM_INVALIDATE_ENG0_ADDR_RANGE_HI32,
 293                                     2 * i, 0x1f);
 294         }
 295 }
 296
 297 void mmhub_v1_0_update_power_gating(struct amdgpu_device *adev,
 298                                 bool enable)
 299 {
 300         if (amdgpu_sriov_vf(adev))
 301                 return;
 302
 303         if (enable && adev->pg_flags & AMD_PG_SUPPORT_MMHUB) {
 304                 if (adev->powerplay.pp_funcs && adev->powerplay.pp_funcs->set_powergating_by_smu)
 305                         amdgpu_dpm_set_powergating_by_smu(adev, AMD_IP_BLOCK_TYPE_GMC, true);
 306
 307         }
 308 }
 309
 310 int mmhub_v1_0_gart_enable(struct amdgpu_device *adev)
 311 {
 312         if (amdgpu_sriov_vf(adev)) {
 313                 /*
 314                  * MC_VM_FB_LOCATION_BASE/TOP is NULL for VF, becuase they are
 315                  * VF copy registers so vbios post doesn't program them, for
 316                  * SRIOV driver need to program them
 317                  */
 318                 WREG32_SOC15(MMHUB, 0, mmMC_VM_FB_LOCATION_BASE,
 319                              adev->gmc.vram_start >> 24);
 320                 WREG32_SOC15(MMHUB, 0, mmMC_VM_FB_LOCATION_TOP,
 321                              adev->gmc.vram_end >> 24);
 322         }
 323
 324         /* GART Enable. */
 325         mmhub_v1_0_init_gart_aperture_regs(adev);
 326         mmhub_v1_0_init_system_aperture_regs(adev);
 327         mmhub_v1_0_init_tlb_regs(adev);
 328         mmhub_v1_0_init_cache_regs(adev);
 329
 330         mmhub_v1_0_enable_system_domain(adev);
 331         mmhub_v1_0_disable_identity_aperture(adev);
 332         mmhub_v1_0_setup_vmid_config(adev);
 333         mmhub_v1_0_program_invalidation(adev);
 334
 335         return 0;
 336 }
 337
 338 void mmhub_v1_0_gart_disable(struct amdgpu_device *adev)
 339 {
 340         u32 tmp;
 341         u32 i;
 342
 343         /* Disable all tables */
 344         for (i = 0; i < 16; i++)
 345                 WREG32_SOC15_OFFSET(MMHUB, 0, mmVM_CONTEXT0_CNTL, i, 0);
 346
 347         /* Setup TLB control */
 348         tmp = RREG32_SOC15(MMHUB, 0, mmMC_VM_MX_L1_TLB_CNTL);
 349         tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 0);
 350         tmp = REG_SET_FIELD(tmp,
 351                                 MC_VM_MX_L1_TLB_CNTL,
 352                                 ENABLE_ADVANCED_DRIVER_MODEL,
 353                                 0);
 354         WREG32_SOC15(MMHUB, 0, mmMC_VM_MX_L1_TLB_CNTL, tmp);
 355
 356         if (!amdgpu_sriov_vf(adev)) {
 357                 /* Setup L2 cache */
 358                 tmp = RREG32_SOC15(MMHUB, 0, mmVM_L2_CNTL);
 359                 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_CACHE, 0);
 360                 WREG32_SOC15(MMHUB, 0, mmVM_L2_CNTL, tmp);
 361                 WREG32_SOC15(MMHUB, 0, mmVM_L2_CNTL3, 0);
 362         }
 363 }
 364
 365 /**
 366  * mmhub_v1_0_set_fault_enable_default - update GART/VM fault handling
 367  *
 368  * @adev: amdgpu_device pointer
 369  * @value: true redirects VM faults to the default page
 370  */
 371 void mmhub_v1_0_set_fault_enable_default(struct amdgpu_device *adev, bool value)
 372 {
 373         u32 tmp;
 374
 375         if (amdgpu_sriov_vf(adev))
 376                 return;
 377
 378         tmp = RREG32_SOC15(MMHUB, 0, mmVM_L2_PROTECTION_FAULT_CNTL);
 379         tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,
 380                         RANGE_PROTECTION_FAULT_ENABLE_DEFAULT, value);
 381         tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,
 382                         PDE0_PROTECTION_FAULT_ENABLE_DEFAULT, value);
 383         tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,
 384                         PDE1_PROTECTION_FAULT_ENABLE_DEFAULT, value);
 385         tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,
 386                         PDE2_PROTECTION_FAULT_ENABLE_DEFAULT, value);
 387         tmp = REG_SET_FIELD(tmp,
 388                         VM_L2_PROTECTION_FAULT_CNTL,
 389                         TRANSLATE_FURTHER_PROTECTION_FAULT_ENABLE_DEFAULT,
 390                         value);
 391         tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,
 392                         NACK_PROTECTION_FAULT_ENABLE_DEFAULT, value);
 393         tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,
 394                         DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT, value);
 395         tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,
 396                         VALID_PROTECTION_FAULT_ENABLE_DEFAULT, value);
 397         tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,
 398                         READ_PROTECTION_FAULT_ENABLE_DEFAULT, value);
 399         tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,
 400                         WRITE_PROTECTION_FAULT_ENABLE_DEFAULT, value);
 401         tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,
 402                         EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT, value);
 403         if (!value) {
 404                 tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,
 405                                 CRASH_ON_NO_RETRY_FAULT, 1);
 406                 tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,
 407                                 CRASH_ON_RETRY_FAULT, 1);
 408     }
 409
 410         WREG32_SOC15(MMHUB, 0, mmVM_L2_PROTECTION_FAULT_CNTL, tmp);
 411 }
 412
 413 void mmhub_v1_0_init(struct amdgpu_device *adev)
 414 {
 415         struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_MMHUB_0];
 416
 417         hub->ctx0_ptb_addr_lo32 =
 418                 SOC15_REG_OFFSET(MMHUB, 0,
 419                                  mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32);
 420         hub->ctx0_ptb_addr_hi32 =
 421                 SOC15_REG_OFFSET(MMHUB, 0,
 422                                  mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32);
 423         hub->vm_inv_eng0_sem =
 424                 SOC15_REG_OFFSET(MMHUB, 0, mmVM_INVALIDATE_ENG0_SEM);
 425         hub->vm_inv_eng0_req =
 426                 SOC15_REG_OFFSET(MMHUB, 0, mmVM_INVALIDATE_ENG0_REQ);
 427         hub->vm_inv_eng0_ack =
 428                 SOC15_REG_OFFSET(MMHUB, 0, mmVM_INVALIDATE_ENG0_ACK);
 429         hub->vm_context0_cntl =
 430                 SOC15_REG_OFFSET(MMHUB, 0, mmVM_CONTEXT0_CNTL);
 431         hub->vm_l2_pro_fault_status =
 432                 SOC15_REG_OFFSET(MMHUB, 0, mmVM_L2_PROTECTION_FAULT_STATUS);
 433         hub->vm_l2_pro_fault_cntl =
 434                 SOC15_REG_OFFSET(MMHUB, 0, mmVM_L2_PROTECTION_FAULT_CNTL);
 435
 436 }
 437
 438 static void mmhub_v1_0_update_medium_grain_clock_gating(struct amdgpu_device *adev,
 439                                                         bool enable)
 440 {
 441         uint32_t def, data, def1, data1, def2 = 0, data2 = 0;
 442
 443         def  = data  = RREG32_SOC15(MMHUB, 0, mmATC_L2_MISC_CG);
 444
 445         if (adev->asic_type != CHIP_RAVEN) {
 446                 def1 = data1 = RREG32_SOC15(MMHUB, 0, mmDAGB0_CNTL_MISC2);
 447                 def2 = data2 = RREG32_SOC15(MMHUB, 0, mmDAGB1_CNTL_MISC2);
 448         } else
 449                 def1 = data1 = RREG32_SOC15(MMHUB, 0, mmDAGB0_CNTL_MISC2_RV);
 450
 451         if (enable && (adev->cg_flags & AMD_CG_SUPPORT_MC_MGCG)) {
 452                 data |= ATC_L2_MISC_CG__ENABLE_MASK;
 453
 454                 data1 &= ~(DAGB0_CNTL_MISC2__DISABLE_WRREQ_CG_MASK |
 455                            DAGB0_CNTL_MISC2__DISABLE_WRRET_CG_MASK |
 456                            DAGB0_CNTL_MISC2__DISABLE_RDREQ_CG_MASK |
 457                            DAGB0_CNTL_MISC2__DISABLE_RDRET_CG_MASK |
 458                            DAGB0_CNTL_MISC2__DISABLE_TLBWR_CG_MASK |
 459                            DAGB0_CNTL_MISC2__DISABLE_TLBRD_CG_MASK);
 460
 461                 if (adev->asic_type != CHIP_RAVEN)
 462                         data2 &= ~(DAGB1_CNTL_MISC2__DISABLE_WRREQ_CG_MASK |
 463                                    DAGB1_CNTL_MISC2__DISABLE_WRRET_CG_MASK |
 464                                    DAGB1_CNTL_MISC2__DISABLE_RDREQ_CG_MASK |
 465                                    DAGB1_CNTL_MISC2__DISABLE_RDRET_CG_MASK |
 466                                    DAGB1_CNTL_MISC2__DISABLE_TLBWR_CG_MASK |
 467                                    DAGB1_CNTL_MISC2__DISABLE_TLBRD_CG_MASK);
 468         } else {
 469                 data &= ~ATC_L2_MISC_CG__ENABLE_MASK;
 470
 471                 data1 |= (DAGB0_CNTL_MISC2__DISABLE_WRREQ_CG_MASK |
 472                           DAGB0_CNTL_MISC2__DISABLE_WRRET_CG_MASK |
 473                           DAGB0_CNTL_MISC2__DISABLE_RDREQ_CG_MASK |
 474                           DAGB0_CNTL_MISC2__DISABLE_RDRET_CG_MASK |
 475                           DAGB0_CNTL_MISC2__DISABLE_TLBWR_CG_MASK |
 476                           DAGB0_CNTL_MISC2__DISABLE_TLBRD_CG_MASK);
 477
 478                 if (adev->asic_type != CHIP_RAVEN)
 479                         data2 |= (DAGB1_CNTL_MISC2__DISABLE_WRREQ_CG_MASK |
 480                                   DAGB1_CNTL_MISC2__DISABLE_WRRET_CG_MASK |
 481                                   DAGB1_CNTL_MISC2__DISABLE_RDREQ_CG_MASK |
 482                                   DAGB1_CNTL_MISC2__DISABLE_RDRET_CG_MASK |
 483                                   DAGB1_CNTL_MISC2__DISABLE_TLBWR_CG_MASK |
 484                                   DAGB1_CNTL_MISC2__DISABLE_TLBRD_CG_MASK);
 485         }
 486
 487         if (def != data)
 488                 WREG32_SOC15(MMHUB, 0, mmATC_L2_MISC_CG, data);
 489
 490         if (def1 != data1) {
 491                 if (adev->asic_type != CHIP_RAVEN)
 492                         WREG32_SOC15(MMHUB, 0, mmDAGB0_CNTL_MISC2, data1);
 493                 else
 494                         WREG32_SOC15(MMHUB, 0, mmDAGB0_CNTL_MISC2_RV, data1);
 495         }
 496
 497         if (adev->asic_type != CHIP_RAVEN && def2 != data2)
 498                 WREG32_SOC15(MMHUB, 0, mmDAGB1_CNTL_MISC2, data2);
 499 }
 500
 501 static void mmhub_v1_0_update_medium_grain_light_sleep(struct amdgpu_device *adev,
 502                                                        bool enable)
 503 {
 504         uint32_t def, data;
 505
 506         def = data = RREG32_SOC15(MMHUB, 0, mmATC_L2_MISC_CG);
 507
 508         if (enable && (adev->cg_flags & AMD_CG_SUPPORT_MC_LS))
 509                 data |= ATC_L2_MISC_CG__MEM_LS_ENABLE_MASK;
 510         else
 511                 data &= ~ATC_L2_MISC_CG__MEM_LS_ENABLE_MASK;
 512
 513         if (def != data)
 514                 WREG32_SOC15(MMHUB, 0, mmATC_L2_MISC_CG, data);
 515 }
 516
 517 int mmhub_v1_0_set_clockgating(struct amdgpu_device *adev,
 518                                enum amd_clockgating_state state)
 519 {
 520         if (amdgpu_sriov_vf(adev))
 521                 return 0;
 522
 523         switch (adev->asic_type) {
 524         case CHIP_VEGA10:
 525         case CHIP_VEGA12:
 526         case CHIP_VEGA20:
 527         case CHIP_RAVEN:
 528         case CHIP_RENOIR:
 529                 mmhub_v1_0_update_medium_grain_clock_gating(adev,
 530                                 state == AMD_CG_STATE_GATE ? true : false);
 531                 mmhub_v1_0_update_medium_grain_light_sleep(adev,
 532                                 state == AMD_CG_STATE_GATE ? true : false);
 533                 break;
 534         default:
 535                 break;
 536         }
 537
 538         return 0;
 539 }
 540
 541 void mmhub_v1_0_get_clockgating(struct amdgpu_device *adev, u32 *flags)
 542 {
 543         int data, data1;
 544
 545         if (amdgpu_sriov_vf(adev))
 546                 *flags = 0;
 547
 548         data = RREG32_SOC15(MMHUB, 0, mmATC_L2_MISC_CG);
 549
 550         data1 = RREG32_SOC15(MMHUB, 0, mmDAGB0_CNTL_MISC2);
 551
 552         /* AMD_CG_SUPPORT_MC_MGCG */
 553         if ((data & ATC_L2_MISC_CG__ENABLE_MASK) &&
 554             !(data1 & (DAGB0_CNTL_MISC2__DISABLE_WRREQ_CG_MASK |
 555                        DAGB0_CNTL_MISC2__DISABLE_WRRET_CG_MASK |
 556                        DAGB0_CNTL_MISC2__DISABLE_RDREQ_CG_MASK |
 557                        DAGB0_CNTL_MISC2__DISABLE_RDRET_CG_MASK |
 558                        DAGB0_CNTL_MISC2__DISABLE_TLBWR_CG_MASK |
 559                        DAGB0_CNTL_MISC2__DISABLE_TLBRD_CG_MASK)))
 560                 *flags |= AMD_CG_SUPPORT_MC_MGCG;
 561
 562         /* AMD_CG_SUPPORT_MC_LS */
 563         if (data & ATC_L2_MISC_CG__MEM_LS_ENABLE_MASK)
 564                 *flags |= AMD_CG_SUPPORT_MC_LS;
 565 }
 566
 567 static void mmhub_v1_0_query_ras_error_count(struct amdgpu_device *adev,
 568                                            void *ras_error_status)
 569 {
 570         int i;
 571         uint32_t ea0_edc_cnt, ea0_edc_cnt2;
 572         uint32_t ea1_edc_cnt, ea1_edc_cnt2;
 573         struct ras_err_data *err_data = (struct ras_err_data *)ras_error_status;
 574
 575         /* EDC CNT will be cleared automatically after read */
 576         ea0_edc_cnt = RREG32_SOC15(MMHUB, 0, mmMMEA0_EDC_CNT_VG20);
 577         ea0_edc_cnt2 = RREG32_SOC15(MMHUB, 0, mmMMEA0_EDC_CNT2_VG20);
 578         ea1_edc_cnt = RREG32_SOC15(MMHUB, 0, mmMMEA1_EDC_CNT_VG20);
 579         ea1_edc_cnt2 = RREG32_SOC15(MMHUB, 0, mmMMEA1_EDC_CNT2_VG20);
 580
 581         /* error count of each error type is recorded by 2 bits,
 582          * ce and ue count in EDC_CNT
 583          */
 584         for (i = 0; i < 5; i++) {
 585                 err_data->ce_count += (ea0_edc_cnt & EA_EDC_CNT_MASK);
 586                 err_data->ce_count += (ea1_edc_cnt & EA_EDC_CNT_MASK);
 587                 ea0_edc_cnt >>= EA_EDC_CNT_SHIFT;
 588                 ea1_edc_cnt >>= EA_EDC_CNT_SHIFT;
 589                 err_data->ue_count += (ea0_edc_cnt & EA_EDC_CNT_MASK);
 590                 err_data->ue_count += (ea1_edc_cnt & EA_EDC_CNT_MASK);
 591                 ea0_edc_cnt >>= EA_EDC_CNT_SHIFT;
 592                 ea1_edc_cnt >>= EA_EDC_CNT_SHIFT;
 593         }
 594         /* successive ue count in EDC_CNT */
 595         for (i = 0; i < 5; i++) {
 596                 err_data->ue_count += (ea0_edc_cnt & EA_EDC_CNT_MASK);
 597                 err_data->ue_count += (ea1_edc_cnt & EA_EDC_CNT_MASK);
 598                 ea0_edc_cnt >>= EA_EDC_CNT_SHIFT;
 599                 ea1_edc_cnt >>= EA_EDC_CNT_SHIFT;
 600         }
 601
 602         /* ce and ue count in EDC_CNT2 */
 603         for (i = 0; i < 3; i++) {
 604                 err_data->ce_count += (ea0_edc_cnt2 & EA_EDC_CNT_MASK);
 605                 err_data->ce_count += (ea1_edc_cnt2 & EA_EDC_CNT_MASK);
 606                 ea0_edc_cnt2 >>= EA_EDC_CNT_SHIFT;
 607                 ea1_edc_cnt2 >>= EA_EDC_CNT_SHIFT;
 608                 err_data->ue_count += (ea0_edc_cnt2 & EA_EDC_CNT_MASK);
 609                 err_data->ue_count += (ea1_edc_cnt2 & EA_EDC_CNT_MASK);
 610                 ea0_edc_cnt2 >>= EA_EDC_CNT_SHIFT;
 611                 ea1_edc_cnt2 >>= EA_EDC_CNT_SHIFT;
 612         }
 613         /* successive ue count in EDC_CNT2 */
 614         for (i = 0; i < 6; i++) {
 615                 err_data->ue_count += (ea0_edc_cnt2 & EA_EDC_CNT_MASK);
 616                 err_data->ue_count += (ea1_edc_cnt2 & EA_EDC_CNT_MASK);
 617                 ea0_edc_cnt2 >>= EA_EDC_CNT_SHIFT;
 618                 ea1_edc_cnt2 >>= EA_EDC_CNT_SHIFT;
 619         }
 620 }
 621
 622 const struct amdgpu_mmhub_funcs mmhub_v1_0_funcs = {
 623         .ras_late_init = amdgpu_mmhub_ras_late_init,
 624         .query_ras_error_count = mmhub_v1_0_query_ras_error_count,
 625 };