drivers/gpu/drm/omapdrm/omap_drv.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * Copyright (C) 2011 Texas Instruments Incorporated - https://www.ti.com/
   4  * Author: Rob Clark <[email protected]>
   5  */
   6
   7 #include <linux/dma-mapping.h>
   8 #include <linux/platform_device.h>
   9 #include <linux/of.h>
  10 #include <linux/sort.h>
  11 #include <linux/sys_soc.h>
  12
  13 #include <drm/drm_atomic.h>
  14 #include <drm/drm_atomic_helper.h>
  15 #include <drm/drm_bridge.h>
  16 #include <drm/drm_bridge_connector.h>
  17 #include <drm/drm_drv.h>
  18 #include <drm/drm_file.h>
  19 #include <drm/drm_ioctl.h>
  20 #include <drm/drm_panel.h>
  21 #include <drm/drm_prime.h>
  22 #include <drm/drm_probe_helper.h>
  23 #include <drm/drm_vblank.h>
  24
  25 #include "omap_dmm_tiler.h"
  26 #include "omap_drv.h"
  27 #include "omap_fbdev.h"
  28
  29 #define DRIVER_NAME             MODULE_NAME
  30 #define DRIVER_DESC             "OMAP DRM"
  31 #define DRIVER_DATE             "20110917"
  32 #define DRIVER_MAJOR            1
  33 #define DRIVER_MINOR            0
  34 #define DRIVER_PATCHLEVEL       0
  35
  36 /*
  37  * mode config funcs
  38  */
  39
  40 /* Notes about mapping DSS and DRM entities:
  41  *    CRTC:        overlay
  42  *    encoder:     manager.. with some extension to allow one primary CRTC
  43  *                 and zero or more video CRTC's to be mapped to one encoder?
  44  *    connector:   dssdev.. manager can be attached/detached from different
  45  *                 devices
  46  */
  47
  48 static void omap_atomic_wait_for_completion(struct drm_device *dev,
  49                                             struct drm_atomic_state *old_state)
  50 {
  51         struct drm_crtc_state *new_crtc_state;
  52         struct drm_crtc *crtc;
  53         unsigned int i;
  54         int ret;
  55
  56         for_each_new_crtc_in_state(old_state, crtc, new_crtc_state, i) {
  57                 if (!new_crtc_state->active)
  58                         continue;
  59
  60                 ret = omap_crtc_wait_pending(crtc);
  61
  62                 if (!ret)
  63                         dev_warn(dev->dev,
  64                                  "atomic complete timeout (pipe %u)!\n", i);
  65         }
  66 }
  67
  68 static void omap_atomic_commit_tail(struct drm_atomic_state *old_state)
  69 {
  70         struct drm_device *dev = old_state->dev;
  71         struct omap_drm_private *priv = dev->dev_private;
  72         bool fence_cookie = dma_fence_begin_signalling();
  73
  74         dispc_runtime_get(priv->dispc);
  75
  76         /* Apply the atomic update. */
  77         drm_atomic_helper_commit_modeset_disables(dev, old_state);
  78
  79         if (priv->omaprev != 0x3430) {
  80                 /* With the current dss dispc implementation we have to enable
  81                  * the new modeset before we can commit planes. The dispc ovl
  82                  * configuration relies on the video mode configuration been
  83                  * written into the HW when the ovl configuration is
  84                  * calculated.
  85                  *
  86                  * This approach is not ideal because after a mode change the
  87                  * plane update is executed only after the first vblank
  88                  * interrupt. The dispc implementation should be fixed so that
  89                  * it is able use uncommitted drm state information.
  90                  */
  91                 drm_atomic_helper_commit_modeset_enables(dev, old_state);
  92                 omap_atomic_wait_for_completion(dev, old_state);
  93
  94                 drm_atomic_helper_commit_planes(dev, old_state, 0);
  95         } else {
  96                 /*
  97                  * OMAP3 DSS seems to have issues with the work-around above,
  98                  * resulting in endless sync losts if a crtc is enabled without
  99                  * a plane. For now, skip the WA for OMAP3.
 100                  */
 101                 drm_atomic_helper_commit_planes(dev, old_state, 0);
 102
 103                 drm_atomic_helper_commit_modeset_enables(dev, old_state);
 104         }
 105
 106         drm_atomic_helper_commit_hw_done(old_state);
 107
 108         dma_fence_end_signalling(fence_cookie);
 109
 110         /*
 111          * Wait for completion of the page flips to ensure that old buffers
 112          * can't be touched by the hardware anymore before cleaning up planes.
 113          */
 114         omap_atomic_wait_for_completion(dev, old_state);
 115
 116         drm_atomic_helper_cleanup_planes(dev, old_state);
 117
 118         dispc_runtime_put(priv->dispc);
 119 }
 120
 121 static int drm_atomic_state_normalized_zpos_cmp(const void *a, const void *b)
 122 {
 123         const struct drm_plane_state *sa = *(struct drm_plane_state **)a;
 124         const struct drm_plane_state *sb = *(struct drm_plane_state **)b;
 125
 126         if (sa->normalized_zpos != sb->normalized_zpos)
 127                 return sa->normalized_zpos - sb->normalized_zpos;
 128         else
 129                 return sa->plane->base.id - sb->plane->base.id;
 130 }
 131
 132 /*
 133  * This replaces the drm_atomic_normalize_zpos to handle the dual overlay case.
 134  *
 135  * Since both halves need to be 'appear' side by side the zpos is
 136  * recalculated when dealing with dual overlay cases so that the other
 137  * planes zpos is consistent.
 138  */
 139 static int omap_atomic_update_normalize_zpos(struct drm_device *dev,
 140                                              struct drm_atomic_state *state)
 141 {
 142         struct drm_crtc *crtc;
 143         struct drm_crtc_state *old_state, *new_state;
 144         struct drm_plane *plane;
 145         int c, i, n, inc;
 146         int total_planes = dev->mode_config.num_total_plane;
 147         struct drm_plane_state **states;
 148         int ret = 0;
 149
 150         states = kmalloc_array(total_planes, sizeof(*states), GFP_KERNEL);
 151         if (!states)
 152                 return -ENOMEM;
 153
 154         for_each_oldnew_crtc_in_state(state, crtc, old_state, new_state, c) {
 155                 if (old_state->plane_mask == new_state->plane_mask &&
 156                     !new_state->zpos_changed)
 157                         continue;
 158
 159                 /* Reset plane increment and index value for every crtc */
 160                 n = 0;
 161
 162                 /*
 163                  * Normalization process might create new states for planes
 164                  * which normalized_zpos has to be recalculated.
 165                  */
 166                 drm_for_each_plane_mask(plane, dev, new_state->plane_mask) {
 167                         struct drm_plane_state *plane_state =
 168                                 drm_atomic_get_plane_state(new_state->state,
 169                                                            plane);
 170                         if (IS_ERR(plane_state)) {
 171                                 ret = PTR_ERR(plane_state);
 172                                 goto done;
 173                         }
 174                         states[n++] = plane_state;
 175                 }
 176
 177                 sort(states, n, sizeof(*states),
 178                      drm_atomic_state_normalized_zpos_cmp, NULL);
 179
 180                 for (i = 0, inc = 0; i < n; i++) {
 181                         plane = states[i]->plane;
 182
 183                         states[i]->normalized_zpos = i + inc;
 184                         DRM_DEBUG_ATOMIC("[PLANE:%d:%s] updated normalized zpos value %d\n",
 185                                          plane->base.id, plane->name,
 186                                          states[i]->normalized_zpos);
 187
 188                         if (is_omap_plane_dual_overlay(states[i]))
 189                                 inc++;
 190                 }
 191                 new_state->zpos_changed = true;
 192         }
 193
 194 done:
 195         kfree(states);
 196         return ret;
 197 }
 198
 199 static int omap_atomic_check(struct drm_device *dev,
 200                              struct drm_atomic_state *state)
 201 {
 202         int ret;
 203
 204         ret = drm_atomic_helper_check(dev, state);
 205         if (ret)
 206                 return ret;
 207
 208         if (dev->mode_config.normalize_zpos) {
 209                 ret = omap_atomic_update_normalize_zpos(dev, state);
 210                 if (ret)
 211                         return ret;
 212         }
 213
 214         return 0;
 215 }
 216
 217 static const struct drm_mode_config_helper_funcs omap_mode_config_helper_funcs = {
 218         .atomic_commit_tail = omap_atomic_commit_tail,
 219 };
 220
 221 static const struct drm_mode_config_funcs omap_mode_config_funcs = {
 222         .fb_create = omap_framebuffer_create,
 223         .atomic_check = omap_atomic_check,
 224         .atomic_commit = drm_atomic_helper_commit,
 225 };
 226
 227 /* Global/shared object state funcs */
 228
 229 /*
 230  * This is a helper that returns the private state currently in operation.
 231  * Note that this would return the "old_state" if called in the atomic check
 232  * path, and the "new_state" after the atomic swap has been done.
 233  */
 234 struct omap_global_state *
 235 omap_get_existing_global_state(struct omap_drm_private *priv)
 236 {
 237         return to_omap_global_state(priv->glob_obj.state);
 238 }
 239
 240 /*
 241  * This acquires the modeset lock set aside for global state, creates
 242  * a new duplicated private object state.
 243  */
 244 struct omap_global_state *__must_check
 245 omap_get_global_state(struct drm_atomic_state *s)
 246 {
 247         struct omap_drm_private *priv = s->dev->dev_private;
 248         struct drm_private_state *priv_state;
 249
 250         priv_state = drm_atomic_get_private_obj_state(s, &priv->glob_obj);
 251         if (IS_ERR(priv_state))
 252                 return ERR_CAST(priv_state);
 253
 254         return to_omap_global_state(priv_state);
 255 }
 256
 257 static struct drm_private_state *
 258 omap_global_duplicate_state(struct drm_private_obj *obj)
 259 {
 260         struct omap_global_state *state;
 261
 262         state = kmemdup(obj->state, sizeof(*state), GFP_KERNEL);
 263         if (!state)
 264                 return NULL;
 265
 266         __drm_atomic_helper_private_obj_duplicate_state(obj, &state->base);
 267
 268         return &state->base;
 269 }
 270
 271 static void omap_global_destroy_state(struct drm_private_obj *obj,
 272                                       struct drm_private_state *state)
 273 {
 274         struct omap_global_state *omap_state = to_omap_global_state(state);
 275
 276         kfree(omap_state);
 277 }
 278
 279 static const struct drm_private_state_funcs omap_global_state_funcs = {
 280         .atomic_duplicate_state = omap_global_duplicate_state,
 281         .atomic_destroy_state = omap_global_destroy_state,
 282 };
 283
 284 static int omap_global_obj_init(struct drm_device *dev)
 285 {
 286         struct omap_drm_private *priv = dev->dev_private;
 287         struct omap_global_state *state;
 288
 289         state = kzalloc(sizeof(*state), GFP_KERNEL);
 290         if (!state)
 291                 return -ENOMEM;
 292
 293         drm_atomic_private_obj_init(dev, &priv->glob_obj, &state->base,
 294                                     &omap_global_state_funcs);
 295         return 0;
 296 }
 297
 298 static void omap_global_obj_fini(struct omap_drm_private *priv)
 299 {
 300         drm_atomic_private_obj_fini(&priv->glob_obj);
 301 }
 302
 303 static void omap_disconnect_pipelines(struct drm_device *ddev)
 304 {
 305         struct omap_drm_private *priv = ddev->dev_private;
 306         unsigned int i;
 307
 308         for (i = 0; i < priv->num_pipes; i++) {
 309                 struct omap_drm_pipeline *pipe = &priv->pipes[i];
 310
 311                 omapdss_device_disconnect(NULL, pipe->output);
 312
 313                 omapdss_device_put(pipe->output);
 314                 pipe->output = NULL;
 315         }
 316
 317         memset(&priv->channels, 0, sizeof(priv->channels));
 318
 319         priv->num_pipes = 0;
 320 }
 321
 322 static int omap_connect_pipelines(struct drm_device *ddev)
 323 {
 324         struct omap_drm_private *priv = ddev->dev_private;
 325         struct omap_dss_device *output = NULL;
 326         int r;
 327
 328         for_each_dss_output(output) {
 329                 r = omapdss_device_connect(priv->dss, NULL, output);
 330                 if (r == -EPROBE_DEFER) {
 331                         omapdss_device_put(output);
 332                         return r;
 333                 } else if (r) {
 334                         dev_warn(output->dev, "could not connect output %s\n",
 335                                  output->name);
 336                 } else {
 337                         struct omap_drm_pipeline *pipe;
 338
 339                         pipe = &priv->pipes[priv->num_pipes++];
 340                         pipe->output = omapdss_device_get(output);
 341
 342                         if (priv->num_pipes == ARRAY_SIZE(priv->pipes)) {
 343                                 /* To balance the 'for_each_dss_output' loop */
 344                                 omapdss_device_put(output);
 345                                 break;
 346                         }
 347                 }
 348         }
 349
 350         return 0;
 351 }
 352
 353 static int omap_compare_pipelines(const void *a, const void *b)
 354 {
 355         const struct omap_drm_pipeline *pipe1 = a;
 356         const struct omap_drm_pipeline *pipe2 = b;
 357
 358         if (pipe1->alias_id > pipe2->alias_id)
 359                 return 1;
 360         else if (pipe1->alias_id < pipe2->alias_id)
 361                 return -1;
 362         return 0;
 363 }
 364
 365 static int omap_modeset_init_properties(struct drm_device *dev)
 366 {
 367         struct omap_drm_private *priv = dev->dev_private;
 368         unsigned int num_planes = dispc_get_num_ovls(priv->dispc);
 369
 370         priv->zorder_prop = drm_property_create_range(dev, 0, "zorder", 0,
 371                                                       num_planes - 1);
 372         if (!priv->zorder_prop)
 373                 return -ENOMEM;
 374
 375         return 0;
 376 }
 377
 378 static int omap_display_id(struct omap_dss_device *output)
 379 {
 380         struct device_node *node = NULL;
 381
 382         if (output->bridge) {
 383                 struct drm_bridge *bridge = output->bridge;
 384
 385                 while (drm_bridge_get_next_bridge(bridge))
 386                         bridge = drm_bridge_get_next_bridge(bridge);
 387
 388                 node = bridge->of_node;
 389         }
 390
 391         return node ? of_alias_get_id(node, "display") : -ENODEV;
 392 }
 393
 394 static int omap_modeset_init(struct drm_device *dev)
 395 {
 396         struct omap_drm_private *priv = dev->dev_private;
 397         int num_ovls = dispc_get_num_ovls(priv->dispc);
 398         int num_mgrs = dispc_get_num_mgrs(priv->dispc);
 399         unsigned int i;
 400         int ret;
 401         u32 plane_crtc_mask;
 402
 403         if (!omapdss_stack_is_ready())
 404                 return -EPROBE_DEFER;
 405
 406         ret = omap_modeset_init_properties(dev);
 407         if (ret < 0)
 408                 return ret;
 409
 410         /*
 411          * This function creates exactly one connector, encoder, crtc,
 412          * and primary plane per each connected dss-device. Each
 413          * connector->encoder->crtc chain is expected to be separate
 414          * and each crtc is connect to a single dss-channel. If the
 415          * configuration does not match the expectations or exceeds
 416          * the available resources, the configuration is rejected.
 417          */
 418         ret = omap_connect_pipelines(dev);
 419         if (ret < 0)
 420                 return ret;
 421
 422         if (priv->num_pipes > num_mgrs || priv->num_pipes > num_ovls) {
 423                 dev_err(dev->dev, "%s(): Too many connected displays\n",
 424                         __func__);
 425                 return -EINVAL;
 426         }
 427
 428         /* Create all planes first. They can all be put to any CRTC. */
 429         plane_crtc_mask = (1 << priv->num_pipes) - 1;
 430
 431         for (i = 0; i < num_ovls; i++) {
 432                 enum drm_plane_type type = i < priv->num_pipes
 433                                          ? DRM_PLANE_TYPE_PRIMARY
 434                                          : DRM_PLANE_TYPE_OVERLAY;
 435                 struct drm_plane *plane;
 436
 437                 if (WARN_ON(priv->num_planes >= ARRAY_SIZE(priv->planes)))
 438                         return -EINVAL;
 439
 440                 plane = omap_plane_init(dev, i, type, plane_crtc_mask);
 441                 if (IS_ERR(plane))
 442                         return PTR_ERR(plane);
 443
 444                 priv->planes[priv->num_planes++] = plane;
 445         }
 446
 447         /*
 448          * Create the encoders, attach the bridges and get the pipeline alias
 449          * IDs.
 450          */
 451         for (i = 0; i < priv->num_pipes; i++) {
 452                 struct omap_drm_pipeline *pipe = &priv->pipes[i];
 453                 int id;
 454
 455                 pipe->encoder = omap_encoder_init(dev, pipe->output);
 456                 if (!pipe->encoder)
 457                         return -ENOMEM;
 458
 459                 if (pipe->output->bridge) {
 460                         ret = drm_bridge_attach(pipe->encoder,
 461                                                 pipe->output->bridge, NULL,
 462                                                 DRM_BRIDGE_ATTACH_NO_CONNECTOR);
 463                         if (ret < 0)
 464                                 return ret;
 465                 }
 466
 467                 id = omap_display_id(pipe->output);
 468                 pipe->alias_id = id >= 0 ? id : i;
 469         }
 470
 471         /* Sort the pipelines by DT aliases. */
 472         sort(priv->pipes, priv->num_pipes, sizeof(priv->pipes[0]),
 473              omap_compare_pipelines, NULL);
 474
 475         /*
 476          * Populate the pipeline lookup table by DISPC channel. Only one display
 477          * is allowed per channel.
 478          */
 479         for (i = 0; i < priv->num_pipes; ++i) {
 480                 struct omap_drm_pipeline *pipe = &priv->pipes[i];
 481                 enum omap_channel channel = pipe->output->dispc_channel;
 482
 483                 if (WARN_ON(priv->channels[channel] != NULL))
 484                         return -EINVAL;
 485
 486                 priv->channels[channel] = pipe;
 487         }
 488
 489         /* Create the connectors and CRTCs. */
 490         for (i = 0; i < priv->num_pipes; i++) {
 491                 struct omap_drm_pipeline *pipe = &priv->pipes[i];
 492                 struct drm_encoder *encoder = pipe->encoder;
 493                 struct drm_crtc *crtc;
 494
 495                 pipe->connector = drm_bridge_connector_init(dev, encoder);
 496                 if (IS_ERR(pipe->connector)) {
 497                         dev_err(priv->dev,
 498                                 "unable to create bridge connector for %s\n",
 499                                 pipe->output->name);
 500                         return PTR_ERR(pipe->connector);
 501                 }
 502
 503                 drm_connector_attach_encoder(pipe->connector, encoder);
 504
 505                 crtc = omap_crtc_init(dev, pipe, priv->planes[i]);
 506                 if (IS_ERR(crtc))
 507                         return PTR_ERR(crtc);
 508
 509                 encoder->possible_crtcs = 1 << i;
 510                 pipe->crtc = crtc;
 511         }
 512
 513         DBG("registered %u planes, %u crtcs/encoders/connectors\n",
 514             priv->num_planes, priv->num_pipes);
 515
 516         dev->mode_config.min_width = 8;
 517         dev->mode_config.min_height = 2;
 518
 519         /*
 520          * Note: these values are used for multiple independent things:
 521          * connector mode filtering, buffer sizes, crtc sizes...
 522          * Use big enough values here to cover all use cases, and do more
 523          * specific checking in the respective code paths.
 524          */
 525         dev->mode_config.max_width = 8192;
 526         dev->mode_config.max_height = 8192;
 527
 528         /* We want the zpos to be normalized */
 529         dev->mode_config.normalize_zpos = true;
 530
 531         dev->mode_config.funcs = &omap_mode_config_funcs;
 532         dev->mode_config.helper_private = &omap_mode_config_helper_funcs;
 533
 534         drm_mode_config_reset(dev);
 535
 536         omap_drm_irq_install(dev);
 537
 538         return 0;
 539 }
 540
 541 static void omap_modeset_fini(struct drm_device *ddev)
 542 {
 543         omap_drm_irq_uninstall(ddev);
 544
 545         drm_mode_config_cleanup(ddev);
 546 }
 547
 548 /*
 549  * drm ioctl funcs
 550  */
 551
 552
 553 static int ioctl_get_param(struct drm_device *dev, void *data,
 554                 struct drm_file *file_priv)
 555 {
 556         struct omap_drm_private *priv = dev->dev_private;
 557         struct drm_omap_param *args = data;
 558
 559         DBG("%p: param=%llu", dev, args->param);
 560
 561         switch (args->param) {
 562         case OMAP_PARAM_CHIPSET_ID:
 563                 args->value = priv->omaprev;
 564                 break;
 565         default:
 566                 DBG("unknown parameter %lld", args->param);
 567                 return -EINVAL;
 568         }
 569
 570         return 0;
 571 }
 572
 573 #define OMAP_BO_USER_MASK       0x00ffffff      /* flags settable by userspace */
 574
 575 static int ioctl_gem_new(struct drm_device *dev, void *data,
 576                 struct drm_file *file_priv)
 577 {
 578         struct drm_omap_gem_new *args = data;
 579         u32 flags = args->flags & OMAP_BO_USER_MASK;
 580
 581         VERB("%p:%p: size=0x%08x, flags=%08x", dev, file_priv,
 582              args->size.bytes, flags);
 583
 584         return omap_gem_new_handle(dev, file_priv, args->size, flags,
 585                                    &args->handle);
 586 }
 587
 588 static int ioctl_gem_info(struct drm_device *dev, void *data,
 589                 struct drm_file *file_priv)
 590 {
 591         struct drm_omap_gem_info *args = data;
 592         struct drm_gem_object *obj;
 593         int ret = 0;
 594
 595         VERB("%p:%p: handle=%d", dev, file_priv, args->handle);
 596
 597         obj = drm_gem_object_lookup(file_priv, args->handle);
 598         if (!obj)
 599                 return -ENOENT;
 600
 601         args->size = omap_gem_mmap_size(obj);
 602         args->offset = omap_gem_mmap_offset(obj);
 603
 604         drm_gem_object_put(obj);
 605
 606         return ret;
 607 }
 608
 609 static const struct drm_ioctl_desc ioctls[DRM_COMMAND_END - DRM_COMMAND_BASE] = {
 610         DRM_IOCTL_DEF_DRV(OMAP_GET_PARAM, ioctl_get_param,
 611                           DRM_RENDER_ALLOW),
 612         DRM_IOCTL_DEF_DRV(OMAP_SET_PARAM, drm_invalid_op,
 613                           DRM_AUTH | DRM_MASTER | DRM_ROOT_ONLY),
 614         DRM_IOCTL_DEF_DRV(OMAP_GEM_NEW, ioctl_gem_new,
 615                           DRM_RENDER_ALLOW),
 616         /* Deprecated, to be removed. */
 617         DRM_IOCTL_DEF_DRV(OMAP_GEM_CPU_PREP, drm_noop,
 618                           DRM_RENDER_ALLOW),
 619         /* Deprecated, to be removed. */
 620         DRM_IOCTL_DEF_DRV(OMAP_GEM_CPU_FINI, drm_noop,
 621                           DRM_RENDER_ALLOW),
 622         DRM_IOCTL_DEF_DRV(OMAP_GEM_INFO, ioctl_gem_info,
 623                           DRM_RENDER_ALLOW),
 624 };
 625
 626 /*
 627  * drm driver funcs
 628  */
 629
 630 static int dev_open(struct drm_device *dev, struct drm_file *file)
 631 {
 632         file->driver_priv = NULL;
 633
 634         DBG("open: dev=%p, file=%p", dev, file);
 635
 636         return 0;
 637 }
 638
 639 DEFINE_DRM_GEM_FOPS(omapdriver_fops);
 640
 641 static const struct drm_driver omap_drm_driver = {
 642         .driver_features = DRIVER_MODESET | DRIVER_GEM  |
 643                 DRIVER_ATOMIC | DRIVER_RENDER,
 644         .open = dev_open,
 645 #ifdef CONFIG_DEBUG_FS
 646         .debugfs_init = omap_debugfs_init,
 647 #endif
 648         .gem_prime_import = omap_gem_prime_import,
 649         .dumb_create = omap_gem_dumb_create,
 650         .dumb_map_offset = omap_gem_dumb_map_offset,
 651         .ioctls = ioctls,
 652         .num_ioctls = DRM_OMAP_NUM_IOCTLS,
 653         .fops = &omapdriver_fops,
 654         .name = DRIVER_NAME,
 655         .desc = DRIVER_DESC,
 656         .date = DRIVER_DATE,
 657         .major = DRIVER_MAJOR,
 658         .minor = DRIVER_MINOR,
 659         .patchlevel = DRIVER_PATCHLEVEL,
 660 };
 661
 662 static const struct soc_device_attribute omapdrm_soc_devices[] = {
 663         { .family = "OMAP3", .data = (void *)0x3430 },
 664         { .family = "OMAP4", .data = (void *)0x4430 },
 665         { .family = "OMAP5", .data = (void *)0x5430 },
 666         { .family = "DRA7",  .data = (void *)0x0752 },
 667         { /* sentinel */ }
 668 };
 669
 670 static int omapdrm_init(struct omap_drm_private *priv, struct device *dev)
 671 {
 672         const struct soc_device_attribute *soc;
 673         struct dss_pdata *pdata = dev->platform_data;
 674         struct drm_device *ddev;
 675         int ret;
 676
 677         DBG("%s", dev_name(dev));
 678
 679         if (drm_firmware_drivers_only())
 680                 return -ENODEV;
 681
 682         /* Allocate and initialize the DRM device. */
 683         ddev = drm_dev_alloc(&omap_drm_driver, dev);
 684         if (IS_ERR(ddev))
 685                 return PTR_ERR(ddev);
 686
 687         priv->ddev = ddev;
 688         ddev->dev_private = priv;
 689
 690         priv->dev = dev;
 691         priv->dss = pdata->dss;
 692         priv->dispc = dispc_get_dispc(priv->dss);
 693
 694         priv->dss->mgr_ops_priv = priv;
 695
 696         soc = soc_device_match(omapdrm_soc_devices);
 697         priv->omaprev = soc ? (uintptr_t)soc->data : 0;
 698         priv->wq = alloc_ordered_workqueue("omapdrm", 0);
 699
 700         mutex_init(&priv->list_lock);
 701         INIT_LIST_HEAD(&priv->obj_list);
 702
 703         /* Get memory bandwidth limits */
 704         priv->max_bandwidth = dispc_get_memory_bandwidth_limit(priv->dispc);
 705
 706         omap_gem_init(ddev);
 707
 708         drm_mode_config_init(ddev);
 709
 710         ret = omap_global_obj_init(ddev);
 711         if (ret)
 712                 goto err_gem_deinit;
 713
 714         ret = omap_hwoverlays_init(priv);
 715         if (ret)
 716                 goto err_free_priv_obj;
 717
 718         ret = omap_modeset_init(ddev);
 719         if (ret) {
 720                 dev_err(priv->dev, "omap_modeset_init failed: ret=%d\n", ret);
 721                 goto err_free_overlays;
 722         }
 723
 724         /* Initialize vblank handling, start with all CRTCs disabled. */
 725         ret = drm_vblank_init(ddev, priv->num_pipes);
 726         if (ret) {
 727                 dev_err(priv->dev, "could not init vblank\n");
 728                 goto err_cleanup_modeset;
 729         }
 730
 731         drm_kms_helper_poll_init(ddev);
 732
 733         /*
 734          * Register the DRM device with the core and the connectors with
 735          * sysfs.
 736          */
 737         ret = drm_dev_register(ddev, 0);
 738         if (ret)
 739                 goto err_cleanup_helpers;
 740
 741         omap_fbdev_setup(ddev);
 742
 743         return 0;
 744
 745 err_cleanup_helpers:
 746         drm_kms_helper_poll_fini(ddev);
 747 err_cleanup_modeset:
 748         omap_modeset_fini(ddev);
 749 err_free_overlays:
 750         omap_hwoverlays_destroy(priv);
 751 err_free_priv_obj:
 752         omap_global_obj_fini(priv);
 753 err_gem_deinit:
 754         drm_mode_config_cleanup(ddev);
 755         omap_gem_deinit(ddev);
 756         destroy_workqueue(priv->wq);
 757         omap_disconnect_pipelines(ddev);
 758         drm_dev_put(ddev);
 759         return ret;
 760 }
 761
 762 static void omapdrm_cleanup(struct omap_drm_private *priv)
 763 {
 764         struct drm_device *ddev = priv->ddev;
 765
 766         DBG("");
 767
 768         drm_dev_unregister(ddev);
 769
 770         drm_kms_helper_poll_fini(ddev);
 771
 772         drm_atomic_helper_shutdown(ddev);
 773
 774         omap_modeset_fini(ddev);
 775         omap_hwoverlays_destroy(priv);
 776         omap_global_obj_fini(priv);
 777         drm_mode_config_cleanup(ddev);
 778         omap_gem_deinit(ddev);
 779
 780         destroy_workqueue(priv->wq);
 781
 782         omap_disconnect_pipelines(ddev);
 783
 784         drm_dev_put(ddev);
 785 }
 786
 787 static int pdev_probe(struct platform_device *pdev)
 788 {
 789         struct omap_drm_private *priv;
 790         int ret;
 791
 792         ret = dma_coerce_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32));
 793         if (ret) {
 794                 dev_err(&pdev->dev, "Failed to set the DMA mask\n");
 795                 return ret;
 796         }
 797
 798         /* Allocate and initialize the driver private structure. */
 799         priv = kzalloc(sizeof(*priv), GFP_KERNEL);
 800         if (!priv)
 801                 return -ENOMEM;
 802
 803         platform_set_drvdata(pdev, priv);
 804
 805         ret = omapdrm_init(priv, &pdev->dev);
 806         if (ret < 0)
 807                 kfree(priv);
 808
 809         return ret;
 810 }
 811
 812 static void pdev_remove(struct platform_device *pdev)
 813 {
 814         struct omap_drm_private *priv = platform_get_drvdata(pdev);
 815
 816         omapdrm_cleanup(priv);
 817         kfree(priv);
 818 }
 819
 820 static void pdev_shutdown(struct platform_device *pdev)
 821 {
 822         struct omap_drm_private *priv = platform_get_drvdata(pdev);
 823
 824         drm_atomic_helper_shutdown(priv->ddev);
 825 }
 826
 827 #ifdef CONFIG_PM_SLEEP
 828 static int omap_drm_suspend(struct device *dev)
 829 {
 830         struct omap_drm_private *priv = dev_get_drvdata(dev);
 831         struct drm_device *drm_dev = priv->ddev;
 832
 833         return drm_mode_config_helper_suspend(drm_dev);
 834 }
 835
 836 static int omap_drm_resume(struct device *dev)
 837 {
 838         struct omap_drm_private *priv = dev_get_drvdata(dev);
 839         struct drm_device *drm_dev = priv->ddev;
 840
 841         drm_mode_config_helper_resume(drm_dev);
 842
 843         return omap_gem_resume(drm_dev);
 844 }
 845 #endif
 846
 847 static SIMPLE_DEV_PM_OPS(omapdrm_pm_ops, omap_drm_suspend, omap_drm_resume);
 848
 849 static struct platform_driver pdev = {
 850         .driver = {
 851                 .name = "omapdrm",
 852                 .pm = &omapdrm_pm_ops,
 853         },
 854         .probe = pdev_probe,
 855         .remove_new = pdev_remove,
 856         .shutdown = pdev_shutdown,
 857 };
 858
 859 static struct platform_driver * const drivers[] = {
 860         &omap_dmm_driver,
 861         &pdev,
 862 };
 863
 864 static int __init omap_drm_init(void)
 865 {
 866         int r;
 867
 868         DBG("init");
 869
 870         r = omap_dss_init();
 871         if (r)
 872                 return r;
 873
 874         r = platform_register_drivers(drivers, ARRAY_SIZE(drivers));
 875         if (r) {
 876                 omap_dss_exit();
 877                 return r;
 878         }
 879
 880         return 0;
 881 }
 882
 883 static void __exit omap_drm_fini(void)
 884 {
 885         DBG("fini");
 886
 887         platform_unregister_drivers(drivers, ARRAY_SIZE(drivers));
 888
 889         omap_dss_exit();
 890 }
 891
 892 module_init(omap_drm_init);
 893 module_exit(omap_drm_fini);
 894
 895 MODULE_AUTHOR("Rob Clark <[email protected]>");
 896 MODULE_AUTHOR("Tomi Valkeinen <[email protected]>");
 897 MODULE_DESCRIPTION("OMAP DRM Display Driver");
 898 MODULE_ALIAS("platform:" DRIVER_NAME);
 899 MODULE_LICENSE("GPL v2");