drivers/gpu/drm/amd/pm/amdgpu_pm.c

   1 /*
   2  * Copyright 2017 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: Rafał Miłecki <[email protected]>
  23  *          Alex Deucher <[email protected]>
  24  */
  25
  26 #include "amdgpu.h"
  27 #include "amdgpu_drv.h"
  28 #include "amdgpu_pm.h"
  29 #include "amdgpu_dpm.h"
  30 #include "atom.h"
  31 #include <linux/pci.h>
  32 #include <linux/hwmon.h>
  33 #include <linux/hwmon-sysfs.h>
  34 #include <linux/nospec.h>
  35 #include <linux/pm_runtime.h>
  36 #include <asm/processor.h>
  37
  38 #define MAX_NUM_OF_FEATURES_PER_SUBSET          8
  39 #define MAX_NUM_OF_SUBSETS                      8
  40
  41 struct od_attribute {
  42         struct kobj_attribute   attribute;
  43         struct list_head        entry;
  44 };
  45
  46 struct od_kobj {
  47         struct kobject          kobj;
  48         struct list_head        entry;
  49         struct list_head        attribute;
  50         void                    *priv;
  51 };
  52
  53 struct od_feature_ops {
  54         umode_t (*is_visible)(struct amdgpu_device *adev);
  55         ssize_t (*show)(struct kobject *kobj, struct kobj_attribute *attr,
  56                         char *buf);
  57         ssize_t (*store)(struct kobject *kobj, struct kobj_attribute *attr,
  58                          const char *buf, size_t count);
  59 };
  60
  61 struct od_feature_item {
  62         const char              *name;
  63         struct od_feature_ops   ops;
  64 };
  65
  66 struct od_feature_container {
  67         char                            *name;
  68         struct od_feature_ops           ops;
  69         struct od_feature_item          sub_feature[MAX_NUM_OF_FEATURES_PER_SUBSET];
  70 };
  71
  72 struct od_feature_set {
  73         struct od_feature_container     containers[MAX_NUM_OF_SUBSETS];
  74 };
  75
  76 static const struct hwmon_temp_label {
  77         enum PP_HWMON_TEMP channel;
  78         const char *label;
  79 } temp_label[] = {
  80         {PP_TEMP_EDGE, "edge"},
  81         {PP_TEMP_JUNCTION, "junction"},
  82         {PP_TEMP_MEM, "mem"},
  83 };
  84
  85 const char * const amdgpu_pp_profile_name[] = {
  86         "BOOTUP_DEFAULT",
  87         "3D_FULL_SCREEN",
  88         "POWER_SAVING",
  89         "VIDEO",
  90         "VR",
  91         "COMPUTE",
  92         "CUSTOM",
  93         "WINDOW_3D",
  94         "CAPPED",
  95         "UNCAPPED",
  96 };
  97
  98 /**
  99  * DOC: power_dpm_state
 100  *
 101  * The power_dpm_state file is a legacy interface and is only provided for
 102  * backwards compatibility. The amdgpu driver provides a sysfs API for adjusting
 103  * certain power related parameters.  The file power_dpm_state is used for this.
 104  * It accepts the following arguments:
 105  *
 106  * - battery
 107  *
 108  * - balanced
 109  *
 110  * - performance
 111  *
 112  * battery
 113  *
 114  * On older GPUs, the vbios provided a special power state for battery
 115  * operation.  Selecting battery switched to this state.  This is no
 116  * longer provided on newer GPUs so the option does nothing in that case.
 117  *
 118  * balanced
 119  *
 120  * On older GPUs, the vbios provided a special power state for balanced
 121  * operation.  Selecting balanced switched to this state.  This is no
 122  * longer provided on newer GPUs so the option does nothing in that case.
 123  *
 124  * performance
 125  *
 126  * On older GPUs, the vbios provided a special power state for performance
 127  * operation.  Selecting performance switched to this state.  This is no
 128  * longer provided on newer GPUs so the option does nothing in that case.
 129  *
 130  */
 131
 132 static ssize_t amdgpu_get_power_dpm_state(struct device *dev,
 133                                           struct device_attribute *attr,
 134                                           char *buf)
 135 {
 136         struct drm_device *ddev = dev_get_drvdata(dev);
 137         struct amdgpu_device *adev = drm_to_adev(ddev);
 138         enum amd_pm_state_type pm;
 139         int ret;
 140
 141         if (amdgpu_in_reset(adev))
 142                 return -EPERM;
 143         if (adev->in_suspend && !adev->in_runpm)
 144                 return -EPERM;
 145
 146         ret = pm_runtime_get_sync(ddev->dev);
 147         if (ret < 0) {
 148                 pm_runtime_put_autosuspend(ddev->dev);
 149                 return ret;
 150         }
 151
 152         amdgpu_dpm_get_current_power_state(adev, &pm);
 153
 154         pm_runtime_mark_last_busy(ddev->dev);
 155         pm_runtime_put_autosuspend(ddev->dev);
 156
 157         return sysfs_emit(buf, "%s\n",
 158                           (pm == POWER_STATE_TYPE_BATTERY) ? "battery" :
 159                           (pm == POWER_STATE_TYPE_BALANCED) ? "balanced" : "performance");
 160 }
 161
 162 static ssize_t amdgpu_set_power_dpm_state(struct device *dev,
 163                                           struct device_attribute *attr,
 164                                           const char *buf,
 165                                           size_t count)
 166 {
 167         struct drm_device *ddev = dev_get_drvdata(dev);
 168         struct amdgpu_device *adev = drm_to_adev(ddev);
 169         enum amd_pm_state_type  state;
 170         int ret;
 171
 172         if (amdgpu_in_reset(adev))
 173                 return -EPERM;
 174         if (adev->in_suspend && !adev->in_runpm)
 175                 return -EPERM;
 176
 177         if (strncmp("battery", buf, strlen("battery")) == 0)
 178                 state = POWER_STATE_TYPE_BATTERY;
 179         else if (strncmp("balanced", buf, strlen("balanced")) == 0)
 180                 state = POWER_STATE_TYPE_BALANCED;
 181         else if (strncmp("performance", buf, strlen("performance")) == 0)
 182                 state = POWER_STATE_TYPE_PERFORMANCE;
 183         else
 184                 return -EINVAL;
 185
 186         ret = pm_runtime_get_sync(ddev->dev);
 187         if (ret < 0) {
 188                 pm_runtime_put_autosuspend(ddev->dev);
 189                 return ret;
 190         }
 191
 192         amdgpu_dpm_set_power_state(adev, state);
 193
 194         pm_runtime_mark_last_busy(ddev->dev);
 195         pm_runtime_put_autosuspend(ddev->dev);
 196
 197         return count;
 198 }
 199
 200
 201 /**
 202  * DOC: power_dpm_force_performance_level
 203  *
 204  * The amdgpu driver provides a sysfs API for adjusting certain power
 205  * related parameters.  The file power_dpm_force_performance_level is
 206  * used for this.  It accepts the following arguments:
 207  *
 208  * - auto
 209  *
 210  * - low
 211  *
 212  * - high
 213  *
 214  * - manual
 215  *
 216  * - profile_standard
 217  *
 218  * - profile_min_sclk
 219  *
 220  * - profile_min_mclk
 221  *
 222  * - profile_peak
 223  *
 224  * auto
 225  *
 226  * When auto is selected, the driver will attempt to dynamically select
 227  * the optimal power profile for current conditions in the driver.
 228  *
 229  * low
 230  *
 231  * When low is selected, the clocks are forced to the lowest power state.
 232  *
 233  * high
 234  *
 235  * When high is selected, the clocks are forced to the highest power state.
 236  *
 237  * manual
 238  *
 239  * When manual is selected, the user can manually adjust which power states
 240  * are enabled for each clock domain via the sysfs pp_dpm_mclk, pp_dpm_sclk,
 241  * and pp_dpm_pcie files and adjust the power state transition heuristics
 242  * via the pp_power_profile_mode sysfs file.
 243  *
 244  * profile_standard
 245  * profile_min_sclk
 246  * profile_min_mclk
 247  * profile_peak
 248  *
 249  * When the profiling modes are selected, clock and power gating are
 250  * disabled and the clocks are set for different profiling cases. This
 251  * mode is recommended for profiling specific work loads where you do
 252  * not want clock or power gating for clock fluctuation to interfere
 253  * with your results. profile_standard sets the clocks to a fixed clock
 254  * level which varies from asic to asic.  profile_min_sclk forces the sclk
 255  * to the lowest level.  profile_min_mclk forces the mclk to the lowest level.
 256  * profile_peak sets all clocks (mclk, sclk, pcie) to the highest levels.
 257  *
 258  */
 259
 260 static ssize_t amdgpu_get_power_dpm_force_performance_level(struct device *dev,
 261                                                             struct device_attribute *attr,
 262                                                             char *buf)
 263 {
 264         struct drm_device *ddev = dev_get_drvdata(dev);
 265         struct amdgpu_device *adev = drm_to_adev(ddev);
 266         enum amd_dpm_forced_level level = 0xff;
 267         int ret;
 268
 269         if (amdgpu_in_reset(adev))
 270                 return -EPERM;
 271         if (adev->in_suspend && !adev->in_runpm)
 272                 return -EPERM;
 273
 274         ret = pm_runtime_get_sync(ddev->dev);
 275         if (ret < 0) {
 276                 pm_runtime_put_autosuspend(ddev->dev);
 277                 return ret;
 278         }
 279
 280         level = amdgpu_dpm_get_performance_level(adev);
 281
 282         pm_runtime_mark_last_busy(ddev->dev);
 283         pm_runtime_put_autosuspend(ddev->dev);
 284
 285         return sysfs_emit(buf, "%s\n",
 286                           (level == AMD_DPM_FORCED_LEVEL_AUTO) ? "auto" :
 287                           (level == AMD_DPM_FORCED_LEVEL_LOW) ? "low" :
 288                           (level == AMD_DPM_FORCED_LEVEL_HIGH) ? "high" :
 289                           (level == AMD_DPM_FORCED_LEVEL_MANUAL) ? "manual" :
 290                           (level == AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD) ? "profile_standard" :
 291                           (level == AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK) ? "profile_min_sclk" :
 292                           (level == AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK) ? "profile_min_mclk" :
 293                           (level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK) ? "profile_peak" :
 294                           (level == AMD_DPM_FORCED_LEVEL_PERF_DETERMINISM) ? "perf_determinism" :
 295                           "unknown");
 296 }
 297
 298 static ssize_t amdgpu_set_power_dpm_force_performance_level(struct device *dev,
 299                                                             struct device_attribute *attr,
 300                                                             const char *buf,
 301                                                             size_t count)
 302 {
 303         struct drm_device *ddev = dev_get_drvdata(dev);
 304         struct amdgpu_device *adev = drm_to_adev(ddev);
 305         enum amd_dpm_forced_level level;
 306         int ret = 0;
 307
 308         if (amdgpu_in_reset(adev))
 309                 return -EPERM;
 310         if (adev->in_suspend && !adev->in_runpm)
 311                 return -EPERM;
 312
 313         if (strncmp("low", buf, strlen("low")) == 0) {
 314                 level = AMD_DPM_FORCED_LEVEL_LOW;
 315         } else if (strncmp("high", buf, strlen("high")) == 0) {
 316                 level = AMD_DPM_FORCED_LEVEL_HIGH;
 317         } else if (strncmp("auto", buf, strlen("auto")) == 0) {
 318                 level = AMD_DPM_FORCED_LEVEL_AUTO;
 319         } else if (strncmp("manual", buf, strlen("manual")) == 0) {
 320                 level = AMD_DPM_FORCED_LEVEL_MANUAL;
 321         } else if (strncmp("profile_exit", buf, strlen("profile_exit")) == 0) {
 322                 level = AMD_DPM_FORCED_LEVEL_PROFILE_EXIT;
 323         } else if (strncmp("profile_standard", buf, strlen("profile_standard")) == 0) {
 324                 level = AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD;
 325         } else if (strncmp("profile_min_sclk", buf, strlen("profile_min_sclk")) == 0) {
 326                 level = AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK;
 327         } else if (strncmp("profile_min_mclk", buf, strlen("profile_min_mclk")) == 0) {
 328                 level = AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK;
 329         } else if (strncmp("profile_peak", buf, strlen("profile_peak")) == 0) {
 330                 level = AMD_DPM_FORCED_LEVEL_PROFILE_PEAK;
 331         } else if (strncmp("perf_determinism", buf, strlen("perf_determinism")) == 0) {
 332                 level = AMD_DPM_FORCED_LEVEL_PERF_DETERMINISM;
 333         }  else {
 334                 return -EINVAL;
 335         }
 336
 337         ret = pm_runtime_get_sync(ddev->dev);
 338         if (ret < 0) {
 339                 pm_runtime_put_autosuspend(ddev->dev);
 340                 return ret;
 341         }
 342
 343         mutex_lock(&adev->pm.stable_pstate_ctx_lock);
 344         if (amdgpu_dpm_force_performance_level(adev, level)) {
 345                 pm_runtime_mark_last_busy(ddev->dev);
 346                 pm_runtime_put_autosuspend(ddev->dev);
 347                 mutex_unlock(&adev->pm.stable_pstate_ctx_lock);
 348                 return -EINVAL;
 349         }
 350         /* override whatever a user ctx may have set */
 351         adev->pm.stable_pstate_ctx = NULL;
 352         mutex_unlock(&adev->pm.stable_pstate_ctx_lock);
 353
 354         pm_runtime_mark_last_busy(ddev->dev);
 355         pm_runtime_put_autosuspend(ddev->dev);
 356
 357         return count;
 358 }
 359
 360 static ssize_t amdgpu_get_pp_num_states(struct device *dev,
 361                 struct device_attribute *attr,
 362                 char *buf)
 363 {
 364         struct drm_device *ddev = dev_get_drvdata(dev);
 365         struct amdgpu_device *adev = drm_to_adev(ddev);
 366         struct pp_states_info data;
 367         uint32_t i;
 368         int buf_len, ret;
 369
 370         if (amdgpu_in_reset(adev))
 371                 return -EPERM;
 372         if (adev->in_suspend && !adev->in_runpm)
 373                 return -EPERM;
 374
 375         ret = pm_runtime_get_sync(ddev->dev);
 376         if (ret < 0) {
 377                 pm_runtime_put_autosuspend(ddev->dev);
 378                 return ret;
 379         }
 380
 381         if (amdgpu_dpm_get_pp_num_states(adev, &data))
 382                 memset(&data, 0, sizeof(data));
 383
 384         pm_runtime_mark_last_busy(ddev->dev);
 385         pm_runtime_put_autosuspend(ddev->dev);
 386
 387         buf_len = sysfs_emit(buf, "states: %d\n", data.nums);
 388         for (i = 0; i < data.nums; i++)
 389                 buf_len += sysfs_emit_at(buf, buf_len, "%d %s\n", i,
 390                                 (data.states[i] == POWER_STATE_TYPE_INTERNAL_BOOT) ? "boot" :
 391                                 (data.states[i] == POWER_STATE_TYPE_BATTERY) ? "battery" :
 392                                 (data.states[i] == POWER_STATE_TYPE_BALANCED) ? "balanced" :
 393                                 (data.states[i] == POWER_STATE_TYPE_PERFORMANCE) ? "performance" : "default");
 394
 395         return buf_len;
 396 }
 397
 398 static ssize_t amdgpu_get_pp_cur_state(struct device *dev,
 399                 struct device_attribute *attr,
 400                 char *buf)
 401 {
 402         struct drm_device *ddev = dev_get_drvdata(dev);
 403         struct amdgpu_device *adev = drm_to_adev(ddev);
 404         struct pp_states_info data = {0};
 405         enum amd_pm_state_type pm = 0;
 406         int i = 0, ret = 0;
 407
 408         if (amdgpu_in_reset(adev))
 409                 return -EPERM;
 410         if (adev->in_suspend && !adev->in_runpm)
 411                 return -EPERM;
 412
 413         ret = pm_runtime_get_sync(ddev->dev);
 414         if (ret < 0) {
 415                 pm_runtime_put_autosuspend(ddev->dev);
 416                 return ret;
 417         }
 418
 419         amdgpu_dpm_get_current_power_state(adev, &pm);
 420
 421         ret = amdgpu_dpm_get_pp_num_states(adev, &data);
 422
 423         pm_runtime_mark_last_busy(ddev->dev);
 424         pm_runtime_put_autosuspend(ddev->dev);
 425
 426         if (ret)
 427                 return ret;
 428
 429         for (i = 0; i < data.nums; i++) {
 430                 if (pm == data.states[i])
 431                         break;
 432         }
 433
 434         if (i == data.nums)
 435                 i = -EINVAL;
 436
 437         return sysfs_emit(buf, "%d\n", i);
 438 }
 439
 440 static ssize_t amdgpu_get_pp_force_state(struct device *dev,
 441                 struct device_attribute *attr,
 442                 char *buf)
 443 {
 444         struct drm_device *ddev = dev_get_drvdata(dev);
 445         struct amdgpu_device *adev = drm_to_adev(ddev);
 446
 447         if (amdgpu_in_reset(adev))
 448                 return -EPERM;
 449         if (adev->in_suspend && !adev->in_runpm)
 450                 return -EPERM;
 451
 452         if (adev->pm.pp_force_state_enabled)
 453                 return amdgpu_get_pp_cur_state(dev, attr, buf);
 454         else
 455                 return sysfs_emit(buf, "\n");
 456 }
 457
 458 static ssize_t amdgpu_set_pp_force_state(struct device *dev,
 459                 struct device_attribute *attr,
 460                 const char *buf,
 461                 size_t count)
 462 {
 463         struct drm_device *ddev = dev_get_drvdata(dev);
 464         struct amdgpu_device *adev = drm_to_adev(ddev);
 465         enum amd_pm_state_type state = 0;
 466         struct pp_states_info data;
 467         unsigned long idx;
 468         int ret;
 469
 470         if (amdgpu_in_reset(adev))
 471                 return -EPERM;
 472         if (adev->in_suspend && !adev->in_runpm)
 473                 return -EPERM;
 474
 475         adev->pm.pp_force_state_enabled = false;
 476
 477         if (strlen(buf) == 1)
 478                 return count;
 479
 480         ret = kstrtoul(buf, 0, &idx);
 481         if (ret || idx >= ARRAY_SIZE(data.states))
 482                 return -EINVAL;
 483
 484         idx = array_index_nospec(idx, ARRAY_SIZE(data.states));
 485
 486         ret = pm_runtime_get_sync(ddev->dev);
 487         if (ret < 0) {
 488                 pm_runtime_put_autosuspend(ddev->dev);
 489                 return ret;
 490         }
 491
 492         ret = amdgpu_dpm_get_pp_num_states(adev, &data);
 493         if (ret)
 494                 goto err_out;
 495
 496         state = data.states[idx];
 497
 498         /* only set user selected power states */
 499         if (state != POWER_STATE_TYPE_INTERNAL_BOOT &&
 500             state != POWER_STATE_TYPE_DEFAULT) {
 501                 ret = amdgpu_dpm_dispatch_task(adev,
 502                                 AMD_PP_TASK_ENABLE_USER_STATE, &state);
 503                 if (ret)
 504                         goto err_out;
 505
 506                 adev->pm.pp_force_state_enabled = true;
 507         }
 508
 509         pm_runtime_mark_last_busy(ddev->dev);
 510         pm_runtime_put_autosuspend(ddev->dev);
 511
 512         return count;
 513
 514 err_out:
 515         pm_runtime_mark_last_busy(ddev->dev);
 516         pm_runtime_put_autosuspend(ddev->dev);
 517         return ret;
 518 }
 519
 520 /**
 521  * DOC: pp_table
 522  *
 523  * The amdgpu driver provides a sysfs API for uploading new powerplay
 524  * tables.  The file pp_table is used for this.  Reading the file
 525  * will dump the current power play table.  Writing to the file
 526  * will attempt to upload a new powerplay table and re-initialize
 527  * powerplay using that new table.
 528  *
 529  */
 530
 531 static ssize_t amdgpu_get_pp_table(struct device *dev,
 532                 struct device_attribute *attr,
 533                 char *buf)
 534 {
 535         struct drm_device *ddev = dev_get_drvdata(dev);
 536         struct amdgpu_device *adev = drm_to_adev(ddev);
 537         char *table = NULL;
 538         int size, ret;
 539
 540         if (amdgpu_in_reset(adev))
 541                 return -EPERM;
 542         if (adev->in_suspend && !adev->in_runpm)
 543                 return -EPERM;
 544
 545         ret = pm_runtime_get_sync(ddev->dev);
 546         if (ret < 0) {
 547                 pm_runtime_put_autosuspend(ddev->dev);
 548                 return ret;
 549         }
 550
 551         size = amdgpu_dpm_get_pp_table(adev, &table);
 552
 553         pm_runtime_mark_last_busy(ddev->dev);
 554         pm_runtime_put_autosuspend(ddev->dev);
 555
 556         if (size <= 0)
 557                 return size;
 558
 559         if (size >= PAGE_SIZE)
 560                 size = PAGE_SIZE - 1;
 561
 562         memcpy(buf, table, size);
 563
 564         return size;
 565 }
 566
 567 static ssize_t amdgpu_set_pp_table(struct device *dev,
 568                 struct device_attribute *attr,
 569                 const char *buf,
 570                 size_t count)
 571 {
 572         struct drm_device *ddev = dev_get_drvdata(dev);
 573         struct amdgpu_device *adev = drm_to_adev(ddev);
 574         int ret = 0;
 575
 576         if (amdgpu_in_reset(adev))
 577                 return -EPERM;
 578         if (adev->in_suspend && !adev->in_runpm)
 579                 return -EPERM;
 580
 581         ret = pm_runtime_get_sync(ddev->dev);
 582         if (ret < 0) {
 583                 pm_runtime_put_autosuspend(ddev->dev);
 584                 return ret;
 585         }
 586
 587         ret = amdgpu_dpm_set_pp_table(adev, buf, count);
 588
 589         pm_runtime_mark_last_busy(ddev->dev);
 590         pm_runtime_put_autosuspend(ddev->dev);
 591
 592         if (ret)
 593                 return ret;
 594
 595         return count;
 596 }
 597
 598 /**
 599  * DOC: pp_od_clk_voltage
 600  *
 601  * The amdgpu driver provides a sysfs API for adjusting the clocks and voltages
 602  * in each power level within a power state.  The pp_od_clk_voltage is used for
 603  * this.
 604  *
 605  * Note that the actual memory controller clock rate are exposed, not
 606  * the effective memory clock of the DRAMs. To translate it, use the
 607  * following formula:
 608  *
 609  * Clock conversion (Mhz):
 610  *
 611  * HBM: effective_memory_clock = memory_controller_clock * 1
 612  *
 613  * G5: effective_memory_clock = memory_controller_clock * 1
 614  *
 615  * G6: effective_memory_clock = memory_controller_clock * 2
 616  *
 617  * DRAM data rate (MT/s):
 618  *
 619  * HBM: effective_memory_clock * 2 = data_rate
 620  *
 621  * G5: effective_memory_clock * 4 = data_rate
 622  *
 623  * G6: effective_memory_clock * 8 = data_rate
 624  *
 625  * Bandwidth (MB/s):
 626  *
 627  * data_rate * vram_bit_width / 8 = memory_bandwidth
 628  *
 629  * Some examples:
 630  *
 631  * G5 on RX460:
 632  *
 633  * memory_controller_clock = 1750 Mhz
 634  *
 635  * effective_memory_clock = 1750 Mhz * 1 = 1750 Mhz
 636  *
 637  * data rate = 1750 * 4 = 7000 MT/s
 638  *
 639  * memory_bandwidth = 7000 * 128 bits / 8 = 112000 MB/s
 640  *
 641  * G6 on RX5700:
 642  *
 643  * memory_controller_clock = 875 Mhz
 644  *
 645  * effective_memory_clock = 875 Mhz * 2 = 1750 Mhz
 646  *
 647  * data rate = 1750 * 8 = 14000 MT/s
 648  *
 649  * memory_bandwidth = 14000 * 256 bits / 8 = 448000 MB/s
 650  *
 651  * < For Vega10 and previous ASICs >
 652  *
 653  * Reading the file will display:
 654  *
 655  * - a list of engine clock levels and voltages labeled OD_SCLK
 656  *
 657  * - a list of memory clock levels and voltages labeled OD_MCLK
 658  *
 659  * - a list of valid ranges for sclk, mclk, and voltage labeled OD_RANGE
 660  *
 661  * To manually adjust these settings, first select manual using
 662  * power_dpm_force_performance_level. Enter a new value for each
 663  * level by writing a string that contains "s/m level clock voltage" to
 664  * the file.  E.g., "s 1 500 820" will update sclk level 1 to be 500 MHz
 665  * at 820 mV; "m 0 350 810" will update mclk level 0 to be 350 MHz at
 666  * 810 mV.  When you have edited all of the states as needed, write
 667  * "c" (commit) to the file to commit your changes.  If you want to reset to the
 668  * default power levels, write "r" (reset) to the file to reset them.
 669  *
 670  *
 671  * < For Vega20 and newer ASICs >
 672  *
 673  * Reading the file will display:
 674  *
 675  * - minimum and maximum engine clock labeled OD_SCLK
 676  *
 677  * - minimum(not available for Vega20 and Navi1x) and maximum memory
 678  *   clock labeled OD_MCLK
 679  *
 680  * - three <frequency, voltage> points labeled OD_VDDC_CURVE.
 681  *   They can be used to calibrate the sclk voltage curve. This is
 682  *   available for Vega20 and NV1X.
 683  *
 684  * - voltage offset(in mV) applied on target voltage calculation.
 685  *   This is available for Sienna Cichlid, Navy Flounder, Dimgrey
 686  *   Cavefish and some later SMU13 ASICs. For these ASICs, the target
 687  *   voltage calculation can be illustrated by "voltage = voltage
 688  *   calculated from v/f curve + overdrive vddgfx offset"
 689  *
 690  * - a list of valid ranges for sclk, mclk, voltage curve points
 691  *   or voltage offset labeled OD_RANGE
 692  *
 693  * < For APUs >
 694  *
 695  * Reading the file will display:
 696  *
 697  * - minimum and maximum engine clock labeled OD_SCLK
 698  *
 699  * - a list of valid ranges for sclk labeled OD_RANGE
 700  *
 701  * < For VanGogh >
 702  *
 703  * Reading the file will display:
 704  *
 705  * - minimum and maximum engine clock labeled OD_SCLK
 706  * - minimum and maximum core clocks labeled OD_CCLK
 707  *
 708  * - a list of valid ranges for sclk and cclk labeled OD_RANGE
 709  *
 710  * To manually adjust these settings:
 711  *
 712  * - First select manual using power_dpm_force_performance_level
 713  *
 714  * - For clock frequency setting, enter a new value by writing a
 715  *   string that contains "s/m index clock" to the file. The index
 716  *   should be 0 if to set minimum clock. And 1 if to set maximum
 717  *   clock. E.g., "s 0 500" will update minimum sclk to be 500 MHz.
 718  *   "m 1 800" will update maximum mclk to be 800Mhz. For core
 719  *   clocks on VanGogh, the string contains "p core index clock".
 720  *   E.g., "p 2 0 800" would set the minimum core clock on core
 721  *   2 to 800Mhz.
 722  *
 723  *   For sclk voltage curve supported by Vega20 and NV1X, enter the new
 724  *   values by writing a string that contains "vc point clock voltage"
 725  *   to the file. The points are indexed by 0, 1 and 2. E.g., "vc 0 300
 726  *   600" will update point1 with clock set as 300Mhz and voltage as 600mV.
 727  *   "vc 2 1000 1000" will update point3 with clock set as 1000Mhz and
 728  *   voltage 1000mV.
 729  *
 730  *   For voltage offset supported by Sienna Cichlid, Navy Flounder, Dimgrey
 731  *   Cavefish and some later SMU13 ASICs, enter the new value by writing a
 732  *   string that contains "vo offset". E.g., "vo -10" will update the extra
 733  *   voltage offset applied to the whole v/f curve line as -10mv.
 734  *
 735  * - When you have edited all of the states as needed, write "c" (commit)
 736  *   to the file to commit your changes
 737  *
 738  * - If you want to reset to the default power levels, write "r" (reset)
 739  *   to the file to reset them
 740  *
 741  */
 742
 743 static ssize_t amdgpu_set_pp_od_clk_voltage(struct device *dev,
 744                 struct device_attribute *attr,
 745                 const char *buf,
 746                 size_t count)
 747 {
 748         struct drm_device *ddev = dev_get_drvdata(dev);
 749         struct amdgpu_device *adev = drm_to_adev(ddev);
 750         int ret;
 751         uint32_t parameter_size = 0;
 752         long parameter[64];
 753         char buf_cpy[128];
 754         char *tmp_str;
 755         char *sub_str;
 756         const char delimiter[3] = {' ', '\n', '\0'};
 757         uint32_t type;
 758
 759         if (amdgpu_in_reset(adev))
 760                 return -EPERM;
 761         if (adev->in_suspend && !adev->in_runpm)
 762                 return -EPERM;
 763
 764         if (count > 127 || count == 0)
 765                 return -EINVAL;
 766
 767         if (*buf == 's')
 768                 type = PP_OD_EDIT_SCLK_VDDC_TABLE;
 769         else if (*buf == 'p')
 770                 type = PP_OD_EDIT_CCLK_VDDC_TABLE;
 771         else if (*buf == 'm')
 772                 type = PP_OD_EDIT_MCLK_VDDC_TABLE;
 773         else if (*buf == 'r')
 774                 type = PP_OD_RESTORE_DEFAULT_TABLE;
 775         else if (*buf == 'c')
 776                 type = PP_OD_COMMIT_DPM_TABLE;
 777         else if (!strncmp(buf, "vc", 2))
 778                 type = PP_OD_EDIT_VDDC_CURVE;
 779         else if (!strncmp(buf, "vo", 2))
 780                 type = PP_OD_EDIT_VDDGFX_OFFSET;
 781         else
 782                 return -EINVAL;
 783
 784         memcpy(buf_cpy, buf, count);
 785         buf_cpy[count] = 0;
 786
 787         tmp_str = buf_cpy;
 788
 789         if ((type == PP_OD_EDIT_VDDC_CURVE) ||
 790              (type == PP_OD_EDIT_VDDGFX_OFFSET))
 791                 tmp_str++;
 792         while (isspace(*++tmp_str));
 793
 794         while ((sub_str = strsep(&tmp_str, delimiter)) != NULL) {
 795                 if (strlen(sub_str) == 0)
 796                         continue;
 797                 ret = kstrtol(sub_str, 0, &parameter[parameter_size]);
 798                 if (ret)
 799                         return -EINVAL;
 800                 parameter_size++;
 801
 802                 if (!tmp_str)
 803                         break;
 804
 805                 while (isspace(*tmp_str))
 806                         tmp_str++;
 807         }
 808
 809         ret = pm_runtime_get_sync(ddev->dev);
 810         if (ret < 0) {
 811                 pm_runtime_put_autosuspend(ddev->dev);
 812                 return ret;
 813         }
 814
 815         if (amdgpu_dpm_set_fine_grain_clk_vol(adev,
 816                                               type,
 817                                               parameter,
 818                                               parameter_size))
 819                 goto err_out;
 820
 821         if (amdgpu_dpm_odn_edit_dpm_table(adev, type,
 822                                           parameter, parameter_size))
 823                 goto err_out;
 824
 825         if (type == PP_OD_COMMIT_DPM_TABLE) {
 826                 if (amdgpu_dpm_dispatch_task(adev,
 827                                              AMD_PP_TASK_READJUST_POWER_STATE,
 828                                              NULL))
 829                         goto err_out;
 830         }
 831
 832         pm_runtime_mark_last_busy(ddev->dev);
 833         pm_runtime_put_autosuspend(ddev->dev);
 834
 835         return count;
 836
 837 err_out:
 838         pm_runtime_mark_last_busy(ddev->dev);
 839         pm_runtime_put_autosuspend(ddev->dev);
 840         return -EINVAL;
 841 }
 842
 843 static ssize_t amdgpu_get_pp_od_clk_voltage(struct device *dev,
 844                 struct device_attribute *attr,
 845                 char *buf)
 846 {
 847         struct drm_device *ddev = dev_get_drvdata(dev);
 848         struct amdgpu_device *adev = drm_to_adev(ddev);
 849         int size = 0;
 850         int ret;
 851         enum pp_clock_type od_clocks[6] = {
 852                 OD_SCLK,
 853                 OD_MCLK,
 854                 OD_VDDC_CURVE,
 855                 OD_RANGE,
 856                 OD_VDDGFX_OFFSET,
 857                 OD_CCLK,
 858         };
 859         uint clk_index;
 860
 861         if (amdgpu_in_reset(adev))
 862                 return -EPERM;
 863         if (adev->in_suspend && !adev->in_runpm)
 864                 return -EPERM;
 865
 866         ret = pm_runtime_get_sync(ddev->dev);
 867         if (ret < 0) {
 868                 pm_runtime_put_autosuspend(ddev->dev);
 869                 return ret;
 870         }
 871
 872         for (clk_index = 0 ; clk_index < 6 ; clk_index++) {
 873                 ret = amdgpu_dpm_emit_clock_levels(adev, od_clocks[clk_index], buf, &size);
 874                 if (ret)
 875                         break;
 876         }
 877         if (ret == -ENOENT) {
 878                 size = amdgpu_dpm_print_clock_levels(adev, OD_SCLK, buf);
 879                 size += amdgpu_dpm_print_clock_levels(adev, OD_MCLK, buf + size);
 880                 size += amdgpu_dpm_print_clock_levels(adev, OD_VDDC_CURVE, buf + size);
 881                 size += amdgpu_dpm_print_clock_levels(adev, OD_VDDGFX_OFFSET, buf + size);
 882                 size += amdgpu_dpm_print_clock_levels(adev, OD_RANGE, buf + size);
 883                 size += amdgpu_dpm_print_clock_levels(adev, OD_CCLK, buf + size);
 884         }
 885
 886         if (size == 0)
 887                 size = sysfs_emit(buf, "\n");
 888
 889         pm_runtime_mark_last_busy(ddev->dev);
 890         pm_runtime_put_autosuspend(ddev->dev);
 891
 892         return size;
 893 }
 894
 895 /**
 896  * DOC: pp_features
 897  *
 898  * The amdgpu driver provides a sysfs API for adjusting what powerplay
 899  * features to be enabled. The file pp_features is used for this. And
 900  * this is only available for Vega10 and later dGPUs.
 901  *
 902  * Reading back the file will show you the followings:
 903  * - Current ppfeature masks
 904  * - List of the all supported powerplay features with their naming,
 905  *   bitmasks and enablement status('Y'/'N' means "enabled"/"disabled").
 906  *
 907  * To manually enable or disable a specific feature, just set or clear
 908  * the corresponding bit from original ppfeature masks and input the
 909  * new ppfeature masks.
 910  */
 911 static ssize_t amdgpu_set_pp_features(struct device *dev,
 912                                       struct device_attribute *attr,
 913                                       const char *buf,
 914                                       size_t count)
 915 {
 916         struct drm_device *ddev = dev_get_drvdata(dev);
 917         struct amdgpu_device *adev = drm_to_adev(ddev);
 918         uint64_t featuremask;
 919         int ret;
 920
 921         if (amdgpu_in_reset(adev))
 922                 return -EPERM;
 923         if (adev->in_suspend && !adev->in_runpm)
 924                 return -EPERM;
 925
 926         ret = kstrtou64(buf, 0, &featuremask);
 927         if (ret)
 928                 return -EINVAL;
 929
 930         ret = pm_runtime_get_sync(ddev->dev);
 931         if (ret < 0) {
 932                 pm_runtime_put_autosuspend(ddev->dev);
 933                 return ret;
 934         }
 935
 936         ret = amdgpu_dpm_set_ppfeature_status(adev, featuremask);
 937
 938         pm_runtime_mark_last_busy(ddev->dev);
 939         pm_runtime_put_autosuspend(ddev->dev);
 940
 941         if (ret)
 942                 return -EINVAL;
 943
 944         return count;
 945 }
 946
 947 static ssize_t amdgpu_get_pp_features(struct device *dev,
 948                                       struct device_attribute *attr,
 949                                       char *buf)
 950 {
 951         struct drm_device *ddev = dev_get_drvdata(dev);
 952         struct amdgpu_device *adev = drm_to_adev(ddev);
 953         ssize_t size;
 954         int ret;
 955
 956         if (amdgpu_in_reset(adev))
 957                 return -EPERM;
 958         if (adev->in_suspend && !adev->in_runpm)
 959                 return -EPERM;
 960
 961         ret = pm_runtime_get_sync(ddev->dev);
 962         if (ret < 0) {
 963                 pm_runtime_put_autosuspend(ddev->dev);
 964                 return ret;
 965         }
 966
 967         size = amdgpu_dpm_get_ppfeature_status(adev, buf);
 968         if (size <= 0)
 969                 size = sysfs_emit(buf, "\n");
 970
 971         pm_runtime_mark_last_busy(ddev->dev);
 972         pm_runtime_put_autosuspend(ddev->dev);
 973
 974         return size;
 975 }
 976
 977 /**
 978  * DOC: pp_dpm_sclk pp_dpm_mclk pp_dpm_socclk pp_dpm_fclk pp_dpm_dcefclk pp_dpm_pcie
 979  *
 980  * The amdgpu driver provides a sysfs API for adjusting what power levels
 981  * are enabled for a given power state.  The files pp_dpm_sclk, pp_dpm_mclk,
 982  * pp_dpm_socclk, pp_dpm_fclk, pp_dpm_dcefclk and pp_dpm_pcie are used for
 983  * this.
 984  *
 985  * pp_dpm_socclk and pp_dpm_dcefclk interfaces are only available for
 986  * Vega10 and later ASICs.
 987  * pp_dpm_fclk interface is only available for Vega20 and later ASICs.
 988  *
 989  * Reading back the files will show you the available power levels within
 990  * the power state and the clock information for those levels. If deep sleep is
 991  * applied to a clock, the level will be denoted by a special level 'S:'
 992  * E.g., ::
 993  *
 994  *  S: 19Mhz *
 995  *  0: 615Mhz
 996  *  1: 800Mhz
 997  *  2: 888Mhz
 998  *  3: 1000Mhz
 999  *
1000  *
1001  * To manually adjust these states, first select manual using
1002  * power_dpm_force_performance_level.
1003  * Secondly, enter a new value for each level by inputing a string that
1004  * contains " echo xx xx xx > pp_dpm_sclk/mclk/pcie"
1005  * E.g.,
1006  *
1007  * .. code-block:: bash
1008  *
1009  *      echo "4 5 6" > pp_dpm_sclk
1010  *
1011  * will enable sclk levels 4, 5, and 6.
1012  *
1013  * NOTE: change to the dcefclk max dpm level is not supported now
1014  */
1015
1016 static ssize_t amdgpu_get_pp_dpm_clock(struct device *dev,
1017                 enum pp_clock_type type,
1018                 char *buf)
1019 {
1020         struct drm_device *ddev = dev_get_drvdata(dev);
1021         struct amdgpu_device *adev = drm_to_adev(ddev);
1022         int size = 0;
1023         int ret = 0;
1024
1025         if (amdgpu_in_reset(adev))
1026                 return -EPERM;
1027         if (adev->in_suspend && !adev->in_runpm)
1028                 return -EPERM;
1029
1030         ret = pm_runtime_get_sync(ddev->dev);
1031         if (ret < 0) {
1032                 pm_runtime_put_autosuspend(ddev->dev);
1033                 return ret;
1034         }
1035
1036         ret = amdgpu_dpm_emit_clock_levels(adev, type, buf, &size);
1037         if (ret == -ENOENT)
1038                 size = amdgpu_dpm_print_clock_levels(adev, type, buf);
1039
1040         if (size == 0)
1041                 size = sysfs_emit(buf, "\n");
1042
1043         pm_runtime_mark_last_busy(ddev->dev);
1044         pm_runtime_put_autosuspend(ddev->dev);
1045
1046         return size;
1047 }
1048
1049 /*
1050  * Worst case: 32 bits individually specified, in octal at 12 characters
1051  * per line (+1 for \n).
1052  */
1053 #define AMDGPU_MASK_BUF_MAX     (32 * 13)
1054
1055 static ssize_t amdgpu_read_mask(const char *buf, size_t count, uint32_t *mask)
1056 {
1057         int ret;
1058         unsigned long level;
1059         char *sub_str = NULL;
1060         char *tmp;
1061         char buf_cpy[AMDGPU_MASK_BUF_MAX + 1];
1062         const char delimiter[3] = {' ', '\n', '\0'};
1063         size_t bytes;
1064
1065         *mask = 0;
1066
1067         bytes = min(count, sizeof(buf_cpy) - 1);
1068         memcpy(buf_cpy, buf, bytes);
1069         buf_cpy[bytes] = '\0';
1070         tmp = buf_cpy;
1071         while ((sub_str = strsep(&tmp, delimiter)) != NULL) {
1072                 if (strlen(sub_str)) {
1073                         ret = kstrtoul(sub_str, 0, &level);
1074                         if (ret || level > 31)
1075                                 return -EINVAL;
1076                         *mask |= 1 << level;
1077                 } else
1078                         break;
1079         }
1080
1081         return 0;
1082 }
1083
1084 static ssize_t amdgpu_set_pp_dpm_clock(struct device *dev,
1085                 enum pp_clock_type type,
1086                 const char *buf,
1087                 size_t count)
1088 {
1089         struct drm_device *ddev = dev_get_drvdata(dev);
1090         struct amdgpu_device *adev = drm_to_adev(ddev);
1091         int ret;
1092         uint32_t mask = 0;
1093
1094         if (amdgpu_in_reset(adev))
1095                 return -EPERM;
1096         if (adev->in_suspend && !adev->in_runpm)
1097                 return -EPERM;
1098
1099         ret = amdgpu_read_mask(buf, count, &mask);
1100         if (ret)
1101                 return ret;
1102
1103         ret = pm_runtime_get_sync(ddev->dev);
1104         if (ret < 0) {
1105                 pm_runtime_put_autosuspend(ddev->dev);
1106                 return ret;
1107         }
1108
1109         ret = amdgpu_dpm_force_clock_level(adev, type, mask);
1110
1111         pm_runtime_mark_last_busy(ddev->dev);
1112         pm_runtime_put_autosuspend(ddev->dev);
1113
1114         if (ret)
1115                 return -EINVAL;
1116
1117         return count;
1118 }
1119
1120 static ssize_t amdgpu_get_pp_dpm_sclk(struct device *dev,
1121                 struct device_attribute *attr,
1122                 char *buf)
1123 {
1124         return amdgpu_get_pp_dpm_clock(dev, PP_SCLK, buf);
1125 }
1126
1127 static ssize_t amdgpu_set_pp_dpm_sclk(struct device *dev,
1128                 struct device_attribute *attr,
1129                 const char *buf,
1130                 size_t count)
1131 {
1132         return amdgpu_set_pp_dpm_clock(dev, PP_SCLK, buf, count);
1133 }
1134
1135 static ssize_t amdgpu_get_pp_dpm_mclk(struct device *dev,
1136                 struct device_attribute *attr,
1137                 char *buf)
1138 {
1139         return amdgpu_get_pp_dpm_clock(dev, PP_MCLK, buf);
1140 }
1141
1142 static ssize_t amdgpu_set_pp_dpm_mclk(struct device *dev,
1143                 struct device_attribute *attr,
1144                 const char *buf,
1145                 size_t count)
1146 {
1147         return amdgpu_set_pp_dpm_clock(dev, PP_MCLK, buf, count);
1148 }
1149
1150 static ssize_t amdgpu_get_pp_dpm_socclk(struct device *dev,
1151                 struct device_attribute *attr,
1152                 char *buf)
1153 {
1154         return amdgpu_get_pp_dpm_clock(dev, PP_SOCCLK, buf);
1155 }
1156
1157 static ssize_t amdgpu_set_pp_dpm_socclk(struct device *dev,
1158                 struct device_attribute *attr,
1159                 const char *buf,
1160                 size_t count)
1161 {
1162         return amdgpu_set_pp_dpm_clock(dev, PP_SOCCLK, buf, count);
1163 }
1164
1165 static ssize_t amdgpu_get_pp_dpm_fclk(struct device *dev,
1166                 struct device_attribute *attr,
1167                 char *buf)
1168 {
1169         return amdgpu_get_pp_dpm_clock(dev, PP_FCLK, buf);
1170 }
1171
1172 static ssize_t amdgpu_set_pp_dpm_fclk(struct device *dev,
1173                 struct device_attribute *attr,
1174                 const char *buf,
1175                 size_t count)
1176 {
1177         return amdgpu_set_pp_dpm_clock(dev, PP_FCLK, buf, count);
1178 }
1179
1180 static ssize_t amdgpu_get_pp_dpm_vclk(struct device *dev,
1181                 struct device_attribute *attr,
1182                 char *buf)
1183 {
1184         return amdgpu_get_pp_dpm_clock(dev, PP_VCLK, buf);
1185 }
1186
1187 static ssize_t amdgpu_set_pp_dpm_vclk(struct device *dev,
1188                 struct device_attribute *attr,
1189                 const char *buf,
1190                 size_t count)
1191 {
1192         return amdgpu_set_pp_dpm_clock(dev, PP_VCLK, buf, count);
1193 }
1194
1195 static ssize_t amdgpu_get_pp_dpm_vclk1(struct device *dev,
1196                 struct device_attribute *attr,
1197                 char *buf)
1198 {
1199         return amdgpu_get_pp_dpm_clock(dev, PP_VCLK1, buf);
1200 }
1201
1202 static ssize_t amdgpu_set_pp_dpm_vclk1(struct device *dev,
1203                 struct device_attribute *attr,
1204                 const char *buf,
1205                 size_t count)
1206 {
1207         return amdgpu_set_pp_dpm_clock(dev, PP_VCLK1, buf, count);
1208 }
1209
1210 static ssize_t amdgpu_get_pp_dpm_dclk(struct device *dev,
1211                 struct device_attribute *attr,
1212                 char *buf)
1213 {
1214         return amdgpu_get_pp_dpm_clock(dev, PP_DCLK, buf);
1215 }
1216
1217 static ssize_t amdgpu_set_pp_dpm_dclk(struct device *dev,
1218                 struct device_attribute *attr,
1219                 const char *buf,
1220                 size_t count)
1221 {
1222         return amdgpu_set_pp_dpm_clock(dev, PP_DCLK, buf, count);
1223 }
1224
1225 static ssize_t amdgpu_get_pp_dpm_dclk1(struct device *dev,
1226                 struct device_attribute *attr,
1227                 char *buf)
1228 {
1229         return amdgpu_get_pp_dpm_clock(dev, PP_DCLK1, buf);
1230 }
1231
1232 static ssize_t amdgpu_set_pp_dpm_dclk1(struct device *dev,
1233                 struct device_attribute *attr,
1234                 const char *buf,
1235                 size_t count)
1236 {
1237         return amdgpu_set_pp_dpm_clock(dev, PP_DCLK1, buf, count);
1238 }
1239
1240 static ssize_t amdgpu_get_pp_dpm_dcefclk(struct device *dev,
1241                 struct device_attribute *attr,
1242                 char *buf)
1243 {
1244         return amdgpu_get_pp_dpm_clock(dev, PP_DCEFCLK, buf);
1245 }
1246
1247 static ssize_t amdgpu_set_pp_dpm_dcefclk(struct device *dev,
1248                 struct device_attribute *attr,
1249                 const char *buf,
1250                 size_t count)
1251 {
1252         return amdgpu_set_pp_dpm_clock(dev, PP_DCEFCLK, buf, count);
1253 }
1254
1255 static ssize_t amdgpu_get_pp_dpm_pcie(struct device *dev,
1256                 struct device_attribute *attr,
1257                 char *buf)
1258 {
1259         return amdgpu_get_pp_dpm_clock(dev, PP_PCIE, buf);
1260 }
1261
1262 static ssize_t amdgpu_set_pp_dpm_pcie(struct device *dev,
1263                 struct device_attribute *attr,
1264                 const char *buf,
1265                 size_t count)
1266 {
1267         return amdgpu_set_pp_dpm_clock(dev, PP_PCIE, buf, count);
1268 }
1269
1270 static ssize_t amdgpu_get_pp_sclk_od(struct device *dev,
1271                 struct device_attribute *attr,
1272                 char *buf)
1273 {
1274         struct drm_device *ddev = dev_get_drvdata(dev);
1275         struct amdgpu_device *adev = drm_to_adev(ddev);
1276         uint32_t value = 0;
1277         int ret;
1278
1279         if (amdgpu_in_reset(adev))
1280                 return -EPERM;
1281         if (adev->in_suspend && !adev->in_runpm)
1282                 return -EPERM;
1283
1284         ret = pm_runtime_get_sync(ddev->dev);
1285         if (ret < 0) {
1286                 pm_runtime_put_autosuspend(ddev->dev);
1287                 return ret;
1288         }
1289
1290         value = amdgpu_dpm_get_sclk_od(adev);
1291
1292         pm_runtime_mark_last_busy(ddev->dev);
1293         pm_runtime_put_autosuspend(ddev->dev);
1294
1295         return sysfs_emit(buf, "%d\n", value);
1296 }
1297
1298 static ssize_t amdgpu_set_pp_sclk_od(struct device *dev,
1299                 struct device_attribute *attr,
1300                 const char *buf,
1301                 size_t count)
1302 {
1303         struct drm_device *ddev = dev_get_drvdata(dev);
1304         struct amdgpu_device *adev = drm_to_adev(ddev);
1305         int ret;
1306         long int value;
1307
1308         if (amdgpu_in_reset(adev))
1309                 return -EPERM;
1310         if (adev->in_suspend && !adev->in_runpm)
1311                 return -EPERM;
1312
1313         ret = kstrtol(buf, 0, &value);
1314
1315         if (ret)
1316                 return -EINVAL;
1317
1318         ret = pm_runtime_get_sync(ddev->dev);
1319         if (ret < 0) {
1320                 pm_runtime_put_autosuspend(ddev->dev);
1321                 return ret;
1322         }
1323
1324         amdgpu_dpm_set_sclk_od(adev, (uint32_t)value);
1325
1326         pm_runtime_mark_last_busy(ddev->dev);
1327         pm_runtime_put_autosuspend(ddev->dev);
1328
1329         return count;
1330 }
1331
1332 static ssize_t amdgpu_get_pp_mclk_od(struct device *dev,
1333                 struct device_attribute *attr,
1334                 char *buf)
1335 {
1336         struct drm_device *ddev = dev_get_drvdata(dev);
1337         struct amdgpu_device *adev = drm_to_adev(ddev);
1338         uint32_t value = 0;
1339         int ret;
1340
1341         if (amdgpu_in_reset(adev))
1342                 return -EPERM;
1343         if (adev->in_suspend && !adev->in_runpm)
1344                 return -EPERM;
1345
1346         ret = pm_runtime_get_sync(ddev->dev);
1347         if (ret < 0) {
1348                 pm_runtime_put_autosuspend(ddev->dev);
1349                 return ret;
1350         }
1351
1352         value = amdgpu_dpm_get_mclk_od(adev);
1353
1354         pm_runtime_mark_last_busy(ddev->dev);
1355         pm_runtime_put_autosuspend(ddev->dev);
1356
1357         return sysfs_emit(buf, "%d\n", value);
1358 }
1359
1360 static ssize_t amdgpu_set_pp_mclk_od(struct device *dev,
1361                 struct device_attribute *attr,
1362                 const char *buf,
1363                 size_t count)
1364 {
1365         struct drm_device *ddev = dev_get_drvdata(dev);
1366         struct amdgpu_device *adev = drm_to_adev(ddev);
1367         int ret;
1368         long int value;
1369
1370         if (amdgpu_in_reset(adev))
1371                 return -EPERM;
1372         if (adev->in_suspend && !adev->in_runpm)
1373                 return -EPERM;
1374
1375         ret = kstrtol(buf, 0, &value);
1376
1377         if (ret)
1378                 return -EINVAL;
1379
1380         ret = pm_runtime_get_sync(ddev->dev);
1381         if (ret < 0) {
1382                 pm_runtime_put_autosuspend(ddev->dev);
1383                 return ret;
1384         }
1385
1386         amdgpu_dpm_set_mclk_od(adev, (uint32_t)value);
1387
1388         pm_runtime_mark_last_busy(ddev->dev);
1389         pm_runtime_put_autosuspend(ddev->dev);
1390
1391         return count;
1392 }
1393
1394 /**
1395  * DOC: pp_power_profile_mode
1396  *
1397  * The amdgpu driver provides a sysfs API for adjusting the heuristics
1398  * related to switching between power levels in a power state.  The file
1399  * pp_power_profile_mode is used for this.
1400  *
1401  * Reading this file outputs a list of all of the predefined power profiles
1402  * and the relevant heuristics settings for that profile.
1403  *
1404  * To select a profile or create a custom profile, first select manual using
1405  * power_dpm_force_performance_level.  Writing the number of a predefined
1406  * profile to pp_power_profile_mode will enable those heuristics.  To
1407  * create a custom set of heuristics, write a string of numbers to the file
1408  * starting with the number of the custom profile along with a setting
1409  * for each heuristic parameter.  Due to differences across asic families
1410  * the heuristic parameters vary from family to family.
1411  *
1412  */
1413
1414 static ssize_t amdgpu_get_pp_power_profile_mode(struct device *dev,
1415                 struct device_attribute *attr,
1416                 char *buf)
1417 {
1418         struct drm_device *ddev = dev_get_drvdata(dev);
1419         struct amdgpu_device *adev = drm_to_adev(ddev);
1420         ssize_t size;
1421         int ret;
1422
1423         if (amdgpu_in_reset(adev))
1424                 return -EPERM;
1425         if (adev->in_suspend && !adev->in_runpm)
1426                 return -EPERM;
1427
1428         ret = pm_runtime_get_sync(ddev->dev);
1429         if (ret < 0) {
1430                 pm_runtime_put_autosuspend(ddev->dev);
1431                 return ret;
1432         }
1433
1434         size = amdgpu_dpm_get_power_profile_mode(adev, buf);
1435         if (size <= 0)
1436                 size = sysfs_emit(buf, "\n");
1437
1438         pm_runtime_mark_last_busy(ddev->dev);
1439         pm_runtime_put_autosuspend(ddev->dev);
1440
1441         return size;
1442 }
1443
1444
1445 static ssize_t amdgpu_set_pp_power_profile_mode(struct device *dev,
1446                 struct device_attribute *attr,
1447                 const char *buf,
1448                 size_t count)
1449 {
1450         int ret;
1451         struct drm_device *ddev = dev_get_drvdata(dev);
1452         struct amdgpu_device *adev = drm_to_adev(ddev);
1453         uint32_t parameter_size = 0;
1454         long parameter[64];
1455         char *sub_str, buf_cpy[128];
1456         char *tmp_str;
1457         uint32_t i = 0;
1458         char tmp[2];
1459         long int profile_mode = 0;
1460         const char delimiter[3] = {' ', '\n', '\0'};
1461
1462         if (amdgpu_in_reset(adev))
1463                 return -EPERM;
1464         if (adev->in_suspend && !adev->in_runpm)
1465                 return -EPERM;
1466
1467         tmp[0] = *(buf);
1468         tmp[1] = '\0';
1469         ret = kstrtol(tmp, 0, &profile_mode);
1470         if (ret)
1471                 return -EINVAL;
1472
1473         if (profile_mode == PP_SMC_POWER_PROFILE_CUSTOM) {
1474                 if (count < 2 || count > 127)
1475                         return -EINVAL;
1476                 while (isspace(*++buf))
1477                         i++;
1478                 memcpy(buf_cpy, buf, count-i);
1479                 tmp_str = buf_cpy;
1480                 while ((sub_str = strsep(&tmp_str, delimiter)) != NULL) {
1481                         if (strlen(sub_str) == 0)
1482                                 continue;
1483                         ret = kstrtol(sub_str, 0, &parameter[parameter_size]);
1484                         if (ret)
1485                                 return -EINVAL;
1486                         parameter_size++;
1487                         while (isspace(*tmp_str))
1488                                 tmp_str++;
1489                 }
1490         }
1491         parameter[parameter_size] = profile_mode;
1492
1493         ret = pm_runtime_get_sync(ddev->dev);
1494         if (ret < 0) {
1495                 pm_runtime_put_autosuspend(ddev->dev);
1496                 return ret;
1497         }
1498
1499         ret = amdgpu_dpm_set_power_profile_mode(adev, parameter, parameter_size);
1500
1501         pm_runtime_mark_last_busy(ddev->dev);
1502         pm_runtime_put_autosuspend(ddev->dev);
1503
1504         if (!ret)
1505                 return count;
1506
1507         return -EINVAL;
1508 }
1509
1510 static int amdgpu_hwmon_get_sensor_generic(struct amdgpu_device *adev,
1511                                            enum amd_pp_sensors sensor,
1512                                            void *query)
1513 {
1514         int r, size = sizeof(uint32_t);
1515
1516         if (amdgpu_in_reset(adev))
1517                 return -EPERM;
1518         if (adev->in_suspend && !adev->in_runpm)
1519                 return -EPERM;
1520
1521         r = pm_runtime_get_sync(adev_to_drm(adev)->dev);
1522         if (r < 0) {
1523                 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
1524                 return r;
1525         }
1526
1527         /* get the sensor value */
1528         r = amdgpu_dpm_read_sensor(adev, sensor, query, &size);
1529
1530         pm_runtime_mark_last_busy(adev_to_drm(adev)->dev);
1531         pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
1532
1533         return r;
1534 }
1535
1536 /**
1537  * DOC: gpu_busy_percent
1538  *
1539  * The amdgpu driver provides a sysfs API for reading how busy the GPU
1540  * is as a percentage.  The file gpu_busy_percent is used for this.
1541  * The SMU firmware computes a percentage of load based on the
1542  * aggregate activity level in the IP cores.
1543  */
1544 static ssize_t amdgpu_get_gpu_busy_percent(struct device *dev,
1545                                            struct device_attribute *attr,
1546                                            char *buf)
1547 {
1548         struct drm_device *ddev = dev_get_drvdata(dev);
1549         struct amdgpu_device *adev = drm_to_adev(ddev);
1550         unsigned int value;
1551         int r;
1552
1553         r = amdgpu_hwmon_get_sensor_generic(adev, AMDGPU_PP_SENSOR_GPU_LOAD, &value);
1554         if (r)
1555                 return r;
1556
1557         return sysfs_emit(buf, "%d\n", value);
1558 }
1559
1560 /**
1561  * DOC: mem_busy_percent
1562  *
1563  * The amdgpu driver provides a sysfs API for reading how busy the VRAM
1564  * is as a percentage.  The file mem_busy_percent is used for this.
1565  * The SMU firmware computes a percentage of load based on the
1566  * aggregate activity level in the IP cores.
1567  */
1568 static ssize_t amdgpu_get_mem_busy_percent(struct device *dev,
1569                                            struct device_attribute *attr,
1570                                            char *buf)
1571 {
1572         struct drm_device *ddev = dev_get_drvdata(dev);
1573         struct amdgpu_device *adev = drm_to_adev(ddev);
1574         unsigned int value;
1575         int r;
1576
1577         r = amdgpu_hwmon_get_sensor_generic(adev, AMDGPU_PP_SENSOR_MEM_LOAD, &value);
1578         if (r)
1579                 return r;
1580
1581         return sysfs_emit(buf, "%d\n", value);
1582 }
1583
1584 /**
1585  * DOC: pcie_bw
1586  *
1587  * The amdgpu driver provides a sysfs API for estimating how much data
1588  * has been received and sent by the GPU in the last second through PCIe.
1589  * The file pcie_bw is used for this.
1590  * The Perf counters count the number of received and sent messages and return
1591  * those values, as well as the maximum payload size of a PCIe packet (mps).
1592  * Note that it is not possible to easily and quickly obtain the size of each
1593  * packet transmitted, so we output the max payload size (mps) to allow for
1594  * quick estimation of the PCIe bandwidth usage
1595  */
1596 static ssize_t amdgpu_get_pcie_bw(struct device *dev,
1597                 struct device_attribute *attr,
1598                 char *buf)
1599 {
1600         struct drm_device *ddev = dev_get_drvdata(dev);
1601         struct amdgpu_device *adev = drm_to_adev(ddev);
1602         uint64_t count0 = 0, count1 = 0;
1603         int ret;
1604
1605         if (amdgpu_in_reset(adev))
1606                 return -EPERM;
1607         if (adev->in_suspend && !adev->in_runpm)
1608                 return -EPERM;
1609
1610         if (adev->flags & AMD_IS_APU)
1611                 return -ENODATA;
1612
1613         if (!adev->asic_funcs->get_pcie_usage)
1614                 return -ENODATA;
1615
1616         ret = pm_runtime_get_sync(ddev->dev);
1617         if (ret < 0) {
1618                 pm_runtime_put_autosuspend(ddev->dev);
1619                 return ret;
1620         }
1621
1622         amdgpu_asic_get_pcie_usage(adev, &count0, &count1);
1623
1624         pm_runtime_mark_last_busy(ddev->dev);
1625         pm_runtime_put_autosuspend(ddev->dev);
1626
1627         return sysfs_emit(buf, "%llu %llu %i\n",
1628                           count0, count1, pcie_get_mps(adev->pdev));
1629 }
1630
1631 /**
1632  * DOC: unique_id
1633  *
1634  * The amdgpu driver provides a sysfs API for providing a unique ID for the GPU
1635  * The file unique_id is used for this.
1636  * This will provide a Unique ID that will persist from machine to machine
1637  *
1638  * NOTE: This will only work for GFX9 and newer. This file will be absent
1639  * on unsupported ASICs (GFX8 and older)
1640  */
1641 static ssize_t amdgpu_get_unique_id(struct device *dev,
1642                 struct device_attribute *attr,
1643                 char *buf)
1644 {
1645         struct drm_device *ddev = dev_get_drvdata(dev);
1646         struct amdgpu_device *adev = drm_to_adev(ddev);
1647
1648         if (amdgpu_in_reset(adev))
1649                 return -EPERM;
1650         if (adev->in_suspend && !adev->in_runpm)
1651                 return -EPERM;
1652
1653         if (adev->unique_id)
1654                 return sysfs_emit(buf, "%016llx\n", adev->unique_id);
1655
1656         return 0;
1657 }
1658
1659 /**
1660  * DOC: thermal_throttling_logging
1661  *
1662  * Thermal throttling pulls down the clock frequency and thus the performance.
1663  * It's an useful mechanism to protect the chip from overheating. Since it
1664  * impacts performance, the user controls whether it is enabled and if so,
1665  * the log frequency.
1666  *
1667  * Reading back the file shows you the status(enabled or disabled) and
1668  * the interval(in seconds) between each thermal logging.
1669  *
1670  * Writing an integer to the file, sets a new logging interval, in seconds.
1671  * The value should be between 1 and 3600. If the value is less than 1,
1672  * thermal logging is disabled. Values greater than 3600 are ignored.
1673  */
1674 static ssize_t amdgpu_get_thermal_throttling_logging(struct device *dev,
1675                                                      struct device_attribute *attr,
1676                                                      char *buf)
1677 {
1678         struct drm_device *ddev = dev_get_drvdata(dev);
1679         struct amdgpu_device *adev = drm_to_adev(ddev);
1680
1681         return sysfs_emit(buf, "%s: thermal throttling logging %s, with interval %d seconds\n",
1682                           adev_to_drm(adev)->unique,
1683                           atomic_read(&adev->throttling_logging_enabled) ? "enabled" : "disabled",
1684                           adev->throttling_logging_rs.interval / HZ + 1);
1685 }
1686
1687 static ssize_t amdgpu_set_thermal_throttling_logging(struct device *dev,
1688                                                      struct device_attribute *attr,
1689                                                      const char *buf,
1690                                                      size_t count)
1691 {
1692         struct drm_device *ddev = dev_get_drvdata(dev);
1693         struct amdgpu_device *adev = drm_to_adev(ddev);
1694         long throttling_logging_interval;
1695         unsigned long flags;
1696         int ret = 0;
1697
1698         ret = kstrtol(buf, 0, &throttling_logging_interval);
1699         if (ret)
1700                 return ret;
1701
1702         if (throttling_logging_interval > 3600)
1703                 return -EINVAL;
1704
1705         if (throttling_logging_interval > 0) {
1706                 raw_spin_lock_irqsave(&adev->throttling_logging_rs.lock, flags);
1707                 /*
1708                  * Reset the ratelimit timer internals.
1709                  * This can effectively restart the timer.
1710                  */
1711                 adev->throttling_logging_rs.interval =
1712                         (throttling_logging_interval - 1) * HZ;
1713                 adev->throttling_logging_rs.begin = 0;
1714                 adev->throttling_logging_rs.printed = 0;
1715                 adev->throttling_logging_rs.missed = 0;
1716                 raw_spin_unlock_irqrestore(&adev->throttling_logging_rs.lock, flags);
1717
1718                 atomic_set(&adev->throttling_logging_enabled, 1);
1719         } else {
1720                 atomic_set(&adev->throttling_logging_enabled, 0);
1721         }
1722
1723         return count;
1724 }
1725
1726 /**
1727  * DOC: apu_thermal_cap
1728  *
1729  * The amdgpu driver provides a sysfs API for retrieving/updating thermal
1730  * limit temperature in millidegrees Celsius
1731  *
1732  * Reading back the file shows you core limit value
1733  *
1734  * Writing an integer to the file, sets a new thermal limit. The value
1735  * should be between 0 and 100. If the value is less than 0 or greater
1736  * than 100, then the write request will be ignored.
1737  */
1738 static ssize_t amdgpu_get_apu_thermal_cap(struct device *dev,
1739                                          struct device_attribute *attr,
1740                                          char *buf)
1741 {
1742         int ret, size;
1743         u32 limit;
1744         struct drm_device *ddev = dev_get_drvdata(dev);
1745         struct amdgpu_device *adev = drm_to_adev(ddev);
1746
1747         ret = pm_runtime_get_sync(ddev->dev);
1748         if (ret < 0) {
1749                 pm_runtime_put_autosuspend(ddev->dev);
1750                 return ret;
1751         }
1752
1753         ret = amdgpu_dpm_get_apu_thermal_limit(adev, &limit);
1754         if (!ret)
1755                 size = sysfs_emit(buf, "%u\n", limit);
1756         else
1757                 size = sysfs_emit(buf, "failed to get thermal limit\n");
1758
1759         pm_runtime_mark_last_busy(ddev->dev);
1760         pm_runtime_put_autosuspend(ddev->dev);
1761
1762         return size;
1763 }
1764
1765 static ssize_t amdgpu_set_apu_thermal_cap(struct device *dev,
1766                                          struct device_attribute *attr,
1767                                          const char *buf,
1768                                          size_t count)
1769 {
1770         int ret;
1771         u32 value;
1772         struct drm_device *ddev = dev_get_drvdata(dev);
1773         struct amdgpu_device *adev = drm_to_adev(ddev);
1774
1775         ret = kstrtou32(buf, 10, &value);
1776         if (ret)
1777                 return ret;
1778
1779         if (value > 100) {
1780                 dev_err(dev, "Invalid argument !\n");
1781                 return -EINVAL;
1782         }
1783
1784         ret = pm_runtime_get_sync(ddev->dev);
1785         if (ret < 0) {
1786                 pm_runtime_put_autosuspend(ddev->dev);
1787                 return ret;
1788         }
1789
1790         ret = amdgpu_dpm_set_apu_thermal_limit(adev, value);
1791         if (ret) {
1792                 dev_err(dev, "failed to update thermal limit\n");
1793                 return ret;
1794         }
1795
1796         pm_runtime_mark_last_busy(ddev->dev);
1797         pm_runtime_put_autosuspend(ddev->dev);
1798
1799         return count;
1800 }
1801
1802 /**
1803  * DOC: gpu_metrics
1804  *
1805  * The amdgpu driver provides a sysfs API for retrieving current gpu
1806  * metrics data. The file gpu_metrics is used for this. Reading the
1807  * file will dump all the current gpu metrics data.
1808  *
1809  * These data include temperature, frequency, engines utilization,
1810  * power consume, throttler status, fan speed and cpu core statistics(
1811  * available for APU only). That's it will give a snapshot of all sensors
1812  * at the same time.
1813  */
1814 static ssize_t amdgpu_get_gpu_metrics(struct device *dev,
1815                                       struct device_attribute *attr,
1816                                       char *buf)
1817 {
1818         struct drm_device *ddev = dev_get_drvdata(dev);
1819         struct amdgpu_device *adev = drm_to_adev(ddev);
1820         void *gpu_metrics;
1821         ssize_t size = 0;
1822         int ret;
1823
1824         if (amdgpu_in_reset(adev))
1825                 return -EPERM;
1826         if (adev->in_suspend && !adev->in_runpm)
1827                 return -EPERM;
1828
1829         ret = pm_runtime_get_sync(ddev->dev);
1830         if (ret < 0) {
1831                 pm_runtime_put_autosuspend(ddev->dev);
1832                 return ret;
1833         }
1834
1835         size = amdgpu_dpm_get_gpu_metrics(adev, &gpu_metrics);
1836         if (size <= 0)
1837                 goto out;
1838
1839         if (size >= PAGE_SIZE)
1840                 size = PAGE_SIZE - 1;
1841
1842         memcpy(buf, gpu_metrics, size);
1843
1844 out:
1845         pm_runtime_mark_last_busy(ddev->dev);
1846         pm_runtime_put_autosuspend(ddev->dev);
1847
1848         return size;
1849 }
1850
1851 static int amdgpu_show_powershift_percent(struct device *dev,
1852                                         char *buf, enum amd_pp_sensors sensor)
1853 {
1854         struct drm_device *ddev = dev_get_drvdata(dev);
1855         struct amdgpu_device *adev = drm_to_adev(ddev);
1856         uint32_t ss_power;
1857         int r = 0, i;
1858
1859         r = amdgpu_hwmon_get_sensor_generic(adev, sensor, (void *)&ss_power);
1860         if (r == -EOPNOTSUPP) {
1861                 /* sensor not available on dGPU, try to read from APU */
1862                 adev = NULL;
1863                 mutex_lock(&mgpu_info.mutex);
1864                 for (i = 0; i < mgpu_info.num_gpu; i++) {
1865                         if (mgpu_info.gpu_ins[i].adev->flags & AMD_IS_APU) {
1866                                 adev = mgpu_info.gpu_ins[i].adev;
1867                                 break;
1868                         }
1869                 }
1870                 mutex_unlock(&mgpu_info.mutex);
1871                 if (adev)
1872                         r = amdgpu_hwmon_get_sensor_generic(adev, sensor, (void *)&ss_power);
1873         }
1874
1875         if (r)
1876                 return r;
1877
1878         return sysfs_emit(buf, "%u%%\n", ss_power);
1879 }
1880
1881 /**
1882  * DOC: smartshift_apu_power
1883  *
1884  * The amdgpu driver provides a sysfs API for reporting APU power
1885  * shift in percentage if platform supports smartshift. Value 0 means that
1886  * there is no powershift and values between [1-100] means that the power
1887  * is shifted to APU, the percentage of boost is with respect to APU power
1888  * limit on the platform.
1889  */
1890
1891 static ssize_t amdgpu_get_smartshift_apu_power(struct device *dev, struct device_attribute *attr,
1892                                                char *buf)
1893 {
1894         return amdgpu_show_powershift_percent(dev, buf, AMDGPU_PP_SENSOR_SS_APU_SHARE);
1895 }
1896
1897 /**
1898  * DOC: smartshift_dgpu_power
1899  *
1900  * The amdgpu driver provides a sysfs API for reporting dGPU power
1901  * shift in percentage if platform supports smartshift. Value 0 means that
1902  * there is no powershift and values between [1-100] means that the power is
1903  * shifted to dGPU, the percentage of boost is with respect to dGPU power
1904  * limit on the platform.
1905  */
1906
1907 static ssize_t amdgpu_get_smartshift_dgpu_power(struct device *dev, struct device_attribute *attr,
1908                                                 char *buf)
1909 {
1910         return amdgpu_show_powershift_percent(dev, buf, AMDGPU_PP_SENSOR_SS_DGPU_SHARE);
1911 }
1912
1913 /**
1914  * DOC: smartshift_bias
1915  *
1916  * The amdgpu driver provides a sysfs API for reporting the
1917  * smartshift(SS2.0) bias level. The value ranges from -100 to 100
1918  * and the default is 0. -100 sets maximum preference to APU
1919  * and 100 sets max perference to dGPU.
1920  */
1921
1922 static ssize_t amdgpu_get_smartshift_bias(struct device *dev,
1923                                           struct device_attribute *attr,
1924                                           char *buf)
1925 {
1926         int r = 0;
1927
1928         r = sysfs_emit(buf, "%d\n", amdgpu_smartshift_bias);
1929
1930         return r;
1931 }
1932
1933 static ssize_t amdgpu_set_smartshift_bias(struct device *dev,
1934                                           struct device_attribute *attr,
1935                                           const char *buf, size_t count)
1936 {
1937         struct drm_device *ddev = dev_get_drvdata(dev);
1938         struct amdgpu_device *adev = drm_to_adev(ddev);
1939         int r = 0;
1940         int bias = 0;
1941
1942         if (amdgpu_in_reset(adev))
1943                 return -EPERM;
1944         if (adev->in_suspend && !adev->in_runpm)
1945                 return -EPERM;
1946
1947         r = pm_runtime_get_sync(ddev->dev);
1948         if (r < 0) {
1949                 pm_runtime_put_autosuspend(ddev->dev);
1950                 return r;
1951         }
1952
1953         r = kstrtoint(buf, 10, &bias);
1954         if (r)
1955                 goto out;
1956
1957         if (bias > AMDGPU_SMARTSHIFT_MAX_BIAS)
1958                 bias = AMDGPU_SMARTSHIFT_MAX_BIAS;
1959         else if (bias < AMDGPU_SMARTSHIFT_MIN_BIAS)
1960                 bias = AMDGPU_SMARTSHIFT_MIN_BIAS;
1961
1962         amdgpu_smartshift_bias = bias;
1963         r = count;
1964
1965         /* TODO: update bias level with SMU message */
1966
1967 out:
1968         pm_runtime_mark_last_busy(ddev->dev);
1969         pm_runtime_put_autosuspend(ddev->dev);
1970         return r;
1971 }
1972
1973 static int ss_power_attr_update(struct amdgpu_device *adev, struct amdgpu_device_attr *attr,
1974                                 uint32_t mask, enum amdgpu_device_attr_states *states)
1975 {
1976         if (!amdgpu_device_supports_smart_shift(adev_to_drm(adev)))
1977                 *states = ATTR_STATE_UNSUPPORTED;
1978
1979         return 0;
1980 }
1981
1982 static int ss_bias_attr_update(struct amdgpu_device *adev, struct amdgpu_device_attr *attr,
1983                                uint32_t mask, enum amdgpu_device_attr_states *states)
1984 {
1985         uint32_t ss_power;
1986
1987         if (!amdgpu_device_supports_smart_shift(adev_to_drm(adev)))
1988                 *states = ATTR_STATE_UNSUPPORTED;
1989         else if (amdgpu_hwmon_get_sensor_generic(adev, AMDGPU_PP_SENSOR_SS_APU_SHARE,
1990                  (void *)&ss_power))
1991                 *states = ATTR_STATE_UNSUPPORTED;
1992         else if (amdgpu_hwmon_get_sensor_generic(adev, AMDGPU_PP_SENSOR_SS_DGPU_SHARE,
1993                  (void *)&ss_power))
1994                 *states = ATTR_STATE_UNSUPPORTED;
1995
1996         return 0;
1997 }
1998
1999 /* Following items will be read out to indicate current plpd policy:
2000  *  - -1: none
2001  *  - 0: disallow
2002  *  - 1: default
2003  *  - 2: optimized
2004  */
2005 static ssize_t amdgpu_get_xgmi_plpd_policy(struct device *dev,
2006                                            struct device_attribute *attr,
2007                                            char *buf)
2008 {
2009         struct drm_device *ddev = dev_get_drvdata(dev);
2010         struct amdgpu_device *adev = drm_to_adev(ddev);
2011         char *mode_desc = "none";
2012         int mode;
2013
2014         if (amdgpu_in_reset(adev))
2015                 return -EPERM;
2016         if (adev->in_suspend && !adev->in_runpm)
2017                 return -EPERM;
2018
2019         mode = amdgpu_dpm_get_xgmi_plpd_mode(adev, &mode_desc);
2020
2021         return sysfs_emit(buf, "%d: %s\n", mode, mode_desc);
2022 }
2023
2024 /* Following argument value is expected from user to change plpd policy
2025  *  - arg 0: disallow plpd
2026  *  - arg 1: default policy
2027  *  - arg 2: optimized policy
2028  */
2029 static ssize_t amdgpu_set_xgmi_plpd_policy(struct device *dev,
2030                                            struct device_attribute *attr,
2031                                            const char *buf, size_t count)
2032 {
2033         struct drm_device *ddev = dev_get_drvdata(dev);
2034         struct amdgpu_device *adev = drm_to_adev(ddev);
2035         int mode, ret;
2036
2037         if (amdgpu_in_reset(adev))
2038                 return -EPERM;
2039         if (adev->in_suspend && !adev->in_runpm)
2040                 return -EPERM;
2041
2042         ret = kstrtos32(buf, 0, &mode);
2043         if (ret)
2044                 return -EINVAL;
2045
2046         ret = pm_runtime_get_sync(ddev->dev);
2047         if (ret < 0) {
2048                 pm_runtime_put_autosuspend(ddev->dev);
2049                 return ret;
2050         }
2051
2052         ret = amdgpu_dpm_set_xgmi_plpd_mode(adev, mode);
2053
2054         pm_runtime_mark_last_busy(ddev->dev);
2055         pm_runtime_put_autosuspend(ddev->dev);
2056
2057         if (ret)
2058                 return ret;
2059
2060         return count;
2061 }
2062
2063 static struct amdgpu_device_attr amdgpu_device_attrs[] = {
2064         AMDGPU_DEVICE_ATTR_RW(power_dpm_state,                          ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF),
2065         AMDGPU_DEVICE_ATTR_RW(power_dpm_force_performance_level,        ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF),
2066         AMDGPU_DEVICE_ATTR_RO(pp_num_states,                            ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF),
2067         AMDGPU_DEVICE_ATTR_RO(pp_cur_state,                             ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF),
2068         AMDGPU_DEVICE_ATTR_RW(pp_force_state,                           ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF),
2069         AMDGPU_DEVICE_ATTR_RW(pp_table,                                 ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF),
2070         AMDGPU_DEVICE_ATTR_RW(pp_dpm_sclk,                              ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF),
2071         AMDGPU_DEVICE_ATTR_RW(pp_dpm_mclk,                              ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF),
2072         AMDGPU_DEVICE_ATTR_RW(pp_dpm_socclk,                            ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF),
2073         AMDGPU_DEVICE_ATTR_RW(pp_dpm_fclk,                              ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF),
2074         AMDGPU_DEVICE_ATTR_RW(pp_dpm_vclk,                              ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF),
2075         AMDGPU_DEVICE_ATTR_RW(pp_dpm_vclk1,                             ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF),
2076         AMDGPU_DEVICE_ATTR_RW(pp_dpm_dclk,                              ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF),
2077         AMDGPU_DEVICE_ATTR_RW(pp_dpm_dclk1,                             ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF),
2078         AMDGPU_DEVICE_ATTR_RW(pp_dpm_dcefclk,                           ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF),
2079         AMDGPU_DEVICE_ATTR_RW(pp_dpm_pcie,                              ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF),
2080         AMDGPU_DEVICE_ATTR_RW(pp_sclk_od,                               ATTR_FLAG_BASIC),
2081         AMDGPU_DEVICE_ATTR_RW(pp_mclk_od,                               ATTR_FLAG_BASIC),
2082         AMDGPU_DEVICE_ATTR_RW(pp_power_profile_mode,                    ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF),
2083         AMDGPU_DEVICE_ATTR_RW(pp_od_clk_voltage,                        ATTR_FLAG_BASIC),
2084         AMDGPU_DEVICE_ATTR_RO(gpu_busy_percent,                         ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF),
2085         AMDGPU_DEVICE_ATTR_RO(mem_busy_percent,                         ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF),
2086         AMDGPU_DEVICE_ATTR_RO(pcie_bw,                                  ATTR_FLAG_BASIC),
2087         AMDGPU_DEVICE_ATTR_RW(pp_features,                              ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF),
2088         AMDGPU_DEVICE_ATTR_RO(unique_id,                                ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF),
2089         AMDGPU_DEVICE_ATTR_RW(thermal_throttling_logging,               ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF),
2090         AMDGPU_DEVICE_ATTR_RW(apu_thermal_cap,                          ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF),
2091         AMDGPU_DEVICE_ATTR_RO(gpu_metrics,                              ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF),
2092         AMDGPU_DEVICE_ATTR_RO(smartshift_apu_power,                     ATTR_FLAG_BASIC,
2093                               .attr_update = ss_power_attr_update),
2094         AMDGPU_DEVICE_ATTR_RO(smartshift_dgpu_power,                    ATTR_FLAG_BASIC,
2095                               .attr_update = ss_power_attr_update),
2096         AMDGPU_DEVICE_ATTR_RW(smartshift_bias,                          ATTR_FLAG_BASIC,
2097                               .attr_update = ss_bias_attr_update),
2098         AMDGPU_DEVICE_ATTR_RW(xgmi_plpd_policy,                         ATTR_FLAG_BASIC),
2099 };
2100
2101 static int default_attr_update(struct amdgpu_device *adev, struct amdgpu_device_attr *attr,
2102                                uint32_t mask, enum amdgpu_device_attr_states *states)
2103 {
2104         struct device_attribute *dev_attr = &attr->dev_attr;
2105         uint32_t mp1_ver = amdgpu_ip_version(adev, MP1_HWIP, 0);
2106         uint32_t gc_ver = amdgpu_ip_version(adev, GC_HWIP, 0);
2107         const char *attr_name = dev_attr->attr.name;
2108
2109         if (!(attr->flags & mask)) {
2110                 *states = ATTR_STATE_UNSUPPORTED;
2111                 return 0;
2112         }
2113
2114 #define DEVICE_ATTR_IS(_name)   (!strcmp(attr_name, #_name))
2115
2116         if (DEVICE_ATTR_IS(pp_dpm_socclk)) {
2117                 if (gc_ver < IP_VERSION(9, 0, 0))
2118                         *states = ATTR_STATE_UNSUPPORTED;
2119         } else if (DEVICE_ATTR_IS(pp_dpm_dcefclk)) {
2120                 if (gc_ver < IP_VERSION(9, 0, 0) ||
2121                     !amdgpu_device_has_display_hardware(adev))
2122                         *states = ATTR_STATE_UNSUPPORTED;
2123         } else if (DEVICE_ATTR_IS(pp_dpm_fclk)) {
2124                 if (mp1_ver < IP_VERSION(10, 0, 0))
2125                         *states = ATTR_STATE_UNSUPPORTED;
2126         } else if (DEVICE_ATTR_IS(pp_od_clk_voltage)) {
2127                 *states = ATTR_STATE_UNSUPPORTED;
2128                 if (amdgpu_dpm_is_overdrive_supported(adev))
2129                         *states = ATTR_STATE_SUPPORTED;
2130         } else if (DEVICE_ATTR_IS(mem_busy_percent)) {
2131                 if ((adev->flags & AMD_IS_APU &&
2132                      gc_ver != IP_VERSION(9, 4, 3)) ||
2133                     gc_ver == IP_VERSION(9, 0, 1))
2134                         *states = ATTR_STATE_UNSUPPORTED;
2135         } else if (DEVICE_ATTR_IS(pcie_bw)) {
2136                 /* PCIe Perf counters won't work on APU nodes */
2137                 if (adev->flags & AMD_IS_APU)
2138                         *states = ATTR_STATE_UNSUPPORTED;
2139         } else if (DEVICE_ATTR_IS(unique_id)) {
2140                 switch (gc_ver) {
2141                 case IP_VERSION(9, 0, 1):
2142                 case IP_VERSION(9, 4, 0):
2143                 case IP_VERSION(9, 4, 1):
2144                 case IP_VERSION(9, 4, 2):
2145                 case IP_VERSION(9, 4, 3):
2146                 case IP_VERSION(10, 3, 0):
2147                 case IP_VERSION(11, 0, 0):
2148                 case IP_VERSION(11, 0, 1):
2149                 case IP_VERSION(11, 0, 2):
2150                 case IP_VERSION(11, 0, 3):
2151                         *states = ATTR_STATE_SUPPORTED;
2152                         break;
2153                 default:
2154                         *states = ATTR_STATE_UNSUPPORTED;
2155                 }
2156         } else if (DEVICE_ATTR_IS(pp_features)) {
2157                 if ((adev->flags & AMD_IS_APU &&
2158                      gc_ver != IP_VERSION(9, 4, 3)) ||
2159                     gc_ver < IP_VERSION(9, 0, 0))
2160                         *states = ATTR_STATE_UNSUPPORTED;
2161         } else if (DEVICE_ATTR_IS(gpu_metrics)) {
2162                 if (gc_ver < IP_VERSION(9, 1, 0))
2163                         *states = ATTR_STATE_UNSUPPORTED;
2164         } else if (DEVICE_ATTR_IS(pp_dpm_vclk)) {
2165                 if (!(gc_ver == IP_VERSION(10, 3, 1) ||
2166                       gc_ver == IP_VERSION(10, 3, 0) ||
2167                       gc_ver == IP_VERSION(10, 1, 2) ||
2168                       gc_ver == IP_VERSION(11, 0, 0) ||
2169                       gc_ver == IP_VERSION(11, 0, 2) ||
2170                       gc_ver == IP_VERSION(11, 0, 3) ||
2171                       gc_ver == IP_VERSION(9, 4, 3)))
2172                         *states = ATTR_STATE_UNSUPPORTED;
2173         } else if (DEVICE_ATTR_IS(pp_dpm_vclk1)) {
2174                 if (!((gc_ver == IP_VERSION(10, 3, 1) ||
2175                            gc_ver == IP_VERSION(10, 3, 0) ||
2176                            gc_ver == IP_VERSION(11, 0, 2) ||
2177                            gc_ver == IP_VERSION(11, 0, 3)) && adev->vcn.num_vcn_inst >= 2))
2178                         *states = ATTR_STATE_UNSUPPORTED;
2179         } else if (DEVICE_ATTR_IS(pp_dpm_dclk)) {
2180                 if (!(gc_ver == IP_VERSION(10, 3, 1) ||
2181                       gc_ver == IP_VERSION(10, 3, 0) ||
2182                       gc_ver == IP_VERSION(10, 1, 2) ||
2183                       gc_ver == IP_VERSION(11, 0, 0) ||
2184                       gc_ver == IP_VERSION(11, 0, 2) ||
2185                       gc_ver == IP_VERSION(11, 0, 3) ||
2186                       gc_ver == IP_VERSION(9, 4, 3)))
2187                         *states = ATTR_STATE_UNSUPPORTED;
2188         } else if (DEVICE_ATTR_IS(pp_dpm_dclk1)) {
2189                 if (!((gc_ver == IP_VERSION(10, 3, 1) ||
2190                            gc_ver == IP_VERSION(10, 3, 0) ||
2191                            gc_ver == IP_VERSION(11, 0, 2) ||
2192                            gc_ver == IP_VERSION(11, 0, 3)) && adev->vcn.num_vcn_inst >= 2))
2193                         *states = ATTR_STATE_UNSUPPORTED;
2194         } else if (DEVICE_ATTR_IS(pp_power_profile_mode)) {
2195                 if (amdgpu_dpm_get_power_profile_mode(adev, NULL) == -EOPNOTSUPP)
2196                         *states = ATTR_STATE_UNSUPPORTED;
2197                 else if ((gc_ver == IP_VERSION(10, 3, 0) ||
2198                           gc_ver == IP_VERSION(11, 0, 3)) && amdgpu_sriov_vf(adev))
2199                         *states = ATTR_STATE_UNSUPPORTED;
2200         } else if (DEVICE_ATTR_IS(xgmi_plpd_policy)) {
2201                 if (amdgpu_dpm_get_xgmi_plpd_mode(adev, NULL) == XGMI_PLPD_NONE)
2202                         *states = ATTR_STATE_UNSUPPORTED;
2203         } else if (DEVICE_ATTR_IS(pp_mclk_od)) {
2204                 if (amdgpu_dpm_get_mclk_od(adev) == -EOPNOTSUPP)
2205                         *states = ATTR_STATE_UNSUPPORTED;
2206         } else if (DEVICE_ATTR_IS(pp_sclk_od)) {
2207                 if (amdgpu_dpm_get_sclk_od(adev) == -EOPNOTSUPP)
2208                         *states = ATTR_STATE_UNSUPPORTED;
2209         } else if (DEVICE_ATTR_IS(apu_thermal_cap)) {
2210                 u32 limit;
2211
2212                 if (amdgpu_dpm_get_apu_thermal_limit(adev, &limit) ==
2213                     -EOPNOTSUPP)
2214                         *states = ATTR_STATE_UNSUPPORTED;
2215         } else if (DEVICE_ATTR_IS(pp_dpm_pcie)) {
2216                 if (gc_ver == IP_VERSION(9, 4, 2) ||
2217                     gc_ver == IP_VERSION(9, 4, 3))
2218                         *states = ATTR_STATE_UNSUPPORTED;
2219         }
2220
2221         switch (gc_ver) {
2222         case IP_VERSION(9, 4, 1):
2223         case IP_VERSION(9, 4, 2):
2224                 /* the Mi series card does not support standalone mclk/socclk/fclk level setting */
2225                 if (DEVICE_ATTR_IS(pp_dpm_mclk) ||
2226                     DEVICE_ATTR_IS(pp_dpm_socclk) ||
2227                     DEVICE_ATTR_IS(pp_dpm_fclk)) {
2228                         dev_attr->attr.mode &= ~S_IWUGO;
2229                         dev_attr->store = NULL;
2230                 }
2231                 break;
2232         case IP_VERSION(10, 3, 0):
2233                 if (DEVICE_ATTR_IS(power_dpm_force_performance_level) &&
2234                     amdgpu_sriov_vf(adev)) {
2235                         dev_attr->attr.mode &= ~0222;
2236                         dev_attr->store = NULL;
2237                 }
2238                 break;
2239         default:
2240                 break;
2241         }
2242
2243         if (DEVICE_ATTR_IS(pp_dpm_dcefclk)) {
2244                 /* SMU MP1 does not support dcefclk level setting */
2245                 if (gc_ver >= IP_VERSION(10, 0, 0)) {
2246                         dev_attr->attr.mode &= ~S_IWUGO;
2247                         dev_attr->store = NULL;
2248                 }
2249         }
2250
2251         /* setting should not be allowed from VF if not in one VF mode */
2252         if (amdgpu_sriov_vf(adev) && !amdgpu_sriov_is_pp_one_vf(adev)) {
2253                 dev_attr->attr.mode &= ~S_IWUGO;
2254                 dev_attr->store = NULL;
2255         }
2256
2257 #undef DEVICE_ATTR_IS
2258
2259         return 0;
2260 }
2261
2262
2263 static int amdgpu_device_attr_create(struct amdgpu_device *adev,
2264                                      struct amdgpu_device_attr *attr,
2265                                      uint32_t mask, struct list_head *attr_list)
2266 {
2267         int ret = 0;
2268         enum amdgpu_device_attr_states attr_states = ATTR_STATE_SUPPORTED;
2269         struct amdgpu_device_attr_entry *attr_entry;
2270         struct device_attribute *dev_attr;
2271         const char *name;
2272
2273         int (*attr_update)(struct amdgpu_device *adev, struct amdgpu_device_attr *attr,
2274                            uint32_t mask, enum amdgpu_device_attr_states *states) = default_attr_update;
2275
2276         if (!attr)
2277                 return -EINVAL;
2278
2279         dev_attr = &attr->dev_attr;
2280         name = dev_attr->attr.name;
2281
2282         attr_update = attr->attr_update ? attr->attr_update : default_attr_update;
2283
2284         ret = attr_update(adev, attr, mask, &attr_states);
2285         if (ret) {
2286                 dev_err(adev->dev, "failed to update device file %s, ret = %d\n",
2287                         name, ret);
2288                 return ret;
2289         }
2290
2291         if (attr_states == ATTR_STATE_UNSUPPORTED)
2292                 return 0;
2293
2294         ret = device_create_file(adev->dev, dev_attr);
2295         if (ret) {
2296                 dev_err(adev->dev, "failed to create device file %s, ret = %d\n",
2297                         name, ret);
2298         }
2299
2300         attr_entry = kmalloc(sizeof(*attr_entry), GFP_KERNEL);
2301         if (!attr_entry)
2302                 return -ENOMEM;
2303
2304         attr_entry->attr = attr;
2305         INIT_LIST_HEAD(&attr_entry->entry);
2306
2307         list_add_tail(&attr_entry->entry, attr_list);
2308
2309         return ret;
2310 }
2311
2312 static void amdgpu_device_attr_remove(struct amdgpu_device *adev, struct amdgpu_device_attr *attr)
2313 {
2314         struct device_attribute *dev_attr = &attr->dev_attr;
2315
2316         device_remove_file(adev->dev, dev_attr);
2317 }
2318
2319 static void amdgpu_device_attr_remove_groups(struct amdgpu_device *adev,
2320                                              struct list_head *attr_list);
2321
2322 static int amdgpu_device_attr_create_groups(struct amdgpu_device *adev,
2323                                             struct amdgpu_device_attr *attrs,
2324                                             uint32_t counts,
2325                                             uint32_t mask,
2326                                             struct list_head *attr_list)
2327 {
2328         int ret = 0;
2329         uint32_t i = 0;
2330
2331         for (i = 0; i < counts; i++) {
2332                 ret = amdgpu_device_attr_create(adev, &attrs[i], mask, attr_list);
2333                 if (ret)
2334                         goto failed;
2335         }
2336
2337         return 0;
2338
2339 failed:
2340         amdgpu_device_attr_remove_groups(adev, attr_list);
2341
2342         return ret;
2343 }
2344
2345 static void amdgpu_device_attr_remove_groups(struct amdgpu_device *adev,
2346                                              struct list_head *attr_list)
2347 {
2348         struct amdgpu_device_attr_entry *entry, *entry_tmp;
2349
2350         if (list_empty(attr_list))
2351                 return ;
2352
2353         list_for_each_entry_safe(entry, entry_tmp, attr_list, entry) {
2354                 amdgpu_device_attr_remove(adev, entry->attr);
2355                 list_del(&entry->entry);
2356                 kfree(entry);
2357         }
2358 }
2359
2360 static ssize_t amdgpu_hwmon_show_temp(struct device *dev,
2361                                       struct device_attribute *attr,
2362                                       char *buf)
2363 {
2364         struct amdgpu_device *adev = dev_get_drvdata(dev);
2365         int channel = to_sensor_dev_attr(attr)->index;
2366         int r, temp = 0;
2367
2368         if (channel >= PP_TEMP_MAX)
2369                 return -EINVAL;
2370
2371         switch (channel) {
2372         case PP_TEMP_JUNCTION:
2373                 /* get current junction temperature */
2374                 r = amdgpu_hwmon_get_sensor_generic(adev, AMDGPU_PP_SENSOR_HOTSPOT_TEMP,
2375                                            (void *)&temp);
2376                 break;
2377         case PP_TEMP_EDGE:
2378                 /* get current edge temperature */
2379                 r = amdgpu_hwmon_get_sensor_generic(adev, AMDGPU_PP_SENSOR_EDGE_TEMP,
2380                                            (void *)&temp);
2381                 break;
2382         case PP_TEMP_MEM:
2383                 /* get current memory temperature */
2384                 r = amdgpu_hwmon_get_sensor_generic(adev, AMDGPU_PP_SENSOR_MEM_TEMP,
2385                                            (void *)&temp);
2386                 break;
2387         default:
2388                 r = -EINVAL;
2389                 break;
2390         }
2391
2392         if (r)
2393                 return r;
2394
2395         return sysfs_emit(buf, "%d\n", temp);
2396 }
2397
2398 static ssize_t amdgpu_hwmon_show_temp_thresh(struct device *dev,
2399                                              struct device_attribute *attr,
2400                                              char *buf)
2401 {
2402         struct amdgpu_device *adev = dev_get_drvdata(dev);
2403         int hyst = to_sensor_dev_attr(attr)->index;
2404         int temp;
2405
2406         if (hyst)
2407                 temp = adev->pm.dpm.thermal.min_temp;
2408         else
2409                 temp = adev->pm.dpm.thermal.max_temp;
2410
2411         return sysfs_emit(buf, "%d\n", temp);
2412 }
2413
2414 static ssize_t amdgpu_hwmon_show_hotspot_temp_thresh(struct device *dev,
2415                                              struct device_attribute *attr,
2416                                              char *buf)
2417 {
2418         struct amdgpu_device *adev = dev_get_drvdata(dev);
2419         int hyst = to_sensor_dev_attr(attr)->index;
2420         int temp;
2421
2422         if (hyst)
2423                 temp = adev->pm.dpm.thermal.min_hotspot_temp;
2424         else
2425                 temp = adev->pm.dpm.thermal.max_hotspot_crit_temp;
2426
2427         return sysfs_emit(buf, "%d\n", temp);
2428 }
2429
2430 static ssize_t amdgpu_hwmon_show_mem_temp_thresh(struct device *dev,
2431                                              struct device_attribute *attr,
2432                                              char *buf)
2433 {
2434         struct amdgpu_device *adev = dev_get_drvdata(dev);
2435         int hyst = to_sensor_dev_attr(attr)->index;
2436         int temp;
2437
2438         if (hyst)
2439                 temp = adev->pm.dpm.thermal.min_mem_temp;
2440         else
2441                 temp = adev->pm.dpm.thermal.max_mem_crit_temp;
2442
2443         return sysfs_emit(buf, "%d\n", temp);
2444 }
2445
2446 static ssize_t amdgpu_hwmon_show_temp_label(struct device *dev,
2447                                              struct device_attribute *attr,
2448                                              char *buf)
2449 {
2450         int channel = to_sensor_dev_attr(attr)->index;
2451
2452         if (channel >= PP_TEMP_MAX)
2453                 return -EINVAL;
2454
2455         return sysfs_emit(buf, "%s\n", temp_label[channel].label);
2456 }
2457
2458 static ssize_t amdgpu_hwmon_show_temp_emergency(struct device *dev,
2459                                              struct device_attribute *attr,
2460                                              char *buf)
2461 {
2462         struct amdgpu_device *adev = dev_get_drvdata(dev);
2463         int channel = to_sensor_dev_attr(attr)->index;
2464         int temp = 0;
2465
2466         if (channel >= PP_TEMP_MAX)
2467                 return -EINVAL;
2468
2469         switch (channel) {
2470         case PP_TEMP_JUNCTION:
2471                 temp = adev->pm.dpm.thermal.max_hotspot_emergency_temp;
2472                 break;
2473         case PP_TEMP_EDGE:
2474                 temp = adev->pm.dpm.thermal.max_edge_emergency_temp;
2475                 break;
2476         case PP_TEMP_MEM:
2477                 temp = adev->pm.dpm.thermal.max_mem_emergency_temp;
2478                 break;
2479         }
2480
2481         return sysfs_emit(buf, "%d\n", temp);
2482 }
2483
2484 static ssize_t amdgpu_hwmon_get_pwm1_enable(struct device *dev,
2485                                             struct device_attribute *attr,
2486                                             char *buf)
2487 {
2488         struct amdgpu_device *adev = dev_get_drvdata(dev);
2489         u32 pwm_mode = 0;
2490         int ret;
2491
2492         if (amdgpu_in_reset(adev))
2493                 return -EPERM;
2494         if (adev->in_suspend && !adev->in_runpm)
2495                 return -EPERM;
2496
2497         ret = pm_runtime_get_sync(adev_to_drm(adev)->dev);
2498         if (ret < 0) {
2499                 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
2500                 return ret;
2501         }
2502
2503         ret = amdgpu_dpm_get_fan_control_mode(adev, &pwm_mode);
2504
2505         pm_runtime_mark_last_busy(adev_to_drm(adev)->dev);
2506         pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
2507
2508         if (ret)
2509                 return -EINVAL;
2510
2511         return sysfs_emit(buf, "%u\n", pwm_mode);
2512 }
2513
2514 static ssize_t amdgpu_hwmon_set_pwm1_enable(struct device *dev,
2515                                             struct device_attribute *attr,
2516                                             const char *buf,
2517                                             size_t count)
2518 {
2519         struct amdgpu_device *adev = dev_get_drvdata(dev);
2520         int err, ret;
2521         int value;
2522
2523         if (amdgpu_in_reset(adev))
2524                 return -EPERM;
2525         if (adev->in_suspend && !adev->in_runpm)
2526                 return -EPERM;
2527
2528         err = kstrtoint(buf, 10, &value);
2529         if (err)
2530                 return err;
2531
2532         ret = pm_runtime_get_sync(adev_to_drm(adev)->dev);
2533         if (ret < 0) {
2534                 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
2535                 return ret;
2536         }
2537
2538         ret = amdgpu_dpm_set_fan_control_mode(adev, value);
2539
2540         pm_runtime_mark_last_busy(adev_to_drm(adev)->dev);
2541         pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
2542
2543         if (ret)
2544                 return -EINVAL;
2545
2546         return count;
2547 }
2548
2549 static ssize_t amdgpu_hwmon_get_pwm1_min(struct device *dev,
2550                                          struct device_attribute *attr,
2551                                          char *buf)
2552 {
2553         return sysfs_emit(buf, "%i\n", 0);
2554 }
2555
2556 static ssize_t amdgpu_hwmon_get_pwm1_max(struct device *dev,
2557                                          struct device_attribute *attr,
2558                                          char *buf)
2559 {
2560         return sysfs_emit(buf, "%i\n", 255);
2561 }
2562
2563 static ssize_t amdgpu_hwmon_set_pwm1(struct device *dev,
2564                                      struct device_attribute *attr,
2565                                      const char *buf, size_t count)
2566 {
2567         struct amdgpu_device *adev = dev_get_drvdata(dev);
2568         int err;
2569         u32 value;
2570         u32 pwm_mode;
2571
2572         if (amdgpu_in_reset(adev))
2573                 return -EPERM;
2574         if (adev->in_suspend && !adev->in_runpm)
2575                 return -EPERM;
2576
2577         err = kstrtou32(buf, 10, &value);
2578         if (err)
2579                 return err;
2580
2581         err = pm_runtime_get_sync(adev_to_drm(adev)->dev);
2582         if (err < 0) {
2583                 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
2584                 return err;
2585         }
2586
2587         err = amdgpu_dpm_get_fan_control_mode(adev, &pwm_mode);
2588         if (err)
2589                 goto out;
2590
2591         if (pwm_mode != AMD_FAN_CTRL_MANUAL) {
2592                 pr_info("manual fan speed control should be enabled first\n");
2593                 err = -EINVAL;
2594                 goto out;
2595         }
2596
2597         err = amdgpu_dpm_set_fan_speed_pwm(adev, value);
2598
2599 out:
2600         pm_runtime_mark_last_busy(adev_to_drm(adev)->dev);
2601         pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
2602
2603         if (err)
2604                 return err;
2605
2606         return count;
2607 }
2608
2609 static ssize_t amdgpu_hwmon_get_pwm1(struct device *dev,
2610                                      struct device_attribute *attr,
2611                                      char *buf)
2612 {
2613         struct amdgpu_device *adev = dev_get_drvdata(dev);
2614         int err;
2615         u32 speed = 0;
2616
2617         if (amdgpu_in_reset(adev))
2618                 return -EPERM;
2619         if (adev->in_suspend && !adev->in_runpm)
2620                 return -EPERM;
2621
2622         err = pm_runtime_get_sync(adev_to_drm(adev)->dev);
2623         if (err < 0) {
2624                 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
2625                 return err;
2626         }
2627
2628         err = amdgpu_dpm_get_fan_speed_pwm(adev, &speed);
2629
2630         pm_runtime_mark_last_busy(adev_to_drm(adev)->dev);
2631         pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
2632
2633         if (err)
2634                 return err;
2635
2636         return sysfs_emit(buf, "%i\n", speed);
2637 }
2638
2639 static ssize_t amdgpu_hwmon_get_fan1_input(struct device *dev,
2640                                            struct device_attribute *attr,
2641                                            char *buf)
2642 {
2643         struct amdgpu_device *adev = dev_get_drvdata(dev);
2644         int err;
2645         u32 speed = 0;
2646
2647         if (amdgpu_in_reset(adev))
2648                 return -EPERM;
2649         if (adev->in_suspend && !adev->in_runpm)
2650                 return -EPERM;
2651
2652         err = pm_runtime_get_sync(adev_to_drm(adev)->dev);
2653         if (err < 0) {
2654                 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
2655                 return err;
2656         }
2657
2658         err = amdgpu_dpm_get_fan_speed_rpm(adev, &speed);
2659
2660         pm_runtime_mark_last_busy(adev_to_drm(adev)->dev);
2661         pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
2662
2663         if (err)
2664                 return err;
2665
2666         return sysfs_emit(buf, "%i\n", speed);
2667 }
2668
2669 static ssize_t amdgpu_hwmon_get_fan1_min(struct device *dev,
2670                                          struct device_attribute *attr,
2671                                          char *buf)
2672 {
2673         struct amdgpu_device *adev = dev_get_drvdata(dev);
2674         u32 min_rpm = 0;
2675         int r;
2676
2677         r = amdgpu_hwmon_get_sensor_generic(adev, AMDGPU_PP_SENSOR_MIN_FAN_RPM,
2678                                    (void *)&min_rpm);
2679
2680         if (r)
2681                 return r;
2682
2683         return sysfs_emit(buf, "%d\n", min_rpm);
2684 }
2685
2686 static ssize_t amdgpu_hwmon_get_fan1_max(struct device *dev,
2687                                          struct device_attribute *attr,
2688                                          char *buf)
2689 {
2690         struct amdgpu_device *adev = dev_get_drvdata(dev);
2691         u32 max_rpm = 0;
2692         int r;
2693
2694         r = amdgpu_hwmon_get_sensor_generic(adev, AMDGPU_PP_SENSOR_MAX_FAN_RPM,
2695                                    (void *)&max_rpm);
2696
2697         if (r)
2698                 return r;
2699
2700         return sysfs_emit(buf, "%d\n", max_rpm);
2701 }
2702
2703 static ssize_t amdgpu_hwmon_get_fan1_target(struct device *dev,
2704                                            struct device_attribute *attr,
2705                                            char *buf)
2706 {
2707         struct amdgpu_device *adev = dev_get_drvdata(dev);
2708         int err;
2709         u32 rpm = 0;
2710
2711         if (amdgpu_in_reset(adev))
2712                 return -EPERM;
2713         if (adev->in_suspend && !adev->in_runpm)
2714                 return -EPERM;
2715
2716         err = pm_runtime_get_sync(adev_to_drm(adev)->dev);
2717         if (err < 0) {
2718                 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
2719                 return err;
2720         }
2721
2722         err = amdgpu_dpm_get_fan_speed_rpm(adev, &rpm);
2723
2724         pm_runtime_mark_last_busy(adev_to_drm(adev)->dev);
2725         pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
2726
2727         if (err)
2728                 return err;
2729
2730         return sysfs_emit(buf, "%i\n", rpm);
2731 }
2732
2733 static ssize_t amdgpu_hwmon_set_fan1_target(struct device *dev,
2734                                      struct device_attribute *attr,
2735                                      const char *buf, size_t count)
2736 {
2737         struct amdgpu_device *adev = dev_get_drvdata(dev);
2738         int err;
2739         u32 value;
2740         u32 pwm_mode;
2741
2742         if (amdgpu_in_reset(adev))
2743                 return -EPERM;
2744         if (adev->in_suspend && !adev->in_runpm)
2745                 return -EPERM;
2746
2747         err = kstrtou32(buf, 10, &value);
2748         if (err)
2749                 return err;
2750
2751         err = pm_runtime_get_sync(adev_to_drm(adev)->dev);
2752         if (err < 0) {
2753                 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
2754                 return err;
2755         }
2756
2757         err = amdgpu_dpm_get_fan_control_mode(adev, &pwm_mode);
2758         if (err)
2759                 goto out;
2760
2761         if (pwm_mode != AMD_FAN_CTRL_MANUAL) {
2762                 err = -ENODATA;
2763                 goto out;
2764         }
2765
2766         err = amdgpu_dpm_set_fan_speed_rpm(adev, value);
2767
2768 out:
2769         pm_runtime_mark_last_busy(adev_to_drm(adev)->dev);
2770         pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
2771
2772         if (err)
2773                 return err;
2774
2775         return count;
2776 }
2777
2778 static ssize_t amdgpu_hwmon_get_fan1_enable(struct device *dev,
2779                                             struct device_attribute *attr,
2780                                             char *buf)
2781 {
2782         struct amdgpu_device *adev = dev_get_drvdata(dev);
2783         u32 pwm_mode = 0;
2784         int ret;
2785
2786         if (amdgpu_in_reset(adev))
2787                 return -EPERM;
2788         if (adev->in_suspend && !adev->in_runpm)
2789                 return -EPERM;
2790
2791         ret = pm_runtime_get_sync(adev_to_drm(adev)->dev);
2792         if (ret < 0) {
2793                 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
2794                 return ret;
2795         }
2796
2797         ret = amdgpu_dpm_get_fan_control_mode(adev, &pwm_mode);
2798
2799         pm_runtime_mark_last_busy(adev_to_drm(adev)->dev);
2800         pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
2801
2802         if (ret)
2803                 return -EINVAL;
2804
2805         return sysfs_emit(buf, "%i\n", pwm_mode == AMD_FAN_CTRL_AUTO ? 0 : 1);
2806 }
2807
2808 static ssize_t amdgpu_hwmon_set_fan1_enable(struct device *dev,
2809                                             struct device_attribute *attr,
2810                                             const char *buf,
2811                                             size_t count)
2812 {
2813         struct amdgpu_device *adev = dev_get_drvdata(dev);
2814         int err;
2815         int value;
2816         u32 pwm_mode;
2817
2818         if (amdgpu_in_reset(adev))
2819                 return -EPERM;
2820         if (adev->in_suspend && !adev->in_runpm)
2821                 return -EPERM;
2822
2823         err = kstrtoint(buf, 10, &value);
2824         if (err)
2825                 return err;
2826
2827         if (value == 0)
2828                 pwm_mode = AMD_FAN_CTRL_AUTO;
2829         else if (value == 1)
2830                 pwm_mode = AMD_FAN_CTRL_MANUAL;
2831         else
2832                 return -EINVAL;
2833
2834         err = pm_runtime_get_sync(adev_to_drm(adev)->dev);
2835         if (err < 0) {
2836                 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
2837                 return err;
2838         }
2839
2840         err = amdgpu_dpm_set_fan_control_mode(adev, pwm_mode);
2841
2842         pm_runtime_mark_last_busy(adev_to_drm(adev)->dev);
2843         pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
2844
2845         if (err)
2846                 return -EINVAL;
2847
2848         return count;
2849 }
2850
2851 static ssize_t amdgpu_hwmon_show_vddgfx(struct device *dev,
2852                                         struct device_attribute *attr,
2853                                         char *buf)
2854 {
2855         struct amdgpu_device *adev = dev_get_drvdata(dev);
2856         u32 vddgfx;
2857         int r;
2858
2859         /* get the voltage */
2860         r = amdgpu_hwmon_get_sensor_generic(adev, AMDGPU_PP_SENSOR_VDDGFX,
2861                                    (void *)&vddgfx);
2862         if (r)
2863                 return r;
2864
2865         return sysfs_emit(buf, "%d\n", vddgfx);
2866 }
2867
2868 static ssize_t amdgpu_hwmon_show_vddgfx_label(struct device *dev,
2869                                               struct device_attribute *attr,
2870                                               char *buf)
2871 {
2872         return sysfs_emit(buf, "vddgfx\n");
2873 }
2874
2875 static ssize_t amdgpu_hwmon_show_vddnb(struct device *dev,
2876                                        struct device_attribute *attr,
2877                                        char *buf)
2878 {
2879         struct amdgpu_device *adev = dev_get_drvdata(dev);
2880         u32 vddnb;
2881         int r;
2882
2883         /* only APUs have vddnb */
2884         if  (!(adev->flags & AMD_IS_APU))
2885                 return -EINVAL;
2886
2887         /* get the voltage */
2888         r = amdgpu_hwmon_get_sensor_generic(adev, AMDGPU_PP_SENSOR_VDDNB,
2889                                    (void *)&vddnb);
2890         if (r)
2891                 return r;
2892
2893         return sysfs_emit(buf, "%d\n", vddnb);
2894 }
2895
2896 static ssize_t amdgpu_hwmon_show_vddnb_label(struct device *dev,
2897                                               struct device_attribute *attr,
2898                                               char *buf)
2899 {
2900         return sysfs_emit(buf, "vddnb\n");
2901 }
2902
2903 static int amdgpu_hwmon_get_power(struct device *dev,
2904                                   enum amd_pp_sensors sensor)
2905 {
2906         struct amdgpu_device *adev = dev_get_drvdata(dev);
2907         unsigned int uw;
2908         u32 query = 0;
2909         int r;
2910
2911         r = amdgpu_hwmon_get_sensor_generic(adev, sensor, (void *)&query);
2912         if (r)
2913                 return r;
2914
2915         /* convert to microwatts */
2916         uw = (query >> 8) * 1000000 + (query & 0xff) * 1000;
2917
2918         return uw;
2919 }
2920
2921 static ssize_t amdgpu_hwmon_show_power_avg(struct device *dev,
2922                                            struct device_attribute *attr,
2923                                            char *buf)
2924 {
2925         ssize_t val;
2926
2927         val = amdgpu_hwmon_get_power(dev, AMDGPU_PP_SENSOR_GPU_AVG_POWER);
2928         if (val < 0)
2929                 return val;
2930
2931         return sysfs_emit(buf, "%zd\n", val);
2932 }
2933
2934 static ssize_t amdgpu_hwmon_show_power_input(struct device *dev,
2935                                              struct device_attribute *attr,
2936                                              char *buf)
2937 {
2938         ssize_t val;
2939
2940         val = amdgpu_hwmon_get_power(dev, AMDGPU_PP_SENSOR_GPU_INPUT_POWER);
2941         if (val < 0)
2942                 return val;
2943
2944         return sysfs_emit(buf, "%zd\n", val);
2945 }
2946
2947 static ssize_t amdgpu_hwmon_show_power_cap_generic(struct device *dev,
2948                                         struct device_attribute *attr,
2949                                         char *buf,
2950                                         enum pp_power_limit_level pp_limit_level)
2951 {
2952         struct amdgpu_device *adev = dev_get_drvdata(dev);
2953         enum pp_power_type power_type = to_sensor_dev_attr(attr)->index;
2954         uint32_t limit;
2955         ssize_t size;
2956         int r;
2957
2958         if (amdgpu_in_reset(adev))
2959                 return -EPERM;
2960         if (adev->in_suspend && !adev->in_runpm)
2961                 return -EPERM;
2962
2963         r = pm_runtime_get_sync(adev_to_drm(adev)->dev);
2964         if (r < 0) {
2965                 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
2966                 return r;
2967         }
2968
2969         r = amdgpu_dpm_get_power_limit(adev, &limit,
2970                                       pp_limit_level, power_type);
2971
2972         if (!r)
2973                 size = sysfs_emit(buf, "%u\n", limit * 1000000);
2974         else
2975                 size = sysfs_emit(buf, "\n");
2976
2977         pm_runtime_mark_last_busy(adev_to_drm(adev)->dev);
2978         pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
2979
2980         return size;
2981 }
2982
2983 static ssize_t amdgpu_hwmon_show_power_cap_min(struct device *dev,
2984                                          struct device_attribute *attr,
2985                                          char *buf)
2986 {
2987         return amdgpu_hwmon_show_power_cap_generic(dev, attr, buf, PP_PWR_LIMIT_MIN);
2988 }
2989
2990 static ssize_t amdgpu_hwmon_show_power_cap_max(struct device *dev,
2991                                          struct device_attribute *attr,
2992                                          char *buf)
2993 {
2994         return amdgpu_hwmon_show_power_cap_generic(dev, attr, buf, PP_PWR_LIMIT_MAX);
2995
2996 }
2997
2998 static ssize_t amdgpu_hwmon_show_power_cap(struct device *dev,
2999                                          struct device_attribute *attr,
3000                                          char *buf)
3001 {
3002         return amdgpu_hwmon_show_power_cap_generic(dev, attr, buf, PP_PWR_LIMIT_CURRENT);
3003
3004 }
3005
3006 static ssize_t amdgpu_hwmon_show_power_cap_default(struct device *dev,
3007                                          struct device_attribute *attr,
3008                                          char *buf)
3009 {
3010         return amdgpu_hwmon_show_power_cap_generic(dev, attr, buf, PP_PWR_LIMIT_DEFAULT);
3011
3012 }
3013
3014 static ssize_t amdgpu_hwmon_show_power_label(struct device *dev,
3015                                          struct device_attribute *attr,
3016                                          char *buf)
3017 {
3018         struct amdgpu_device *adev = dev_get_drvdata(dev);
3019         uint32_t gc_ver = amdgpu_ip_version(adev, GC_HWIP, 0);
3020
3021         if (gc_ver == IP_VERSION(10, 3, 1))
3022                 return sysfs_emit(buf, "%s\n",
3023                                   to_sensor_dev_attr(attr)->index == PP_PWR_TYPE_FAST ?
3024                                   "fastPPT" : "slowPPT");
3025         else
3026                 return sysfs_emit(buf, "PPT\n");
3027 }
3028
3029 static ssize_t amdgpu_hwmon_set_power_cap(struct device *dev,
3030                 struct device_attribute *attr,
3031                 const char *buf,
3032                 size_t count)
3033 {
3034         struct amdgpu_device *adev = dev_get_drvdata(dev);
3035         int limit_type = to_sensor_dev_attr(attr)->index;
3036         int err;
3037         u32 value;
3038
3039         if (amdgpu_in_reset(adev))
3040                 return -EPERM;
3041         if (adev->in_suspend && !adev->in_runpm)
3042                 return -EPERM;
3043
3044         if (amdgpu_sriov_vf(adev))
3045                 return -EINVAL;
3046
3047         err = kstrtou32(buf, 10, &value);
3048         if (err)
3049                 return err;
3050
3051         value = value / 1000000; /* convert to Watt */
3052         value |= limit_type << 24;
3053
3054         err = pm_runtime_get_sync(adev_to_drm(adev)->dev);
3055         if (err < 0) {
3056                 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
3057                 return err;
3058         }
3059
3060         err = amdgpu_dpm_set_power_limit(adev, value);
3061
3062         pm_runtime_mark_last_busy(adev_to_drm(adev)->dev);
3063         pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
3064
3065         if (err)
3066                 return err;
3067
3068         return count;
3069 }
3070
3071 static ssize_t amdgpu_hwmon_show_sclk(struct device *dev,
3072                                       struct device_attribute *attr,
3073                                       char *buf)
3074 {
3075         struct amdgpu_device *adev = dev_get_drvdata(dev);
3076         uint32_t sclk;
3077         int r;
3078
3079         /* get the sclk */
3080         r = amdgpu_hwmon_get_sensor_generic(adev, AMDGPU_PP_SENSOR_GFX_SCLK,
3081                                    (void *)&sclk);
3082         if (r)
3083                 return r;
3084
3085         return sysfs_emit(buf, "%u\n", sclk * 10 * 1000);
3086 }
3087
3088 static ssize_t amdgpu_hwmon_show_sclk_label(struct device *dev,
3089                                             struct device_attribute *attr,
3090                                             char *buf)
3091 {
3092         return sysfs_emit(buf, "sclk\n");
3093 }
3094
3095 static ssize_t amdgpu_hwmon_show_mclk(struct device *dev,
3096                                       struct device_attribute *attr,
3097                                       char *buf)
3098 {
3099         struct amdgpu_device *adev = dev_get_drvdata(dev);
3100         uint32_t mclk;
3101         int r;
3102
3103         /* get the sclk */
3104         r = amdgpu_hwmon_get_sensor_generic(adev, AMDGPU_PP_SENSOR_GFX_MCLK,
3105                                    (void *)&mclk);
3106         if (r)
3107                 return r;
3108
3109         return sysfs_emit(buf, "%u\n", mclk * 10 * 1000);
3110 }
3111
3112 static ssize_t amdgpu_hwmon_show_mclk_label(struct device *dev,
3113                                             struct device_attribute *attr,
3114                                             char *buf)
3115 {
3116         return sysfs_emit(buf, "mclk\n");
3117 }
3118
3119 /**
3120  * DOC: hwmon
3121  *
3122  * The amdgpu driver exposes the following sensor interfaces:
3123  *
3124  * - GPU temperature (via the on-die sensor)
3125  *
3126  * - GPU voltage
3127  *
3128  * - Northbridge voltage (APUs only)
3129  *
3130  * - GPU power
3131  *
3132  * - GPU fan
3133  *
3134  * - GPU gfx/compute engine clock
3135  *
3136  * - GPU memory clock (dGPU only)
3137  *
3138  * hwmon interfaces for GPU temperature:
3139  *
3140  * - temp[1-3]_input: the on die GPU temperature in millidegrees Celsius
3141  *   - temp2_input and temp3_input are supported on SOC15 dGPUs only
3142  *
3143  * - temp[1-3]_label: temperature channel label
3144  *   - temp2_label and temp3_label are supported on SOC15 dGPUs only
3145  *
3146  * - temp[1-3]_crit: temperature critical max value in millidegrees Celsius
3147  *   - temp2_crit and temp3_crit are supported on SOC15 dGPUs only
3148  *
3149  * - temp[1-3]_crit_hyst: temperature hysteresis for critical limit in millidegrees Celsius
3150  *   - temp2_crit_hyst and temp3_crit_hyst are supported on SOC15 dGPUs only
3151  *
3152  * - temp[1-3]_emergency: temperature emergency max value(asic shutdown) in millidegrees Celsius
3153  *   - these are supported on SOC15 dGPUs only
3154  *
3155  * hwmon interfaces for GPU voltage:
3156  *
3157  * - in0_input: the voltage on the GPU in millivolts
3158  *
3159  * - in1_input: the voltage on the Northbridge in millivolts
3160  *
3161  * hwmon interfaces for GPU power:
3162  *
3163  * - power1_average: average power used by the SoC in microWatts.  On APUs this includes the CPU.
3164  *
3165  * - power1_input: instantaneous power used by the SoC in microWatts.  On APUs this includes the CPU.
3166  *
3167  * - power1_cap_min: minimum cap supported in microWatts
3168  *
3169  * - power1_cap_max: maximum cap supported in microWatts
3170  *
3171  * - power1_cap: selected power cap in microWatts
3172  *
3173  * hwmon interfaces for GPU fan:
3174  *
3175  * - pwm1: pulse width modulation fan level (0-255)
3176  *
3177  * - pwm1_enable: pulse width modulation fan control method (0: no fan speed control, 1: manual fan speed control using pwm interface, 2: automatic fan speed control)
3178  *
3179  * - pwm1_min: pulse width modulation fan control minimum level (0)
3180  *
3181  * - pwm1_max: pulse width modulation fan control maximum level (255)
3182  *
3183  * - fan1_min: a minimum value Unit: revolution/min (RPM)
3184  *
3185  * - fan1_max: a maximum value Unit: revolution/max (RPM)
3186  *
3187  * - fan1_input: fan speed in RPM
3188  *
3189  * - fan[1-\*]_target: Desired fan speed Unit: revolution/min (RPM)
3190  *
3191  * - fan[1-\*]_enable: Enable or disable the sensors.1: Enable 0: Disable
3192  *
3193  * NOTE: DO NOT set the fan speed via "pwm1" and "fan[1-\*]_target" interfaces at the same time.
3194  *       That will get the former one overridden.
3195  *
3196  * hwmon interfaces for GPU clocks:
3197  *
3198  * - freq1_input: the gfx/compute clock in hertz
3199  *
3200  * - freq2_input: the memory clock in hertz
3201  *
3202  * You can use hwmon tools like sensors to view this information on your system.
3203  *
3204  */
3205
3206 static SENSOR_DEVICE_ATTR(temp1_input, S_IRUGO, amdgpu_hwmon_show_temp, NULL, PP_TEMP_EDGE);
3207 static SENSOR_DEVICE_ATTR(temp1_crit, S_IRUGO, amdgpu_hwmon_show_temp_thresh, NULL, 0);
3208 static SENSOR_DEVICE_ATTR(temp1_crit_hyst, S_IRUGO, amdgpu_hwmon_show_temp_thresh, NULL, 1);
3209 static SENSOR_DEVICE_ATTR(temp1_emergency, S_IRUGO, amdgpu_hwmon_show_temp_emergency, NULL, PP_TEMP_EDGE);
3210 static SENSOR_DEVICE_ATTR(temp2_input, S_IRUGO, amdgpu_hwmon_show_temp, NULL, PP_TEMP_JUNCTION);
3211 static SENSOR_DEVICE_ATTR(temp2_crit, S_IRUGO, amdgpu_hwmon_show_hotspot_temp_thresh, NULL, 0);
3212 static SENSOR_DEVICE_ATTR(temp2_crit_hyst, S_IRUGO, amdgpu_hwmon_show_hotspot_temp_thresh, NULL, 1);
3213 static SENSOR_DEVICE_ATTR(temp2_emergency, S_IRUGO, amdgpu_hwmon_show_temp_emergency, NULL, PP_TEMP_JUNCTION);
3214 static SENSOR_DEVICE_ATTR(temp3_input, S_IRUGO, amdgpu_hwmon_show_temp, NULL, PP_TEMP_MEM);
3215 static SENSOR_DEVICE_ATTR(temp3_crit, S_IRUGO, amdgpu_hwmon_show_mem_temp_thresh, NULL, 0);
3216 static SENSOR_DEVICE_ATTR(temp3_crit_hyst, S_IRUGO, amdgpu_hwmon_show_mem_temp_thresh, NULL, 1);
3217 static SENSOR_DEVICE_ATTR(temp3_emergency, S_IRUGO, amdgpu_hwmon_show_temp_emergency, NULL, PP_TEMP_MEM);
3218 static SENSOR_DEVICE_ATTR(temp1_label, S_IRUGO, amdgpu_hwmon_show_temp_label, NULL, PP_TEMP_EDGE);
3219 static SENSOR_DEVICE_ATTR(temp2_label, S_IRUGO, amdgpu_hwmon_show_temp_label, NULL, PP_TEMP_JUNCTION);
3220 static SENSOR_DEVICE_ATTR(temp3_label, S_IRUGO, amdgpu_hwmon_show_temp_label, NULL, PP_TEMP_MEM);
3221 static SENSOR_DEVICE_ATTR(pwm1, S_IRUGO | S_IWUSR, amdgpu_hwmon_get_pwm1, amdgpu_hwmon_set_pwm1, 0);
3222 static SENSOR_DEVICE_ATTR(pwm1_enable, S_IRUGO | S_IWUSR, amdgpu_hwmon_get_pwm1_enable, amdgpu_hwmon_set_pwm1_enable, 0);
3223 static SENSOR_DEVICE_ATTR(pwm1_min, S_IRUGO, amdgpu_hwmon_get_pwm1_min, NULL, 0);
3224 static SENSOR_DEVICE_ATTR(pwm1_max, S_IRUGO, amdgpu_hwmon_get_pwm1_max, NULL, 0);
3225 static SENSOR_DEVICE_ATTR(fan1_input, S_IRUGO, amdgpu_hwmon_get_fan1_input, NULL, 0);
3226 static SENSOR_DEVICE_ATTR(fan1_min, S_IRUGO, amdgpu_hwmon_get_fan1_min, NULL, 0);
3227 static SENSOR_DEVICE_ATTR(fan1_max, S_IRUGO, amdgpu_hwmon_get_fan1_max, NULL, 0);
3228 static SENSOR_DEVICE_ATTR(fan1_target, S_IRUGO | S_IWUSR, amdgpu_hwmon_get_fan1_target, amdgpu_hwmon_set_fan1_target, 0);
3229 static SENSOR_DEVICE_ATTR(fan1_enable, S_IRUGO | S_IWUSR, amdgpu_hwmon_get_fan1_enable, amdgpu_hwmon_set_fan1_enable, 0);
3230 static SENSOR_DEVICE_ATTR(in0_input, S_IRUGO, amdgpu_hwmon_show_vddgfx, NULL, 0);
3231 static SENSOR_DEVICE_ATTR(in0_label, S_IRUGO, amdgpu_hwmon_show_vddgfx_label, NULL, 0);
3232 static SENSOR_DEVICE_ATTR(in1_input, S_IRUGO, amdgpu_hwmon_show_vddnb, NULL, 0);
3233 static SENSOR_DEVICE_ATTR(in1_label, S_IRUGO, amdgpu_hwmon_show_vddnb_label, NULL, 0);
3234 static SENSOR_DEVICE_ATTR(power1_average, S_IRUGO, amdgpu_hwmon_show_power_avg, NULL, 0);
3235 static SENSOR_DEVICE_ATTR(power1_input, S_IRUGO, amdgpu_hwmon_show_power_input, NULL, 0);
3236 static SENSOR_DEVICE_ATTR(power1_cap_max, S_IRUGO, amdgpu_hwmon_show_power_cap_max, NULL, 0);
3237 static SENSOR_DEVICE_ATTR(power1_cap_min, S_IRUGO, amdgpu_hwmon_show_power_cap_min, NULL, 0);
3238 static SENSOR_DEVICE_ATTR(power1_cap, S_IRUGO | S_IWUSR, amdgpu_hwmon_show_power_cap, amdgpu_hwmon_set_power_cap, 0);
3239 static SENSOR_DEVICE_ATTR(power1_cap_default, S_IRUGO, amdgpu_hwmon_show_power_cap_default, NULL, 0);
3240 static SENSOR_DEVICE_ATTR(power1_label, S_IRUGO, amdgpu_hwmon_show_power_label, NULL, 0);
3241 static SENSOR_DEVICE_ATTR(power2_average, S_IRUGO, amdgpu_hwmon_show_power_avg, NULL, 1);
3242 static SENSOR_DEVICE_ATTR(power2_cap_max, S_IRUGO, amdgpu_hwmon_show_power_cap_max, NULL, 1);
3243 static SENSOR_DEVICE_ATTR(power2_cap_min, S_IRUGO, amdgpu_hwmon_show_power_cap_min, NULL, 1);
3244 static SENSOR_DEVICE_ATTR(power2_cap, S_IRUGO | S_IWUSR, amdgpu_hwmon_show_power_cap, amdgpu_hwmon_set_power_cap, 1);
3245 static SENSOR_DEVICE_ATTR(power2_cap_default, S_IRUGO, amdgpu_hwmon_show_power_cap_default, NULL, 1);
3246 static SENSOR_DEVICE_ATTR(power2_label, S_IRUGO, amdgpu_hwmon_show_power_label, NULL, 1);
3247 static SENSOR_DEVICE_ATTR(freq1_input, S_IRUGO, amdgpu_hwmon_show_sclk, NULL, 0);
3248 static SENSOR_DEVICE_ATTR(freq1_label, S_IRUGO, amdgpu_hwmon_show_sclk_label, NULL, 0);
3249 static SENSOR_DEVICE_ATTR(freq2_input, S_IRUGO, amdgpu_hwmon_show_mclk, NULL, 0);
3250 static SENSOR_DEVICE_ATTR(freq2_label, S_IRUGO, amdgpu_hwmon_show_mclk_label, NULL, 0);
3251
3252 static struct attribute *hwmon_attributes[] = {
3253         &sensor_dev_attr_temp1_input.dev_attr.attr,
3254         &sensor_dev_attr_temp1_crit.dev_attr.attr,
3255         &sensor_dev_attr_temp1_crit_hyst.dev_attr.attr,
3256         &sensor_dev_attr_temp2_input.dev_attr.attr,
3257         &sensor_dev_attr_temp2_crit.dev_attr.attr,
3258         &sensor_dev_attr_temp2_crit_hyst.dev_attr.attr,
3259         &sensor_dev_attr_temp3_input.dev_attr.attr,
3260         &sensor_dev_attr_temp3_crit.dev_attr.attr,
3261         &sensor_dev_attr_temp3_crit_hyst.dev_attr.attr,
3262         &sensor_dev_attr_temp1_emergency.dev_attr.attr,
3263         &sensor_dev_attr_temp2_emergency.dev_attr.attr,
3264         &sensor_dev_attr_temp3_emergency.dev_attr.attr,
3265         &sensor_dev_attr_temp1_label.dev_attr.attr,
3266         &sensor_dev_attr_temp2_label.dev_attr.attr,
3267         &sensor_dev_attr_temp3_label.dev_attr.attr,
3268         &sensor_dev_attr_pwm1.dev_attr.attr,
3269         &sensor_dev_attr_pwm1_enable.dev_attr.attr,
3270         &sensor_dev_attr_pwm1_min.dev_attr.attr,
3271         &sensor_dev_attr_pwm1_max.dev_attr.attr,
3272         &sensor_dev_attr_fan1_input.dev_attr.attr,
3273         &sensor_dev_attr_fan1_min.dev_attr.attr,
3274         &sensor_dev_attr_fan1_max.dev_attr.attr,
3275         &sensor_dev_attr_fan1_target.dev_attr.attr,
3276         &sensor_dev_attr_fan1_enable.dev_attr.attr,
3277         &sensor_dev_attr_in0_input.dev_attr.attr,
3278         &sensor_dev_attr_in0_label.dev_attr.attr,
3279         &sensor_dev_attr_in1_input.dev_attr.attr,
3280         &sensor_dev_attr_in1_label.dev_attr.attr,
3281         &sensor_dev_attr_power1_average.dev_attr.attr,
3282         &sensor_dev_attr_power1_input.dev_attr.attr,
3283         &sensor_dev_attr_power1_cap_max.dev_attr.attr,
3284         &sensor_dev_attr_power1_cap_min.dev_attr.attr,
3285         &sensor_dev_attr_power1_cap.dev_attr.attr,
3286         &sensor_dev_attr_power1_cap_default.dev_attr.attr,
3287         &sensor_dev_attr_power1_label.dev_attr.attr,
3288         &sensor_dev_attr_power2_average.dev_attr.attr,
3289         &sensor_dev_attr_power2_cap_max.dev_attr.attr,
3290         &sensor_dev_attr_power2_cap_min.dev_attr.attr,
3291         &sensor_dev_attr_power2_cap.dev_attr.attr,
3292         &sensor_dev_attr_power2_cap_default.dev_attr.attr,
3293         &sensor_dev_attr_power2_label.dev_attr.attr,
3294         &sensor_dev_attr_freq1_input.dev_attr.attr,
3295         &sensor_dev_attr_freq1_label.dev_attr.attr,
3296         &sensor_dev_attr_freq2_input.dev_attr.attr,
3297         &sensor_dev_attr_freq2_label.dev_attr.attr,
3298         NULL
3299 };
3300
3301 static umode_t hwmon_attributes_visible(struct kobject *kobj,
3302                                         struct attribute *attr, int index)
3303 {
3304         struct device *dev = kobj_to_dev(kobj);
3305         struct amdgpu_device *adev = dev_get_drvdata(dev);
3306         umode_t effective_mode = attr->mode;
3307         uint32_t gc_ver = amdgpu_ip_version(adev, GC_HWIP, 0);
3308         uint32_t tmp;
3309
3310         /* under pp one vf mode manage of hwmon attributes is not supported */
3311         if (amdgpu_sriov_is_pp_one_vf(adev))
3312                 effective_mode &= ~S_IWUSR;
3313
3314         /* Skip fan attributes if fan is not present */
3315         if (adev->pm.no_fan && (attr == &sensor_dev_attr_pwm1.dev_attr.attr ||
3316             attr == &sensor_dev_attr_pwm1_enable.dev_attr.attr ||
3317             attr == &sensor_dev_attr_pwm1_max.dev_attr.attr ||
3318             attr == &sensor_dev_attr_pwm1_min.dev_attr.attr ||
3319             attr == &sensor_dev_attr_fan1_input.dev_attr.attr ||
3320             attr == &sensor_dev_attr_fan1_min.dev_attr.attr ||
3321             attr == &sensor_dev_attr_fan1_max.dev_attr.attr ||
3322             attr == &sensor_dev_attr_fan1_target.dev_attr.attr ||
3323             attr == &sensor_dev_attr_fan1_enable.dev_attr.attr))
3324                 return 0;
3325
3326         /* Skip fan attributes on APU */
3327         if ((adev->flags & AMD_IS_APU) &&
3328             (attr == &sensor_dev_attr_pwm1.dev_attr.attr ||
3329              attr == &sensor_dev_attr_pwm1_enable.dev_attr.attr ||
3330              attr == &sensor_dev_attr_pwm1_max.dev_attr.attr ||
3331              attr == &sensor_dev_attr_pwm1_min.dev_attr.attr ||
3332              attr == &sensor_dev_attr_fan1_input.dev_attr.attr ||
3333              attr == &sensor_dev_attr_fan1_min.dev_attr.attr ||
3334              attr == &sensor_dev_attr_fan1_max.dev_attr.attr ||
3335              attr == &sensor_dev_attr_fan1_target.dev_attr.attr ||
3336              attr == &sensor_dev_attr_fan1_enable.dev_attr.attr))
3337                 return 0;
3338
3339         /* Skip crit temp on APU */
3340         if ((((adev->flags & AMD_IS_APU) && (adev->family >= AMDGPU_FAMILY_CZ)) ||
3341             (gc_ver == IP_VERSION(9, 4, 3))) &&
3342             (attr == &sensor_dev_attr_temp1_crit.dev_attr.attr ||
3343              attr == &sensor_dev_attr_temp1_crit_hyst.dev_attr.attr))
3344                 return 0;
3345
3346         /* Skip limit attributes if DPM is not enabled */
3347         if (!adev->pm.dpm_enabled &&
3348             (attr == &sensor_dev_attr_temp1_crit.dev_attr.attr ||
3349              attr == &sensor_dev_attr_temp1_crit_hyst.dev_attr.attr ||
3350              attr == &sensor_dev_attr_pwm1.dev_attr.attr ||
3351              attr == &sensor_dev_attr_pwm1_enable.dev_attr.attr ||
3352              attr == &sensor_dev_attr_pwm1_max.dev_attr.attr ||
3353              attr == &sensor_dev_attr_pwm1_min.dev_attr.attr ||
3354              attr == &sensor_dev_attr_fan1_input.dev_attr.attr ||
3355              attr == &sensor_dev_attr_fan1_min.dev_attr.attr ||
3356              attr == &sensor_dev_attr_fan1_max.dev_attr.attr ||
3357              attr == &sensor_dev_attr_fan1_target.dev_attr.attr ||
3358              attr == &sensor_dev_attr_fan1_enable.dev_attr.attr))
3359                 return 0;
3360
3361         /* mask fan attributes if we have no bindings for this asic to expose */
3362         if (((amdgpu_dpm_get_fan_speed_pwm(adev, NULL) == -EOPNOTSUPP) &&
3363               attr == &sensor_dev_attr_pwm1.dev_attr.attr) || /* can't query fan */
3364             ((amdgpu_dpm_get_fan_control_mode(adev, NULL) == -EOPNOTSUPP) &&
3365              attr == &sensor_dev_attr_pwm1_enable.dev_attr.attr)) /* can't query state */
3366                 effective_mode &= ~S_IRUGO;
3367
3368         if (((amdgpu_dpm_set_fan_speed_pwm(adev, U32_MAX) == -EOPNOTSUPP) &&
3369               attr == &sensor_dev_attr_pwm1.dev_attr.attr) || /* can't manage fan */
3370               ((amdgpu_dpm_set_fan_control_mode(adev, U32_MAX) == -EOPNOTSUPP) &&
3371               attr == &sensor_dev_attr_pwm1_enable.dev_attr.attr)) /* can't manage state */
3372                 effective_mode &= ~S_IWUSR;
3373
3374         /* not implemented yet for APUs other than GC 10.3.1 (vangogh) and 9.4.3 */
3375         if (((adev->family == AMDGPU_FAMILY_SI) ||
3376              ((adev->flags & AMD_IS_APU) && (gc_ver != IP_VERSION(10, 3, 1)) &&
3377               (gc_ver != IP_VERSION(9, 4, 3)))) &&
3378             (attr == &sensor_dev_attr_power1_cap_max.dev_attr.attr ||
3379              attr == &sensor_dev_attr_power1_cap_min.dev_attr.attr ||
3380              attr == &sensor_dev_attr_power1_cap.dev_attr.attr ||
3381              attr == &sensor_dev_attr_power1_cap_default.dev_attr.attr))
3382                 return 0;
3383
3384         /* not implemented yet for APUs having < GC 9.3.0 (Renoir) */
3385         if (((adev->family == AMDGPU_FAMILY_SI) ||
3386              ((adev->flags & AMD_IS_APU) && (gc_ver < IP_VERSION(9, 3, 0)))) &&
3387             (attr == &sensor_dev_attr_power1_average.dev_attr.attr))
3388                 return 0;
3389
3390         /* not all products support both average and instantaneous */
3391         if (attr == &sensor_dev_attr_power1_average.dev_attr.attr &&
3392             amdgpu_hwmon_get_sensor_generic(adev, AMDGPU_PP_SENSOR_GPU_AVG_POWER, (void *)&tmp) == -EOPNOTSUPP)
3393                 return 0;
3394         if (attr == &sensor_dev_attr_power1_input.dev_attr.attr &&
3395             amdgpu_hwmon_get_sensor_generic(adev, AMDGPU_PP_SENSOR_GPU_INPUT_POWER, (void *)&tmp) == -EOPNOTSUPP)
3396                 return 0;
3397
3398         /* hide max/min values if we can't both query and manage the fan */
3399         if (((amdgpu_dpm_set_fan_speed_pwm(adev, U32_MAX) == -EOPNOTSUPP) &&
3400               (amdgpu_dpm_get_fan_speed_pwm(adev, NULL) == -EOPNOTSUPP) &&
3401               (amdgpu_dpm_set_fan_speed_rpm(adev, U32_MAX) == -EOPNOTSUPP) &&
3402               (amdgpu_dpm_get_fan_speed_rpm(adev, NULL) == -EOPNOTSUPP)) &&
3403             (attr == &sensor_dev_attr_pwm1_max.dev_attr.attr ||
3404              attr == &sensor_dev_attr_pwm1_min.dev_attr.attr))
3405                 return 0;
3406
3407         if ((amdgpu_dpm_set_fan_speed_rpm(adev, U32_MAX) == -EOPNOTSUPP) &&
3408              (amdgpu_dpm_get_fan_speed_rpm(adev, NULL) == -EOPNOTSUPP) &&
3409              (attr == &sensor_dev_attr_fan1_max.dev_attr.attr ||
3410              attr == &sensor_dev_attr_fan1_min.dev_attr.attr))
3411                 return 0;
3412
3413         if ((adev->family == AMDGPU_FAMILY_SI ||        /* not implemented yet */
3414              adev->family == AMDGPU_FAMILY_KV ||        /* not implemented yet */
3415              (gc_ver == IP_VERSION(9, 4, 3))) &&
3416             (attr == &sensor_dev_attr_in0_input.dev_attr.attr ||
3417              attr == &sensor_dev_attr_in0_label.dev_attr.attr))
3418                 return 0;
3419
3420         /* only APUs other than gc 9,4,3 have vddnb */
3421         if ((!(adev->flags & AMD_IS_APU) || (gc_ver == IP_VERSION(9, 4, 3))) &&
3422             (attr == &sensor_dev_attr_in1_input.dev_attr.attr ||
3423              attr == &sensor_dev_attr_in1_label.dev_attr.attr))
3424                 return 0;
3425
3426         /* no mclk on APUs other than gc 9,4,3*/
3427         if (((adev->flags & AMD_IS_APU) && (gc_ver != IP_VERSION(9, 4, 3))) &&
3428             (attr == &sensor_dev_attr_freq2_input.dev_attr.attr ||
3429              attr == &sensor_dev_attr_freq2_label.dev_attr.attr))
3430                 return 0;
3431
3432         if (((adev->flags & AMD_IS_APU) || gc_ver < IP_VERSION(9, 0, 0)) &&
3433             (gc_ver != IP_VERSION(9, 4, 3)) &&
3434             (attr == &sensor_dev_attr_temp2_input.dev_attr.attr ||
3435              attr == &sensor_dev_attr_temp2_label.dev_attr.attr ||
3436              attr == &sensor_dev_attr_temp2_crit.dev_attr.attr ||
3437              attr == &sensor_dev_attr_temp3_input.dev_attr.attr ||
3438              attr == &sensor_dev_attr_temp3_label.dev_attr.attr ||
3439              attr == &sensor_dev_attr_temp3_crit.dev_attr.attr))
3440                 return 0;
3441
3442         /* hotspot temperature for gc 9,4,3*/
3443         if (gc_ver == IP_VERSION(9, 4, 3)) {
3444                 if (attr == &sensor_dev_attr_temp1_input.dev_attr.attr ||
3445                     attr == &sensor_dev_attr_temp1_emergency.dev_attr.attr ||
3446                     attr == &sensor_dev_attr_temp1_label.dev_attr.attr)
3447                         return 0;
3448
3449                 if (attr == &sensor_dev_attr_temp2_emergency.dev_attr.attr ||
3450                     attr == &sensor_dev_attr_temp3_emergency.dev_attr.attr)
3451                         return attr->mode;
3452         }
3453
3454         /* only SOC15 dGPUs support hotspot and mem temperatures */
3455         if (((adev->flags & AMD_IS_APU) || gc_ver < IP_VERSION(9, 0, 0)) &&
3456             (attr == &sensor_dev_attr_temp2_crit_hyst.dev_attr.attr ||
3457              attr == &sensor_dev_attr_temp3_crit_hyst.dev_attr.attr ||
3458              attr == &sensor_dev_attr_temp1_emergency.dev_attr.attr ||
3459              attr == &sensor_dev_attr_temp2_emergency.dev_attr.attr ||
3460              attr == &sensor_dev_attr_temp3_emergency.dev_attr.attr))
3461                 return 0;
3462
3463         /* only Vangogh has fast PPT limit and power labels */
3464         if (!(gc_ver == IP_VERSION(10, 3, 1)) &&
3465             (attr == &sensor_dev_attr_power2_average.dev_attr.attr ||
3466              attr == &sensor_dev_attr_power2_cap_max.dev_attr.attr ||
3467              attr == &sensor_dev_attr_power2_cap_min.dev_attr.attr ||
3468              attr == &sensor_dev_attr_power2_cap.dev_attr.attr ||
3469              attr == &sensor_dev_attr_power2_cap_default.dev_attr.attr ||
3470              attr == &sensor_dev_attr_power2_label.dev_attr.attr))
3471                 return 0;
3472
3473         return effective_mode;
3474 }
3475
3476 static const struct attribute_group hwmon_attrgroup = {
3477         .attrs = hwmon_attributes,
3478         .is_visible = hwmon_attributes_visible,
3479 };
3480
3481 static const struct attribute_group *hwmon_groups[] = {
3482         &hwmon_attrgroup,
3483         NULL
3484 };
3485
3486 static int amdgpu_retrieve_od_settings(struct amdgpu_device *adev,
3487                                        enum pp_clock_type od_type,
3488                                        char *buf)
3489 {
3490         int size = 0;
3491         int ret;
3492
3493         if (amdgpu_in_reset(adev))
3494                 return -EPERM;
3495         if (adev->in_suspend && !adev->in_runpm)
3496                 return -EPERM;
3497
3498         ret = pm_runtime_get_sync(adev->dev);
3499         if (ret < 0) {
3500                 pm_runtime_put_autosuspend(adev->dev);
3501                 return ret;
3502         }
3503
3504         size = amdgpu_dpm_print_clock_levels(adev, od_type, buf);
3505         if (size == 0)
3506                 size = sysfs_emit(buf, "\n");
3507
3508         pm_runtime_mark_last_busy(adev->dev);
3509         pm_runtime_put_autosuspend(adev->dev);
3510
3511         return size;
3512 }
3513
3514 static int parse_input_od_command_lines(const char *buf,
3515                                         size_t count,
3516                                         u32 *type,
3517                                         long *params,
3518                                         uint32_t *num_of_params)
3519 {
3520         const char delimiter[3] = {' ', '\n', '\0'};
3521         uint32_t parameter_size = 0;
3522         char buf_cpy[128] = {0};
3523         char *tmp_str, *sub_str;
3524         int ret;
3525
3526         if (count > sizeof(buf_cpy) - 1)
3527                 return -EINVAL;
3528
3529         memcpy(buf_cpy, buf, count);
3530         tmp_str = buf_cpy;
3531
3532         /* skip heading spaces */
3533         while (isspace(*tmp_str))
3534                 tmp_str++;
3535
3536         switch (*tmp_str) {
3537         case 'c':
3538                 *type = PP_OD_COMMIT_DPM_TABLE;
3539                 return 0;
3540         case 'r':
3541                 params[parameter_size] = *type;
3542                 *num_of_params = 1;
3543                 *type = PP_OD_RESTORE_DEFAULT_TABLE;
3544                 return 0;
3545         default:
3546                 break;
3547         }
3548
3549         while ((sub_str = strsep(&tmp_str, delimiter)) != NULL) {
3550                 if (strlen(sub_str) == 0)
3551                         continue;
3552
3553                 ret = kstrtol(sub_str, 0, &params[parameter_size]);
3554                 if (ret)
3555                         return -EINVAL;
3556                 parameter_size++;
3557
3558                 while (isspace(*tmp_str))
3559                         tmp_str++;
3560         }
3561
3562         *num_of_params = parameter_size;
3563
3564         return 0;
3565 }
3566
3567 static int
3568 amdgpu_distribute_custom_od_settings(struct amdgpu_device *adev,
3569                                      enum PP_OD_DPM_TABLE_COMMAND cmd_type,
3570                                      const char *in_buf,
3571                                      size_t count)
3572 {
3573         uint32_t parameter_size = 0;
3574         long parameter[64];
3575         int ret;
3576
3577         if (amdgpu_in_reset(adev))
3578                 return -EPERM;
3579         if (adev->in_suspend && !adev->in_runpm)
3580                 return -EPERM;
3581
3582         ret = parse_input_od_command_lines(in_buf,
3583                                            count,
3584                                            &cmd_type,
3585                                            parameter,
3586                                            &parameter_size);
3587         if (ret)
3588                 return ret;
3589
3590         ret = pm_runtime_get_sync(adev->dev);
3591         if (ret < 0)
3592                 goto err_out0;
3593
3594         ret = amdgpu_dpm_odn_edit_dpm_table(adev,
3595                                             cmd_type,
3596                                             parameter,
3597                                             parameter_size);
3598         if (ret)
3599                 goto err_out1;
3600
3601         if (cmd_type == PP_OD_COMMIT_DPM_TABLE) {
3602                 ret = amdgpu_dpm_dispatch_task(adev,
3603                                                AMD_PP_TASK_READJUST_POWER_STATE,
3604                                                NULL);
3605                 if (ret)
3606                         goto err_out1;
3607         }
3608
3609         pm_runtime_mark_last_busy(adev->dev);
3610         pm_runtime_put_autosuspend(adev->dev);
3611
3612         return count;
3613
3614 err_out1:
3615         pm_runtime_mark_last_busy(adev->dev);
3616 err_out0:
3617         pm_runtime_put_autosuspend(adev->dev);
3618
3619         return ret;
3620 }
3621
3622 /**
3623  * DOC: fan_curve
3624  *
3625  * The amdgpu driver provides a sysfs API for checking and adjusting the fan
3626  * control curve line.
3627  *
3628  * Reading back the file shows you the current settings(temperature in Celsius
3629  * degree and fan speed in pwm) applied to every anchor point of the curve line
3630  * and their permitted ranges if changable.
3631  *
3632  * Writing a desired string(with the format like "anchor_point_index temperature
3633  * fan_speed_in_pwm") to the file, change the settings for the specific anchor
3634  * point accordingly.
3635  *
3636  * When you have finished the editing, write "c" (commit) to the file to commit
3637  * your changes.
3638  *
3639  * If you want to reset to the default value, write "r" (reset) to the file to
3640  * reset them
3641  *
3642  * There are two fan control modes supported: auto and manual. With auto mode,
3643  * PMFW handles the fan speed control(how fan speed reacts to ASIC temperature).
3644  * While with manual mode, users can set their own fan curve line as what
3645  * described here. Normally the ASIC is booted up with auto mode. Any
3646  * settings via this interface will switch the fan control to manual mode
3647  * implicitly.
3648  */
3649 static ssize_t fan_curve_show(struct kobject *kobj,
3650                               struct kobj_attribute *attr,
3651                               char *buf)
3652 {
3653         struct od_kobj *container = container_of(kobj, struct od_kobj, kobj);
3654         struct amdgpu_device *adev = (struct amdgpu_device *)container->priv;
3655
3656         return (ssize_t)amdgpu_retrieve_od_settings(adev, OD_FAN_CURVE, buf);
3657 }
3658
3659 static ssize_t fan_curve_store(struct kobject *kobj,
3660                                struct kobj_attribute *attr,
3661                                const char *buf,
3662                                size_t count)
3663 {
3664         struct od_kobj *container = container_of(kobj, struct od_kobj, kobj);
3665         struct amdgpu_device *adev = (struct amdgpu_device *)container->priv;
3666
3667         return (ssize_t)amdgpu_distribute_custom_od_settings(adev,
3668                                                              PP_OD_EDIT_FAN_CURVE,
3669                                                              buf,
3670                                                              count);
3671 }
3672
3673 static umode_t fan_curve_visible(struct amdgpu_device *adev)
3674 {
3675         umode_t umode = 0000;
3676
3677         if (adev->pm.od_feature_mask & OD_OPS_SUPPORT_FAN_CURVE_RETRIEVE)
3678                 umode |= S_IRUSR | S_IRGRP | S_IROTH;
3679
3680         if (adev->pm.od_feature_mask & OD_OPS_SUPPORT_FAN_CURVE_SET)
3681                 umode |= S_IWUSR;
3682
3683         return umode;
3684 }
3685
3686 /**
3687  * DOC: acoustic_limit_rpm_threshold
3688  *
3689  * The amdgpu driver provides a sysfs API for checking and adjusting the
3690  * acoustic limit in RPM for fan control.
3691  *
3692  * Reading back the file shows you the current setting and the permitted
3693  * ranges if changable.
3694  *
3695  * Writing an integer to the file, change the setting accordingly.
3696  *
3697  * When you have finished the editing, write "c" (commit) to the file to commit
3698  * your changes.
3699  *
3700  * If you want to reset to the default value, write "r" (reset) to the file to
3701  * reset them
3702  *
3703  * This setting works under auto fan control mode only. It adjusts the PMFW's
3704  * behavior about the maximum speed in RPM the fan can spin. Setting via this
3705  * interface will switch the fan control to auto mode implicitly.
3706  */
3707 static ssize_t acoustic_limit_threshold_show(struct kobject *kobj,
3708                                              struct kobj_attribute *attr,
3709                                              char *buf)
3710 {
3711         struct od_kobj *container = container_of(kobj, struct od_kobj, kobj);
3712         struct amdgpu_device *adev = (struct amdgpu_device *)container->priv;
3713
3714         return (ssize_t)amdgpu_retrieve_od_settings(adev, OD_ACOUSTIC_LIMIT, buf);
3715 }
3716
3717 static ssize_t acoustic_limit_threshold_store(struct kobject *kobj,
3718                                               struct kobj_attribute *attr,
3719                                               const char *buf,
3720                                               size_t count)
3721 {
3722         struct od_kobj *container = container_of(kobj, struct od_kobj, kobj);
3723         struct amdgpu_device *adev = (struct amdgpu_device *)container->priv;
3724
3725         return (ssize_t)amdgpu_distribute_custom_od_settings(adev,
3726                                                              PP_OD_EDIT_ACOUSTIC_LIMIT,
3727                                                              buf,
3728                                                              count);
3729 }
3730
3731 static umode_t acoustic_limit_threshold_visible(struct amdgpu_device *adev)
3732 {
3733         umode_t umode = 0000;
3734
3735         if (adev->pm.od_feature_mask & OD_OPS_SUPPORT_ACOUSTIC_LIMIT_THRESHOLD_RETRIEVE)
3736                 umode |= S_IRUSR | S_IRGRP | S_IROTH;
3737
3738         if (adev->pm.od_feature_mask & OD_OPS_SUPPORT_ACOUSTIC_LIMIT_THRESHOLD_SET)
3739                 umode |= S_IWUSR;
3740
3741         return umode;
3742 }
3743
3744 /**
3745  * DOC: acoustic_target_rpm_threshold
3746  *
3747  * The amdgpu driver provides a sysfs API for checking and adjusting the
3748  * acoustic target in RPM for fan control.
3749  *
3750  * Reading back the file shows you the current setting and the permitted
3751  * ranges if changable.
3752  *
3753  * Writing an integer to the file, change the setting accordingly.
3754  *
3755  * When you have finished the editing, write "c" (commit) to the file to commit
3756  * your changes.
3757  *
3758  * If you want to reset to the default value, write "r" (reset) to the file to
3759  * reset them
3760  *
3761  * This setting works under auto fan control mode only. It can co-exist with
3762  * other settings which can work also under auto mode. It adjusts the PMFW's
3763  * behavior about the maximum speed in RPM the fan can spin when ASIC
3764  * temperature is not greater than target temperature. Setting via this
3765  * interface will switch the fan control to auto mode implicitly.
3766  */
3767 static ssize_t acoustic_target_threshold_show(struct kobject *kobj,
3768                                               struct kobj_attribute *attr,
3769                                               char *buf)
3770 {
3771         struct od_kobj *container = container_of(kobj, struct od_kobj, kobj);
3772         struct amdgpu_device *adev = (struct amdgpu_device *)container->priv;
3773
3774         return (ssize_t)amdgpu_retrieve_od_settings(adev, OD_ACOUSTIC_TARGET, buf);
3775 }
3776
3777 static ssize_t acoustic_target_threshold_store(struct kobject *kobj,
3778                                                struct kobj_attribute *attr,
3779                                                const char *buf,
3780                                                size_t count)
3781 {
3782         struct od_kobj *container = container_of(kobj, struct od_kobj, kobj);
3783         struct amdgpu_device *adev = (struct amdgpu_device *)container->priv;
3784
3785         return (ssize_t)amdgpu_distribute_custom_od_settings(adev,
3786                                                              PP_OD_EDIT_ACOUSTIC_TARGET,
3787                                                              buf,
3788                                                              count);
3789 }
3790
3791 static umode_t acoustic_target_threshold_visible(struct amdgpu_device *adev)
3792 {
3793         umode_t umode = 0000;
3794
3795         if (adev->pm.od_feature_mask & OD_OPS_SUPPORT_ACOUSTIC_TARGET_THRESHOLD_RETRIEVE)
3796                 umode |= S_IRUSR | S_IRGRP | S_IROTH;
3797
3798         if (adev->pm.od_feature_mask & OD_OPS_SUPPORT_ACOUSTIC_TARGET_THRESHOLD_SET)
3799                 umode |= S_IWUSR;
3800
3801         return umode;
3802 }
3803
3804 /**
3805  * DOC: fan_target_temperature
3806  *
3807  * The amdgpu driver provides a sysfs API for checking and adjusting the
3808  * target tempeature in Celsius degree for fan control.
3809  *
3810  * Reading back the file shows you the current setting and the permitted
3811  * ranges if changable.
3812  *
3813  * Writing an integer to the file, change the setting accordingly.
3814  *
3815  * When you have finished the editing, write "c" (commit) to the file to commit
3816  * your changes.
3817  *
3818  * If you want to reset to the default value, write "r" (reset) to the file to
3819  * reset them
3820  *
3821  * This setting works under auto fan control mode only. It can co-exist with
3822  * other settings which can work also under auto mode. Paring with the
3823  * acoustic_target_rpm_threshold setting, they define the maximum speed in
3824  * RPM the fan can spin when ASIC temperature is not greater than target
3825  * temperature. Setting via this interface will switch the fan control to
3826  * auto mode implicitly.
3827  */
3828 static ssize_t fan_target_temperature_show(struct kobject *kobj,
3829                                            struct kobj_attribute *attr,
3830                                            char *buf)
3831 {
3832         struct od_kobj *container = container_of(kobj, struct od_kobj, kobj);
3833         struct amdgpu_device *adev = (struct amdgpu_device *)container->priv;
3834
3835         return (ssize_t)amdgpu_retrieve_od_settings(adev, OD_FAN_TARGET_TEMPERATURE, buf);
3836 }
3837
3838 static ssize_t fan_target_temperature_store(struct kobject *kobj,
3839                                             struct kobj_attribute *attr,
3840                                             const char *buf,
3841                                             size_t count)
3842 {
3843         struct od_kobj *container = container_of(kobj, struct od_kobj, kobj);
3844         struct amdgpu_device *adev = (struct amdgpu_device *)container->priv;
3845
3846         return (ssize_t)amdgpu_distribute_custom_od_settings(adev,
3847                                                              PP_OD_EDIT_FAN_TARGET_TEMPERATURE,
3848                                                              buf,
3849                                                              count);
3850 }
3851
3852 static umode_t fan_target_temperature_visible(struct amdgpu_device *adev)
3853 {
3854         umode_t umode = 0000;
3855
3856         if (adev->pm.od_feature_mask & OD_OPS_SUPPORT_FAN_TARGET_TEMPERATURE_RETRIEVE)
3857                 umode |= S_IRUSR | S_IRGRP | S_IROTH;
3858
3859         if (adev->pm.od_feature_mask & OD_OPS_SUPPORT_FAN_TARGET_TEMPERATURE_SET)
3860                 umode |= S_IWUSR;
3861
3862         return umode;
3863 }
3864
3865 /**
3866  * DOC: fan_minimum_pwm
3867  *
3868  * The amdgpu driver provides a sysfs API for checking and adjusting the
3869  * minimum fan speed in PWM.
3870  *
3871  * Reading back the file shows you the current setting and the permitted
3872  * ranges if changable.
3873  *
3874  * Writing an integer to the file, change the setting accordingly.
3875  *
3876  * When you have finished the editing, write "c" (commit) to the file to commit
3877  * your changes.
3878  *
3879  * If you want to reset to the default value, write "r" (reset) to the file to
3880  * reset them
3881  *
3882  * This setting works under auto fan control mode only. It can co-exist with
3883  * other settings which can work also under auto mode. It adjusts the PMFW's
3884  * behavior about the minimum fan speed in PWM the fan should spin. Setting
3885  * via this interface will switch the fan control to auto mode implicitly.
3886  */
3887 static ssize_t fan_minimum_pwm_show(struct kobject *kobj,
3888                                     struct kobj_attribute *attr,
3889                                     char *buf)
3890 {
3891         struct od_kobj *container = container_of(kobj, struct od_kobj, kobj);
3892         struct amdgpu_device *adev = (struct amdgpu_device *)container->priv;
3893
3894         return (ssize_t)amdgpu_retrieve_od_settings(adev, OD_FAN_MINIMUM_PWM, buf);
3895 }
3896
3897 static ssize_t fan_minimum_pwm_store(struct kobject *kobj,
3898                                      struct kobj_attribute *attr,
3899                                      const char *buf,
3900                                      size_t count)
3901 {
3902         struct od_kobj *container = container_of(kobj, struct od_kobj, kobj);
3903         struct amdgpu_device *adev = (struct amdgpu_device *)container->priv;
3904
3905         return (ssize_t)amdgpu_distribute_custom_od_settings(adev,
3906                                                              PP_OD_EDIT_FAN_MINIMUM_PWM,
3907                                                              buf,
3908                                                              count);
3909 }
3910
3911 static umode_t fan_minimum_pwm_visible(struct amdgpu_device *adev)
3912 {
3913         umode_t umode = 0000;
3914
3915         if (adev->pm.od_feature_mask & OD_OPS_SUPPORT_FAN_MINIMUM_PWM_RETRIEVE)
3916                 umode |= S_IRUSR | S_IRGRP | S_IROTH;
3917
3918         if (adev->pm.od_feature_mask & OD_OPS_SUPPORT_FAN_MINIMUM_PWM_SET)
3919                 umode |= S_IWUSR;
3920
3921         return umode;
3922 }
3923
3924 static struct od_feature_set amdgpu_od_set = {
3925         .containers = {
3926                 [0] = {
3927                         .name = "fan_ctrl",
3928                         .sub_feature = {
3929                                 [0] = {
3930                                         .name = "fan_curve",
3931                                         .ops = {
3932                                                 .is_visible = fan_curve_visible,
3933                                                 .show = fan_curve_show,
3934                                                 .store = fan_curve_store,
3935                                         },
3936                                 },
3937                                 [1] = {
3938                                         .name = "acoustic_limit_rpm_threshold",
3939                                         .ops = {
3940                                                 .is_visible = acoustic_limit_threshold_visible,
3941                                                 .show = acoustic_limit_threshold_show,
3942                                                 .store = acoustic_limit_threshold_store,
3943                                         },
3944                                 },
3945                                 [2] = {
3946                                         .name = "acoustic_target_rpm_threshold",
3947                                         .ops = {
3948                                                 .is_visible = acoustic_target_threshold_visible,
3949                                                 .show = acoustic_target_threshold_show,
3950                                                 .store = acoustic_target_threshold_store,
3951                                         },
3952                                 },
3953                                 [3] = {
3954                                         .name = "fan_target_temperature",
3955                                         .ops = {
3956                                                 .is_visible = fan_target_temperature_visible,
3957                                                 .show = fan_target_temperature_show,
3958                                                 .store = fan_target_temperature_store,
3959                                         },
3960                                 },
3961                                 [4] = {
3962                                         .name = "fan_minimum_pwm",
3963                                         .ops = {
3964                                                 .is_visible = fan_minimum_pwm_visible,
3965                                                 .show = fan_minimum_pwm_show,
3966                                                 .store = fan_minimum_pwm_store,
3967                                         },
3968                                 },
3969                         },
3970                 },
3971         },
3972 };
3973
3974 static void od_kobj_release(struct kobject *kobj)
3975 {
3976         struct od_kobj *od_kobj = container_of(kobj, struct od_kobj, kobj);
3977
3978         kfree(od_kobj);
3979 }
3980
3981 static const struct kobj_type od_ktype = {
3982         .release        = od_kobj_release,
3983         .sysfs_ops      = &kobj_sysfs_ops,
3984 };
3985
3986 static void amdgpu_od_set_fini(struct amdgpu_device *adev)
3987 {
3988         struct od_kobj *container, *container_next;
3989         struct od_attribute *attribute, *attribute_next;
3990
3991         if (list_empty(&adev->pm.od_kobj_list))
3992                 return;
3993
3994         list_for_each_entry_safe(container, container_next,
3995                                  &adev->pm.od_kobj_list, entry) {
3996                 list_del(&container->entry);
3997
3998                 list_for_each_entry_safe(attribute, attribute_next,
3999                                          &container->attribute, entry) {
4000                         list_del(&attribute->entry);
4001                         sysfs_remove_file(&container->kobj,
4002                                           &attribute->attribute.attr);
4003                         kfree(attribute);
4004                 }
4005
4006                 kobject_put(&container->kobj);
4007         }
4008 }
4009
4010 static bool amdgpu_is_od_feature_supported(struct amdgpu_device *adev,
4011                                            struct od_feature_ops *feature_ops)
4012 {
4013         umode_t mode;
4014
4015         if (!feature_ops->is_visible)
4016                 return false;
4017
4018         /*
4019          * If the feature has no user read and write mode set,
4020          * we can assume the feature is actually not supported.(?)
4021          * And the revelant sysfs interface should not be exposed.
4022          */
4023         mode = feature_ops->is_visible(adev);
4024         if (mode & (S_IRUSR | S_IWUSR))
4025                 return true;
4026
4027         return false;
4028 }
4029
4030 static bool amdgpu_od_is_self_contained(struct amdgpu_device *adev,
4031                                         struct od_feature_container *container)
4032 {
4033         int i;
4034
4035         /*
4036          * If there is no valid entry within the container, the container
4037          * is recognized as a self contained container. And the valid entry
4038          * here means it has a valid naming and it is visible/supported by
4039          * the ASIC.
4040          */
4041         for (i = 0; i < ARRAY_SIZE(container->sub_feature); i++) {
4042                 if (container->sub_feature[i].name &&
4043                     amdgpu_is_od_feature_supported(adev,
4044                         &container->sub_feature[i].ops))
4045                         return false;
4046         }
4047
4048         return true;
4049 }
4050
4051 static int amdgpu_od_set_init(struct amdgpu_device *adev)
4052 {
4053         struct od_kobj *top_set, *sub_set;
4054         struct od_attribute *attribute;
4055         struct od_feature_container *container;
4056         struct od_feature_item *feature;
4057         int i, j;
4058         int ret;
4059
4060         /* Setup the top `gpu_od` directory which holds all other OD interfaces */
4061         top_set = kzalloc(sizeof(*top_set), GFP_KERNEL);
4062         if (!top_set)
4063                 return -ENOMEM;
4064         list_add(&top_set->entry, &adev->pm.od_kobj_list);
4065
4066         ret = kobject_init_and_add(&top_set->kobj,
4067                                    &od_ktype,
4068                                    &adev->dev->kobj,
4069                                    "%s",
4070                                    "gpu_od");
4071         if (ret)
4072                 goto err_out;
4073         INIT_LIST_HEAD(&top_set->attribute);
4074         top_set->priv = adev;
4075
4076         for (i = 0; i < ARRAY_SIZE(amdgpu_od_set.containers); i++) {
4077                 container = &amdgpu_od_set.containers[i];
4078
4079                 if (!container->name)
4080                         continue;
4081
4082                 /*
4083                  * If there is valid entries within the container, the container
4084                  * will be presented as a sub directory and all its holding entries
4085                  * will be presented as plain files under it.
4086                  * While if there is no valid entry within the container, the container
4087                  * itself will be presented as a plain file under top `gpu_od` directory.
4088                  */
4089                 if (amdgpu_od_is_self_contained(adev, container)) {
4090                         if (!amdgpu_is_od_feature_supported(adev,
4091                              &container->ops))
4092                                 continue;
4093
4094                         /*
4095                          * The container is presented as a plain file under top `gpu_od`
4096                          * directory.
4097                          */
4098                         attribute = kzalloc(sizeof(*attribute), GFP_KERNEL);
4099                         if (!attribute) {
4100                                 ret = -ENOMEM;
4101                                 goto err_out;
4102                         }
4103                         list_add(&attribute->entry, &top_set->attribute);
4104
4105                         attribute->attribute.attr.mode =
4106                                         container->ops.is_visible(adev);
4107                         attribute->attribute.attr.name = container->name;
4108                         attribute->attribute.show =
4109                                         container->ops.show;
4110                         attribute->attribute.store =
4111                                         container->ops.store;
4112                         ret = sysfs_create_file(&top_set->kobj,
4113                                                 &attribute->attribute.attr);
4114                         if (ret)
4115                                 goto err_out;
4116                 } else {
4117                         /* The container is presented as a sub directory. */
4118                         sub_set = kzalloc(sizeof(*sub_set), GFP_KERNEL);
4119                         if (!sub_set) {
4120                                 ret = -ENOMEM;
4121                                 goto err_out;
4122                         }
4123                         list_add(&sub_set->entry, &adev->pm.od_kobj_list);
4124
4125                         ret = kobject_init_and_add(&sub_set->kobj,
4126                                                    &od_ktype,
4127                                                    &top_set->kobj,
4128                                                    "%s",
4129                                                    container->name);
4130                         if (ret)
4131                                 goto err_out;
4132                         INIT_LIST_HEAD(&sub_set->attribute);
4133                         sub_set->priv = adev;
4134
4135                         for (j = 0; j < ARRAY_SIZE(container->sub_feature); j++) {
4136                                 feature = &container->sub_feature[j];
4137                                 if (!feature->name)
4138                                         continue;
4139
4140                                 if (!amdgpu_is_od_feature_supported(adev,
4141                                      &feature->ops))
4142                                         continue;
4143
4144                                 /*
4145                                  * With the container presented as a sub directory, the entry within
4146                                  * it is presented as a plain file under the sub directory.
4147                                  */
4148                                 attribute = kzalloc(sizeof(*attribute), GFP_KERNEL);
4149                                 if (!attribute) {
4150                                         ret = -ENOMEM;
4151                                         goto err_out;
4152                                 }
4153                                 list_add(&attribute->entry, &sub_set->attribute);
4154
4155                                 attribute->attribute.attr.mode =
4156                                                 feature->ops.is_visible(adev);
4157                                 attribute->attribute.attr.name = feature->name;
4158                                 attribute->attribute.show =
4159                                                 feature->ops.show;
4160                                 attribute->attribute.store =
4161                                                 feature->ops.store;
4162                                 ret = sysfs_create_file(&sub_set->kobj,
4163                                                         &attribute->attribute.attr);
4164                                 if (ret)
4165                                         goto err_out;
4166                         }
4167                 }
4168         }
4169
4170         return 0;
4171
4172 err_out:
4173         amdgpu_od_set_fini(adev);
4174
4175         return ret;
4176 }
4177
4178 int amdgpu_pm_sysfs_init(struct amdgpu_device *adev)
4179 {
4180         enum amdgpu_sriov_vf_mode mode;
4181         uint32_t mask = 0;
4182         int ret;
4183
4184         if (adev->pm.sysfs_initialized)
4185                 return 0;
4186
4187         INIT_LIST_HEAD(&adev->pm.pm_attr_list);
4188
4189         if (adev->pm.dpm_enabled == 0)
4190                 return 0;
4191
4192         mode = amdgpu_virt_get_sriov_vf_mode(adev);
4193
4194         /* under multi-vf mode, the hwmon attributes are all not supported */
4195         if (mode != SRIOV_VF_MODE_MULTI_VF) {
4196                 adev->pm.int_hwmon_dev = hwmon_device_register_with_groups(adev->dev,
4197                                                                                                                 DRIVER_NAME, adev,
4198                                                                                                                 hwmon_groups);
4199                 if (IS_ERR(adev->pm.int_hwmon_dev)) {
4200                         ret = PTR_ERR(adev->pm.int_hwmon_dev);
4201                         dev_err(adev->dev, "Unable to register hwmon device: %d\n", ret);
4202                         return ret;
4203                 }
4204         }
4205
4206         switch (mode) {
4207         case SRIOV_VF_MODE_ONE_VF:
4208                 mask = ATTR_FLAG_ONEVF;
4209                 break;
4210         case SRIOV_VF_MODE_MULTI_VF:
4211                 mask = 0;
4212                 break;
4213         case SRIOV_VF_MODE_BARE_METAL:
4214         default:
4215                 mask = ATTR_FLAG_MASK_ALL;
4216                 break;
4217         }
4218
4219         ret = amdgpu_device_attr_create_groups(adev,
4220                                                amdgpu_device_attrs,
4221                                                ARRAY_SIZE(amdgpu_device_attrs),
4222                                                mask,
4223                                                &adev->pm.pm_attr_list);
4224         if (ret)
4225                 goto err_out0;
4226
4227         if (amdgpu_dpm_is_overdrive_supported(adev)) {
4228                 ret = amdgpu_od_set_init(adev);
4229                 if (ret)
4230                         goto err_out1;
4231         }
4232
4233         adev->pm.sysfs_initialized = true;
4234
4235         return 0;
4236
4237 err_out1:
4238         amdgpu_device_attr_remove_groups(adev, &adev->pm.pm_attr_list);
4239 err_out0:
4240         if (adev->pm.int_hwmon_dev)
4241                 hwmon_device_unregister(adev->pm.int_hwmon_dev);
4242
4243         return ret;
4244 }
4245
4246 void amdgpu_pm_sysfs_fini(struct amdgpu_device *adev)
4247 {
4248         amdgpu_od_set_fini(adev);
4249
4250         if (adev->pm.int_hwmon_dev)
4251                 hwmon_device_unregister(adev->pm.int_hwmon_dev);
4252
4253         amdgpu_device_attr_remove_groups(adev, &adev->pm.pm_attr_list);
4254 }
4255
4256 /*
4257  * Debugfs info
4258  */
4259 #if defined(CONFIG_DEBUG_FS)
4260
4261 static void amdgpu_debugfs_prints_cpu_info(struct seq_file *m,
4262                                            struct amdgpu_device *adev)
4263 {
4264         uint16_t *p_val;
4265         uint32_t size;
4266         int i;
4267         uint32_t num_cpu_cores = amdgpu_dpm_get_num_cpu_cores(adev);
4268
4269         if (amdgpu_dpm_is_cclk_dpm_supported(adev)) {
4270                 p_val = kcalloc(num_cpu_cores, sizeof(uint16_t),
4271                                 GFP_KERNEL);
4272
4273                 if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_CPU_CLK,
4274                                             (void *)p_val, &size)) {
4275                         for (i = 0; i < num_cpu_cores; i++)
4276                                 seq_printf(m, "\t%u MHz (CPU%d)\n",
4277                                            *(p_val + i), i);
4278                 }
4279
4280                 kfree(p_val);
4281         }
4282 }
4283
4284 static int amdgpu_debugfs_pm_info_pp(struct seq_file *m, struct amdgpu_device *adev)
4285 {
4286         uint32_t mp1_ver = amdgpu_ip_version(adev, MP1_HWIP, 0);
4287         uint32_t gc_ver = amdgpu_ip_version(adev, GC_HWIP, 0);
4288         uint32_t value;
4289         uint64_t value64 = 0;
4290         uint32_t query = 0;
4291         int size;
4292
4293         /* GPU Clocks */
4294         size = sizeof(value);
4295         seq_printf(m, "GFX Clocks and Power:\n");
4296
4297         amdgpu_debugfs_prints_cpu_info(m, adev);
4298
4299         if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_GFX_MCLK, (void *)&value, &size))
4300                 seq_printf(m, "\t%u MHz (MCLK)\n", value/100);
4301         if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_GFX_SCLK, (void *)&value, &size))
4302                 seq_printf(m, "\t%u MHz (SCLK)\n", value/100);
4303         if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_STABLE_PSTATE_SCLK, (void *)&value, &size))
4304                 seq_printf(m, "\t%u MHz (PSTATE_SCLK)\n", value/100);
4305         if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_STABLE_PSTATE_MCLK, (void *)&value, &size))
4306                 seq_printf(m, "\t%u MHz (PSTATE_MCLK)\n", value/100);
4307         if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_VDDGFX, (void *)&value, &size))
4308                 seq_printf(m, "\t%u mV (VDDGFX)\n", value);
4309         if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_VDDNB, (void *)&value, &size))
4310                 seq_printf(m, "\t%u mV (VDDNB)\n", value);
4311         size = sizeof(uint32_t);
4312         if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_GPU_AVG_POWER, (void *)&query, &size))
4313                 seq_printf(m, "\t%u.%02u W (average GPU)\n", query >> 8, query & 0xff);
4314         size = sizeof(uint32_t);
4315         if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_GPU_INPUT_POWER, (void *)&query, &size))
4316                 seq_printf(m, "\t%u.%02u W (current GPU)\n", query >> 8, query & 0xff);
4317         size = sizeof(value);
4318         seq_printf(m, "\n");
4319
4320         /* GPU Temp */
4321         if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_GPU_TEMP, (void *)&value, &size))
4322                 seq_printf(m, "GPU Temperature: %u C\n", value/1000);
4323
4324         /* GPU Load */
4325         if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_GPU_LOAD, (void *)&value, &size))
4326                 seq_printf(m, "GPU Load: %u %%\n", value);
4327         /* MEM Load */
4328         if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_MEM_LOAD, (void *)&value, &size))
4329                 seq_printf(m, "MEM Load: %u %%\n", value);
4330
4331         seq_printf(m, "\n");
4332
4333         /* SMC feature mask */
4334         if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_ENABLED_SMC_FEATURES_MASK, (void *)&value64, &size))
4335                 seq_printf(m, "SMC Feature Mask: 0x%016llx\n", value64);
4336
4337         /* ASICs greater than CHIP_VEGA20 supports these sensors */
4338         if (gc_ver != IP_VERSION(9, 4, 0) && mp1_ver > IP_VERSION(9, 0, 0)) {
4339                 /* VCN clocks */
4340                 if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_VCN_POWER_STATE, (void *)&value, &size)) {
4341                         if (!value) {
4342                                 seq_printf(m, "VCN: Disabled\n");
4343                         } else {
4344                                 seq_printf(m, "VCN: Enabled\n");
4345                                 if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_UVD_DCLK, (void *)&value, &size))
4346                                         seq_printf(m, "\t%u MHz (DCLK)\n", value/100);
4347                                 if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_UVD_VCLK, (void *)&value, &size))
4348                                         seq_printf(m, "\t%u MHz (VCLK)\n", value/100);
4349                         }
4350                 }
4351                 seq_printf(m, "\n");
4352         } else {
4353                 /* UVD clocks */
4354                 if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_UVD_POWER, (void *)&value, &size)) {
4355                         if (!value) {
4356                                 seq_printf(m, "UVD: Disabled\n");
4357                         } else {
4358                                 seq_printf(m, "UVD: Enabled\n");
4359                                 if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_UVD_DCLK, (void *)&value, &size))
4360                                         seq_printf(m, "\t%u MHz (DCLK)\n", value/100);
4361                                 if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_UVD_VCLK, (void *)&value, &size))
4362                                         seq_printf(m, "\t%u MHz (VCLK)\n", value/100);
4363                         }
4364                 }
4365                 seq_printf(m, "\n");
4366
4367                 /* VCE clocks */
4368                 if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_VCE_POWER, (void *)&value, &size)) {
4369                         if (!value) {
4370                                 seq_printf(m, "VCE: Disabled\n");
4371                         } else {
4372                                 seq_printf(m, "VCE: Enabled\n");
4373                                 if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_VCE_ECCLK, (void *)&value, &size))
4374                                         seq_printf(m, "\t%u MHz (ECCLK)\n", value/100);
4375                         }
4376                 }
4377         }
4378
4379         return 0;
4380 }
4381
4382 static const struct cg_flag_name clocks[] = {
4383         {AMD_CG_SUPPORT_GFX_FGCG, "Graphics Fine Grain Clock Gating"},
4384         {AMD_CG_SUPPORT_GFX_MGCG, "Graphics Medium Grain Clock Gating"},
4385         {AMD_CG_SUPPORT_GFX_MGLS, "Graphics Medium Grain memory Light Sleep"},
4386         {AMD_CG_SUPPORT_GFX_CGCG, "Graphics Coarse Grain Clock Gating"},
4387         {AMD_CG_SUPPORT_GFX_CGLS, "Graphics Coarse Grain memory Light Sleep"},
4388         {AMD_CG_SUPPORT_GFX_CGTS, "Graphics Coarse Grain Tree Shader Clock Gating"},
4389         {AMD_CG_SUPPORT_GFX_CGTS_LS, "Graphics Coarse Grain Tree Shader Light Sleep"},
4390         {AMD_CG_SUPPORT_GFX_CP_LS, "Graphics Command Processor Light Sleep"},
4391         {AMD_CG_SUPPORT_GFX_RLC_LS, "Graphics Run List Controller Light Sleep"},
4392         {AMD_CG_SUPPORT_GFX_3D_CGCG, "Graphics 3D Coarse Grain Clock Gating"},
4393         {AMD_CG_SUPPORT_GFX_3D_CGLS, "Graphics 3D Coarse Grain memory Light Sleep"},
4394         {AMD_CG_SUPPORT_MC_LS, "Memory Controller Light Sleep"},
4395         {AMD_CG_SUPPORT_MC_MGCG, "Memory Controller Medium Grain Clock Gating"},
4396         {AMD_CG_SUPPORT_SDMA_LS, "System Direct Memory Access Light Sleep"},
4397         {AMD_CG_SUPPORT_SDMA_MGCG, "System Direct Memory Access Medium Grain Clock Gating"},
4398         {AMD_CG_SUPPORT_BIF_MGCG, "Bus Interface Medium Grain Clock Gating"},
4399         {AMD_CG_SUPPORT_BIF_LS, "Bus Interface Light Sleep"},
4400         {AMD_CG_SUPPORT_UVD_MGCG, "Unified Video Decoder Medium Grain Clock Gating"},
4401         {AMD_CG_SUPPORT_VCE_MGCG, "Video Compression Engine Medium Grain Clock Gating"},
4402         {AMD_CG_SUPPORT_HDP_LS, "Host Data Path Light Sleep"},
4403         {AMD_CG_SUPPORT_HDP_MGCG, "Host Data Path Medium Grain Clock Gating"},
4404         {AMD_CG_SUPPORT_DRM_MGCG, "Digital Right Management Medium Grain Clock Gating"},
4405         {AMD_CG_SUPPORT_DRM_LS, "Digital Right Management Light Sleep"},
4406         {AMD_CG_SUPPORT_ROM_MGCG, "Rom Medium Grain Clock Gating"},
4407         {AMD_CG_SUPPORT_DF_MGCG, "Data Fabric Medium Grain Clock Gating"},
4408         {AMD_CG_SUPPORT_VCN_MGCG, "VCN Medium Grain Clock Gating"},
4409         {AMD_CG_SUPPORT_HDP_DS, "Host Data Path Deep Sleep"},
4410         {AMD_CG_SUPPORT_HDP_SD, "Host Data Path Shutdown"},
4411         {AMD_CG_SUPPORT_IH_CG, "Interrupt Handler Clock Gating"},
4412         {AMD_CG_SUPPORT_JPEG_MGCG, "JPEG Medium Grain Clock Gating"},
4413         {AMD_CG_SUPPORT_REPEATER_FGCG, "Repeater Fine Grain Clock Gating"},
4414         {AMD_CG_SUPPORT_GFX_PERF_CLK, "Perfmon Clock Gating"},
4415         {AMD_CG_SUPPORT_ATHUB_MGCG, "Address Translation Hub Medium Grain Clock Gating"},
4416         {AMD_CG_SUPPORT_ATHUB_LS, "Address Translation Hub Light Sleep"},
4417         {0, NULL},
4418 };
4419
4420 static void amdgpu_parse_cg_state(struct seq_file *m, u64 flags)
4421 {
4422         int i;
4423
4424         for (i = 0; clocks[i].flag; i++)
4425                 seq_printf(m, "\t%s: %s\n", clocks[i].name,
4426                            (flags & clocks[i].flag) ? "On" : "Off");
4427 }
4428
4429 static int amdgpu_debugfs_pm_info_show(struct seq_file *m, void *unused)
4430 {
4431         struct amdgpu_device *adev = (struct amdgpu_device *)m->private;
4432         struct drm_device *dev = adev_to_drm(adev);
4433         u64 flags = 0;
4434         int r;
4435
4436         if (amdgpu_in_reset(adev))
4437                 return -EPERM;
4438         if (adev->in_suspend && !adev->in_runpm)
4439                 return -EPERM;
4440
4441         r = pm_runtime_get_sync(dev->dev);
4442         if (r < 0) {
4443                 pm_runtime_put_autosuspend(dev->dev);
4444                 return r;
4445         }
4446
4447         if (amdgpu_dpm_debugfs_print_current_performance_level(adev, m)) {
4448                 r = amdgpu_debugfs_pm_info_pp(m, adev);
4449                 if (r)
4450                         goto out;
4451         }
4452
4453         amdgpu_device_ip_get_clockgating_state(adev, &flags);
4454
4455         seq_printf(m, "Clock Gating Flags Mask: 0x%llx\n", flags);
4456         amdgpu_parse_cg_state(m, flags);
4457         seq_printf(m, "\n");
4458
4459 out:
4460         pm_runtime_mark_last_busy(dev->dev);
4461         pm_runtime_put_autosuspend(dev->dev);
4462
4463         return r;
4464 }
4465
4466 DEFINE_SHOW_ATTRIBUTE(amdgpu_debugfs_pm_info);
4467
4468 /*
4469  * amdgpu_pm_priv_buffer_read - Read memory region allocated to FW
4470  *
4471  * Reads debug memory region allocated to PMFW
4472  */
4473 static ssize_t amdgpu_pm_prv_buffer_read(struct file *f, char __user *buf,
4474                                          size_t size, loff_t *pos)
4475 {
4476         struct amdgpu_device *adev = file_inode(f)->i_private;
4477         size_t smu_prv_buf_size;
4478         void *smu_prv_buf;
4479         int ret = 0;
4480
4481         if (amdgpu_in_reset(adev))
4482                 return -EPERM;
4483         if (adev->in_suspend && !adev->in_runpm)
4484                 return -EPERM;
4485
4486         ret = amdgpu_dpm_get_smu_prv_buf_details(adev, &smu_prv_buf, &smu_prv_buf_size);
4487         if (ret)
4488                 return ret;
4489
4490         if (!smu_prv_buf || !smu_prv_buf_size)
4491                 return -EINVAL;
4492
4493         return simple_read_from_buffer(buf, size, pos, smu_prv_buf,
4494                                        smu_prv_buf_size);
4495 }
4496
4497 static const struct file_operations amdgpu_debugfs_pm_prv_buffer_fops = {
4498         .owner = THIS_MODULE,
4499         .open = simple_open,
4500         .read = amdgpu_pm_prv_buffer_read,
4501         .llseek = default_llseek,
4502 };
4503
4504 #endif
4505
4506 void amdgpu_debugfs_pm_init(struct amdgpu_device *adev)
4507 {
4508 #if defined(CONFIG_DEBUG_FS)
4509         struct drm_minor *minor = adev_to_drm(adev)->primary;
4510         struct dentry *root = minor->debugfs_root;
4511
4512         if (!adev->pm.dpm_enabled)
4513                 return;
4514
4515         debugfs_create_file("amdgpu_pm_info", 0444, root, adev,
4516                             &amdgpu_debugfs_pm_info_fops);
4517
4518         if (adev->pm.smu_prv_buffer_size > 0)
4519                 debugfs_create_file_size("amdgpu_pm_prv_buffer", 0444, root,
4520                                          adev,
4521                                          &amdgpu_debugfs_pm_prv_buffer_fops,
4522                                          adev->pm.smu_prv_buffer_size);
4523
4524         amdgpu_dpm_stb_debug_fs_init(adev);
4525 #endif
4526 }