drivers/phy/qualcomm/phy-qcom-qmp-combo.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Copyright (c) 2017, The Linux Foundation. All rights reserved.
   4  */
   5
   6 #include <linux/clk.h>
   7 #include <linux/clk-provider.h>
   8 #include <linux/delay.h>
   9 #include <linux/err.h>
  10 #include <linux/io.h>
  11 #include <linux/iopoll.h>
  12 #include <linux/kernel.h>
  13 #include <linux/module.h>
  14 #include <linux/of.h>
  15 #include <linux/of_address.h>
  16 #include <linux/phy/phy.h>
  17 #include <linux/platform_device.h>
  18 #include <linux/regulator/consumer.h>
  19 #include <linux/reset.h>
  20 #include <linux/slab.h>
  21 #include <linux/usb/typec.h>
  22 #include <linux/usb/typec_mux.h>
  23
  24 #include <drm/bridge/aux-bridge.h>
  25
  26 #include <dt-bindings/phy/phy-qcom-qmp.h>
  27
  28 #include "phy-qcom-qmp-common.h"
  29
  30 #include "phy-qcom-qmp.h"
  31 #include "phy-qcom-qmp-pcs-misc-v3.h"
  32 #include "phy-qcom-qmp-pcs-usb-v4.h"
  33 #include "phy-qcom-qmp-pcs-usb-v5.h"
  34 #include "phy-qcom-qmp-pcs-usb-v6.h"
  35
  36 #include "phy-qcom-qmp-dp-com-v3.h"
  37
  38 #include "phy-qcom-qmp-dp-phy.h"
  39 #include "phy-qcom-qmp-dp-phy-v3.h"
  40 #include "phy-qcom-qmp-dp-phy-v4.h"
  41 #include "phy-qcom-qmp-dp-phy-v5.h"
  42 #include "phy-qcom-qmp-dp-phy-v6.h"
  43
  44 /* QPHY_V3_DP_COM_RESET_OVRD_CTRL register bits */
  45 /* DP PHY soft reset */
  46 #define SW_DPPHY_RESET                          BIT(0)
  47 /* mux to select DP PHY reset control, 0:HW control, 1: software reset */
  48 #define SW_DPPHY_RESET_MUX                      BIT(1)
  49 /* USB3 PHY soft reset */
  50 #define SW_USB3PHY_RESET                        BIT(2)
  51 /* mux to select USB3 PHY reset control, 0:HW control, 1: software reset */
  52 #define SW_USB3PHY_RESET_MUX                    BIT(3)
  53
  54 /* QPHY_V3_DP_COM_PHY_MODE_CTRL register bits */
  55 #define USB3_MODE                               BIT(0) /* enables USB3 mode */
  56 #define DP_MODE                                 BIT(1) /* enables DP mode */
  57
  58 /* QPHY_V3_DP_COM_TYPEC_CTRL register bits */
  59 #define SW_PORTSELECT_VAL                       BIT(0)
  60 #define SW_PORTSELECT_MUX                       BIT(1)
  61
  62 #define PHY_INIT_COMPLETE_TIMEOUT               10000
  63
  64 /* set of registers with offsets different per-PHY */
  65 enum qphy_reg_layout {
  66         /* PCS registers */
  67         QPHY_SW_RESET,
  68         QPHY_START_CTRL,
  69         QPHY_PCS_STATUS,
  70         QPHY_PCS_AUTONOMOUS_MODE_CTRL,
  71         QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR,
  72         QPHY_PCS_POWER_DOWN_CONTROL,
  73
  74         QPHY_COM_RESETSM_CNTRL,
  75         QPHY_COM_C_READY_STATUS,
  76         QPHY_COM_CMN_STATUS,
  77         QPHY_COM_BIAS_EN_CLKBUFLR_EN,
  78
  79         QPHY_DP_PHY_STATUS,
  80         QPHY_DP_PHY_VCO_DIV,
  81
  82         QPHY_TX_TX_POL_INV,
  83         QPHY_TX_TX_DRV_LVL,
  84         QPHY_TX_TX_EMP_POST1_LVL,
  85         QPHY_TX_HIGHZ_DRVR_EN,
  86         QPHY_TX_TRANSCEIVER_BIAS_EN,
  87
  88         /* Keep last to ensure regs_layout arrays are properly initialized */
  89         QPHY_LAYOUT_SIZE
  90 };
  91
  92 static const unsigned int qmp_v3_usb3phy_regs_layout[QPHY_LAYOUT_SIZE] = {
  93         [QPHY_SW_RESET]                 = QPHY_V3_PCS_SW_RESET,
  94         [QPHY_START_CTRL]               = QPHY_V3_PCS_START_CONTROL,
  95         [QPHY_PCS_STATUS]               = QPHY_V3_PCS_PCS_STATUS,
  96         [QPHY_PCS_POWER_DOWN_CONTROL]   = QPHY_V3_PCS_POWER_DOWN_CONTROL,
  97         [QPHY_PCS_AUTONOMOUS_MODE_CTRL] = QPHY_V3_PCS_AUTONOMOUS_MODE_CTRL,
  98         [QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR] = QPHY_V3_PCS_LFPS_RXTERM_IRQ_CLEAR,
  99
 100         [QPHY_COM_RESETSM_CNTRL]        = QSERDES_V3_COM_RESETSM_CNTRL,
 101         [QPHY_COM_C_READY_STATUS]       = QSERDES_V3_COM_C_READY_STATUS,
 102         [QPHY_COM_CMN_STATUS]           = QSERDES_V3_COM_CMN_STATUS,
 103         [QPHY_COM_BIAS_EN_CLKBUFLR_EN]  = QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN,
 104
 105         [QPHY_DP_PHY_STATUS]            = QSERDES_V3_DP_PHY_STATUS,
 106         [QPHY_DP_PHY_VCO_DIV]           = QSERDES_V3_DP_PHY_VCO_DIV,
 107
 108         [QPHY_TX_TX_POL_INV]            = QSERDES_V3_TX_TX_POL_INV,
 109         [QPHY_TX_TX_DRV_LVL]            = QSERDES_V3_TX_TX_DRV_LVL,
 110         [QPHY_TX_TX_EMP_POST1_LVL]      = QSERDES_V3_TX_TX_EMP_POST1_LVL,
 111         [QPHY_TX_HIGHZ_DRVR_EN]         = QSERDES_V3_TX_HIGHZ_DRVR_EN,
 112         [QPHY_TX_TRANSCEIVER_BIAS_EN]   = QSERDES_V3_TX_TRANSCEIVER_BIAS_EN,
 113 };
 114
 115 static const unsigned int qmp_v45_usb3phy_regs_layout[QPHY_LAYOUT_SIZE] = {
 116         [QPHY_SW_RESET]                 = QPHY_V4_PCS_SW_RESET,
 117         [QPHY_START_CTRL]               = QPHY_V4_PCS_START_CONTROL,
 118         [QPHY_PCS_STATUS]               = QPHY_V4_PCS_PCS_STATUS1,
 119         [QPHY_PCS_POWER_DOWN_CONTROL]   = QPHY_V4_PCS_POWER_DOWN_CONTROL,
 120
 121         /* In PCS_USB */
 122         [QPHY_PCS_AUTONOMOUS_MODE_CTRL] = QPHY_V4_PCS_USB3_AUTONOMOUS_MODE_CTRL,
 123         [QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR] = QPHY_V4_PCS_USB3_LFPS_RXTERM_IRQ_CLEAR,
 124
 125         [QPHY_COM_RESETSM_CNTRL]        = QSERDES_V4_COM_RESETSM_CNTRL,
 126         [QPHY_COM_C_READY_STATUS]       = QSERDES_V4_COM_C_READY_STATUS,
 127         [QPHY_COM_CMN_STATUS]           = QSERDES_V4_COM_CMN_STATUS,
 128         [QPHY_COM_BIAS_EN_CLKBUFLR_EN]  = QSERDES_V4_COM_BIAS_EN_CLKBUFLR_EN,
 129
 130         [QPHY_DP_PHY_STATUS]            = QSERDES_V4_DP_PHY_STATUS,
 131         [QPHY_DP_PHY_VCO_DIV]           = QSERDES_V4_DP_PHY_VCO_DIV,
 132
 133         [QPHY_TX_TX_POL_INV]            = QSERDES_V4_TX_TX_POL_INV,
 134         [QPHY_TX_TX_DRV_LVL]            = QSERDES_V4_TX_TX_DRV_LVL,
 135         [QPHY_TX_TX_EMP_POST1_LVL]      = QSERDES_V4_TX_TX_EMP_POST1_LVL,
 136         [QPHY_TX_HIGHZ_DRVR_EN]         = QSERDES_V4_TX_HIGHZ_DRVR_EN,
 137         [QPHY_TX_TRANSCEIVER_BIAS_EN]   = QSERDES_V4_TX_TRANSCEIVER_BIAS_EN,
 138 };
 139
 140 static const unsigned int qmp_v5_5nm_usb3phy_regs_layout[QPHY_LAYOUT_SIZE] = {
 141         [QPHY_SW_RESET]                 = QPHY_V5_PCS_SW_RESET,
 142         [QPHY_START_CTRL]               = QPHY_V5_PCS_START_CONTROL,
 143         [QPHY_PCS_STATUS]               = QPHY_V5_PCS_PCS_STATUS1,
 144         [QPHY_PCS_POWER_DOWN_CONTROL]   = QPHY_V5_PCS_POWER_DOWN_CONTROL,
 145
 146         /* In PCS_USB */
 147         [QPHY_PCS_AUTONOMOUS_MODE_CTRL] = QPHY_V5_PCS_USB3_AUTONOMOUS_MODE_CTRL,
 148         [QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR] = QPHY_V5_PCS_USB3_LFPS_RXTERM_IRQ_CLEAR,
 149
 150         [QPHY_COM_RESETSM_CNTRL]        = QSERDES_V5_COM_RESETSM_CNTRL,
 151         [QPHY_COM_C_READY_STATUS]       = QSERDES_V5_COM_C_READY_STATUS,
 152         [QPHY_COM_CMN_STATUS]           = QSERDES_V5_COM_CMN_STATUS,
 153         [QPHY_COM_BIAS_EN_CLKBUFLR_EN]  = QSERDES_V5_COM_BIAS_EN_CLKBUFLR_EN,
 154
 155         [QPHY_DP_PHY_STATUS]            = QSERDES_V5_DP_PHY_STATUS,
 156         [QPHY_DP_PHY_VCO_DIV]           = QSERDES_V5_DP_PHY_VCO_DIV,
 157
 158         [QPHY_TX_TX_POL_INV]            = QSERDES_V5_5NM_TX_TX_POL_INV,
 159         [QPHY_TX_TX_DRV_LVL]            = QSERDES_V5_5NM_TX_TX_DRV_LVL,
 160         [QPHY_TX_TX_EMP_POST1_LVL]      = QSERDES_V5_5NM_TX_TX_EMP_POST1_LVL,
 161         [QPHY_TX_HIGHZ_DRVR_EN]         = QSERDES_V5_5NM_TX_HIGHZ_DRVR_EN,
 162         [QPHY_TX_TRANSCEIVER_BIAS_EN]   = QSERDES_V5_5NM_TX_TRANSCEIVER_BIAS_EN,
 163 };
 164
 165 static const unsigned int qmp_v6_usb3phy_regs_layout[QPHY_LAYOUT_SIZE] = {
 166         [QPHY_SW_RESET]                 = QPHY_V6_PCS_SW_RESET,
 167         [QPHY_START_CTRL]               = QPHY_V6_PCS_START_CONTROL,
 168         [QPHY_PCS_STATUS]               = QPHY_V6_PCS_PCS_STATUS1,
 169         [QPHY_PCS_POWER_DOWN_CONTROL]   = QPHY_V6_PCS_POWER_DOWN_CONTROL,
 170
 171         /* In PCS_USB */
 172         [QPHY_PCS_AUTONOMOUS_MODE_CTRL] = QPHY_V6_PCS_USB3_AUTONOMOUS_MODE_CTRL,
 173         [QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR] = QPHY_V6_PCS_USB3_LFPS_RXTERM_IRQ_CLEAR,
 174
 175         [QPHY_COM_RESETSM_CNTRL]        = QSERDES_V6_COM_RESETSM_CNTRL,
 176         [QPHY_COM_C_READY_STATUS]       = QSERDES_V6_COM_C_READY_STATUS,
 177         [QPHY_COM_CMN_STATUS]           = QSERDES_V6_COM_CMN_STATUS,
 178         [QPHY_COM_BIAS_EN_CLKBUFLR_EN]  = QSERDES_V6_COM_PLL_BIAS_EN_CLK_BUFLR_EN,
 179
 180         [QPHY_DP_PHY_STATUS]            = QSERDES_V6_DP_PHY_STATUS,
 181         [QPHY_DP_PHY_VCO_DIV]           = QSERDES_V6_DP_PHY_VCO_DIV,
 182
 183         [QPHY_TX_TX_POL_INV]            = QSERDES_V6_TX_TX_POL_INV,
 184         [QPHY_TX_TX_DRV_LVL]            = QSERDES_V6_TX_TX_DRV_LVL,
 185         [QPHY_TX_TX_EMP_POST1_LVL]      = QSERDES_V6_TX_TX_EMP_POST1_LVL,
 186         [QPHY_TX_HIGHZ_DRVR_EN]         = QSERDES_V6_TX_HIGHZ_DRVR_EN,
 187         [QPHY_TX_TRANSCEIVER_BIAS_EN]   = QSERDES_V6_TX_TRANSCEIVER_BIAS_EN,
 188 };
 189
 190 static const unsigned int qmp_v6_n4_usb3phy_regs_layout[QPHY_LAYOUT_SIZE] = {
 191         [QPHY_SW_RESET]                 = QPHY_V6_N4_PCS_SW_RESET,
 192         [QPHY_START_CTRL]               = QPHY_V6_N4_PCS_START_CONTROL,
 193         [QPHY_PCS_STATUS]               = QPHY_V6_N4_PCS_PCS_STATUS1,
 194         [QPHY_PCS_POWER_DOWN_CONTROL]   = QPHY_V6_N4_PCS_POWER_DOWN_CONTROL,
 195
 196         /* In PCS_USB */
 197         [QPHY_PCS_AUTONOMOUS_MODE_CTRL] = QPHY_V6_PCS_USB3_AUTONOMOUS_MODE_CTRL,
 198         [QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR] = QPHY_V6_PCS_USB3_LFPS_RXTERM_IRQ_CLEAR,
 199
 200         [QPHY_COM_RESETSM_CNTRL]        = QSERDES_V6_COM_RESETSM_CNTRL,
 201         [QPHY_COM_C_READY_STATUS]       = QSERDES_V6_COM_C_READY_STATUS,
 202         [QPHY_COM_CMN_STATUS]           = QSERDES_V6_COM_CMN_STATUS,
 203         [QPHY_COM_BIAS_EN_CLKBUFLR_EN]  = QSERDES_V6_COM_PLL_BIAS_EN_CLK_BUFLR_EN,
 204
 205         [QPHY_DP_PHY_STATUS]            = QSERDES_V6_DP_PHY_STATUS,
 206         [QPHY_DP_PHY_VCO_DIV]           = QSERDES_V6_DP_PHY_VCO_DIV,
 207
 208         [QPHY_TX_TX_POL_INV]            = QSERDES_V6_N4_TX_TX_POL_INV,
 209         [QPHY_TX_TX_DRV_LVL]            = QSERDES_V6_N4_TX_TX_DRV_LVL,
 210         [QPHY_TX_TX_EMP_POST1_LVL]      = QSERDES_V6_N4_TX_TX_EMP_POST1_LVL,
 211         [QPHY_TX_HIGHZ_DRVR_EN]         = QSERDES_V6_N4_TX_HIGHZ_DRVR_EN,
 212         [QPHY_TX_TRANSCEIVER_BIAS_EN]   = QSERDES_V6_N4_TX_TRANSCEIVER_BIAS_EN,
 213 };
 214
 215 static const struct qmp_phy_init_tbl qmp_v3_usb3_serdes_tbl[] = {
 216         QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_IVCO, 0x07),
 217         QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_EN_SEL, 0x14),
 218         QMP_PHY_INIT_CFG(QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN, 0x08),
 219         QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x30),
 220         QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYS_CLK_CTRL, 0x02),
 221         QMP_PHY_INIT_CFG(QSERDES_V3_COM_RESETSM_CNTRL2, 0x08),
 222         QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_CONFIG, 0x16),
 223         QMP_PHY_INIT_CFG(QSERDES_V3_COM_SVS_MODE_CLK_SEL, 0x01),
 224         QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x80),
 225         QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x82),
 226         QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START1_MODE0, 0xab),
 227         QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0xea),
 228         QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x02),
 229         QMP_PHY_INIT_CFG(QSERDES_V3_COM_CP_CTRL_MODE0, 0x06),
 230         QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_RCTRL_MODE0, 0x16),
 231         QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_CCTRL_MODE0, 0x36),
 232         QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
 233         QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE0, 0x3f),
 234         QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE2_MODE0, 0x01),
 235         QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE1_MODE0, 0xc9),
 236         QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORECLK_DIV_MODE0, 0x0a),
 237         QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP3_MODE0, 0x00),
 238         QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x34),
 239         QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x15),
 240         QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x04),
 241         QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORE_CLK_EN, 0x00),
 242         QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_CFG, 0x00),
 243         QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x00),
 244         QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_BUF_ENABLE, 0x0a),
 245         QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_EN_CENTER, 0x01),
 246         QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER1, 0x31),
 247         QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER2, 0x01),
 248         QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER1, 0x00),
 249         QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER2, 0x00),
 250         QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE1, 0x85),
 251         QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE2, 0x07),
 252 };
 253
 254 static const struct qmp_phy_init_tbl qmp_v3_usb3_tx_tbl[] = {
 255         QMP_PHY_INIT_CFG(QSERDES_V3_TX_HIGHZ_DRVR_EN, 0x10),
 256         QMP_PHY_INIT_CFG(QSERDES_V3_TX_RCV_DETECT_LVL_2, 0x12),
 257         QMP_PHY_INIT_CFG(QSERDES_V3_TX_LANE_MODE_1, 0x16),
 258         QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_RX, 0x09),
 259         QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX, 0x06),
 260 };
 261
 262 static const struct qmp_phy_init_tbl qmp_v3_dp_serdes_tbl[] = {
 263         QMP_PHY_INIT_CFG(QSERDES_V3_COM_SVS_MODE_CLK_SEL, 0x01),
 264         QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_EN_SEL, 0x37),
 265         QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYS_CLK_CTRL, 0x02),
 266         QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_ENABLE1, 0x0e),
 267         QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_BUF_ENABLE, 0x06),
 268         QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x30),
 269         QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_CONFIG, 0x02),
 270         QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START1_MODE0, 0x00),
 271         QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE0, 0x3f),
 272         QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
 273         QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x00),
 274         QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP3_MODE0, 0x00),
 275         QMP_PHY_INIT_CFG(QSERDES_V3_COM_BG_TIMER, 0x0a),
 276         QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORECLK_DIV_MODE0, 0x0a),
 277         QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_CTRL, 0x00),
 278         QMP_PHY_INIT_CFG(QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN, 0x3f),
 279         QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORE_CLK_EN, 0x1f),
 280         QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_IVCO, 0x07),
 281         QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_CCTRL_MODE0, 0x36),
 282         QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_RCTRL_MODE0, 0x16),
 283         QMP_PHY_INIT_CFG(QSERDES_V3_COM_CP_CTRL_MODE0, 0x06),
 284 };
 285
 286 static const struct qmp_phy_init_tbl qmp_v3_dp_serdes_tbl_rbr[] = {
 287         QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x0c),
 288         QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x69),
 289         QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0x80),
 290         QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x07),
 291         QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x6f),
 292         QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x08),
 293         QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x00),
 294 };
 295
 296 static const struct qmp_phy_init_tbl qmp_v3_dp_serdes_tbl_hbr[] = {
 297         QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x04),
 298         QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x69),
 299         QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0x80),
 300         QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x07),
 301         QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x0f),
 302         QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x0e),
 303         QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x00),
 304 };
 305
 306 static const struct qmp_phy_init_tbl qmp_v3_dp_serdes_tbl_hbr2[] = {
 307         QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x00),
 308         QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x8c),
 309         QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0x00),
 310         QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x0a),
 311         QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x1f),
 312         QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x1c),
 313         QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x00),
 314 };
 315
 316 static const struct qmp_phy_init_tbl qmp_v3_dp_serdes_tbl_hbr3[] = {
 317         QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x03),
 318         QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x69),
 319         QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0x80),
 320         QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x07),
 321         QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x2f),
 322         QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x2a),
 323         QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x08),
 324 };
 325
 326 static const struct qmp_phy_init_tbl qmp_v3_dp_tx_tbl[] = {
 327         QMP_PHY_INIT_CFG(QSERDES_V3_TX_TRANSCEIVER_BIAS_EN, 0x1a),
 328         QMP_PHY_INIT_CFG(QSERDES_V3_TX_VMODE_CTRL1, 0x40),
 329         QMP_PHY_INIT_CFG(QSERDES_V3_TX_PRE_STALL_LDO_BOOST_EN, 0x30),
 330         QMP_PHY_INIT_CFG(QSERDES_V3_TX_INTERFACE_SELECT, 0x3d),
 331         QMP_PHY_INIT_CFG(QSERDES_V3_TX_CLKBUF_ENABLE, 0x0f),
 332         QMP_PHY_INIT_CFG(QSERDES_V3_TX_RESET_TSYNC_EN, 0x03),
 333         QMP_PHY_INIT_CFG(QSERDES_V3_TX_TRAN_DRVR_EMP_EN, 0x03),
 334         QMP_PHY_INIT_CFG(QSERDES_V3_TX_PARRATE_REC_DETECT_IDLE_EN, 0x00),
 335         QMP_PHY_INIT_CFG(QSERDES_V3_TX_TX_INTERFACE_MODE, 0x00),
 336         QMP_PHY_INIT_CFG(QSERDES_V3_TX_TX_BAND, 0x4),
 337         QMP_PHY_INIT_CFG(QSERDES_V3_TX_TX_POL_INV, 0x0a),
 338         QMP_PHY_INIT_CFG(QSERDES_V3_TX_TX_DRV_LVL, 0x38),
 339         QMP_PHY_INIT_CFG(QSERDES_V3_TX_TX_EMP_POST1_LVL, 0x20),
 340         QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX, 0x06),
 341         QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_RX, 0x07),
 342 };
 343
 344 static const struct qmp_phy_init_tbl qmp_v3_usb3_rx_tbl[] = {
 345         QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_FO_GAIN, 0x0b),
 346         QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f),
 347         QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4e),
 348         QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL4, 0x18),
 349         QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x77),
 350         QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
 351         QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_CNTRL, 0x03),
 352         QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_DEGLITCH_CNTRL, 0x16),
 353         QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x75),
 354 };
 355
 356 static const struct qmp_phy_init_tbl qmp_v3_usb3_pcs_tbl[] = {
 357         /* FLL settings */
 358         QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL2, 0x83),
 359         QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_L, 0x09),
 360         QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_H_TOL, 0xa2),
 361         QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_MAN_CODE, 0x40),
 362         QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL1, 0x02),
 363
 364         /* Lock Det settings */
 365         QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG1, 0xd1),
 366         QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG2, 0x1f),
 367         QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG3, 0x47),
 368         QMP_PHY_INIT_CFG(QPHY_V3_PCS_POWER_STATE_CONFIG2, 0x1b),
 369
 370         QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_LVL, 0xba),
 371         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V0, 0x9f),
 372         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V1, 0x9f),
 373         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V2, 0xb7),
 374         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V3, 0x4e),
 375         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V4, 0x65),
 376         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_LS, 0x6b),
 377         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V0, 0x15),
 378         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V0, 0x0d),
 379         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V1, 0x15),
 380         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V1, 0x0d),
 381         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V2, 0x15),
 382         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V2, 0x0d),
 383         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V3, 0x15),
 384         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V3, 0x1d),
 385         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V4, 0x15),
 386         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V4, 0x0d),
 387         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_LS, 0x15),
 388         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_LS, 0x0d),
 389
 390         QMP_PHY_INIT_CFG(QPHY_V3_PCS_RATE_SLEW_CNTRL, 0x02),
 391         QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x04),
 392         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TSYNC_RSYNC_TIME, 0x44),
 393         QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x04),
 394         QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7),
 395         QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03),
 396         QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_L, 0x40),
 397         QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_H, 0x00),
 398         QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_WAIT_TIME, 0x75),
 399         QMP_PHY_INIT_CFG(QPHY_V3_PCS_LFPS_TX_ECSTART_EQTLOCK, 0x86),
 400         QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_RUN_TIME, 0x13),
 401 };
 402
 403 static const struct qmp_phy_init_tbl sm6350_usb3_rx_tbl[] = {
 404         QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_FO_GAIN, 0x0b),
 405         QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f),
 406         QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4e),
 407         QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL4, 0x18),
 408         QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x77),
 409         QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
 410         QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_CNTRL, 0x03),
 411         QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_DEGLITCH_CNTRL, 0x16),
 412         QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_MODE_00, 0x05),
 413         QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x75),
 414 };
 415
 416 static const struct qmp_phy_init_tbl sm6350_usb3_pcs_tbl[] = {
 417         /* FLL settings */
 418         QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL2, 0x83),
 419         QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_L, 0x09),
 420         QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_H_TOL, 0xa2),
 421         QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_MAN_CODE, 0x40),
 422         QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL1, 0x02),
 423
 424         /* Lock Det settings */
 425         QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG1, 0xd1),
 426         QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG2, 0x1f),
 427         QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG3, 0x47),
 428         QMP_PHY_INIT_CFG(QPHY_V3_PCS_POWER_STATE_CONFIG2, 0x1b),
 429
 430         QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_LVL, 0xcc),
 431         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V0, 0x9f),
 432         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V1, 0x9f),
 433         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V2, 0xb7),
 434         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V3, 0x4e),
 435         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V4, 0x65),
 436         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_LS, 0x6b),
 437         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V0, 0x15),
 438         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V0, 0x0d),
 439         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V1, 0x15),
 440         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V1, 0x0d),
 441         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V2, 0x15),
 442         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V2, 0x0d),
 443         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V3, 0x15),
 444         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V3, 0x1d),
 445         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V4, 0x15),
 446         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V4, 0x0d),
 447         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_LS, 0x15),
 448         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_LS, 0x0d),
 449
 450         QMP_PHY_INIT_CFG(QPHY_V3_PCS_RATE_SLEW_CNTRL, 0x02),
 451         QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x04),
 452         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TSYNC_RSYNC_TIME, 0x44),
 453         QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x04),
 454         QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7),
 455         QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03),
 456         QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_L, 0x40),
 457         QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_H, 0x00),
 458         QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_WAIT_TIME, 0x75),
 459         QMP_PHY_INIT_CFG(QPHY_V3_PCS_LFPS_TX_ECSTART_EQTLOCK, 0x86),
 460         QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_RUN_TIME, 0x13),
 461         QMP_PHY_INIT_CFG(QPHY_V3_PCS_LFPS_DET_HIGH_COUNT_VAL, 0x04),
 462
 463         QMP_PHY_INIT_CFG(QPHY_V3_PCS_REFGEN_REQ_CONFIG1, 0x21),
 464         QMP_PHY_INIT_CFG(QPHY_V3_PCS_REFGEN_REQ_CONFIG2, 0x60),
 465 };
 466
 467 static const struct qmp_phy_init_tbl sm8150_usb3_serdes_tbl[] = {
 468         QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_EN_CENTER, 0x01),
 469         QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_PER1, 0x31),
 470         QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_PER2, 0x01),
 471         QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE1_MODE0, 0xde),
 472         QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE2_MODE0, 0x07),
 473         QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE1_MODE1, 0xde),
 474         QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE2_MODE1, 0x07),
 475         QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_BUF_ENABLE, 0x0a),
 476         QMP_PHY_INIT_CFG(QSERDES_V4_COM_CMN_IPTRIM, 0x20),
 477         QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE0, 0x06),
 478         QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE1, 0x06),
 479         QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE0, 0x16),
 480         QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE1, 0x16),
 481         QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE0, 0x36),
 482         QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE1, 0x36),
 483         QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_EN_SEL, 0x1a),
 484         QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x04),
 485         QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x14),
 486         QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x34),
 487         QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE1, 0x34),
 488         QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE1, 0x82),
 489         QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x82),
 490         QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE1, 0x82),
 491         QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE0, 0xab),
 492         QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE0, 0xea),
 493         QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x02),
 494         QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_MAP, 0x02),
 495         QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE1, 0xab),
 496         QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE1, 0xea),
 497         QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE1, 0x02),
 498         QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE1_MODE0, 0x24),
 499         QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE1_MODE1, 0x24),
 500         QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE2_MODE1, 0x02),
 501         QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x01),
 502         QMP_PHY_INIT_CFG(QSERDES_V4_COM_CORECLK_DIV_MODE1, 0x08),
 503         QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0xca),
 504         QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1e),
 505         QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0xca),
 506         QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x1e),
 507         QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_HSCLK_SEL, 0x11),
 508 };
 509
 510 static const struct qmp_phy_init_tbl sm8150_usb3_tx_tbl[] = {
 511         QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_TX, 0x00),
 512         QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_RX, 0x00),
 513         QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0xd5),
 514         QMP_PHY_INIT_CFG(QSERDES_V4_TX_RCV_DETECT_LVL_2, 0x12),
 515         QMP_PHY_INIT_CFG(QSERDES_V4_TX_PI_QEC_CTRL, 0x20),
 516 };
 517
 518 static const struct qmp_phy_init_tbl sm8150_usb3_rx_tbl[] = {
 519         QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x05),
 520         QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_FO_GAIN, 0x2f),
 521         QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f),
 522         QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_LOW, 0xff),
 523         QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x0f),
 524         QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0x99),
 525         QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH1, 0x04),
 526         QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH2, 0x08),
 527         QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN1, 0x05),
 528         QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN2, 0x05),
 529         QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL1, 0x54),
 530         QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL2, 0x0e),
 531         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f),
 532         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4a),
 533         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a),
 534         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0),
 535         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00),
 536         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x77),
 537         QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x04),
 538         QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x0e),
 539         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0xbf),
 540         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH, 0xbf),
 541         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0x3f),
 542         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0x7f),
 543         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x94),
 544         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0xdc),
 545         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0xdc),
 546         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0x5c),
 547         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x0b),
 548         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0xb3),
 549         QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_EN_TIMER, 0x04),
 550         QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),
 551         QMP_PHY_INIT_CFG(QSERDES_V4_RX_AUX_DATA_TCOARSE_TFINE, 0xa0),
 552         QMP_PHY_INIT_CFG(QSERDES_V4_RX_DCC_CTRL1, 0x0c),
 553         QMP_PHY_INIT_CFG(QSERDES_V4_RX_GM_CAL, 0x1f),
 554         QMP_PHY_INIT_CFG(QSERDES_V4_RX_VTH_CODE, 0x10),
 555 };
 556
 557 static const struct qmp_phy_init_tbl sm8150_usb3_pcs_tbl[] = {
 558         /* Lock Det settings */
 559         QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG1, 0xd0),
 560         QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG2, 0x07),
 561         QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG6, 0x13),
 562
 563         QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x21),
 564         QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0xaa),
 565         QMP_PHY_INIT_CFG(QPHY_V4_PCS_CDR_RESET_TIME, 0x0a),
 566         QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG1, 0x88),
 567         QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG2, 0x13),
 568         QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCS_TX_RX_CONFIG, 0x0c),
 569         QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG1, 0x4b),
 570         QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG5, 0x10),
 571 };
 572
 573 static const struct qmp_phy_init_tbl sm8150_usb3_pcs_usb_tbl[] = {
 574         QMP_PHY_INIT_CFG(QPHY_V4_PCS_USB3_LFPS_DET_HIGH_COUNT_VAL, 0xf8),
 575         QMP_PHY_INIT_CFG(QPHY_V4_PCS_USB3_RXEQTRAINING_DFE_TIME_S2, 0x07),
 576 };
 577
 578 static const struct qmp_phy_init_tbl sm8250_usb3_tx_tbl[] = {
 579         QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_TX, 0x60),
 580         QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_RX, 0x60),
 581         QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_TX, 0x11),
 582         QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_RX, 0x02),
 583         QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0xd5),
 584         QMP_PHY_INIT_CFG(QSERDES_V4_TX_RCV_DETECT_LVL_2, 0x12),
 585         QMP_PHY_INIT_CFG_LANE(QSERDES_V4_TX_PI_QEC_CTRL, 0x40, 1),
 586         QMP_PHY_INIT_CFG_LANE(QSERDES_V4_TX_PI_QEC_CTRL, 0x54, 2),
 587 };
 588
 589 static const struct qmp_phy_init_tbl sm8250_usb3_rx_tbl[] = {
 590         QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x06),
 591         QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_FO_GAIN, 0x2f),
 592         QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f),
 593         QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_LOW, 0xff),
 594         QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x0f),
 595         QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0x99),
 596         QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH1, 0x04),
 597         QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH2, 0x08),
 598         QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN1, 0x05),
 599         QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN2, 0x05),
 600         QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL1, 0x54),
 601         QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL2, 0x0c),
 602         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f),
 603         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4a),
 604         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a),
 605         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0),
 606         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00),
 607         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x77),
 608         QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x04),
 609         QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x0e),
 610         QMP_PHY_INIT_CFG_LANE(QSERDES_V4_RX_RX_MODE_00_LOW, 0xff, 1),
 611         QMP_PHY_INIT_CFG_LANE(QSERDES_V4_RX_RX_MODE_00_LOW, 0x7f, 2),
 612         QMP_PHY_INIT_CFG_LANE(QSERDES_V4_RX_RX_MODE_00_HIGH, 0x7f, 1),
 613         QMP_PHY_INIT_CFG_LANE(QSERDES_V4_RX_RX_MODE_00_HIGH, 0xff, 2),
 614         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0x7f),
 615         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0x7f),
 616         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x97),
 617         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0xdc),
 618         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0xdc),
 619         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0x5c),
 620         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x7b),
 621         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0xb4),
 622         QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_EN_TIMER, 0x04),
 623         QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),
 624         QMP_PHY_INIT_CFG(QSERDES_V4_RX_AUX_DATA_TCOARSE_TFINE, 0xa0),
 625         QMP_PHY_INIT_CFG(QSERDES_V4_RX_DCC_CTRL1, 0x0c),
 626         QMP_PHY_INIT_CFG(QSERDES_V4_RX_GM_CAL, 0x1f),
 627         QMP_PHY_INIT_CFG(QSERDES_V4_RX_VTH_CODE, 0x10),
 628 };
 629
 630 static const struct qmp_phy_init_tbl sm8250_usb3_pcs_tbl[] = {
 631         QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG1, 0xd0),
 632         QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG2, 0x07),
 633         QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG3, 0x20),
 634         QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG6, 0x13),
 635         QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x21),
 636         QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0xa9),
 637         QMP_PHY_INIT_CFG(QPHY_V4_PCS_CDR_RESET_TIME, 0x0a),
 638         QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG1, 0x88),
 639         QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG2, 0x13),
 640         QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCS_TX_RX_CONFIG, 0x0c),
 641         QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG1, 0x4b),
 642         QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG5, 0x10),
 643 };
 644
 645 static const struct qmp_phy_init_tbl sm8250_usb3_pcs_usb_tbl[] = {
 646         QMP_PHY_INIT_CFG(QPHY_V4_PCS_USB3_LFPS_DET_HIGH_COUNT_VAL, 0xf8),
 647         QMP_PHY_INIT_CFG(QPHY_V4_PCS_USB3_RXEQTRAINING_DFE_TIME_S2, 0x07),
 648 };
 649
 650 static const struct qmp_phy_init_tbl sm8350_usb3_tx_tbl[] = {
 651         QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_TX, 0x00),
 652         QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_RX, 0x00),
 653         QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_TX, 0x16),
 654         QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_RX, 0x0e),
 655         QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_1, 0x35),
 656         QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_3, 0x3f),
 657         QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_4, 0x7f),
 658         QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_5, 0x3f),
 659         QMP_PHY_INIT_CFG(QSERDES_V5_TX_RCV_DETECT_LVL_2, 0x12),
 660         QMP_PHY_INIT_CFG(QSERDES_V5_TX_PI_QEC_CTRL, 0x21),
 661 };
 662
 663 static const struct qmp_phy_init_tbl sm8350_usb3_rx_tbl[] = {
 664         QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FO_GAIN, 0x0a),
 665         QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SO_GAIN, 0x05),
 666         QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_FO_GAIN, 0x2f),
 667         QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f),
 668         QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_COUNT_LOW, 0xff),
 669         QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x0f),
 670         QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_PI_CONTROLS, 0x99),
 671         QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH1, 0x08),
 672         QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH2, 0x08),
 673         QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_GAIN1, 0x00),
 674         QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_GAIN2, 0x04),
 675         QMP_PHY_INIT_CFG(QSERDES_V5_RX_VGA_CAL_CNTRL1, 0x54),
 676         QMP_PHY_INIT_CFG(QSERDES_V5_RX_VGA_CAL_CNTRL2, 0x0f),
 677         QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f),
 678         QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4a),
 679         QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a),
 680         QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_IDAC_TSETTLE_LOW, 0xc0),
 681         QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_IDAC_TSETTLE_HIGH, 0x00),
 682         QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x47),
 683         QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_CNTRL, 0x04),
 684         QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_DEGLITCH_CNTRL, 0x0e),
 685         QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_LOW, 0xbb),
 686         QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH, 0x7b),
 687         QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH2, 0xbb),
 688         QMP_PHY_INIT_CFG_LANE(QSERDES_V5_RX_RX_MODE_00_HIGH3, 0x3d, 1),
 689         QMP_PHY_INIT_CFG_LANE(QSERDES_V5_RX_RX_MODE_00_HIGH3, 0x3c, 2),
 690         QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH4, 0xdb),
 691         QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_LOW, 0x64),
 692         QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH, 0x24),
 693         QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH2, 0xd2),
 694         QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH3, 0x13),
 695         QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH4, 0xa9),
 696         QMP_PHY_INIT_CFG(QSERDES_V5_RX_DFE_EN_TIMER, 0x04),
 697         QMP_PHY_INIT_CFG(QSERDES_V5_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),
 698         QMP_PHY_INIT_CFG(QSERDES_V5_RX_AUX_DATA_TCOARSE_TFINE, 0xa0),
 699         QMP_PHY_INIT_CFG(QSERDES_V5_RX_DCC_CTRL1, 0x0c),
 700         QMP_PHY_INIT_CFG(QSERDES_V5_RX_GM_CAL, 0x00),
 701         QMP_PHY_INIT_CFG(QSERDES_V5_RX_VTH_CODE, 0x10),
 702 };
 703
 704 static const struct qmp_phy_init_tbl sm8350_usb3_pcs_tbl[] = {
 705         QMP_PHY_INIT_CFG(QPHY_V4_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7),
 706         QMP_PHY_INIT_CFG(QPHY_V4_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03),
 707         QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG1, 0xd0),
 708         QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG2, 0x07),
 709         QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG3, 0x20),
 710         QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG6, 0x13),
 711         QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x21),
 712         QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0xaa),
 713         QMP_PHY_INIT_CFG(QPHY_V4_PCS_CDR_RESET_TIME, 0x0a),
 714         QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG1, 0x88),
 715         QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG2, 0x13),
 716         QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCS_TX_RX_CONFIG, 0x0c),
 717         QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG1, 0x4b),
 718         QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG5, 0x10),
 719 };
 720
 721 static const struct qmp_phy_init_tbl sm8350_usb3_pcs_usb_tbl[] = {
 722         QMP_PHY_INIT_CFG(QPHY_V5_PCS_USB3_RCVR_DTCT_DLY_U3_L, 0x40),
 723         QMP_PHY_INIT_CFG(QPHY_V5_PCS_USB3_RCVR_DTCT_DLY_U3_H, 0x00),
 724         QMP_PHY_INIT_CFG(QPHY_V5_PCS_USB3_LFPS_DET_HIGH_COUNT_VAL, 0xf8),
 725         QMP_PHY_INIT_CFG(QPHY_V5_PCS_USB3_RXEQTRAINING_DFE_TIME_S2, 0x07),
 726 };
 727
 728 static const struct qmp_phy_init_tbl sm8550_usb3_serdes_tbl[] = {
 729         QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_STEP_SIZE1_MODE1, 0xc0),
 730         QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_STEP_SIZE2_MODE1, 0x01),
 731         QMP_PHY_INIT_CFG(QSERDES_V6_COM_CP_CTRL_MODE1, 0x02),
 732         QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_RCTRL_MODE1, 0x16),
 733         QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CCTRL_MODE1, 0x36),
 734         QMP_PHY_INIT_CFG(QSERDES_V6_COM_CORECLK_DIV_MODE1, 0x04),
 735         QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP1_MODE1, 0x16),
 736         QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP2_MODE1, 0x41),
 737         QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE1, 0x41),
 738         QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MSB_MODE1, 0x00),
 739         QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START1_MODE1, 0x55),
 740         QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START2_MODE1, 0x75),
 741         QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START3_MODE1, 0x01),
 742         QMP_PHY_INIT_CFG(QSERDES_V6_COM_HSCLK_SEL_1, 0x01),
 743         QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE1_MODE1, 0x25),
 744         QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE2_MODE1, 0x02),
 745         QMP_PHY_INIT_CFG(QSERDES_V6_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0x5c),
 746         QMP_PHY_INIT_CFG(QSERDES_V6_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x0f),
 747         QMP_PHY_INIT_CFG(QSERDES_V6_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0x5c),
 748         QMP_PHY_INIT_CFG(QSERDES_V6_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x0f),
 749         QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_STEP_SIZE1_MODE0, 0xc0),
 750         QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_STEP_SIZE2_MODE0, 0x01),
 751         QMP_PHY_INIT_CFG(QSERDES_V6_COM_CP_CTRL_MODE0, 0x02),
 752         QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_RCTRL_MODE0, 0x16),
 753         QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CCTRL_MODE0, 0x36),
 754         QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP1_MODE0, 0x08),
 755         QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP2_MODE0, 0x1a),
 756         QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE0, 0x41),
 757         QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MSB_MODE0, 0x00),
 758         QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START1_MODE0, 0x55),
 759         QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START2_MODE0, 0x75),
 760         QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START3_MODE0, 0x01),
 761         QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE1_MODE0, 0x25),
 762         QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE2_MODE0, 0x02),
 763         QMP_PHY_INIT_CFG(QSERDES_V6_COM_BG_TIMER, 0x0a),
 764         QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_EN_CENTER, 0x01),
 765         QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_PER1, 0x62),
 766         QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_PER2, 0x02),
 767         QMP_PHY_INIT_CFG(QSERDES_V6_COM_SYSCLK_BUF_ENABLE, 0x0c),
 768         QMP_PHY_INIT_CFG(QSERDES_V6_COM_SYSCLK_EN_SEL, 0x1a),
 769         QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP_CFG, 0x14),
 770         QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE_MAP, 0x04),
 771         QMP_PHY_INIT_CFG(QSERDES_V6_COM_CORE_CLK_EN, 0x20),
 772         QMP_PHY_INIT_CFG(QSERDES_V6_COM_CMN_CONFIG_1, 0x16),
 773         QMP_PHY_INIT_CFG(QSERDES_V6_COM_AUTO_GAIN_ADJ_CTRL_1, 0xb6),
 774         QMP_PHY_INIT_CFG(QSERDES_V6_COM_AUTO_GAIN_ADJ_CTRL_2, 0x4b),
 775         QMP_PHY_INIT_CFG(QSERDES_V6_COM_AUTO_GAIN_ADJ_CTRL_3, 0x37),
 776         QMP_PHY_INIT_CFG(QSERDES_V6_COM_ADDITIONAL_MISC, 0x0c),
 777 };
 778
 779 static const struct qmp_phy_init_tbl sm8550_usb3_tx_tbl[] = {
 780         QMP_PHY_INIT_CFG(QSERDES_V6_TX_RES_CODE_LANE_TX, 0x00),
 781         QMP_PHY_INIT_CFG(QSERDES_V6_TX_RES_CODE_LANE_RX, 0x00),
 782         QMP_PHY_INIT_CFG(QSERDES_V6_TX_RES_CODE_LANE_OFFSET_TX, 0x1f),
 783         QMP_PHY_INIT_CFG(QSERDES_V6_TX_RES_CODE_LANE_OFFSET_RX, 0x09),
 784         QMP_PHY_INIT_CFG(QSERDES_V6_TX_LANE_MODE_1, 0xf5),
 785         QMP_PHY_INIT_CFG(QSERDES_V6_TX_LANE_MODE_3, 0x3f),
 786         QMP_PHY_INIT_CFG(QSERDES_V6_TX_LANE_MODE_4, 0x3f),
 787         QMP_PHY_INIT_CFG(QSERDES_V6_TX_LANE_MODE_5, 0x5f),
 788         QMP_PHY_INIT_CFG(QSERDES_V6_TX_RCV_DETECT_LVL_2, 0x12),
 789         QMP_PHY_INIT_CFG_LANE(QSERDES_V6_TX_PI_QEC_CTRL, 0x21, 1),
 790         QMP_PHY_INIT_CFG_LANE(QSERDES_V6_TX_PI_QEC_CTRL, 0x05, 2),
 791 };
 792
 793 static const struct qmp_phy_init_tbl sm8550_usb3_rx_tbl[] = {
 794         QMP_PHY_INIT_CFG(QSERDES_V6_RX_UCDR_FO_GAIN, 0x0a),
 795         QMP_PHY_INIT_CFG(QSERDES_V6_RX_UCDR_SO_GAIN, 0x06),
 796         QMP_PHY_INIT_CFG(QSERDES_V6_RX_UCDR_FASTLOCK_FO_GAIN, 0x2f),
 797         QMP_PHY_INIT_CFG(QSERDES_V6_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f),
 798         QMP_PHY_INIT_CFG(QSERDES_V6_RX_UCDR_FASTLOCK_COUNT_LOW, 0xff),
 799         QMP_PHY_INIT_CFG(QSERDES_V6_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x0f),
 800         QMP_PHY_INIT_CFG(QSERDES_V6_RX_UCDR_PI_CONTROLS, 0x99),
 801         QMP_PHY_INIT_CFG(QSERDES_V6_RX_UCDR_SB2_THRESH1, 0x08),
 802         QMP_PHY_INIT_CFG(QSERDES_V6_RX_UCDR_SB2_THRESH2, 0x08),
 803         QMP_PHY_INIT_CFG(QSERDES_V6_RX_UCDR_SB2_GAIN1, 0x00),
 804         QMP_PHY_INIT_CFG(QSERDES_V6_RX_UCDR_SB2_GAIN2, 0x0a),
 805         QMP_PHY_INIT_CFG(QSERDES_V6_RX_AUX_DATA_TCOARSE_TFINE, 0xa0),
 806         QMP_PHY_INIT_CFG(QSERDES_V6_RX_VGA_CAL_CNTRL1, 0x54),
 807         QMP_PHY_INIT_CFG(QSERDES_V6_RX_VGA_CAL_CNTRL2, 0x0f),
 808         QMP_PHY_INIT_CFG(QSERDES_V6_RX_GM_CAL, 0x13),
 809         QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f),
 810         QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4a),
 811         QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a),
 812         QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_IDAC_TSETTLE_LOW, 0x07),
 813         QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_IDAC_TSETTLE_HIGH, 0x00),
 814         QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x47),
 815         QMP_PHY_INIT_CFG(QSERDES_V6_RX_SIGDET_CNTRL, 0x04),
 816         QMP_PHY_INIT_CFG(QSERDES_V6_RX_SIGDET_DEGLITCH_CNTRL, 0x0e),
 817         QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_MODE_01_LOW, 0xdc),
 818         QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_MODE_01_HIGH, 0x5c),
 819         QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_MODE_01_HIGH2, 0x9c),
 820         QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_MODE_01_HIGH3, 0x1d),
 821         QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_MODE_01_HIGH4, 0x09),
 822         QMP_PHY_INIT_CFG(QSERDES_V6_RX_DFE_EN_TIMER, 0x04),
 823         QMP_PHY_INIT_CFG(QSERDES_V6_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),
 824         QMP_PHY_INIT_CFG(QSERDES_V6_RX_DCC_CTRL1, 0x0c),
 825         QMP_PHY_INIT_CFG(QSERDES_V6_RX_VTH_CODE, 0x10),
 826         QMP_PHY_INIT_CFG(QSERDES_V6_RX_SIGDET_CAL_CTRL1, 0x14),
 827         QMP_PHY_INIT_CFG(QSERDES_V6_RX_SIGDET_CAL_TRIM, 0x08),
 828
 829         QMP_PHY_INIT_CFG_LANE(QSERDES_V6_RX_RX_MODE_00_LOW, 0x3f, 1),
 830         QMP_PHY_INIT_CFG_LANE(QSERDES_V6_RX_RX_MODE_00_HIGH, 0xbf, 1),
 831         QMP_PHY_INIT_CFG_LANE(QSERDES_V6_RX_RX_MODE_00_HIGH2, 0xff, 1),
 832         QMP_PHY_INIT_CFG_LANE(QSERDES_V6_RX_RX_MODE_00_HIGH3, 0xdf, 1),
 833         QMP_PHY_INIT_CFG_LANE(QSERDES_V6_RX_RX_MODE_00_HIGH4, 0xed, 1),
 834
 835         QMP_PHY_INIT_CFG_LANE(QSERDES_V6_RX_RX_MODE_00_LOW, 0xbf, 2),
 836         QMP_PHY_INIT_CFG_LANE(QSERDES_V6_RX_RX_MODE_00_HIGH, 0xbf, 2),
 837         QMP_PHY_INIT_CFG_LANE(QSERDES_V6_RX_RX_MODE_00_HIGH2, 0xbf, 2),
 838         QMP_PHY_INIT_CFG_LANE(QSERDES_V6_RX_RX_MODE_00_HIGH3, 0xdf, 2),
 839         QMP_PHY_INIT_CFG_LANE(QSERDES_V6_RX_RX_MODE_00_HIGH4, 0xfd, 2),
 840 };
 841
 842 static const struct qmp_phy_init_tbl sm8550_usb3_pcs_tbl[] = {
 843         QMP_PHY_INIT_CFG(QPHY_V6_PCS_LOCK_DETECT_CONFIG1, 0xc4),
 844         QMP_PHY_INIT_CFG(QPHY_V6_PCS_LOCK_DETECT_CONFIG2, 0x89),
 845         QMP_PHY_INIT_CFG(QPHY_V6_PCS_LOCK_DETECT_CONFIG3, 0x20),
 846         QMP_PHY_INIT_CFG(QPHY_V6_PCS_LOCK_DETECT_CONFIG6, 0x13),
 847         QMP_PHY_INIT_CFG(QPHY_V6_PCS_REFGEN_REQ_CONFIG1, 0x21),
 848         QMP_PHY_INIT_CFG(QPHY_V6_PCS_RX_SIGDET_LVL, 0x99),
 849         QMP_PHY_INIT_CFG(QPHY_V6_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7),
 850         QMP_PHY_INIT_CFG(QPHY_V6_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03),
 851         QMP_PHY_INIT_CFG(QPHY_V6_PCS_CDR_RESET_TIME, 0x0a),
 852         QMP_PHY_INIT_CFG(QPHY_V6_PCS_ALIGN_DETECT_CONFIG1, 0x88),
 853         QMP_PHY_INIT_CFG(QPHY_V6_PCS_ALIGN_DETECT_CONFIG2, 0x13),
 854         QMP_PHY_INIT_CFG(QPHY_V6_PCS_PCS_TX_RX_CONFIG, 0x0c),
 855         QMP_PHY_INIT_CFG(QPHY_V6_PCS_EQ_CONFIG1, 0x4b),
 856         QMP_PHY_INIT_CFG(QPHY_V6_PCS_EQ_CONFIG5, 0x10),
 857 };
 858
 859 static const struct qmp_phy_init_tbl sm8550_usb3_pcs_usb_tbl[] = {
 860         QMP_PHY_INIT_CFG(QPHY_V6_PCS_USB3_LFPS_DET_HIGH_COUNT_VAL, 0xf8),
 861         QMP_PHY_INIT_CFG(QPHY_V6_PCS_USB3_RXEQTRAINING_DFE_TIME_S2, 0x07),
 862         QMP_PHY_INIT_CFG(QPHY_V6_PCS_USB3_RCVR_DTCT_DLY_U3_L, 0x40),
 863         QMP_PHY_INIT_CFG(QPHY_V6_PCS_USB3_RCVR_DTCT_DLY_U3_H, 0x00),
 864         QMP_PHY_INIT_CFG(QPHY_V6_PCS_USB3_POWER_STATE_CONFIG1, 0x68),
 865 };
 866
 867 static const struct qmp_phy_init_tbl qmp_v4_dp_serdes_tbl[] = {
 868         QMP_PHY_INIT_CFG(QSERDES_V4_COM_SVS_MODE_CLK_SEL, 0x05),
 869         QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_EN_SEL, 0x3b),
 870         QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYS_CLK_CTRL, 0x02),
 871         QMP_PHY_INIT_CFG(QSERDES_V4_COM_CLK_ENABLE1, 0x0c),
 872         QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_BUF_ENABLE, 0x06),
 873         QMP_PHY_INIT_CFG(QSERDES_V4_COM_CLK_SELECT, 0x30),
 874         QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_IVCO, 0x0f),
 875         QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE0, 0x36),
 876         QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE0, 0x16),
 877         QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE0, 0x06),
 878         QMP_PHY_INIT_CFG(QSERDES_V4_COM_CMN_CONFIG, 0x02),
 879         QMP_PHY_INIT_CFG(QSERDES_V4_COM_INTEGLOOP_GAIN0_MODE0, 0x3f),
 880         QMP_PHY_INIT_CFG(QSERDES_V4_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
 881         QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_MAP, 0x00),
 882         QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE0, 0x00),
 883         QMP_PHY_INIT_CFG(QSERDES_V4_COM_BG_TIMER, 0x0a),
 884         QMP_PHY_INIT_CFG(QSERDES_V4_COM_CORECLK_DIV_MODE0, 0x0a),
 885         QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_CTRL, 0x00),
 886         QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIAS_EN_CLKBUFLR_EN, 0x17),
 887         QMP_PHY_INIT_CFG(QSERDES_V4_COM_CORE_CLK_EN, 0x1f),
 888 };
 889
 890 static const struct qmp_phy_init_tbl qmp_v4_dp_serdes_tbl_rbr[] = {
 891         QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x05),
 892         QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x69),
 893         QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE0, 0x80),
 894         QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x07),
 895         QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x6f),
 896         QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x08),
 897         QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x04),
 898 };
 899
 900 static const struct qmp_phy_init_tbl qmp_v4_dp_serdes_tbl_hbr[] = {
 901         QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x03),
 902         QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x69),
 903         QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE0, 0x80),
 904         QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x07),
 905         QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x0f),
 906         QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x0e),
 907         QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x08),
 908 };
 909
 910 static const struct qmp_phy_init_tbl qmp_v4_dp_serdes_tbl_hbr2[] = {
 911         QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x01),
 912         QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x8c),
 913         QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE0, 0x00),
 914         QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x0a),
 915         QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x1f),
 916         QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x1c),
 917         QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x08),
 918 };
 919
 920 static const struct qmp_phy_init_tbl qmp_v4_dp_serdes_tbl_hbr3[] = {
 921         QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x00),
 922         QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x69),
 923         QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE0, 0x80),
 924         QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x07),
 925         QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x2f),
 926         QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x2a),
 927         QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x08),
 928 };
 929
 930 static const struct qmp_phy_init_tbl qmp_v4_dp_tx_tbl[] = {
 931         QMP_PHY_INIT_CFG(QSERDES_V4_TX_VMODE_CTRL1, 0x40),
 932         QMP_PHY_INIT_CFG(QSERDES_V4_TX_PRE_STALL_LDO_BOOST_EN, 0x30),
 933         QMP_PHY_INIT_CFG(QSERDES_V4_TX_INTERFACE_SELECT, 0x3b),
 934         QMP_PHY_INIT_CFG(QSERDES_V4_TX_CLKBUF_ENABLE, 0x0f),
 935         QMP_PHY_INIT_CFG(QSERDES_V4_TX_RESET_TSYNC_EN, 0x03),
 936         QMP_PHY_INIT_CFG(QSERDES_V4_TX_TRAN_DRVR_EMP_EN, 0x0f),
 937         QMP_PHY_INIT_CFG(QSERDES_V4_TX_PARRATE_REC_DETECT_IDLE_EN, 0x00),
 938         QMP_PHY_INIT_CFG(QSERDES_V4_TX_TX_INTERFACE_MODE, 0x00),
 939         QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_TX, 0x11),
 940         QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_RX, 0x11),
 941         QMP_PHY_INIT_CFG(QSERDES_V4_TX_TX_BAND, 0x4),
 942         QMP_PHY_INIT_CFG(QSERDES_V4_TX_TX_POL_INV, 0x0a),
 943         QMP_PHY_INIT_CFG(QSERDES_V4_TX_TX_DRV_LVL, 0x2a),
 944         QMP_PHY_INIT_CFG(QSERDES_V4_TX_TX_EMP_POST1_LVL, 0x20),
 945 };
 946
 947 static const struct qmp_phy_init_tbl qmp_v5_dp_serdes_tbl[] = {
 948         QMP_PHY_INIT_CFG(QSERDES_V4_COM_SVS_MODE_CLK_SEL, 0x05),
 949         QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_EN_SEL, 0x3b),
 950         QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYS_CLK_CTRL, 0x02),
 951         QMP_PHY_INIT_CFG(QSERDES_V4_COM_CLK_ENABLE1, 0x0c),
 952         QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_BUF_ENABLE, 0x06),
 953         QMP_PHY_INIT_CFG(QSERDES_V4_COM_CLK_SELECT, 0x30),
 954         QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_IVCO, 0x0f),
 955         QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE0, 0x36),
 956         QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE1, 0x36),
 957         QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE0, 0x16),
 958         QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE1, 0x16),
 959         QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE0, 0x06),
 960         QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE1, 0x06),
 961         QMP_PHY_INIT_CFG(QSERDES_V4_COM_CMN_CONFIG, 0x02),
 962         QMP_PHY_INIT_CFG(QSERDES_V4_COM_INTEGLOOP_GAIN0_MODE0, 0x3f),
 963         QMP_PHY_INIT_CFG(QSERDES_V4_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
 964         QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_MAP, 0x02),
 965         QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE0, 0x00),
 966         QMP_PHY_INIT_CFG(QSERDES_V4_COM_BG_TIMER, 0x0a),
 967         QMP_PHY_INIT_CFG(QSERDES_V4_COM_CORECLK_DIV_MODE0, 0x0a),
 968         QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_CTRL, 0x00),
 969         QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIAS_EN_CLKBUFLR_EN, 0x17),
 970         QMP_PHY_INIT_CFG(QSERDES_V4_COM_CORE_CLK_EN, 0x1f),
 971 };
 972
 973 static const struct qmp_phy_init_tbl qmp_v5_dp_tx_tbl[] = {
 974         QMP_PHY_INIT_CFG(QSERDES_V5_TX_VMODE_CTRL1, 0x40),
 975         QMP_PHY_INIT_CFG(QSERDES_V5_TX_PRE_STALL_LDO_BOOST_EN, 0x30),
 976         QMP_PHY_INIT_CFG(QSERDES_V5_TX_INTERFACE_SELECT, 0x3b),
 977         QMP_PHY_INIT_CFG(QSERDES_V5_TX_CLKBUF_ENABLE, 0x0f),
 978         QMP_PHY_INIT_CFG(QSERDES_V5_TX_RESET_TSYNC_EN, 0x03),
 979         QMP_PHY_INIT_CFG(QSERDES_V5_TX_TRAN_DRVR_EMP_EN, 0x0f),
 980         QMP_PHY_INIT_CFG(QSERDES_V5_TX_PARRATE_REC_DETECT_IDLE_EN, 0x00),
 981         QMP_PHY_INIT_CFG(QSERDES_V5_TX_TX_INTERFACE_MODE, 0x00),
 982         QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_TX, 0x11),
 983         QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_RX, 0x11),
 984         QMP_PHY_INIT_CFG(QSERDES_V5_TX_TX_BAND, 0x04),
 985 };
 986
 987 static const struct qmp_phy_init_tbl qmp_v5_5nm_dp_tx_tbl[] = {
 988         QMP_PHY_INIT_CFG(QSERDES_V5_5NM_TX_LANE_MODE_3, 0x51),
 989         QMP_PHY_INIT_CFG(QSERDES_V5_5NM_TX_TRANSCEIVER_BIAS_EN, 0x1a),
 990         QMP_PHY_INIT_CFG(QSERDES_V5_5NM_TX_VMODE_CTRL1, 0x40),
 991         QMP_PHY_INIT_CFG(QSERDES_V5_5NM_TX_PRE_STALL_LDO_BOOST_EN, 0x0),
 992         QMP_PHY_INIT_CFG(QSERDES_V5_5NM_TX_INTERFACE_SELECT, 0xff),
 993         QMP_PHY_INIT_CFG(QSERDES_V5_5NM_TX_CLKBUF_ENABLE, 0x0f),
 994         QMP_PHY_INIT_CFG(QSERDES_V5_5NM_TX_RESET_TSYNC_EN, 0x03),
 995         QMP_PHY_INIT_CFG(QSERDES_V5_5NM_TX_TRAN_DRVR_EMP_EN, 0xf),
 996         QMP_PHY_INIT_CFG(QSERDES_V5_5NM_TX_PARRATE_REC_DETECT_IDLE_EN, 0x00),
 997         QMP_PHY_INIT_CFG(QSERDES_V5_5NM_TX_RES_CODE_LANE_OFFSET_TX, 0x11),
 998         QMP_PHY_INIT_CFG(QSERDES_V5_5NM_TX_RES_CODE_LANE_OFFSET_RX, 0x11),
 999         QMP_PHY_INIT_CFG(QSERDES_V5_5NM_TX_TX_BAND, 0x01),
1000 };
1001
1002 static const struct qmp_phy_init_tbl qmp_v6_dp_serdes_tbl[] = {
1003         QMP_PHY_INIT_CFG(QSERDES_V6_COM_SVS_MODE_CLK_SEL, 0x15),
1004         QMP_PHY_INIT_CFG(QSERDES_V6_COM_SYSCLK_EN_SEL, 0x3b),
1005         QMP_PHY_INIT_CFG(QSERDES_V6_COM_SYS_CLK_CTRL, 0x02),
1006         QMP_PHY_INIT_CFG(QSERDES_V6_COM_CLK_ENABLE1, 0x0c),
1007         QMP_PHY_INIT_CFG(QSERDES_V6_COM_SYSCLK_BUF_ENABLE, 0x06),
1008         QMP_PHY_INIT_CFG(QSERDES_V6_COM_CLK_SELECT, 0x30),
1009         QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_IVCO, 0x0f),
1010         QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CCTRL_MODE0, 0x36),
1011         QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_RCTRL_MODE0, 0x16),
1012         QMP_PHY_INIT_CFG(QSERDES_V6_COM_CP_CTRL_MODE0, 0x06),
1013         QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START1_MODE0, 0x00),
1014         QMP_PHY_INIT_CFG(QSERDES_V6_COM_CMN_CONFIG_1, 0x12),
1015         QMP_PHY_INIT_CFG(QSERDES_V6_COM_INTEGLOOP_GAIN0_MODE0, 0x3f),
1016         QMP_PHY_INIT_CFG(QSERDES_V6_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
1017         QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE_MAP, 0x00),
1018         QMP_PHY_INIT_CFG(QSERDES_V6_COM_BG_TIMER, 0x0a),
1019         QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CORE_CLK_DIV_MODE0, 0x14),
1020         QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE_CTRL, 0x00),
1021         QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_BIAS_EN_CLK_BUFLR_EN, 0x17),
1022         QMP_PHY_INIT_CFG(QSERDES_V6_COM_CORE_CLK_EN, 0x0f),
1023 };
1024
1025 static const struct qmp_phy_init_tbl qmp_v6_n4_dp_serdes_tbl[] = {
1026         QMP_PHY_INIT_CFG(QSERDES_V6_COM_SVS_MODE_CLK_SEL, 0x15),
1027         QMP_PHY_INIT_CFG(QSERDES_V6_COM_SYSCLK_EN_SEL, 0x3b),
1028         QMP_PHY_INIT_CFG(QSERDES_V6_COM_SYS_CLK_CTRL, 0x02),
1029         QMP_PHY_INIT_CFG(QSERDES_V6_COM_CLK_ENABLE1, 0x0c),
1030         QMP_PHY_INIT_CFG(QSERDES_V6_COM_SYSCLK_BUF_ENABLE, 0x06),
1031         QMP_PHY_INIT_CFG(QSERDES_V6_COM_CLK_SELECT, 0x30),
1032         QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_IVCO, 0x07),
1033         QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CCTRL_MODE0, 0x36),
1034         QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_RCTRL_MODE0, 0x16),
1035         QMP_PHY_INIT_CFG(QSERDES_V6_COM_CP_CTRL_MODE0, 0x06),
1036         QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE0, 0x34),
1037         QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START1_MODE0, 0x00),
1038         QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START2_MODE0, 0xc0),
1039         QMP_PHY_INIT_CFG(QSERDES_V6_COM_CMN_CONFIG_1, 0x12),
1040         QMP_PHY_INIT_CFG(QSERDES_V6_COM_INTEGLOOP_GAIN0_MODE0, 0x3f),
1041         QMP_PHY_INIT_CFG(QSERDES_V6_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
1042         QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE_MAP, 0x00),
1043         QMP_PHY_INIT_CFG(QSERDES_V6_COM_BG_TIMER, 0x0a),
1044         QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CORE_CLK_DIV_MODE0, 0x14),
1045         QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE_CTRL, 0x00),
1046         QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_BIAS_EN_CLK_BUFLR_EN, 0x17),
1047         QMP_PHY_INIT_CFG(QSERDES_V6_COM_CORE_CLK_EN, 0x0f),
1048 };
1049
1050 static const struct qmp_phy_init_tbl qmp_v6_dp_tx_tbl[] = {
1051         QMP_PHY_INIT_CFG(QSERDES_V6_TX_VMODE_CTRL1, 0x40),
1052         QMP_PHY_INIT_CFG(QSERDES_V6_TX_PRE_STALL_LDO_BOOST_EN, 0x30),
1053         QMP_PHY_INIT_CFG(QSERDES_V6_TX_INTERFACE_SELECT, 0x3b),
1054         QMP_PHY_INIT_CFG(QSERDES_V6_TX_CLKBUF_ENABLE, 0x0f),
1055         QMP_PHY_INIT_CFG(QSERDES_V6_TX_RESET_TSYNC_EN, 0x03),
1056         QMP_PHY_INIT_CFG(QSERDES_V6_TX_TRAN_DRVR_EMP_EN, 0x0f),
1057         QMP_PHY_INIT_CFG(QSERDES_V6_TX_PARRATE_REC_DETECT_IDLE_EN, 0x00),
1058         QMP_PHY_INIT_CFG(QSERDES_V6_TX_TX_INTERFACE_MODE, 0x00),
1059         QMP_PHY_INIT_CFG(QSERDES_V6_TX_RES_CODE_LANE_OFFSET_TX, 0x0c),
1060         QMP_PHY_INIT_CFG(QSERDES_V6_TX_RES_CODE_LANE_OFFSET_RX, 0x0c),
1061         QMP_PHY_INIT_CFG(QSERDES_V6_TX_TX_BAND, 0x4),
1062 };
1063
1064 static const struct qmp_phy_init_tbl qmp_v6_n4_dp_tx_tbl[] = {
1065         QMP_PHY_INIT_CFG(QSERDES_V6_N4_TX_VMODE_CTRL1, 0x40),
1066         QMP_PHY_INIT_CFG(QSERDES_V6_N4_TX_PRE_STALL_LDO_BOOST_EN, 0x00),
1067         QMP_PHY_INIT_CFG(QSERDES_V6_N4_TX_INTERFACE_SELECT, 0xff),
1068         QMP_PHY_INIT_CFG(QSERDES_V6_N4_TX_CLKBUF_ENABLE, 0x0f),
1069         QMP_PHY_INIT_CFG(QSERDES_V6_N4_TX_RESET_TSYNC_EN, 0x03),
1070         QMP_PHY_INIT_CFG(QSERDES_V6_N4_TX_TRAN_DRVR_EMP_EN, 0x0f),
1071         QMP_PHY_INIT_CFG(QSERDES_V6_N4_TX_PARRATE_REC_DETECT_IDLE_EN, 0x00),
1072         QMP_PHY_INIT_CFG(QSERDES_V6_N4_TX_RES_CODE_LANE_OFFSET_TX, 0x11),
1073         QMP_PHY_INIT_CFG(QSERDES_V6_N4_TX_RES_CODE_LANE_OFFSET_RX, 0x11),
1074         QMP_PHY_INIT_CFG(QSERDES_V6_N4_TX_TX_BAND, 0x1),
1075 };
1076
1077 static const struct qmp_phy_init_tbl qmp_v6_dp_serdes_tbl_rbr[] = {
1078         QMP_PHY_INIT_CFG(QSERDES_V6_COM_HSCLK_SEL_1, 0x05),
1079         QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE0, 0x34),
1080         QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START2_MODE0, 0xc0),
1081         QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START3_MODE0, 0x0b),
1082         QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP1_MODE0, 0x37),
1083         QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP2_MODE0, 0x04),
1084         QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP_EN, 0x04),
1085         QMP_PHY_INIT_CFG(QSERDES_V6_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0x71),
1086         QMP_PHY_INIT_CFG(QSERDES_V6_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x0c),
1087 };
1088
1089 static const struct qmp_phy_init_tbl qmp_v6_dp_serdes_tbl_hbr[] = {
1090         QMP_PHY_INIT_CFG(QSERDES_V6_COM_HSCLK_SEL_1, 0x03),
1091         QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE0, 0x34),
1092         QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START2_MODE0, 0xc0),
1093         QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START3_MODE0, 0x0b),
1094         QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP1_MODE0, 0x07),
1095         QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP2_MODE0, 0x07),
1096         QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP_EN, 0x08),
1097         QMP_PHY_INIT_CFG(QSERDES_V6_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0x71),
1098         QMP_PHY_INIT_CFG(QSERDES_V6_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x0c),
1099 };
1100
1101 static const struct qmp_phy_init_tbl qmp_v6_dp_serdes_tbl_hbr2[] = {
1102         QMP_PHY_INIT_CFG(QSERDES_V6_COM_HSCLK_SEL_1, 0x01),
1103         QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE0, 0x46),
1104         QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START2_MODE0, 0x00),
1105         QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START3_MODE0, 0x05),
1106         QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP1_MODE0, 0x0f),
1107         QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP2_MODE0, 0x0e),
1108         QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP_EN, 0x08),
1109         QMP_PHY_INIT_CFG(QSERDES_V6_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0x97),
1110         QMP_PHY_INIT_CFG(QSERDES_V6_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x10),
1111 };
1112
1113 static const struct qmp_phy_init_tbl qmp_v6_dp_serdes_tbl_hbr3[] = {
1114         QMP_PHY_INIT_CFG(QSERDES_V6_COM_HSCLK_SEL_1, 0x00),
1115         QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE0, 0x34),
1116         QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START2_MODE0, 0xc0),
1117         QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START3_MODE0, 0x0b),
1118         QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP1_MODE0, 0x17),
1119         QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP2_MODE0, 0x15),
1120         QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP_EN, 0x08),
1121         QMP_PHY_INIT_CFG(QSERDES_V6_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0x71),
1122         QMP_PHY_INIT_CFG(QSERDES_V6_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x0c),
1123 };
1124
1125 static const struct qmp_phy_init_tbl qmp_v6_n4_dp_serdes_tbl_rbr[] = {
1126         QMP_PHY_INIT_CFG(QSERDES_V6_COM_HSCLK_SEL_1, 0x05),
1127         QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE0, 0x34),
1128         QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP_EN, 0x04),
1129         QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START3_MODE0, 0x0b),
1130         QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP1_MODE0, 0x37),
1131         QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP2_MODE0, 0x04),
1132         QMP_PHY_INIT_CFG(QSERDES_V6_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0x71),
1133         QMP_PHY_INIT_CFG(QSERDES_V6_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x0c),
1134         QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_EN_CENTER, 0x01),
1135         QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_ADJ_PER1, 0x00),
1136         QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_PER1, 0x6b),
1137         QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_PER2, 0x02),
1138         QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_STEP_SIZE1_MODE0, 0x92),
1139         QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_STEP_SIZE2_MODE0, 0x01),
1140 };
1141
1142 static const struct qmp_phy_init_tbl qmp_v6_n4_dp_serdes_tbl_hbr[] = {
1143         QMP_PHY_INIT_CFG(QSERDES_V6_COM_HSCLK_SEL_1, 0x03),
1144         QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE0, 0x34),
1145         QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP_EN, 0x08),
1146         QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START3_MODE0, 0x0b),
1147         QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP1_MODE0, 0x07),
1148         QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP2_MODE0, 0x07),
1149         QMP_PHY_INIT_CFG(QSERDES_V6_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0x71),
1150         QMP_PHY_INIT_CFG(QSERDES_V6_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x0c),
1151         QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_EN_CENTER, 0x01),
1152         QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_ADJ_PER1, 0x00),
1153         QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_PER1, 0x6b),
1154         QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_PER2, 0x02),
1155         QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_STEP_SIZE1_MODE0, 0x92),
1156         QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_STEP_SIZE2_MODE0, 0x01),
1157 };
1158
1159 static const struct qmp_phy_init_tbl qmp_v6_n4_dp_serdes_tbl_hbr2[] = {
1160         QMP_PHY_INIT_CFG(QSERDES_V6_COM_HSCLK_SEL_1, 0x01),
1161         QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE0, 0x46),
1162         QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP_EN, 0x08),
1163         QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START3_MODE0, 0x05),
1164         QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP1_MODE0, 0x0f),
1165         QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP2_MODE0, 0x0e),
1166         QMP_PHY_INIT_CFG(QSERDES_V6_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0x97),
1167         QMP_PHY_INIT_CFG(QSERDES_V6_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x10),
1168         QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_EN_CENTER, 0x01),
1169         QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_ADJ_PER1, 0x00),
1170         QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_PER1, 0x6b),
1171         QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_PER2, 0x02),
1172         QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_STEP_SIZE1_MODE0, 0x18),
1173         QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_STEP_SIZE2_MODE0, 0x02),
1174 };
1175
1176 static const struct qmp_phy_init_tbl qmp_v6_n4_dp_serdes_tbl_hbr3[] = {
1177         QMP_PHY_INIT_CFG(QSERDES_V6_COM_HSCLK_SEL_1, 0x00),
1178         QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE0, 0x34),
1179         QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP_EN, 0x08),
1180         QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START3_MODE0, 0x0b),
1181         QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP1_MODE0, 0x17),
1182         QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP2_MODE0, 0x15),
1183         QMP_PHY_INIT_CFG(QSERDES_V6_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0x71),
1184         QMP_PHY_INIT_CFG(QSERDES_V6_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x0c),
1185         QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_EN_CENTER, 0x01),
1186         QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_ADJ_PER1, 0x00),
1187         QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_PER1, 0x6b),
1188         QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_PER2, 0x02),
1189         QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_STEP_SIZE1_MODE0, 0x92),
1190         QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_STEP_SIZE2_MODE0, 0x01),
1191 };
1192
1193 static const struct qmp_phy_init_tbl sc8280xp_usb43dp_serdes_tbl[] = {
1194         QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_EN_CENTER, 0x01),
1195         QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_PER1, 0x31),
1196         QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_PER2, 0x01),
1197         QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE1_MODE0, 0xfd),
1198         QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE2_MODE0, 0x0d),
1199         QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE1_MODE1, 0xfd),
1200         QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE2_MODE1, 0x0d),
1201         QMP_PHY_INIT_CFG(QSERDES_V5_COM_SYSCLK_BUF_ENABLE, 0x0a),
1202         QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE0, 0x02),
1203         QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE1, 0x02),
1204         QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE0, 0x16),
1205         QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE1, 0x16),
1206         QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE0, 0x36),
1207         QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE1, 0x36),
1208         QMP_PHY_INIT_CFG(QSERDES_V5_COM_SYSCLK_EN_SEL, 0x1a),
1209         QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP_EN, 0x04),
1210         QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE0, 0x14),
1211         QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE0, 0x34),
1212         QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE1, 0x34),
1213         QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE1, 0x82),
1214         QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE0, 0x04),
1215         QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MSB_MODE0, 0x01),
1216         QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE1, 0x04),
1217         QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MSB_MODE1, 0x01),
1218         QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START1_MODE0, 0x55),
1219         QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START2_MODE0, 0xd5),
1220         QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START3_MODE0, 0x05),
1221         QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START1_MODE1, 0x55),
1222         QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START2_MODE1, 0xd5),
1223         QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START3_MODE1, 0x05),
1224         QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE_MAP, 0x02),
1225         QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE1_MODE0, 0xd4),
1226         QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE2_MODE0, 0x00),
1227         QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE1_MODE1, 0xd4),
1228         QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE2_MODE1, 0x00),
1229         QMP_PHY_INIT_CFG(QSERDES_V5_COM_HSCLK_SEL, 0x13),
1230         QMP_PHY_INIT_CFG(QSERDES_V5_COM_HSCLK_HS_SWITCH_SEL, 0x00),
1231         QMP_PHY_INIT_CFG(QSERDES_V5_COM_CORECLK_DIV_MODE0, 0x0a),
1232         QMP_PHY_INIT_CFG(QSERDES_V5_COM_CORECLK_DIV_MODE1, 0x04),
1233         QMP_PHY_INIT_CFG(QSERDES_V5_COM_CORE_CLK_EN, 0x60),
1234         QMP_PHY_INIT_CFG(QSERDES_V5_COM_CMN_CONFIG, 0x76),
1235         QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_IVCO, 0xff),
1236         QMP_PHY_INIT_CFG(QSERDES_V5_COM_INTEGLOOP_GAIN0_MODE0, 0x20),
1237         QMP_PHY_INIT_CFG(QSERDES_V5_COM_INTEGLOOP_GAIN0_MODE1, 0x20),
1238         QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE_INITVAL2, 0x00),
1239         QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE_MAXVAL2, 0x01),
1240         QMP_PHY_INIT_CFG(QSERDES_V5_COM_SVS_MODE_CLK_SEL, 0x0a),
1241 };
1242
1243 static const struct qmp_phy_init_tbl sc8280xp_usb43dp_tx_tbl[] = {
1244         QMP_PHY_INIT_CFG(QSERDES_V5_5NM_TX_LANE_MODE_1, 0x05),
1245         QMP_PHY_INIT_CFG(QSERDES_V5_5NM_TX_LANE_MODE_2, 0xc2),
1246         QMP_PHY_INIT_CFG(QSERDES_V5_5NM_TX_LANE_MODE_3, 0x10),
1247         QMP_PHY_INIT_CFG(QSERDES_V5_5NM_TX_RES_CODE_LANE_OFFSET_TX, 0x1f),
1248         QMP_PHY_INIT_CFG(QSERDES_V5_5NM_TX_RES_CODE_LANE_OFFSET_RX, 0x0a),
1249 };
1250
1251 static const struct qmp_phy_init_tbl sc8280xp_usb43dp_rx_tbl[] = {
1252         QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_SIGDET_CNTRL, 0x04),
1253         QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_SIGDET_DEGLITCH_CNTRL, 0x0e),
1254         QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_SIGDET_ENABLES, 0x00),
1255         QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_RX_MODE_RATE_0_1_B0, 0xd2),
1256         QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_RX_MODE_RATE_0_1_B1, 0xd2),
1257         QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_RX_MODE_RATE_0_1_B2, 0xdb),
1258         QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_RX_MODE_RATE_0_1_B3, 0x21),
1259         QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_RX_MODE_RATE_0_1_B4, 0x3f),
1260         QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_RX_MODE_RATE_0_1_B5, 0x80),
1261         QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_RX_MODE_RATE_0_1_B6, 0x45),
1262         QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_RX_MODE_RATE_0_1_B7, 0x00),
1263         QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_RX_MODE_RATE2_B0, 0x6b),
1264         QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_RX_MODE_RATE2_B1, 0x63),
1265         QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_RX_MODE_RATE2_B2, 0xb6),
1266         QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_RX_MODE_RATE2_B3, 0x23),
1267         QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_RX_MODE_RATE2_B4, 0x35),
1268         QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_RX_MODE_RATE2_B5, 0x30),
1269         QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_RX_MODE_RATE2_B6, 0x8e),
1270         QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_RX_MODE_RATE2_B7, 0x00),
1271         QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_RX_IVCM_CAL_CODE_OVERRIDE, 0x00),
1272         QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_RX_IVCM_CAL_CTRL2, 0x80),
1273         QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_RX_SUMMER_CAL_SPD_MODE, 0x1b),
1274         QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),
1275         QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_UCDR_PI_CONTROLS, 0x15),
1276         QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_UCDR_SB2_GAIN2_RATE2, 0x0a),
1277         QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_RX_IVCM_POSTCAL_OFFSET, 0x7c),
1278         QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_VGA_CAL_CNTRL1, 0x00),
1279         QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_VGA_CAL_MAN_VAL, 0x0d),
1280         QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_DFE_DAC_ENABLE1, 0x00),
1281         QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_DFE_3, 0x45),
1282         QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_GM_CAL, 0x09),
1283         QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_UCDR_FO_GAIN_RATE2, 0x09),
1284         QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_UCDR_SO_GAIN_RATE2, 0x05),
1285         QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_Q_PI_INTRINSIC_BIAS_RATE32, 0x3f),
1286 };
1287
1288 static const struct qmp_phy_init_tbl sc8280xp_usb43dp_pcs_tbl[] = {
1289         QMP_PHY_INIT_CFG(QPHY_V5_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7),
1290         QMP_PHY_INIT_CFG(QPHY_V5_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03),
1291         QMP_PHY_INIT_CFG(QPHY_V5_PCS_LOCK_DETECT_CONFIG1, 0xd0),
1292         QMP_PHY_INIT_CFG(QPHY_V5_PCS_LOCK_DETECT_CONFIG2, 0x07),
1293         QMP_PHY_INIT_CFG(QPHY_V5_PCS_LOCK_DETECT_CONFIG3, 0x20),
1294         QMP_PHY_INIT_CFG(QPHY_V5_PCS_LOCK_DETECT_CONFIG6, 0x13),
1295         QMP_PHY_INIT_CFG(QPHY_V5_PCS_REFGEN_REQ_CONFIG1, 0x21),
1296         QMP_PHY_INIT_CFG(QPHY_V5_PCS_RX_SIGDET_LVL, 0xaa),
1297         QMP_PHY_INIT_CFG(QPHY_V5_PCS_RX_CONFIG, 0x0a),
1298         QMP_PHY_INIT_CFG(QPHY_V5_PCS_ALIGN_DETECT_CONFIG1, 0x88),
1299         QMP_PHY_INIT_CFG(QPHY_V5_PCS_ALIGN_DETECT_CONFIG2, 0x13),
1300         QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCS_TX_RX_CONFIG, 0x0c),
1301         QMP_PHY_INIT_CFG(QPHY_V5_PCS_EQ_CONFIG1, 0x4b),
1302         QMP_PHY_INIT_CFG(QPHY_V5_PCS_EQ_CONFIG5, 0x10),
1303         QMP_PHY_INIT_CFG(QPHY_V5_PCS_USB3_LFPS_DET_HIGH_COUNT_VAL, 0xf8),
1304         QMP_PHY_INIT_CFG(QPHY_V5_PCS_USB3_RXEQTRAINING_DFE_TIME_S2, 0x07),
1305 };
1306
1307 static const struct qmp_phy_init_tbl x1e80100_usb43dp_serdes_tbl[] = {
1308         QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_EN_CENTER, 0x01),
1309         QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_PER1, 0x62),
1310         QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_PER2, 0x02),
1311         QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_STEP_SIZE1_MODE0, 0xc2),
1312         QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_STEP_SIZE2_MODE0, 0x03),
1313         QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_STEP_SIZE1_MODE1, 0xc2),
1314         QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_STEP_SIZE2_MODE1, 0x03),
1315         QMP_PHY_INIT_CFG(QSERDES_V6_COM_SYSCLK_BUF_ENABLE, 0x0a),
1316         QMP_PHY_INIT_CFG(QSERDES_V6_COM_CP_CTRL_MODE0, 0x02),
1317         QMP_PHY_INIT_CFG(QSERDES_V6_COM_CP_CTRL_MODE1, 0x02),
1318         QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_RCTRL_MODE0, 0x16),
1319         QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_RCTRL_MODE1, 0x16),
1320         QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CCTRL_MODE0, 0x36),
1321         QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CCTRL_MODE1, 0x36),
1322         QMP_PHY_INIT_CFG(QSERDES_V6_COM_SYSCLK_EN_SEL, 0x1a),
1323         QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP_EN, 0x04),
1324         QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP_CFG, 0x04),
1325         QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP1_MODE0, 0x08),
1326         QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP2_MODE0, 0x1a),
1327         QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP1_MODE1, 0x16),
1328         QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP2_MODE1, 0x41),
1329         QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE0, 0x82),
1330         QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MSB_MODE0, 0x00),
1331         QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE1, 0x82),
1332         QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MSB_MODE1, 0x00),
1333         QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START1_MODE0, 0x55),
1334         QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START2_MODE0, 0x55),
1335         QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START3_MODE0, 0x03),
1336         QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START1_MODE1, 0x55),
1337         QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START2_MODE1, 0x55),
1338         QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START3_MODE1, 0x03),
1339         QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE_MAP, 0x14),
1340         QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE1_MODE0, 0xba),
1341         QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE2_MODE0, 0x00),
1342         QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE1_MODE1, 0xba),
1343         QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE2_MODE1, 0x00),
1344         QMP_PHY_INIT_CFG(QSERDES_V6_COM_HSCLK_SEL_1, 0x13),
1345         QMP_PHY_INIT_CFG(QSERDES_V6_COM_HSCLK_HS_SWITCH_SEL_1, 0x00),
1346         QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CORE_CLK_DIV_MODE0, 0x0a),
1347         QMP_PHY_INIT_CFG(QSERDES_V6_COM_CORECLK_DIV_MODE1, 0x04),
1348         QMP_PHY_INIT_CFG(QSERDES_V6_COM_CORE_CLK_EN, 0xa0),
1349         QMP_PHY_INIT_CFG(QSERDES_V6_COM_CMN_CONFIG_1, 0x76),
1350         QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_IVCO, 0x0f),
1351         QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_IVCO_MODE1, 0x0f),
1352         QMP_PHY_INIT_CFG(QSERDES_V6_COM_INTEGLOOP_GAIN0_MODE0, 0x20),
1353         QMP_PHY_INIT_CFG(QSERDES_V6_COM_INTEGLOOP_GAIN0_MODE1, 0x20),
1354         QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE_INITVAL2, 0x00),
1355         QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE_MAXVAL2, 0x01),
1356         QMP_PHY_INIT_CFG(QSERDES_V6_COM_SVS_MODE_CLK_SEL, 0x0a),
1357         QMP_PHY_INIT_CFG(QSERDES_V6_COM_BG_TIMER, 0x0a),
1358 };
1359
1360 static const struct qmp_phy_init_tbl x1e80100_usb43dp_tx_tbl[] = {
1361         QMP_PHY_INIT_CFG(QSERDES_V6_N4_TX_LANE_MODE_1, 0x05),
1362         QMP_PHY_INIT_CFG(QSERDES_V6_N4_TX_LANE_MODE_2, 0x50),
1363         QMP_PHY_INIT_CFG(QSERDES_V6_N4_TX_LANE_MODE_3, 0x50),
1364         QMP_PHY_INIT_CFG(QSERDES_V6_N4_TX_RES_CODE_LANE_OFFSET_TX, 0x1f),
1365         QMP_PHY_INIT_CFG(QSERDES_V6_N4_TX_RES_CODE_LANE_OFFSET_RX, 0x0a),
1366 };
1367
1368 static const struct qmp_phy_init_tbl x1e80100_usb43dp_rx_tbl[] = {
1369         QMP_PHY_INIT_CFG(QSERDES_V6_N4_RX_SIGDET_CNTRL, 0x04),
1370         QMP_PHY_INIT_CFG(QSERDES_V6_N4_RX_SIGDET_DEGLITCH_CNTRL, 0x0e),
1371         QMP_PHY_INIT_CFG(QSERDES_V6_N4_RX_SIGDET_ENABLES, 0x00),
1372         QMP_PHY_INIT_CFG(QSERDES_V6_N4_RX_MODE_RATE_0_1_B0, 0xc3),
1373         QMP_PHY_INIT_CFG(QSERDES_V6_N4_RX_MODE_RATE_0_1_B1, 0xc3),
1374         QMP_PHY_INIT_CFG(QSERDES_V6_N4_RX_MODE_RATE_0_1_B2, 0xd8),
1375         QMP_PHY_INIT_CFG(QSERDES_V6_N4_RX_MODE_RATE_0_1_B3, 0x9e),
1376         QMP_PHY_INIT_CFG(QSERDES_V6_N4_RX_MODE_RATE_0_1_B4, 0x36),
1377         QMP_PHY_INIT_CFG(QSERDES_V6_N4_RX_MODE_RATE_0_1_B5, 0xb6),
1378         QMP_PHY_INIT_CFG(QSERDES_V6_N4_RX_MODE_RATE_0_1_B6, 0x64),
1379         QMP_PHY_INIT_CFG(QSERDES_V6_N4_RX_MODE_RATE2_B0, 0xd6),
1380         QMP_PHY_INIT_CFG(QSERDES_V6_N4_RX_MODE_RATE2_B1, 0xee),
1381         QMP_PHY_INIT_CFG(QSERDES_V6_N4_RX_MODE_RATE2_B2, 0x18),
1382         QMP_PHY_INIT_CFG(QSERDES_V6_N4_RX_MODE_RATE2_B3, 0x9a),
1383         QMP_PHY_INIT_CFG(QSERDES_V6_N4_RX_MODE_RATE2_B4, 0x04),
1384         QMP_PHY_INIT_CFG(QSERDES_V6_N4_RX_MODE_RATE2_B5, 0x36),
1385         QMP_PHY_INIT_CFG(QSERDES_V6_N4_RX_MODE_RATE2_B6, 0xe3),
1386         QMP_PHY_INIT_CFG(QSERDES_V6_N4_RX_IVCM_CAL_CODE_OVERRIDE, 0x00),
1387         QMP_PHY_INIT_CFG(QSERDES_V6_N4_RX_RX_IVCM_CAL_CTRL2, 0x80),
1388         QMP_PHY_INIT_CFG(QSERDES_V6_N4_RX_RX_SUMMER_CAL_SPD_MODE, 0x2f),
1389         QMP_PHY_INIT_CFG(QSERDES_V6_N4_RX_DFE_CTLE_POST_CAL_OFFSET, 0x08),
1390         QMP_PHY_INIT_CFG(QSERDES_V6_N4_RX_UCDR_PI_CONTROLS, 0x15),
1391         QMP_PHY_INIT_CFG(QSERDES_V6_N4_RX_UCDR_PI_CTRL1, 0xd0),
1392         QMP_PHY_INIT_CFG(QSERDES_V6_N4_RX_UCDR_PI_CTRL2, 0x48),
1393         QMP_PHY_INIT_CFG(QSERDES_V6_N4_RX_UCDR_SB2_GAIN2_RATE2, 0x0a),
1394         QMP_PHY_INIT_CFG(QSERDES_V6_N4_RX_RX_IVCM_POSTCAL_OFFSET, 0x7c),
1395         QMP_PHY_INIT_CFG(QSERDES_V6_N4_RX_VGA_CAL_CNTRL1, 0x00),
1396         QMP_PHY_INIT_CFG(QSERDES_V6_N4_RX_VGA_CAL_MAN_VAL, 0x04),
1397         QMP_PHY_INIT_CFG(QSERDES_V6_N4_RX_DFE_DAC_ENABLE1, 0x88),
1398         QMP_PHY_INIT_CFG(QSERDES_V6_N4_RX_DFE_3, 0x45),
1399         QMP_PHY_INIT_CFG(QSERDES_V6_N4_RX_GM_CAL, 0x0d),
1400         QMP_PHY_INIT_CFG(QSERDES_V6_N4_RX_UCDR_FO_GAIN_RATE2, 0x09),
1401         QMP_PHY_INIT_CFG(QSERDES_V6_N4_RX_UCDR_SO_GAIN_RATE2, 0x05),
1402         QMP_PHY_INIT_CFG(QSERDES_V6_N4_RX_Q_PI_INTRINSIC_BIAS_RATE32, 0x2f),
1403         QMP_PHY_INIT_CFG(QSERDES_V6_N4_RX_RX_BKUP_CTRL1, 0x14),
1404 };
1405
1406 static const struct qmp_phy_init_tbl x1e80100_usb43dp_pcs_tbl[] = {
1407         QMP_PHY_INIT_CFG(QPHY_V6_N4_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7),
1408         QMP_PHY_INIT_CFG(QPHY_V6_N4_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03),
1409         QMP_PHY_INIT_CFG(QPHY_V6_N4_PCS_LOCK_DETECT_CONFIG1, 0xc4),
1410         QMP_PHY_INIT_CFG(QPHY_V6_N4_PCS_LOCK_DETECT_CONFIG2, 0x89),
1411         QMP_PHY_INIT_CFG(QPHY_V6_N4_PCS_LOCK_DETECT_CONFIG3, 0x20),
1412         QMP_PHY_INIT_CFG(QPHY_V6_N4_PCS_LOCK_DETECT_CONFIG6, 0x13),
1413         QMP_PHY_INIT_CFG(QPHY_V6_N4_PCS_REFGEN_REQ_CONFIG1, 0x21),
1414         QMP_PHY_INIT_CFG(QPHY_V6_N4_PCS_RX_SIGDET_LVL, 0x55),
1415         QMP_PHY_INIT_CFG(QPHY_V6_N4_PCS_RX_CONFIG, 0x0a),
1416         QMP_PHY_INIT_CFG(QPHY_V6_N4_PCS_ALIGN_DETECT_CONFIG1, 0xd4),
1417         QMP_PHY_INIT_CFG(QPHY_V6_N4_PCS_ALIGN_DETECT_CONFIG2, 0x30),
1418         QMP_PHY_INIT_CFG(QPHY_V6_N4_PCS_PCS_TX_RX_CONFIG, 0x0c),
1419         QMP_PHY_INIT_CFG(QPHY_V6_N4_PCS_EQ_CONFIG1, 0x4b),
1420         QMP_PHY_INIT_CFG(QPHY_V6_N4_PCS_EQ_CONFIG5, 0x10),
1421 };
1422
1423 static const struct qmp_phy_init_tbl x1e80100_usb43dp_pcs_usb_tbl[] = {
1424         QMP_PHY_INIT_CFG(QPHY_V6_PCS_USB3_LFPS_DET_HIGH_COUNT_VAL, 0xf8),
1425         QMP_PHY_INIT_CFG(QPHY_V6_PCS_USB3_RXEQTRAINING_DFE_TIME_S2, 0x07),
1426 };
1427
1428 /* list of regulators */
1429 struct qmp_regulator_data {
1430         const char *name;
1431         unsigned int enable_load;
1432 };
1433
1434 static struct qmp_regulator_data qmp_phy_vreg_l[] = {
1435         { .name = "vdda-phy", .enable_load = 21800 },
1436         { .name = "vdda-pll", .enable_load = 36000 },
1437 };
1438
1439 static const u8 qmp_dp_v3_pre_emphasis_hbr3_hbr2[4][4] = {
1440         { 0x00, 0x0c, 0x15, 0x1a },
1441         { 0x02, 0x0e, 0x16, 0xff },
1442         { 0x02, 0x11, 0xff, 0xff },
1443         { 0x04, 0xff, 0xff, 0xff }
1444 };
1445
1446 static const u8 qmp_dp_v3_voltage_swing_hbr3_hbr2[4][4] = {
1447         { 0x02, 0x12, 0x16, 0x1a },
1448         { 0x09, 0x19, 0x1f, 0xff },
1449         { 0x10, 0x1f, 0xff, 0xff },
1450         { 0x1f, 0xff, 0xff, 0xff }
1451 };
1452
1453 static const u8 qmp_dp_v3_pre_emphasis_hbr_rbr[4][4] = {
1454         { 0x00, 0x0c, 0x14, 0x19 },
1455         { 0x00, 0x0b, 0x12, 0xff },
1456         { 0x00, 0x0b, 0xff, 0xff },
1457         { 0x04, 0xff, 0xff, 0xff }
1458 };
1459
1460 static const u8 qmp_dp_v3_voltage_swing_hbr_rbr[4][4] = {
1461         { 0x08, 0x0f, 0x16, 0x1f },
1462         { 0x11, 0x1e, 0x1f, 0xff },
1463         { 0x19, 0x1f, 0xff, 0xff },
1464         { 0x1f, 0xff, 0xff, 0xff }
1465 };
1466
1467 static const u8 qmp_dp_v4_pre_emphasis_hbr3_hbr2[4][4] = {
1468         { 0x00, 0x0c, 0x15, 0x1b },
1469         { 0x02, 0x0e, 0x16, 0xff },
1470         { 0x02, 0x11, 0xff, 0xff },
1471         { 0x04, 0xff, 0xff, 0xff }
1472 };
1473
1474 static const u8 qmp_dp_v4_pre_emphasis_hbr_rbr[4][4] = {
1475         { 0x00, 0x0d, 0x14, 0x1a },
1476         { 0x00, 0x0e, 0x15, 0xff },
1477         { 0x00, 0x0d, 0xff, 0xff },
1478         { 0x03, 0xff, 0xff, 0xff }
1479 };
1480
1481 static const u8 qmp_dp_v4_voltage_swing_hbr_rbr[4][4] = {
1482         { 0x08, 0x0f, 0x16, 0x1f },
1483         { 0x11, 0x1e, 0x1f, 0xff },
1484         { 0x16, 0x1f, 0xff, 0xff },
1485         { 0x1f, 0xff, 0xff, 0xff }
1486 };
1487
1488 static const u8 qmp_dp_v5_pre_emphasis_hbr3_hbr2[4][4] = {
1489         { 0x20, 0x2c, 0x35, 0x3b },
1490         { 0x22, 0x2e, 0x36, 0xff },
1491         { 0x22, 0x31, 0xff, 0xff },
1492         { 0x24, 0xff, 0xff, 0xff }
1493 };
1494
1495 static const u8 qmp_dp_v5_voltage_swing_hbr3_hbr2[4][4] = {
1496         { 0x22, 0x32, 0x36, 0x3a },
1497         { 0x29, 0x39, 0x3f, 0xff },
1498         { 0x30, 0x3f, 0xff, 0xff },
1499         { 0x3f, 0xff, 0xff, 0xff }
1500 };
1501
1502 static const u8 qmp_dp_v5_pre_emphasis_hbr_rbr[4][4] = {
1503         { 0x20, 0x2d, 0x34, 0x3a },
1504         { 0x20, 0x2e, 0x35, 0xff },
1505         { 0x20, 0x2e, 0xff, 0xff },
1506         { 0x24, 0xff, 0xff, 0xff }
1507 };
1508
1509 static const u8 qmp_dp_v5_voltage_swing_hbr_rbr[4][4] = {
1510         { 0x28, 0x2f, 0x36, 0x3f },
1511         { 0x31, 0x3e, 0x3f, 0xff },
1512         { 0x36, 0x3f, 0xff, 0xff },
1513         { 0x3f, 0xff, 0xff, 0xff }
1514 };
1515
1516 static const u8 qmp_dp_v6_voltage_swing_hbr_rbr[4][4] = {
1517         { 0x27, 0x2f, 0x36, 0x3f },
1518         { 0x31, 0x3e, 0x3f, 0xff },
1519         { 0x36, 0x3f, 0xff, 0xff },
1520         { 0x3f, 0xff, 0xff, 0xff }
1521 };
1522
1523 static const u8 qmp_dp_v6_pre_emphasis_hbr_rbr[4][4] = {
1524         { 0x20, 0x2d, 0x34, 0x3a },
1525         { 0x20, 0x2e, 0x35, 0xff },
1526         { 0x20, 0x2e, 0xff, 0xff },
1527         { 0x22, 0xff, 0xff, 0xff }
1528 };
1529
1530 struct qmp_combo;
1531
1532 struct qmp_combo_offsets {
1533         u16 com;
1534         u16 txa;
1535         u16 rxa;
1536         u16 txb;
1537         u16 rxb;
1538         u16 usb3_serdes;
1539         u16 usb3_pcs_misc;
1540         u16 usb3_pcs;
1541         u16 usb3_pcs_usb;
1542         u16 dp_serdes;
1543         u16 dp_txa;
1544         u16 dp_txb;
1545         u16 dp_dp_phy;
1546 };
1547
1548 struct qmp_phy_cfg {
1549         const struct qmp_combo_offsets *offsets;
1550
1551         /* Init sequence for PHY blocks - serdes, tx, rx, pcs */
1552         const struct qmp_phy_init_tbl *serdes_tbl;
1553         int serdes_tbl_num;
1554         const struct qmp_phy_init_tbl *tx_tbl;
1555         int tx_tbl_num;
1556         const struct qmp_phy_init_tbl *rx_tbl;
1557         int rx_tbl_num;
1558         const struct qmp_phy_init_tbl *pcs_tbl;
1559         int pcs_tbl_num;
1560         const struct qmp_phy_init_tbl *pcs_usb_tbl;
1561         int pcs_usb_tbl_num;
1562
1563         const struct qmp_phy_init_tbl *dp_serdes_tbl;
1564         int dp_serdes_tbl_num;
1565         const struct qmp_phy_init_tbl *dp_tx_tbl;
1566         int dp_tx_tbl_num;
1567
1568         /* Init sequence for DP PHY block link rates */
1569         const struct qmp_phy_init_tbl *serdes_tbl_rbr;
1570         int serdes_tbl_rbr_num;
1571         const struct qmp_phy_init_tbl *serdes_tbl_hbr;
1572         int serdes_tbl_hbr_num;
1573         const struct qmp_phy_init_tbl *serdes_tbl_hbr2;
1574         int serdes_tbl_hbr2_num;
1575         const struct qmp_phy_init_tbl *serdes_tbl_hbr3;
1576         int serdes_tbl_hbr3_num;
1577
1578         /* DP PHY swing and pre_emphasis tables */
1579         const u8 (*swing_hbr_rbr)[4][4];
1580         const u8 (*swing_hbr3_hbr2)[4][4];
1581         const u8 (*pre_emphasis_hbr_rbr)[4][4];
1582         const u8 (*pre_emphasis_hbr3_hbr2)[4][4];
1583
1584         /* DP PHY callbacks */
1585         int (*configure_dp_phy)(struct qmp_combo *qmp);
1586         void (*configure_dp_tx)(struct qmp_combo *qmp);
1587         int (*calibrate_dp_phy)(struct qmp_combo *qmp);
1588         void (*dp_aux_init)(struct qmp_combo *qmp);
1589
1590         /* resets to be requested */
1591         const char * const *reset_list;
1592         int num_resets;
1593         /* regulators to be requested */
1594         const struct qmp_regulator_data *vreg_list;
1595         int num_vregs;
1596
1597         /* array of registers with different offsets */
1598         const unsigned int *regs;
1599
1600         /* true, if PHY needs delay after POWER_DOWN */
1601         bool has_pwrdn_delay;
1602
1603         /* Offset from PCS to PCS_USB region */
1604         unsigned int pcs_usb_offset;
1605
1606 };
1607
1608 struct qmp_combo {
1609         struct device *dev;
1610
1611         const struct qmp_phy_cfg *cfg;
1612
1613         void __iomem *com;
1614
1615         void __iomem *serdes;
1616         void __iomem *tx;
1617         void __iomem *rx;
1618         void __iomem *pcs;
1619         void __iomem *tx2;
1620         void __iomem *rx2;
1621         void __iomem *pcs_misc;
1622         void __iomem *pcs_usb;
1623
1624         void __iomem *dp_serdes;
1625         void __iomem *dp_tx;
1626         void __iomem *dp_tx2;
1627         void __iomem *dp_dp_phy;
1628
1629         struct clk *pipe_clk;
1630         struct clk_bulk_data *clks;
1631         int num_clks;
1632         struct reset_control_bulk_data *resets;
1633         struct regulator_bulk_data *vregs;
1634
1635         struct mutex phy_mutex;
1636         int init_count;
1637
1638         struct phy *usb_phy;
1639         enum phy_mode mode;
1640         unsigned int usb_init_count;
1641
1642         struct phy *dp_phy;
1643         unsigned int dp_aux_cfg;
1644         struct phy_configure_opts_dp dp_opts;
1645         unsigned int dp_init_count;
1646
1647         struct clk_fixed_rate pipe_clk_fixed;
1648         struct clk_hw dp_link_hw;
1649         struct clk_hw dp_pixel_hw;
1650
1651         struct typec_switch_dev *sw;
1652         enum typec_orientation orientation;
1653 };
1654
1655 static void qmp_v3_dp_aux_init(struct qmp_combo *qmp);
1656 static void qmp_v3_configure_dp_tx(struct qmp_combo *qmp);
1657 static int qmp_v3_configure_dp_phy(struct qmp_combo *qmp);
1658 static int qmp_v3_calibrate_dp_phy(struct qmp_combo *qmp);
1659
1660 static void qmp_v4_dp_aux_init(struct qmp_combo *qmp);
1661 static void qmp_v4_configure_dp_tx(struct qmp_combo *qmp);
1662 static int qmp_v4_configure_dp_phy(struct qmp_combo *qmp);
1663 static int qmp_v4_calibrate_dp_phy(struct qmp_combo *qmp);
1664
1665 static inline void qphy_setbits(void __iomem *base, u32 offset, u32 val)
1666 {
1667         u32 reg;
1668
1669         reg = readl(base + offset);
1670         reg |= val;
1671         writel(reg, base + offset);
1672
1673         /* ensure that above write is through */
1674         readl(base + offset);
1675 }
1676
1677 static inline void qphy_clrbits(void __iomem *base, u32 offset, u32 val)
1678 {
1679         u32 reg;
1680
1681         reg = readl(base + offset);
1682         reg &= ~val;
1683         writel(reg, base + offset);
1684
1685         /* ensure that above write is through */
1686         readl(base + offset);
1687 }
1688
1689 /* list of clocks required by phy */
1690 static const char * const qmp_combo_phy_clk_l[] = {
1691         "aux", "cfg_ahb", "ref", "com_aux",
1692 };
1693
1694 /* list of resets */
1695 static const char * const msm8996_usb3phy_reset_l[] = {
1696         "phy", "common",
1697 };
1698
1699 static const char * const sc7180_usb3phy_reset_l[] = {
1700         "phy",
1701 };
1702
1703 static const struct qmp_combo_offsets qmp_combo_offsets_v3 = {
1704         .com            = 0x0000,
1705         .txa            = 0x1200,
1706         .rxa            = 0x1400,
1707         .txb            = 0x1600,
1708         .rxb            = 0x1800,
1709         .usb3_serdes    = 0x1000,
1710         .usb3_pcs_misc  = 0x1a00,
1711         .usb3_pcs       = 0x1c00,
1712         .usb3_pcs_usb   = 0x1f00,
1713         .dp_serdes      = 0x2000,
1714         .dp_txa         = 0x2200,
1715         .dp_txb         = 0x2600,
1716         .dp_dp_phy      = 0x2a00,
1717 };
1718
1719 static const struct qmp_combo_offsets qmp_combo_offsets_v5 = {
1720         .com            = 0x0000,
1721         .txa            = 0x0400,
1722         .rxa            = 0x0600,
1723         .txb            = 0x0a00,
1724         .rxb            = 0x0c00,
1725         .usb3_serdes    = 0x1000,
1726         .usb3_pcs_misc  = 0x1200,
1727         .usb3_pcs       = 0x1400,
1728         .usb3_pcs_usb   = 0x1700,
1729         .dp_serdes      = 0x2000,
1730         .dp_dp_phy      = 0x2200,
1731 };
1732
1733 static const struct qmp_phy_cfg sc7180_usb3dpphy_cfg = {
1734         .offsets                = &qmp_combo_offsets_v3,
1735
1736         .serdes_tbl             = qmp_v3_usb3_serdes_tbl,
1737         .serdes_tbl_num         = ARRAY_SIZE(qmp_v3_usb3_serdes_tbl),
1738         .tx_tbl                 = qmp_v3_usb3_tx_tbl,
1739         .tx_tbl_num             = ARRAY_SIZE(qmp_v3_usb3_tx_tbl),
1740         .rx_tbl                 = qmp_v3_usb3_rx_tbl,
1741         .rx_tbl_num             = ARRAY_SIZE(qmp_v3_usb3_rx_tbl),
1742         .pcs_tbl                = qmp_v3_usb3_pcs_tbl,
1743         .pcs_tbl_num            = ARRAY_SIZE(qmp_v3_usb3_pcs_tbl),
1744
1745         .dp_serdes_tbl          = qmp_v3_dp_serdes_tbl,
1746         .dp_serdes_tbl_num      = ARRAY_SIZE(qmp_v3_dp_serdes_tbl),
1747         .dp_tx_tbl              = qmp_v3_dp_tx_tbl,
1748         .dp_tx_tbl_num          = ARRAY_SIZE(qmp_v3_dp_tx_tbl),
1749
1750         .serdes_tbl_rbr         = qmp_v3_dp_serdes_tbl_rbr,
1751         .serdes_tbl_rbr_num     = ARRAY_SIZE(qmp_v3_dp_serdes_tbl_rbr),
1752         .serdes_tbl_hbr         = qmp_v3_dp_serdes_tbl_hbr,
1753         .serdes_tbl_hbr_num     = ARRAY_SIZE(qmp_v3_dp_serdes_tbl_hbr),
1754         .serdes_tbl_hbr2        = qmp_v3_dp_serdes_tbl_hbr2,
1755         .serdes_tbl_hbr2_num    = ARRAY_SIZE(qmp_v3_dp_serdes_tbl_hbr2),
1756         .serdes_tbl_hbr3        = qmp_v3_dp_serdes_tbl_hbr3,
1757         .serdes_tbl_hbr3_num    = ARRAY_SIZE(qmp_v3_dp_serdes_tbl_hbr3),
1758
1759         .swing_hbr_rbr          = &qmp_dp_v3_voltage_swing_hbr_rbr,
1760         .pre_emphasis_hbr_rbr   = &qmp_dp_v3_pre_emphasis_hbr_rbr,
1761         .swing_hbr3_hbr2        = &qmp_dp_v3_voltage_swing_hbr3_hbr2,
1762         .pre_emphasis_hbr3_hbr2 = &qmp_dp_v3_pre_emphasis_hbr3_hbr2,
1763
1764         .dp_aux_init            = qmp_v3_dp_aux_init,
1765         .configure_dp_tx        = qmp_v3_configure_dp_tx,
1766         .configure_dp_phy       = qmp_v3_configure_dp_phy,
1767         .calibrate_dp_phy       = qmp_v3_calibrate_dp_phy,
1768
1769         .reset_list             = sc7180_usb3phy_reset_l,
1770         .num_resets             = ARRAY_SIZE(sc7180_usb3phy_reset_l),
1771         .vreg_list              = qmp_phy_vreg_l,
1772         .num_vregs              = ARRAY_SIZE(qmp_phy_vreg_l),
1773         .regs                   = qmp_v3_usb3phy_regs_layout,
1774
1775         .has_pwrdn_delay        = true,
1776 };
1777
1778 static const struct qmp_phy_cfg sdm845_usb3dpphy_cfg = {
1779         .offsets                = &qmp_combo_offsets_v3,
1780
1781         .serdes_tbl             = qmp_v3_usb3_serdes_tbl,
1782         .serdes_tbl_num         = ARRAY_SIZE(qmp_v3_usb3_serdes_tbl),
1783         .tx_tbl                 = qmp_v3_usb3_tx_tbl,
1784         .tx_tbl_num             = ARRAY_SIZE(qmp_v3_usb3_tx_tbl),
1785         .rx_tbl                 = qmp_v3_usb3_rx_tbl,
1786         .rx_tbl_num             = ARRAY_SIZE(qmp_v3_usb3_rx_tbl),
1787         .pcs_tbl                = qmp_v3_usb3_pcs_tbl,
1788         .pcs_tbl_num            = ARRAY_SIZE(qmp_v3_usb3_pcs_tbl),
1789
1790         .dp_serdes_tbl          = qmp_v3_dp_serdes_tbl,
1791         .dp_serdes_tbl_num      = ARRAY_SIZE(qmp_v3_dp_serdes_tbl),
1792         .dp_tx_tbl              = qmp_v3_dp_tx_tbl,
1793         .dp_tx_tbl_num          = ARRAY_SIZE(qmp_v3_dp_tx_tbl),
1794
1795         .serdes_tbl_rbr         = qmp_v3_dp_serdes_tbl_rbr,
1796         .serdes_tbl_rbr_num     = ARRAY_SIZE(qmp_v3_dp_serdes_tbl_rbr),
1797         .serdes_tbl_hbr         = qmp_v3_dp_serdes_tbl_hbr,
1798         .serdes_tbl_hbr_num     = ARRAY_SIZE(qmp_v3_dp_serdes_tbl_hbr),
1799         .serdes_tbl_hbr2        = qmp_v3_dp_serdes_tbl_hbr2,
1800         .serdes_tbl_hbr2_num    = ARRAY_SIZE(qmp_v3_dp_serdes_tbl_hbr2),
1801         .serdes_tbl_hbr3        = qmp_v3_dp_serdes_tbl_hbr3,
1802         .serdes_tbl_hbr3_num    = ARRAY_SIZE(qmp_v3_dp_serdes_tbl_hbr3),
1803
1804         .swing_hbr_rbr          = &qmp_dp_v3_voltage_swing_hbr_rbr,
1805         .pre_emphasis_hbr_rbr   = &qmp_dp_v3_pre_emphasis_hbr_rbr,
1806         .swing_hbr3_hbr2        = &qmp_dp_v3_voltage_swing_hbr3_hbr2,
1807         .pre_emphasis_hbr3_hbr2 = &qmp_dp_v3_pre_emphasis_hbr3_hbr2,
1808
1809         .dp_aux_init            = qmp_v3_dp_aux_init,
1810         .configure_dp_tx        = qmp_v3_configure_dp_tx,
1811         .configure_dp_phy       = qmp_v3_configure_dp_phy,
1812         .calibrate_dp_phy       = qmp_v3_calibrate_dp_phy,
1813
1814         .reset_list             = msm8996_usb3phy_reset_l,
1815         .num_resets             = ARRAY_SIZE(msm8996_usb3phy_reset_l),
1816         .vreg_list              = qmp_phy_vreg_l,
1817         .num_vregs              = ARRAY_SIZE(qmp_phy_vreg_l),
1818         .regs                   = qmp_v3_usb3phy_regs_layout,
1819
1820         .has_pwrdn_delay        = true,
1821 };
1822
1823 static const struct qmp_phy_cfg sc8180x_usb3dpphy_cfg = {
1824         .offsets                = &qmp_combo_offsets_v3,
1825
1826         .serdes_tbl             = sm8150_usb3_serdes_tbl,
1827         .serdes_tbl_num         = ARRAY_SIZE(sm8150_usb3_serdes_tbl),
1828         .tx_tbl                 = sm8150_usb3_tx_tbl,
1829         .tx_tbl_num             = ARRAY_SIZE(sm8150_usb3_tx_tbl),
1830         .rx_tbl                 = sm8150_usb3_rx_tbl,
1831         .rx_tbl_num             = ARRAY_SIZE(sm8150_usb3_rx_tbl),
1832         .pcs_tbl                = sm8150_usb3_pcs_tbl,
1833         .pcs_tbl_num            = ARRAY_SIZE(sm8150_usb3_pcs_tbl),
1834         .pcs_usb_tbl            = sm8150_usb3_pcs_usb_tbl,
1835         .pcs_usb_tbl_num        = ARRAY_SIZE(sm8150_usb3_pcs_usb_tbl),
1836
1837         .dp_serdes_tbl          = qmp_v4_dp_serdes_tbl,
1838         .dp_serdes_tbl_num      = ARRAY_SIZE(qmp_v4_dp_serdes_tbl),
1839         .dp_tx_tbl              = qmp_v4_dp_tx_tbl,
1840         .dp_tx_tbl_num          = ARRAY_SIZE(qmp_v4_dp_tx_tbl),
1841
1842         .serdes_tbl_rbr         = qmp_v4_dp_serdes_tbl_rbr,
1843         .serdes_tbl_rbr_num     = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_rbr),
1844         .serdes_tbl_hbr         = qmp_v4_dp_serdes_tbl_hbr,
1845         .serdes_tbl_hbr_num     = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_hbr),
1846         .serdes_tbl_hbr2        = qmp_v4_dp_serdes_tbl_hbr2,
1847         .serdes_tbl_hbr2_num    = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_hbr2),
1848         .serdes_tbl_hbr3        = qmp_v4_dp_serdes_tbl_hbr3,
1849         .serdes_tbl_hbr3_num    = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_hbr3),
1850
1851         .swing_hbr_rbr          = &qmp_dp_v3_voltage_swing_hbr_rbr,
1852         .pre_emphasis_hbr_rbr   = &qmp_dp_v3_pre_emphasis_hbr_rbr,
1853         .swing_hbr3_hbr2        = &qmp_dp_v3_voltage_swing_hbr3_hbr2,
1854         .pre_emphasis_hbr3_hbr2 = &qmp_dp_v3_pre_emphasis_hbr3_hbr2,
1855
1856         .dp_aux_init            = qmp_v4_dp_aux_init,
1857         .configure_dp_tx        = qmp_v4_configure_dp_tx,
1858         .configure_dp_phy       = qmp_v4_configure_dp_phy,
1859         .calibrate_dp_phy       = qmp_v4_calibrate_dp_phy,
1860
1861         .reset_list             = msm8996_usb3phy_reset_l,
1862         .num_resets             = ARRAY_SIZE(msm8996_usb3phy_reset_l),
1863         .vreg_list              = qmp_phy_vreg_l,
1864         .num_vregs              = ARRAY_SIZE(qmp_phy_vreg_l),
1865         .regs                   = qmp_v45_usb3phy_regs_layout,
1866         .pcs_usb_offset         = 0x300,
1867
1868         .has_pwrdn_delay        = true,
1869 };
1870
1871 static const struct qmp_phy_cfg sc8280xp_usb43dpphy_cfg = {
1872         .offsets                = &qmp_combo_offsets_v5,
1873
1874         .serdes_tbl             = sc8280xp_usb43dp_serdes_tbl,
1875         .serdes_tbl_num         = ARRAY_SIZE(sc8280xp_usb43dp_serdes_tbl),
1876         .tx_tbl                 = sc8280xp_usb43dp_tx_tbl,
1877         .tx_tbl_num             = ARRAY_SIZE(sc8280xp_usb43dp_tx_tbl),
1878         .rx_tbl                 = sc8280xp_usb43dp_rx_tbl,
1879         .rx_tbl_num             = ARRAY_SIZE(sc8280xp_usb43dp_rx_tbl),
1880         .pcs_tbl                = sc8280xp_usb43dp_pcs_tbl,
1881         .pcs_tbl_num            = ARRAY_SIZE(sc8280xp_usb43dp_pcs_tbl),
1882
1883         .dp_serdes_tbl          = qmp_v5_dp_serdes_tbl,
1884         .dp_serdes_tbl_num      = ARRAY_SIZE(qmp_v5_dp_serdes_tbl),
1885         .dp_tx_tbl              = qmp_v5_5nm_dp_tx_tbl,
1886         .dp_tx_tbl_num          = ARRAY_SIZE(qmp_v5_5nm_dp_tx_tbl),
1887
1888         .serdes_tbl_rbr         = qmp_v4_dp_serdes_tbl_rbr,
1889         .serdes_tbl_rbr_num     = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_rbr),
1890         .serdes_tbl_hbr         = qmp_v4_dp_serdes_tbl_hbr,
1891         .serdes_tbl_hbr_num     = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_hbr),
1892         .serdes_tbl_hbr2        = qmp_v4_dp_serdes_tbl_hbr2,
1893         .serdes_tbl_hbr2_num    = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_hbr2),
1894         .serdes_tbl_hbr3        = qmp_v4_dp_serdes_tbl_hbr3,
1895         .serdes_tbl_hbr3_num    = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_hbr3),
1896
1897         .swing_hbr_rbr          = &qmp_dp_v5_voltage_swing_hbr_rbr,
1898         .pre_emphasis_hbr_rbr   = &qmp_dp_v5_pre_emphasis_hbr_rbr,
1899         .swing_hbr3_hbr2        = &qmp_dp_v5_voltage_swing_hbr3_hbr2,
1900         .pre_emphasis_hbr3_hbr2 = &qmp_dp_v5_pre_emphasis_hbr3_hbr2,
1901
1902         .dp_aux_init            = qmp_v4_dp_aux_init,
1903         .configure_dp_tx        = qmp_v4_configure_dp_tx,
1904         .configure_dp_phy       = qmp_v4_configure_dp_phy,
1905         .calibrate_dp_phy       = qmp_v4_calibrate_dp_phy,
1906
1907         .reset_list             = msm8996_usb3phy_reset_l,
1908         .num_resets             = ARRAY_SIZE(msm8996_usb3phy_reset_l),
1909         .vreg_list              = qmp_phy_vreg_l,
1910         .num_vregs              = ARRAY_SIZE(qmp_phy_vreg_l),
1911         .regs                   = qmp_v5_5nm_usb3phy_regs_layout,
1912 };
1913
1914 static const struct qmp_phy_cfg x1e80100_usb3dpphy_cfg = {
1915         .offsets                = &qmp_combo_offsets_v5,
1916
1917         .serdes_tbl             = x1e80100_usb43dp_serdes_tbl,
1918         .serdes_tbl_num         = ARRAY_SIZE(x1e80100_usb43dp_serdes_tbl),
1919         .tx_tbl                 = x1e80100_usb43dp_tx_tbl,
1920         .tx_tbl_num             = ARRAY_SIZE(x1e80100_usb43dp_tx_tbl),
1921         .rx_tbl                 = x1e80100_usb43dp_rx_tbl,
1922         .rx_tbl_num             = ARRAY_SIZE(x1e80100_usb43dp_rx_tbl),
1923         .pcs_tbl                = x1e80100_usb43dp_pcs_tbl,
1924         .pcs_tbl_num            = ARRAY_SIZE(x1e80100_usb43dp_pcs_tbl),
1925         .pcs_usb_tbl            = x1e80100_usb43dp_pcs_usb_tbl,
1926         .pcs_usb_tbl_num        = ARRAY_SIZE(x1e80100_usb43dp_pcs_usb_tbl),
1927
1928         .dp_serdes_tbl          = qmp_v6_n4_dp_serdes_tbl,
1929         .dp_serdes_tbl_num      = ARRAY_SIZE(qmp_v6_n4_dp_serdes_tbl),
1930         .dp_tx_tbl              = qmp_v6_n4_dp_tx_tbl,
1931         .dp_tx_tbl_num          = ARRAY_SIZE(qmp_v6_n4_dp_tx_tbl),
1932
1933         .serdes_tbl_rbr         = qmp_v6_n4_dp_serdes_tbl_rbr,
1934         .serdes_tbl_rbr_num     = ARRAY_SIZE(qmp_v6_n4_dp_serdes_tbl_rbr),
1935         .serdes_tbl_hbr         = qmp_v6_n4_dp_serdes_tbl_hbr,
1936         .serdes_tbl_hbr_num     = ARRAY_SIZE(qmp_v6_n4_dp_serdes_tbl_hbr),
1937         .serdes_tbl_hbr2        = qmp_v6_n4_dp_serdes_tbl_hbr2,
1938         .serdes_tbl_hbr2_num    = ARRAY_SIZE(qmp_v6_n4_dp_serdes_tbl_hbr2),
1939         .serdes_tbl_hbr3        = qmp_v6_n4_dp_serdes_tbl_hbr3,
1940         .serdes_tbl_hbr3_num    = ARRAY_SIZE(qmp_v6_n4_dp_serdes_tbl_hbr3),
1941
1942         .swing_hbr_rbr          = &qmp_dp_v6_voltage_swing_hbr_rbr,
1943         .pre_emphasis_hbr_rbr   = &qmp_dp_v6_pre_emphasis_hbr_rbr,
1944         .swing_hbr3_hbr2        = &qmp_dp_v5_voltage_swing_hbr3_hbr2,
1945         .pre_emphasis_hbr3_hbr2 = &qmp_dp_v5_pre_emphasis_hbr3_hbr2,
1946
1947         .dp_aux_init            = qmp_v4_dp_aux_init,
1948         .configure_dp_tx        = qmp_v4_configure_dp_tx,
1949         .configure_dp_phy       = qmp_v4_configure_dp_phy,
1950         .calibrate_dp_phy       = qmp_v4_calibrate_dp_phy,
1951
1952         .reset_list             = msm8996_usb3phy_reset_l,
1953         .num_resets             = ARRAY_SIZE(msm8996_usb3phy_reset_l),
1954         .vreg_list              = qmp_phy_vreg_l,
1955         .num_vregs              = ARRAY_SIZE(qmp_phy_vreg_l),
1956         .regs                   = qmp_v6_n4_usb3phy_regs_layout,
1957 };
1958
1959 static const struct qmp_phy_cfg sm6350_usb3dpphy_cfg = {
1960         .offsets                = &qmp_combo_offsets_v3,
1961
1962         .serdes_tbl             = qmp_v3_usb3_serdes_tbl,
1963         .serdes_tbl_num         = ARRAY_SIZE(qmp_v3_usb3_serdes_tbl),
1964         .tx_tbl                 = qmp_v3_usb3_tx_tbl,
1965         .tx_tbl_num             = ARRAY_SIZE(qmp_v3_usb3_tx_tbl),
1966         .rx_tbl                 = sm6350_usb3_rx_tbl,
1967         .rx_tbl_num             = ARRAY_SIZE(sm6350_usb3_rx_tbl),
1968         .pcs_tbl                = sm6350_usb3_pcs_tbl,
1969         .pcs_tbl_num            = ARRAY_SIZE(sm6350_usb3_pcs_tbl),
1970
1971         .dp_serdes_tbl          = qmp_v3_dp_serdes_tbl,
1972         .dp_serdes_tbl_num      = ARRAY_SIZE(qmp_v3_dp_serdes_tbl),
1973         .dp_tx_tbl              = qmp_v3_dp_tx_tbl,
1974         .dp_tx_tbl_num          = ARRAY_SIZE(qmp_v3_dp_tx_tbl),
1975
1976         .serdes_tbl_rbr         = qmp_v3_dp_serdes_tbl_rbr,
1977         .serdes_tbl_rbr_num     = ARRAY_SIZE(qmp_v3_dp_serdes_tbl_rbr),
1978         .serdes_tbl_hbr         = qmp_v3_dp_serdes_tbl_hbr,
1979         .serdes_tbl_hbr_num     = ARRAY_SIZE(qmp_v3_dp_serdes_tbl_hbr),
1980         .serdes_tbl_hbr2        = qmp_v3_dp_serdes_tbl_hbr2,
1981         .serdes_tbl_hbr2_num    = ARRAY_SIZE(qmp_v3_dp_serdes_tbl_hbr2),
1982         .serdes_tbl_hbr3        = qmp_v3_dp_serdes_tbl_hbr3,
1983         .serdes_tbl_hbr3_num    = ARRAY_SIZE(qmp_v3_dp_serdes_tbl_hbr3),
1984
1985         .swing_hbr_rbr          = &qmp_dp_v3_voltage_swing_hbr_rbr,
1986         .pre_emphasis_hbr_rbr   = &qmp_dp_v3_pre_emphasis_hbr_rbr,
1987         .swing_hbr3_hbr2        = &qmp_dp_v3_voltage_swing_hbr3_hbr2,
1988         .pre_emphasis_hbr3_hbr2 = &qmp_dp_v3_pre_emphasis_hbr3_hbr2,
1989
1990         .dp_aux_init            = qmp_v3_dp_aux_init,
1991         .configure_dp_tx        = qmp_v3_configure_dp_tx,
1992         .configure_dp_phy       = qmp_v3_configure_dp_phy,
1993         .calibrate_dp_phy       = qmp_v3_calibrate_dp_phy,
1994
1995         .reset_list             = msm8996_usb3phy_reset_l,
1996         .num_resets             = ARRAY_SIZE(msm8996_usb3phy_reset_l),
1997         .vreg_list              = qmp_phy_vreg_l,
1998         .num_vregs              = ARRAY_SIZE(qmp_phy_vreg_l),
1999         .regs                   = qmp_v3_usb3phy_regs_layout,
2000 };
2001
2002 static const struct qmp_phy_cfg sm8250_usb3dpphy_cfg = {
2003         .offsets                = &qmp_combo_offsets_v3,
2004
2005         .serdes_tbl             = sm8150_usb3_serdes_tbl,
2006         .serdes_tbl_num         = ARRAY_SIZE(sm8150_usb3_serdes_tbl),
2007         .tx_tbl                 = sm8250_usb3_tx_tbl,
2008         .tx_tbl_num             = ARRAY_SIZE(sm8250_usb3_tx_tbl),
2009         .rx_tbl                 = sm8250_usb3_rx_tbl,
2010         .rx_tbl_num             = ARRAY_SIZE(sm8250_usb3_rx_tbl),
2011         .pcs_tbl                = sm8250_usb3_pcs_tbl,
2012         .pcs_tbl_num            = ARRAY_SIZE(sm8250_usb3_pcs_tbl),
2013         .pcs_usb_tbl            = sm8250_usb3_pcs_usb_tbl,
2014         .pcs_usb_tbl_num        = ARRAY_SIZE(sm8250_usb3_pcs_usb_tbl),
2015
2016         .dp_serdes_tbl          = qmp_v4_dp_serdes_tbl,
2017         .dp_serdes_tbl_num      = ARRAY_SIZE(qmp_v4_dp_serdes_tbl),
2018         .dp_tx_tbl              = qmp_v4_dp_tx_tbl,
2019         .dp_tx_tbl_num          = ARRAY_SIZE(qmp_v4_dp_tx_tbl),
2020
2021         .serdes_tbl_rbr         = qmp_v4_dp_serdes_tbl_rbr,
2022         .serdes_tbl_rbr_num     = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_rbr),
2023         .serdes_tbl_hbr         = qmp_v4_dp_serdes_tbl_hbr,
2024         .serdes_tbl_hbr_num     = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_hbr),
2025         .serdes_tbl_hbr2        = qmp_v4_dp_serdes_tbl_hbr2,
2026         .serdes_tbl_hbr2_num    = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_hbr2),
2027         .serdes_tbl_hbr3        = qmp_v4_dp_serdes_tbl_hbr3,
2028         .serdes_tbl_hbr3_num    = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_hbr3),
2029
2030         .swing_hbr_rbr          = &qmp_dp_v3_voltage_swing_hbr_rbr,
2031         .pre_emphasis_hbr_rbr   = &qmp_dp_v3_pre_emphasis_hbr_rbr,
2032         .swing_hbr3_hbr2        = &qmp_dp_v3_voltage_swing_hbr3_hbr2,
2033         .pre_emphasis_hbr3_hbr2 = &qmp_dp_v3_pre_emphasis_hbr3_hbr2,
2034
2035         .dp_aux_init            = qmp_v4_dp_aux_init,
2036         .configure_dp_tx        = qmp_v4_configure_dp_tx,
2037         .configure_dp_phy       = qmp_v4_configure_dp_phy,
2038         .calibrate_dp_phy       = qmp_v4_calibrate_dp_phy,
2039
2040         .reset_list             = msm8996_usb3phy_reset_l,
2041         .num_resets             = ARRAY_SIZE(msm8996_usb3phy_reset_l),
2042         .vreg_list              = qmp_phy_vreg_l,
2043         .num_vregs              = ARRAY_SIZE(qmp_phy_vreg_l),
2044         .regs                   = qmp_v45_usb3phy_regs_layout,
2045         .pcs_usb_offset         = 0x300,
2046
2047         .has_pwrdn_delay        = true,
2048 };
2049
2050 static const struct qmp_phy_cfg sm8350_usb3dpphy_cfg = {
2051         .offsets                = &qmp_combo_offsets_v3,
2052
2053         .serdes_tbl             = sm8150_usb3_serdes_tbl,
2054         .serdes_tbl_num         = ARRAY_SIZE(sm8150_usb3_serdes_tbl),
2055         .tx_tbl                 = sm8350_usb3_tx_tbl,
2056         .tx_tbl_num             = ARRAY_SIZE(sm8350_usb3_tx_tbl),
2057         .rx_tbl                 = sm8350_usb3_rx_tbl,
2058         .rx_tbl_num             = ARRAY_SIZE(sm8350_usb3_rx_tbl),
2059         .pcs_tbl                = sm8350_usb3_pcs_tbl,
2060         .pcs_tbl_num            = ARRAY_SIZE(sm8350_usb3_pcs_tbl),
2061         .pcs_usb_tbl            = sm8350_usb3_pcs_usb_tbl,
2062         .pcs_usb_tbl_num        = ARRAY_SIZE(sm8350_usb3_pcs_usb_tbl),
2063
2064         .dp_serdes_tbl          = qmp_v4_dp_serdes_tbl,
2065         .dp_serdes_tbl_num      = ARRAY_SIZE(qmp_v4_dp_serdes_tbl),
2066         .dp_tx_tbl              = qmp_v5_dp_tx_tbl,
2067         .dp_tx_tbl_num          = ARRAY_SIZE(qmp_v5_dp_tx_tbl),
2068
2069         .serdes_tbl_rbr         = qmp_v4_dp_serdes_tbl_rbr,
2070         .serdes_tbl_rbr_num     = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_rbr),
2071         .serdes_tbl_hbr         = qmp_v4_dp_serdes_tbl_hbr,
2072         .serdes_tbl_hbr_num     = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_hbr),
2073         .serdes_tbl_hbr2        = qmp_v4_dp_serdes_tbl_hbr2,
2074         .serdes_tbl_hbr2_num    = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_hbr2),
2075         .serdes_tbl_hbr3        = qmp_v4_dp_serdes_tbl_hbr3,
2076         .serdes_tbl_hbr3_num    = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_hbr3),
2077
2078         .swing_hbr_rbr          = &qmp_dp_v4_voltage_swing_hbr_rbr,
2079         .pre_emphasis_hbr_rbr   = &qmp_dp_v4_pre_emphasis_hbr_rbr,
2080         .swing_hbr3_hbr2        = &qmp_dp_v3_voltage_swing_hbr3_hbr2,
2081         .pre_emphasis_hbr3_hbr2 = &qmp_dp_v4_pre_emphasis_hbr3_hbr2,
2082
2083         .dp_aux_init            = qmp_v4_dp_aux_init,
2084         .configure_dp_tx        = qmp_v4_configure_dp_tx,
2085         .configure_dp_phy       = qmp_v4_configure_dp_phy,
2086         .calibrate_dp_phy       = qmp_v4_calibrate_dp_phy,
2087
2088         .reset_list             = msm8996_usb3phy_reset_l,
2089         .num_resets             = ARRAY_SIZE(msm8996_usb3phy_reset_l),
2090         .vreg_list              = qmp_phy_vreg_l,
2091         .num_vregs              = ARRAY_SIZE(qmp_phy_vreg_l),
2092         .regs                   = qmp_v45_usb3phy_regs_layout,
2093
2094         .has_pwrdn_delay        = true,
2095 };
2096
2097 static const struct qmp_phy_cfg sm8550_usb3dpphy_cfg = {
2098         .offsets                = &qmp_combo_offsets_v3,
2099
2100         .serdes_tbl             = sm8550_usb3_serdes_tbl,
2101         .serdes_tbl_num         = ARRAY_SIZE(sm8550_usb3_serdes_tbl),
2102         .tx_tbl                 = sm8550_usb3_tx_tbl,
2103         .tx_tbl_num             = ARRAY_SIZE(sm8550_usb3_tx_tbl),
2104         .rx_tbl                 = sm8550_usb3_rx_tbl,
2105         .rx_tbl_num             = ARRAY_SIZE(sm8550_usb3_rx_tbl),
2106         .pcs_tbl                = sm8550_usb3_pcs_tbl,
2107         .pcs_tbl_num            = ARRAY_SIZE(sm8550_usb3_pcs_tbl),
2108         .pcs_usb_tbl            = sm8550_usb3_pcs_usb_tbl,
2109         .pcs_usb_tbl_num        = ARRAY_SIZE(sm8550_usb3_pcs_usb_tbl),
2110
2111         .dp_serdes_tbl          = qmp_v6_dp_serdes_tbl,
2112         .dp_serdes_tbl_num      = ARRAY_SIZE(qmp_v6_dp_serdes_tbl),
2113         .dp_tx_tbl              = qmp_v6_dp_tx_tbl,
2114         .dp_tx_tbl_num          = ARRAY_SIZE(qmp_v6_dp_tx_tbl),
2115
2116         .serdes_tbl_rbr         = qmp_v6_dp_serdes_tbl_rbr,
2117         .serdes_tbl_rbr_num     = ARRAY_SIZE(qmp_v6_dp_serdes_tbl_rbr),
2118         .serdes_tbl_hbr         = qmp_v6_dp_serdes_tbl_hbr,
2119         .serdes_tbl_hbr_num     = ARRAY_SIZE(qmp_v6_dp_serdes_tbl_hbr),
2120         .serdes_tbl_hbr2        = qmp_v6_dp_serdes_tbl_hbr2,
2121         .serdes_tbl_hbr2_num    = ARRAY_SIZE(qmp_v6_dp_serdes_tbl_hbr2),
2122         .serdes_tbl_hbr3        = qmp_v6_dp_serdes_tbl_hbr3,
2123         .serdes_tbl_hbr3_num    = ARRAY_SIZE(qmp_v6_dp_serdes_tbl_hbr3),
2124
2125         .swing_hbr_rbr          = &qmp_dp_v5_voltage_swing_hbr_rbr,
2126         .pre_emphasis_hbr_rbr   = &qmp_dp_v6_pre_emphasis_hbr_rbr,
2127         .swing_hbr3_hbr2        = &qmp_dp_v5_voltage_swing_hbr3_hbr2,
2128         .pre_emphasis_hbr3_hbr2 = &qmp_dp_v5_pre_emphasis_hbr3_hbr2,
2129
2130         .dp_aux_init            = qmp_v4_dp_aux_init,
2131         .configure_dp_tx        = qmp_v4_configure_dp_tx,
2132         .configure_dp_phy       = qmp_v4_configure_dp_phy,
2133         .calibrate_dp_phy       = qmp_v4_calibrate_dp_phy,
2134
2135         .regs                   = qmp_v6_usb3phy_regs_layout,
2136         .reset_list             = msm8996_usb3phy_reset_l,
2137         .num_resets             = ARRAY_SIZE(msm8996_usb3phy_reset_l),
2138         .vreg_list              = qmp_phy_vreg_l,
2139         .num_vregs              = ARRAY_SIZE(qmp_phy_vreg_l),
2140 };
2141
2142 static const struct qmp_phy_cfg sm8650_usb3dpphy_cfg = {
2143         .offsets                = &qmp_combo_offsets_v3,
2144
2145         .serdes_tbl             = sm8550_usb3_serdes_tbl,
2146         .serdes_tbl_num         = ARRAY_SIZE(sm8550_usb3_serdes_tbl),
2147         .tx_tbl                 = sm8550_usb3_tx_tbl,
2148         .tx_tbl_num             = ARRAY_SIZE(sm8550_usb3_tx_tbl),
2149         .rx_tbl                 = sm8550_usb3_rx_tbl,
2150         .rx_tbl_num             = ARRAY_SIZE(sm8550_usb3_rx_tbl),
2151         .pcs_tbl                = sm8550_usb3_pcs_tbl,
2152         .pcs_tbl_num            = ARRAY_SIZE(sm8550_usb3_pcs_tbl),
2153         .pcs_usb_tbl            = sm8550_usb3_pcs_usb_tbl,
2154         .pcs_usb_tbl_num        = ARRAY_SIZE(sm8550_usb3_pcs_usb_tbl),
2155
2156         .dp_serdes_tbl          = qmp_v6_dp_serdes_tbl,
2157         .dp_serdes_tbl_num      = ARRAY_SIZE(qmp_v6_dp_serdes_tbl),
2158         .dp_tx_tbl              = qmp_v6_dp_tx_tbl,
2159         .dp_tx_tbl_num          = ARRAY_SIZE(qmp_v6_dp_tx_tbl),
2160
2161         .serdes_tbl_rbr         = qmp_v6_dp_serdes_tbl_rbr,
2162         .serdes_tbl_rbr_num     = ARRAY_SIZE(qmp_v6_dp_serdes_tbl_rbr),
2163         .serdes_tbl_hbr         = qmp_v6_dp_serdes_tbl_hbr,
2164         .serdes_tbl_hbr_num     = ARRAY_SIZE(qmp_v6_dp_serdes_tbl_hbr),
2165         .serdes_tbl_hbr2        = qmp_v6_dp_serdes_tbl_hbr2,
2166         .serdes_tbl_hbr2_num    = ARRAY_SIZE(qmp_v6_dp_serdes_tbl_hbr2),
2167         .serdes_tbl_hbr3        = qmp_v6_dp_serdes_tbl_hbr3,
2168         .serdes_tbl_hbr3_num    = ARRAY_SIZE(qmp_v6_dp_serdes_tbl_hbr3),
2169
2170         .swing_hbr_rbr          = &qmp_dp_v6_voltage_swing_hbr_rbr,
2171         .pre_emphasis_hbr_rbr   = &qmp_dp_v6_pre_emphasis_hbr_rbr,
2172         .swing_hbr3_hbr2        = &qmp_dp_v5_voltage_swing_hbr3_hbr2,
2173         .pre_emphasis_hbr3_hbr2 = &qmp_dp_v5_pre_emphasis_hbr3_hbr2,
2174
2175         .dp_aux_init            = qmp_v4_dp_aux_init,
2176         .configure_dp_tx        = qmp_v4_configure_dp_tx,
2177         .configure_dp_phy       = qmp_v4_configure_dp_phy,
2178         .calibrate_dp_phy       = qmp_v4_calibrate_dp_phy,
2179
2180         .regs                   = qmp_v6_usb3phy_regs_layout,
2181         .reset_list             = msm8996_usb3phy_reset_l,
2182         .num_resets             = ARRAY_SIZE(msm8996_usb3phy_reset_l),
2183         .vreg_list              = qmp_phy_vreg_l,
2184         .num_vregs              = ARRAY_SIZE(qmp_phy_vreg_l),
2185 };
2186
2187 static int qmp_combo_dp_serdes_init(struct qmp_combo *qmp)
2188 {
2189         const struct qmp_phy_cfg *cfg = qmp->cfg;
2190         void __iomem *serdes = qmp->dp_serdes;
2191         const struct phy_configure_opts_dp *dp_opts = &qmp->dp_opts;
2192
2193         qmp_configure(qmp->dev, serdes, cfg->dp_serdes_tbl,
2194                       cfg->dp_serdes_tbl_num);
2195
2196         switch (dp_opts->link_rate) {
2197         case 1620:
2198                 qmp_configure(qmp->dev, serdes, cfg->serdes_tbl_rbr,
2199                               cfg->serdes_tbl_rbr_num);
2200                 break;
2201         case 2700:
2202                 qmp_configure(qmp->dev, serdes, cfg->serdes_tbl_hbr,
2203                               cfg->serdes_tbl_hbr_num);
2204                 break;
2205         case 5400:
2206                 qmp_configure(qmp->dev, serdes, cfg->serdes_tbl_hbr2,
2207                               cfg->serdes_tbl_hbr2_num);
2208                 break;
2209         case 8100:
2210                 qmp_configure(qmp->dev, serdes, cfg->serdes_tbl_hbr3,
2211                               cfg->serdes_tbl_hbr3_num);
2212                 break;
2213         default:
2214                 /* Other link rates aren't supported */
2215                 return -EINVAL;
2216         }
2217
2218         return 0;
2219 }
2220
2221 static void qmp_v3_dp_aux_init(struct qmp_combo *qmp)
2222 {
2223         const struct qmp_phy_cfg *cfg = qmp->cfg;
2224
2225         writel(DP_PHY_PD_CTL_PWRDN | DP_PHY_PD_CTL_AUX_PWRDN |
2226                DP_PHY_PD_CTL_PLL_PWRDN | DP_PHY_PD_CTL_DP_CLAMP_EN,
2227                qmp->dp_dp_phy + QSERDES_DP_PHY_PD_CTL);
2228
2229         /* Turn on BIAS current for PHY/PLL */
2230         writel(QSERDES_V3_COM_BIAS_EN | QSERDES_V3_COM_BIAS_EN_MUX |
2231                QSERDES_V3_COM_CLKBUF_L_EN | QSERDES_V3_COM_EN_SYSCLK_TX_SEL,
2232                qmp->dp_serdes + cfg->regs[QPHY_COM_BIAS_EN_CLKBUFLR_EN]);
2233
2234         writel(DP_PHY_PD_CTL_PSR_PWRDN, qmp->dp_dp_phy + QSERDES_DP_PHY_PD_CTL);
2235
2236         writel(DP_PHY_PD_CTL_PWRDN | DP_PHY_PD_CTL_AUX_PWRDN |
2237                DP_PHY_PD_CTL_LANE_0_1_PWRDN |
2238                DP_PHY_PD_CTL_LANE_2_3_PWRDN | DP_PHY_PD_CTL_PLL_PWRDN |
2239                DP_PHY_PD_CTL_DP_CLAMP_EN,
2240                qmp->dp_dp_phy + QSERDES_DP_PHY_PD_CTL);
2241
2242         writel(QSERDES_V3_COM_BIAS_EN |
2243                QSERDES_V3_COM_BIAS_EN_MUX | QSERDES_V3_COM_CLKBUF_R_EN |
2244                QSERDES_V3_COM_CLKBUF_L_EN | QSERDES_V3_COM_EN_SYSCLK_TX_SEL |
2245                QSERDES_V3_COM_CLKBUF_RX_DRIVE_L,
2246                qmp->dp_serdes + cfg->regs[QPHY_COM_BIAS_EN_CLKBUFLR_EN]);
2247
2248         writel(0x00, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG0);
2249         writel(0x13, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG1);
2250         writel(0x24, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG2);
2251         writel(0x00, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG3);
2252         writel(0x0a, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG4);
2253         writel(0x26, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG5);
2254         writel(0x0a, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG6);
2255         writel(0x03, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG7);
2256         writel(0xbb, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG8);
2257         writel(0x03, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG9);
2258         qmp->dp_aux_cfg = 0;
2259
2260         writel(PHY_AUX_STOP_ERR_MASK | PHY_AUX_DEC_ERR_MASK |
2261                PHY_AUX_SYNC_ERR_MASK | PHY_AUX_ALIGN_ERR_MASK |
2262                PHY_AUX_REQ_ERR_MASK,
2263                qmp->dp_dp_phy + QSERDES_V3_DP_PHY_AUX_INTERRUPT_MASK);
2264 }
2265
2266 static int qmp_combo_configure_dp_swing(struct qmp_combo *qmp)
2267 {
2268         const struct phy_configure_opts_dp *dp_opts = &qmp->dp_opts;
2269         const struct qmp_phy_cfg *cfg = qmp->cfg;
2270         unsigned int v_level = 0, p_level = 0;
2271         u8 voltage_swing_cfg, pre_emphasis_cfg;
2272         int i;
2273
2274         for (i = 0; i < dp_opts->lanes; i++) {
2275                 v_level = max(v_level, dp_opts->voltage[i]);
2276                 p_level = max(p_level, dp_opts->pre[i]);
2277         }
2278
2279         if (dp_opts->link_rate <= 2700) {
2280                 voltage_swing_cfg = (*cfg->swing_hbr_rbr)[v_level][p_level];
2281                 pre_emphasis_cfg = (*cfg->pre_emphasis_hbr_rbr)[v_level][p_level];
2282         } else {
2283                 voltage_swing_cfg = (*cfg->swing_hbr3_hbr2)[v_level][p_level];
2284                 pre_emphasis_cfg = (*cfg->pre_emphasis_hbr3_hbr2)[v_level][p_level];
2285         }
2286
2287         /* TODO: Move check to config check */
2288         if (voltage_swing_cfg == 0xFF && pre_emphasis_cfg == 0xFF)
2289                 return -EINVAL;
2290
2291         /* Enable MUX to use Cursor values from these registers */
2292         voltage_swing_cfg |= DP_PHY_TXn_TX_DRV_LVL_MUX_EN;
2293         pre_emphasis_cfg |= DP_PHY_TXn_TX_EMP_POST1_LVL_MUX_EN;
2294
2295         writel(voltage_swing_cfg, qmp->dp_tx + cfg->regs[QPHY_TX_TX_DRV_LVL]);
2296         writel(pre_emphasis_cfg, qmp->dp_tx + cfg->regs[QPHY_TX_TX_EMP_POST1_LVL]);
2297         writel(voltage_swing_cfg, qmp->dp_tx2 + cfg->regs[QPHY_TX_TX_DRV_LVL]);
2298         writel(pre_emphasis_cfg, qmp->dp_tx2 + cfg->regs[QPHY_TX_TX_EMP_POST1_LVL]);
2299
2300         return 0;
2301 }
2302
2303 static void qmp_v3_configure_dp_tx(struct qmp_combo *qmp)
2304 {
2305         const struct phy_configure_opts_dp *dp_opts = &qmp->dp_opts;
2306         u32 bias_en, drvr_en;
2307
2308         if (qmp_combo_configure_dp_swing(qmp) < 0)
2309                 return;
2310
2311         if (dp_opts->lanes == 1) {
2312                 bias_en = 0x3e;
2313                 drvr_en = 0x13;
2314         } else {
2315                 bias_en = 0x3f;
2316                 drvr_en = 0x10;
2317         }
2318
2319         writel(drvr_en, qmp->dp_tx + QSERDES_V3_TX_HIGHZ_DRVR_EN);
2320         writel(bias_en, qmp->dp_tx + QSERDES_V3_TX_TRANSCEIVER_BIAS_EN);
2321         writel(drvr_en, qmp->dp_tx2 + QSERDES_V3_TX_HIGHZ_DRVR_EN);
2322         writel(bias_en, qmp->dp_tx2 + QSERDES_V3_TX_TRANSCEIVER_BIAS_EN);
2323 }
2324
2325 static bool qmp_combo_configure_dp_mode(struct qmp_combo *qmp)
2326 {
2327         bool reverse = (qmp->orientation == TYPEC_ORIENTATION_REVERSE);
2328         const struct phy_configure_opts_dp *dp_opts = &qmp->dp_opts;
2329         u32 val;
2330
2331         val = DP_PHY_PD_CTL_PWRDN | DP_PHY_PD_CTL_AUX_PWRDN |
2332               DP_PHY_PD_CTL_PLL_PWRDN | DP_PHY_PD_CTL_DP_CLAMP_EN;
2333
2334         if (dp_opts->lanes == 4 || reverse)
2335                 val |= DP_PHY_PD_CTL_LANE_0_1_PWRDN;
2336         if (dp_opts->lanes == 4 || !reverse)
2337                 val |= DP_PHY_PD_CTL_LANE_2_3_PWRDN;
2338
2339         writel(val, qmp->dp_dp_phy + QSERDES_DP_PHY_PD_CTL);
2340
2341         if (reverse)
2342                 writel(0x4c, qmp->dp_dp_phy + QSERDES_DP_PHY_MODE);
2343         else
2344                 writel(0x5c, qmp->dp_dp_phy + QSERDES_DP_PHY_MODE);
2345
2346         return reverse;
2347 }
2348
2349 static int qmp_combo_configure_dp_clocks(struct qmp_combo *qmp)
2350 {
2351         const struct phy_configure_opts_dp *dp_opts = &qmp->dp_opts;
2352         u32 phy_vco_div;
2353         unsigned long pixel_freq;
2354         const struct qmp_phy_cfg *cfg = qmp->cfg;
2355
2356         switch (dp_opts->link_rate) {
2357         case 1620:
2358                 phy_vco_div = 0x1;
2359                 pixel_freq = 1620000000UL / 2;
2360                 break;
2361         case 2700:
2362                 phy_vco_div = 0x1;
2363                 pixel_freq = 2700000000UL / 2;
2364                 break;
2365         case 5400:
2366                 phy_vco_div = 0x2;
2367                 pixel_freq = 5400000000UL / 4;
2368                 break;
2369         case 8100:
2370                 phy_vco_div = 0x0;
2371                 pixel_freq = 8100000000UL / 6;
2372                 break;
2373         default:
2374                 /* Other link rates aren't supported */
2375                 return -EINVAL;
2376         }
2377         writel(phy_vco_div, qmp->dp_dp_phy + cfg->regs[QPHY_DP_PHY_VCO_DIV]);
2378
2379         clk_set_rate(qmp->dp_link_hw.clk, dp_opts->link_rate * 100000);
2380         clk_set_rate(qmp->dp_pixel_hw.clk, pixel_freq);
2381
2382         return 0;
2383 }
2384
2385 static int qmp_v3_configure_dp_phy(struct qmp_combo *qmp)
2386 {
2387         const struct qmp_phy_cfg *cfg = qmp->cfg;
2388         u32 status;
2389         int ret;
2390
2391         qmp_combo_configure_dp_mode(qmp);
2392
2393         writel(0x05, qmp->dp_dp_phy + QSERDES_V3_DP_PHY_TX0_TX1_LANE_CTL);
2394         writel(0x05, qmp->dp_dp_phy + QSERDES_V3_DP_PHY_TX2_TX3_LANE_CTL);
2395
2396         ret = qmp_combo_configure_dp_clocks(qmp);
2397         if (ret)
2398                 return ret;
2399
2400         writel(0x04, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG2);
2401         writel(0x01, qmp->dp_dp_phy + QSERDES_DP_PHY_CFG);
2402         writel(0x05, qmp->dp_dp_phy + QSERDES_DP_PHY_CFG);
2403         writel(0x01, qmp->dp_dp_phy + QSERDES_DP_PHY_CFG);
2404         writel(0x09, qmp->dp_dp_phy + QSERDES_DP_PHY_CFG);
2405
2406         writel(0x20, qmp->dp_serdes + cfg->regs[QPHY_COM_RESETSM_CNTRL]);
2407
2408         if (readl_poll_timeout(qmp->dp_serdes + cfg->regs[QPHY_COM_C_READY_STATUS],
2409                         status,
2410                         ((status & BIT(0)) > 0),
2411                         500,
2412                         10000))
2413                 return -ETIMEDOUT;
2414
2415         writel(0x19, qmp->dp_dp_phy + QSERDES_DP_PHY_CFG);
2416
2417         if (readl_poll_timeout(qmp->dp_dp_phy + cfg->regs[QPHY_DP_PHY_STATUS],
2418                         status,
2419                         ((status & BIT(1)) > 0),
2420                         500,
2421                         10000))
2422                 return -ETIMEDOUT;
2423
2424         writel(0x18, qmp->dp_dp_phy + QSERDES_DP_PHY_CFG);
2425         udelay(2000);
2426         writel(0x19, qmp->dp_dp_phy + QSERDES_DP_PHY_CFG);
2427
2428         return readl_poll_timeout(qmp->dp_dp_phy + cfg->regs[QPHY_DP_PHY_STATUS],
2429                         status,
2430                         ((status & BIT(1)) > 0),
2431                         500,
2432                         10000);
2433 }
2434
2435 /*
2436  * We need to calibrate the aux setting here as many times
2437  * as the caller tries
2438  */
2439 static int qmp_v3_calibrate_dp_phy(struct qmp_combo *qmp)
2440 {
2441         static const u8 cfg1_settings[] = { 0x13, 0x23, 0x1d };
2442         u8 val;
2443
2444         qmp->dp_aux_cfg++;
2445         qmp->dp_aux_cfg %= ARRAY_SIZE(cfg1_settings);
2446         val = cfg1_settings[qmp->dp_aux_cfg];
2447
2448         writel(val, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG1);
2449
2450         return 0;
2451 }
2452
2453 static void qmp_v4_dp_aux_init(struct qmp_combo *qmp)
2454 {
2455         const struct qmp_phy_cfg *cfg = qmp->cfg;
2456
2457         writel(DP_PHY_PD_CTL_PWRDN | DP_PHY_PD_CTL_PSR_PWRDN | DP_PHY_PD_CTL_AUX_PWRDN |
2458                DP_PHY_PD_CTL_PLL_PWRDN | DP_PHY_PD_CTL_DP_CLAMP_EN,
2459                qmp->dp_dp_phy + QSERDES_DP_PHY_PD_CTL);
2460
2461         /* Turn on BIAS current for PHY/PLL */
2462         writel(0x17, qmp->dp_serdes + cfg->regs[QPHY_COM_BIAS_EN_CLKBUFLR_EN]);
2463
2464         writel(0x00, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG0);
2465         writel(0x13, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG1);
2466         writel(0xa4, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG2);
2467         writel(0x00, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG3);
2468         writel(0x0a, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG4);
2469         writel(0x26, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG5);
2470         writel(0x0a, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG6);
2471         writel(0x03, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG7);
2472         writel(0xb7, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG8);
2473         writel(0x03, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG9);
2474         qmp->dp_aux_cfg = 0;
2475
2476         writel(PHY_AUX_STOP_ERR_MASK | PHY_AUX_DEC_ERR_MASK |
2477                PHY_AUX_SYNC_ERR_MASK | PHY_AUX_ALIGN_ERR_MASK |
2478                PHY_AUX_REQ_ERR_MASK,
2479                qmp->dp_dp_phy + QSERDES_V4_DP_PHY_AUX_INTERRUPT_MASK);
2480 }
2481
2482 static void qmp_v4_configure_dp_tx(struct qmp_combo *qmp)
2483 {
2484         const struct qmp_phy_cfg *cfg = qmp->cfg;
2485
2486         /* Program default values before writing proper values */
2487         writel(0x27, qmp->dp_tx + cfg->regs[QPHY_TX_TX_DRV_LVL]);
2488         writel(0x27, qmp->dp_tx2 + cfg->regs[QPHY_TX_TX_DRV_LVL]);
2489
2490         writel(0x20, qmp->dp_tx + cfg->regs[QPHY_TX_TX_EMP_POST1_LVL]);
2491         writel(0x20, qmp->dp_tx2 + cfg->regs[QPHY_TX_TX_EMP_POST1_LVL]);
2492
2493         qmp_combo_configure_dp_swing(qmp);
2494 }
2495
2496 static int qmp_v456_configure_dp_phy(struct qmp_combo *qmp)
2497 {
2498         const struct qmp_phy_cfg *cfg = qmp->cfg;
2499         u32 status;
2500         int ret;
2501
2502         writel(0x0f, qmp->dp_dp_phy + QSERDES_DP_PHY_CFG_1);
2503
2504         qmp_combo_configure_dp_mode(qmp);
2505
2506         writel(0x13, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG1);
2507         writel(0xa4, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG2);
2508
2509         writel(0x05, qmp->dp_dp_phy + QSERDES_V4_DP_PHY_TX0_TX1_LANE_CTL);
2510         writel(0x05, qmp->dp_dp_phy + QSERDES_V4_DP_PHY_TX2_TX3_LANE_CTL);
2511
2512         ret = qmp_combo_configure_dp_clocks(qmp);
2513         if (ret)
2514                 return ret;
2515
2516         writel(0x01, qmp->dp_dp_phy + QSERDES_DP_PHY_CFG);
2517         writel(0x05, qmp->dp_dp_phy + QSERDES_DP_PHY_CFG);
2518         writel(0x01, qmp->dp_dp_phy + QSERDES_DP_PHY_CFG);
2519         writel(0x09, qmp->dp_dp_phy + QSERDES_DP_PHY_CFG);
2520
2521         writel(0x20, qmp->dp_serdes + cfg->regs[QPHY_COM_RESETSM_CNTRL]);
2522
2523         if (readl_poll_timeout(qmp->dp_serdes + cfg->regs[QPHY_COM_C_READY_STATUS],
2524                         status,
2525                         ((status & BIT(0)) > 0),
2526                         500,
2527                         10000))
2528                 return -ETIMEDOUT;
2529
2530         if (readl_poll_timeout(qmp->dp_serdes + cfg->regs[QPHY_COM_CMN_STATUS],
2531                         status,
2532                         ((status & BIT(0)) > 0),
2533                         500,
2534                         10000))
2535                 return -ETIMEDOUT;
2536
2537         if (readl_poll_timeout(qmp->dp_serdes + cfg->regs[QPHY_COM_CMN_STATUS],
2538                         status,
2539                         ((status & BIT(1)) > 0),
2540                         500,
2541                         10000))
2542                 return -ETIMEDOUT;
2543
2544         writel(0x19, qmp->dp_dp_phy + QSERDES_DP_PHY_CFG);
2545
2546         if (readl_poll_timeout(qmp->dp_dp_phy + cfg->regs[QPHY_DP_PHY_STATUS],
2547                         status,
2548                         ((status & BIT(0)) > 0),
2549                         500,
2550                         10000))
2551                 return -ETIMEDOUT;
2552
2553         if (readl_poll_timeout(qmp->dp_dp_phy + cfg->regs[QPHY_DP_PHY_STATUS],
2554                         status,
2555                         ((status & BIT(1)) > 0),
2556                         500,
2557                         10000))
2558                 return -ETIMEDOUT;
2559
2560         return 0;
2561 }
2562
2563 static int qmp_v4_configure_dp_phy(struct qmp_combo *qmp)
2564 {
2565         const struct qmp_phy_cfg *cfg = qmp->cfg;
2566         bool reverse = (qmp->orientation == TYPEC_ORIENTATION_REVERSE);
2567         const struct phy_configure_opts_dp *dp_opts = &qmp->dp_opts;
2568         u32 bias0_en, drvr0_en, bias1_en, drvr1_en;
2569         u32 status;
2570         int ret;
2571
2572         ret = qmp_v456_configure_dp_phy(qmp);
2573         if (ret < 0)
2574                 return ret;
2575
2576         /*
2577          * At least for 7nm DP PHY this has to be done after enabling link
2578          * clock.
2579          */
2580
2581         if (dp_opts->lanes == 1) {
2582                 bias0_en = reverse ? 0x3e : 0x15;
2583                 bias1_en = reverse ? 0x15 : 0x3e;
2584                 drvr0_en = reverse ? 0x13 : 0x10;
2585                 drvr1_en = reverse ? 0x10 : 0x13;
2586         } else if (dp_opts->lanes == 2) {
2587                 bias0_en = reverse ? 0x3f : 0x15;
2588                 bias1_en = reverse ? 0x15 : 0x3f;
2589                 drvr0_en = 0x10;
2590                 drvr1_en = 0x10;
2591         } else {
2592                 bias0_en = 0x3f;
2593                 bias1_en = 0x3f;
2594                 drvr0_en = 0x10;
2595                 drvr1_en = 0x10;
2596         }
2597
2598         writel(drvr0_en, qmp->dp_tx + cfg->regs[QPHY_TX_HIGHZ_DRVR_EN]);
2599         writel(bias0_en, qmp->dp_tx + cfg->regs[QPHY_TX_TRANSCEIVER_BIAS_EN]);
2600         writel(drvr1_en, qmp->dp_tx2 + cfg->regs[QPHY_TX_HIGHZ_DRVR_EN]);
2601         writel(bias1_en, qmp->dp_tx2 + cfg->regs[QPHY_TX_TRANSCEIVER_BIAS_EN]);
2602
2603         writel(0x18, qmp->dp_dp_phy + QSERDES_DP_PHY_CFG);
2604         udelay(2000);
2605         writel(0x19, qmp->dp_dp_phy + QSERDES_DP_PHY_CFG);
2606
2607         if (readl_poll_timeout(qmp->dp_dp_phy + cfg->regs[QPHY_DP_PHY_STATUS],
2608                         status,
2609                         ((status & BIT(1)) > 0),
2610                         500,
2611                         10000))
2612                 return -ETIMEDOUT;
2613
2614         writel(0x0a, qmp->dp_tx + cfg->regs[QPHY_TX_TX_POL_INV]);
2615         writel(0x0a, qmp->dp_tx2 + cfg->regs[QPHY_TX_TX_POL_INV]);
2616
2617         writel(0x27, qmp->dp_tx + cfg->regs[QPHY_TX_TX_DRV_LVL]);
2618         writel(0x27, qmp->dp_tx2 + cfg->regs[QPHY_TX_TX_DRV_LVL]);
2619
2620         writel(0x20, qmp->dp_tx + cfg->regs[QPHY_TX_TX_EMP_POST1_LVL]);
2621         writel(0x20, qmp->dp_tx2 + cfg->regs[QPHY_TX_TX_EMP_POST1_LVL]);
2622
2623         return 0;
2624 }
2625
2626 /*
2627  * We need to calibrate the aux setting here as many times
2628  * as the caller tries
2629  */
2630 static int qmp_v4_calibrate_dp_phy(struct qmp_combo *qmp)
2631 {
2632         static const u8 cfg1_settings[] = { 0x20, 0x13, 0x23, 0x1d };
2633         u8 val;
2634
2635         qmp->dp_aux_cfg++;
2636         qmp->dp_aux_cfg %= ARRAY_SIZE(cfg1_settings);
2637         val = cfg1_settings[qmp->dp_aux_cfg];
2638
2639         writel(val, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG1);
2640
2641         return 0;
2642 }
2643
2644 static int qmp_combo_dp_configure(struct phy *phy, union phy_configure_opts *opts)
2645 {
2646         const struct phy_configure_opts_dp *dp_opts = &opts->dp;
2647         struct qmp_combo *qmp = phy_get_drvdata(phy);
2648         const struct qmp_phy_cfg *cfg = qmp->cfg;
2649
2650         mutex_lock(&qmp->phy_mutex);
2651
2652         memcpy(&qmp->dp_opts, dp_opts, sizeof(*dp_opts));
2653         if (qmp->dp_opts.set_voltages) {
2654                 cfg->configure_dp_tx(qmp);
2655                 qmp->dp_opts.set_voltages = 0;
2656         }
2657
2658         mutex_unlock(&qmp->phy_mutex);
2659
2660         return 0;
2661 }
2662
2663 static int qmp_combo_dp_calibrate(struct phy *phy)
2664 {
2665         struct qmp_combo *qmp = phy_get_drvdata(phy);
2666         const struct qmp_phy_cfg *cfg = qmp->cfg;
2667         int ret = 0;
2668
2669         mutex_lock(&qmp->phy_mutex);
2670
2671         if (cfg->calibrate_dp_phy)
2672                 ret = cfg->calibrate_dp_phy(qmp);
2673
2674         mutex_unlock(&qmp->phy_mutex);
2675
2676         return ret;
2677 }
2678
2679 static int qmp_combo_com_init(struct qmp_combo *qmp, bool force)
2680 {
2681         const struct qmp_phy_cfg *cfg = qmp->cfg;
2682         void __iomem *com = qmp->com;
2683         int ret;
2684         u32 val;
2685
2686         if (!force && qmp->init_count++)
2687                 return 0;
2688
2689         ret = regulator_bulk_enable(cfg->num_vregs, qmp->vregs);
2690         if (ret) {
2691                 dev_err(qmp->dev, "failed to enable regulators, err=%d\n", ret);
2692                 goto err_decrement_count;
2693         }
2694
2695         ret = reset_control_bulk_assert(cfg->num_resets, qmp->resets);
2696         if (ret) {
2697                 dev_err(qmp->dev, "reset assert failed\n");
2698                 goto err_disable_regulators;
2699         }
2700
2701         ret = reset_control_bulk_deassert(cfg->num_resets, qmp->resets);
2702         if (ret) {
2703                 dev_err(qmp->dev, "reset deassert failed\n");
2704                 goto err_disable_regulators;
2705         }
2706
2707         ret = clk_bulk_prepare_enable(qmp->num_clks, qmp->clks);
2708         if (ret)
2709                 goto err_assert_reset;
2710
2711         qphy_setbits(com, QPHY_V3_DP_COM_POWER_DOWN_CTRL, SW_PWRDN);
2712
2713         /* override hardware control for reset of qmp phy */
2714         qphy_setbits(com, QPHY_V3_DP_COM_RESET_OVRD_CTRL,
2715                         SW_DPPHY_RESET_MUX | SW_DPPHY_RESET |
2716                         SW_USB3PHY_RESET_MUX | SW_USB3PHY_RESET);
2717
2718         /* Use software based port select and switch on typec orientation */
2719         val = SW_PORTSELECT_MUX;
2720         if (qmp->orientation == TYPEC_ORIENTATION_REVERSE)
2721                 val |= SW_PORTSELECT_VAL;
2722         writel(val, com + QPHY_V3_DP_COM_TYPEC_CTRL);
2723         writel(USB3_MODE | DP_MODE, com + QPHY_V3_DP_COM_PHY_MODE_CTRL);
2724
2725         /* bring both QMP USB and QMP DP PHYs PCS block out of reset */
2726         qphy_clrbits(com, QPHY_V3_DP_COM_RESET_OVRD_CTRL,
2727                         SW_DPPHY_RESET_MUX | SW_DPPHY_RESET |
2728                         SW_USB3PHY_RESET_MUX | SW_USB3PHY_RESET);
2729
2730         qphy_clrbits(com, QPHY_V3_DP_COM_SWI_CTRL, 0x03);
2731         qphy_clrbits(com, QPHY_V3_DP_COM_SW_RESET, SW_RESET);
2732
2733         qphy_setbits(qmp->pcs, cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL],
2734                         SW_PWRDN);
2735
2736         return 0;
2737
2738 err_assert_reset:
2739         reset_control_bulk_assert(cfg->num_resets, qmp->resets);
2740 err_disable_regulators:
2741         regulator_bulk_disable(cfg->num_vregs, qmp->vregs);
2742 err_decrement_count:
2743         qmp->init_count--;
2744
2745         return ret;
2746 }
2747
2748 static int qmp_combo_com_exit(struct qmp_combo *qmp, bool force)
2749 {
2750         const struct qmp_phy_cfg *cfg = qmp->cfg;
2751
2752         if (!force && --qmp->init_count)
2753                 return 0;
2754
2755         reset_control_bulk_assert(cfg->num_resets, qmp->resets);
2756
2757         clk_bulk_disable_unprepare(qmp->num_clks, qmp->clks);
2758
2759         regulator_bulk_disable(cfg->num_vregs, qmp->vregs);
2760
2761         return 0;
2762 }
2763
2764 static int qmp_combo_dp_init(struct phy *phy)
2765 {
2766         struct qmp_combo *qmp = phy_get_drvdata(phy);
2767         const struct qmp_phy_cfg *cfg = qmp->cfg;
2768         int ret;
2769
2770         mutex_lock(&qmp->phy_mutex);
2771
2772         ret = qmp_combo_com_init(qmp, false);
2773         if (ret)
2774                 goto out_unlock;
2775
2776         cfg->dp_aux_init(qmp);
2777
2778         qmp->dp_init_count++;
2779
2780 out_unlock:
2781         mutex_unlock(&qmp->phy_mutex);
2782         return ret;
2783 }
2784
2785 static int qmp_combo_dp_exit(struct phy *phy)
2786 {
2787         struct qmp_combo *qmp = phy_get_drvdata(phy);
2788
2789         mutex_lock(&qmp->phy_mutex);
2790
2791         qmp_combo_com_exit(qmp, false);
2792
2793         qmp->dp_init_count--;
2794
2795         mutex_unlock(&qmp->phy_mutex);
2796
2797         return 0;
2798 }
2799
2800 static int qmp_combo_dp_power_on(struct phy *phy)
2801 {
2802         struct qmp_combo *qmp = phy_get_drvdata(phy);
2803         const struct qmp_phy_cfg *cfg = qmp->cfg;
2804         void __iomem *tx = qmp->dp_tx;
2805         void __iomem *tx2 = qmp->dp_tx2;
2806
2807         mutex_lock(&qmp->phy_mutex);
2808
2809         qmp_combo_dp_serdes_init(qmp);
2810
2811         qmp_configure_lane(qmp->dev, tx, cfg->dp_tx_tbl, cfg->dp_tx_tbl_num, 1);
2812         qmp_configure_lane(qmp->dev, tx2, cfg->dp_tx_tbl, cfg->dp_tx_tbl_num, 2);
2813
2814         /* Configure special DP tx tunings */
2815         cfg->configure_dp_tx(qmp);
2816
2817         /* Configure link rate, swing, etc. */
2818         cfg->configure_dp_phy(qmp);
2819
2820         mutex_unlock(&qmp->phy_mutex);
2821
2822         return 0;
2823 }
2824
2825 static int qmp_combo_dp_power_off(struct phy *phy)
2826 {
2827         struct qmp_combo *qmp = phy_get_drvdata(phy);
2828
2829         mutex_lock(&qmp->phy_mutex);
2830
2831         /* Assert DP PHY power down */
2832         writel(DP_PHY_PD_CTL_PSR_PWRDN, qmp->dp_dp_phy + QSERDES_DP_PHY_PD_CTL);
2833
2834         mutex_unlock(&qmp->phy_mutex);
2835
2836         return 0;
2837 }
2838
2839 static int qmp_combo_usb_power_on(struct phy *phy)
2840 {
2841         struct qmp_combo *qmp = phy_get_drvdata(phy);
2842         const struct qmp_phy_cfg *cfg = qmp->cfg;
2843         void __iomem *serdes = qmp->serdes;
2844         void __iomem *tx = qmp->tx;
2845         void __iomem *rx = qmp->rx;
2846         void __iomem *tx2 = qmp->tx2;
2847         void __iomem *rx2 = qmp->rx2;
2848         void __iomem *pcs = qmp->pcs;
2849         void __iomem *pcs_usb = qmp->pcs_usb;
2850         void __iomem *status;
2851         unsigned int val;
2852         int ret;
2853
2854         qmp_configure(qmp->dev, serdes, cfg->serdes_tbl, cfg->serdes_tbl_num);
2855
2856         ret = clk_prepare_enable(qmp->pipe_clk);
2857         if (ret) {
2858                 dev_err(qmp->dev, "pipe_clk enable failed err=%d\n", ret);
2859                 return ret;
2860         }
2861
2862         /* Tx, Rx, and PCS configurations */
2863         qmp_configure_lane(qmp->dev, tx, cfg->tx_tbl, cfg->tx_tbl_num, 1);
2864         qmp_configure_lane(qmp->dev, tx2, cfg->tx_tbl, cfg->tx_tbl_num, 2);
2865
2866         qmp_configure_lane(qmp->dev, rx, cfg->rx_tbl, cfg->rx_tbl_num, 1);
2867         qmp_configure_lane(qmp->dev, rx2, cfg->rx_tbl, cfg->rx_tbl_num, 2);
2868
2869         qmp_configure(qmp->dev, pcs, cfg->pcs_tbl, cfg->pcs_tbl_num);
2870
2871         if (pcs_usb)
2872                 qmp_configure(qmp->dev, pcs_usb, cfg->pcs_usb_tbl,
2873                               cfg->pcs_usb_tbl_num);
2874
2875         if (cfg->has_pwrdn_delay)
2876                 usleep_range(10, 20);
2877
2878         /* Pull PHY out of reset state */
2879         qphy_clrbits(pcs, cfg->regs[QPHY_SW_RESET], SW_RESET);
2880
2881         /* start SerDes and Phy-Coding-Sublayer */
2882         qphy_setbits(pcs, cfg->regs[QPHY_START_CTRL], SERDES_START | PCS_START);
2883
2884         status = pcs + cfg->regs[QPHY_PCS_STATUS];
2885         ret = readl_poll_timeout(status, val, !(val & PHYSTATUS), 200,
2886                         PHY_INIT_COMPLETE_TIMEOUT);
2887         if (ret) {
2888                 dev_err(qmp->dev, "phy initialization timed-out\n");
2889                 goto err_disable_pipe_clk;
2890         }
2891
2892         return 0;
2893
2894 err_disable_pipe_clk:
2895         clk_disable_unprepare(qmp->pipe_clk);
2896
2897         return ret;
2898 }
2899
2900 static int qmp_combo_usb_power_off(struct phy *phy)
2901 {
2902         struct qmp_combo *qmp = phy_get_drvdata(phy);
2903         const struct qmp_phy_cfg *cfg = qmp->cfg;
2904
2905         clk_disable_unprepare(qmp->pipe_clk);
2906
2907         /* PHY reset */
2908         qphy_setbits(qmp->pcs, cfg->regs[QPHY_SW_RESET], SW_RESET);
2909
2910         /* stop SerDes and Phy-Coding-Sublayer */
2911         qphy_clrbits(qmp->pcs, cfg->regs[QPHY_START_CTRL],
2912                         SERDES_START | PCS_START);
2913
2914         /* Put PHY into POWER DOWN state: active low */
2915         qphy_clrbits(qmp->pcs, cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL],
2916                         SW_PWRDN);
2917
2918         return 0;
2919 }
2920
2921 static int qmp_combo_usb_init(struct phy *phy)
2922 {
2923         struct qmp_combo *qmp = phy_get_drvdata(phy);
2924         int ret;
2925
2926         mutex_lock(&qmp->phy_mutex);
2927         ret = qmp_combo_com_init(qmp, false);
2928         if (ret)
2929                 goto out_unlock;
2930
2931         ret = qmp_combo_usb_power_on(phy);
2932         if (ret) {
2933                 qmp_combo_com_exit(qmp, false);
2934                 goto out_unlock;
2935         }
2936
2937         qmp->usb_init_count++;
2938
2939 out_unlock:
2940         mutex_unlock(&qmp->phy_mutex);
2941         return ret;
2942 }
2943
2944 static int qmp_combo_usb_exit(struct phy *phy)
2945 {
2946         struct qmp_combo *qmp = phy_get_drvdata(phy);
2947         int ret;
2948
2949         mutex_lock(&qmp->phy_mutex);
2950         ret = qmp_combo_usb_power_off(phy);
2951         if (ret)
2952                 goto out_unlock;
2953
2954         ret = qmp_combo_com_exit(qmp, false);
2955         if (ret)
2956                 goto out_unlock;
2957
2958         qmp->usb_init_count--;
2959
2960 out_unlock:
2961         mutex_unlock(&qmp->phy_mutex);
2962         return ret;
2963 }
2964
2965 static int qmp_combo_usb_set_mode(struct phy *phy, enum phy_mode mode, int submode)
2966 {
2967         struct qmp_combo *qmp = phy_get_drvdata(phy);
2968
2969         qmp->mode = mode;
2970
2971         return 0;
2972 }
2973
2974 static const struct phy_ops qmp_combo_usb_phy_ops = {
2975         .init           = qmp_combo_usb_init,
2976         .exit           = qmp_combo_usb_exit,
2977         .set_mode       = qmp_combo_usb_set_mode,
2978         .owner          = THIS_MODULE,
2979 };
2980
2981 static const struct phy_ops qmp_combo_dp_phy_ops = {
2982         .init           = qmp_combo_dp_init,
2983         .configure      = qmp_combo_dp_configure,
2984         .power_on       = qmp_combo_dp_power_on,
2985         .calibrate      = qmp_combo_dp_calibrate,
2986         .power_off      = qmp_combo_dp_power_off,
2987         .exit           = qmp_combo_dp_exit,
2988         .owner          = THIS_MODULE,
2989 };
2990
2991 static void qmp_combo_enable_autonomous_mode(struct qmp_combo *qmp)
2992 {
2993         const struct qmp_phy_cfg *cfg = qmp->cfg;
2994         void __iomem *pcs_usb = qmp->pcs_usb ?: qmp->pcs;
2995         void __iomem *pcs_misc = qmp->pcs_misc;
2996         u32 intr_mask;
2997
2998         if (qmp->mode == PHY_MODE_USB_HOST_SS ||
2999             qmp->mode == PHY_MODE_USB_DEVICE_SS)
3000                 intr_mask = ARCVR_DTCT_EN | ALFPS_DTCT_EN;
3001         else
3002                 intr_mask = ARCVR_DTCT_EN | ARCVR_DTCT_EVENT_SEL;
3003
3004         /* Clear any pending interrupts status */
3005         qphy_setbits(pcs_usb, cfg->regs[QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR], IRQ_CLEAR);
3006         /* Writing 1 followed by 0 clears the interrupt */
3007         qphy_clrbits(pcs_usb, cfg->regs[QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR], IRQ_CLEAR);
3008
3009         qphy_clrbits(pcs_usb, cfg->regs[QPHY_PCS_AUTONOMOUS_MODE_CTRL],
3010                      ARCVR_DTCT_EN | ALFPS_DTCT_EN | ARCVR_DTCT_EVENT_SEL);
3011
3012         /* Enable required PHY autonomous mode interrupts */
3013         qphy_setbits(pcs_usb, cfg->regs[QPHY_PCS_AUTONOMOUS_MODE_CTRL], intr_mask);
3014
3015         /* Enable i/o clamp_n for autonomous mode */
3016         if (pcs_misc)
3017                 qphy_clrbits(pcs_misc, QPHY_V3_PCS_MISC_CLAMP_ENABLE, CLAMP_EN);
3018 }
3019
3020 static void qmp_combo_disable_autonomous_mode(struct qmp_combo *qmp)
3021 {
3022         const struct qmp_phy_cfg *cfg = qmp->cfg;
3023         void __iomem *pcs_usb = qmp->pcs_usb ?: qmp->pcs;
3024         void __iomem *pcs_misc = qmp->pcs_misc;
3025
3026         /* Disable i/o clamp_n on resume for normal mode */
3027         if (pcs_misc)
3028                 qphy_setbits(pcs_misc, QPHY_V3_PCS_MISC_CLAMP_ENABLE, CLAMP_EN);
3029
3030         qphy_clrbits(pcs_usb, cfg->regs[QPHY_PCS_AUTONOMOUS_MODE_CTRL],
3031                      ARCVR_DTCT_EN | ARCVR_DTCT_EVENT_SEL | ALFPS_DTCT_EN);
3032
3033         qphy_setbits(pcs_usb, cfg->regs[QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR], IRQ_CLEAR);
3034         /* Writing 1 followed by 0 clears the interrupt */
3035         qphy_clrbits(pcs_usb, cfg->regs[QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR], IRQ_CLEAR);
3036 }
3037
3038 static int __maybe_unused qmp_combo_runtime_suspend(struct device *dev)
3039 {
3040         struct qmp_combo *qmp = dev_get_drvdata(dev);
3041
3042         dev_vdbg(dev, "Suspending QMP phy, mode:%d\n", qmp->mode);
3043
3044         if (!qmp->init_count) {
3045                 dev_vdbg(dev, "PHY not initialized, bailing out\n");
3046                 return 0;
3047         }
3048
3049         qmp_combo_enable_autonomous_mode(qmp);
3050
3051         clk_disable_unprepare(qmp->pipe_clk);
3052         clk_bulk_disable_unprepare(qmp->num_clks, qmp->clks);
3053
3054         return 0;
3055 }
3056
3057 static int __maybe_unused qmp_combo_runtime_resume(struct device *dev)
3058 {
3059         struct qmp_combo *qmp = dev_get_drvdata(dev);
3060         int ret = 0;
3061
3062         dev_vdbg(dev, "Resuming QMP phy, mode:%d\n", qmp->mode);
3063
3064         if (!qmp->init_count) {
3065                 dev_vdbg(dev, "PHY not initialized, bailing out\n");
3066                 return 0;
3067         }
3068
3069         ret = clk_bulk_prepare_enable(qmp->num_clks, qmp->clks);
3070         if (ret)
3071                 return ret;
3072
3073         ret = clk_prepare_enable(qmp->pipe_clk);
3074         if (ret) {
3075                 dev_err(dev, "pipe_clk enable failed, err=%d\n", ret);
3076                 clk_bulk_disable_unprepare(qmp->num_clks, qmp->clks);
3077                 return ret;
3078         }
3079
3080         qmp_combo_disable_autonomous_mode(qmp);
3081
3082         return 0;
3083 }
3084
3085 static const struct dev_pm_ops qmp_combo_pm_ops = {
3086         SET_RUNTIME_PM_OPS(qmp_combo_runtime_suspend,
3087                            qmp_combo_runtime_resume, NULL)
3088 };
3089
3090 static int qmp_combo_vreg_init(struct qmp_combo *qmp)
3091 {
3092         const struct qmp_phy_cfg *cfg = qmp->cfg;
3093         struct device *dev = qmp->dev;
3094         int num = cfg->num_vregs;
3095         int ret, i;
3096
3097         qmp->vregs = devm_kcalloc(dev, num, sizeof(*qmp->vregs), GFP_KERNEL);
3098         if (!qmp->vregs)
3099                 return -ENOMEM;
3100
3101         for (i = 0; i < num; i++)
3102                 qmp->vregs[i].supply = cfg->vreg_list[i].name;
3103
3104         ret = devm_regulator_bulk_get(dev, num, qmp->vregs);
3105         if (ret) {
3106                 dev_err(dev, "failed at devm_regulator_bulk_get\n");
3107                 return ret;
3108         }
3109
3110         for (i = 0; i < num; i++) {
3111                 ret = regulator_set_load(qmp->vregs[i].consumer,
3112                                         cfg->vreg_list[i].enable_load);
3113                 if (ret) {
3114                         dev_err(dev, "failed to set load at %s\n",
3115                                 qmp->vregs[i].supply);
3116                         return ret;
3117                 }
3118         }
3119
3120         return 0;
3121 }
3122
3123 static int qmp_combo_reset_init(struct qmp_combo *qmp)
3124 {
3125         const struct qmp_phy_cfg *cfg = qmp->cfg;
3126         struct device *dev = qmp->dev;
3127         int i;
3128         int ret;
3129
3130         qmp->resets = devm_kcalloc(dev, cfg->num_resets,
3131                                    sizeof(*qmp->resets), GFP_KERNEL);
3132         if (!qmp->resets)
3133                 return -ENOMEM;
3134
3135         for (i = 0; i < cfg->num_resets; i++)
3136                 qmp->resets[i].id = cfg->reset_list[i];
3137
3138         ret = devm_reset_control_bulk_get_exclusive(dev, cfg->num_resets, qmp->resets);
3139         if (ret)
3140                 return dev_err_probe(dev, ret, "failed to get resets\n");
3141
3142         return 0;
3143 }
3144
3145 static int qmp_combo_clk_init(struct qmp_combo *qmp)
3146 {
3147         struct device *dev = qmp->dev;
3148         int num = ARRAY_SIZE(qmp_combo_phy_clk_l);
3149         int i;
3150
3151         qmp->clks = devm_kcalloc(dev, num, sizeof(*qmp->clks), GFP_KERNEL);
3152         if (!qmp->clks)
3153                 return -ENOMEM;
3154
3155         for (i = 0; i < num; i++)
3156                 qmp->clks[i].id = qmp_combo_phy_clk_l[i];
3157
3158         qmp->num_clks = num;
3159
3160         return devm_clk_bulk_get_optional(dev, num, qmp->clks);
3161 }
3162
3163 static void phy_clk_release_provider(void *res)
3164 {
3165         of_clk_del_provider(res);
3166 }
3167
3168 /*
3169  * Register a fixed rate pipe clock.
3170  *
3171  * The <s>_pipe_clksrc generated by PHY goes to the GCC that gate
3172  * controls it. The <s>_pipe_clk coming out of the GCC is requested
3173  * by the PHY driver for its operations.
3174  * We register the <s>_pipe_clksrc here. The gcc driver takes care
3175  * of assigning this <s>_pipe_clksrc as parent to <s>_pipe_clk.
3176  * Below picture shows this relationship.
3177  *
3178  *         +---------------+
3179  *         |   PHY block   |<<---------------------------------------+
3180  *         |               |                                         |
3181  *         |   +-------+   |                   +-----+               |
3182  *   I/P---^-->|  PLL  |---^--->pipe_clksrc--->| GCC |--->pipe_clk---+
3183  *    clk  |   +-------+   |                   +-----+
3184  *         +---------------+
3185  */
3186 static int phy_pipe_clk_register(struct qmp_combo *qmp, struct device_node *np)
3187 {
3188         struct clk_fixed_rate *fixed = &qmp->pipe_clk_fixed;
3189         struct clk_init_data init = { };
3190         char name[64];
3191
3192         snprintf(name, sizeof(name), "%s::pipe_clk", dev_name(qmp->dev));
3193         init.name = name;
3194         init.ops = &clk_fixed_rate_ops;
3195
3196         /* controllers using QMP phys use 125MHz pipe clock interface */
3197         fixed->fixed_rate = 125000000;
3198         fixed->hw.init = &init;
3199
3200         return devm_clk_hw_register(qmp->dev, &fixed->hw);
3201 }
3202
3203 /*
3204  * Display Port PLL driver block diagram for branch clocks
3205  *
3206  *              +------------------------------+
3207  *              |         DP_VCO_CLK           |
3208  *              |                              |
3209  *              |    +-------------------+     |
3210  *              |    |   (DP PLL/VCO)    |     |
3211  *              |    +---------+---------+     |
3212  *              |              v               |
3213  *              |   +----------+-----------+   |
3214  *              |   | hsclk_divsel_clk_src |   |
3215  *              |   +----------+-----------+   |
3216  *              +------------------------------+
3217  *                              |
3218  *          +---------<---------v------------>----------+
3219  *          |                                           |
3220  * +--------v----------------+                          |
3221  * |    dp_phy_pll_link_clk  |                          |
3222  * |     link_clk            |                          |
3223  * +--------+----------------+                          |
3224  *          |                                           |
3225  *          |                                           |
3226  *          v                                           v
3227  * Input to DISPCC block                                |
3228  * for link clk, crypto clk                             |
3229  * and interface clock                                  |
3230  *                                                      |
3231  *                                                      |
3232  *      +--------<------------+-----------------+---<---+
3233  *      |                     |                 |
3234  * +----v---------+  +--------v-----+  +--------v------+
3235  * | vco_divided  |  | vco_divided  |  | vco_divided   |
3236  * |    _clk_src  |  |    _clk_src  |  |    _clk_src   |
3237  * |              |  |              |  |               |
3238  * |divsel_six    |  |  divsel_two  |  |  divsel_four  |
3239  * +-------+------+  +-----+--------+  +--------+------+
3240  *         |                 |                  |
3241  *         v---->----------v-------------<------v
3242  *                         |
3243  *              +----------+-----------------+
3244  *              |   dp_phy_pll_vco_div_clk   |
3245  *              +---------+------------------+
3246  *                        |
3247  *                        v
3248  *              Input to DISPCC block
3249  *              for DP pixel clock
3250  *
3251  */
3252 static int qmp_dp_pixel_clk_determine_rate(struct clk_hw *hw, struct clk_rate_request *req)
3253 {
3254         switch (req->rate) {
3255         case 1620000000UL / 2:
3256         case 2700000000UL / 2:
3257         /* 5.4 and 8.1 GHz are same link rate as 2.7GHz, i.e. div 4 and div 6 */
3258                 return 0;
3259         default:
3260                 return -EINVAL;
3261         }
3262 }
3263
3264 static unsigned long qmp_dp_pixel_clk_recalc_rate(struct clk_hw *hw, unsigned long parent_rate)
3265 {
3266         const struct qmp_combo *qmp;
3267         const struct phy_configure_opts_dp *dp_opts;
3268
3269         qmp = container_of(hw, struct qmp_combo, dp_pixel_hw);
3270         dp_opts = &qmp->dp_opts;
3271
3272         switch (dp_opts->link_rate) {
3273         case 1620:
3274                 return 1620000000UL / 2;
3275         case 2700:
3276                 return 2700000000UL / 2;
3277         case 5400:
3278                 return 5400000000UL / 4;
3279         case 8100:
3280                 return 8100000000UL / 6;
3281         default:
3282                 return 0;
3283         }
3284 }
3285
3286 static const struct clk_ops qmp_dp_pixel_clk_ops = {
3287         .determine_rate = qmp_dp_pixel_clk_determine_rate,
3288         .recalc_rate    = qmp_dp_pixel_clk_recalc_rate,
3289 };
3290
3291 static int qmp_dp_link_clk_determine_rate(struct clk_hw *hw, struct clk_rate_request *req)
3292 {
3293         switch (req->rate) {
3294         case 162000000:
3295         case 270000000:
3296         case 540000000:
3297         case 810000000:
3298                 return 0;
3299         default:
3300                 return -EINVAL;
3301         }
3302 }
3303
3304 static unsigned long qmp_dp_link_clk_recalc_rate(struct clk_hw *hw, unsigned long parent_rate)
3305 {
3306         const struct qmp_combo *qmp;
3307         const struct phy_configure_opts_dp *dp_opts;
3308
3309         qmp = container_of(hw, struct qmp_combo, dp_link_hw);
3310         dp_opts = &qmp->dp_opts;
3311
3312         switch (dp_opts->link_rate) {
3313         case 1620:
3314         case 2700:
3315         case 5400:
3316         case 8100:
3317                 return dp_opts->link_rate * 100000;
3318         default:
3319                 return 0;
3320         }
3321 }
3322
3323 static const struct clk_ops qmp_dp_link_clk_ops = {
3324         .determine_rate = qmp_dp_link_clk_determine_rate,
3325         .recalc_rate    = qmp_dp_link_clk_recalc_rate,
3326 };
3327
3328 static struct clk_hw *qmp_dp_clks_hw_get(struct of_phandle_args *clkspec, void *data)
3329 {
3330         struct qmp_combo *qmp = data;
3331         unsigned int idx = clkspec->args[0];
3332
3333         if (idx >= 2) {
3334                 pr_err("%s: invalid index %u\n", __func__, idx);
3335                 return ERR_PTR(-EINVAL);
3336         }
3337
3338         if (idx == 0)
3339                 return &qmp->dp_link_hw;
3340
3341         return &qmp->dp_pixel_hw;
3342 }
3343
3344 static int phy_dp_clks_register(struct qmp_combo *qmp, struct device_node *np)
3345 {
3346         struct clk_init_data init = { };
3347         char name[64];
3348         int ret;
3349
3350         snprintf(name, sizeof(name), "%s::link_clk", dev_name(qmp->dev));
3351         init.ops = &qmp_dp_link_clk_ops;
3352         init.name = name;
3353         qmp->dp_link_hw.init = &init;
3354         ret = devm_clk_hw_register(qmp->dev, &qmp->dp_link_hw);
3355         if (ret)
3356                 return ret;
3357
3358         snprintf(name, sizeof(name), "%s::vco_div_clk", dev_name(qmp->dev));
3359         init.ops = &qmp_dp_pixel_clk_ops;
3360         init.name = name;
3361         qmp->dp_pixel_hw.init = &init;
3362         ret = devm_clk_hw_register(qmp->dev, &qmp->dp_pixel_hw);
3363         if (ret)
3364                 return ret;
3365
3366         return 0;
3367 }
3368
3369 static struct clk_hw *qmp_combo_clk_hw_get(struct of_phandle_args *clkspec, void *data)
3370 {
3371         struct qmp_combo *qmp = data;
3372
3373         switch (clkspec->args[0]) {
3374         case QMP_USB43DP_USB3_PIPE_CLK:
3375                 return &qmp->pipe_clk_fixed.hw;
3376         case QMP_USB43DP_DP_LINK_CLK:
3377                 return &qmp->dp_link_hw;
3378         case QMP_USB43DP_DP_VCO_DIV_CLK:
3379                 return &qmp->dp_pixel_hw;
3380         }
3381
3382         return ERR_PTR(-EINVAL);
3383 }
3384
3385 static int qmp_combo_register_clocks(struct qmp_combo *qmp, struct device_node *usb_np,
3386                                         struct device_node *dp_np)
3387 {
3388         int ret;
3389
3390         ret = phy_pipe_clk_register(qmp, usb_np);
3391         if (ret)
3392                 return ret;
3393
3394         ret = phy_dp_clks_register(qmp, dp_np);
3395         if (ret)
3396                 return ret;
3397
3398         /*
3399          * Register a single provider for bindings without child nodes.
3400          */
3401         if (usb_np == qmp->dev->of_node)
3402                 return devm_of_clk_add_hw_provider(qmp->dev, qmp_combo_clk_hw_get, qmp);
3403
3404         /*
3405          * Register multiple providers for legacy bindings with child nodes.
3406          */
3407         ret = of_clk_add_hw_provider(usb_np, of_clk_hw_simple_get,
3408                                         &qmp->pipe_clk_fixed.hw);
3409         if (ret)
3410                 return ret;
3411
3412         /*
3413          * Roll a devm action because the clock provider is the child node, but
3414          * the child node is not actually a device.
3415          */
3416         ret = devm_add_action_or_reset(qmp->dev, phy_clk_release_provider, usb_np);
3417         if (ret)
3418                 return ret;
3419
3420         ret = of_clk_add_hw_provider(dp_np, qmp_dp_clks_hw_get, qmp);
3421         if (ret)
3422                 return ret;
3423
3424         return devm_add_action_or_reset(qmp->dev, phy_clk_release_provider, dp_np);
3425 }
3426
3427 #if IS_ENABLED(CONFIG_TYPEC)
3428 static int qmp_combo_typec_switch_set(struct typec_switch_dev *sw,
3429                                       enum typec_orientation orientation)
3430 {
3431         struct qmp_combo *qmp = typec_switch_get_drvdata(sw);
3432         const struct qmp_phy_cfg *cfg = qmp->cfg;
3433
3434         if (orientation == qmp->orientation || orientation == TYPEC_ORIENTATION_NONE)
3435                 return 0;
3436
3437         mutex_lock(&qmp->phy_mutex);
3438         qmp->orientation = orientation;
3439
3440         if (qmp->init_count) {
3441                 if (qmp->usb_init_count)
3442                         qmp_combo_usb_power_off(qmp->usb_phy);
3443                 qmp_combo_com_exit(qmp, true);
3444
3445                 qmp_combo_com_init(qmp, true);
3446                 if (qmp->usb_init_count)
3447                         qmp_combo_usb_power_on(qmp->usb_phy);
3448                 if (qmp->dp_init_count)
3449                         cfg->dp_aux_init(qmp);
3450         }
3451         mutex_unlock(&qmp->phy_mutex);
3452
3453         return 0;
3454 }
3455
3456 static void qmp_combo_typec_unregister(void *data)
3457 {
3458         struct qmp_combo *qmp = data;
3459
3460         typec_switch_unregister(qmp->sw);
3461 }
3462
3463 static int qmp_combo_typec_switch_register(struct qmp_combo *qmp)
3464 {
3465         struct typec_switch_desc sw_desc = {};
3466         struct device *dev = qmp->dev;
3467
3468         sw_desc.drvdata = qmp;
3469         sw_desc.fwnode = dev->fwnode;
3470         sw_desc.set = qmp_combo_typec_switch_set;
3471         qmp->sw = typec_switch_register(dev, &sw_desc);
3472         if (IS_ERR(qmp->sw)) {
3473                 dev_err(dev, "Unable to register typec switch: %pe\n", qmp->sw);
3474                 return PTR_ERR(qmp->sw);
3475         }
3476
3477         return devm_add_action_or_reset(dev, qmp_combo_typec_unregister, qmp);
3478 }
3479 #else
3480 static int qmp_combo_typec_switch_register(struct qmp_combo *qmp)
3481 {
3482         return 0;
3483 }
3484 #endif
3485
3486 static int qmp_combo_parse_dt_legacy_dp(struct qmp_combo *qmp, struct device_node *np)
3487 {
3488         struct device *dev = qmp->dev;
3489
3490         /*
3491          * Get memory resources from the DP child node:
3492          * Resources are indexed as: tx -> 0; rx -> 1; pcs -> 2;
3493          * tx2 -> 3; rx2 -> 4
3494          *
3495          * Note that only tx/tx2 and pcs (dp_phy) are used by the DP
3496          * implementation.
3497          */
3498         qmp->dp_tx = devm_of_iomap(dev, np, 0, NULL);
3499         if (IS_ERR(qmp->dp_tx))
3500                 return PTR_ERR(qmp->dp_tx);
3501
3502         qmp->dp_dp_phy = devm_of_iomap(dev, np, 2, NULL);
3503         if (IS_ERR(qmp->dp_dp_phy))
3504                 return PTR_ERR(qmp->dp_dp_phy);
3505
3506         qmp->dp_tx2 = devm_of_iomap(dev, np, 3, NULL);
3507         if (IS_ERR(qmp->dp_tx2))
3508                 return PTR_ERR(qmp->dp_tx2);
3509
3510         return 0;
3511 }
3512
3513 static int qmp_combo_parse_dt_legacy_usb(struct qmp_combo *qmp, struct device_node *np)
3514 {
3515         const struct qmp_phy_cfg *cfg = qmp->cfg;
3516         struct device *dev = qmp->dev;
3517
3518         /*
3519          * Get memory resources from the USB child node:
3520          * Resources are indexed as: tx -> 0; rx -> 1; pcs -> 2;
3521          * tx2 -> 3; rx2 -> 4; pcs_misc (optional) -> 5
3522          */
3523         qmp->tx = devm_of_iomap(dev, np, 0, NULL);
3524         if (IS_ERR(qmp->tx))
3525                 return PTR_ERR(qmp->tx);
3526
3527         qmp->rx = devm_of_iomap(dev, np, 1, NULL);
3528         if (IS_ERR(qmp->rx))
3529                 return PTR_ERR(qmp->rx);
3530
3531         qmp->pcs = devm_of_iomap(dev, np, 2, NULL);
3532         if (IS_ERR(qmp->pcs))
3533                 return PTR_ERR(qmp->pcs);
3534
3535         if (cfg->pcs_usb_offset)
3536                 qmp->pcs_usb = qmp->pcs + cfg->pcs_usb_offset;
3537
3538         qmp->tx2 = devm_of_iomap(dev, np, 3, NULL);
3539         if (IS_ERR(qmp->tx2))
3540                 return PTR_ERR(qmp->tx2);
3541
3542         qmp->rx2 = devm_of_iomap(dev, np, 4, NULL);
3543         if (IS_ERR(qmp->rx2))
3544                 return PTR_ERR(qmp->rx2);
3545
3546         qmp->pcs_misc = devm_of_iomap(dev, np, 5, NULL);
3547         if (IS_ERR(qmp->pcs_misc)) {
3548                 dev_vdbg(dev, "PHY pcs_misc-reg not used\n");
3549                 qmp->pcs_misc = NULL;
3550         }
3551
3552         qmp->pipe_clk = devm_get_clk_from_child(dev, np, NULL);
3553         if (IS_ERR(qmp->pipe_clk)) {
3554                 return dev_err_probe(dev, PTR_ERR(qmp->pipe_clk),
3555                                      "failed to get pipe clock\n");
3556         }
3557
3558         return 0;
3559 }
3560
3561 static int qmp_combo_parse_dt_legacy(struct qmp_combo *qmp, struct device_node *usb_np,
3562                                         struct device_node *dp_np)
3563 {
3564         struct platform_device *pdev = to_platform_device(qmp->dev);
3565         int ret;
3566
3567         qmp->serdes = devm_platform_ioremap_resource(pdev, 0);
3568         if (IS_ERR(qmp->serdes))
3569                 return PTR_ERR(qmp->serdes);
3570
3571         qmp->com = devm_platform_ioremap_resource(pdev, 1);
3572         if (IS_ERR(qmp->com))
3573                 return PTR_ERR(qmp->com);
3574
3575         qmp->dp_serdes = devm_platform_ioremap_resource(pdev, 2);
3576         if (IS_ERR(qmp->dp_serdes))
3577                 return PTR_ERR(qmp->dp_serdes);
3578
3579         ret = qmp_combo_parse_dt_legacy_usb(qmp, usb_np);
3580         if (ret)
3581                 return ret;
3582
3583         ret = qmp_combo_parse_dt_legacy_dp(qmp, dp_np);
3584         if (ret)
3585                 return ret;
3586
3587         ret = devm_clk_bulk_get_all(qmp->dev, &qmp->clks);
3588         if (ret < 0)
3589                 return ret;
3590
3591         qmp->num_clks = ret;
3592
3593         return 0;
3594 }
3595
3596 static int qmp_combo_parse_dt(struct qmp_combo *qmp)
3597 {
3598         struct platform_device *pdev = to_platform_device(qmp->dev);
3599         const struct qmp_phy_cfg *cfg = qmp->cfg;
3600         const struct qmp_combo_offsets *offs = cfg->offsets;
3601         struct device *dev = qmp->dev;
3602         void __iomem *base;
3603         int ret;
3604
3605         if (!offs)
3606                 return -EINVAL;
3607
3608         base = devm_platform_ioremap_resource(pdev, 0);
3609         if (IS_ERR(base))
3610                 return PTR_ERR(base);
3611
3612         qmp->com = base + offs->com;
3613         qmp->tx = base + offs->txa;
3614         qmp->rx = base + offs->rxa;
3615         qmp->tx2 = base + offs->txb;
3616         qmp->rx2 = base + offs->rxb;
3617
3618         qmp->serdes = base + offs->usb3_serdes;
3619         qmp->pcs_misc = base + offs->usb3_pcs_misc;
3620         qmp->pcs = base + offs->usb3_pcs;
3621         qmp->pcs_usb = base + offs->usb3_pcs_usb;
3622
3623         qmp->dp_serdes = base + offs->dp_serdes;
3624         if (offs->dp_txa) {
3625                 qmp->dp_tx = base + offs->dp_txa;
3626                 qmp->dp_tx2 = base + offs->dp_txb;
3627         } else {
3628                 qmp->dp_tx = base + offs->txa;
3629                 qmp->dp_tx2 = base + offs->txb;
3630         }
3631         qmp->dp_dp_phy = base + offs->dp_dp_phy;
3632
3633         ret = qmp_combo_clk_init(qmp);
3634         if (ret)
3635                 return ret;
3636
3637         qmp->pipe_clk = devm_clk_get(dev, "usb3_pipe");
3638         if (IS_ERR(qmp->pipe_clk)) {
3639                 return dev_err_probe(dev, PTR_ERR(qmp->pipe_clk),
3640                                 "failed to get usb3_pipe clock\n");
3641         }
3642
3643         return 0;
3644 }
3645
3646 static struct phy *qmp_combo_phy_xlate(struct device *dev, const struct of_phandle_args *args)
3647 {
3648         struct qmp_combo *qmp = dev_get_drvdata(dev);
3649
3650         if (args->args_count == 0)
3651                 return ERR_PTR(-EINVAL);
3652
3653         switch (args->args[0]) {
3654         case QMP_USB43DP_USB3_PHY:
3655                 return qmp->usb_phy;
3656         case QMP_USB43DP_DP_PHY:
3657                 return qmp->dp_phy;
3658         }
3659
3660         return ERR_PTR(-EINVAL);
3661 }
3662
3663 static int qmp_combo_probe(struct platform_device *pdev)
3664 {
3665         struct qmp_combo *qmp;
3666         struct device *dev = &pdev->dev;
3667         struct device_node *dp_np, *usb_np;
3668         struct phy_provider *phy_provider;
3669         int ret;
3670
3671         qmp = devm_kzalloc(dev, sizeof(*qmp), GFP_KERNEL);
3672         if (!qmp)
3673                 return -ENOMEM;
3674
3675         qmp->dev = dev;
3676         dev_set_drvdata(dev, qmp);
3677
3678         qmp->orientation = TYPEC_ORIENTATION_NORMAL;
3679
3680         qmp->cfg = of_device_get_match_data(dev);
3681         if (!qmp->cfg)
3682                 return -EINVAL;
3683
3684         mutex_init(&qmp->phy_mutex);
3685
3686         ret = qmp_combo_reset_init(qmp);
3687         if (ret)
3688                 return ret;
3689
3690         ret = qmp_combo_vreg_init(qmp);
3691         if (ret)
3692                 return ret;
3693
3694         /* Check for legacy binding with child nodes. */
3695         usb_np = of_get_child_by_name(dev->of_node, "usb3-phy");
3696         if (usb_np) {
3697                 dp_np = of_get_child_by_name(dev->of_node, "dp-phy");
3698                 if (!dp_np) {
3699                         of_node_put(usb_np);
3700                         return -EINVAL;
3701                 }
3702
3703                 ret = qmp_combo_parse_dt_legacy(qmp, usb_np, dp_np);
3704         } else {
3705                 usb_np = of_node_get(dev->of_node);
3706                 dp_np = of_node_get(dev->of_node);
3707
3708                 ret = qmp_combo_parse_dt(qmp);
3709         }
3710         if (ret)
3711                 goto err_node_put;
3712
3713         ret = qmp_combo_typec_switch_register(qmp);
3714         if (ret)
3715                 goto err_node_put;
3716
3717         ret = drm_aux_bridge_register(dev);
3718         if (ret)
3719                 goto err_node_put;
3720
3721         pm_runtime_set_active(dev);
3722         ret = devm_pm_runtime_enable(dev);
3723         if (ret)
3724                 goto err_node_put;
3725         /*
3726          * Prevent runtime pm from being ON by default. Users can enable
3727          * it using power/control in sysfs.
3728          */
3729         pm_runtime_forbid(dev);
3730
3731         ret = qmp_combo_register_clocks(qmp, usb_np, dp_np);
3732         if (ret)
3733                 goto err_node_put;
3734
3735         qmp->usb_phy = devm_phy_create(dev, usb_np, &qmp_combo_usb_phy_ops);
3736         if (IS_ERR(qmp->usb_phy)) {
3737                 ret = PTR_ERR(qmp->usb_phy);
3738                 dev_err(dev, "failed to create USB PHY: %d\n", ret);
3739                 goto err_node_put;
3740         }
3741
3742         phy_set_drvdata(qmp->usb_phy, qmp);
3743
3744         qmp->dp_phy = devm_phy_create(dev, dp_np, &qmp_combo_dp_phy_ops);
3745         if (IS_ERR(qmp->dp_phy)) {
3746                 ret = PTR_ERR(qmp->dp_phy);
3747                 dev_err(dev, "failed to create DP PHY: %d\n", ret);
3748                 goto err_node_put;
3749         }
3750
3751         phy_set_drvdata(qmp->dp_phy, qmp);
3752
3753         if (usb_np == dev->of_node)
3754                 phy_provider = devm_of_phy_provider_register(dev, qmp_combo_phy_xlate);
3755         else
3756                 phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate);
3757
3758         of_node_put(usb_np);
3759         of_node_put(dp_np);
3760
3761         return PTR_ERR_OR_ZERO(phy_provider);
3762
3763 err_node_put:
3764         of_node_put(usb_np);
3765         of_node_put(dp_np);
3766         return ret;
3767 }
3768
3769 static const struct of_device_id qmp_combo_of_match_table[] = {
3770         {
3771                 .compatible = "qcom,sc7180-qmp-usb3-dp-phy",
3772                 .data = &sc7180_usb3dpphy_cfg,
3773         },
3774         {
3775                 .compatible = "qcom,sc7280-qmp-usb3-dp-phy",
3776                 .data = &sm8250_usb3dpphy_cfg,
3777         },
3778         {
3779                 .compatible = "qcom,sc8180x-qmp-usb3-dp-phy",
3780                 .data = &sc8180x_usb3dpphy_cfg,
3781         },
3782         {
3783                 .compatible = "qcom,sc8280xp-qmp-usb43dp-phy",
3784                 .data = &sc8280xp_usb43dpphy_cfg,
3785         },
3786         {
3787                 .compatible = "qcom,sdm845-qmp-usb3-dp-phy",
3788                 .data = &sdm845_usb3dpphy_cfg,
3789         },
3790         {
3791                 .compatible = "qcom,sm6350-qmp-usb3-dp-phy",
3792                 .data = &sm6350_usb3dpphy_cfg,
3793         },
3794         {
3795                 .compatible = "qcom,sm8150-qmp-usb3-dp-phy",
3796                 .data = &sc8180x_usb3dpphy_cfg,
3797         },
3798         {
3799                 .compatible = "qcom,sm8250-qmp-usb3-dp-phy",
3800                 .data = &sm8250_usb3dpphy_cfg,
3801         },
3802         {
3803                 .compatible = "qcom,sm8350-qmp-usb3-dp-phy",
3804                 .data = &sm8350_usb3dpphy_cfg,
3805         },
3806         {
3807                 .compatible = "qcom,sm8450-qmp-usb3-dp-phy",
3808                 .data = &sm8350_usb3dpphy_cfg,
3809         },
3810         {
3811                 .compatible = "qcom,sm8550-qmp-usb3-dp-phy",
3812                 .data = &sm8550_usb3dpphy_cfg,
3813         },
3814         {
3815                 .compatible = "qcom,sm8650-qmp-usb3-dp-phy",
3816                 .data = &sm8650_usb3dpphy_cfg,
3817         },
3818         {
3819                 .compatible = "qcom,x1e80100-qmp-usb3-dp-phy",
3820                 .data = &x1e80100_usb3dpphy_cfg,
3821         },
3822         { }
3823 };
3824 MODULE_DEVICE_TABLE(of, qmp_combo_of_match_table);
3825
3826 static struct platform_driver qmp_combo_driver = {
3827         .probe          = qmp_combo_probe,
3828         .driver = {
3829                 .name   = "qcom-qmp-combo-phy",
3830                 .pm     = &qmp_combo_pm_ops,
3831                 .of_match_table = qmp_combo_of_match_table,
3832         },
3833 };
3834
3835 module_platform_driver(qmp_combo_driver);
3836
3837 MODULE_AUTHOR("Vivek Gautam <[email protected]>");
3838 MODULE_DESCRIPTION("Qualcomm QMP USB+DP combo PHY driver");
3839 MODULE_LICENSE("GPL v2");