drivers/platform/x86/amd/pmc.c

   1 // SPDX-License-Identifier: GPL-2.0-or-later
   2 /*
   3  * AMD SoC Power Management Controller Driver
   4  *
   5  * Copyright (c) 2020, Advanced Micro Devices, Inc.
   6  * All Rights Reserved.
   7  *
   8  * Author: Shyam Sundar S K <[email protected]>
   9  */
  10
  11 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  12
  13 #include <linux/acpi.h>
  14 #include <linux/bitfield.h>
  15 #include <linux/bits.h>
  16 #include <linux/debugfs.h>
  17 #include <linux/delay.h>
  18 #include <linux/io.h>
  19 #include <linux/iopoll.h>
  20 #include <linux/limits.h>
  21 #include <linux/module.h>
  22 #include <linux/pci.h>
  23 #include <linux/platform_device.h>
  24 #include <linux/rtc.h>
  25 #include <linux/serio.h>
  26 #include <linux/suspend.h>
  27 #include <linux/seq_file.h>
  28 #include <linux/uaccess.h>
  29
  30 /* SMU communication registers */
  31 #define AMD_PMC_REGISTER_MESSAGE        0x538
  32 #define AMD_PMC_REGISTER_RESPONSE       0x980
  33 #define AMD_PMC_REGISTER_ARGUMENT       0x9BC
  34
  35 /* PMC Scratch Registers */
  36 #define AMD_PMC_SCRATCH_REG_CZN         0x94
  37 #define AMD_PMC_SCRATCH_REG_YC          0xD14
  38
  39 /* STB Registers */
  40 #define AMD_PMC_STB_INDEX_ADDRESS       0xF8
  41 #define AMD_PMC_STB_INDEX_DATA          0xFC
  42 #define AMD_PMC_STB_PMI_0               0x03E30600
  43 #define AMD_PMC_STB_S2IDLE_PREPARE      0xC6000001
  44 #define AMD_PMC_STB_S2IDLE_RESTORE      0xC6000002
  45 #define AMD_PMC_STB_S2IDLE_CHECK        0xC6000003
  46 #define AMD_PMC_STB_DUMMY_PC            0xC6000007
  47
  48 /* STB S2D(Spill to DRAM) has different message port offset */
  49 #define STB_SPILL_TO_DRAM               0xBE
  50 #define AMD_S2D_REGISTER_MESSAGE        0xA20
  51 #define AMD_S2D_REGISTER_RESPONSE       0xA80
  52 #define AMD_S2D_REGISTER_ARGUMENT       0xA88
  53
  54 /* STB Spill to DRAM Parameters */
  55 #define S2D_TELEMETRY_BYTES_MAX         0x100000
  56 #define S2D_TELEMETRY_DRAMBYTES_MAX     0x1000000
  57
  58 /* Base address of SMU for mapping physical address to virtual address */
  59 #define AMD_PMC_SMU_INDEX_ADDRESS       0xB8
  60 #define AMD_PMC_SMU_INDEX_DATA          0xBC
  61 #define AMD_PMC_MAPPING_SIZE            0x01000
  62 #define AMD_PMC_BASE_ADDR_OFFSET        0x10000
  63 #define AMD_PMC_BASE_ADDR_LO            0x13B102E8
  64 #define AMD_PMC_BASE_ADDR_HI            0x13B102EC
  65 #define AMD_PMC_BASE_ADDR_LO_MASK       GENMASK(15, 0)
  66 #define AMD_PMC_BASE_ADDR_HI_MASK       GENMASK(31, 20)
  67
  68 /* SMU Response Codes */
  69 #define AMD_PMC_RESULT_OK                    0x01
  70 #define AMD_PMC_RESULT_CMD_REJECT_BUSY       0xFC
  71 #define AMD_PMC_RESULT_CMD_REJECT_PREREQ     0xFD
  72 #define AMD_PMC_RESULT_CMD_UNKNOWN           0xFE
  73 #define AMD_PMC_RESULT_FAILED                0xFF
  74
  75 /* FCH SSC Registers */
  76 #define FCH_S0I3_ENTRY_TIME_L_OFFSET    0x30
  77 #define FCH_S0I3_ENTRY_TIME_H_OFFSET    0x34
  78 #define FCH_S0I3_EXIT_TIME_L_OFFSET     0x38
  79 #define FCH_S0I3_EXIT_TIME_H_OFFSET     0x3C
  80 #define FCH_SSC_MAPPING_SIZE            0x800
  81 #define FCH_BASE_PHY_ADDR_LOW           0xFED81100
  82 #define FCH_BASE_PHY_ADDR_HIGH          0x00000000
  83
  84 /* SMU Message Definations */
  85 #define SMU_MSG_GETSMUVERSION           0x02
  86 #define SMU_MSG_LOG_GETDRAM_ADDR_HI     0x04
  87 #define SMU_MSG_LOG_GETDRAM_ADDR_LO     0x05
  88 #define SMU_MSG_LOG_START               0x06
  89 #define SMU_MSG_LOG_RESET               0x07
  90 #define SMU_MSG_LOG_DUMP_DATA           0x08
  91 #define SMU_MSG_GET_SUP_CONSTRAINTS     0x09
  92 /* List of supported CPU ids */
  93 #define AMD_CPU_ID_RV                   0x15D0
  94 #define AMD_CPU_ID_RN                   0x1630
  95 #define AMD_CPU_ID_PCO                  AMD_CPU_ID_RV
  96 #define AMD_CPU_ID_CZN                  AMD_CPU_ID_RN
  97 #define AMD_CPU_ID_YC                   0x14B5
  98 #define AMD_CPU_ID_CB                   0x14D8
  99 #define AMD_CPU_ID_PS                   0x14E8
 100
 101 #define PMC_MSG_DELAY_MIN_US            50
 102 #define RESPONSE_REGISTER_LOOP_MAX      20000
 103
 104 #define SOC_SUBSYSTEM_IP_MAX    12
 105 #define DELAY_MIN_US            2000
 106 #define DELAY_MAX_US            3000
 107 #define FIFO_SIZE               4096
 108
 109 enum amd_pmc_def {
 110         MSG_TEST = 0x01,
 111         MSG_OS_HINT_PCO,
 112         MSG_OS_HINT_RN,
 113 };
 114
 115 enum s2d_arg {
 116         S2D_TELEMETRY_SIZE = 0x01,
 117         S2D_PHYS_ADDR_LOW,
 118         S2D_PHYS_ADDR_HIGH,
 119         S2D_NUM_SAMPLES,
 120 };
 121
 122 struct amd_pmc_bit_map {
 123         const char *name;
 124         u32 bit_mask;
 125 };
 126
 127 static const struct amd_pmc_bit_map soc15_ip_blk[] = {
 128         {"DISPLAY",     BIT(0)},
 129         {"CPU",         BIT(1)},
 130         {"GFX",         BIT(2)},
 131         {"VDD",         BIT(3)},
 132         {"ACP",         BIT(4)},
 133         {"VCN",         BIT(5)},
 134         {"ISP",         BIT(6)},
 135         {"NBIO",        BIT(7)},
 136         {"DF",          BIT(8)},
 137         {"USB0",        BIT(9)},
 138         {"USB1",        BIT(10)},
 139         {"LAPIC",       BIT(11)},
 140         {}
 141 };
 142
 143 struct amd_pmc_dev {
 144         void __iomem *regbase;
 145         void __iomem *smu_virt_addr;
 146         void __iomem *stb_virt_addr;
 147         void __iomem *fch_virt_addr;
 148         bool msg_port;
 149         u32 base_addr;
 150         u32 cpu_id;
 151         u32 active_ips;
 152 /* SMU version information */
 153         u8 smu_program;
 154         u8 major;
 155         u8 minor;
 156         u8 rev;
 157         struct device *dev;
 158         struct pci_dev *rdev;
 159         struct mutex lock; /* generic mutex lock */
 160         struct dentry *dbgfs_dir;
 161 };
 162
 163 static bool enable_stb;
 164 module_param(enable_stb, bool, 0644);
 165 MODULE_PARM_DESC(enable_stb, "Enable the STB debug mechanism");
 166
 167 static bool disable_workarounds;
 168 module_param(disable_workarounds, bool, 0644);
 169 MODULE_PARM_DESC(disable_workarounds, "Disable workarounds for platform bugs");
 170
 171 static struct amd_pmc_dev pmc;
 172 static int amd_pmc_send_cmd(struct amd_pmc_dev *dev, u32 arg, u32 *data, u8 msg, bool ret);
 173 static int amd_pmc_read_stb(struct amd_pmc_dev *dev, u32 *buf);
 174 static int amd_pmc_write_stb(struct amd_pmc_dev *dev, u32 data);
 175
 176 static inline u32 amd_pmc_reg_read(struct amd_pmc_dev *dev, int reg_offset)
 177 {
 178         return ioread32(dev->regbase + reg_offset);
 179 }
 180
 181 static inline void amd_pmc_reg_write(struct amd_pmc_dev *dev, int reg_offset, u32 val)
 182 {
 183         iowrite32(val, dev->regbase + reg_offset);
 184 }
 185
 186 struct smu_metrics {
 187         u32 table_version;
 188         u32 hint_count;
 189         u32 s0i3_last_entry_status;
 190         u32 timein_s0i2;
 191         u64 timeentering_s0i3_lastcapture;
 192         u64 timeentering_s0i3_totaltime;
 193         u64 timeto_resume_to_os_lastcapture;
 194         u64 timeto_resume_to_os_totaltime;
 195         u64 timein_s0i3_lastcapture;
 196         u64 timein_s0i3_totaltime;
 197         u64 timein_swdrips_lastcapture;
 198         u64 timein_swdrips_totaltime;
 199         u64 timecondition_notmet_lastcapture[SOC_SUBSYSTEM_IP_MAX];
 200         u64 timecondition_notmet_totaltime[SOC_SUBSYSTEM_IP_MAX];
 201 } __packed;
 202
 203 static int amd_pmc_stb_debugfs_open(struct inode *inode, struct file *filp)
 204 {
 205         struct amd_pmc_dev *dev = filp->f_inode->i_private;
 206         u32 size = FIFO_SIZE * sizeof(u32);
 207         u32 *buf;
 208         int rc;
 209
 210         buf = kzalloc(size, GFP_KERNEL);
 211         if (!buf)
 212                 return -ENOMEM;
 213
 214         rc = amd_pmc_read_stb(dev, buf);
 215         if (rc) {
 216                 kfree(buf);
 217                 return rc;
 218         }
 219
 220         filp->private_data = buf;
 221         return rc;
 222 }
 223
 224 static ssize_t amd_pmc_stb_debugfs_read(struct file *filp, char __user *buf, size_t size,
 225                                         loff_t *pos)
 226 {
 227         if (!filp->private_data)
 228                 return -EINVAL;
 229
 230         return simple_read_from_buffer(buf, size, pos, filp->private_data,
 231                                        FIFO_SIZE * sizeof(u32));
 232 }
 233
 234 static int amd_pmc_stb_debugfs_release(struct inode *inode, struct file *filp)
 235 {
 236         kfree(filp->private_data);
 237         return 0;
 238 }
 239
 240 static const struct file_operations amd_pmc_stb_debugfs_fops = {
 241         .owner = THIS_MODULE,
 242         .open = amd_pmc_stb_debugfs_open,
 243         .read = amd_pmc_stb_debugfs_read,
 244         .release = amd_pmc_stb_debugfs_release,
 245 };
 246
 247 static int amd_pmc_stb_debugfs_open_v2(struct inode *inode, struct file *filp)
 248 {
 249         struct amd_pmc_dev *dev = filp->f_inode->i_private;
 250         u32 *buf, fsize, num_samples, stb_rdptr_offset = 0;
 251         int ret;
 252
 253         /* Write dummy postcode while reading the STB buffer */
 254         ret = amd_pmc_write_stb(dev, AMD_PMC_STB_DUMMY_PC);
 255         if (ret)
 256                 dev_err(dev->dev, "error writing to STB: %d\n", ret);
 257
 258         buf = kzalloc(S2D_TELEMETRY_BYTES_MAX, GFP_KERNEL);
 259         if (!buf)
 260                 return -ENOMEM;
 261
 262         /* Spill to DRAM num_samples uses separate SMU message port */
 263         dev->msg_port = 1;
 264
 265         /* Get the num_samples to calculate the last push location */
 266         ret = amd_pmc_send_cmd(dev, S2D_NUM_SAMPLES, &num_samples, STB_SPILL_TO_DRAM, 1);
 267         /* Clear msg_port for other SMU operation */
 268         dev->msg_port = 0;
 269         if (ret) {
 270                 dev_err(dev->dev, "error: S2D_NUM_SAMPLES not supported : %d\n", ret);
 271                 return ret;
 272         }
 273
 274         /* Start capturing data from the last push location */
 275         if (num_samples > S2D_TELEMETRY_BYTES_MAX) {
 276                 fsize  = S2D_TELEMETRY_BYTES_MAX;
 277                 stb_rdptr_offset = num_samples - fsize;
 278         } else {
 279                 fsize = num_samples;
 280                 stb_rdptr_offset = 0;
 281         }
 282
 283         memcpy_fromio(buf, dev->stb_virt_addr + stb_rdptr_offset, fsize);
 284         filp->private_data = buf;
 285
 286         return 0;
 287 }
 288
 289 static ssize_t amd_pmc_stb_debugfs_read_v2(struct file *filp, char __user *buf, size_t size,
 290                                            loff_t *pos)
 291 {
 292         if (!filp->private_data)
 293                 return -EINVAL;
 294
 295         return simple_read_from_buffer(buf, size, pos, filp->private_data,
 296                                         S2D_TELEMETRY_BYTES_MAX);
 297 }
 298
 299 static int amd_pmc_stb_debugfs_release_v2(struct inode *inode, struct file *filp)
 300 {
 301         kfree(filp->private_data);
 302         return 0;
 303 }
 304
 305 static const struct file_operations amd_pmc_stb_debugfs_fops_v2 = {
 306         .owner = THIS_MODULE,
 307         .open = amd_pmc_stb_debugfs_open_v2,
 308         .read = amd_pmc_stb_debugfs_read_v2,
 309         .release = amd_pmc_stb_debugfs_release_v2,
 310 };
 311
 312 static int amd_pmc_setup_smu_logging(struct amd_pmc_dev *dev)
 313 {
 314         if (dev->cpu_id == AMD_CPU_ID_PCO) {
 315                 dev_warn_once(dev->dev, "SMU debugging info not supported on this platform\n");
 316                 return -EINVAL;
 317         }
 318
 319         /* Get Active devices list from SMU */
 320         if (!dev->active_ips)
 321                 amd_pmc_send_cmd(dev, 0, &dev->active_ips, SMU_MSG_GET_SUP_CONSTRAINTS, 1);
 322
 323         /* Get dram address */
 324         if (!dev->smu_virt_addr) {
 325                 u32 phys_addr_low, phys_addr_hi;
 326                 u64 smu_phys_addr;
 327
 328                 amd_pmc_send_cmd(dev, 0, &phys_addr_low, SMU_MSG_LOG_GETDRAM_ADDR_LO, 1);
 329                 amd_pmc_send_cmd(dev, 0, &phys_addr_hi, SMU_MSG_LOG_GETDRAM_ADDR_HI, 1);
 330                 smu_phys_addr = ((u64)phys_addr_hi << 32 | phys_addr_low);
 331
 332                 dev->smu_virt_addr = devm_ioremap(dev->dev, smu_phys_addr,
 333                                                   sizeof(struct smu_metrics));
 334                 if (!dev->smu_virt_addr)
 335                         return -ENOMEM;
 336         }
 337
 338         /* Start the logging */
 339         amd_pmc_send_cmd(dev, 0, NULL, SMU_MSG_LOG_RESET, 0);
 340         amd_pmc_send_cmd(dev, 0, NULL, SMU_MSG_LOG_START, 0);
 341
 342         return 0;
 343 }
 344
 345 static int amd_pmc_idlemask_read(struct amd_pmc_dev *pdev, struct device *dev,
 346                                  struct seq_file *s)
 347 {
 348         u32 val;
 349
 350         switch (pdev->cpu_id) {
 351         case AMD_CPU_ID_CZN:
 352                 val = amd_pmc_reg_read(pdev, AMD_PMC_SCRATCH_REG_CZN);
 353                 break;
 354         case AMD_CPU_ID_YC:
 355         case AMD_CPU_ID_CB:
 356         case AMD_CPU_ID_PS:
 357                 val = amd_pmc_reg_read(pdev, AMD_PMC_SCRATCH_REG_YC);
 358                 break;
 359         default:
 360                 return -EINVAL;
 361         }
 362
 363         if (dev)
 364                 dev_dbg(pdev->dev, "SMU idlemask s0i3: 0x%x\n", val);
 365
 366         if (s)
 367                 seq_printf(s, "SMU idlemask : 0x%x\n", val);
 368
 369         return 0;
 370 }
 371
 372 static int get_metrics_table(struct amd_pmc_dev *pdev, struct smu_metrics *table)
 373 {
 374         if (!pdev->smu_virt_addr) {
 375                 int ret = amd_pmc_setup_smu_logging(pdev);
 376
 377                 if (ret)
 378                         return ret;
 379         }
 380
 381         if (pdev->cpu_id == AMD_CPU_ID_PCO)
 382                 return -ENODEV;
 383         memcpy_fromio(table, pdev->smu_virt_addr, sizeof(struct smu_metrics));
 384         return 0;
 385 }
 386
 387 static void amd_pmc_validate_deepest(struct amd_pmc_dev *pdev)
 388 {
 389         struct smu_metrics table;
 390
 391         if (get_metrics_table(pdev, &table))
 392                 return;
 393
 394         if (!table.s0i3_last_entry_status)
 395                 dev_warn(pdev->dev, "Last suspend didn't reach deepest state\n");
 396         else
 397                 dev_dbg(pdev->dev, "Last suspend in deepest state for %lluus\n",
 398                          table.timein_s0i3_lastcapture);
 399 }
 400
 401 static int amd_pmc_get_smu_version(struct amd_pmc_dev *dev)
 402 {
 403         int rc;
 404         u32 val;
 405
 406         rc = amd_pmc_send_cmd(dev, 0, &val, SMU_MSG_GETSMUVERSION, 1);
 407         if (rc)
 408                 return rc;
 409
 410         dev->smu_program = (val >> 24) & GENMASK(7, 0);
 411         dev->major = (val >> 16) & GENMASK(7, 0);
 412         dev->minor = (val >> 8) & GENMASK(7, 0);
 413         dev->rev = (val >> 0) & GENMASK(7, 0);
 414
 415         dev_dbg(dev->dev, "SMU program %u version is %u.%u.%u\n",
 416                 dev->smu_program, dev->major, dev->minor, dev->rev);
 417
 418         return 0;
 419 }
 420
 421 static ssize_t smu_fw_version_show(struct device *d, struct device_attribute *attr,
 422                                    char *buf)
 423 {
 424         struct amd_pmc_dev *dev = dev_get_drvdata(d);
 425
 426         if (!dev->major) {
 427                 int rc = amd_pmc_get_smu_version(dev);
 428
 429                 if (rc)
 430                         return rc;
 431         }
 432         return sysfs_emit(buf, "%u.%u.%u\n", dev->major, dev->minor, dev->rev);
 433 }
 434
 435 static ssize_t smu_program_show(struct device *d, struct device_attribute *attr,
 436                                    char *buf)
 437 {
 438         struct amd_pmc_dev *dev = dev_get_drvdata(d);
 439
 440         if (!dev->major) {
 441                 int rc = amd_pmc_get_smu_version(dev);
 442
 443                 if (rc)
 444                         return rc;
 445         }
 446         return sysfs_emit(buf, "%u\n", dev->smu_program);
 447 }
 448
 449 static DEVICE_ATTR_RO(smu_fw_version);
 450 static DEVICE_ATTR_RO(smu_program);
 451
 452 static struct attribute *pmc_attrs[] = {
 453         &dev_attr_smu_fw_version.attr,
 454         &dev_attr_smu_program.attr,
 455         NULL,
 456 };
 457 ATTRIBUTE_GROUPS(pmc);
 458
 459 static int smu_fw_info_show(struct seq_file *s, void *unused)
 460 {
 461         struct amd_pmc_dev *dev = s->private;
 462         struct smu_metrics table;
 463         int idx;
 464
 465         if (get_metrics_table(dev, &table))
 466                 return -EINVAL;
 467
 468         seq_puts(s, "\n=== SMU Statistics ===\n");
 469         seq_printf(s, "Table Version: %d\n", table.table_version);
 470         seq_printf(s, "Hint Count: %d\n", table.hint_count);
 471         seq_printf(s, "Last S0i3 Status: %s\n", table.s0i3_last_entry_status ? "Success" :
 472                    "Unknown/Fail");
 473         seq_printf(s, "Time (in us) to S0i3: %lld\n", table.timeentering_s0i3_lastcapture);
 474         seq_printf(s, "Time (in us) in S0i3: %lld\n", table.timein_s0i3_lastcapture);
 475         seq_printf(s, "Time (in us) to resume from S0i3: %lld\n",
 476                    table.timeto_resume_to_os_lastcapture);
 477
 478         seq_puts(s, "\n=== Active time (in us) ===\n");
 479         for (idx = 0 ; idx < SOC_SUBSYSTEM_IP_MAX ; idx++) {
 480                 if (soc15_ip_blk[idx].bit_mask & dev->active_ips)
 481                         seq_printf(s, "%-8s : %lld\n", soc15_ip_blk[idx].name,
 482                                    table.timecondition_notmet_lastcapture[idx]);
 483         }
 484
 485         return 0;
 486 }
 487 DEFINE_SHOW_ATTRIBUTE(smu_fw_info);
 488
 489 static int s0ix_stats_show(struct seq_file *s, void *unused)
 490 {
 491         struct amd_pmc_dev *dev = s->private;
 492         u64 entry_time, exit_time, residency;
 493
 494         /* Use FCH registers to get the S0ix stats */
 495         if (!dev->fch_virt_addr) {
 496                 u32 base_addr_lo = FCH_BASE_PHY_ADDR_LOW;
 497                 u32 base_addr_hi = FCH_BASE_PHY_ADDR_HIGH;
 498                 u64 fch_phys_addr = ((u64)base_addr_hi << 32 | base_addr_lo);
 499
 500                 dev->fch_virt_addr = devm_ioremap(dev->dev, fch_phys_addr, FCH_SSC_MAPPING_SIZE);
 501                 if (!dev->fch_virt_addr)
 502                         return -ENOMEM;
 503         }
 504
 505         entry_time = ioread32(dev->fch_virt_addr + FCH_S0I3_ENTRY_TIME_H_OFFSET);
 506         entry_time = entry_time << 32 | ioread32(dev->fch_virt_addr + FCH_S0I3_ENTRY_TIME_L_OFFSET);
 507
 508         exit_time = ioread32(dev->fch_virt_addr + FCH_S0I3_EXIT_TIME_H_OFFSET);
 509         exit_time = exit_time << 32 | ioread32(dev->fch_virt_addr + FCH_S0I3_EXIT_TIME_L_OFFSET);
 510
 511         /* It's in 48MHz. We need to convert it */
 512         residency = exit_time - entry_time;
 513         do_div(residency, 48);
 514
 515         seq_puts(s, "=== S0ix statistics ===\n");
 516         seq_printf(s, "S0ix Entry Time: %lld\n", entry_time);
 517         seq_printf(s, "S0ix Exit Time: %lld\n", exit_time);
 518         seq_printf(s, "Residency Time: %lld\n", residency);
 519
 520         return 0;
 521 }
 522 DEFINE_SHOW_ATTRIBUTE(s0ix_stats);
 523
 524 static int amd_pmc_idlemask_show(struct seq_file *s, void *unused)
 525 {
 526         struct amd_pmc_dev *dev = s->private;
 527         int rc;
 528
 529         /* we haven't yet read SMU version */
 530         if (!dev->major) {
 531                 rc = amd_pmc_get_smu_version(dev);
 532                 if (rc)
 533                         return rc;
 534         }
 535
 536         if (dev->major > 56 || (dev->major >= 55 && dev->minor >= 37)) {
 537                 rc = amd_pmc_idlemask_read(dev, NULL, s);
 538                 if (rc)
 539                         return rc;
 540         } else {
 541                 seq_puts(s, "Unsupported SMU version for Idlemask\n");
 542         }
 543
 544         return 0;
 545 }
 546 DEFINE_SHOW_ATTRIBUTE(amd_pmc_idlemask);
 547
 548 static void amd_pmc_dbgfs_unregister(struct amd_pmc_dev *dev)
 549 {
 550         debugfs_remove_recursive(dev->dbgfs_dir);
 551 }
 552
 553 static void amd_pmc_dbgfs_register(struct amd_pmc_dev *dev)
 554 {
 555         dev->dbgfs_dir = debugfs_create_dir("amd_pmc", NULL);
 556         debugfs_create_file("smu_fw_info", 0644, dev->dbgfs_dir, dev,
 557                             &smu_fw_info_fops);
 558         debugfs_create_file("s0ix_stats", 0644, dev->dbgfs_dir, dev,
 559                             &s0ix_stats_fops);
 560         debugfs_create_file("amd_pmc_idlemask", 0644, dev->dbgfs_dir, dev,
 561                             &amd_pmc_idlemask_fops);
 562         /* Enable STB only when the module_param is set */
 563         if (enable_stb) {
 564                 if (dev->cpu_id == AMD_CPU_ID_YC || dev->cpu_id == AMD_CPU_ID_CB ||
 565                     dev->cpu_id == AMD_CPU_ID_PS)
 566                         debugfs_create_file("stb_read", 0644, dev->dbgfs_dir, dev,
 567                                             &amd_pmc_stb_debugfs_fops_v2);
 568                 else
 569                         debugfs_create_file("stb_read", 0644, dev->dbgfs_dir, dev,
 570                                             &amd_pmc_stb_debugfs_fops);
 571         }
 572 }
 573
 574 static void amd_pmc_dump_registers(struct amd_pmc_dev *dev)
 575 {
 576         u32 value, message, argument, response;
 577
 578         if (dev->msg_port) {
 579                 message = AMD_S2D_REGISTER_MESSAGE;
 580                 argument = AMD_S2D_REGISTER_ARGUMENT;
 581                 response = AMD_S2D_REGISTER_RESPONSE;
 582         } else {
 583                 message = AMD_PMC_REGISTER_MESSAGE;
 584                 argument = AMD_PMC_REGISTER_ARGUMENT;
 585                 response = AMD_PMC_REGISTER_RESPONSE;
 586         }
 587
 588         value = amd_pmc_reg_read(dev, response);
 589         dev_dbg(dev->dev, "AMD_%s_REGISTER_RESPONSE:%x\n", dev->msg_port ? "S2D" : "PMC", value);
 590
 591         value = amd_pmc_reg_read(dev, argument);
 592         dev_dbg(dev->dev, "AMD_%s_REGISTER_ARGUMENT:%x\n", dev->msg_port ? "S2D" : "PMC", value);
 593
 594         value = amd_pmc_reg_read(dev, message);
 595         dev_dbg(dev->dev, "AMD_%s_REGISTER_MESSAGE:%x\n", dev->msg_port ? "S2D" : "PMC", value);
 596 }
 597
 598 static int amd_pmc_send_cmd(struct amd_pmc_dev *dev, u32 arg, u32 *data, u8 msg, bool ret)
 599 {
 600         int rc;
 601         u32 val, message, argument, response;
 602
 603         mutex_lock(&dev->lock);
 604
 605         if (dev->msg_port) {
 606                 message = AMD_S2D_REGISTER_MESSAGE;
 607                 argument = AMD_S2D_REGISTER_ARGUMENT;
 608                 response = AMD_S2D_REGISTER_RESPONSE;
 609         } else {
 610                 message = AMD_PMC_REGISTER_MESSAGE;
 611                 argument = AMD_PMC_REGISTER_ARGUMENT;
 612                 response = AMD_PMC_REGISTER_RESPONSE;
 613         }
 614
 615         /* Wait until we get a valid response */
 616         rc = readx_poll_timeout(ioread32, dev->regbase + response,
 617                                 val, val != 0, PMC_MSG_DELAY_MIN_US,
 618                                 PMC_MSG_DELAY_MIN_US * RESPONSE_REGISTER_LOOP_MAX);
 619         if (rc) {
 620                 dev_err(dev->dev, "failed to talk to SMU\n");
 621                 goto out_unlock;
 622         }
 623
 624         /* Write zero to response register */
 625         amd_pmc_reg_write(dev, response, 0);
 626
 627         /* Write argument into response register */
 628         amd_pmc_reg_write(dev, argument, arg);
 629
 630         /* Write message ID to message ID register */
 631         amd_pmc_reg_write(dev, message, msg);
 632
 633         /* Wait until we get a valid response */
 634         rc = readx_poll_timeout(ioread32, dev->regbase + response,
 635                                 val, val != 0, PMC_MSG_DELAY_MIN_US,
 636                                 PMC_MSG_DELAY_MIN_US * RESPONSE_REGISTER_LOOP_MAX);
 637         if (rc) {
 638                 dev_err(dev->dev, "SMU response timed out\n");
 639                 goto out_unlock;
 640         }
 641
 642         switch (val) {
 643         case AMD_PMC_RESULT_OK:
 644                 if (ret) {
 645                         /* PMFW may take longer time to return back the data */
 646                         usleep_range(DELAY_MIN_US, 10 * DELAY_MAX_US);
 647                         *data = amd_pmc_reg_read(dev, argument);
 648                 }
 649                 break;
 650         case AMD_PMC_RESULT_CMD_REJECT_BUSY:
 651                 dev_err(dev->dev, "SMU not ready. err: 0x%x\n", val);
 652                 rc = -EBUSY;
 653                 goto out_unlock;
 654         case AMD_PMC_RESULT_CMD_UNKNOWN:
 655                 dev_err(dev->dev, "SMU cmd unknown. err: 0x%x\n", val);
 656                 rc = -EINVAL;
 657                 goto out_unlock;
 658         case AMD_PMC_RESULT_CMD_REJECT_PREREQ:
 659         case AMD_PMC_RESULT_FAILED:
 660         default:
 661                 dev_err(dev->dev, "SMU cmd failed. err: 0x%x\n", val);
 662                 rc = -EIO;
 663                 goto out_unlock;
 664         }
 665
 666 out_unlock:
 667         mutex_unlock(&dev->lock);
 668         amd_pmc_dump_registers(dev);
 669         return rc;
 670 }
 671
 672 static int amd_pmc_get_os_hint(struct amd_pmc_dev *dev)
 673 {
 674         switch (dev->cpu_id) {
 675         case AMD_CPU_ID_PCO:
 676                 return MSG_OS_HINT_PCO;
 677         case AMD_CPU_ID_RN:
 678         case AMD_CPU_ID_YC:
 679         case AMD_CPU_ID_CB:
 680         case AMD_CPU_ID_PS:
 681                 return MSG_OS_HINT_RN;
 682         }
 683         return -EINVAL;
 684 }
 685
 686 static int amd_pmc_czn_wa_irq1(struct amd_pmc_dev *pdev)
 687 {
 688         struct device *d;
 689         int rc;
 690
 691         if (!pdev->major) {
 692                 rc = amd_pmc_get_smu_version(pdev);
 693                 if (rc)
 694                         return rc;
 695         }
 696
 697         if (pdev->major > 64 || (pdev->major == 64 && pdev->minor > 65))
 698                 return 0;
 699
 700         d = bus_find_device_by_name(&serio_bus, NULL, "serio0");
 701         if (!d)
 702                 return 0;
 703         if (device_may_wakeup(d)) {
 704                 dev_info_once(d, "Disabling IRQ1 wakeup source to avoid platform firmware bug\n");
 705                 disable_irq_wake(1);
 706                 device_set_wakeup_enable(d, false);
 707         }
 708         put_device(d);
 709
 710         return 0;
 711 }
 712
 713 static int amd_pmc_verify_czn_rtc(struct amd_pmc_dev *pdev, u32 *arg)
 714 {
 715         struct rtc_device *rtc_device;
 716         time64_t then, now, duration;
 717         struct rtc_wkalrm alarm;
 718         struct rtc_time tm;
 719         int rc;
 720
 721         /* we haven't yet read SMU version */
 722         if (!pdev->major) {
 723                 rc = amd_pmc_get_smu_version(pdev);
 724                 if (rc)
 725                         return rc;
 726         }
 727
 728         if (pdev->major < 64 || (pdev->major == 64 && pdev->minor < 53))
 729                 return 0;
 730
 731         rtc_device = rtc_class_open("rtc0");
 732         if (!rtc_device)
 733                 return 0;
 734         rc = rtc_read_alarm(rtc_device, &alarm);
 735         if (rc)
 736                 return rc;
 737         if (!alarm.enabled) {
 738                 dev_dbg(pdev->dev, "alarm not enabled\n");
 739                 return 0;
 740         }
 741         rc = rtc_read_time(rtc_device, &tm);
 742         if (rc)
 743                 return rc;
 744         then = rtc_tm_to_time64(&alarm.time);
 745         now = rtc_tm_to_time64(&tm);
 746         duration = then-now;
 747
 748         /* in the past */
 749         if (then < now)
 750                 return 0;
 751
 752         /* will be stored in upper 16 bits of s0i3 hint argument,
 753          * so timer wakeup from s0i3 is limited to ~18 hours or less
 754          */
 755         if (duration <= 4 || duration > U16_MAX)
 756                 return -EINVAL;
 757
 758         *arg |= (duration << 16);
 759         rc = rtc_alarm_irq_enable(rtc_device, 0);
 760         dev_dbg(pdev->dev, "wakeup timer programmed for %lld seconds\n", duration);
 761
 762         return rc;
 763 }
 764
 765 static void amd_pmc_s2idle_prepare(void)
 766 {
 767         struct amd_pmc_dev *pdev = &pmc;
 768         int rc;
 769         u8 msg;
 770         u32 arg = 1;
 771
 772         /* Reset and Start SMU logging - to monitor the s0i3 stats */
 773         amd_pmc_setup_smu_logging(pdev);
 774
 775         /* Activate CZN specific platform bug workarounds */
 776         if (pdev->cpu_id == AMD_CPU_ID_CZN && !disable_workarounds) {
 777                 rc = amd_pmc_verify_czn_rtc(pdev, &arg);
 778                 if (rc) {
 779                         dev_err(pdev->dev, "failed to set RTC: %d\n", rc);
 780                         return;
 781                 }
 782         }
 783
 784         msg = amd_pmc_get_os_hint(pdev);
 785         rc = amd_pmc_send_cmd(pdev, arg, NULL, msg, 0);
 786         if (rc) {
 787                 dev_err(pdev->dev, "suspend failed: %d\n", rc);
 788                 return;
 789         }
 790
 791         rc = amd_pmc_write_stb(pdev, AMD_PMC_STB_S2IDLE_PREPARE);
 792         if (rc)
 793                 dev_err(pdev->dev, "error writing to STB: %d\n", rc);
 794 }
 795
 796 static void amd_pmc_s2idle_check(void)
 797 {
 798         struct amd_pmc_dev *pdev = &pmc;
 799         struct smu_metrics table;
 800         int rc;
 801
 802         /* CZN: Ensure that future s0i3 entry attempts at least 10ms passed */
 803         if (pdev->cpu_id == AMD_CPU_ID_CZN && !get_metrics_table(pdev, &table) &&
 804             table.s0i3_last_entry_status)
 805                 usleep_range(10000, 20000);
 806
 807         /* Dump the IdleMask before we add to the STB */
 808         amd_pmc_idlemask_read(pdev, pdev->dev, NULL);
 809
 810         rc = amd_pmc_write_stb(pdev, AMD_PMC_STB_S2IDLE_CHECK);
 811         if (rc)
 812                 dev_err(pdev->dev, "error writing to STB: %d\n", rc);
 813 }
 814
 815 static void amd_pmc_s2idle_restore(void)
 816 {
 817         struct amd_pmc_dev *pdev = &pmc;
 818         int rc;
 819         u8 msg;
 820
 821         msg = amd_pmc_get_os_hint(pdev);
 822         rc = amd_pmc_send_cmd(pdev, 0, NULL, msg, 0);
 823         if (rc)
 824                 dev_err(pdev->dev, "resume failed: %d\n", rc);
 825
 826         /* Let SMU know that we are looking for stats */
 827         amd_pmc_send_cmd(pdev, 0, NULL, SMU_MSG_LOG_DUMP_DATA, 0);
 828
 829         rc = amd_pmc_write_stb(pdev, AMD_PMC_STB_S2IDLE_RESTORE);
 830         if (rc)
 831                 dev_err(pdev->dev, "error writing to STB: %d\n", rc);
 832
 833         /* Notify on failed entry */
 834         amd_pmc_validate_deepest(pdev);
 835 }
 836
 837 static struct acpi_s2idle_dev_ops amd_pmc_s2idle_dev_ops = {
 838         .prepare = amd_pmc_s2idle_prepare,
 839         .check = amd_pmc_s2idle_check,
 840         .restore = amd_pmc_s2idle_restore,
 841 };
 842
 843 static int __maybe_unused amd_pmc_suspend_handler(struct device *dev)
 844 {
 845         struct amd_pmc_dev *pdev = dev_get_drvdata(dev);
 846
 847         if (pdev->cpu_id == AMD_CPU_ID_CZN && !disable_workarounds) {
 848                 int rc = amd_pmc_czn_wa_irq1(pdev);
 849
 850                 if (rc) {
 851                         dev_err(pdev->dev, "failed to adjust keyboard wakeup: %d\n", rc);
 852                         return rc;
 853                 }
 854         }
 855
 856         return 0;
 857 }
 858
 859 static DEFINE_SIMPLE_DEV_PM_OPS(amd_pmc_pm, amd_pmc_suspend_handler, NULL);
 860
 861 static const struct pci_device_id pmc_pci_ids[] = {
 862         { PCI_DEVICE(PCI_VENDOR_ID_AMD, AMD_CPU_ID_PS) },
 863         { PCI_DEVICE(PCI_VENDOR_ID_AMD, AMD_CPU_ID_CB) },
 864         { PCI_DEVICE(PCI_VENDOR_ID_AMD, AMD_CPU_ID_YC) },
 865         { PCI_DEVICE(PCI_VENDOR_ID_AMD, AMD_CPU_ID_CZN) },
 866         { PCI_DEVICE(PCI_VENDOR_ID_AMD, AMD_CPU_ID_RN) },
 867         { PCI_DEVICE(PCI_VENDOR_ID_AMD, AMD_CPU_ID_PCO) },
 868         { PCI_DEVICE(PCI_VENDOR_ID_AMD, AMD_CPU_ID_RV) },
 869         { }
 870 };
 871
 872 static int amd_pmc_s2d_init(struct amd_pmc_dev *dev)
 873 {
 874         u32 phys_addr_low, phys_addr_hi;
 875         u64 stb_phys_addr;
 876         u32 size = 0;
 877
 878         /* Spill to DRAM feature uses separate SMU message port */
 879         dev->msg_port = 1;
 880
 881         amd_pmc_send_cmd(dev, S2D_TELEMETRY_SIZE, &size, STB_SPILL_TO_DRAM, 1);
 882         if (size != S2D_TELEMETRY_BYTES_MAX)
 883                 return -EIO;
 884
 885         /* Get STB DRAM address */
 886         amd_pmc_send_cmd(dev, S2D_PHYS_ADDR_LOW, &phys_addr_low, STB_SPILL_TO_DRAM, 1);
 887         amd_pmc_send_cmd(dev, S2D_PHYS_ADDR_HIGH, &phys_addr_hi, STB_SPILL_TO_DRAM, 1);
 888
 889         stb_phys_addr = ((u64)phys_addr_hi << 32 | phys_addr_low);
 890
 891         /* Clear msg_port for other SMU operation */
 892         dev->msg_port = 0;
 893
 894         dev->stb_virt_addr = devm_ioremap(dev->dev, stb_phys_addr, S2D_TELEMETRY_DRAMBYTES_MAX);
 895         if (!dev->stb_virt_addr)
 896                 return -ENOMEM;
 897
 898         return 0;
 899 }
 900
 901 static int amd_pmc_write_stb(struct amd_pmc_dev *dev, u32 data)
 902 {
 903         int err;
 904
 905         err = pci_write_config_dword(dev->rdev, AMD_PMC_STB_INDEX_ADDRESS, AMD_PMC_STB_PMI_0);
 906         if (err) {
 907                 dev_err(dev->dev, "failed to write addr in stb: 0x%X\n",
 908                         AMD_PMC_STB_INDEX_ADDRESS);
 909                 return pcibios_err_to_errno(err);
 910         }
 911
 912         err = pci_write_config_dword(dev->rdev, AMD_PMC_STB_INDEX_DATA, data);
 913         if (err) {
 914                 dev_err(dev->dev, "failed to write data in stb: 0x%X\n",
 915                         AMD_PMC_STB_INDEX_DATA);
 916                 return pcibios_err_to_errno(err);
 917         }
 918
 919         return 0;
 920 }
 921
 922 static int amd_pmc_read_stb(struct amd_pmc_dev *dev, u32 *buf)
 923 {
 924         int i, err;
 925
 926         err = pci_write_config_dword(dev->rdev, AMD_PMC_STB_INDEX_ADDRESS, AMD_PMC_STB_PMI_0);
 927         if (err) {
 928                 dev_err(dev->dev, "error writing addr to stb: 0x%X\n",
 929                         AMD_PMC_STB_INDEX_ADDRESS);
 930                 return pcibios_err_to_errno(err);
 931         }
 932
 933         for (i = 0; i < FIFO_SIZE; i++) {
 934                 err = pci_read_config_dword(dev->rdev, AMD_PMC_STB_INDEX_DATA, buf++);
 935                 if (err) {
 936                         dev_err(dev->dev, "error reading data from stb: 0x%X\n",
 937                                 AMD_PMC_STB_INDEX_DATA);
 938                         return pcibios_err_to_errno(err);
 939                 }
 940         }
 941
 942         return 0;
 943 }
 944
 945 static int amd_pmc_probe(struct platform_device *pdev)
 946 {
 947         struct amd_pmc_dev *dev = &pmc;
 948         struct pci_dev *rdev;
 949         u32 base_addr_lo, base_addr_hi;
 950         u64 base_addr;
 951         int err;
 952         u32 val;
 953
 954         dev->dev = &pdev->dev;
 955
 956         rdev = pci_get_domain_bus_and_slot(0, 0, PCI_DEVFN(0, 0));
 957         if (!rdev || !pci_match_id(pmc_pci_ids, rdev)) {
 958                 err = -ENODEV;
 959                 goto err_pci_dev_put;
 960         }
 961
 962         dev->cpu_id = rdev->device;
 963         dev->rdev = rdev;
 964         err = pci_write_config_dword(rdev, AMD_PMC_SMU_INDEX_ADDRESS, AMD_PMC_BASE_ADDR_LO);
 965         if (err) {
 966                 dev_err(dev->dev, "error writing to 0x%x\n", AMD_PMC_SMU_INDEX_ADDRESS);
 967                 err = pcibios_err_to_errno(err);
 968                 goto err_pci_dev_put;
 969         }
 970
 971         err = pci_read_config_dword(rdev, AMD_PMC_SMU_INDEX_DATA, &val);
 972         if (err) {
 973                 err = pcibios_err_to_errno(err);
 974                 goto err_pci_dev_put;
 975         }
 976
 977         base_addr_lo = val & AMD_PMC_BASE_ADDR_HI_MASK;
 978
 979         err = pci_write_config_dword(rdev, AMD_PMC_SMU_INDEX_ADDRESS, AMD_PMC_BASE_ADDR_HI);
 980         if (err) {
 981                 dev_err(dev->dev, "error writing to 0x%x\n", AMD_PMC_SMU_INDEX_ADDRESS);
 982                 err = pcibios_err_to_errno(err);
 983                 goto err_pci_dev_put;
 984         }
 985
 986         err = pci_read_config_dword(rdev, AMD_PMC_SMU_INDEX_DATA, &val);
 987         if (err) {
 988                 err = pcibios_err_to_errno(err);
 989                 goto err_pci_dev_put;
 990         }
 991
 992         base_addr_hi = val & AMD_PMC_BASE_ADDR_LO_MASK;
 993         base_addr = ((u64)base_addr_hi << 32 | base_addr_lo);
 994
 995         dev->regbase = devm_ioremap(dev->dev, base_addr + AMD_PMC_BASE_ADDR_OFFSET,
 996                                     AMD_PMC_MAPPING_SIZE);
 997         if (!dev->regbase) {
 998                 err = -ENOMEM;
 999                 goto err_pci_dev_put;
1000         }
1001
1002         mutex_init(&dev->lock);
1003
1004         if (enable_stb && (dev->cpu_id == AMD_CPU_ID_YC || dev->cpu_id == AMD_CPU_ID_CB)) {
1005                 err = amd_pmc_s2d_init(dev);
1006                 if (err)
1007                         goto err_pci_dev_put;
1008         }
1009
1010         platform_set_drvdata(pdev, dev);
1011         if (IS_ENABLED(CONFIG_SUSPEND)) {
1012                 err = acpi_register_lps0_dev(&amd_pmc_s2idle_dev_ops);
1013                 if (err)
1014                         dev_warn(dev->dev, "failed to register LPS0 sleep handler, expect increased power consumption\n");
1015         }
1016
1017         amd_pmc_dbgfs_register(dev);
1018         return 0;
1019
1020 err_pci_dev_put:
1021         pci_dev_put(rdev);
1022         return err;
1023 }
1024
1025 static int amd_pmc_remove(struct platform_device *pdev)
1026 {
1027         struct amd_pmc_dev *dev = platform_get_drvdata(pdev);
1028
1029         if (IS_ENABLED(CONFIG_SUSPEND))
1030                 acpi_unregister_lps0_dev(&amd_pmc_s2idle_dev_ops);
1031         amd_pmc_dbgfs_unregister(dev);
1032         pci_dev_put(dev->rdev);
1033         mutex_destroy(&dev->lock);
1034         return 0;
1035 }
1036
1037 static const struct acpi_device_id amd_pmc_acpi_ids[] = {
1038         {"AMDI0005", 0},
1039         {"AMDI0006", 0},
1040         {"AMDI0007", 0},
1041         {"AMDI0008", 0},
1042         {"AMDI0009", 0},
1043         {"AMD0004", 0},
1044         {"AMD0005", 0},
1045         { }
1046 };
1047 MODULE_DEVICE_TABLE(acpi, amd_pmc_acpi_ids);
1048
1049 static struct platform_driver amd_pmc_driver = {
1050         .driver = {
1051                 .name = "amd_pmc",
1052                 .acpi_match_table = amd_pmc_acpi_ids,
1053                 .dev_groups = pmc_groups,
1054                 .pm = pm_sleep_ptr(&amd_pmc_pm),
1055         },
1056         .probe = amd_pmc_probe,
1057         .remove = amd_pmc_remove,
1058 };
1059 module_platform_driver(amd_pmc_driver);
1060
1061 MODULE_LICENSE("GPL v2");
1062 MODULE_DESCRIPTION("AMD PMC Driver");