drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c

   1 /*
   2  * Copyright 2017 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: Rafał Miłecki <[email protected]>
  23  *          Alex Deucher <[email protected]>
  24  */
  25 #include <drm/drmP.h>
  26 #include "amdgpu.h"
  27 #include "amdgpu_drv.h"
  28 #include "amdgpu_pm.h"
  29 #include "amdgpu_dpm.h"
  30 #include "amdgpu_display.h"
  31 #include "amdgpu_smu.h"
  32 #include "atom.h"
  33 #include <linux/power_supply.h>
  34 #include <linux/hwmon.h>
  35 #include <linux/hwmon-sysfs.h>
  36 #include <linux/nospec.h>
  37 #include "hwmgr.h"
  38 #define WIDTH_4K 3840
  39
  40 static int amdgpu_debugfs_pm_init(struct amdgpu_device *adev);
  41
  42 static const struct cg_flag_name clocks[] = {
  43         {AMD_CG_SUPPORT_GFX_MGCG, "Graphics Medium Grain Clock Gating"},
  44         {AMD_CG_SUPPORT_GFX_MGLS, "Graphics Medium Grain memory Light Sleep"},
  45         {AMD_CG_SUPPORT_GFX_CGCG, "Graphics Coarse Grain Clock Gating"},
  46         {AMD_CG_SUPPORT_GFX_CGLS, "Graphics Coarse Grain memory Light Sleep"},
  47         {AMD_CG_SUPPORT_GFX_CGTS, "Graphics Coarse Grain Tree Shader Clock Gating"},
  48         {AMD_CG_SUPPORT_GFX_CGTS_LS, "Graphics Coarse Grain Tree Shader Light Sleep"},
  49         {AMD_CG_SUPPORT_GFX_CP_LS, "Graphics Command Processor Light Sleep"},
  50         {AMD_CG_SUPPORT_GFX_RLC_LS, "Graphics Run List Controller Light Sleep"},
  51         {AMD_CG_SUPPORT_GFX_3D_CGCG, "Graphics 3D Coarse Grain Clock Gating"},
  52         {AMD_CG_SUPPORT_GFX_3D_CGLS, "Graphics 3D Coarse Grain memory Light Sleep"},
  53         {AMD_CG_SUPPORT_MC_LS, "Memory Controller Light Sleep"},
  54         {AMD_CG_SUPPORT_MC_MGCG, "Memory Controller Medium Grain Clock Gating"},
  55         {AMD_CG_SUPPORT_SDMA_LS, "System Direct Memory Access Light Sleep"},
  56         {AMD_CG_SUPPORT_SDMA_MGCG, "System Direct Memory Access Medium Grain Clock Gating"},
  57         {AMD_CG_SUPPORT_BIF_MGCG, "Bus Interface Medium Grain Clock Gating"},
  58         {AMD_CG_SUPPORT_BIF_LS, "Bus Interface Light Sleep"},
  59         {AMD_CG_SUPPORT_UVD_MGCG, "Unified Video Decoder Medium Grain Clock Gating"},
  60         {AMD_CG_SUPPORT_VCE_MGCG, "Video Compression Engine Medium Grain Clock Gating"},
  61         {AMD_CG_SUPPORT_HDP_LS, "Host Data Path Light Sleep"},
  62         {AMD_CG_SUPPORT_HDP_MGCG, "Host Data Path Medium Grain Clock Gating"},
  63         {AMD_CG_SUPPORT_DRM_MGCG, "Digital Right Management Medium Grain Clock Gating"},
  64         {AMD_CG_SUPPORT_DRM_LS, "Digital Right Management Light Sleep"},
  65         {AMD_CG_SUPPORT_ROM_MGCG, "Rom Medium Grain Clock Gating"},
  66         {AMD_CG_SUPPORT_DF_MGCG, "Data Fabric Medium Grain Clock Gating"},
  67         {0, NULL},
  68 };
  69
  70 void amdgpu_pm_acpi_event_handler(struct amdgpu_device *adev)
  71 {
  72         if (adev->pm.dpm_enabled) {
  73                 mutex_lock(&adev->pm.mutex);
  74                 if (power_supply_is_system_supplied() > 0)
  75                         adev->pm.ac_power = true;
  76                 else
  77                         adev->pm.ac_power = false;
  78                 if (adev->powerplay.pp_funcs->enable_bapm)
  79                         amdgpu_dpm_enable_bapm(adev, adev->pm.ac_power);
  80                 mutex_unlock(&adev->pm.mutex);
  81         }
  82 }
  83
  84 int amdgpu_dpm_read_sensor(struct amdgpu_device *adev, enum amd_pp_sensors sensor,
  85                            void *data, uint32_t *size)
  86 {
  87         int ret = 0;
  88
  89         if (!data || !size)
  90                 return -EINVAL;
  91
  92         if (is_support_sw_smu(adev))
  93                 ret = smu_read_sensor(&adev->smu, sensor, data, size);
  94         else {
  95                 if (adev->powerplay.pp_funcs && adev->powerplay.pp_funcs->read_sensor)
  96                         ret = adev->powerplay.pp_funcs->read_sensor((adev)->powerplay.pp_handle,
  97                                                                     sensor, data, size);
  98                 else
  99                         ret = -EINVAL;
 100         }
 101
 102         return ret;
 103 }
 104
 105 /**
 106  * DOC: power_dpm_state
 107  *
 108  * The power_dpm_state file is a legacy interface and is only provided for
 109  * backwards compatibility. The amdgpu driver provides a sysfs API for adjusting
 110  * certain power related parameters.  The file power_dpm_state is used for this.
 111  * It accepts the following arguments:
 112  *
 113  * - battery
 114  *
 115  * - balanced
 116  *
 117  * - performance
 118  *
 119  * battery
 120  *
 121  * On older GPUs, the vbios provided a special power state for battery
 122  * operation.  Selecting battery switched to this state.  This is no
 123  * longer provided on newer GPUs so the option does nothing in that case.
 124  *
 125  * balanced
 126  *
 127  * On older GPUs, the vbios provided a special power state for balanced
 128  * operation.  Selecting balanced switched to this state.  This is no
 129  * longer provided on newer GPUs so the option does nothing in that case.
 130  *
 131  * performance
 132  *
 133  * On older GPUs, the vbios provided a special power state for performance
 134  * operation.  Selecting performance switched to this state.  This is no
 135  * longer provided on newer GPUs so the option does nothing in that case.
 136  *
 137  */
 138
 139 static ssize_t amdgpu_get_dpm_state(struct device *dev,
 140                                     struct device_attribute *attr,
 141                                     char *buf)
 142 {
 143         struct drm_device *ddev = dev_get_drvdata(dev);
 144         struct amdgpu_device *adev = ddev->dev_private;
 145         enum amd_pm_state_type pm;
 146
 147         if (adev->powerplay.pp_funcs->get_current_power_state)
 148                 pm = amdgpu_dpm_get_current_power_state(adev);
 149         else
 150                 pm = adev->pm.dpm.user_state;
 151
 152         return snprintf(buf, PAGE_SIZE, "%s\n",
 153                         (pm == POWER_STATE_TYPE_BATTERY) ? "battery" :
 154                         (pm == POWER_STATE_TYPE_BALANCED) ? "balanced" : "performance");
 155 }
 156
 157 static ssize_t amdgpu_set_dpm_state(struct device *dev,
 158                                     struct device_attribute *attr,
 159                                     const char *buf,
 160                                     size_t count)
 161 {
 162         struct drm_device *ddev = dev_get_drvdata(dev);
 163         struct amdgpu_device *adev = ddev->dev_private;
 164         enum amd_pm_state_type  state;
 165
 166         if (strncmp("battery", buf, strlen("battery")) == 0)
 167                 state = POWER_STATE_TYPE_BATTERY;
 168         else if (strncmp("balanced", buf, strlen("balanced")) == 0)
 169                 state = POWER_STATE_TYPE_BALANCED;
 170         else if (strncmp("performance", buf, strlen("performance")) == 0)
 171                 state = POWER_STATE_TYPE_PERFORMANCE;
 172         else {
 173                 count = -EINVAL;
 174                 goto fail;
 175         }
 176
 177         if (adev->powerplay.pp_funcs->dispatch_tasks) {
 178                 amdgpu_dpm_dispatch_task(adev, AMD_PP_TASK_ENABLE_USER_STATE, &state);
 179         } else {
 180                 mutex_lock(&adev->pm.mutex);
 181                 adev->pm.dpm.user_state = state;
 182                 mutex_unlock(&adev->pm.mutex);
 183
 184                 /* Can't set dpm state when the card is off */
 185                 if (!(adev->flags & AMD_IS_PX) ||
 186                     (ddev->switch_power_state == DRM_SWITCH_POWER_ON))
 187                         amdgpu_pm_compute_clocks(adev);
 188         }
 189 fail:
 190         return count;
 191 }
 192
 193
 194 /**
 195  * DOC: power_dpm_force_performance_level
 196  *
 197  * The amdgpu driver provides a sysfs API for adjusting certain power
 198  * related parameters.  The file power_dpm_force_performance_level is
 199  * used for this.  It accepts the following arguments:
 200  *
 201  * - auto
 202  *
 203  * - low
 204  *
 205  * - high
 206  *
 207  * - manual
 208  *
 209  * - profile_standard
 210  *
 211  * - profile_min_sclk
 212  *
 213  * - profile_min_mclk
 214  *
 215  * - profile_peak
 216  *
 217  * auto
 218  *
 219  * When auto is selected, the driver will attempt to dynamically select
 220  * the optimal power profile for current conditions in the driver.
 221  *
 222  * low
 223  *
 224  * When low is selected, the clocks are forced to the lowest power state.
 225  *
 226  * high
 227  *
 228  * When high is selected, the clocks are forced to the highest power state.
 229  *
 230  * manual
 231  *
 232  * When manual is selected, the user can manually adjust which power states
 233  * are enabled for each clock domain via the sysfs pp_dpm_mclk, pp_dpm_sclk,
 234  * and pp_dpm_pcie files and adjust the power state transition heuristics
 235  * via the pp_power_profile_mode sysfs file.
 236  *
 237  * profile_standard
 238  * profile_min_sclk
 239  * profile_min_mclk
 240  * profile_peak
 241  *
 242  * When the profiling modes are selected, clock and power gating are
 243  * disabled and the clocks are set for different profiling cases. This
 244  * mode is recommended for profiling specific work loads where you do
 245  * not want clock or power gating for clock fluctuation to interfere
 246  * with your results. profile_standard sets the clocks to a fixed clock
 247  * level which varies from asic to asic.  profile_min_sclk forces the sclk
 248  * to the lowest level.  profile_min_mclk forces the mclk to the lowest level.
 249  * profile_peak sets all clocks (mclk, sclk, pcie) to the highest levels.
 250  *
 251  */
 252
 253 static ssize_t amdgpu_get_dpm_forced_performance_level(struct device *dev,
 254                                                 struct device_attribute *attr,
 255                                                                 char *buf)
 256 {
 257         struct drm_device *ddev = dev_get_drvdata(dev);
 258         struct amdgpu_device *adev = ddev->dev_private;
 259         enum amd_dpm_forced_level level = 0xff;
 260
 261         if  ((adev->flags & AMD_IS_PX) &&
 262              (ddev->switch_power_state != DRM_SWITCH_POWER_ON))
 263                 return snprintf(buf, PAGE_SIZE, "off\n");
 264
 265         if (adev->powerplay.pp_funcs->get_performance_level)
 266                 level = amdgpu_dpm_get_performance_level(adev);
 267         else
 268                 level = adev->pm.dpm.forced_level;
 269
 270         return snprintf(buf, PAGE_SIZE, "%s\n",
 271                         (level == AMD_DPM_FORCED_LEVEL_AUTO) ? "auto" :
 272                         (level == AMD_DPM_FORCED_LEVEL_LOW) ? "low" :
 273                         (level == AMD_DPM_FORCED_LEVEL_HIGH) ? "high" :
 274                         (level == AMD_DPM_FORCED_LEVEL_MANUAL) ? "manual" :
 275                         (level == AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD) ? "profile_standard" :
 276                         (level == AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK) ? "profile_min_sclk" :
 277                         (level == AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK) ? "profile_min_mclk" :
 278                         (level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK) ? "profile_peak" :
 279                         "unknown");
 280 }
 281
 282 static ssize_t amdgpu_set_dpm_forced_performance_level(struct device *dev,
 283                                                        struct device_attribute *attr,
 284                                                        const char *buf,
 285                                                        size_t count)
 286 {
 287         struct drm_device *ddev = dev_get_drvdata(dev);
 288         struct amdgpu_device *adev = ddev->dev_private;
 289         enum amd_dpm_forced_level level;
 290         enum amd_dpm_forced_level current_level = 0xff;
 291         int ret = 0;
 292
 293         /* Can't force performance level when the card is off */
 294         if  ((adev->flags & AMD_IS_PX) &&
 295              (ddev->switch_power_state != DRM_SWITCH_POWER_ON))
 296                 return -EINVAL;
 297
 298         if (adev->powerplay.pp_funcs->get_performance_level)
 299                 current_level = amdgpu_dpm_get_performance_level(adev);
 300
 301         if (strncmp("low", buf, strlen("low")) == 0) {
 302                 level = AMD_DPM_FORCED_LEVEL_LOW;
 303         } else if (strncmp("high", buf, strlen("high")) == 0) {
 304                 level = AMD_DPM_FORCED_LEVEL_HIGH;
 305         } else if (strncmp("auto", buf, strlen("auto")) == 0) {
 306                 level = AMD_DPM_FORCED_LEVEL_AUTO;
 307         } else if (strncmp("manual", buf, strlen("manual")) == 0) {
 308                 level = AMD_DPM_FORCED_LEVEL_MANUAL;
 309         } else if (strncmp("profile_exit", buf, strlen("profile_exit")) == 0) {
 310                 level = AMD_DPM_FORCED_LEVEL_PROFILE_EXIT;
 311         } else if (strncmp("profile_standard", buf, strlen("profile_standard")) == 0) {
 312                 level = AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD;
 313         } else if (strncmp("profile_min_sclk", buf, strlen("profile_min_sclk")) == 0) {
 314                 level = AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK;
 315         } else if (strncmp("profile_min_mclk", buf, strlen("profile_min_mclk")) == 0) {
 316                 level = AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK;
 317         } else if (strncmp("profile_peak", buf, strlen("profile_peak")) == 0) {
 318                 level = AMD_DPM_FORCED_LEVEL_PROFILE_PEAK;
 319         }  else {
 320                 count = -EINVAL;
 321                 goto fail;
 322         }
 323
 324         if (current_level == level)
 325                 return count;
 326
 327         if (adev->powerplay.pp_funcs->force_performance_level) {
 328                 mutex_lock(&adev->pm.mutex);
 329                 if (adev->pm.dpm.thermal_active) {
 330                         count = -EINVAL;
 331                         mutex_unlock(&adev->pm.mutex);
 332                         goto fail;
 333                 }
 334                 ret = amdgpu_dpm_force_performance_level(adev, level);
 335                 if (ret)
 336                         count = -EINVAL;
 337                 else
 338                         adev->pm.dpm.forced_level = level;
 339                 mutex_unlock(&adev->pm.mutex);
 340         }
 341
 342 fail:
 343         return count;
 344 }
 345
 346 static ssize_t amdgpu_get_pp_num_states(struct device *dev,
 347                 struct device_attribute *attr,
 348                 char *buf)
 349 {
 350         struct drm_device *ddev = dev_get_drvdata(dev);
 351         struct amdgpu_device *adev = ddev->dev_private;
 352         struct pp_states_info data;
 353         int i, buf_len, ret;
 354
 355         if (is_support_sw_smu(adev)) {
 356                 ret = smu_get_power_num_states(&adev->smu, &data);
 357                 if (ret)
 358                         return ret;
 359         } else if (adev->powerplay.pp_funcs->get_pp_num_states)
 360                 amdgpu_dpm_get_pp_num_states(adev, &data);
 361
 362         buf_len = snprintf(buf, PAGE_SIZE, "states: %d\n", data.nums);
 363         for (i = 0; i < data.nums; i++)
 364                 buf_len += snprintf(buf + buf_len, PAGE_SIZE, "%d %s\n", i,
 365                                 (data.states[i] == POWER_STATE_TYPE_INTERNAL_BOOT) ? "boot" :
 366                                 (data.states[i] == POWER_STATE_TYPE_BATTERY) ? "battery" :
 367                                 (data.states[i] == POWER_STATE_TYPE_BALANCED) ? "balanced" :
 368                                 (data.states[i] == POWER_STATE_TYPE_PERFORMANCE) ? "performance" : "default");
 369
 370         return buf_len;
 371 }
 372
 373 static ssize_t amdgpu_get_pp_cur_state(struct device *dev,
 374                 struct device_attribute *attr,
 375                 char *buf)
 376 {
 377         struct drm_device *ddev = dev_get_drvdata(dev);
 378         struct amdgpu_device *adev = ddev->dev_private;
 379         struct pp_states_info data;
 380         struct smu_context *smu = &adev->smu;
 381         enum amd_pm_state_type pm = 0;
 382         int i = 0, ret = 0;
 383
 384         if (is_support_sw_smu(adev)) {
 385                 pm = smu_get_current_power_state(smu);
 386                 ret = smu_get_power_num_states(smu, &data);
 387                 if (ret)
 388                         return ret;
 389         } else if (adev->powerplay.pp_funcs->get_current_power_state
 390                  && adev->powerplay.pp_funcs->get_pp_num_states) {
 391                 pm = amdgpu_dpm_get_current_power_state(adev);
 392                 amdgpu_dpm_get_pp_num_states(adev, &data);
 393         }
 394
 395         for (i = 0; i < data.nums; i++) {
 396                 if (pm == data.states[i])
 397                         break;
 398         }
 399
 400         if (i == data.nums)
 401                 i = -EINVAL;
 402
 403         return snprintf(buf, PAGE_SIZE, "%d\n", i);
 404 }
 405
 406 static ssize_t amdgpu_get_pp_force_state(struct device *dev,
 407                 struct device_attribute *attr,
 408                 char *buf)
 409 {
 410         struct drm_device *ddev = dev_get_drvdata(dev);
 411         struct amdgpu_device *adev = ddev->dev_private;
 412
 413         if (adev->pp_force_state_enabled)
 414                 return amdgpu_get_pp_cur_state(dev, attr, buf);
 415         else
 416                 return snprintf(buf, PAGE_SIZE, "\n");
 417 }
 418
 419 static ssize_t amdgpu_set_pp_force_state(struct device *dev,
 420                 struct device_attribute *attr,
 421                 const char *buf,
 422                 size_t count)
 423 {
 424         struct drm_device *ddev = dev_get_drvdata(dev);
 425         struct amdgpu_device *adev = ddev->dev_private;
 426         enum amd_pm_state_type state = 0;
 427         unsigned long idx;
 428         int ret;
 429
 430         if (strlen(buf) == 1)
 431                 adev->pp_force_state_enabled = false;
 432         else if (is_support_sw_smu(adev))
 433                 adev->pp_force_state_enabled = false;
 434         else if (adev->powerplay.pp_funcs->dispatch_tasks &&
 435                         adev->powerplay.pp_funcs->get_pp_num_states) {
 436                 struct pp_states_info data;
 437
 438                 ret = kstrtoul(buf, 0, &idx);
 439                 if (ret || idx >= ARRAY_SIZE(data.states)) {
 440                         count = -EINVAL;
 441                         goto fail;
 442                 }
 443                 idx = array_index_nospec(idx, ARRAY_SIZE(data.states));
 444
 445                 amdgpu_dpm_get_pp_num_states(adev, &data);
 446                 state = data.states[idx];
 447                 /* only set user selected power states */
 448                 if (state != POWER_STATE_TYPE_INTERNAL_BOOT &&
 449                     state != POWER_STATE_TYPE_DEFAULT) {
 450                         amdgpu_dpm_dispatch_task(adev,
 451                                         AMD_PP_TASK_ENABLE_USER_STATE, &state);
 452                         adev->pp_force_state_enabled = true;
 453                 }
 454         }
 455 fail:
 456         return count;
 457 }
 458
 459 /**
 460  * DOC: pp_table
 461  *
 462  * The amdgpu driver provides a sysfs API for uploading new powerplay
 463  * tables.  The file pp_table is used for this.  Reading the file
 464  * will dump the current power play table.  Writing to the file
 465  * will attempt to upload a new powerplay table and re-initialize
 466  * powerplay using that new table.
 467  *
 468  */
 469
 470 static ssize_t amdgpu_get_pp_table(struct device *dev,
 471                 struct device_attribute *attr,
 472                 char *buf)
 473 {
 474         struct drm_device *ddev = dev_get_drvdata(dev);
 475         struct amdgpu_device *adev = ddev->dev_private;
 476         char *table = NULL;
 477         int size;
 478
 479         if (is_support_sw_smu(adev)) {
 480                 size = smu_sys_get_pp_table(&adev->smu, (void **)&table);
 481                 if (size < 0)
 482                         return size;
 483         }
 484         else if (adev->powerplay.pp_funcs->get_pp_table)
 485                 size = amdgpu_dpm_get_pp_table(adev, &table);
 486         else
 487                 return 0;
 488
 489         if (size >= PAGE_SIZE)
 490                 size = PAGE_SIZE - 1;
 491
 492         memcpy(buf, table, size);
 493
 494         return size;
 495 }
 496
 497 static ssize_t amdgpu_set_pp_table(struct device *dev,
 498                 struct device_attribute *attr,
 499                 const char *buf,
 500                 size_t count)
 501 {
 502         struct drm_device *ddev = dev_get_drvdata(dev);
 503         struct amdgpu_device *adev = ddev->dev_private;
 504         int ret = 0;
 505
 506         if (is_support_sw_smu(adev)) {
 507                 ret = smu_sys_set_pp_table(&adev->smu, (void *)buf, count);
 508                 if (ret)
 509                         return ret;
 510         } else if (adev->powerplay.pp_funcs->set_pp_table)
 511                 amdgpu_dpm_set_pp_table(adev, buf, count);
 512
 513         return count;
 514 }
 515
 516 /**
 517  * DOC: pp_od_clk_voltage
 518  *
 519  * The amdgpu driver provides a sysfs API for adjusting the clocks and voltages
 520  * in each power level within a power state.  The pp_od_clk_voltage is used for
 521  * this.
 522  *
 523  * < For Vega10 and previous ASICs >
 524  *
 525  * Reading the file will display:
 526  *
 527  * - a list of engine clock levels and voltages labeled OD_SCLK
 528  *
 529  * - a list of memory clock levels and voltages labeled OD_MCLK
 530  *
 531  * - a list of valid ranges for sclk, mclk, and voltage labeled OD_RANGE
 532  *
 533  * To manually adjust these settings, first select manual using
 534  * power_dpm_force_performance_level. Enter a new value for each
 535  * level by writing a string that contains "s/m level clock voltage" to
 536  * the file.  E.g., "s 1 500 820" will update sclk level 1 to be 500 MHz
 537  * at 820 mV; "m 0 350 810" will update mclk level 0 to be 350 MHz at
 538  * 810 mV.  When you have edited all of the states as needed, write
 539  * "c" (commit) to the file to commit your changes.  If you want to reset to the
 540  * default power levels, write "r" (reset) to the file to reset them.
 541  *
 542  *
 543  * < For Vega20 >
 544  *
 545  * Reading the file will display:
 546  *
 547  * - minimum and maximum engine clock labeled OD_SCLK
 548  *
 549  * - maximum memory clock labeled OD_MCLK
 550  *
 551  * - three <frequency, voltage> points labeled OD_VDDC_CURVE.
 552  *   They can be used to calibrate the sclk voltage curve.
 553  *
 554  * - a list of valid ranges for sclk, mclk, and voltage curve points
 555  *   labeled OD_RANGE
 556  *
 557  * To manually adjust these settings:
 558  *
 559  * - First select manual using power_dpm_force_performance_level
 560  *
 561  * - For clock frequency setting, enter a new value by writing a
 562  *   string that contains "s/m index clock" to the file. The index
 563  *   should be 0 if to set minimum clock. And 1 if to set maximum
 564  *   clock. E.g., "s 0 500" will update minimum sclk to be 500 MHz.
 565  *   "m 1 800" will update maximum mclk to be 800Mhz.
 566  *
 567  *   For sclk voltage curve, enter the new values by writing a
 568  *   string that contains "vc point clock voltage" to the file. The
 569  *   points are indexed by 0, 1 and 2. E.g., "vc 0 300 600" will
 570  *   update point1 with clock set as 300Mhz and voltage as
 571  *   600mV. "vc 2 1000 1000" will update point3 with clock set
 572  *   as 1000Mhz and voltage 1000mV.
 573  *
 574  * - When you have edited all of the states as needed, write "c" (commit)
 575  *   to the file to commit your changes
 576  *
 577  * - If you want to reset to the default power levels, write "r" (reset)
 578  *   to the file to reset them
 579  *
 580  */
 581
 582 static ssize_t amdgpu_set_pp_od_clk_voltage(struct device *dev,
 583                 struct device_attribute *attr,
 584                 const char *buf,
 585                 size_t count)
 586 {
 587         struct drm_device *ddev = dev_get_drvdata(dev);
 588         struct amdgpu_device *adev = ddev->dev_private;
 589         int ret;
 590         uint32_t parameter_size = 0;
 591         long parameter[64];
 592         char buf_cpy[128];
 593         char *tmp_str;
 594         char *sub_str;
 595         const char delimiter[3] = {' ', '\n', '\0'};
 596         uint32_t type;
 597
 598         if (count > 127)
 599                 return -EINVAL;
 600
 601         if (*buf == 's')
 602                 type = PP_OD_EDIT_SCLK_VDDC_TABLE;
 603         else if (*buf == 'm')
 604                 type = PP_OD_EDIT_MCLK_VDDC_TABLE;
 605         else if(*buf == 'r')
 606                 type = PP_OD_RESTORE_DEFAULT_TABLE;
 607         else if (*buf == 'c')
 608                 type = PP_OD_COMMIT_DPM_TABLE;
 609         else if (!strncmp(buf, "vc", 2))
 610                 type = PP_OD_EDIT_VDDC_CURVE;
 611         else
 612                 return -EINVAL;
 613
 614         memcpy(buf_cpy, buf, count+1);
 615
 616         tmp_str = buf_cpy;
 617
 618         if (type == PP_OD_EDIT_VDDC_CURVE)
 619                 tmp_str++;
 620         while (isspace(*++tmp_str));
 621
 622         while (tmp_str[0]) {
 623                 sub_str = strsep(&tmp_str, delimiter);
 624                 ret = kstrtol(sub_str, 0, &parameter[parameter_size]);
 625                 if (ret)
 626                         return -EINVAL;
 627                 parameter_size++;
 628
 629                 while (isspace(*tmp_str))
 630                         tmp_str++;
 631         }
 632
 633         if (adev->powerplay.pp_funcs->odn_edit_dpm_table)
 634                 ret = amdgpu_dpm_odn_edit_dpm_table(adev, type,
 635                                                 parameter, parameter_size);
 636
 637         if (ret)
 638                 return -EINVAL;
 639
 640         if (type == PP_OD_COMMIT_DPM_TABLE) {
 641                 if (adev->powerplay.pp_funcs->dispatch_tasks) {
 642                         amdgpu_dpm_dispatch_task(adev, AMD_PP_TASK_READJUST_POWER_STATE, NULL);
 643                         return count;
 644                 } else {
 645                         return -EINVAL;
 646                 }
 647         }
 648
 649         return count;
 650 }
 651
 652 static ssize_t amdgpu_get_pp_od_clk_voltage(struct device *dev,
 653                 struct device_attribute *attr,
 654                 char *buf)
 655 {
 656         struct drm_device *ddev = dev_get_drvdata(dev);
 657         struct amdgpu_device *adev = ddev->dev_private;
 658         uint32_t size = 0;
 659
 660         if (adev->powerplay.pp_funcs->print_clock_levels) {
 661                 size = amdgpu_dpm_print_clock_levels(adev, OD_SCLK, buf);
 662                 size += amdgpu_dpm_print_clock_levels(adev, OD_MCLK, buf+size);
 663                 size += amdgpu_dpm_print_clock_levels(adev, OD_VDDC_CURVE, buf+size);
 664                 size += amdgpu_dpm_print_clock_levels(adev, OD_RANGE, buf+size);
 665                 return size;
 666         } else {
 667                 return snprintf(buf, PAGE_SIZE, "\n");
 668         }
 669
 670 }
 671
 672 /**
 673  * DOC: ppfeatures
 674  *
 675  * The amdgpu driver provides a sysfs API for adjusting what powerplay
 676  * features to be enabled. The file ppfeatures is used for this. And
 677  * this is only available for Vega10 and later dGPUs.
 678  *
 679  * Reading back the file will show you the followings:
 680  * - Current ppfeature masks
 681  * - List of the all supported powerplay features with their naming,
 682  *   bitmasks and enablement status('Y'/'N' means "enabled"/"disabled").
 683  *
 684  * To manually enable or disable a specific feature, just set or clear
 685  * the corresponding bit from original ppfeature masks and input the
 686  * new ppfeature masks.
 687  */
 688 static ssize_t amdgpu_set_ppfeature_status(struct device *dev,
 689                 struct device_attribute *attr,
 690                 const char *buf,
 691                 size_t count)
 692 {
 693         struct drm_device *ddev = dev_get_drvdata(dev);
 694         struct amdgpu_device *adev = ddev->dev_private;
 695         uint64_t featuremask;
 696         int ret;
 697
 698         ret = kstrtou64(buf, 0, &featuremask);
 699         if (ret)
 700                 return -EINVAL;
 701
 702         pr_debug("featuremask = 0x%llx\n", featuremask);
 703
 704         if (adev->powerplay.pp_funcs->set_ppfeature_status) {
 705                 ret = amdgpu_dpm_set_ppfeature_status(adev, featuremask);
 706                 if (ret)
 707                         return -EINVAL;
 708         }
 709
 710         return count;
 711 }
 712
 713 static ssize_t amdgpu_get_ppfeature_status(struct device *dev,
 714                 struct device_attribute *attr,
 715                 char *buf)
 716 {
 717         struct drm_device *ddev = dev_get_drvdata(dev);
 718         struct amdgpu_device *adev = ddev->dev_private;
 719
 720         if (adev->powerplay.pp_funcs->get_ppfeature_status)
 721                 return amdgpu_dpm_get_ppfeature_status(adev, buf);
 722
 723         return snprintf(buf, PAGE_SIZE, "\n");
 724 }
 725
 726 /**
 727  * DOC: pp_dpm_sclk pp_dpm_mclk pp_dpm_socclk pp_dpm_fclk pp_dpm_dcefclk
 728  * pp_dpm_pcie
 729  *
 730  * The amdgpu driver provides a sysfs API for adjusting what power levels
 731  * are enabled for a given power state.  The files pp_dpm_sclk, pp_dpm_mclk,
 732  * pp_dpm_socclk, pp_dpm_fclk, pp_dpm_dcefclk and pp_dpm_pcie are used for
 733  * this.
 734  *
 735  * pp_dpm_socclk and pp_dpm_dcefclk interfaces are only available for
 736  * Vega10 and later ASICs.
 737  * pp_dpm_fclk interface is only available for Vega20 and later ASICs.
 738  *
 739  * Reading back the files will show you the available power levels within
 740  * the power state and the clock information for those levels.
 741  *
 742  * To manually adjust these states, first select manual using
 743  * power_dpm_force_performance_level.
 744  * Secondly,Enter a new value for each level by inputing a string that
 745  * contains " echo xx xx xx > pp_dpm_sclk/mclk/pcie"
 746  * E.g., echo 4 5 6 to > pp_dpm_sclk will enable sclk levels 4, 5, and 6.
 747  *
 748  * NOTE: change to the dcefclk max dpm level is not supported now
 749  */
 750
 751 static ssize_t amdgpu_get_pp_dpm_sclk(struct device *dev,
 752                 struct device_attribute *attr,
 753                 char *buf)
 754 {
 755         struct drm_device *ddev = dev_get_drvdata(dev);
 756         struct amdgpu_device *adev = ddev->dev_private;
 757
 758         if (is_support_sw_smu(adev))
 759                 return smu_print_clk_levels(&adev->smu, PP_SCLK, buf);
 760         else if (adev->powerplay.pp_funcs->print_clock_levels)
 761                 return amdgpu_dpm_print_clock_levels(adev, PP_SCLK, buf);
 762         else
 763                 return snprintf(buf, PAGE_SIZE, "\n");
 764 }
 765
 766 /*
 767  * Worst case: 32 bits individually specified, in octal at 12 characters
 768  * per line (+1 for \n).
 769  */
 770 #define AMDGPU_MASK_BUF_MAX     (32 * 13)
 771
 772 static ssize_t amdgpu_read_mask(const char *buf, size_t count, uint32_t *mask)
 773 {
 774         int ret;
 775         long level;
 776         char *sub_str = NULL;
 777         char *tmp;
 778         char buf_cpy[AMDGPU_MASK_BUF_MAX + 1];
 779         const char delimiter[3] = {' ', '\n', '\0'};
 780         size_t bytes;
 781
 782         *mask = 0;
 783
 784         bytes = min(count, sizeof(buf_cpy) - 1);
 785         memcpy(buf_cpy, buf, bytes);
 786         buf_cpy[bytes] = '\0';
 787         tmp = buf_cpy;
 788         while (tmp[0]) {
 789                 sub_str = strsep(&tmp, delimiter);
 790                 if (strlen(sub_str)) {
 791                         ret = kstrtol(sub_str, 0, &level);
 792                         if (ret)
 793                                 return -EINVAL;
 794                         *mask |= 1 << level;
 795                 } else
 796                         break;
 797         }
 798
 799         return 0;
 800 }
 801
 802 static ssize_t amdgpu_set_pp_dpm_sclk(struct device *dev,
 803                 struct device_attribute *attr,
 804                 const char *buf,
 805                 size_t count)
 806 {
 807         struct drm_device *ddev = dev_get_drvdata(dev);
 808         struct amdgpu_device *adev = ddev->dev_private;
 809         int ret;
 810         uint32_t mask = 0;
 811
 812         ret = amdgpu_read_mask(buf, count, &mask);
 813         if (ret)
 814                 return ret;
 815
 816         if (is_support_sw_smu(adev))
 817                 ret = smu_force_clk_levels(&adev->smu, PP_SCLK, mask);
 818         else if (adev->powerplay.pp_funcs->force_clock_level)
 819                 ret = amdgpu_dpm_force_clock_level(adev, PP_SCLK, mask);
 820
 821         if (ret)
 822                 return -EINVAL;
 823
 824         return count;
 825 }
 826
 827 static ssize_t amdgpu_get_pp_dpm_mclk(struct device *dev,
 828                 struct device_attribute *attr,
 829                 char *buf)
 830 {
 831         struct drm_device *ddev = dev_get_drvdata(dev);
 832         struct amdgpu_device *adev = ddev->dev_private;
 833
 834         if (is_support_sw_smu(adev))
 835                 return smu_print_clk_levels(&adev->smu, PP_MCLK, buf);
 836         else if (adev->powerplay.pp_funcs->print_clock_levels)
 837                 return amdgpu_dpm_print_clock_levels(adev, PP_MCLK, buf);
 838         else
 839                 return snprintf(buf, PAGE_SIZE, "\n");
 840 }
 841
 842 static ssize_t amdgpu_set_pp_dpm_mclk(struct device *dev,
 843                 struct device_attribute *attr,
 844                 const char *buf,
 845                 size_t count)
 846 {
 847         struct drm_device *ddev = dev_get_drvdata(dev);
 848         struct amdgpu_device *adev = ddev->dev_private;
 849         int ret;
 850         uint32_t mask = 0;
 851
 852         ret = amdgpu_read_mask(buf, count, &mask);
 853         if (ret)
 854                 return ret;
 855
 856         if (is_support_sw_smu(adev))
 857                 ret = smu_force_clk_levels(&adev->smu, PP_MCLK, mask);
 858         else if (adev->powerplay.pp_funcs->force_clock_level)
 859                 ret = amdgpu_dpm_force_clock_level(adev, PP_MCLK, mask);
 860
 861         if (ret)
 862                 return -EINVAL;
 863
 864         return count;
 865 }
 866
 867 static ssize_t amdgpu_get_pp_dpm_socclk(struct device *dev,
 868                 struct device_attribute *attr,
 869                 char *buf)
 870 {
 871         struct drm_device *ddev = dev_get_drvdata(dev);
 872         struct amdgpu_device *adev = ddev->dev_private;
 873
 874         if (adev->powerplay.pp_funcs->print_clock_levels)
 875                 return amdgpu_dpm_print_clock_levels(adev, PP_SOCCLK, buf);
 876         else
 877                 return snprintf(buf, PAGE_SIZE, "\n");
 878 }
 879
 880 static ssize_t amdgpu_set_pp_dpm_socclk(struct device *dev,
 881                 struct device_attribute *attr,
 882                 const char *buf,
 883                 size_t count)
 884 {
 885         struct drm_device *ddev = dev_get_drvdata(dev);
 886         struct amdgpu_device *adev = ddev->dev_private;
 887         int ret;
 888         uint32_t mask = 0;
 889
 890         ret = amdgpu_read_mask(buf, count, &mask);
 891         if (ret)
 892                 return ret;
 893
 894         if (adev->powerplay.pp_funcs->force_clock_level)
 895                 ret = amdgpu_dpm_force_clock_level(adev, PP_SOCCLK, mask);
 896
 897         if (ret)
 898                 return -EINVAL;
 899
 900         return count;
 901 }
 902
 903 static ssize_t amdgpu_get_pp_dpm_fclk(struct device *dev,
 904                 struct device_attribute *attr,
 905                 char *buf)
 906 {
 907         struct drm_device *ddev = dev_get_drvdata(dev);
 908         struct amdgpu_device *adev = ddev->dev_private;
 909
 910         if (adev->powerplay.pp_funcs->print_clock_levels)
 911                 return amdgpu_dpm_print_clock_levels(adev, PP_FCLK, buf);
 912         else
 913                 return snprintf(buf, PAGE_SIZE, "\n");
 914 }
 915
 916 static ssize_t amdgpu_set_pp_dpm_fclk(struct device *dev,
 917                 struct device_attribute *attr,
 918                 const char *buf,
 919                 size_t count)
 920 {
 921         struct drm_device *ddev = dev_get_drvdata(dev);
 922         struct amdgpu_device *adev = ddev->dev_private;
 923         int ret;
 924         uint32_t mask = 0;
 925
 926         ret = amdgpu_read_mask(buf, count, &mask);
 927         if (ret)
 928                 return ret;
 929
 930         if (adev->powerplay.pp_funcs->force_clock_level)
 931                 ret = amdgpu_dpm_force_clock_level(adev, PP_FCLK, mask);
 932
 933         if (ret)
 934                 return -EINVAL;
 935
 936         return count;
 937 }
 938
 939 static ssize_t amdgpu_get_pp_dpm_dcefclk(struct device *dev,
 940                 struct device_attribute *attr,
 941                 char *buf)
 942 {
 943         struct drm_device *ddev = dev_get_drvdata(dev);
 944         struct amdgpu_device *adev = ddev->dev_private;
 945
 946         if (adev->powerplay.pp_funcs->print_clock_levels)
 947                 return amdgpu_dpm_print_clock_levels(adev, PP_DCEFCLK, buf);
 948         else
 949                 return snprintf(buf, PAGE_SIZE, "\n");
 950 }
 951
 952 static ssize_t amdgpu_set_pp_dpm_dcefclk(struct device *dev,
 953                 struct device_attribute *attr,
 954                 const char *buf,
 955                 size_t count)
 956 {
 957         struct drm_device *ddev = dev_get_drvdata(dev);
 958         struct amdgpu_device *adev = ddev->dev_private;
 959         int ret;
 960         uint32_t mask = 0;
 961
 962         ret = amdgpu_read_mask(buf, count, &mask);
 963         if (ret)
 964                 return ret;
 965
 966         if (adev->powerplay.pp_funcs->force_clock_level)
 967                 ret = amdgpu_dpm_force_clock_level(adev, PP_DCEFCLK, mask);
 968
 969         if (ret)
 970                 return -EINVAL;
 971
 972         return count;
 973 }
 974
 975 static ssize_t amdgpu_get_pp_dpm_pcie(struct device *dev,
 976                 struct device_attribute *attr,
 977                 char *buf)
 978 {
 979         struct drm_device *ddev = dev_get_drvdata(dev);
 980         struct amdgpu_device *adev = ddev->dev_private;
 981
 982         if (adev->powerplay.pp_funcs->print_clock_levels)
 983                 return amdgpu_dpm_print_clock_levels(adev, PP_PCIE, buf);
 984         else
 985                 return snprintf(buf, PAGE_SIZE, "\n");
 986 }
 987
 988 static ssize_t amdgpu_set_pp_dpm_pcie(struct device *dev,
 989                 struct device_attribute *attr,
 990                 const char *buf,
 991                 size_t count)
 992 {
 993         struct drm_device *ddev = dev_get_drvdata(dev);
 994         struct amdgpu_device *adev = ddev->dev_private;
 995         int ret;
 996         uint32_t mask = 0;
 997
 998         ret = amdgpu_read_mask(buf, count, &mask);
 999         if (ret)
1000                 return ret;
1001
1002         if (adev->powerplay.pp_funcs->force_clock_level)
1003                 ret = amdgpu_dpm_force_clock_level(adev, PP_PCIE, mask);
1004
1005         if (ret)
1006                 return -EINVAL;
1007
1008         return count;
1009 }
1010
1011 static ssize_t amdgpu_get_pp_sclk_od(struct device *dev,
1012                 struct device_attribute *attr,
1013                 char *buf)
1014 {
1015         struct drm_device *ddev = dev_get_drvdata(dev);
1016         struct amdgpu_device *adev = ddev->dev_private;
1017         uint32_t value = 0;
1018
1019         if (adev->powerplay.pp_funcs->get_sclk_od)
1020                 value = amdgpu_dpm_get_sclk_od(adev);
1021
1022         return snprintf(buf, PAGE_SIZE, "%d\n", value);
1023 }
1024
1025 static ssize_t amdgpu_set_pp_sclk_od(struct device *dev,
1026                 struct device_attribute *attr,
1027                 const char *buf,
1028                 size_t count)
1029 {
1030         struct drm_device *ddev = dev_get_drvdata(dev);
1031         struct amdgpu_device *adev = ddev->dev_private;
1032         int ret;
1033         long int value;
1034
1035         ret = kstrtol(buf, 0, &value);
1036
1037         if (ret) {
1038                 count = -EINVAL;
1039                 goto fail;
1040         }
1041         if (adev->powerplay.pp_funcs->set_sclk_od)
1042                 amdgpu_dpm_set_sclk_od(adev, (uint32_t)value);
1043
1044         if (adev->powerplay.pp_funcs->dispatch_tasks) {
1045                 amdgpu_dpm_dispatch_task(adev, AMD_PP_TASK_READJUST_POWER_STATE, NULL);
1046         } else {
1047                 adev->pm.dpm.current_ps = adev->pm.dpm.boot_ps;
1048                 amdgpu_pm_compute_clocks(adev);
1049         }
1050
1051 fail:
1052         return count;
1053 }
1054
1055 static ssize_t amdgpu_get_pp_mclk_od(struct device *dev,
1056                 struct device_attribute *attr,
1057                 char *buf)
1058 {
1059         struct drm_device *ddev = dev_get_drvdata(dev);
1060         struct amdgpu_device *adev = ddev->dev_private;
1061         uint32_t value = 0;
1062
1063         if (adev->powerplay.pp_funcs->get_mclk_od)
1064                 value = amdgpu_dpm_get_mclk_od(adev);
1065
1066         return snprintf(buf, PAGE_SIZE, "%d\n", value);
1067 }
1068
1069 static ssize_t amdgpu_set_pp_mclk_od(struct device *dev,
1070                 struct device_attribute *attr,
1071                 const char *buf,
1072                 size_t count)
1073 {
1074         struct drm_device *ddev = dev_get_drvdata(dev);
1075         struct amdgpu_device *adev = ddev->dev_private;
1076         int ret;
1077         long int value;
1078
1079         ret = kstrtol(buf, 0, &value);
1080
1081         if (ret) {
1082                 count = -EINVAL;
1083                 goto fail;
1084         }
1085         if (adev->powerplay.pp_funcs->set_mclk_od)
1086                 amdgpu_dpm_set_mclk_od(adev, (uint32_t)value);
1087
1088         if (adev->powerplay.pp_funcs->dispatch_tasks) {
1089                 amdgpu_dpm_dispatch_task(adev, AMD_PP_TASK_READJUST_POWER_STATE, NULL);
1090         } else {
1091                 adev->pm.dpm.current_ps = adev->pm.dpm.boot_ps;
1092                 amdgpu_pm_compute_clocks(adev);
1093         }
1094
1095 fail:
1096         return count;
1097 }
1098
1099 /**
1100  * DOC: pp_power_profile_mode
1101  *
1102  * The amdgpu driver provides a sysfs API for adjusting the heuristics
1103  * related to switching between power levels in a power state.  The file
1104  * pp_power_profile_mode is used for this.
1105  *
1106  * Reading this file outputs a list of all of the predefined power profiles
1107  * and the relevant heuristics settings for that profile.
1108  *
1109  * To select a profile or create a custom profile, first select manual using
1110  * power_dpm_force_performance_level.  Writing the number of a predefined
1111  * profile to pp_power_profile_mode will enable those heuristics.  To
1112  * create a custom set of heuristics, write a string of numbers to the file
1113  * starting with the number of the custom profile along with a setting
1114  * for each heuristic parameter.  Due to differences across asic families
1115  * the heuristic parameters vary from family to family.
1116  *
1117  */
1118
1119 static ssize_t amdgpu_get_pp_power_profile_mode(struct device *dev,
1120                 struct device_attribute *attr,
1121                 char *buf)
1122 {
1123         struct drm_device *ddev = dev_get_drvdata(dev);
1124         struct amdgpu_device *adev = ddev->dev_private;
1125
1126         if (adev->powerplay.pp_funcs->get_power_profile_mode)
1127                 return amdgpu_dpm_get_power_profile_mode(adev, buf);
1128
1129         return snprintf(buf, PAGE_SIZE, "\n");
1130 }
1131
1132
1133 static ssize_t amdgpu_set_pp_power_profile_mode(struct device *dev,
1134                 struct device_attribute *attr,
1135                 const char *buf,
1136                 size_t count)
1137 {
1138         int ret = 0xff;
1139         struct drm_device *ddev = dev_get_drvdata(dev);
1140         struct amdgpu_device *adev = ddev->dev_private;
1141         uint32_t parameter_size = 0;
1142         long parameter[64];
1143         char *sub_str, buf_cpy[128];
1144         char *tmp_str;
1145         uint32_t i = 0;
1146         char tmp[2];
1147         long int profile_mode = 0;
1148         const char delimiter[3] = {' ', '\n', '\0'};
1149
1150         tmp[0] = *(buf);
1151         tmp[1] = '\0';
1152         ret = kstrtol(tmp, 0, &profile_mode);
1153         if (ret)
1154                 goto fail;
1155
1156         if (profile_mode == PP_SMC_POWER_PROFILE_CUSTOM) {
1157                 if (count < 2 || count > 127)
1158                         return -EINVAL;
1159                 while (isspace(*++buf))
1160                         i++;
1161                 memcpy(buf_cpy, buf, count-i);
1162                 tmp_str = buf_cpy;
1163                 while (tmp_str[0]) {
1164                         sub_str = strsep(&tmp_str, delimiter);
1165                         ret = kstrtol(sub_str, 0, &parameter[parameter_size]);
1166                         if (ret) {
1167                                 count = -EINVAL;
1168                                 goto fail;
1169                         }
1170                         parameter_size++;
1171                         while (isspace(*tmp_str))
1172                                 tmp_str++;
1173                 }
1174         }
1175         parameter[parameter_size] = profile_mode;
1176         if (adev->powerplay.pp_funcs->set_power_profile_mode)
1177                 ret = amdgpu_dpm_set_power_profile_mode(adev, parameter, parameter_size);
1178
1179         if (!ret)
1180                 return count;
1181 fail:
1182         return -EINVAL;
1183 }
1184
1185 /**
1186  * DOC: busy_percent
1187  *
1188  * The amdgpu driver provides a sysfs API for reading how busy the GPU
1189  * is as a percentage.  The file gpu_busy_percent is used for this.
1190  * The SMU firmware computes a percentage of load based on the
1191  * aggregate activity level in the IP cores.
1192  */
1193 static ssize_t amdgpu_get_busy_percent(struct device *dev,
1194                 struct device_attribute *attr,
1195                 char *buf)
1196 {
1197         struct drm_device *ddev = dev_get_drvdata(dev);
1198         struct amdgpu_device *adev = ddev->dev_private;
1199         int r, value, size = sizeof(value);
1200
1201         /* read the IP busy sensor */
1202         r = amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_GPU_LOAD,
1203                                    (void *)&value, &size);
1204
1205         if (r)
1206                 return r;
1207
1208         return snprintf(buf, PAGE_SIZE, "%d\n", value);
1209 }
1210
1211 /**
1212  * DOC: pcie_bw
1213  *
1214  * The amdgpu driver provides a sysfs API for estimating how much data
1215  * has been received and sent by the GPU in the last second through PCIe.
1216  * The file pcie_bw is used for this.
1217  * The Perf counters count the number of received and sent messages and return
1218  * those values, as well as the maximum payload size of a PCIe packet (mps).
1219  * Note that it is not possible to easily and quickly obtain the size of each
1220  * packet transmitted, so we output the max payload size (mps) to allow for
1221  * quick estimation of the PCIe bandwidth usage
1222  */
1223 static ssize_t amdgpu_get_pcie_bw(struct device *dev,
1224                 struct device_attribute *attr,
1225                 char *buf)
1226 {
1227         struct drm_device *ddev = dev_get_drvdata(dev);
1228         struct amdgpu_device *adev = ddev->dev_private;
1229         uint64_t count0, count1;
1230
1231         amdgpu_asic_get_pcie_usage(adev, &count0, &count1);
1232         return snprintf(buf, PAGE_SIZE, "%llu %llu %i\n",
1233                         count0, count1, pcie_get_mps(adev->pdev));
1234 }
1235
1236 static DEVICE_ATTR(power_dpm_state, S_IRUGO | S_IWUSR, amdgpu_get_dpm_state, amdgpu_set_dpm_state);
1237 static DEVICE_ATTR(power_dpm_force_performance_level, S_IRUGO | S_IWUSR,
1238                    amdgpu_get_dpm_forced_performance_level,
1239                    amdgpu_set_dpm_forced_performance_level);
1240 static DEVICE_ATTR(pp_num_states, S_IRUGO, amdgpu_get_pp_num_states, NULL);
1241 static DEVICE_ATTR(pp_cur_state, S_IRUGO, amdgpu_get_pp_cur_state, NULL);
1242 static DEVICE_ATTR(pp_force_state, S_IRUGO | S_IWUSR,
1243                 amdgpu_get_pp_force_state,
1244                 amdgpu_set_pp_force_state);
1245 static DEVICE_ATTR(pp_table, S_IRUGO | S_IWUSR,
1246                 amdgpu_get_pp_table,
1247                 amdgpu_set_pp_table);
1248 static DEVICE_ATTR(pp_dpm_sclk, S_IRUGO | S_IWUSR,
1249                 amdgpu_get_pp_dpm_sclk,
1250                 amdgpu_set_pp_dpm_sclk);
1251 static DEVICE_ATTR(pp_dpm_mclk, S_IRUGO | S_IWUSR,
1252                 amdgpu_get_pp_dpm_mclk,
1253                 amdgpu_set_pp_dpm_mclk);
1254 static DEVICE_ATTR(pp_dpm_socclk, S_IRUGO | S_IWUSR,
1255                 amdgpu_get_pp_dpm_socclk,
1256                 amdgpu_set_pp_dpm_socclk);
1257 static DEVICE_ATTR(pp_dpm_fclk, S_IRUGO | S_IWUSR,
1258                 amdgpu_get_pp_dpm_fclk,
1259                 amdgpu_set_pp_dpm_fclk);
1260 static DEVICE_ATTR(pp_dpm_dcefclk, S_IRUGO | S_IWUSR,
1261                 amdgpu_get_pp_dpm_dcefclk,
1262                 amdgpu_set_pp_dpm_dcefclk);
1263 static DEVICE_ATTR(pp_dpm_pcie, S_IRUGO | S_IWUSR,
1264                 amdgpu_get_pp_dpm_pcie,
1265                 amdgpu_set_pp_dpm_pcie);
1266 static DEVICE_ATTR(pp_sclk_od, S_IRUGO | S_IWUSR,
1267                 amdgpu_get_pp_sclk_od,
1268                 amdgpu_set_pp_sclk_od);
1269 static DEVICE_ATTR(pp_mclk_od, S_IRUGO | S_IWUSR,
1270                 amdgpu_get_pp_mclk_od,
1271                 amdgpu_set_pp_mclk_od);
1272 static DEVICE_ATTR(pp_power_profile_mode, S_IRUGO | S_IWUSR,
1273                 amdgpu_get_pp_power_profile_mode,
1274                 amdgpu_set_pp_power_profile_mode);
1275 static DEVICE_ATTR(pp_od_clk_voltage, S_IRUGO | S_IWUSR,
1276                 amdgpu_get_pp_od_clk_voltage,
1277                 amdgpu_set_pp_od_clk_voltage);
1278 static DEVICE_ATTR(gpu_busy_percent, S_IRUGO,
1279                 amdgpu_get_busy_percent, NULL);
1280 static DEVICE_ATTR(pcie_bw, S_IRUGO, amdgpu_get_pcie_bw, NULL);
1281 static DEVICE_ATTR(ppfeatures, S_IRUGO | S_IWUSR,
1282                 amdgpu_get_ppfeature_status,
1283                 amdgpu_set_ppfeature_status);
1284
1285 static ssize_t amdgpu_hwmon_show_temp(struct device *dev,
1286                                       struct device_attribute *attr,
1287                                       char *buf)
1288 {
1289         struct amdgpu_device *adev = dev_get_drvdata(dev);
1290         struct drm_device *ddev = adev->ddev;
1291         int r, temp, size = sizeof(temp);
1292
1293         /* Can't get temperature when the card is off */
1294         if  ((adev->flags & AMD_IS_PX) &&
1295              (ddev->switch_power_state != DRM_SWITCH_POWER_ON))
1296                 return -EINVAL;
1297
1298         /* get the temperature */
1299         r = amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_GPU_TEMP,
1300                                    (void *)&temp, &size);
1301         if (r)
1302                 return r;
1303
1304         return snprintf(buf, PAGE_SIZE, "%d\n", temp);
1305 }
1306
1307 static ssize_t amdgpu_hwmon_show_temp_thresh(struct device *dev,
1308                                              struct device_attribute *attr,
1309                                              char *buf)
1310 {
1311         struct amdgpu_device *adev = dev_get_drvdata(dev);
1312         int hyst = to_sensor_dev_attr(attr)->index;
1313         int temp;
1314
1315         if (hyst)
1316                 temp = adev->pm.dpm.thermal.min_temp;
1317         else
1318                 temp = adev->pm.dpm.thermal.max_temp;
1319
1320         return snprintf(buf, PAGE_SIZE, "%d\n", temp);
1321 }
1322
1323 static ssize_t amdgpu_hwmon_get_pwm1_enable(struct device *dev,
1324                                             struct device_attribute *attr,
1325                                             char *buf)
1326 {
1327         struct amdgpu_device *adev = dev_get_drvdata(dev);
1328         u32 pwm_mode = 0;
1329
1330         if (!adev->powerplay.pp_funcs->get_fan_control_mode)
1331                 return -EINVAL;
1332
1333         pwm_mode = amdgpu_dpm_get_fan_control_mode(adev);
1334
1335         return sprintf(buf, "%i\n", pwm_mode);
1336 }
1337
1338 static ssize_t amdgpu_hwmon_set_pwm1_enable(struct device *dev,
1339                                             struct device_attribute *attr,
1340                                             const char *buf,
1341                                             size_t count)
1342 {
1343         struct amdgpu_device *adev = dev_get_drvdata(dev);
1344         int err;
1345         int value;
1346
1347         /* Can't adjust fan when the card is off */
1348         if  ((adev->flags & AMD_IS_PX) &&
1349              (adev->ddev->switch_power_state != DRM_SWITCH_POWER_ON))
1350                 return -EINVAL;
1351
1352         if (!adev->powerplay.pp_funcs->set_fan_control_mode)
1353                 return -EINVAL;
1354
1355         err = kstrtoint(buf, 10, &value);
1356         if (err)
1357                 return err;
1358
1359         amdgpu_dpm_set_fan_control_mode(adev, value);
1360
1361         return count;
1362 }
1363
1364 static ssize_t amdgpu_hwmon_get_pwm1_min(struct device *dev,
1365                                          struct device_attribute *attr,
1366                                          char *buf)
1367 {
1368         return sprintf(buf, "%i\n", 0);
1369 }
1370
1371 static ssize_t amdgpu_hwmon_get_pwm1_max(struct device *dev,
1372                                          struct device_attribute *attr,
1373                                          char *buf)
1374 {
1375         return sprintf(buf, "%i\n", 255);
1376 }
1377
1378 static ssize_t amdgpu_hwmon_set_pwm1(struct device *dev,
1379                                      struct device_attribute *attr,
1380                                      const char *buf, size_t count)
1381 {
1382         struct amdgpu_device *adev = dev_get_drvdata(dev);
1383         int err;
1384         u32 value;
1385         u32 pwm_mode;
1386
1387         /* Can't adjust fan when the card is off */
1388         if  ((adev->flags & AMD_IS_PX) &&
1389              (adev->ddev->switch_power_state != DRM_SWITCH_POWER_ON))
1390                 return -EINVAL;
1391
1392         pwm_mode = amdgpu_dpm_get_fan_control_mode(adev);
1393         if (pwm_mode != AMD_FAN_CTRL_MANUAL) {
1394                 pr_info("manual fan speed control should be enabled first\n");
1395                 return -EINVAL;
1396         }
1397
1398         err = kstrtou32(buf, 10, &value);
1399         if (err)
1400                 return err;
1401
1402         value = (value * 100) / 255;
1403
1404         if (adev->powerplay.pp_funcs->set_fan_speed_percent) {
1405                 err = amdgpu_dpm_set_fan_speed_percent(adev, value);
1406                 if (err)
1407                         return err;
1408         }
1409
1410         return count;
1411 }
1412
1413 static ssize_t amdgpu_hwmon_get_pwm1(struct device *dev,
1414                                      struct device_attribute *attr,
1415                                      char *buf)
1416 {
1417         struct amdgpu_device *adev = dev_get_drvdata(dev);
1418         int err;
1419         u32 speed = 0;
1420
1421         /* Can't adjust fan when the card is off */
1422         if  ((adev->flags & AMD_IS_PX) &&
1423              (adev->ddev->switch_power_state != DRM_SWITCH_POWER_ON))
1424                 return -EINVAL;
1425
1426         if (adev->powerplay.pp_funcs->get_fan_speed_percent) {
1427                 err = amdgpu_dpm_get_fan_speed_percent(adev, &speed);
1428                 if (err)
1429                         return err;
1430         }
1431
1432         speed = (speed * 255) / 100;
1433
1434         return sprintf(buf, "%i\n", speed);
1435 }
1436
1437 static ssize_t amdgpu_hwmon_get_fan1_input(struct device *dev,
1438                                            struct device_attribute *attr,
1439                                            char *buf)
1440 {
1441         struct amdgpu_device *adev = dev_get_drvdata(dev);
1442         int err;
1443         u32 speed = 0;
1444
1445         /* Can't adjust fan when the card is off */
1446         if  ((adev->flags & AMD_IS_PX) &&
1447              (adev->ddev->switch_power_state != DRM_SWITCH_POWER_ON))
1448                 return -EINVAL;
1449
1450         if (adev->powerplay.pp_funcs->get_fan_speed_rpm) {
1451                 err = amdgpu_dpm_get_fan_speed_rpm(adev, &speed);
1452                 if (err)
1453                         return err;
1454         }
1455
1456         return sprintf(buf, "%i\n", speed);
1457 }
1458
1459 static ssize_t amdgpu_hwmon_get_fan1_min(struct device *dev,
1460                                          struct device_attribute *attr,
1461                                          char *buf)
1462 {
1463         struct amdgpu_device *adev = dev_get_drvdata(dev);
1464         u32 min_rpm = 0;
1465         u32 size = sizeof(min_rpm);
1466         int r;
1467
1468         r = amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_MIN_FAN_RPM,
1469                                    (void *)&min_rpm, &size);
1470         if (r)
1471                 return r;
1472
1473         return snprintf(buf, PAGE_SIZE, "%d\n", min_rpm);
1474 }
1475
1476 static ssize_t amdgpu_hwmon_get_fan1_max(struct device *dev,
1477                                          struct device_attribute *attr,
1478                                          char *buf)
1479 {
1480         struct amdgpu_device *adev = dev_get_drvdata(dev);
1481         u32 max_rpm = 0;
1482         u32 size = sizeof(max_rpm);
1483         int r;
1484
1485         r = amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_MAX_FAN_RPM,
1486                                    (void *)&max_rpm, &size);
1487         if (r)
1488                 return r;
1489
1490         return snprintf(buf, PAGE_SIZE, "%d\n", max_rpm);
1491 }
1492
1493 static ssize_t amdgpu_hwmon_get_fan1_target(struct device *dev,
1494                                            struct device_attribute *attr,
1495                                            char *buf)
1496 {
1497         struct amdgpu_device *adev = dev_get_drvdata(dev);
1498         int err;
1499         u32 rpm = 0;
1500
1501         /* Can't adjust fan when the card is off */
1502         if  ((adev->flags & AMD_IS_PX) &&
1503              (adev->ddev->switch_power_state != DRM_SWITCH_POWER_ON))
1504                 return -EINVAL;
1505
1506         if (adev->powerplay.pp_funcs->get_fan_speed_rpm) {
1507                 err = amdgpu_dpm_get_fan_speed_rpm(adev, &rpm);
1508                 if (err)
1509                         return err;
1510         }
1511
1512         return sprintf(buf, "%i\n", rpm);
1513 }
1514
1515 static ssize_t amdgpu_hwmon_set_fan1_target(struct device *dev,
1516                                      struct device_attribute *attr,
1517                                      const char *buf, size_t count)
1518 {
1519         struct amdgpu_device *adev = dev_get_drvdata(dev);
1520         int err;
1521         u32 value;
1522         u32 pwm_mode;
1523
1524         pwm_mode = amdgpu_dpm_get_fan_control_mode(adev);
1525         if (pwm_mode != AMD_FAN_CTRL_MANUAL)
1526                 return -ENODATA;
1527
1528         /* Can't adjust fan when the card is off */
1529         if  ((adev->flags & AMD_IS_PX) &&
1530              (adev->ddev->switch_power_state != DRM_SWITCH_POWER_ON))
1531                 return -EINVAL;
1532
1533         err = kstrtou32(buf, 10, &value);
1534         if (err)
1535                 return err;
1536
1537         if (adev->powerplay.pp_funcs->set_fan_speed_rpm) {
1538                 err = amdgpu_dpm_set_fan_speed_rpm(adev, value);
1539                 if (err)
1540                         return err;
1541         }
1542
1543         return count;
1544 }
1545
1546 static ssize_t amdgpu_hwmon_get_fan1_enable(struct device *dev,
1547                                             struct device_attribute *attr,
1548                                             char *buf)
1549 {
1550         struct amdgpu_device *adev = dev_get_drvdata(dev);
1551         u32 pwm_mode = 0;
1552
1553         if (!adev->powerplay.pp_funcs->get_fan_control_mode)
1554                 return -EINVAL;
1555
1556         pwm_mode = amdgpu_dpm_get_fan_control_mode(adev);
1557
1558         return sprintf(buf, "%i\n", pwm_mode == AMD_FAN_CTRL_AUTO ? 0 : 1);
1559 }
1560
1561 static ssize_t amdgpu_hwmon_set_fan1_enable(struct device *dev,
1562                                             struct device_attribute *attr,
1563                                             const char *buf,
1564                                             size_t count)
1565 {
1566         struct amdgpu_device *adev = dev_get_drvdata(dev);
1567         int err;
1568         int value;
1569         u32 pwm_mode;
1570
1571         /* Can't adjust fan when the card is off */
1572         if  ((adev->flags & AMD_IS_PX) &&
1573              (adev->ddev->switch_power_state != DRM_SWITCH_POWER_ON))
1574                 return -EINVAL;
1575
1576         if (!adev->powerplay.pp_funcs->set_fan_control_mode)
1577                 return -EINVAL;
1578
1579         err = kstrtoint(buf, 10, &value);
1580         if (err)
1581                 return err;
1582
1583         if (value == 0)
1584                 pwm_mode = AMD_FAN_CTRL_AUTO;
1585         else if (value == 1)
1586                 pwm_mode = AMD_FAN_CTRL_MANUAL;
1587         else
1588                 return -EINVAL;
1589
1590         amdgpu_dpm_set_fan_control_mode(adev, pwm_mode);
1591
1592         return count;
1593 }
1594
1595 static ssize_t amdgpu_hwmon_show_vddgfx(struct device *dev,
1596                                         struct device_attribute *attr,
1597                                         char *buf)
1598 {
1599         struct amdgpu_device *adev = dev_get_drvdata(dev);
1600         struct drm_device *ddev = adev->ddev;
1601         u32 vddgfx;
1602         int r, size = sizeof(vddgfx);
1603
1604         /* Can't get voltage when the card is off */
1605         if  ((adev->flags & AMD_IS_PX) &&
1606              (ddev->switch_power_state != DRM_SWITCH_POWER_ON))
1607                 return -EINVAL;
1608
1609         /* get the voltage */
1610         r = amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_VDDGFX,
1611                                    (void *)&vddgfx, &size);
1612         if (r)
1613                 return r;
1614
1615         return snprintf(buf, PAGE_SIZE, "%d\n", vddgfx);
1616 }
1617
1618 static ssize_t amdgpu_hwmon_show_vddgfx_label(struct device *dev,
1619                                               struct device_attribute *attr,
1620                                               char *buf)
1621 {
1622         return snprintf(buf, PAGE_SIZE, "vddgfx\n");
1623 }
1624
1625 static ssize_t amdgpu_hwmon_show_vddnb(struct device *dev,
1626                                        struct device_attribute *attr,
1627                                        char *buf)
1628 {
1629         struct amdgpu_device *adev = dev_get_drvdata(dev);
1630         struct drm_device *ddev = adev->ddev;
1631         u32 vddnb;
1632         int r, size = sizeof(vddnb);
1633
1634         /* only APUs have vddnb */
1635         if  (!(adev->flags & AMD_IS_APU))
1636                 return -EINVAL;
1637
1638         /* Can't get voltage when the card is off */
1639         if  ((adev->flags & AMD_IS_PX) &&
1640              (ddev->switch_power_state != DRM_SWITCH_POWER_ON))
1641                 return -EINVAL;
1642
1643         /* get the voltage */
1644         r = amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_VDDNB,
1645                                    (void *)&vddnb, &size);
1646         if (r)
1647                 return r;
1648
1649         return snprintf(buf, PAGE_SIZE, "%d\n", vddnb);
1650 }
1651
1652 static ssize_t amdgpu_hwmon_show_vddnb_label(struct device *dev,
1653                                               struct device_attribute *attr,
1654                                               char *buf)
1655 {
1656         return snprintf(buf, PAGE_SIZE, "vddnb\n");
1657 }
1658
1659 static ssize_t amdgpu_hwmon_show_power_avg(struct device *dev,
1660                                            struct device_attribute *attr,
1661                                            char *buf)
1662 {
1663         struct amdgpu_device *adev = dev_get_drvdata(dev);
1664         struct drm_device *ddev = adev->ddev;
1665         u32 query = 0;
1666         int r, size = sizeof(u32);
1667         unsigned uw;
1668
1669         /* Can't get power when the card is off */
1670         if  ((adev->flags & AMD_IS_PX) &&
1671              (ddev->switch_power_state != DRM_SWITCH_POWER_ON))
1672                 return -EINVAL;
1673
1674         /* get the voltage */
1675         r = amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_GPU_POWER,
1676                                    (void *)&query, &size);
1677         if (r)
1678                 return r;
1679
1680         /* convert to microwatts */
1681         uw = (query >> 8) * 1000000 + (query & 0xff) * 1000;
1682
1683         return snprintf(buf, PAGE_SIZE, "%u\n", uw);
1684 }
1685
1686 static ssize_t amdgpu_hwmon_show_power_cap_min(struct device *dev,
1687                                          struct device_attribute *attr,
1688                                          char *buf)
1689 {
1690         return sprintf(buf, "%i\n", 0);
1691 }
1692
1693 static ssize_t amdgpu_hwmon_show_power_cap_max(struct device *dev,
1694                                          struct device_attribute *attr,
1695                                          char *buf)
1696 {
1697         struct amdgpu_device *adev = dev_get_drvdata(dev);
1698         uint32_t limit = 0;
1699
1700         if (adev->powerplay.pp_funcs && adev->powerplay.pp_funcs->get_power_limit) {
1701                 adev->powerplay.pp_funcs->get_power_limit(adev->powerplay.pp_handle, &limit, true);
1702                 return snprintf(buf, PAGE_SIZE, "%u\n", limit * 1000000);
1703         } else {
1704                 return snprintf(buf, PAGE_SIZE, "\n");
1705         }
1706 }
1707
1708 static ssize_t amdgpu_hwmon_show_power_cap(struct device *dev,
1709                                          struct device_attribute *attr,
1710                                          char *buf)
1711 {
1712         struct amdgpu_device *adev = dev_get_drvdata(dev);
1713         uint32_t limit = 0;
1714
1715         if (adev->powerplay.pp_funcs && adev->powerplay.pp_funcs->get_power_limit) {
1716                 adev->powerplay.pp_funcs->get_power_limit(adev->powerplay.pp_handle, &limit, false);
1717                 return snprintf(buf, PAGE_SIZE, "%u\n", limit * 1000000);
1718         } else {
1719                 return snprintf(buf, PAGE_SIZE, "\n");
1720         }
1721 }
1722
1723
1724 static ssize_t amdgpu_hwmon_set_power_cap(struct device *dev,
1725                 struct device_attribute *attr,
1726                 const char *buf,
1727                 size_t count)
1728 {
1729         struct amdgpu_device *adev = dev_get_drvdata(dev);
1730         int err;
1731         u32 value;
1732
1733         err = kstrtou32(buf, 10, &value);
1734         if (err)
1735                 return err;
1736
1737         value = value / 1000000; /* convert to Watt */
1738         if (adev->powerplay.pp_funcs && adev->powerplay.pp_funcs->set_power_limit) {
1739                 err = adev->powerplay.pp_funcs->set_power_limit(adev->powerplay.pp_handle, value);
1740                 if (err)
1741                         return err;
1742         } else {
1743                 return -EINVAL;
1744         }
1745
1746         return count;
1747 }
1748
1749 static ssize_t amdgpu_hwmon_show_sclk(struct device *dev,
1750                                       struct device_attribute *attr,
1751                                       char *buf)
1752 {
1753         struct amdgpu_device *adev = dev_get_drvdata(dev);
1754         struct drm_device *ddev = adev->ddev;
1755         uint32_t sclk;
1756         int r, size = sizeof(sclk);
1757
1758         /* Can't get voltage when the card is off */
1759         if  ((adev->flags & AMD_IS_PX) &&
1760              (ddev->switch_power_state != DRM_SWITCH_POWER_ON))
1761                 return -EINVAL;
1762
1763         /* sanity check PP is enabled */
1764         if (!(adev->powerplay.pp_funcs &&
1765               adev->powerplay.pp_funcs->read_sensor))
1766               return -EINVAL;
1767
1768         /* get the sclk */
1769         r = amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_GFX_SCLK,
1770                                    (void *)&sclk, &size);
1771         if (r)
1772                 return r;
1773
1774         return snprintf(buf, PAGE_SIZE, "%d\n", sclk * 10 * 1000);
1775 }
1776
1777 static ssize_t amdgpu_hwmon_show_sclk_label(struct device *dev,
1778                                             struct device_attribute *attr,
1779                                             char *buf)
1780 {
1781         return snprintf(buf, PAGE_SIZE, "sclk\n");
1782 }
1783
1784 static ssize_t amdgpu_hwmon_show_mclk(struct device *dev,
1785                                       struct device_attribute *attr,
1786                                       char *buf)
1787 {
1788         struct amdgpu_device *adev = dev_get_drvdata(dev);
1789         struct drm_device *ddev = adev->ddev;
1790         uint32_t mclk;
1791         int r, size = sizeof(mclk);
1792
1793         /* Can't get voltage when the card is off */
1794         if  ((adev->flags & AMD_IS_PX) &&
1795              (ddev->switch_power_state != DRM_SWITCH_POWER_ON))
1796                 return -EINVAL;
1797
1798         /* sanity check PP is enabled */
1799         if (!(adev->powerplay.pp_funcs &&
1800               adev->powerplay.pp_funcs->read_sensor))
1801               return -EINVAL;
1802
1803         /* get the sclk */
1804         r = amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_GFX_MCLK,
1805                                    (void *)&mclk, &size);
1806         if (r)
1807                 return r;
1808
1809         return snprintf(buf, PAGE_SIZE, "%d\n", mclk * 10 * 1000);
1810 }
1811
1812 static ssize_t amdgpu_hwmon_show_mclk_label(struct device *dev,
1813                                             struct device_attribute *attr,
1814                                             char *buf)
1815 {
1816         return snprintf(buf, PAGE_SIZE, "mclk\n");
1817 }
1818
1819 /**
1820  * DOC: hwmon
1821  *
1822  * The amdgpu driver exposes the following sensor interfaces:
1823  *
1824  * - GPU temperature (via the on-die sensor)
1825  *
1826  * - GPU voltage
1827  *
1828  * - Northbridge voltage (APUs only)
1829  *
1830  * - GPU power
1831  *
1832  * - GPU fan
1833  *
1834  * - GPU gfx/compute engine clock
1835  *
1836  * - GPU memory clock (dGPU only)
1837  *
1838  * hwmon interfaces for GPU temperature:
1839  *
1840  * - temp1_input: the on die GPU temperature in millidegrees Celsius
1841  *
1842  * - temp1_crit: temperature critical max value in millidegrees Celsius
1843  *
1844  * - temp1_crit_hyst: temperature hysteresis for critical limit in millidegrees Celsius
1845  *
1846  * hwmon interfaces for GPU voltage:
1847  *
1848  * - in0_input: the voltage on the GPU in millivolts
1849  *
1850  * - in1_input: the voltage on the Northbridge in millivolts
1851  *
1852  * hwmon interfaces for GPU power:
1853  *
1854  * - power1_average: average power used by the GPU in microWatts
1855  *
1856  * - power1_cap_min: minimum cap supported in microWatts
1857  *
1858  * - power1_cap_max: maximum cap supported in microWatts
1859  *
1860  * - power1_cap: selected power cap in microWatts
1861  *
1862  * hwmon interfaces for GPU fan:
1863  *
1864  * - pwm1: pulse width modulation fan level (0-255)
1865  *
1866  * - pwm1_enable: pulse width modulation fan control method (0: no fan speed control, 1: manual fan speed control using pwm interface, 2: automatic fan speed control)
1867  *
1868  * - pwm1_min: pulse width modulation fan control minimum level (0)
1869  *
1870  * - pwm1_max: pulse width modulation fan control maximum level (255)
1871  *
1872  * - fan1_min: an minimum value Unit: revolution/min (RPM)
1873  *
1874  * - fan1_max: an maxmum value Unit: revolution/max (RPM)
1875  *
1876  * - fan1_input: fan speed in RPM
1877  *
1878  * - fan[1-*]_target: Desired fan speed Unit: revolution/min (RPM)
1879  *
1880  * - fan[1-*]_enable: Enable or disable the sensors.1: Enable 0: Disable
1881  *
1882  * hwmon interfaces for GPU clocks:
1883  *
1884  * - freq1_input: the gfx/compute clock in hertz
1885  *
1886  * - freq2_input: the memory clock in hertz
1887  *
1888  * You can use hwmon tools like sensors to view this information on your system.
1889  *
1890  */
1891
1892 static SENSOR_DEVICE_ATTR(temp1_input, S_IRUGO, amdgpu_hwmon_show_temp, NULL, 0);
1893 static SENSOR_DEVICE_ATTR(temp1_crit, S_IRUGO, amdgpu_hwmon_show_temp_thresh, NULL, 0);
1894 static SENSOR_DEVICE_ATTR(temp1_crit_hyst, S_IRUGO, amdgpu_hwmon_show_temp_thresh, NULL, 1);
1895 static SENSOR_DEVICE_ATTR(pwm1, S_IRUGO | S_IWUSR, amdgpu_hwmon_get_pwm1, amdgpu_hwmon_set_pwm1, 0);
1896 static SENSOR_DEVICE_ATTR(pwm1_enable, S_IRUGO | S_IWUSR, amdgpu_hwmon_get_pwm1_enable, amdgpu_hwmon_set_pwm1_enable, 0);
1897 static SENSOR_DEVICE_ATTR(pwm1_min, S_IRUGO, amdgpu_hwmon_get_pwm1_min, NULL, 0);
1898 static SENSOR_DEVICE_ATTR(pwm1_max, S_IRUGO, amdgpu_hwmon_get_pwm1_max, NULL, 0);
1899 static SENSOR_DEVICE_ATTR(fan1_input, S_IRUGO, amdgpu_hwmon_get_fan1_input, NULL, 0);
1900 static SENSOR_DEVICE_ATTR(fan1_min, S_IRUGO, amdgpu_hwmon_get_fan1_min, NULL, 0);
1901 static SENSOR_DEVICE_ATTR(fan1_max, S_IRUGO, amdgpu_hwmon_get_fan1_max, NULL, 0);
1902 static SENSOR_DEVICE_ATTR(fan1_target, S_IRUGO | S_IWUSR, amdgpu_hwmon_get_fan1_target, amdgpu_hwmon_set_fan1_target, 0);
1903 static SENSOR_DEVICE_ATTR(fan1_enable, S_IRUGO | S_IWUSR, amdgpu_hwmon_get_fan1_enable, amdgpu_hwmon_set_fan1_enable, 0);
1904 static SENSOR_DEVICE_ATTR(in0_input, S_IRUGO, amdgpu_hwmon_show_vddgfx, NULL, 0);
1905 static SENSOR_DEVICE_ATTR(in0_label, S_IRUGO, amdgpu_hwmon_show_vddgfx_label, NULL, 0);
1906 static SENSOR_DEVICE_ATTR(in1_input, S_IRUGO, amdgpu_hwmon_show_vddnb, NULL, 0);
1907 static SENSOR_DEVICE_ATTR(in1_label, S_IRUGO, amdgpu_hwmon_show_vddnb_label, NULL, 0);
1908 static SENSOR_DEVICE_ATTR(power1_average, S_IRUGO, amdgpu_hwmon_show_power_avg, NULL, 0);
1909 static SENSOR_DEVICE_ATTR(power1_cap_max, S_IRUGO, amdgpu_hwmon_show_power_cap_max, NULL, 0);
1910 static SENSOR_DEVICE_ATTR(power1_cap_min, S_IRUGO, amdgpu_hwmon_show_power_cap_min, NULL, 0);
1911 static SENSOR_DEVICE_ATTR(power1_cap, S_IRUGO | S_IWUSR, amdgpu_hwmon_show_power_cap, amdgpu_hwmon_set_power_cap, 0);
1912 static SENSOR_DEVICE_ATTR(freq1_input, S_IRUGO, amdgpu_hwmon_show_sclk, NULL, 0);
1913 static SENSOR_DEVICE_ATTR(freq1_label, S_IRUGO, amdgpu_hwmon_show_sclk_label, NULL, 0);
1914 static SENSOR_DEVICE_ATTR(freq2_input, S_IRUGO, amdgpu_hwmon_show_mclk, NULL, 0);
1915 static SENSOR_DEVICE_ATTR(freq2_label, S_IRUGO, amdgpu_hwmon_show_mclk_label, NULL, 0);
1916
1917 static struct attribute *hwmon_attributes[] = {
1918         &sensor_dev_attr_temp1_input.dev_attr.attr,
1919         &sensor_dev_attr_temp1_crit.dev_attr.attr,
1920         &sensor_dev_attr_temp1_crit_hyst.dev_attr.attr,
1921         &sensor_dev_attr_pwm1.dev_attr.attr,
1922         &sensor_dev_attr_pwm1_enable.dev_attr.attr,
1923         &sensor_dev_attr_pwm1_min.dev_attr.attr,
1924         &sensor_dev_attr_pwm1_max.dev_attr.attr,
1925         &sensor_dev_attr_fan1_input.dev_attr.attr,
1926         &sensor_dev_attr_fan1_min.dev_attr.attr,
1927         &sensor_dev_attr_fan1_max.dev_attr.attr,
1928         &sensor_dev_attr_fan1_target.dev_attr.attr,
1929         &sensor_dev_attr_fan1_enable.dev_attr.attr,
1930         &sensor_dev_attr_in0_input.dev_attr.attr,
1931         &sensor_dev_attr_in0_label.dev_attr.attr,
1932         &sensor_dev_attr_in1_input.dev_attr.attr,
1933         &sensor_dev_attr_in1_label.dev_attr.attr,
1934         &sensor_dev_attr_power1_average.dev_attr.attr,
1935         &sensor_dev_attr_power1_cap_max.dev_attr.attr,
1936         &sensor_dev_attr_power1_cap_min.dev_attr.attr,
1937         &sensor_dev_attr_power1_cap.dev_attr.attr,
1938         &sensor_dev_attr_freq1_input.dev_attr.attr,
1939         &sensor_dev_attr_freq1_label.dev_attr.attr,
1940         &sensor_dev_attr_freq2_input.dev_attr.attr,
1941         &sensor_dev_attr_freq2_label.dev_attr.attr,
1942         NULL
1943 };
1944
1945 static umode_t hwmon_attributes_visible(struct kobject *kobj,
1946                                         struct attribute *attr, int index)
1947 {
1948         struct device *dev = kobj_to_dev(kobj);
1949         struct amdgpu_device *adev = dev_get_drvdata(dev);
1950         umode_t effective_mode = attr->mode;
1951
1952         /* Skip fan attributes if fan is not present */
1953         if (adev->pm.no_fan && (attr == &sensor_dev_attr_pwm1.dev_attr.attr ||
1954             attr == &sensor_dev_attr_pwm1_enable.dev_attr.attr ||
1955             attr == &sensor_dev_attr_pwm1_max.dev_attr.attr ||
1956             attr == &sensor_dev_attr_pwm1_min.dev_attr.attr ||
1957             attr == &sensor_dev_attr_fan1_input.dev_attr.attr ||
1958             attr == &sensor_dev_attr_fan1_min.dev_attr.attr ||
1959             attr == &sensor_dev_attr_fan1_max.dev_attr.attr ||
1960             attr == &sensor_dev_attr_fan1_target.dev_attr.attr ||
1961             attr == &sensor_dev_attr_fan1_enable.dev_attr.attr))
1962                 return 0;
1963
1964         /* Skip fan attributes on APU */
1965         if ((adev->flags & AMD_IS_APU) &&
1966             (attr == &sensor_dev_attr_pwm1.dev_attr.attr ||
1967              attr == &sensor_dev_attr_pwm1_enable.dev_attr.attr ||
1968              attr == &sensor_dev_attr_pwm1_max.dev_attr.attr ||
1969              attr == &sensor_dev_attr_pwm1_min.dev_attr.attr ||
1970              attr == &sensor_dev_attr_fan1_input.dev_attr.attr ||
1971              attr == &sensor_dev_attr_fan1_min.dev_attr.attr ||
1972              attr == &sensor_dev_attr_fan1_max.dev_attr.attr ||
1973              attr == &sensor_dev_attr_fan1_target.dev_attr.attr ||
1974              attr == &sensor_dev_attr_fan1_enable.dev_attr.attr))
1975                 return 0;
1976
1977         /* Skip limit attributes if DPM is not enabled */
1978         if (!adev->pm.dpm_enabled &&
1979             (attr == &sensor_dev_attr_temp1_crit.dev_attr.attr ||
1980              attr == &sensor_dev_attr_temp1_crit_hyst.dev_attr.attr ||
1981              attr == &sensor_dev_attr_pwm1.dev_attr.attr ||
1982              attr == &sensor_dev_attr_pwm1_enable.dev_attr.attr ||
1983              attr == &sensor_dev_attr_pwm1_max.dev_attr.attr ||
1984              attr == &sensor_dev_attr_pwm1_min.dev_attr.attr ||
1985              attr == &sensor_dev_attr_fan1_input.dev_attr.attr ||
1986              attr == &sensor_dev_attr_fan1_min.dev_attr.attr ||
1987              attr == &sensor_dev_attr_fan1_max.dev_attr.attr ||
1988              attr == &sensor_dev_attr_fan1_target.dev_attr.attr ||
1989              attr == &sensor_dev_attr_fan1_enable.dev_attr.attr))
1990                 return 0;
1991
1992         /* mask fan attributes if we have no bindings for this asic to expose */
1993         if ((!adev->powerplay.pp_funcs->get_fan_speed_percent &&
1994              attr == &sensor_dev_attr_pwm1.dev_attr.attr) || /* can't query fan */
1995             (!adev->powerplay.pp_funcs->get_fan_control_mode &&
1996              attr == &sensor_dev_attr_pwm1_enable.dev_attr.attr)) /* can't query state */
1997                 effective_mode &= ~S_IRUGO;
1998
1999         if ((!adev->powerplay.pp_funcs->set_fan_speed_percent &&
2000              attr == &sensor_dev_attr_pwm1.dev_attr.attr) || /* can't manage fan */
2001             (!adev->powerplay.pp_funcs->set_fan_control_mode &&
2002              attr == &sensor_dev_attr_pwm1_enable.dev_attr.attr)) /* can't manage state */
2003                 effective_mode &= ~S_IWUSR;
2004
2005         if ((adev->flags & AMD_IS_APU) &&
2006             (attr == &sensor_dev_attr_power1_average.dev_attr.attr ||
2007              attr == &sensor_dev_attr_power1_cap_max.dev_attr.attr ||
2008              attr == &sensor_dev_attr_power1_cap_min.dev_attr.attr||
2009              attr == &sensor_dev_attr_power1_cap.dev_attr.attr))
2010                 return 0;
2011
2012         /* hide max/min values if we can't both query and manage the fan */
2013         if ((!adev->powerplay.pp_funcs->set_fan_speed_percent &&
2014              !adev->powerplay.pp_funcs->get_fan_speed_percent) &&
2015              (!adev->powerplay.pp_funcs->set_fan_speed_rpm &&
2016              !adev->powerplay.pp_funcs->get_fan_speed_rpm) &&
2017             (attr == &sensor_dev_attr_pwm1_max.dev_attr.attr ||
2018              attr == &sensor_dev_attr_pwm1_min.dev_attr.attr))
2019                 return 0;
2020
2021         if ((!adev->powerplay.pp_funcs->set_fan_speed_rpm &&
2022              !adev->powerplay.pp_funcs->get_fan_speed_rpm) &&
2023             (attr == &sensor_dev_attr_fan1_max.dev_attr.attr ||
2024              attr == &sensor_dev_attr_fan1_min.dev_attr.attr))
2025                 return 0;
2026
2027         /* only APUs have vddnb */
2028         if (!(adev->flags & AMD_IS_APU) &&
2029             (attr == &sensor_dev_attr_in1_input.dev_attr.attr ||
2030              attr == &sensor_dev_attr_in1_label.dev_attr.attr))
2031                 return 0;
2032
2033         /* no mclk on APUs */
2034         if ((adev->flags & AMD_IS_APU) &&
2035             (attr == &sensor_dev_attr_freq2_input.dev_attr.attr ||
2036              attr == &sensor_dev_attr_freq2_label.dev_attr.attr))
2037                 return 0;
2038
2039         return effective_mode;
2040 }
2041
2042 static const struct attribute_group hwmon_attrgroup = {
2043         .attrs = hwmon_attributes,
2044         .is_visible = hwmon_attributes_visible,
2045 };
2046
2047 static const struct attribute_group *hwmon_groups[] = {
2048         &hwmon_attrgroup,
2049         NULL
2050 };
2051
2052 void amdgpu_dpm_thermal_work_handler(struct work_struct *work)
2053 {
2054         struct amdgpu_device *adev =
2055                 container_of(work, struct amdgpu_device,
2056                              pm.dpm.thermal.work);
2057         /* switch to the thermal state */
2058         enum amd_pm_state_type dpm_state = POWER_STATE_TYPE_INTERNAL_THERMAL;
2059         int temp, size = sizeof(temp);
2060
2061         if (!adev->pm.dpm_enabled)
2062                 return;
2063
2064         if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_GPU_TEMP,
2065                                     (void *)&temp, &size)) {
2066                 if (temp < adev->pm.dpm.thermal.min_temp)
2067                         /* switch back the user state */
2068                         dpm_state = adev->pm.dpm.user_state;
2069         } else {
2070                 if (adev->pm.dpm.thermal.high_to_low)
2071                         /* switch back the user state */
2072                         dpm_state = adev->pm.dpm.user_state;
2073         }
2074         mutex_lock(&adev->pm.mutex);
2075         if (dpm_state == POWER_STATE_TYPE_INTERNAL_THERMAL)
2076                 adev->pm.dpm.thermal_active = true;
2077         else
2078                 adev->pm.dpm.thermal_active = false;
2079         adev->pm.dpm.state = dpm_state;
2080         mutex_unlock(&adev->pm.mutex);
2081
2082         amdgpu_pm_compute_clocks(adev);
2083 }
2084
2085 static struct amdgpu_ps *amdgpu_dpm_pick_power_state(struct amdgpu_device *adev,
2086                                                      enum amd_pm_state_type dpm_state)
2087 {
2088         int i;
2089         struct amdgpu_ps *ps;
2090         u32 ui_class;
2091         bool single_display = (adev->pm.dpm.new_active_crtc_count < 2) ?
2092                 true : false;
2093
2094         /* check if the vblank period is too short to adjust the mclk */
2095         if (single_display && adev->powerplay.pp_funcs->vblank_too_short) {
2096                 if (amdgpu_dpm_vblank_too_short(adev))
2097                         single_display = false;
2098         }
2099
2100         /* certain older asics have a separare 3D performance state,
2101          * so try that first if the user selected performance
2102          */
2103         if (dpm_state == POWER_STATE_TYPE_PERFORMANCE)
2104                 dpm_state = POWER_STATE_TYPE_INTERNAL_3DPERF;
2105         /* balanced states don't exist at the moment */
2106         if (dpm_state == POWER_STATE_TYPE_BALANCED)
2107                 dpm_state = POWER_STATE_TYPE_PERFORMANCE;
2108
2109 restart_search:
2110         /* Pick the best power state based on current conditions */
2111         for (i = 0; i < adev->pm.dpm.num_ps; i++) {
2112                 ps = &adev->pm.dpm.ps[i];
2113                 ui_class = ps->class & ATOM_PPLIB_CLASSIFICATION_UI_MASK;
2114                 switch (dpm_state) {
2115                 /* user states */
2116                 case POWER_STATE_TYPE_BATTERY:
2117                         if (ui_class == ATOM_PPLIB_CLASSIFICATION_UI_BATTERY) {
2118                                 if (ps->caps & ATOM_PPLIB_SINGLE_DISPLAY_ONLY) {
2119                                         if (single_display)
2120                                                 return ps;
2121                                 } else
2122                                         return ps;
2123                         }
2124                         break;
2125                 case POWER_STATE_TYPE_BALANCED:
2126                         if (ui_class == ATOM_PPLIB_CLASSIFICATION_UI_BALANCED) {
2127                                 if (ps->caps & ATOM_PPLIB_SINGLE_DISPLAY_ONLY) {
2128                                         if (single_display)
2129                                                 return ps;
2130                                 } else
2131                                         return ps;
2132                         }
2133                         break;
2134                 case POWER_STATE_TYPE_PERFORMANCE:
2135                         if (ui_class == ATOM_PPLIB_CLASSIFICATION_UI_PERFORMANCE) {
2136                                 if (ps->caps & ATOM_PPLIB_SINGLE_DISPLAY_ONLY) {
2137                                         if (single_display)
2138                                                 return ps;
2139                                 } else
2140                                         return ps;
2141                         }
2142                         break;
2143                 /* internal states */
2144                 case POWER_STATE_TYPE_INTERNAL_UVD:
2145                         if (adev->pm.dpm.uvd_ps)
2146                                 return adev->pm.dpm.uvd_ps;
2147                         else
2148                                 break;
2149                 case POWER_STATE_TYPE_INTERNAL_UVD_SD:
2150                         if (ps->class & ATOM_PPLIB_CLASSIFICATION_SDSTATE)
2151                                 return ps;
2152                         break;
2153                 case POWER_STATE_TYPE_INTERNAL_UVD_HD:
2154                         if (ps->class & ATOM_PPLIB_CLASSIFICATION_HDSTATE)
2155                                 return ps;
2156                         break;
2157                 case POWER_STATE_TYPE_INTERNAL_UVD_HD2:
2158                         if (ps->class & ATOM_PPLIB_CLASSIFICATION_HD2STATE)
2159                                 return ps;
2160                         break;
2161                 case POWER_STATE_TYPE_INTERNAL_UVD_MVC:
2162                         if (ps->class2 & ATOM_PPLIB_CLASSIFICATION2_MVC)
2163                                 return ps;
2164                         break;
2165                 case POWER_STATE_TYPE_INTERNAL_BOOT:
2166                         return adev->pm.dpm.boot_ps;
2167                 case POWER_STATE_TYPE_INTERNAL_THERMAL:
2168                         if (ps->class & ATOM_PPLIB_CLASSIFICATION_THERMAL)
2169                                 return ps;
2170                         break;
2171                 case POWER_STATE_TYPE_INTERNAL_ACPI:
2172                         if (ps->class & ATOM_PPLIB_CLASSIFICATION_ACPI)
2173                                 return ps;
2174                         break;
2175                 case POWER_STATE_TYPE_INTERNAL_ULV:
2176                         if (ps->class2 & ATOM_PPLIB_CLASSIFICATION2_ULV)
2177                                 return ps;
2178                         break;
2179                 case POWER_STATE_TYPE_INTERNAL_3DPERF:
2180                         if (ps->class & ATOM_PPLIB_CLASSIFICATION_3DPERFORMANCE)
2181                                 return ps;
2182                         break;
2183                 default:
2184                         break;
2185                 }
2186         }
2187         /* use a fallback state if we didn't match */
2188         switch (dpm_state) {
2189         case POWER_STATE_TYPE_INTERNAL_UVD_SD:
2190                 dpm_state = POWER_STATE_TYPE_INTERNAL_UVD_HD;
2191                 goto restart_search;
2192         case POWER_STATE_TYPE_INTERNAL_UVD_HD:
2193         case POWER_STATE_TYPE_INTERNAL_UVD_HD2:
2194         case POWER_STATE_TYPE_INTERNAL_UVD_MVC:
2195                 if (adev->pm.dpm.uvd_ps) {
2196                         return adev->pm.dpm.uvd_ps;
2197                 } else {
2198                         dpm_state = POWER_STATE_TYPE_PERFORMANCE;
2199                         goto restart_search;
2200                 }
2201         case POWER_STATE_TYPE_INTERNAL_THERMAL:
2202                 dpm_state = POWER_STATE_TYPE_INTERNAL_ACPI;
2203                 goto restart_search;
2204         case POWER_STATE_TYPE_INTERNAL_ACPI:
2205                 dpm_state = POWER_STATE_TYPE_BATTERY;
2206                 goto restart_search;
2207         case POWER_STATE_TYPE_BATTERY:
2208         case POWER_STATE_TYPE_BALANCED:
2209         case POWER_STATE_TYPE_INTERNAL_3DPERF:
2210                 dpm_state = POWER_STATE_TYPE_PERFORMANCE;
2211                 goto restart_search;
2212         default:
2213                 break;
2214         }
2215
2216         return NULL;
2217 }
2218
2219 static void amdgpu_dpm_change_power_state_locked(struct amdgpu_device *adev)
2220 {
2221         struct amdgpu_ps *ps;
2222         enum amd_pm_state_type dpm_state;
2223         int ret;
2224         bool equal = false;
2225
2226         /* if dpm init failed */
2227         if (!adev->pm.dpm_enabled)
2228                 return;
2229
2230         if (adev->pm.dpm.user_state != adev->pm.dpm.state) {
2231                 /* add other state override checks here */
2232                 if ((!adev->pm.dpm.thermal_active) &&
2233                     (!adev->pm.dpm.uvd_active))
2234                         adev->pm.dpm.state = adev->pm.dpm.user_state;
2235         }
2236         dpm_state = adev->pm.dpm.state;
2237
2238         ps = amdgpu_dpm_pick_power_state(adev, dpm_state);
2239         if (ps)
2240                 adev->pm.dpm.requested_ps = ps;
2241         else
2242                 return;
2243
2244         if (amdgpu_dpm == 1 && adev->powerplay.pp_funcs->print_power_state) {
2245                 printk("switching from power state:\n");
2246                 amdgpu_dpm_print_power_state(adev, adev->pm.dpm.current_ps);
2247                 printk("switching to power state:\n");
2248                 amdgpu_dpm_print_power_state(adev, adev->pm.dpm.requested_ps);
2249         }
2250
2251         /* update whether vce is active */
2252         ps->vce_active = adev->pm.dpm.vce_active;
2253         if (adev->powerplay.pp_funcs->display_configuration_changed)
2254                 amdgpu_dpm_display_configuration_changed(adev);
2255
2256         ret = amdgpu_dpm_pre_set_power_state(adev);
2257         if (ret)
2258                 return;
2259
2260         if (adev->powerplay.pp_funcs->check_state_equal) {
2261                 if (0 != amdgpu_dpm_check_state_equal(adev, adev->pm.dpm.current_ps, adev->pm.dpm.requested_ps, &equal))
2262                         equal = false;
2263         }
2264
2265         if (equal)
2266                 return;
2267
2268         amdgpu_dpm_set_power_state(adev);
2269         amdgpu_dpm_post_set_power_state(adev);
2270
2271         adev->pm.dpm.current_active_crtcs = adev->pm.dpm.new_active_crtcs;
2272         adev->pm.dpm.current_active_crtc_count = adev->pm.dpm.new_active_crtc_count;
2273
2274         if (adev->powerplay.pp_funcs->force_performance_level) {
2275                 if (adev->pm.dpm.thermal_active) {
2276                         enum amd_dpm_forced_level level = adev->pm.dpm.forced_level;
2277                         /* force low perf level for thermal */
2278                         amdgpu_dpm_force_performance_level(adev, AMD_DPM_FORCED_LEVEL_LOW);
2279                         /* save the user's level */
2280                         adev->pm.dpm.forced_level = level;
2281                 } else {
2282                         /* otherwise, user selected level */
2283                         amdgpu_dpm_force_performance_level(adev, adev->pm.dpm.forced_level);
2284                 }
2285         }
2286 }
2287
2288 void amdgpu_dpm_enable_uvd(struct amdgpu_device *adev, bool enable)
2289 {
2290         if (adev->powerplay.pp_funcs->set_powergating_by_smu) {
2291                 /* enable/disable UVD */
2292                 mutex_lock(&adev->pm.mutex);
2293                 amdgpu_dpm_set_powergating_by_smu(adev, AMD_IP_BLOCK_TYPE_UVD, !enable);
2294                 mutex_unlock(&adev->pm.mutex);
2295         }
2296         /* enable/disable Low Memory PState for UVD (4k videos) */
2297         if (adev->asic_type == CHIP_STONEY &&
2298                 adev->uvd.decode_image_width >= WIDTH_4K) {
2299                 struct pp_hwmgr *hwmgr = adev->powerplay.pp_handle;
2300
2301                 if (hwmgr && hwmgr->hwmgr_func &&
2302                     hwmgr->hwmgr_func->update_nbdpm_pstate)
2303                         hwmgr->hwmgr_func->update_nbdpm_pstate(hwmgr,
2304                                                                !enable,
2305                                                                true);
2306         }
2307 }
2308
2309 void amdgpu_dpm_enable_vce(struct amdgpu_device *adev, bool enable)
2310 {
2311         if (adev->powerplay.pp_funcs->set_powergating_by_smu) {
2312                 /* enable/disable VCE */
2313                 mutex_lock(&adev->pm.mutex);
2314                 amdgpu_dpm_set_powergating_by_smu(adev, AMD_IP_BLOCK_TYPE_VCE, !enable);
2315                 mutex_unlock(&adev->pm.mutex);
2316         }
2317 }
2318
2319 void amdgpu_pm_print_power_states(struct amdgpu_device *adev)
2320 {
2321         int i;
2322
2323         if (adev->powerplay.pp_funcs->print_power_state == NULL)
2324                 return;
2325
2326         for (i = 0; i < adev->pm.dpm.num_ps; i++)
2327                 amdgpu_dpm_print_power_state(adev, &adev->pm.dpm.ps[i]);
2328
2329 }
2330
2331 int amdgpu_pm_sysfs_init(struct amdgpu_device *adev)
2332 {
2333         struct pp_hwmgr *hwmgr = adev->powerplay.pp_handle;
2334         int ret;
2335
2336         if (adev->pm.sysfs_initialized)
2337                 return 0;
2338
2339         if (adev->pm.dpm_enabled == 0)
2340                 return 0;
2341
2342         adev->pm.int_hwmon_dev = hwmon_device_register_with_groups(adev->dev,
2343                                                                    DRIVER_NAME, adev,
2344                                                                    hwmon_groups);
2345         if (IS_ERR(adev->pm.int_hwmon_dev)) {
2346                 ret = PTR_ERR(adev->pm.int_hwmon_dev);
2347                 dev_err(adev->dev,
2348                         "Unable to register hwmon device: %d\n", ret);
2349                 return ret;
2350         }
2351
2352         ret = device_create_file(adev->dev, &dev_attr_power_dpm_state);
2353         if (ret) {
2354                 DRM_ERROR("failed to create device file for dpm state\n");
2355                 return ret;
2356         }
2357         ret = device_create_file(adev->dev, &dev_attr_power_dpm_force_performance_level);
2358         if (ret) {
2359                 DRM_ERROR("failed to create device file for dpm state\n");
2360                 return ret;
2361         }
2362
2363
2364         ret = device_create_file(adev->dev, &dev_attr_pp_num_states);
2365         if (ret) {
2366                 DRM_ERROR("failed to create device file pp_num_states\n");
2367                 return ret;
2368         }
2369         ret = device_create_file(adev->dev, &dev_attr_pp_cur_state);
2370         if (ret) {
2371                 DRM_ERROR("failed to create device file pp_cur_state\n");
2372                 return ret;
2373         }
2374         ret = device_create_file(adev->dev, &dev_attr_pp_force_state);
2375         if (ret) {
2376                 DRM_ERROR("failed to create device file pp_force_state\n");
2377                 return ret;
2378         }
2379         ret = device_create_file(adev->dev, &dev_attr_pp_table);
2380         if (ret) {
2381                 DRM_ERROR("failed to create device file pp_table\n");
2382                 return ret;
2383         }
2384
2385         ret = device_create_file(adev->dev, &dev_attr_pp_dpm_sclk);
2386         if (ret) {
2387                 DRM_ERROR("failed to create device file pp_dpm_sclk\n");
2388                 return ret;
2389         }
2390         ret = device_create_file(adev->dev, &dev_attr_pp_dpm_mclk);
2391         if (ret) {
2392                 DRM_ERROR("failed to create device file pp_dpm_mclk\n");
2393                 return ret;
2394         }
2395         if (adev->asic_type >= CHIP_VEGA10) {
2396                 ret = device_create_file(adev->dev, &dev_attr_pp_dpm_socclk);
2397                 if (ret) {
2398                         DRM_ERROR("failed to create device file pp_dpm_socclk\n");
2399                         return ret;
2400                 }
2401                 ret = device_create_file(adev->dev, &dev_attr_pp_dpm_dcefclk);
2402                 if (ret) {
2403                         DRM_ERROR("failed to create device file pp_dpm_dcefclk\n");
2404                         return ret;
2405                 }
2406         }
2407         if (adev->asic_type >= CHIP_VEGA20) {
2408                 ret = device_create_file(adev->dev, &dev_attr_pp_dpm_fclk);
2409                 if (ret) {
2410                         DRM_ERROR("failed to create device file pp_dpm_fclk\n");
2411                         return ret;
2412                 }
2413         }
2414         ret = device_create_file(adev->dev, &dev_attr_pp_dpm_pcie);
2415         if (ret) {
2416                 DRM_ERROR("failed to create device file pp_dpm_pcie\n");
2417                 return ret;
2418         }
2419         ret = device_create_file(adev->dev, &dev_attr_pp_sclk_od);
2420         if (ret) {
2421                 DRM_ERROR("failed to create device file pp_sclk_od\n");
2422                 return ret;
2423         }
2424         ret = device_create_file(adev->dev, &dev_attr_pp_mclk_od);
2425         if (ret) {
2426                 DRM_ERROR("failed to create device file pp_mclk_od\n");
2427                 return ret;
2428         }
2429         ret = device_create_file(adev->dev,
2430                         &dev_attr_pp_power_profile_mode);
2431         if (ret) {
2432                 DRM_ERROR("failed to create device file "
2433                                 "pp_power_profile_mode\n");
2434                 return ret;
2435         }
2436         if (hwmgr->od_enabled) {
2437                 ret = device_create_file(adev->dev,
2438                                 &dev_attr_pp_od_clk_voltage);
2439                 if (ret) {
2440                         DRM_ERROR("failed to create device file "
2441                                         "pp_od_clk_voltage\n");
2442                         return ret;
2443                 }
2444         }
2445         ret = device_create_file(adev->dev,
2446                         &dev_attr_gpu_busy_percent);
2447         if (ret) {
2448                 DRM_ERROR("failed to create device file "
2449                                 "gpu_busy_level\n");
2450                 return ret;
2451         }
2452         /* PCIe Perf counters won't work on APU nodes */
2453         if (!(adev->flags & AMD_IS_APU)) {
2454                 ret = device_create_file(adev->dev, &dev_attr_pcie_bw);
2455                 if (ret) {
2456                         DRM_ERROR("failed to create device file pcie_bw\n");
2457                         return ret;
2458                 }
2459         }
2460         ret = amdgpu_debugfs_pm_init(adev);
2461         if (ret) {
2462                 DRM_ERROR("Failed to register debugfs file for dpm!\n");
2463                 return ret;
2464         }
2465
2466         if ((adev->asic_type >= CHIP_VEGA10) &&
2467             !(adev->flags & AMD_IS_APU)) {
2468                 ret = device_create_file(adev->dev,
2469                                 &dev_attr_ppfeatures);
2470                 if (ret) {
2471                         DRM_ERROR("failed to create device file "
2472                                         "ppfeatures\n");
2473                         return ret;
2474                 }
2475         }
2476
2477         adev->pm.sysfs_initialized = true;
2478
2479         return 0;
2480 }
2481
2482 void amdgpu_pm_sysfs_fini(struct amdgpu_device *adev)
2483 {
2484         struct pp_hwmgr *hwmgr = adev->powerplay.pp_handle;
2485
2486         if (adev->pm.dpm_enabled == 0)
2487                 return;
2488
2489         if (adev->pm.int_hwmon_dev)
2490                 hwmon_device_unregister(adev->pm.int_hwmon_dev);
2491         device_remove_file(adev->dev, &dev_attr_power_dpm_state);
2492         device_remove_file(adev->dev, &dev_attr_power_dpm_force_performance_level);
2493
2494         device_remove_file(adev->dev, &dev_attr_pp_num_states);
2495         device_remove_file(adev->dev, &dev_attr_pp_cur_state);
2496         device_remove_file(adev->dev, &dev_attr_pp_force_state);
2497         device_remove_file(adev->dev, &dev_attr_pp_table);
2498
2499         device_remove_file(adev->dev, &dev_attr_pp_dpm_sclk);
2500         device_remove_file(adev->dev, &dev_attr_pp_dpm_mclk);
2501         if (adev->asic_type >= CHIP_VEGA10) {
2502                 device_remove_file(adev->dev, &dev_attr_pp_dpm_socclk);
2503                 device_remove_file(adev->dev, &dev_attr_pp_dpm_dcefclk);
2504         }
2505         device_remove_file(adev->dev, &dev_attr_pp_dpm_pcie);
2506         if (adev->asic_type >= CHIP_VEGA20)
2507                 device_remove_file(adev->dev, &dev_attr_pp_dpm_fclk);
2508         device_remove_file(adev->dev, &dev_attr_pp_sclk_od);
2509         device_remove_file(adev->dev, &dev_attr_pp_mclk_od);
2510         device_remove_file(adev->dev,
2511                         &dev_attr_pp_power_profile_mode);
2512         if (hwmgr->od_enabled)
2513                 device_remove_file(adev->dev,
2514                                 &dev_attr_pp_od_clk_voltage);
2515         device_remove_file(adev->dev, &dev_attr_gpu_busy_percent);
2516         if (!(adev->flags & AMD_IS_APU))
2517                 device_remove_file(adev->dev, &dev_attr_pcie_bw);
2518         if ((adev->asic_type >= CHIP_VEGA10) &&
2519             !(adev->flags & AMD_IS_APU))
2520                 device_remove_file(adev->dev, &dev_attr_ppfeatures);
2521 }
2522
2523 void amdgpu_pm_compute_clocks(struct amdgpu_device *adev)
2524 {
2525         int i = 0;
2526
2527         if (!adev->pm.dpm_enabled)
2528                 return;
2529
2530         if (adev->mode_info.num_crtc)
2531                 amdgpu_display_bandwidth_update(adev);
2532
2533         for (i = 0; i < AMDGPU_MAX_RINGS; i++) {
2534                 struct amdgpu_ring *ring = adev->rings[i];
2535                 if (ring && ring->sched.ready)
2536                         amdgpu_fence_wait_empty(ring);
2537         }
2538
2539         if (adev->powerplay.pp_funcs->dispatch_tasks) {
2540                 if (!amdgpu_device_has_dc_support(adev)) {
2541                         mutex_lock(&adev->pm.mutex);
2542                         amdgpu_dpm_get_active_displays(adev);
2543                         adev->pm.pm_display_cfg.num_display = adev->pm.dpm.new_active_crtc_count;
2544                         adev->pm.pm_display_cfg.vrefresh = amdgpu_dpm_get_vrefresh(adev);
2545                         adev->pm.pm_display_cfg.min_vblank_time = amdgpu_dpm_get_vblank_time(adev);
2546                         /* we have issues with mclk switching with refresh rates over 120 hz on the non-DC code. */
2547                         if (adev->pm.pm_display_cfg.vrefresh > 120)
2548                                 adev->pm.pm_display_cfg.min_vblank_time = 0;
2549                         if (adev->powerplay.pp_funcs->display_configuration_change)
2550                                 adev->powerplay.pp_funcs->display_configuration_change(
2551                                                                 adev->powerplay.pp_handle,
2552                                                                 &adev->pm.pm_display_cfg);
2553                         mutex_unlock(&adev->pm.mutex);
2554                 }
2555                 amdgpu_dpm_dispatch_task(adev, AMD_PP_TASK_DISPLAY_CONFIG_CHANGE, NULL);
2556         } else {
2557                 mutex_lock(&adev->pm.mutex);
2558                 amdgpu_dpm_get_active_displays(adev);
2559                 amdgpu_dpm_change_power_state_locked(adev);
2560                 mutex_unlock(&adev->pm.mutex);
2561         }
2562 }
2563
2564 /*
2565  * Debugfs info
2566  */
2567 #if defined(CONFIG_DEBUG_FS)
2568
2569 static int amdgpu_debugfs_pm_info_pp(struct seq_file *m, struct amdgpu_device *adev)
2570 {
2571         uint32_t value;
2572         uint64_t value64;
2573         uint32_t query = 0;
2574         int size;
2575
2576         /* GPU Clocks */
2577         size = sizeof(value);
2578         seq_printf(m, "GFX Clocks and Power:\n");
2579         if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_GFX_MCLK, (void *)&value, &size))
2580                 seq_printf(m, "\t%u MHz (MCLK)\n", value/100);
2581         if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_GFX_SCLK, (void *)&value, &size))
2582                 seq_printf(m, "\t%u MHz (SCLK)\n", value/100);
2583         if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_STABLE_PSTATE_SCLK, (void *)&value, &size))
2584                 seq_printf(m, "\t%u MHz (PSTATE_SCLK)\n", value/100);
2585         if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_STABLE_PSTATE_MCLK, (void *)&value, &size))
2586                 seq_printf(m, "\t%u MHz (PSTATE_MCLK)\n", value/100);
2587         if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_VDDGFX, (void *)&value, &size))
2588                 seq_printf(m, "\t%u mV (VDDGFX)\n", value);
2589         if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_VDDNB, (void *)&value, &size))
2590                 seq_printf(m, "\t%u mV (VDDNB)\n", value);
2591         size = sizeof(uint32_t);
2592         if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_GPU_POWER, (void *)&query, &size))
2593                 seq_printf(m, "\t%u.%u W (average GPU)\n", query >> 8, query & 0xff);
2594         size = sizeof(value);
2595         seq_printf(m, "\n");
2596
2597         /* GPU Temp */
2598         if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_GPU_TEMP, (void *)&value, &size))
2599                 seq_printf(m, "GPU Temperature: %u C\n", value/1000);
2600
2601         /* GPU Load */
2602         if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_GPU_LOAD, (void *)&value, &size))
2603                 seq_printf(m, "GPU Load: %u %%\n", value);
2604         seq_printf(m, "\n");
2605
2606         /* SMC feature mask */
2607         if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_ENABLED_SMC_FEATURES_MASK, (void *)&value64, &size))
2608                 seq_printf(m, "SMC Feature Mask: 0x%016llx\n", value64);
2609
2610         /* UVD clocks */
2611         if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_UVD_POWER, (void *)&value, &size)) {
2612                 if (!value) {
2613                         seq_printf(m, "UVD: Disabled\n");
2614                 } else {
2615                         seq_printf(m, "UVD: Enabled\n");
2616                         if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_UVD_DCLK, (void *)&value, &size))
2617                                 seq_printf(m, "\t%u MHz (DCLK)\n", value/100);
2618                         if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_UVD_VCLK, (void *)&value, &size))
2619                                 seq_printf(m, "\t%u MHz (VCLK)\n", value/100);
2620                 }
2621         }
2622         seq_printf(m, "\n");
2623
2624         /* VCE clocks */
2625         if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_VCE_POWER, (void *)&value, &size)) {
2626                 if (!value) {
2627                         seq_printf(m, "VCE: Disabled\n");
2628                 } else {
2629                         seq_printf(m, "VCE: Enabled\n");
2630                         if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_VCE_ECCLK, (void *)&value, &size))
2631                                 seq_printf(m, "\t%u MHz (ECCLK)\n", value/100);
2632                 }
2633         }
2634
2635         return 0;
2636 }
2637
2638 static void amdgpu_parse_cg_state(struct seq_file *m, u32 flags)
2639 {
2640         int i;
2641
2642         for (i = 0; clocks[i].flag; i++)
2643                 seq_printf(m, "\t%s: %s\n", clocks[i].name,
2644                            (flags & clocks[i].flag) ? "On" : "Off");
2645 }
2646
2647 static int amdgpu_debugfs_pm_info(struct seq_file *m, void *data)
2648 {
2649         struct drm_info_node *node = (struct drm_info_node *) m->private;
2650         struct drm_device *dev = node->minor->dev;
2651         struct amdgpu_device *adev = dev->dev_private;
2652         struct drm_device *ddev = adev->ddev;
2653         u32 flags = 0;
2654
2655         amdgpu_device_ip_get_clockgating_state(adev, &flags);
2656         seq_printf(m, "Clock Gating Flags Mask: 0x%x\n", flags);
2657         amdgpu_parse_cg_state(m, flags);
2658         seq_printf(m, "\n");
2659
2660         if (!adev->pm.dpm_enabled) {
2661                 seq_printf(m, "dpm not enabled\n");
2662                 return 0;
2663         }
2664         if  ((adev->flags & AMD_IS_PX) &&
2665              (ddev->switch_power_state != DRM_SWITCH_POWER_ON)) {
2666                 seq_printf(m, "PX asic powered off\n");
2667         } else if (adev->powerplay.pp_funcs->debugfs_print_current_performance_level) {
2668                 mutex_lock(&adev->pm.mutex);
2669                 if (adev->powerplay.pp_funcs->debugfs_print_current_performance_level)
2670                         adev->powerplay.pp_funcs->debugfs_print_current_performance_level(adev, m);
2671                 else
2672                         seq_printf(m, "Debugfs support not implemented for this asic\n");
2673                 mutex_unlock(&adev->pm.mutex);
2674         } else {
2675                 return amdgpu_debugfs_pm_info_pp(m, adev);
2676         }
2677
2678         return 0;
2679 }
2680
2681 static const struct drm_info_list amdgpu_pm_info_list[] = {
2682         {"amdgpu_pm_info", amdgpu_debugfs_pm_info, 0, NULL},
2683 };
2684 #endif
2685
2686 static int amdgpu_debugfs_pm_init(struct amdgpu_device *adev)
2687 {
2688 #if defined(CONFIG_DEBUG_FS)
2689         return amdgpu_debugfs_add_files(adev, amdgpu_pm_info_list, ARRAY_SIZE(amdgpu_pm_info_list));
2690 #else
2691         return 0;
2692 #endif
2693 }