drivers/gpu/drm/i915/intel_display.c

   1 /*
   2  * Copyright © 2006-2007 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  21  * DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *      Eric Anholt <[email protected]>
  25  */
  26
  27 #include <linux/dmi.h>
  28 #include <linux/module.h>
  29 #include <linux/input.h>
  30 #include <linux/i2c.h>
  31 #include <linux/kernel.h>
  32 #include <linux/slab.h>
  33 #include <linux/vgaarb.h>
  34 #include <drm/drm_edid.h>
  35 #include <drm/drmP.h>
  36 #include "intel_drv.h"
  37 #include <drm/i915_drm.h>
  38 #include "i915_drv.h"
  39 #include "i915_trace.h"
  40 #include <drm/drm_atomic.h>
  41 #include <drm/drm_atomic_helper.h>
  42 #include <drm/drm_dp_helper.h>
  43 #include <drm/drm_crtc_helper.h>
  44 #include <drm/drm_plane_helper.h>
  45 #include <drm/drm_rect.h>
  46 #include <linux/dma_remapping.h>
  47
  48 /* Primary plane formats for gen <= 3 */
  49 static const uint32_t i8xx_primary_formats[] = {
  50         DRM_FORMAT_C8,
  51         DRM_FORMAT_RGB565,
  52         DRM_FORMAT_XRGB1555,
  53         DRM_FORMAT_XRGB8888,
  54 };
  55
  56 /* Primary plane formats for gen >= 4 */
  57 static const uint32_t i965_primary_formats[] = {
  58         DRM_FORMAT_C8,
  59         DRM_FORMAT_RGB565,
  60         DRM_FORMAT_XRGB8888,
  61         DRM_FORMAT_XBGR8888,
  62         DRM_FORMAT_XRGB2101010,
  63         DRM_FORMAT_XBGR2101010,
  64 };
  65
  66 static const uint32_t skl_primary_formats[] = {
  67         DRM_FORMAT_C8,
  68         DRM_FORMAT_RGB565,
  69         DRM_FORMAT_XRGB8888,
  70         DRM_FORMAT_XBGR8888,
  71         DRM_FORMAT_ARGB8888,
  72         DRM_FORMAT_ABGR8888,
  73         DRM_FORMAT_XRGB2101010,
  74         DRM_FORMAT_XBGR2101010,
  75 };
  76
  77 /* Cursor formats */
  78 static const uint32_t intel_cursor_formats[] = {
  79         DRM_FORMAT_ARGB8888,
  80 };
  81
  82 static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
  83
  84 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
  85                                 struct intel_crtc_state *pipe_config);
  86 static void ironlake_pch_clock_get(struct intel_crtc *crtc,
  87                                    struct intel_crtc_state *pipe_config);
  88
  89 static int intel_set_mode(struct drm_atomic_state *state);
  90 static int intel_framebuffer_init(struct drm_device *dev,
  91                                   struct intel_framebuffer *ifb,
  92                                   struct drm_mode_fb_cmd2 *mode_cmd,
  93                                   struct drm_i915_gem_object *obj);
  94 static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc);
  95 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc);
  96 static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
  97                                          struct intel_link_m_n *m_n,
  98                                          struct intel_link_m_n *m2_n2);
  99 static void ironlake_set_pipeconf(struct drm_crtc *crtc);
 100 static void haswell_set_pipeconf(struct drm_crtc *crtc);
 101 static void intel_set_pipe_csc(struct drm_crtc *crtc);
 102 static void vlv_prepare_pll(struct intel_crtc *crtc,
 103                             const struct intel_crtc_state *pipe_config);
 104 static void chv_prepare_pll(struct intel_crtc *crtc,
 105                             const struct intel_crtc_state *pipe_config);
 106 static void intel_begin_crtc_commit(struct drm_crtc *crtc);
 107 static void intel_finish_crtc_commit(struct drm_crtc *crtc);
 108 static void skl_init_scalers(struct drm_device *dev, struct intel_crtc *intel_crtc,
 109         struct intel_crtc_state *crtc_state);
 110 static int i9xx_get_refclk(const struct intel_crtc_state *crtc_state,
 111                            int num_connectors);
 112
 113 static struct intel_encoder *intel_find_encoder(struct intel_connector *connector, int pipe)
 114 {
 115         if (!connector->mst_port)
 116                 return connector->encoder;
 117         else
 118                 return &connector->mst_port->mst_encoders[pipe]->base;
 119 }
 120
 121 typedef struct {
 122         int     min, max;
 123 } intel_range_t;
 124
 125 typedef struct {
 126         int     dot_limit;
 127         int     p2_slow, p2_fast;
 128 } intel_p2_t;
 129
 130 typedef struct intel_limit intel_limit_t;
 131 struct intel_limit {
 132         intel_range_t   dot, vco, n, m, m1, m2, p, p1;
 133         intel_p2_t          p2;
 134 };
 135
 136 int
 137 intel_pch_rawclk(struct drm_device *dev)
 138 {
 139         struct drm_i915_private *dev_priv = dev->dev_private;
 140
 141         WARN_ON(!HAS_PCH_SPLIT(dev));
 142
 143         return I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK;
 144 }
 145
 146 static inline u32 /* units of 100MHz */
 147 intel_fdi_link_freq(struct drm_device *dev)
 148 {
 149         if (IS_GEN5(dev)) {
 150                 struct drm_i915_private *dev_priv = dev->dev_private;
 151                 return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
 152         } else
 153                 return 27;
 154 }
 155
 156 static const intel_limit_t intel_limits_i8xx_dac = {
 157         .dot = { .min = 25000, .max = 350000 },
 158         .vco = { .min = 908000, .max = 1512000 },
 159         .n = { .min = 2, .max = 16 },
 160         .m = { .min = 96, .max = 140 },
 161         .m1 = { .min = 18, .max = 26 },
 162         .m2 = { .min = 6, .max = 16 },
 163         .p = { .min = 4, .max = 128 },
 164         .p1 = { .min = 2, .max = 33 },
 165         .p2 = { .dot_limit = 165000,
 166                 .p2_slow = 4, .p2_fast = 2 },
 167 };
 168
 169 static const intel_limit_t intel_limits_i8xx_dvo = {
 170         .dot = { .min = 25000, .max = 350000 },
 171         .vco = { .min = 908000, .max = 1512000 },
 172         .n = { .min = 2, .max = 16 },
 173         .m = { .min = 96, .max = 140 },
 174         .m1 = { .min = 18, .max = 26 },
 175         .m2 = { .min = 6, .max = 16 },
 176         .p = { .min = 4, .max = 128 },
 177         .p1 = { .min = 2, .max = 33 },
 178         .p2 = { .dot_limit = 165000,
 179                 .p2_slow = 4, .p2_fast = 4 },
 180 };
 181
 182 static const intel_limit_t intel_limits_i8xx_lvds = {
 183         .dot = { .min = 25000, .max = 350000 },
 184         .vco = { .min = 908000, .max = 1512000 },
 185         .n = { .min = 2, .max = 16 },
 186         .m = { .min = 96, .max = 140 },
 187         .m1 = { .min = 18, .max = 26 },
 188         .m2 = { .min = 6, .max = 16 },
 189         .p = { .min = 4, .max = 128 },
 190         .p1 = { .min = 1, .max = 6 },
 191         .p2 = { .dot_limit = 165000,
 192                 .p2_slow = 14, .p2_fast = 7 },
 193 };
 194
 195 static const intel_limit_t intel_limits_i9xx_sdvo = {
 196         .dot = { .min = 20000, .max = 400000 },
 197         .vco = { .min = 1400000, .max = 2800000 },
 198         .n = { .min = 1, .max = 6 },
 199         .m = { .min = 70, .max = 120 },
 200         .m1 = { .min = 8, .max = 18 },
 201         .m2 = { .min = 3, .max = 7 },
 202         .p = { .min = 5, .max = 80 },
 203         .p1 = { .min = 1, .max = 8 },
 204         .p2 = { .dot_limit = 200000,
 205                 .p2_slow = 10, .p2_fast = 5 },
 206 };
 207
 208 static const intel_limit_t intel_limits_i9xx_lvds = {
 209         .dot = { .min = 20000, .max = 400000 },
 210         .vco = { .min = 1400000, .max = 2800000 },
 211         .n = { .min = 1, .max = 6 },
 212         .m = { .min = 70, .max = 120 },
 213         .m1 = { .min = 8, .max = 18 },
 214         .m2 = { .min = 3, .max = 7 },
 215         .p = { .min = 7, .max = 98 },
 216         .p1 = { .min = 1, .max = 8 },
 217         .p2 = { .dot_limit = 112000,
 218                 .p2_slow = 14, .p2_fast = 7 },
 219 };
 220
 221
 222 static const intel_limit_t intel_limits_g4x_sdvo = {
 223         .dot = { .min = 25000, .max = 270000 },
 224         .vco = { .min = 1750000, .max = 3500000},
 225         .n = { .min = 1, .max = 4 },
 226         .m = { .min = 104, .max = 138 },
 227         .m1 = { .min = 17, .max = 23 },
 228         .m2 = { .min = 5, .max = 11 },
 229         .p = { .min = 10, .max = 30 },
 230         .p1 = { .min = 1, .max = 3},
 231         .p2 = { .dot_limit = 270000,
 232                 .p2_slow = 10,
 233                 .p2_fast = 10
 234         },
 235 };
 236
 237 static const intel_limit_t intel_limits_g4x_hdmi = {
 238         .dot = { .min = 22000, .max = 400000 },
 239         .vco = { .min = 1750000, .max = 3500000},
 240         .n = { .min = 1, .max = 4 },
 241         .m = { .min = 104, .max = 138 },
 242         .m1 = { .min = 16, .max = 23 },
 243         .m2 = { .min = 5, .max = 11 },
 244         .p = { .min = 5, .max = 80 },
 245         .p1 = { .min = 1, .max = 8},
 246         .p2 = { .dot_limit = 165000,
 247                 .p2_slow = 10, .p2_fast = 5 },
 248 };
 249
 250 static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
 251         .dot = { .min = 20000, .max = 115000 },
 252         .vco = { .min = 1750000, .max = 3500000 },
 253         .n = { .min = 1, .max = 3 },
 254         .m = { .min = 104, .max = 138 },
 255         .m1 = { .min = 17, .max = 23 },
 256         .m2 = { .min = 5, .max = 11 },
 257         .p = { .min = 28, .max = 112 },
 258         .p1 = { .min = 2, .max = 8 },
 259         .p2 = { .dot_limit = 0,
 260                 .p2_slow = 14, .p2_fast = 14
 261         },
 262 };
 263
 264 static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
 265         .dot = { .min = 80000, .max = 224000 },
 266         .vco = { .min = 1750000, .max = 3500000 },
 267         .n = { .min = 1, .max = 3 },
 268         .m = { .min = 104, .max = 138 },
 269         .m1 = { .min = 17, .max = 23 },
 270         .m2 = { .min = 5, .max = 11 },
 271         .p = { .min = 14, .max = 42 },
 272         .p1 = { .min = 2, .max = 6 },
 273         .p2 = { .dot_limit = 0,
 274                 .p2_slow = 7, .p2_fast = 7
 275         },
 276 };
 277
 278 static const intel_limit_t intel_limits_pineview_sdvo = {
 279         .dot = { .min = 20000, .max = 400000},
 280         .vco = { .min = 1700000, .max = 3500000 },
 281         /* Pineview's Ncounter is a ring counter */
 282         .n = { .min = 3, .max = 6 },
 283         .m = { .min = 2, .max = 256 },
 284         /* Pineview only has one combined m divider, which we treat as m2. */
 285         .m1 = { .min = 0, .max = 0 },
 286         .m2 = { .min = 0, .max = 254 },
 287         .p = { .min = 5, .max = 80 },
 288         .p1 = { .min = 1, .max = 8 },
 289         .p2 = { .dot_limit = 200000,
 290                 .p2_slow = 10, .p2_fast = 5 },
 291 };
 292
 293 static const intel_limit_t intel_limits_pineview_lvds = {
 294         .dot = { .min = 20000, .max = 400000 },
 295         .vco = { .min = 1700000, .max = 3500000 },
 296         .n = { .min = 3, .max = 6 },
 297         .m = { .min = 2, .max = 256 },
 298         .m1 = { .min = 0, .max = 0 },
 299         .m2 = { .min = 0, .max = 254 },
 300         .p = { .min = 7, .max = 112 },
 301         .p1 = { .min = 1, .max = 8 },
 302         .p2 = { .dot_limit = 112000,
 303                 .p2_slow = 14, .p2_fast = 14 },
 304 };
 305
 306 /* Ironlake / Sandybridge
 307  *
 308  * We calculate clock using (register_value + 2) for N/M1/M2, so here
 309  * the range value for them is (actual_value - 2).
 310  */
 311 static const intel_limit_t intel_limits_ironlake_dac = {
 312         .dot = { .min = 25000, .max = 350000 },
 313         .vco = { .min = 1760000, .max = 3510000 },
 314         .n = { .min = 1, .max = 5 },
 315         .m = { .min = 79, .max = 127 },
 316         .m1 = { .min = 12, .max = 22 },
 317         .m2 = { .min = 5, .max = 9 },
 318         .p = { .min = 5, .max = 80 },
 319         .p1 = { .min = 1, .max = 8 },
 320         .p2 = { .dot_limit = 225000,
 321                 .p2_slow = 10, .p2_fast = 5 },
 322 };
 323
 324 static const intel_limit_t intel_limits_ironlake_single_lvds = {
 325         .dot = { .min = 25000, .max = 350000 },
 326         .vco = { .min = 1760000, .max = 3510000 },
 327         .n = { .min = 1, .max = 3 },
 328         .m = { .min = 79, .max = 118 },
 329         .m1 = { .min = 12, .max = 22 },
 330         .m2 = { .min = 5, .max = 9 },
 331         .p = { .min = 28, .max = 112 },
 332         .p1 = { .min = 2, .max = 8 },
 333         .p2 = { .dot_limit = 225000,
 334                 .p2_slow = 14, .p2_fast = 14 },
 335 };
 336
 337 static const intel_limit_t intel_limits_ironlake_dual_lvds = {
 338         .dot = { .min = 25000, .max = 350000 },
 339         .vco = { .min = 1760000, .max = 3510000 },
 340         .n = { .min = 1, .max = 3 },
 341         .m = { .min = 79, .max = 127 },
 342         .m1 = { .min = 12, .max = 22 },
 343         .m2 = { .min = 5, .max = 9 },
 344         .p = { .min = 14, .max = 56 },
 345         .p1 = { .min = 2, .max = 8 },
 346         .p2 = { .dot_limit = 225000,
 347                 .p2_slow = 7, .p2_fast = 7 },
 348 };
 349
 350 /* LVDS 100mhz refclk limits. */
 351 static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
 352         .dot = { .min = 25000, .max = 350000 },
 353         .vco = { .min = 1760000, .max = 3510000 },
 354         .n = { .min = 1, .max = 2 },
 355         .m = { .min = 79, .max = 126 },
 356         .m1 = { .min = 12, .max = 22 },
 357         .m2 = { .min = 5, .max = 9 },
 358         .p = { .min = 28, .max = 112 },
 359         .p1 = { .min = 2, .max = 8 },
 360         .p2 = { .dot_limit = 225000,
 361                 .p2_slow = 14, .p2_fast = 14 },
 362 };
 363
 364 static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
 365         .dot = { .min = 25000, .max = 350000 },
 366         .vco = { .min = 1760000, .max = 3510000 },
 367         .n = { .min = 1, .max = 3 },
 368         .m = { .min = 79, .max = 126 },
 369         .m1 = { .min = 12, .max = 22 },
 370         .m2 = { .min = 5, .max = 9 },
 371         .p = { .min = 14, .max = 42 },
 372         .p1 = { .min = 2, .max = 6 },
 373         .p2 = { .dot_limit = 225000,
 374                 .p2_slow = 7, .p2_fast = 7 },
 375 };
 376
 377 static const intel_limit_t intel_limits_vlv = {
 378          /*
 379           * These are the data rate limits (measured in fast clocks)
 380           * since those are the strictest limits we have. The fast
 381           * clock and actual rate limits are more relaxed, so checking
 382           * them would make no difference.
 383           */
 384         .dot = { .min = 25000 * 5, .max = 270000 * 5 },
 385         .vco = { .min = 4000000, .max = 6000000 },
 386         .n = { .min = 1, .max = 7 },
 387         .m1 = { .min = 2, .max = 3 },
 388         .m2 = { .min = 11, .max = 156 },
 389         .p1 = { .min = 2, .max = 3 },
 390         .p2 = { .p2_slow = 2, .p2_fast = 20 }, /* slow=min, fast=max */
 391 };
 392
 393 static const intel_limit_t intel_limits_chv = {
 394         /*
 395          * These are the data rate limits (measured in fast clocks)
 396          * since those are the strictest limits we have.  The fast
 397          * clock and actual rate limits are more relaxed, so checking
 398          * them would make no difference.
 399          */
 400         .dot = { .min = 25000 * 5, .max = 540000 * 5},
 401         .vco = { .min = 4800000, .max = 6480000 },
 402         .n = { .min = 1, .max = 1 },
 403         .m1 = { .min = 2, .max = 2 },
 404         .m2 = { .min = 24 << 22, .max = 175 << 22 },
 405         .p1 = { .min = 2, .max = 4 },
 406         .p2 = { .p2_slow = 1, .p2_fast = 14 },
 407 };
 408
 409 static const intel_limit_t intel_limits_bxt = {
 410         /* FIXME: find real dot limits */
 411         .dot = { .min = 0, .max = INT_MAX },
 412         .vco = { .min = 4800000, .max = 6480000 },
 413         .n = { .min = 1, .max = 1 },
 414         .m1 = { .min = 2, .max = 2 },
 415         /* FIXME: find real m2 limits */
 416         .m2 = { .min = 2 << 22, .max = 255 << 22 },
 417         .p1 = { .min = 2, .max = 4 },
 418         .p2 = { .p2_slow = 1, .p2_fast = 20 },
 419 };
 420
 421 static void vlv_clock(int refclk, intel_clock_t *clock)
 422 {
 423         clock->m = clock->m1 * clock->m2;
 424         clock->p = clock->p1 * clock->p2;
 425         if (WARN_ON(clock->n == 0 || clock->p == 0))
 426                 return;
 427         clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
 428         clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
 429 }
 430
 431 static bool
 432 needs_modeset(struct drm_crtc_state *state)
 433 {
 434         return state->mode_changed || state->active_changed;
 435 }
 436
 437 /**
 438  * Returns whether any output on the specified pipe is of the specified type
 439  */
 440 bool intel_pipe_has_type(struct intel_crtc *crtc, enum intel_output_type type)
 441 {
 442         struct drm_device *dev = crtc->base.dev;
 443         struct intel_encoder *encoder;
 444
 445         for_each_encoder_on_crtc(dev, &crtc->base, encoder)
 446                 if (encoder->type == type)
 447                         return true;
 448
 449         return false;
 450 }
 451
 452 /**
 453  * Returns whether any output on the specified pipe will have the specified
 454  * type after a staged modeset is complete, i.e., the same as
 455  * intel_pipe_has_type() but looking at encoder->new_crtc instead of
 456  * encoder->crtc.
 457  */
 458 static bool intel_pipe_will_have_type(const struct intel_crtc_state *crtc_state,
 459                                       int type)
 460 {
 461         struct drm_atomic_state *state = crtc_state->base.state;
 462         struct drm_connector *connector;
 463         struct drm_connector_state *connector_state;
 464         struct intel_encoder *encoder;
 465         int i, num_connectors = 0;
 466
 467         for_each_connector_in_state(state, connector, connector_state, i) {
 468                 if (connector_state->crtc != crtc_state->base.crtc)
 469                         continue;
 470
 471                 num_connectors++;
 472
 473                 encoder = to_intel_encoder(connector_state->best_encoder);
 474                 if (encoder->type == type)
 475                         return true;
 476         }
 477
 478         WARN_ON(num_connectors == 0);
 479
 480         return false;
 481 }
 482
 483 static const intel_limit_t *
 484 intel_ironlake_limit(struct intel_crtc_state *crtc_state, int refclk)
 485 {
 486         struct drm_device *dev = crtc_state->base.crtc->dev;
 487         const intel_limit_t *limit;
 488
 489         if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
 490                 if (intel_is_dual_link_lvds(dev)) {
 491                         if (refclk == 100000)
 492                                 limit = &intel_limits_ironlake_dual_lvds_100m;
 493                         else
 494                                 limit = &intel_limits_ironlake_dual_lvds;
 495                 } else {
 496                         if (refclk == 100000)
 497                                 limit = &intel_limits_ironlake_single_lvds_100m;
 498                         else
 499                                 limit = &intel_limits_ironlake_single_lvds;
 500                 }
 501         } else
 502                 limit = &intel_limits_ironlake_dac;
 503
 504         return limit;
 505 }
 506
 507 static const intel_limit_t *
 508 intel_g4x_limit(struct intel_crtc_state *crtc_state)
 509 {
 510         struct drm_device *dev = crtc_state->base.crtc->dev;
 511         const intel_limit_t *limit;
 512
 513         if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
 514                 if (intel_is_dual_link_lvds(dev))
 515                         limit = &intel_limits_g4x_dual_channel_lvds;
 516                 else
 517                         limit = &intel_limits_g4x_single_channel_lvds;
 518         } else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_HDMI) ||
 519                    intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_ANALOG)) {
 520                 limit = &intel_limits_g4x_hdmi;
 521         } else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_SDVO)) {
 522                 limit = &intel_limits_g4x_sdvo;
 523         } else /* The option is for other outputs */
 524                 limit = &intel_limits_i9xx_sdvo;
 525
 526         return limit;
 527 }
 528
 529 static const intel_limit_t *
 530 intel_limit(struct intel_crtc_state *crtc_state, int refclk)
 531 {
 532         struct drm_device *dev = crtc_state->base.crtc->dev;
 533         const intel_limit_t *limit;
 534
 535         if (IS_BROXTON(dev))
 536                 limit = &intel_limits_bxt;
 537         else if (HAS_PCH_SPLIT(dev))
 538                 limit = intel_ironlake_limit(crtc_state, refclk);
 539         else if (IS_G4X(dev)) {
 540                 limit = intel_g4x_limit(crtc_state);
 541         } else if (IS_PINEVIEW(dev)) {
 542                 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS))
 543                         limit = &intel_limits_pineview_lvds;
 544                 else
 545                         limit = &intel_limits_pineview_sdvo;
 546         } else if (IS_CHERRYVIEW(dev)) {
 547                 limit = &intel_limits_chv;
 548         } else if (IS_VALLEYVIEW(dev)) {
 549                 limit = &intel_limits_vlv;
 550         } else if (!IS_GEN2(dev)) {
 551                 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS))
 552                         limit = &intel_limits_i9xx_lvds;
 553                 else
 554                         limit = &intel_limits_i9xx_sdvo;
 555         } else {
 556                 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS))
 557                         limit = &intel_limits_i8xx_lvds;
 558                 else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_DVO))
 559                         limit = &intel_limits_i8xx_dvo;
 560                 else
 561                         limit = &intel_limits_i8xx_dac;
 562         }
 563         return limit;
 564 }
 565
 566 /* m1 is reserved as 0 in Pineview, n is a ring counter */
 567 static void pineview_clock(int refclk, intel_clock_t *clock)
 568 {
 569         clock->m = clock->m2 + 2;
 570         clock->p = clock->p1 * clock->p2;
 571         if (WARN_ON(clock->n == 0 || clock->p == 0))
 572                 return;
 573         clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
 574         clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
 575 }
 576
 577 static uint32_t i9xx_dpll_compute_m(struct dpll *dpll)
 578 {
 579         return 5 * (dpll->m1 + 2) + (dpll->m2 + 2);
 580 }
 581
 582 static void i9xx_clock(int refclk, intel_clock_t *clock)
 583 {
 584         clock->m = i9xx_dpll_compute_m(clock);
 585         clock->p = clock->p1 * clock->p2;
 586         if (WARN_ON(clock->n + 2 == 0 || clock->p == 0))
 587                 return;
 588         clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n + 2);
 589         clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
 590 }
 591
 592 static void chv_clock(int refclk, intel_clock_t *clock)
 593 {
 594         clock->m = clock->m1 * clock->m2;
 595         clock->p = clock->p1 * clock->p2;
 596         if (WARN_ON(clock->n == 0 || clock->p == 0))
 597                 return;
 598         clock->vco = DIV_ROUND_CLOSEST_ULL((uint64_t)refclk * clock->m,
 599                         clock->n << 22);
 600         clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
 601 }
 602
 603 #define INTELPllInvalid(s)   do { /* DRM_DEBUG(s); */ return false; } while (0)
 604 /**
 605  * Returns whether the given set of divisors are valid for a given refclk with
 606  * the given connectors.
 607  */
 608
 609 static bool intel_PLL_is_valid(struct drm_device *dev,
 610                                const intel_limit_t *limit,
 611                                const intel_clock_t *clock)
 612 {
 613         if (clock->n   < limit->n.min   || limit->n.max   < clock->n)
 614                 INTELPllInvalid("n out of range\n");
 615         if (clock->p1  < limit->p1.min  || limit->p1.max  < clock->p1)
 616                 INTELPllInvalid("p1 out of range\n");
 617         if (clock->m2  < limit->m2.min  || limit->m2.max  < clock->m2)
 618                 INTELPllInvalid("m2 out of range\n");
 619         if (clock->m1  < limit->m1.min  || limit->m1.max  < clock->m1)
 620                 INTELPllInvalid("m1 out of range\n");
 621
 622         if (!IS_PINEVIEW(dev) && !IS_VALLEYVIEW(dev) && !IS_BROXTON(dev))
 623                 if (clock->m1 <= clock->m2)
 624                         INTELPllInvalid("m1 <= m2\n");
 625
 626         if (!IS_VALLEYVIEW(dev) && !IS_BROXTON(dev)) {
 627                 if (clock->p < limit->p.min || limit->p.max < clock->p)
 628                         INTELPllInvalid("p out of range\n");
 629                 if (clock->m < limit->m.min || limit->m.max < clock->m)
 630                         INTELPllInvalid("m out of range\n");
 631         }
 632
 633         if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
 634                 INTELPllInvalid("vco out of range\n");
 635         /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
 636          * connector, etc., rather than just a single range.
 637          */
 638         if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
 639                 INTELPllInvalid("dot out of range\n");
 640
 641         return true;
 642 }
 643
 644 static int
 645 i9xx_select_p2_div(const intel_limit_t *limit,
 646                    const struct intel_crtc_state *crtc_state,
 647                    int target)
 648 {
 649         struct drm_device *dev = crtc_state->base.crtc->dev;
 650
 651         if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
 652                 /*
 653                  * For LVDS just rely on its current settings for dual-channel.
 654                  * We haven't figured out how to reliably set up different
 655                  * single/dual channel state, if we even can.
 656                  */
 657                 if (intel_is_dual_link_lvds(dev))
 658                         return limit->p2.p2_fast;
 659                 else
 660                         return limit->p2.p2_slow;
 661         } else {
 662                 if (target < limit->p2.dot_limit)
 663                         return limit->p2.p2_slow;
 664                 else
 665                         return limit->p2.p2_fast;
 666         }
 667 }
 668
 669 static bool
 670 i9xx_find_best_dpll(const intel_limit_t *limit,
 671                     struct intel_crtc_state *crtc_state,
 672                     int target, int refclk, intel_clock_t *match_clock,
 673                     intel_clock_t *best_clock)
 674 {
 675         struct drm_device *dev = crtc_state->base.crtc->dev;
 676         intel_clock_t clock;
 677         int err = target;
 678
 679         memset(best_clock, 0, sizeof(*best_clock));
 680
 681         clock.p2 = i9xx_select_p2_div(limit, crtc_state, target);
 682
 683         for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
 684              clock.m1++) {
 685                 for (clock.m2 = limit->m2.min;
 686                      clock.m2 <= limit->m2.max; clock.m2++) {
 687                         if (clock.m2 >= clock.m1)
 688                                 break;
 689                         for (clock.n = limit->n.min;
 690                              clock.n <= limit->n.max; clock.n++) {
 691                                 for (clock.p1 = limit->p1.min;
 692                                         clock.p1 <= limit->p1.max; clock.p1++) {
 693                                         int this_err;
 694
 695                                         i9xx_clock(refclk, &clock);
 696                                         if (!intel_PLL_is_valid(dev, limit,
 697                                                                 &clock))
 698                                                 continue;
 699                                         if (match_clock &&
 700                                             clock.p != match_clock->p)
 701                                                 continue;
 702
 703                                         this_err = abs(clock.dot - target);
 704                                         if (this_err < err) {
 705                                                 *best_clock = clock;
 706                                                 err = this_err;
 707                                         }
 708                                 }
 709                         }
 710                 }
 711         }
 712
 713         return (err != target);
 714 }
 715
 716 static bool
 717 pnv_find_best_dpll(const intel_limit_t *limit,
 718                    struct intel_crtc_state *crtc_state,
 719                    int target, int refclk, intel_clock_t *match_clock,
 720                    intel_clock_t *best_clock)
 721 {
 722         struct drm_device *dev = crtc_state->base.crtc->dev;
 723         intel_clock_t clock;
 724         int err = target;
 725
 726         memset(best_clock, 0, sizeof(*best_clock));
 727
 728         clock.p2 = i9xx_select_p2_div(limit, crtc_state, target);
 729
 730         for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
 731              clock.m1++) {
 732                 for (clock.m2 = limit->m2.min;
 733                      clock.m2 <= limit->m2.max; clock.m2++) {
 734                         for (clock.n = limit->n.min;
 735                              clock.n <= limit->n.max; clock.n++) {
 736                                 for (clock.p1 = limit->p1.min;
 737                                         clock.p1 <= limit->p1.max; clock.p1++) {
 738                                         int this_err;
 739
 740                                         pineview_clock(refclk, &clock);
 741                                         if (!intel_PLL_is_valid(dev, limit,
 742                                                                 &clock))
 743                                                 continue;
 744                                         if (match_clock &&
 745                                             clock.p != match_clock->p)
 746                                                 continue;
 747
 748                                         this_err = abs(clock.dot - target);
 749                                         if (this_err < err) {
 750                                                 *best_clock = clock;
 751                                                 err = this_err;
 752                                         }
 753                                 }
 754                         }
 755                 }
 756         }
 757
 758         return (err != target);
 759 }
 760
 761 static bool
 762 g4x_find_best_dpll(const intel_limit_t *limit,
 763                    struct intel_crtc_state *crtc_state,
 764                    int target, int refclk, intel_clock_t *match_clock,
 765                    intel_clock_t *best_clock)
 766 {
 767         struct drm_device *dev = crtc_state->base.crtc->dev;
 768         intel_clock_t clock;
 769         int max_n;
 770         bool found = false;
 771         /* approximately equals target * 0.00585 */
 772         int err_most = (target >> 8) + (target >> 9);
 773
 774         memset(best_clock, 0, sizeof(*best_clock));
 775
 776         clock.p2 = i9xx_select_p2_div(limit, crtc_state, target);
 777
 778         max_n = limit->n.max;
 779         /* based on hardware requirement, prefer smaller n to precision */
 780         for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
 781                 /* based on hardware requirement, prefere larger m1,m2 */
 782                 for (clock.m1 = limit->m1.max;
 783                      clock.m1 >= limit->m1.min; clock.m1--) {
 784                         for (clock.m2 = limit->m2.max;
 785                              clock.m2 >= limit->m2.min; clock.m2--) {
 786                                 for (clock.p1 = limit->p1.max;
 787                                      clock.p1 >= limit->p1.min; clock.p1--) {
 788                                         int this_err;
 789
 790                                         i9xx_clock(refclk, &clock);
 791                                         if (!intel_PLL_is_valid(dev, limit,
 792                                                                 &clock))
 793                                                 continue;
 794
 795                                         this_err = abs(clock.dot - target);
 796                                         if (this_err < err_most) {
 797                                                 *best_clock = clock;
 798                                                 err_most = this_err;
 799                                                 max_n = clock.n;
 800                                                 found = true;
 801                                         }
 802                                 }
 803                         }
 804                 }
 805         }
 806         return found;
 807 }
 808
 809 /*
 810  * Check if the calculated PLL configuration is more optimal compared to the
 811  * best configuration and error found so far. Return the calculated error.
 812  */
 813 static bool vlv_PLL_is_optimal(struct drm_device *dev, int target_freq,
 814                                const intel_clock_t *calculated_clock,
 815                                const intel_clock_t *best_clock,
 816                                unsigned int best_error_ppm,
 817                                unsigned int *error_ppm)
 818 {
 819         /*
 820          * For CHV ignore the error and consider only the P value.
 821          * Prefer a bigger P value based on HW requirements.
 822          */
 823         if (IS_CHERRYVIEW(dev)) {
 824                 *error_ppm = 0;
 825
 826                 return calculated_clock->p > best_clock->p;
 827         }
 828
 829         if (WARN_ON_ONCE(!target_freq))
 830                 return false;
 831
 832         *error_ppm = div_u64(1000000ULL *
 833                                 abs(target_freq - calculated_clock->dot),
 834                              target_freq);
 835         /*
 836          * Prefer a better P value over a better (smaller) error if the error
 837          * is small. Ensure this preference for future configurations too by
 838          * setting the error to 0.
 839          */
 840         if (*error_ppm < 100 && calculated_clock->p > best_clock->p) {
 841                 *error_ppm = 0;
 842
 843                 return true;
 844         }
 845
 846         return *error_ppm + 10 < best_error_ppm;
 847 }
 848
 849 static bool
 850 vlv_find_best_dpll(const intel_limit_t *limit,
 851                    struct intel_crtc_state *crtc_state,
 852                    int target, int refclk, intel_clock_t *match_clock,
 853                    intel_clock_t *best_clock)
 854 {
 855         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
 856         struct drm_device *dev = crtc->base.dev;
 857         intel_clock_t clock;
 858         unsigned int bestppm = 1000000;
 859         /* min update 19.2 MHz */
 860         int max_n = min(limit->n.max, refclk / 19200);
 861         bool found = false;
 862
 863         target *= 5; /* fast clock */
 864
 865         memset(best_clock, 0, sizeof(*best_clock));
 866
 867         /* based on hardware requirement, prefer smaller n to precision */
 868         for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
 869                 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
 870                         for (clock.p2 = limit->p2.p2_fast; clock.p2 >= limit->p2.p2_slow;
 871                              clock.p2 -= clock.p2 > 10 ? 2 : 1) {
 872                                 clock.p = clock.p1 * clock.p2;
 873                                 /* based on hardware requirement, prefer bigger m1,m2 values */
 874                                 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; clock.m1++) {
 875                                         unsigned int ppm;
 876
 877                                         clock.m2 = DIV_ROUND_CLOSEST(target * clock.p * clock.n,
 878                                                                      refclk * clock.m1);
 879
 880                                         vlv_clock(refclk, &clock);
 881
 882                                         if (!intel_PLL_is_valid(dev, limit,
 883                                                                 &clock))
 884                                                 continue;
 885
 886                                         if (!vlv_PLL_is_optimal(dev, target,
 887                                                                 &clock,
 888                                                                 best_clock,
 889                                                                 bestppm, &ppm))
 890                                                 continue;
 891
 892                                         *best_clock = clock;
 893                                         bestppm = ppm;
 894                                         found = true;
 895                                 }
 896                         }
 897                 }
 898         }
 899
 900         return found;
 901 }
 902
 903 static bool
 904 chv_find_best_dpll(const intel_limit_t *limit,
 905                    struct intel_crtc_state *crtc_state,
 906                    int target, int refclk, intel_clock_t *match_clock,
 907                    intel_clock_t *best_clock)
 908 {
 909         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
 910         struct drm_device *dev = crtc->base.dev;
 911         unsigned int best_error_ppm;
 912         intel_clock_t clock;
 913         uint64_t m2;
 914         int found = false;
 915
 916         memset(best_clock, 0, sizeof(*best_clock));
 917         best_error_ppm = 1000000;
 918
 919         /*
 920          * Based on hardware doc, the n always set to 1, and m1 always
 921          * set to 2.  If requires to support 200Mhz refclk, we need to
 922          * revisit this because n may not 1 anymore.
 923          */
 924         clock.n = 1, clock.m1 = 2;
 925         target *= 5;    /* fast clock */
 926
 927         for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
 928                 for (clock.p2 = limit->p2.p2_fast;
 929                                 clock.p2 >= limit->p2.p2_slow;
 930                                 clock.p2 -= clock.p2 > 10 ? 2 : 1) {
 931                         unsigned int error_ppm;
 932
 933                         clock.p = clock.p1 * clock.p2;
 934
 935                         m2 = DIV_ROUND_CLOSEST_ULL(((uint64_t)target * clock.p *
 936                                         clock.n) << 22, refclk * clock.m1);
 937
 938                         if (m2 > INT_MAX/clock.m1)
 939                                 continue;
 940
 941                         clock.m2 = m2;
 942
 943                         chv_clock(refclk, &clock);
 944
 945                         if (!intel_PLL_is_valid(dev, limit, &clock))
 946                                 continue;
 947
 948                         if (!vlv_PLL_is_optimal(dev, target, &clock, best_clock,
 949                                                 best_error_ppm, &error_ppm))
 950                                 continue;
 951
 952                         *best_clock = clock;
 953                         best_error_ppm = error_ppm;
 954                         found = true;
 955                 }
 956         }
 957
 958         return found;
 959 }
 960
 961 bool bxt_find_best_dpll(struct intel_crtc_state *crtc_state, int target_clock,
 962                         intel_clock_t *best_clock)
 963 {
 964         int refclk = i9xx_get_refclk(crtc_state, 0);
 965
 966         return chv_find_best_dpll(intel_limit(crtc_state, refclk), crtc_state,
 967                                   target_clock, refclk, NULL, best_clock);
 968 }
 969
 970 bool intel_crtc_active(struct drm_crtc *crtc)
 971 {
 972         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 973
 974         /* Be paranoid as we can arrive here with only partial
 975          * state retrieved from the hardware during setup.
 976          *
 977          * We can ditch the adjusted_mode.crtc_clock check as soon
 978          * as Haswell has gained clock readout/fastboot support.
 979          *
 980          * We can ditch the crtc->primary->fb check as soon as we can
 981          * properly reconstruct framebuffers.
 982          *
 983          * FIXME: The intel_crtc->active here should be switched to
 984          * crtc->state->active once we have proper CRTC states wired up
 985          * for atomic.
 986          */
 987         return intel_crtc->active && crtc->primary->state->fb &&
 988                 intel_crtc->config->base.adjusted_mode.crtc_clock;
 989 }
 990
 991 enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
 992                                              enum pipe pipe)
 993 {
 994         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
 995         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 996
 997         return intel_crtc->config->cpu_transcoder;
 998 }
 999
1000 static bool pipe_dsl_stopped(struct drm_device *dev, enum pipe pipe)
1001 {
1002         struct drm_i915_private *dev_priv = dev->dev_private;
1003         u32 reg = PIPEDSL(pipe);
1004         u32 line1, line2;
1005         u32 line_mask;
1006
1007         if (IS_GEN2(dev))
1008                 line_mask = DSL_LINEMASK_GEN2;
1009         else
1010                 line_mask = DSL_LINEMASK_GEN3;
1011
1012         line1 = I915_READ(reg) & line_mask;
1013         mdelay(5);
1014         line2 = I915_READ(reg) & line_mask;
1015
1016         return line1 == line2;
1017 }
1018
1019 /*
1020  * intel_wait_for_pipe_off - wait for pipe to turn off
1021  * @crtc: crtc whose pipe to wait for
1022  *
1023  * After disabling a pipe, we can't wait for vblank in the usual way,
1024  * spinning on the vblank interrupt status bit, since we won't actually
1025  * see an interrupt when the pipe is disabled.
1026  *
1027  * On Gen4 and above:
1028  *   wait for the pipe register state bit to turn off
1029  *
1030  * Otherwise:
1031  *   wait for the display line value to settle (it usually
1032  *   ends up stopping at the start of the next frame).
1033  *
1034  */
1035 static void intel_wait_for_pipe_off(struct intel_crtc *crtc)
1036 {
1037         struct drm_device *dev = crtc->base.dev;
1038         struct drm_i915_private *dev_priv = dev->dev_private;
1039         enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
1040         enum pipe pipe = crtc->pipe;
1041
1042         if (INTEL_INFO(dev)->gen >= 4) {
1043                 int reg = PIPECONF(cpu_transcoder);
1044
1045                 /* Wait for the Pipe State to go off */
1046                 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
1047                              100))
1048                         WARN(1, "pipe_off wait timed out\n");
1049         } else {
1050                 /* Wait for the display line to settle */
1051                 if (wait_for(pipe_dsl_stopped(dev, pipe), 100))
1052                         WARN(1, "pipe_off wait timed out\n");
1053         }
1054 }
1055
1056 /*
1057  * ibx_digital_port_connected - is the specified port connected?
1058  * @dev_priv: i915 private structure
1059  * @port: the port to test
1060  *
1061  * Returns true if @port is connected, false otherwise.
1062  */
1063 bool ibx_digital_port_connected(struct drm_i915_private *dev_priv,
1064                                 struct intel_digital_port *port)
1065 {
1066         u32 bit;
1067
1068         if (HAS_PCH_IBX(dev_priv->dev)) {
1069                 switch (port->port) {
1070                 case PORT_B:
1071                         bit = SDE_PORTB_HOTPLUG;
1072                         break;
1073                 case PORT_C:
1074                         bit = SDE_PORTC_HOTPLUG;
1075                         break;
1076                 case PORT_D:
1077                         bit = SDE_PORTD_HOTPLUG;
1078                         break;
1079                 default:
1080                         return true;
1081                 }
1082         } else {
1083                 switch (port->port) {
1084                 case PORT_B:
1085                         bit = SDE_PORTB_HOTPLUG_CPT;
1086                         break;
1087                 case PORT_C:
1088                         bit = SDE_PORTC_HOTPLUG_CPT;
1089                         break;
1090                 case PORT_D:
1091                         bit = SDE_PORTD_HOTPLUG_CPT;
1092                         break;
1093                 default:
1094                         return true;
1095                 }
1096         }
1097
1098         return I915_READ(SDEISR) & bit;
1099 }
1100
1101 static const char *state_string(bool enabled)
1102 {
1103         return enabled ? "on" : "off";
1104 }
1105
1106 /* Only for pre-ILK configs */
1107 void assert_pll(struct drm_i915_private *dev_priv,
1108                 enum pipe pipe, bool state)
1109 {
1110         int reg;
1111         u32 val;
1112         bool cur_state;
1113
1114         reg = DPLL(pipe);
1115         val = I915_READ(reg);
1116         cur_state = !!(val & DPLL_VCO_ENABLE);
1117         I915_STATE_WARN(cur_state != state,
1118              "PLL state assertion failure (expected %s, current %s)\n",
1119              state_string(state), state_string(cur_state));
1120 }
1121
1122 /* XXX: the dsi pll is shared between MIPI DSI ports */
1123 static void assert_dsi_pll(struct drm_i915_private *dev_priv, bool state)
1124 {
1125         u32 val;
1126         bool cur_state;
1127
1128         mutex_lock(&dev_priv->sb_lock);
1129         val = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL);
1130         mutex_unlock(&dev_priv->sb_lock);
1131
1132         cur_state = val & DSI_PLL_VCO_EN;
1133         I915_STATE_WARN(cur_state != state,
1134              "DSI PLL state assertion failure (expected %s, current %s)\n",
1135              state_string(state), state_string(cur_state));
1136 }
1137 #define assert_dsi_pll_enabled(d) assert_dsi_pll(d, true)
1138 #define assert_dsi_pll_disabled(d) assert_dsi_pll(d, false)
1139
1140 struct intel_shared_dpll *
1141 intel_crtc_to_shared_dpll(struct intel_crtc *crtc)
1142 {
1143         struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
1144
1145         if (crtc->config->shared_dpll < 0)
1146                 return NULL;
1147
1148         return &dev_priv->shared_dplls[crtc->config->shared_dpll];
1149 }
1150
1151 /* For ILK+ */
1152 void assert_shared_dpll(struct drm_i915_private *dev_priv,
1153                         struct intel_shared_dpll *pll,
1154                         bool state)
1155 {
1156         bool cur_state;
1157         struct intel_dpll_hw_state hw_state;
1158
1159         if (WARN (!pll,
1160                   "asserting DPLL %s with no DPLL\n", state_string(state)))
1161                 return;
1162
1163         cur_state = pll->get_hw_state(dev_priv, pll, &hw_state);
1164         I915_STATE_WARN(cur_state != state,
1165              "%s assertion failure (expected %s, current %s)\n",
1166              pll->name, state_string(state), state_string(cur_state));
1167 }
1168
1169 static void assert_fdi_tx(struct drm_i915_private *dev_priv,
1170                           enum pipe pipe, bool state)
1171 {
1172         int reg;
1173         u32 val;
1174         bool cur_state;
1175         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1176                                                                       pipe);
1177
1178         if (HAS_DDI(dev_priv->dev)) {
1179                 /* DDI does not have a specific FDI_TX register */
1180                 reg = TRANS_DDI_FUNC_CTL(cpu_transcoder);
1181                 val = I915_READ(reg);
1182                 cur_state = !!(val & TRANS_DDI_FUNC_ENABLE);
1183         } else {
1184                 reg = FDI_TX_CTL(pipe);
1185                 val = I915_READ(reg);
1186                 cur_state = !!(val & FDI_TX_ENABLE);
1187         }
1188         I915_STATE_WARN(cur_state != state,
1189              "FDI TX state assertion failure (expected %s, current %s)\n",
1190              state_string(state), state_string(cur_state));
1191 }
1192 #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
1193 #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
1194
1195 static void assert_fdi_rx(struct drm_i915_private *dev_priv,
1196                           enum pipe pipe, bool state)
1197 {
1198         int reg;
1199         u32 val;
1200         bool cur_state;
1201
1202         reg = FDI_RX_CTL(pipe);
1203         val = I915_READ(reg);
1204         cur_state = !!(val & FDI_RX_ENABLE);
1205         I915_STATE_WARN(cur_state != state,
1206              "FDI RX state assertion failure (expected %s, current %s)\n",
1207              state_string(state), state_string(cur_state));
1208 }
1209 #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1210 #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1211
1212 static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
1213                                       enum pipe pipe)
1214 {
1215         int reg;
1216         u32 val;
1217
1218         /* ILK FDI PLL is always enabled */
1219         if (INTEL_INFO(dev_priv->dev)->gen == 5)
1220                 return;
1221
1222         /* On Haswell, DDI ports are responsible for the FDI PLL setup */
1223         if (HAS_DDI(dev_priv->dev))
1224                 return;
1225
1226         reg = FDI_TX_CTL(pipe);
1227         val = I915_READ(reg);
1228         I915_STATE_WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
1229 }
1230
1231 void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
1232                        enum pipe pipe, bool state)
1233 {
1234         int reg;
1235         u32 val;
1236         bool cur_state;
1237
1238         reg = FDI_RX_CTL(pipe);
1239         val = I915_READ(reg);
1240         cur_state = !!(val & FDI_RX_PLL_ENABLE);
1241         I915_STATE_WARN(cur_state != state,
1242              "FDI RX PLL assertion failure (expected %s, current %s)\n",
1243              state_string(state), state_string(cur_state));
1244 }
1245
1246 void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1247                            enum pipe pipe)
1248 {
1249         struct drm_device *dev = dev_priv->dev;
1250         int pp_reg;
1251         u32 val;
1252         enum pipe panel_pipe = PIPE_A;
1253         bool locked = true;
1254
1255         if (WARN_ON(HAS_DDI(dev)))
1256                 return;
1257
1258         if (HAS_PCH_SPLIT(dev)) {
1259                 u32 port_sel;
1260
1261                 pp_reg = PCH_PP_CONTROL;
1262                 port_sel = I915_READ(PCH_PP_ON_DELAYS) & PANEL_PORT_SELECT_MASK;
1263
1264                 if (port_sel == PANEL_PORT_SELECT_LVDS &&
1265                     I915_READ(PCH_LVDS) & LVDS_PIPEB_SELECT)
1266                         panel_pipe = PIPE_B;
1267                 /* XXX: else fix for eDP */
1268         } else if (IS_VALLEYVIEW(dev)) {
1269                 /* presumably write lock depends on pipe, not port select */
1270                 pp_reg = VLV_PIPE_PP_CONTROL(pipe);
1271                 panel_pipe = pipe;
1272         } else {
1273                 pp_reg = PP_CONTROL;
1274                 if (I915_READ(LVDS) & LVDS_PIPEB_SELECT)
1275                         panel_pipe = PIPE_B;
1276         }
1277
1278         val = I915_READ(pp_reg);
1279         if (!(val & PANEL_POWER_ON) ||
1280             ((val & PANEL_UNLOCK_MASK) == PANEL_UNLOCK_REGS))
1281                 locked = false;
1282
1283         I915_STATE_WARN(panel_pipe == pipe && locked,
1284              "panel assertion failure, pipe %c regs locked\n",
1285              pipe_name(pipe));
1286 }
1287
1288 static void assert_cursor(struct drm_i915_private *dev_priv,
1289                           enum pipe pipe, bool state)
1290 {
1291         struct drm_device *dev = dev_priv->dev;
1292         bool cur_state;
1293
1294         if (IS_845G(dev) || IS_I865G(dev))
1295                 cur_state = I915_READ(_CURACNTR) & CURSOR_ENABLE;
1296         else
1297                 cur_state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE;
1298
1299         I915_STATE_WARN(cur_state != state,
1300              "cursor on pipe %c assertion failure (expected %s, current %s)\n",
1301              pipe_name(pipe), state_string(state), state_string(cur_state));
1302 }
1303 #define assert_cursor_enabled(d, p) assert_cursor(d, p, true)
1304 #define assert_cursor_disabled(d, p) assert_cursor(d, p, false)
1305
1306 void assert_pipe(struct drm_i915_private *dev_priv,
1307                  enum pipe pipe, bool state)
1308 {
1309         int reg;
1310         u32 val;
1311         bool cur_state;
1312         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1313                                                                       pipe);
1314
1315         /* if we need the pipe quirk it must be always on */
1316         if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
1317             (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
1318                 state = true;
1319
1320         if (!intel_display_power_is_enabled(dev_priv,
1321                                 POWER_DOMAIN_TRANSCODER(cpu_transcoder))) {
1322                 cur_state = false;
1323         } else {
1324                 reg = PIPECONF(cpu_transcoder);
1325                 val = I915_READ(reg);
1326                 cur_state = !!(val & PIPECONF_ENABLE);
1327         }
1328
1329         I915_STATE_WARN(cur_state != state,
1330              "pipe %c assertion failure (expected %s, current %s)\n",
1331              pipe_name(pipe), state_string(state), state_string(cur_state));
1332 }
1333
1334 static void assert_plane(struct drm_i915_private *dev_priv,
1335                          enum plane plane, bool state)
1336 {
1337         int reg;
1338         u32 val;
1339         bool cur_state;
1340
1341         reg = DSPCNTR(plane);
1342         val = I915_READ(reg);
1343         cur_state = !!(val & DISPLAY_PLANE_ENABLE);
1344         I915_STATE_WARN(cur_state != state,
1345              "plane %c assertion failure (expected %s, current %s)\n",
1346              plane_name(plane), state_string(state), state_string(cur_state));
1347 }
1348
1349 #define assert_plane_enabled(d, p) assert_plane(d, p, true)
1350 #define assert_plane_disabled(d, p) assert_plane(d, p, false)
1351
1352 static void assert_planes_disabled(struct drm_i915_private *dev_priv,
1353                                    enum pipe pipe)
1354 {
1355         struct drm_device *dev = dev_priv->dev;
1356         int reg, i;
1357         u32 val;
1358         int cur_pipe;
1359
1360         /* Primary planes are fixed to pipes on gen4+ */
1361         if (INTEL_INFO(dev)->gen >= 4) {
1362                 reg = DSPCNTR(pipe);
1363                 val = I915_READ(reg);
1364                 I915_STATE_WARN(val & DISPLAY_PLANE_ENABLE,
1365                      "plane %c assertion failure, should be disabled but not\n",
1366                      plane_name(pipe));
1367                 return;
1368         }
1369
1370         /* Need to check both planes against the pipe */
1371         for_each_pipe(dev_priv, i) {
1372                 reg = DSPCNTR(i);
1373                 val = I915_READ(reg);
1374                 cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
1375                         DISPPLANE_SEL_PIPE_SHIFT;
1376                 I915_STATE_WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
1377                      "plane %c assertion failure, should be off on pipe %c but is still active\n",
1378                      plane_name(i), pipe_name(pipe));
1379         }
1380 }
1381
1382 static void assert_sprites_disabled(struct drm_i915_private *dev_priv,
1383                                     enum pipe pipe)
1384 {
1385         struct drm_device *dev = dev_priv->dev;
1386         int reg, sprite;
1387         u32 val;
1388
1389         if (INTEL_INFO(dev)->gen >= 9) {
1390                 for_each_sprite(dev_priv, pipe, sprite) {
1391                         val = I915_READ(PLANE_CTL(pipe, sprite));
1392                         I915_STATE_WARN(val & PLANE_CTL_ENABLE,
1393                              "plane %d assertion failure, should be off on pipe %c but is still active\n",
1394                              sprite, pipe_name(pipe));
1395                 }
1396         } else if (IS_VALLEYVIEW(dev)) {
1397                 for_each_sprite(dev_priv, pipe, sprite) {
1398                         reg = SPCNTR(pipe, sprite);
1399                         val = I915_READ(reg);
1400                         I915_STATE_WARN(val & SP_ENABLE,
1401                              "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1402                              sprite_name(pipe, sprite), pipe_name(pipe));
1403                 }
1404         } else if (INTEL_INFO(dev)->gen >= 7) {
1405                 reg = SPRCTL(pipe);
1406                 val = I915_READ(reg);
1407                 I915_STATE_WARN(val & SPRITE_ENABLE,
1408                      "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1409                      plane_name(pipe), pipe_name(pipe));
1410         } else if (INTEL_INFO(dev)->gen >= 5) {
1411                 reg = DVSCNTR(pipe);
1412                 val = I915_READ(reg);
1413                 I915_STATE_WARN(val & DVS_ENABLE,
1414                      "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1415                      plane_name(pipe), pipe_name(pipe));
1416         }
1417 }
1418
1419 static void assert_vblank_disabled(struct drm_crtc *crtc)
1420 {
1421         if (I915_STATE_WARN_ON(drm_crtc_vblank_get(crtc) == 0))
1422                 drm_crtc_vblank_put(crtc);
1423 }
1424
1425 static void ibx_assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
1426 {
1427         u32 val;
1428         bool enabled;
1429
1430         I915_STATE_WARN_ON(!(HAS_PCH_IBX(dev_priv->dev) || HAS_PCH_CPT(dev_priv->dev)));
1431
1432         val = I915_READ(PCH_DREF_CONTROL);
1433         enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
1434                             DREF_SUPERSPREAD_SOURCE_MASK));
1435         I915_STATE_WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
1436 }
1437
1438 static void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv,
1439                                            enum pipe pipe)
1440 {
1441         int reg;
1442         u32 val;
1443         bool enabled;
1444
1445         reg = PCH_TRANSCONF(pipe);
1446         val = I915_READ(reg);
1447         enabled = !!(val & TRANS_ENABLE);
1448         I915_STATE_WARN(enabled,
1449              "transcoder assertion failed, should be off on pipe %c but is still active\n",
1450              pipe_name(pipe));
1451 }
1452
1453 static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1454                             enum pipe pipe, u32 port_sel, u32 val)
1455 {
1456         if ((val & DP_PORT_EN) == 0)
1457                 return false;
1458
1459         if (HAS_PCH_CPT(dev_priv->dev)) {
1460                 u32     trans_dp_ctl_reg = TRANS_DP_CTL(pipe);
1461                 u32     trans_dp_ctl = I915_READ(trans_dp_ctl_reg);
1462                 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1463                         return false;
1464         } else if (IS_CHERRYVIEW(dev_priv->dev)) {
1465                 if ((val & DP_PIPE_MASK_CHV) != DP_PIPE_SELECT_CHV(pipe))
1466                         return false;
1467         } else {
1468                 if ((val & DP_PIPE_MASK) != (pipe << 30))
1469                         return false;
1470         }
1471         return true;
1472 }
1473
1474 static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1475                               enum pipe pipe, u32 val)
1476 {
1477         if ((val & SDVO_ENABLE) == 0)
1478                 return false;
1479
1480         if (HAS_PCH_CPT(dev_priv->dev)) {
1481                 if ((val & SDVO_PIPE_SEL_MASK_CPT) != SDVO_PIPE_SEL_CPT(pipe))
1482                         return false;
1483         } else if (IS_CHERRYVIEW(dev_priv->dev)) {
1484                 if ((val & SDVO_PIPE_SEL_MASK_CHV) != SDVO_PIPE_SEL_CHV(pipe))
1485                         return false;
1486         } else {
1487                 if ((val & SDVO_PIPE_SEL_MASK) != SDVO_PIPE_SEL(pipe))
1488                         return false;
1489         }
1490         return true;
1491 }
1492
1493 static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1494                               enum pipe pipe, u32 val)
1495 {
1496         if ((val & LVDS_PORT_EN) == 0)
1497                 return false;
1498
1499         if (HAS_PCH_CPT(dev_priv->dev)) {
1500                 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1501                         return false;
1502         } else {
1503                 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1504                         return false;
1505         }
1506         return true;
1507 }
1508
1509 static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1510                               enum pipe pipe, u32 val)
1511 {
1512         if ((val & ADPA_DAC_ENABLE) == 0)
1513                 return false;
1514         if (HAS_PCH_CPT(dev_priv->dev)) {
1515                 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1516                         return false;
1517         } else {
1518                 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1519                         return false;
1520         }
1521         return true;
1522 }
1523
1524 static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
1525                                    enum pipe pipe, int reg, u32 port_sel)
1526 {
1527         u32 val = I915_READ(reg);
1528         I915_STATE_WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
1529              "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
1530              reg, pipe_name(pipe));
1531
1532         I915_STATE_WARN(HAS_PCH_IBX(dev_priv->dev) && (val & DP_PORT_EN) == 0
1533              && (val & DP_PIPEB_SELECT),
1534              "IBX PCH dp port still using transcoder B\n");
1535 }
1536
1537 static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1538                                      enum pipe pipe, int reg)
1539 {
1540         u32 val = I915_READ(reg);
1541         I915_STATE_WARN(hdmi_pipe_enabled(dev_priv, pipe, val),
1542              "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
1543              reg, pipe_name(pipe));
1544
1545         I915_STATE_WARN(HAS_PCH_IBX(dev_priv->dev) && (val & SDVO_ENABLE) == 0
1546              && (val & SDVO_PIPE_B_SELECT),
1547              "IBX PCH hdmi port still using transcoder B\n");
1548 }
1549
1550 static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1551                                       enum pipe pipe)
1552 {
1553         int reg;
1554         u32 val;
1555
1556         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1557         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1558         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
1559
1560         reg = PCH_ADPA;
1561         val = I915_READ(reg);
1562         I915_STATE_WARN(adpa_pipe_enabled(dev_priv, pipe, val),
1563              "PCH VGA enabled on transcoder %c, should be disabled\n",
1564              pipe_name(pipe));
1565
1566         reg = PCH_LVDS;
1567         val = I915_READ(reg);
1568         I915_STATE_WARN(lvds_pipe_enabled(dev_priv, pipe, val),
1569              "PCH LVDS enabled on transcoder %c, should be disabled\n",
1570              pipe_name(pipe));
1571
1572         assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIB);
1573         assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIC);
1574         assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID);
1575 }
1576
1577 static void intel_init_dpio(struct drm_device *dev)
1578 {
1579         struct drm_i915_private *dev_priv = dev->dev_private;
1580
1581         if (!IS_VALLEYVIEW(dev))
1582                 return;
1583
1584         /*
1585          * IOSF_PORT_DPIO is used for VLV x2 PHY (DP/HDMI B and C),
1586          * CHV x1 PHY (DP/HDMI D)
1587          * IOSF_PORT_DPIO_2 is used for CHV x2 PHY (DP/HDMI B and C)
1588          */
1589         if (IS_CHERRYVIEW(dev)) {
1590                 DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO_2;
1591                 DPIO_PHY_IOSF_PORT(DPIO_PHY1) = IOSF_PORT_DPIO;
1592         } else {
1593                 DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO;
1594         }
1595 }
1596
1597 static void vlv_enable_pll(struct intel_crtc *crtc,
1598                            const struct intel_crtc_state *pipe_config)
1599 {
1600         struct drm_device *dev = crtc->base.dev;
1601         struct drm_i915_private *dev_priv = dev->dev_private;
1602         int reg = DPLL(crtc->pipe);
1603         u32 dpll = pipe_config->dpll_hw_state.dpll;
1604
1605         assert_pipe_disabled(dev_priv, crtc->pipe);
1606
1607         /* No really, not for ILK+ */
1608         BUG_ON(!IS_VALLEYVIEW(dev_priv->dev));
1609
1610         /* PLL is protected by panel, make sure we can write it */
1611         if (IS_MOBILE(dev_priv->dev))
1612                 assert_panel_unlocked(dev_priv, crtc->pipe);
1613
1614         I915_WRITE(reg, dpll);
1615         POSTING_READ(reg);
1616         udelay(150);
1617
1618         if (wait_for(((I915_READ(reg) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
1619                 DRM_ERROR("DPLL %d failed to lock\n", crtc->pipe);
1620
1621         I915_WRITE(DPLL_MD(crtc->pipe), pipe_config->dpll_hw_state.dpll_md);
1622         POSTING_READ(DPLL_MD(crtc->pipe));
1623
1624         /* We do this three times for luck */
1625         I915_WRITE(reg, dpll);
1626         POSTING_READ(reg);
1627         udelay(150); /* wait for warmup */
1628         I915_WRITE(reg, dpll);
1629         POSTING_READ(reg);
1630         udelay(150); /* wait for warmup */
1631         I915_WRITE(reg, dpll);
1632         POSTING_READ(reg);
1633         udelay(150); /* wait for warmup */
1634 }
1635
1636 static void chv_enable_pll(struct intel_crtc *crtc,
1637                            const struct intel_crtc_state *pipe_config)
1638 {
1639         struct drm_device *dev = crtc->base.dev;
1640         struct drm_i915_private *dev_priv = dev->dev_private;
1641         int pipe = crtc->pipe;
1642         enum dpio_channel port = vlv_pipe_to_channel(pipe);
1643         u32 tmp;
1644
1645         assert_pipe_disabled(dev_priv, crtc->pipe);
1646
1647         BUG_ON(!IS_CHERRYVIEW(dev_priv->dev));
1648
1649         mutex_lock(&dev_priv->sb_lock);
1650
1651         /* Enable back the 10bit clock to display controller */
1652         tmp = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1653         tmp |= DPIO_DCLKP_EN;
1654         vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), tmp);
1655
1656         mutex_unlock(&dev_priv->sb_lock);
1657
1658         /*
1659          * Need to wait > 100ns between dclkp clock enable bit and PLL enable.
1660          */
1661         udelay(1);
1662
1663         /* Enable PLL */
1664         I915_WRITE(DPLL(pipe), pipe_config->dpll_hw_state.dpll);
1665
1666         /* Check PLL is locked */
1667         if (wait_for(((I915_READ(DPLL(pipe)) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
1668                 DRM_ERROR("PLL %d failed to lock\n", pipe);
1669
1670         /* not sure when this should be written */
1671         I915_WRITE(DPLL_MD(pipe), pipe_config->dpll_hw_state.dpll_md);
1672         POSTING_READ(DPLL_MD(pipe));
1673 }
1674
1675 static int intel_num_dvo_pipes(struct drm_device *dev)
1676 {
1677         struct intel_crtc *crtc;
1678         int count = 0;
1679
1680         for_each_intel_crtc(dev, crtc)
1681                 count += crtc->base.state->active &&
1682                         intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO);
1683
1684         return count;
1685 }
1686
1687 static void i9xx_enable_pll(struct intel_crtc *crtc)
1688 {
1689         struct drm_device *dev = crtc->base.dev;
1690         struct drm_i915_private *dev_priv = dev->dev_private;
1691         int reg = DPLL(crtc->pipe);
1692         u32 dpll = crtc->config->dpll_hw_state.dpll;
1693
1694         assert_pipe_disabled(dev_priv, crtc->pipe);
1695
1696         /* No really, not for ILK+ */
1697         BUG_ON(INTEL_INFO(dev)->gen >= 5);
1698
1699         /* PLL is protected by panel, make sure we can write it */
1700         if (IS_MOBILE(dev) && !IS_I830(dev))
1701                 assert_panel_unlocked(dev_priv, crtc->pipe);
1702
1703         /* Enable DVO 2x clock on both PLLs if necessary */
1704         if (IS_I830(dev) && intel_num_dvo_pipes(dev) > 0) {
1705                 /*
1706                  * It appears to be important that we don't enable this
1707                  * for the current pipe before otherwise configuring the
1708                  * PLL. No idea how this should be handled if multiple
1709                  * DVO outputs are enabled simultaneosly.
1710                  */
1711                 dpll |= DPLL_DVO_2X_MODE;
1712                 I915_WRITE(DPLL(!crtc->pipe),
1713                            I915_READ(DPLL(!crtc->pipe)) | DPLL_DVO_2X_MODE);
1714         }
1715
1716         /* Wait for the clocks to stabilize. */
1717         POSTING_READ(reg);
1718         udelay(150);
1719
1720         if (INTEL_INFO(dev)->gen >= 4) {
1721                 I915_WRITE(DPLL_MD(crtc->pipe),
1722                            crtc->config->dpll_hw_state.dpll_md);
1723         } else {
1724                 /* The pixel multiplier can only be updated once the
1725                  * DPLL is enabled and the clocks are stable.
1726                  *
1727                  * So write it again.
1728                  */
1729                 I915_WRITE(reg, dpll);
1730         }
1731
1732         /* We do this three times for luck */
1733         I915_WRITE(reg, dpll);
1734         POSTING_READ(reg);
1735         udelay(150); /* wait for warmup */
1736         I915_WRITE(reg, dpll);
1737         POSTING_READ(reg);
1738         udelay(150); /* wait for warmup */
1739         I915_WRITE(reg, dpll);
1740         POSTING_READ(reg);
1741         udelay(150); /* wait for warmup */
1742 }
1743
1744 /**
1745  * i9xx_disable_pll - disable a PLL
1746  * @dev_priv: i915 private structure
1747  * @pipe: pipe PLL to disable
1748  *
1749  * Disable the PLL for @pipe, making sure the pipe is off first.
1750  *
1751  * Note!  This is for pre-ILK only.
1752  */
1753 static void i9xx_disable_pll(struct intel_crtc *crtc)
1754 {
1755         struct drm_device *dev = crtc->base.dev;
1756         struct drm_i915_private *dev_priv = dev->dev_private;
1757         enum pipe pipe = crtc->pipe;
1758
1759         /* Disable DVO 2x clock on both PLLs if necessary */
1760         if (IS_I830(dev) &&
1761             intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO) &&
1762             !intel_num_dvo_pipes(dev)) {
1763                 I915_WRITE(DPLL(PIPE_B),
1764                            I915_READ(DPLL(PIPE_B)) & ~DPLL_DVO_2X_MODE);
1765                 I915_WRITE(DPLL(PIPE_A),
1766                            I915_READ(DPLL(PIPE_A)) & ~DPLL_DVO_2X_MODE);
1767         }
1768
1769         /* Don't disable pipe or pipe PLLs if needed */
1770         if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
1771             (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
1772                 return;
1773
1774         /* Make sure the pipe isn't still relying on us */
1775         assert_pipe_disabled(dev_priv, pipe);
1776
1777         I915_WRITE(DPLL(pipe), 0);
1778         POSTING_READ(DPLL(pipe));
1779 }
1780
1781 static void vlv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1782 {
1783         u32 val = 0;
1784
1785         /* Make sure the pipe isn't still relying on us */
1786         assert_pipe_disabled(dev_priv, pipe);
1787
1788         /*
1789          * Leave integrated clock source and reference clock enabled for pipe B.
1790          * The latter is needed for VGA hotplug / manual detection.
1791          */
1792         if (pipe == PIPE_B)
1793                 val = DPLL_INTEGRATED_CRI_CLK_VLV | DPLL_REFA_CLK_ENABLE_VLV;
1794         I915_WRITE(DPLL(pipe), val);
1795         POSTING_READ(DPLL(pipe));
1796
1797 }
1798
1799 static void chv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1800 {
1801         enum dpio_channel port = vlv_pipe_to_channel(pipe);
1802         u32 val;
1803
1804         /* Make sure the pipe isn't still relying on us */
1805         assert_pipe_disabled(dev_priv, pipe);
1806
1807         /* Set PLL en = 0 */
1808         val = DPLL_SSC_REF_CLOCK_CHV | DPLL_REFA_CLK_ENABLE_VLV;
1809         if (pipe != PIPE_A)
1810                 val |= DPLL_INTEGRATED_CRI_CLK_VLV;
1811         I915_WRITE(DPLL(pipe), val);
1812         POSTING_READ(DPLL(pipe));
1813
1814         mutex_lock(&dev_priv->sb_lock);
1815
1816         /* Disable 10bit clock to display controller */
1817         val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1818         val &= ~DPIO_DCLKP_EN;
1819         vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), val);
1820
1821         /* disable left/right clock distribution */
1822         if (pipe != PIPE_B) {
1823                 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW5_CH0);
1824                 val &= ~(CHV_BUFLEFTENA1_MASK | CHV_BUFRIGHTENA1_MASK);
1825                 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW5_CH0, val);
1826         } else {
1827                 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW1_CH1);
1828                 val &= ~(CHV_BUFLEFTENA2_MASK | CHV_BUFRIGHTENA2_MASK);
1829                 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW1_CH1, val);
1830         }
1831
1832         mutex_unlock(&dev_priv->sb_lock);
1833 }
1834
1835 void vlv_wait_port_ready(struct drm_i915_private *dev_priv,
1836                          struct intel_digital_port *dport,
1837                          unsigned int expected_mask)
1838 {
1839         u32 port_mask;
1840         int dpll_reg;
1841
1842         switch (dport->port) {
1843         case PORT_B:
1844                 port_mask = DPLL_PORTB_READY_MASK;
1845                 dpll_reg = DPLL(0);
1846                 break;
1847         case PORT_C:
1848                 port_mask = DPLL_PORTC_READY_MASK;
1849                 dpll_reg = DPLL(0);
1850                 expected_mask <<= 4;
1851                 break;
1852         case PORT_D:
1853                 port_mask = DPLL_PORTD_READY_MASK;
1854                 dpll_reg = DPIO_PHY_STATUS;
1855                 break;
1856         default:
1857                 BUG();
1858         }
1859
1860         if (wait_for((I915_READ(dpll_reg) & port_mask) == expected_mask, 1000))
1861                 WARN(1, "timed out waiting for port %c ready: got 0x%x, expected 0x%x\n",
1862                      port_name(dport->port), I915_READ(dpll_reg) & port_mask, expected_mask);
1863 }
1864
1865 static void intel_prepare_shared_dpll(struct intel_crtc *crtc)
1866 {
1867         struct drm_device *dev = crtc->base.dev;
1868         struct drm_i915_private *dev_priv = dev->dev_private;
1869         struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1870
1871         if (WARN_ON(pll == NULL))
1872                 return;
1873
1874         WARN_ON(!pll->config.crtc_mask);
1875         if (pll->active == 0) {
1876                 DRM_DEBUG_DRIVER("setting up %s\n", pll->name);
1877                 WARN_ON(pll->on);
1878                 assert_shared_dpll_disabled(dev_priv, pll);
1879
1880                 pll->mode_set(dev_priv, pll);
1881         }
1882 }
1883
1884 /**
1885  * intel_enable_shared_dpll - enable PCH PLL
1886  * @dev_priv: i915 private structure
1887  * @pipe: pipe PLL to enable
1888  *
1889  * The PCH PLL needs to be enabled before the PCH transcoder, since it
1890  * drives the transcoder clock.
1891  */
1892 static void intel_enable_shared_dpll(struct intel_crtc *crtc)
1893 {
1894         struct drm_device *dev = crtc->base.dev;
1895         struct drm_i915_private *dev_priv = dev->dev_private;
1896         struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1897
1898         if (WARN_ON(pll == NULL))
1899                 return;
1900
1901         if (WARN_ON(pll->config.crtc_mask == 0))
1902                 return;
1903
1904         DRM_DEBUG_KMS("enable %s (active %d, on? %d) for crtc %d\n",
1905                       pll->name, pll->active, pll->on,
1906                       crtc->base.base.id);
1907
1908         if (pll->active++) {
1909                 WARN_ON(!pll->on);
1910                 assert_shared_dpll_enabled(dev_priv, pll);
1911                 return;
1912         }
1913         WARN_ON(pll->on);
1914
1915         intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
1916
1917         DRM_DEBUG_KMS("enabling %s\n", pll->name);
1918         pll->enable(dev_priv, pll);
1919         pll->on = true;
1920 }
1921
1922 static void intel_disable_shared_dpll(struct intel_crtc *crtc)
1923 {
1924         struct drm_device *dev = crtc->base.dev;
1925         struct drm_i915_private *dev_priv = dev->dev_private;
1926         struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1927
1928         /* PCH only available on ILK+ */
1929         BUG_ON(INTEL_INFO(dev)->gen < 5);
1930         if (pll == NULL)
1931                 return;
1932
1933         if (WARN_ON(!(pll->config.crtc_mask & (1 << drm_crtc_index(&crtc->base)))))
1934                 return;
1935
1936         DRM_DEBUG_KMS("disable %s (active %d, on? %d) for crtc %d\n",
1937                       pll->name, pll->active, pll->on,
1938                       crtc->base.base.id);
1939
1940         if (WARN_ON(pll->active == 0)) {
1941                 assert_shared_dpll_disabled(dev_priv, pll);
1942                 return;
1943         }
1944
1945         assert_shared_dpll_enabled(dev_priv, pll);
1946         WARN_ON(!pll->on);
1947         if (--pll->active)
1948                 return;
1949
1950         DRM_DEBUG_KMS("disabling %s\n", pll->name);
1951         pll->disable(dev_priv, pll);
1952         pll->on = false;
1953
1954         intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS);
1955 }
1956
1957 static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1958                                            enum pipe pipe)
1959 {
1960         struct drm_device *dev = dev_priv->dev;
1961         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1962         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1963         uint32_t reg, val, pipeconf_val;
1964
1965         /* PCH only available on ILK+ */
1966         BUG_ON(!HAS_PCH_SPLIT(dev));
1967
1968         /* Make sure PCH DPLL is enabled */
1969         assert_shared_dpll_enabled(dev_priv,
1970                                    intel_crtc_to_shared_dpll(intel_crtc));
1971
1972         /* FDI must be feeding us bits for PCH ports */
1973         assert_fdi_tx_enabled(dev_priv, pipe);
1974         assert_fdi_rx_enabled(dev_priv, pipe);
1975
1976         if (HAS_PCH_CPT(dev)) {
1977                 /* Workaround: Set the timing override bit before enabling the
1978                  * pch transcoder. */
1979                 reg = TRANS_CHICKEN2(pipe);
1980                 val = I915_READ(reg);
1981                 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1982                 I915_WRITE(reg, val);
1983         }
1984
1985         reg = PCH_TRANSCONF(pipe);
1986         val = I915_READ(reg);
1987         pipeconf_val = I915_READ(PIPECONF(pipe));
1988
1989         if (HAS_PCH_IBX(dev_priv->dev)) {
1990                 /*
1991                  * Make the BPC in transcoder be consistent with
1992                  * that in pipeconf reg. For HDMI we must use 8bpc
1993                  * here for both 8bpc and 12bpc.
1994                  */
1995                 val &= ~PIPECONF_BPC_MASK;
1996                 if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_HDMI))
1997                         val |= PIPECONF_8BPC;
1998                 else
1999                         val |= pipeconf_val & PIPECONF_BPC_MASK;
2000         }
2001
2002         val &= ~TRANS_INTERLACE_MASK;
2003         if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
2004                 if (HAS_PCH_IBX(dev_priv->dev) &&
2005                     intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
2006                         val |= TRANS_LEGACY_INTERLACED_ILK;
2007                 else
2008                         val |= TRANS_INTERLACED;
2009         else
2010                 val |= TRANS_PROGRESSIVE;
2011
2012         I915_WRITE(reg, val | TRANS_ENABLE);
2013         if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
2014                 DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe));
2015 }
2016
2017 static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
2018                                       enum transcoder cpu_transcoder)
2019 {
2020         u32 val, pipeconf_val;
2021
2022         /* PCH only available on ILK+ */
2023         BUG_ON(!HAS_PCH_SPLIT(dev_priv->dev));
2024
2025         /* FDI must be feeding us bits for PCH ports */
2026         assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder);
2027         assert_fdi_rx_enabled(dev_priv, TRANSCODER_A);
2028
2029         /* Workaround: set timing override bit. */
2030         val = I915_READ(_TRANSA_CHICKEN2);
2031         val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
2032         I915_WRITE(_TRANSA_CHICKEN2, val);
2033
2034         val = TRANS_ENABLE;
2035         pipeconf_val = I915_READ(PIPECONF(cpu_transcoder));
2036
2037         if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) ==
2038             PIPECONF_INTERLACED_ILK)
2039                 val |= TRANS_INTERLACED;
2040         else
2041                 val |= TRANS_PROGRESSIVE;
2042
2043         I915_WRITE(LPT_TRANSCONF, val);
2044         if (wait_for(I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE, 100))
2045                 DRM_ERROR("Failed to enable PCH transcoder\n");
2046 }
2047
2048 static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv,
2049                                             enum pipe pipe)
2050 {
2051         struct drm_device *dev = dev_priv->dev;
2052         uint32_t reg, val;
2053
2054         /* FDI relies on the transcoder */
2055         assert_fdi_tx_disabled(dev_priv, pipe);
2056         assert_fdi_rx_disabled(dev_priv, pipe);
2057
2058         /* Ports must be off as well */
2059         assert_pch_ports_disabled(dev_priv, pipe);
2060
2061         reg = PCH_TRANSCONF(pipe);
2062         val = I915_READ(reg);
2063         val &= ~TRANS_ENABLE;
2064         I915_WRITE(reg, val);
2065         /* wait for PCH transcoder off, transcoder state */
2066         if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
2067                 DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe));
2068
2069         if (!HAS_PCH_IBX(dev)) {
2070                 /* Workaround: Clear the timing override chicken bit again. */
2071                 reg = TRANS_CHICKEN2(pipe);
2072                 val = I915_READ(reg);
2073                 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
2074                 I915_WRITE(reg, val);
2075         }
2076 }
2077
2078 static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv)
2079 {
2080         u32 val;
2081
2082         val = I915_READ(LPT_TRANSCONF);
2083         val &= ~TRANS_ENABLE;
2084         I915_WRITE(LPT_TRANSCONF, val);
2085         /* wait for PCH transcoder off, transcoder state */
2086         if (wait_for((I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE) == 0, 50))
2087                 DRM_ERROR("Failed to disable PCH transcoder\n");
2088
2089         /* Workaround: clear timing override bit. */
2090         val = I915_READ(_TRANSA_CHICKEN2);
2091         val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
2092         I915_WRITE(_TRANSA_CHICKEN2, val);
2093 }
2094
2095 /**
2096  * intel_enable_pipe - enable a pipe, asserting requirements
2097  * @crtc: crtc responsible for the pipe
2098  *
2099  * Enable @crtc's pipe, making sure that various hardware specific requirements
2100  * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
2101  */
2102 static void intel_enable_pipe(struct intel_crtc *crtc)
2103 {
2104         struct drm_device *dev = crtc->base.dev;
2105         struct drm_i915_private *dev_priv = dev->dev_private;
2106         enum pipe pipe = crtc->pipe;
2107         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
2108                                                                       pipe);
2109         enum pipe pch_transcoder;
2110         int reg;
2111         u32 val;
2112
2113         assert_planes_disabled(dev_priv, pipe);
2114         assert_cursor_disabled(dev_priv, pipe);
2115         assert_sprites_disabled(dev_priv, pipe);
2116
2117         if (HAS_PCH_LPT(dev_priv->dev))
2118                 pch_transcoder = TRANSCODER_A;
2119         else
2120                 pch_transcoder = pipe;
2121
2122         /*
2123          * A pipe without a PLL won't actually be able to drive bits from
2124          * a plane.  On ILK+ the pipe PLLs are integrated, so we don't
2125          * need the check.
2126          */
2127         if (HAS_GMCH_DISPLAY(dev_priv->dev))
2128                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI))
2129                         assert_dsi_pll_enabled(dev_priv);
2130                 else
2131                         assert_pll_enabled(dev_priv, pipe);
2132         else {
2133                 if (crtc->config->has_pch_encoder) {
2134                         /* if driving the PCH, we need FDI enabled */
2135                         assert_fdi_rx_pll_enabled(dev_priv, pch_transcoder);
2136                         assert_fdi_tx_pll_enabled(dev_priv,
2137                                                   (enum pipe) cpu_transcoder);
2138                 }
2139                 /* FIXME: assert CPU port conditions for SNB+ */
2140         }
2141
2142         reg = PIPECONF(cpu_transcoder);
2143         val = I915_READ(reg);
2144         if (val & PIPECONF_ENABLE) {
2145                 WARN_ON(!((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
2146                           (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE)));
2147                 return;
2148         }
2149
2150         I915_WRITE(reg, val | PIPECONF_ENABLE);
2151         POSTING_READ(reg);
2152 }
2153
2154 /**
2155  * intel_disable_pipe - disable a pipe, asserting requirements
2156  * @crtc: crtc whose pipes is to be disabled
2157  *
2158  * Disable the pipe of @crtc, making sure that various hardware
2159  * specific requirements are met, if applicable, e.g. plane
2160  * disabled, panel fitter off, etc.
2161  *
2162  * Will wait until the pipe has shut down before returning.
2163  */
2164 static void intel_disable_pipe(struct intel_crtc *crtc)
2165 {
2166         struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
2167         enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
2168         enum pipe pipe = crtc->pipe;
2169         int reg;
2170         u32 val;
2171
2172         /*
2173          * Make sure planes won't keep trying to pump pixels to us,
2174          * or we might hang the display.
2175          */
2176         assert_planes_disabled(dev_priv, pipe);
2177         assert_cursor_disabled(dev_priv, pipe);
2178         assert_sprites_disabled(dev_priv, pipe);
2179
2180         reg = PIPECONF(cpu_transcoder);
2181         val = I915_READ(reg);
2182         if ((val & PIPECONF_ENABLE) == 0)
2183                 return;
2184
2185         /*
2186          * Double wide has implications for planes
2187          * so best keep it disabled when not needed.
2188          */
2189         if (crtc->config->double_wide)
2190                 val &= ~PIPECONF_DOUBLE_WIDE;
2191
2192         /* Don't disable pipe or pipe PLLs if needed */
2193         if (!(pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) &&
2194             !(pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
2195                 val &= ~PIPECONF_ENABLE;
2196
2197         I915_WRITE(reg, val);
2198         if ((val & PIPECONF_ENABLE) == 0)
2199                 intel_wait_for_pipe_off(crtc);
2200 }
2201
2202 static bool need_vtd_wa(struct drm_device *dev)
2203 {
2204 #ifdef CONFIG_INTEL_IOMMU
2205         if (INTEL_INFO(dev)->gen >= 6 && intel_iommu_gfx_mapped)
2206                 return true;
2207 #endif
2208         return false;
2209 }
2210
2211 unsigned int
2212 intel_tile_height(struct drm_device *dev, uint32_t pixel_format,
2213                   uint64_t fb_format_modifier)
2214 {
2215         unsigned int tile_height;
2216         uint32_t pixel_bytes;
2217
2218         switch (fb_format_modifier) {
2219         case DRM_FORMAT_MOD_NONE:
2220                 tile_height = 1;
2221                 break;
2222         case I915_FORMAT_MOD_X_TILED:
2223                 tile_height = IS_GEN2(dev) ? 16 : 8;
2224                 break;
2225         case I915_FORMAT_MOD_Y_TILED:
2226                 tile_height = 32;
2227                 break;
2228         case I915_FORMAT_MOD_Yf_TILED:
2229                 pixel_bytes = drm_format_plane_cpp(pixel_format, 0);
2230                 switch (pixel_bytes) {
2231                 default:
2232                 case 1:
2233                         tile_height = 64;
2234                         break;
2235                 case 2:
2236                 case 4:
2237                         tile_height = 32;
2238                         break;
2239                 case 8:
2240                         tile_height = 16;
2241                         break;
2242                 case 16:
2243                         WARN_ONCE(1,
2244                                   "128-bit pixels are not supported for display!");
2245                         tile_height = 16;
2246                         break;
2247                 }
2248                 break;
2249         default:
2250                 MISSING_CASE(fb_format_modifier);
2251                 tile_height = 1;
2252                 break;
2253         }
2254
2255         return tile_height;
2256 }
2257
2258 unsigned int
2259 intel_fb_align_height(struct drm_device *dev, unsigned int height,
2260                       uint32_t pixel_format, uint64_t fb_format_modifier)
2261 {
2262         return ALIGN(height, intel_tile_height(dev, pixel_format,
2263                                                fb_format_modifier));
2264 }
2265
2266 static int
2267 intel_fill_fb_ggtt_view(struct i915_ggtt_view *view, struct drm_framebuffer *fb,
2268                         const struct drm_plane_state *plane_state)
2269 {
2270         struct intel_rotation_info *info = &view->rotation_info;
2271
2272         *view = i915_ggtt_view_normal;
2273
2274         if (!plane_state)
2275                 return 0;
2276
2277         if (!intel_rotation_90_or_270(plane_state->rotation))
2278                 return 0;
2279
2280         *view = i915_ggtt_view_rotated;
2281
2282         info->height = fb->height;
2283         info->pixel_format = fb->pixel_format;
2284         info->pitch = fb->pitches[0];
2285         info->fb_modifier = fb->modifier[0];
2286
2287         return 0;
2288 }
2289
2290 static unsigned int intel_linear_alignment(struct drm_i915_private *dev_priv)
2291 {
2292         if (INTEL_INFO(dev_priv)->gen >= 9)
2293                 return 256 * 1024;
2294         else if (IS_BROADWATER(dev_priv) || IS_CRESTLINE(dev_priv) ||
2295                  IS_VALLEYVIEW(dev_priv))
2296                 return 128 * 1024;
2297         else if (INTEL_INFO(dev_priv)->gen >= 4)
2298                 return 4 * 1024;
2299         else
2300                 return 0;
2301 }
2302
2303 int
2304 intel_pin_and_fence_fb_obj(struct drm_plane *plane,
2305                            struct drm_framebuffer *fb,
2306                            const struct drm_plane_state *plane_state,
2307                            struct intel_engine_cs *pipelined)
2308 {
2309         struct drm_device *dev = fb->dev;
2310         struct drm_i915_private *dev_priv = dev->dev_private;
2311         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
2312         struct i915_ggtt_view view;
2313         u32 alignment;
2314         int ret;
2315
2316         WARN_ON(!mutex_is_locked(&dev->struct_mutex));
2317
2318         switch (fb->modifier[0]) {
2319         case DRM_FORMAT_MOD_NONE:
2320                 alignment = intel_linear_alignment(dev_priv);
2321                 break;
2322         case I915_FORMAT_MOD_X_TILED:
2323                 if (INTEL_INFO(dev)->gen >= 9)
2324                         alignment = 256 * 1024;
2325                 else {
2326                         /* pin() will align the object as required by fence */
2327                         alignment = 0;
2328                 }
2329                 break;
2330         case I915_FORMAT_MOD_Y_TILED:
2331         case I915_FORMAT_MOD_Yf_TILED:
2332                 if (WARN_ONCE(INTEL_INFO(dev)->gen < 9,
2333                           "Y tiling bo slipped through, driver bug!\n"))
2334                         return -EINVAL;
2335                 alignment = 1 * 1024 * 1024;
2336                 break;
2337         default:
2338                 MISSING_CASE(fb->modifier[0]);
2339                 return -EINVAL;
2340         }
2341
2342         ret = intel_fill_fb_ggtt_view(&view, fb, plane_state);
2343         if (ret)
2344                 return ret;
2345
2346         /* Note that the w/a also requires 64 PTE of padding following the
2347          * bo. We currently fill all unused PTE with the shadow page and so
2348          * we should always have valid PTE following the scanout preventing
2349          * the VT-d warning.
2350          */
2351         if (need_vtd_wa(dev) && alignment < 256 * 1024)
2352                 alignment = 256 * 1024;
2353
2354         /*
2355          * Global gtt pte registers are special registers which actually forward
2356          * writes to a chunk of system memory. Which means that there is no risk
2357          * that the register values disappear as soon as we call
2358          * intel_runtime_pm_put(), so it is correct to wrap only the
2359          * pin/unpin/fence and not more.
2360          */
2361         intel_runtime_pm_get(dev_priv);
2362
2363         dev_priv->mm.interruptible = false;
2364         ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined,
2365                                                    &view);
2366         if (ret)
2367                 goto err_interruptible;
2368
2369         /* Install a fence for tiled scan-out. Pre-i965 always needs a
2370          * fence, whereas 965+ only requires a fence if using
2371          * framebuffer compression.  For simplicity, we always install
2372          * a fence as the cost is not that onerous.
2373          */
2374         ret = i915_gem_object_get_fence(obj);
2375         if (ret)
2376                 goto err_unpin;
2377
2378         i915_gem_object_pin_fence(obj);
2379
2380         dev_priv->mm.interruptible = true;
2381         intel_runtime_pm_put(dev_priv);
2382         return 0;
2383
2384 err_unpin:
2385         i915_gem_object_unpin_from_display_plane(obj, &view);
2386 err_interruptible:
2387         dev_priv->mm.interruptible = true;
2388         intel_runtime_pm_put(dev_priv);
2389         return ret;
2390 }
2391
2392 static void intel_unpin_fb_obj(struct drm_framebuffer *fb,
2393                                const struct drm_plane_state *plane_state)
2394 {
2395         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
2396         struct i915_ggtt_view view;
2397         int ret;
2398
2399         WARN_ON(!mutex_is_locked(&obj->base.dev->struct_mutex));
2400
2401         ret = intel_fill_fb_ggtt_view(&view, fb, plane_state);
2402         WARN_ONCE(ret, "Couldn't get view from plane state!");
2403
2404         i915_gem_object_unpin_fence(obj);
2405         i915_gem_object_unpin_from_display_plane(obj, &view);
2406 }
2407
2408 /* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel
2409  * is assumed to be a power-of-two. */
2410 unsigned long intel_gen4_compute_page_offset(struct drm_i915_private *dev_priv,
2411                                              int *x, int *y,
2412                                              unsigned int tiling_mode,
2413                                              unsigned int cpp,
2414                                              unsigned int pitch)
2415 {
2416         if (tiling_mode != I915_TILING_NONE) {
2417                 unsigned int tile_rows, tiles;
2418
2419                 tile_rows = *y / 8;
2420                 *y %= 8;
2421
2422                 tiles = *x / (512/cpp);
2423                 *x %= 512/cpp;
2424
2425                 return tile_rows * pitch * 8 + tiles * 4096;
2426         } else {
2427                 unsigned int alignment = intel_linear_alignment(dev_priv) - 1;
2428                 unsigned int offset;
2429
2430                 offset = *y * pitch + *x * cpp;
2431                 *y = (offset & alignment) / pitch;
2432                 *x = ((offset & alignment) - *y * pitch) / cpp;
2433                 return offset & ~alignment;
2434         }
2435 }
2436
2437 static int i9xx_format_to_fourcc(int format)
2438 {
2439         switch (format) {
2440         case DISPPLANE_8BPP:
2441                 return DRM_FORMAT_C8;
2442         case DISPPLANE_BGRX555:
2443                 return DRM_FORMAT_XRGB1555;
2444         case DISPPLANE_BGRX565:
2445                 return DRM_FORMAT_RGB565;
2446         default:
2447         case DISPPLANE_BGRX888:
2448                 return DRM_FORMAT_XRGB8888;
2449         case DISPPLANE_RGBX888:
2450                 return DRM_FORMAT_XBGR8888;
2451         case DISPPLANE_BGRX101010:
2452                 return DRM_FORMAT_XRGB2101010;
2453         case DISPPLANE_RGBX101010:
2454                 return DRM_FORMAT_XBGR2101010;
2455         }
2456 }
2457
2458 static int skl_format_to_fourcc(int format, bool rgb_order, bool alpha)
2459 {
2460         switch (format) {
2461         case PLANE_CTL_FORMAT_RGB_565:
2462                 return DRM_FORMAT_RGB565;
2463         default:
2464         case PLANE_CTL_FORMAT_XRGB_8888:
2465                 if (rgb_order) {
2466                         if (alpha)
2467                                 return DRM_FORMAT_ABGR8888;
2468                         else
2469                                 return DRM_FORMAT_XBGR8888;
2470                 } else {
2471                         if (alpha)
2472                                 return DRM_FORMAT_ARGB8888;
2473                         else
2474                                 return DRM_FORMAT_XRGB8888;
2475                 }
2476         case PLANE_CTL_FORMAT_XRGB_2101010:
2477                 if (rgb_order)
2478                         return DRM_FORMAT_XBGR2101010;
2479                 else
2480                         return DRM_FORMAT_XRGB2101010;
2481         }
2482 }
2483
2484 static bool
2485 intel_alloc_initial_plane_obj(struct intel_crtc *crtc,
2486                               struct intel_initial_plane_config *plane_config)
2487 {
2488         struct drm_device *dev = crtc->base.dev;
2489         struct drm_i915_gem_object *obj = NULL;
2490         struct drm_mode_fb_cmd2 mode_cmd = { 0 };
2491         struct drm_framebuffer *fb = &plane_config->fb->base;
2492         u32 base_aligned = round_down(plane_config->base, PAGE_SIZE);
2493         u32 size_aligned = round_up(plane_config->base + plane_config->size,
2494                                     PAGE_SIZE);
2495
2496         size_aligned -= base_aligned;
2497
2498         if (plane_config->size == 0)
2499                 return false;
2500
2501         obj = i915_gem_object_create_stolen_for_preallocated(dev,
2502                                                              base_aligned,
2503                                                              base_aligned,
2504                                                              size_aligned);
2505         if (!obj)
2506                 return false;
2507
2508         obj->tiling_mode = plane_config->tiling;
2509         if (obj->tiling_mode == I915_TILING_X)
2510                 obj->stride = fb->pitches[0];
2511
2512         mode_cmd.pixel_format = fb->pixel_format;
2513         mode_cmd.width = fb->width;
2514         mode_cmd.height = fb->height;
2515         mode_cmd.pitches[0] = fb->pitches[0];
2516         mode_cmd.modifier[0] = fb->modifier[0];
2517         mode_cmd.flags = DRM_MODE_FB_MODIFIERS;
2518
2519         mutex_lock(&dev->struct_mutex);
2520         if (intel_framebuffer_init(dev, to_intel_framebuffer(fb),
2521                                    &mode_cmd, obj)) {
2522                 DRM_DEBUG_KMS("intel fb init failed\n");
2523                 goto out_unref_obj;
2524         }
2525         mutex_unlock(&dev->struct_mutex);
2526
2527         DRM_DEBUG_KMS("initial plane fb obj %p\n", obj);
2528         return true;
2529
2530 out_unref_obj:
2531         drm_gem_object_unreference(&obj->base);
2532         mutex_unlock(&dev->struct_mutex);
2533         return false;
2534 }
2535
2536 /* Update plane->state->fb to match plane->fb after driver-internal updates */
2537 static void
2538 update_state_fb(struct drm_plane *plane)
2539 {
2540         if (plane->fb == plane->state->fb)
2541                 return;
2542
2543         if (plane->state->fb)
2544                 drm_framebuffer_unreference(plane->state->fb);
2545         plane->state->fb = plane->fb;
2546         if (plane->state->fb)
2547                 drm_framebuffer_reference(plane->state->fb);
2548 }
2549
2550 static void
2551 intel_find_initial_plane_obj(struct intel_crtc *intel_crtc,
2552                              struct intel_initial_plane_config *plane_config)
2553 {
2554         struct drm_device *dev = intel_crtc->base.dev;
2555         struct drm_i915_private *dev_priv = dev->dev_private;
2556         struct drm_crtc *c;
2557         struct intel_crtc *i;
2558         struct drm_i915_gem_object *obj;
2559         struct drm_plane *primary = intel_crtc->base.primary;
2560         struct drm_framebuffer *fb;
2561
2562         if (!plane_config->fb)
2563                 return;
2564
2565         if (intel_alloc_initial_plane_obj(intel_crtc, plane_config)) {
2566                 fb = &plane_config->fb->base;
2567                 goto valid_fb;
2568         }
2569
2570         kfree(plane_config->fb);
2571
2572         /*
2573          * Failed to alloc the obj, check to see if we should share
2574          * an fb with another CRTC instead
2575          */
2576         for_each_crtc(dev, c) {
2577                 i = to_intel_crtc(c);
2578
2579                 if (c == &intel_crtc->base)
2580                         continue;
2581
2582                 if (!i->active)
2583                         continue;
2584
2585                 fb = c->primary->fb;
2586                 if (!fb)
2587                         continue;
2588
2589                 obj = intel_fb_obj(fb);
2590                 if (i915_gem_obj_ggtt_offset(obj) == plane_config->base) {
2591                         drm_framebuffer_reference(fb);
2592                         goto valid_fb;
2593                 }
2594         }
2595
2596         return;
2597
2598 valid_fb:
2599         obj = intel_fb_obj(fb);
2600         if (obj->tiling_mode != I915_TILING_NONE)
2601                 dev_priv->preserve_bios_swizzle = true;
2602
2603         primary->fb = fb;
2604         primary->crtc = primary->state->crtc = &intel_crtc->base;
2605         update_state_fb(primary);
2606         intel_crtc->base.state->plane_mask |= (1 << drm_plane_index(primary));
2607         obj->frontbuffer_bits |= INTEL_FRONTBUFFER_PRIMARY(intel_crtc->pipe);
2608 }
2609
2610 static void i9xx_update_primary_plane(struct drm_crtc *crtc,
2611                                       struct drm_framebuffer *fb,
2612                                       int x, int y)
2613 {
2614         struct drm_device *dev = crtc->dev;
2615         struct drm_i915_private *dev_priv = dev->dev_private;
2616         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2617         struct drm_plane *primary = crtc->primary;
2618         bool visible = to_intel_plane_state(primary->state)->visible;
2619         struct drm_i915_gem_object *obj;
2620         int plane = intel_crtc->plane;
2621         unsigned long linear_offset;
2622         u32 dspcntr;
2623         u32 reg = DSPCNTR(plane);
2624         int pixel_size;
2625
2626         if (!visible || !fb) {
2627                 I915_WRITE(reg, 0);
2628                 if (INTEL_INFO(dev)->gen >= 4)
2629                         I915_WRITE(DSPSURF(plane), 0);
2630                 else
2631                         I915_WRITE(DSPADDR(plane), 0);
2632                 POSTING_READ(reg);
2633                 return;
2634         }
2635
2636         obj = intel_fb_obj(fb);
2637         if (WARN_ON(obj == NULL))
2638                 return;
2639
2640         pixel_size = drm_format_plane_cpp(fb->pixel_format, 0);
2641
2642         dspcntr = DISPPLANE_GAMMA_ENABLE;
2643
2644         dspcntr |= DISPLAY_PLANE_ENABLE;
2645
2646         if (INTEL_INFO(dev)->gen < 4) {
2647                 if (intel_crtc->pipe == PIPE_B)
2648                         dspcntr |= DISPPLANE_SEL_PIPE_B;
2649
2650                 /* pipesrc and dspsize control the size that is scaled from,
2651                  * which should always be the user's requested size.
2652                  */
2653                 I915_WRITE(DSPSIZE(plane),
2654                            ((intel_crtc->config->pipe_src_h - 1) << 16) |
2655                            (intel_crtc->config->pipe_src_w - 1));
2656                 I915_WRITE(DSPPOS(plane), 0);
2657         } else if (IS_CHERRYVIEW(dev) && plane == PLANE_B) {
2658                 I915_WRITE(PRIMSIZE(plane),
2659                            ((intel_crtc->config->pipe_src_h - 1) << 16) |
2660                            (intel_crtc->config->pipe_src_w - 1));
2661                 I915_WRITE(PRIMPOS(plane), 0);
2662                 I915_WRITE(PRIMCNSTALPHA(plane), 0);
2663         }
2664
2665         switch (fb->pixel_format) {
2666         case DRM_FORMAT_C8:
2667                 dspcntr |= DISPPLANE_8BPP;
2668                 break;
2669         case DRM_FORMAT_XRGB1555:
2670                 dspcntr |= DISPPLANE_BGRX555;
2671                 break;
2672         case DRM_FORMAT_RGB565:
2673                 dspcntr |= DISPPLANE_BGRX565;
2674                 break;
2675         case DRM_FORMAT_XRGB8888:
2676                 dspcntr |= DISPPLANE_BGRX888;
2677                 break;
2678         case DRM_FORMAT_XBGR8888:
2679                 dspcntr |= DISPPLANE_RGBX888;
2680                 break;
2681         case DRM_FORMAT_XRGB2101010:
2682                 dspcntr |= DISPPLANE_BGRX101010;
2683                 break;
2684         case DRM_FORMAT_XBGR2101010:
2685                 dspcntr |= DISPPLANE_RGBX101010;
2686                 break;
2687         default:
2688                 BUG();
2689         }
2690
2691         if (INTEL_INFO(dev)->gen >= 4 &&
2692             obj->tiling_mode != I915_TILING_NONE)
2693                 dspcntr |= DISPPLANE_TILED;
2694
2695         if (IS_G4X(dev))
2696                 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2697
2698         linear_offset = y * fb->pitches[0] + x * pixel_size;
2699
2700         if (INTEL_INFO(dev)->gen >= 4) {
2701                 intel_crtc->dspaddr_offset =
2702                         intel_gen4_compute_page_offset(dev_priv,
2703                                                        &x, &y, obj->tiling_mode,
2704                                                        pixel_size,
2705                                                        fb->pitches[0]);
2706                 linear_offset -= intel_crtc->dspaddr_offset;
2707         } else {
2708                 intel_crtc->dspaddr_offset = linear_offset;
2709         }
2710
2711         if (crtc->primary->state->rotation == BIT(DRM_ROTATE_180)) {
2712                 dspcntr |= DISPPLANE_ROTATE_180;
2713
2714                 x += (intel_crtc->config->pipe_src_w - 1);
2715                 y += (intel_crtc->config->pipe_src_h - 1);
2716
2717                 /* Finding the last pixel of the last line of the display
2718                 data and adding to linear_offset*/
2719                 linear_offset +=
2720                         (intel_crtc->config->pipe_src_h - 1) * fb->pitches[0] +
2721                         (intel_crtc->config->pipe_src_w - 1) * pixel_size;
2722         }
2723
2724         I915_WRITE(reg, dspcntr);
2725
2726         I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2727         if (INTEL_INFO(dev)->gen >= 4) {
2728                 I915_WRITE(DSPSURF(plane),
2729                            i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
2730                 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2731                 I915_WRITE(DSPLINOFF(plane), linear_offset);
2732         } else
2733                 I915_WRITE(DSPADDR(plane), i915_gem_obj_ggtt_offset(obj) + linear_offset);
2734         POSTING_READ(reg);
2735 }
2736
2737 static void ironlake_update_primary_plane(struct drm_crtc *crtc,
2738                                           struct drm_framebuffer *fb,
2739                                           int x, int y)
2740 {
2741         struct drm_device *dev = crtc->dev;
2742         struct drm_i915_private *dev_priv = dev->dev_private;
2743         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2744         struct drm_plane *primary = crtc->primary;
2745         bool visible = to_intel_plane_state(primary->state)->visible;
2746         struct drm_i915_gem_object *obj;
2747         int plane = intel_crtc->plane;
2748         unsigned long linear_offset;
2749         u32 dspcntr;
2750         u32 reg = DSPCNTR(plane);
2751         int pixel_size;
2752
2753         if (!visible || !fb) {
2754                 I915_WRITE(reg, 0);
2755                 I915_WRITE(DSPSURF(plane), 0);
2756                 POSTING_READ(reg);
2757                 return;
2758         }
2759
2760         obj = intel_fb_obj(fb);
2761         if (WARN_ON(obj == NULL))
2762                 return;
2763
2764         pixel_size = drm_format_plane_cpp(fb->pixel_format, 0);
2765
2766         dspcntr = DISPPLANE_GAMMA_ENABLE;
2767
2768         dspcntr |= DISPLAY_PLANE_ENABLE;
2769
2770         if (IS_HASWELL(dev) || IS_BROADWELL(dev))
2771                 dspcntr |= DISPPLANE_PIPE_CSC_ENABLE;
2772
2773         switch (fb->pixel_format) {
2774         case DRM_FORMAT_C8:
2775                 dspcntr |= DISPPLANE_8BPP;
2776                 break;
2777         case DRM_FORMAT_RGB565:
2778                 dspcntr |= DISPPLANE_BGRX565;
2779                 break;
2780         case DRM_FORMAT_XRGB8888:
2781                 dspcntr |= DISPPLANE_BGRX888;
2782                 break;
2783         case DRM_FORMAT_XBGR8888:
2784                 dspcntr |= DISPPLANE_RGBX888;
2785                 break;
2786         case DRM_FORMAT_XRGB2101010:
2787                 dspcntr |= DISPPLANE_BGRX101010;
2788                 break;
2789         case DRM_FORMAT_XBGR2101010:
2790                 dspcntr |= DISPPLANE_RGBX101010;
2791                 break;
2792         default:
2793                 BUG();
2794         }
2795
2796         if (obj->tiling_mode != I915_TILING_NONE)
2797                 dspcntr |= DISPPLANE_TILED;
2798
2799         if (!IS_HASWELL(dev) && !IS_BROADWELL(dev))
2800                 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2801
2802         linear_offset = y * fb->pitches[0] + x * pixel_size;
2803         intel_crtc->dspaddr_offset =
2804                 intel_gen4_compute_page_offset(dev_priv,
2805                                                &x, &y, obj->tiling_mode,
2806                                                pixel_size,
2807                                                fb->pitches[0]);
2808         linear_offset -= intel_crtc->dspaddr_offset;
2809         if (crtc->primary->state->rotation == BIT(DRM_ROTATE_180)) {
2810                 dspcntr |= DISPPLANE_ROTATE_180;
2811
2812                 if (!IS_HASWELL(dev) && !IS_BROADWELL(dev)) {
2813                         x += (intel_crtc->config->pipe_src_w - 1);
2814                         y += (intel_crtc->config->pipe_src_h - 1);
2815
2816                         /* Finding the last pixel of the last line of the display
2817                         data and adding to linear_offset*/
2818                         linear_offset +=
2819                                 (intel_crtc->config->pipe_src_h - 1) * fb->pitches[0] +
2820                                 (intel_crtc->config->pipe_src_w - 1) * pixel_size;
2821                 }
2822         }
2823
2824         I915_WRITE(reg, dspcntr);
2825
2826         I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2827         I915_WRITE(DSPSURF(plane),
2828                    i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
2829         if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
2830                 I915_WRITE(DSPOFFSET(plane), (y << 16) | x);
2831         } else {
2832                 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2833                 I915_WRITE(DSPLINOFF(plane), linear_offset);
2834         }
2835         POSTING_READ(reg);
2836 }
2837
2838 u32 intel_fb_stride_alignment(struct drm_device *dev, uint64_t fb_modifier,
2839                               uint32_t pixel_format)
2840 {
2841         u32 bits_per_pixel = drm_format_plane_cpp(pixel_format, 0) * 8;
2842
2843         /*
2844          * The stride is either expressed as a multiple of 64 bytes
2845          * chunks for linear buffers or in number of tiles for tiled
2846          * buffers.
2847          */
2848         switch (fb_modifier) {
2849         case DRM_FORMAT_MOD_NONE:
2850                 return 64;
2851         case I915_FORMAT_MOD_X_TILED:
2852                 if (INTEL_INFO(dev)->gen == 2)
2853                         return 128;
2854                 return 512;
2855         case I915_FORMAT_MOD_Y_TILED:
2856                 /* No need to check for old gens and Y tiling since this is
2857                  * about the display engine and those will be blocked before
2858                  * we get here.
2859                  */
2860                 return 128;
2861         case I915_FORMAT_MOD_Yf_TILED:
2862                 if (bits_per_pixel == 8)
2863                         return 64;
2864                 else
2865                         return 128;
2866         default:
2867                 MISSING_CASE(fb_modifier);
2868                 return 64;
2869         }
2870 }
2871
2872 unsigned long intel_plane_obj_offset(struct intel_plane *intel_plane,
2873                                      struct drm_i915_gem_object *obj)
2874 {
2875         const struct i915_ggtt_view *view = &i915_ggtt_view_normal;
2876
2877         if (intel_rotation_90_or_270(intel_plane->base.state->rotation))
2878                 view = &i915_ggtt_view_rotated;
2879
2880         return i915_gem_obj_ggtt_offset_view(obj, view);
2881 }
2882
2883 /*
2884  * This function detaches (aka. unbinds) unused scalers in hardware
2885  */
2886 static void skl_detach_scalers(struct intel_crtc *intel_crtc)
2887 {
2888         struct drm_device *dev;
2889         struct drm_i915_private *dev_priv;
2890         struct intel_crtc_scaler_state *scaler_state;
2891         int i;
2892
2893         dev = intel_crtc->base.dev;
2894         dev_priv = dev->dev_private;
2895         scaler_state = &intel_crtc->config->scaler_state;
2896
2897         /* loop through and disable scalers that aren't in use */
2898         for (i = 0; i < intel_crtc->num_scalers; i++) {
2899                 if (!scaler_state->scalers[i].in_use) {
2900                         I915_WRITE(SKL_PS_CTRL(intel_crtc->pipe, i), 0);
2901                         I915_WRITE(SKL_PS_WIN_POS(intel_crtc->pipe, i), 0);
2902                         I915_WRITE(SKL_PS_WIN_SZ(intel_crtc->pipe, i), 0);
2903                         DRM_DEBUG_KMS("CRTC:%d Disabled scaler id %u.%u\n",
2904                                 intel_crtc->base.base.id, intel_crtc->pipe, i);
2905                 }
2906         }
2907 }
2908
2909 u32 skl_plane_ctl_format(uint32_t pixel_format)
2910 {
2911         switch (pixel_format) {
2912         case DRM_FORMAT_C8:
2913                 return PLANE_CTL_FORMAT_INDEXED;
2914         case DRM_FORMAT_RGB565:
2915                 return PLANE_CTL_FORMAT_RGB_565;
2916         case DRM_FORMAT_XBGR8888:
2917                 return PLANE_CTL_FORMAT_XRGB_8888 | PLANE_CTL_ORDER_RGBX;
2918         case DRM_FORMAT_XRGB8888:
2919                 return PLANE_CTL_FORMAT_XRGB_8888;
2920         /*
2921          * XXX: For ARBG/ABGR formats we default to expecting scanout buffers
2922          * to be already pre-multiplied. We need to add a knob (or a different
2923          * DRM_FORMAT) for user-space to configure that.
2924          */
2925         case DRM_FORMAT_ABGR8888:
2926                 return PLANE_CTL_FORMAT_XRGB_8888 | PLANE_CTL_ORDER_RGBX |
2927                         PLANE_CTL_ALPHA_SW_PREMULTIPLY;
2928         case DRM_FORMAT_ARGB8888:
2929                 return PLANE_CTL_FORMAT_XRGB_8888 |
2930                         PLANE_CTL_ALPHA_SW_PREMULTIPLY;
2931         case DRM_FORMAT_XRGB2101010:
2932                 return PLANE_CTL_FORMAT_XRGB_2101010;
2933         case DRM_FORMAT_XBGR2101010:
2934                 return PLANE_CTL_ORDER_RGBX | PLANE_CTL_FORMAT_XRGB_2101010;
2935         case DRM_FORMAT_YUYV:
2936                 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YUYV;
2937         case DRM_FORMAT_YVYU:
2938                 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YVYU;
2939         case DRM_FORMAT_UYVY:
2940                 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_UYVY;
2941         case DRM_FORMAT_VYUY:
2942                 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_VYUY;
2943         default:
2944                 MISSING_CASE(pixel_format);
2945         }
2946
2947         return 0;
2948 }
2949
2950 u32 skl_plane_ctl_tiling(uint64_t fb_modifier)
2951 {
2952         switch (fb_modifier) {
2953         case DRM_FORMAT_MOD_NONE:
2954                 break;
2955         case I915_FORMAT_MOD_X_TILED:
2956                 return PLANE_CTL_TILED_X;
2957         case I915_FORMAT_MOD_Y_TILED:
2958                 return PLANE_CTL_TILED_Y;
2959         case I915_FORMAT_MOD_Yf_TILED:
2960                 return PLANE_CTL_TILED_YF;
2961         default:
2962                 MISSING_CASE(fb_modifier);
2963         }
2964
2965         return 0;
2966 }
2967
2968 u32 skl_plane_ctl_rotation(unsigned int rotation)
2969 {
2970         switch (rotation) {
2971         case BIT(DRM_ROTATE_0):
2972                 break;
2973         /*
2974          * DRM_ROTATE_ is counter clockwise to stay compatible with Xrandr
2975          * while i915 HW rotation is clockwise, thats why this swapping.
2976          */
2977         case BIT(DRM_ROTATE_90):
2978                 return PLANE_CTL_ROTATE_270;
2979         case BIT(DRM_ROTATE_180):
2980                 return PLANE_CTL_ROTATE_180;
2981         case BIT(DRM_ROTATE_270):
2982                 return PLANE_CTL_ROTATE_90;
2983         default:
2984                 MISSING_CASE(rotation);
2985         }
2986
2987         return 0;
2988 }
2989
2990 static void skylake_update_primary_plane(struct drm_crtc *crtc,
2991                                          struct drm_framebuffer *fb,
2992                                          int x, int y)
2993 {
2994         struct drm_device *dev = crtc->dev;
2995         struct drm_i915_private *dev_priv = dev->dev_private;
2996         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2997         struct drm_plane *plane = crtc->primary;
2998         bool visible = to_intel_plane_state(plane->state)->visible;
2999         struct drm_i915_gem_object *obj;
3000         int pipe = intel_crtc->pipe;
3001         u32 plane_ctl, stride_div, stride;
3002         u32 tile_height, plane_offset, plane_size;
3003         unsigned int rotation;
3004         int x_offset, y_offset;
3005         unsigned long surf_addr;
3006         struct intel_crtc_state *crtc_state = intel_crtc->config;
3007         struct intel_plane_state *plane_state;
3008         int src_x = 0, src_y = 0, src_w = 0, src_h = 0;
3009         int dst_x = 0, dst_y = 0, dst_w = 0, dst_h = 0;
3010         int scaler_id = -1;
3011
3012         plane_state = to_intel_plane_state(plane->state);
3013
3014         if (!visible || !fb) {
3015                 I915_WRITE(PLANE_CTL(pipe, 0), 0);
3016                 I915_WRITE(PLANE_SURF(pipe, 0), 0);
3017                 POSTING_READ(PLANE_CTL(pipe, 0));
3018                 return;
3019         }
3020
3021         plane_ctl = PLANE_CTL_ENABLE |
3022                     PLANE_CTL_PIPE_GAMMA_ENABLE |
3023                     PLANE_CTL_PIPE_CSC_ENABLE;
3024
3025         plane_ctl |= skl_plane_ctl_format(fb->pixel_format);
3026         plane_ctl |= skl_plane_ctl_tiling(fb->modifier[0]);
3027         plane_ctl |= PLANE_CTL_PLANE_GAMMA_DISABLE;
3028
3029         rotation = plane->state->rotation;
3030         plane_ctl |= skl_plane_ctl_rotation(rotation);
3031
3032         obj = intel_fb_obj(fb);
3033         stride_div = intel_fb_stride_alignment(dev, fb->modifier[0],
3034                                                fb->pixel_format);
3035         surf_addr = intel_plane_obj_offset(to_intel_plane(plane), obj);
3036
3037         /*
3038          * FIXME: intel_plane_state->src, dst aren't set when transitional
3039          * update_plane helpers are called from legacy paths.
3040          * Once full atomic crtc is available, below check can be avoided.
3041          */
3042         if (drm_rect_width(&plane_state->src)) {
3043                 scaler_id = plane_state->scaler_id;
3044                 src_x = plane_state->src.x1 >> 16;
3045                 src_y = plane_state->src.y1 >> 16;
3046                 src_w = drm_rect_width(&plane_state->src) >> 16;
3047                 src_h = drm_rect_height(&plane_state->src) >> 16;
3048                 dst_x = plane_state->dst.x1;
3049                 dst_y = plane_state->dst.y1;
3050                 dst_w = drm_rect_width(&plane_state->dst);
3051                 dst_h = drm_rect_height(&plane_state->dst);
3052
3053                 WARN_ON(x != src_x || y != src_y);
3054         } else {
3055                 src_w = intel_crtc->config->pipe_src_w;
3056                 src_h = intel_crtc->config->pipe_src_h;
3057         }
3058
3059         if (intel_rotation_90_or_270(rotation)) {
3060                 /* stride = Surface height in tiles */
3061                 tile_height = intel_tile_height(dev, fb->pixel_format,
3062                                                 fb->modifier[0]);
3063                 stride = DIV_ROUND_UP(fb->height, tile_height);
3064                 x_offset = stride * tile_height - y - src_h;
3065                 y_offset = x;
3066                 plane_size = (src_w - 1) << 16 | (src_h - 1);
3067         } else {
3068                 stride = fb->pitches[0] / stride_div;
3069                 x_offset = x;
3070                 y_offset = y;
3071                 plane_size = (src_h - 1) << 16 | (src_w - 1);
3072         }
3073         plane_offset = y_offset << 16 | x_offset;
3074
3075         I915_WRITE(PLANE_CTL(pipe, 0), plane_ctl);
3076         I915_WRITE(PLANE_OFFSET(pipe, 0), plane_offset);
3077         I915_WRITE(PLANE_SIZE(pipe, 0), plane_size);
3078         I915_WRITE(PLANE_STRIDE(pipe, 0), stride);
3079
3080         if (scaler_id >= 0) {
3081                 uint32_t ps_ctrl = 0;
3082
3083                 WARN_ON(!dst_w || !dst_h);
3084                 ps_ctrl = PS_SCALER_EN | PS_PLANE_SEL(0) |
3085                         crtc_state->scaler_state.scalers[scaler_id].mode;
3086                 I915_WRITE(SKL_PS_CTRL(pipe, scaler_id), ps_ctrl);
3087                 I915_WRITE(SKL_PS_PWR_GATE(pipe, scaler_id), 0);
3088                 I915_WRITE(SKL_PS_WIN_POS(pipe, scaler_id), (dst_x << 16) | dst_y);
3089                 I915_WRITE(SKL_PS_WIN_SZ(pipe, scaler_id), (dst_w << 16) | dst_h);
3090                 I915_WRITE(PLANE_POS(pipe, 0), 0);
3091         } else {
3092                 I915_WRITE(PLANE_POS(pipe, 0), (dst_y << 16) | dst_x);
3093         }
3094
3095         I915_WRITE(PLANE_SURF(pipe, 0), surf_addr);
3096
3097         POSTING_READ(PLANE_SURF(pipe, 0));
3098 }
3099
3100 /* Assume fb object is pinned & idle & fenced and just update base pointers */
3101 static int
3102 intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
3103                            int x, int y, enum mode_set_atomic state)
3104 {
3105         struct drm_device *dev = crtc->dev;
3106         struct drm_i915_private *dev_priv = dev->dev_private;
3107
3108         if (dev_priv->display.disable_fbc)
3109                 dev_priv->display.disable_fbc(dev);
3110
3111         dev_priv->display.update_primary_plane(crtc, fb, x, y);
3112
3113         return 0;
3114 }
3115
3116 static void intel_complete_page_flips(struct drm_device *dev)
3117 {
3118         struct drm_crtc *crtc;
3119
3120         for_each_crtc(dev, crtc) {
3121                 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3122                 enum plane plane = intel_crtc->plane;
3123
3124                 intel_prepare_page_flip(dev, plane);
3125                 intel_finish_page_flip_plane(dev, plane);
3126         }
3127 }
3128
3129 static void intel_update_primary_planes(struct drm_device *dev)
3130 {
3131         struct drm_i915_private *dev_priv = dev->dev_private;
3132         struct drm_crtc *crtc;
3133
3134         for_each_crtc(dev, crtc) {
3135                 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3136
3137                 drm_modeset_lock(&crtc->mutex, NULL);
3138                 /*
3139                  * FIXME: Once we have proper support for primary planes (and
3140                  * disabling them without disabling the entire crtc) allow again
3141                  * a NULL crtc->primary->fb.
3142                  */
3143                 if (intel_crtc->active && crtc->primary->fb)
3144                         dev_priv->display.update_primary_plane(crtc,
3145                                                                crtc->primary->fb,
3146                                                                crtc->x,
3147                                                                crtc->y);
3148                 drm_modeset_unlock(&crtc->mutex);
3149         }
3150 }
3151
3152 void intel_prepare_reset(struct drm_device *dev)
3153 {
3154         /* no reset support for gen2 */
3155         if (IS_GEN2(dev))
3156                 return;
3157
3158         /* reset doesn't touch the display */
3159         if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev))
3160                 return;
3161
3162         drm_modeset_lock_all(dev);
3163         /*
3164          * Disabling the crtcs gracefully seems nicer. Also the
3165          * g33 docs say we should at least disable all the planes.
3166          */
3167         intel_display_suspend(dev);
3168 }
3169
3170 void intel_finish_reset(struct drm_device *dev)
3171 {
3172         struct drm_i915_private *dev_priv = to_i915(dev);
3173
3174         /*
3175          * Flips in the rings will be nuked by the reset,
3176          * so complete all pending flips so that user space
3177          * will get its events and not get stuck.
3178          */
3179         intel_complete_page_flips(dev);
3180
3181         /* no reset support for gen2 */
3182         if (IS_GEN2(dev))
3183                 return;
3184
3185         /* reset doesn't touch the display */
3186         if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev)) {
3187                 /*
3188                  * Flips in the rings have been nuked by the reset,
3189                  * so update the base address of all primary
3190                  * planes to the the last fb to make sure we're
3191                  * showing the correct fb after a reset.
3192                  */
3193                 intel_update_primary_planes(dev);
3194                 return;
3195         }
3196
3197         /*
3198          * The display has been reset as well,
3199          * so need a full re-initialization.
3200          */
3201         intel_runtime_pm_disable_interrupts(dev_priv);
3202         intel_runtime_pm_enable_interrupts(dev_priv);
3203
3204         intel_modeset_init_hw(dev);
3205
3206         spin_lock_irq(&dev_priv->irq_lock);
3207         if (dev_priv->display.hpd_irq_setup)
3208                 dev_priv->display.hpd_irq_setup(dev);
3209         spin_unlock_irq(&dev_priv->irq_lock);
3210
3211         intel_modeset_setup_hw_state(dev, true);
3212
3213         intel_hpd_init(dev_priv);
3214
3215         drm_modeset_unlock_all(dev);
3216 }
3217
3218 static void
3219 intel_finish_fb(struct drm_framebuffer *old_fb)
3220 {
3221         struct drm_i915_gem_object *obj = intel_fb_obj(old_fb);
3222         struct drm_i915_private *dev_priv = to_i915(obj->base.dev);
3223         bool was_interruptible = dev_priv->mm.interruptible;
3224         int ret;
3225
3226         /* Big Hammer, we also need to ensure that any pending
3227          * MI_WAIT_FOR_EVENT inside a user batch buffer on the
3228          * current scanout is retired before unpinning the old
3229          * framebuffer. Note that we rely on userspace rendering
3230          * into the buffer attached to the pipe they are waiting
3231          * on. If not, userspace generates a GPU hang with IPEHR
3232          * point to the MI_WAIT_FOR_EVENT.
3233          *
3234          * This should only fail upon a hung GPU, in which case we
3235          * can safely continue.
3236          */
3237         dev_priv->mm.interruptible = false;
3238         ret = i915_gem_object_wait_rendering(obj, true);
3239         dev_priv->mm.interruptible = was_interruptible;
3240
3241         WARN_ON(ret);
3242 }
3243
3244 static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc)
3245 {
3246         struct drm_device *dev = crtc->dev;
3247         struct drm_i915_private *dev_priv = dev->dev_private;
3248         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3249         bool pending;
3250
3251         if (i915_reset_in_progress(&dev_priv->gpu_error) ||
3252             intel_crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
3253                 return false;
3254
3255         spin_lock_irq(&dev->event_lock);
3256         pending = to_intel_crtc(crtc)->unpin_work != NULL;
3257         spin_unlock_irq(&dev->event_lock);
3258
3259         return pending;
3260 }
3261
3262 static void intel_update_pipe_size(struct intel_crtc *crtc)
3263 {
3264         struct drm_device *dev = crtc->base.dev;
3265         struct drm_i915_private *dev_priv = dev->dev_private;
3266         const struct drm_display_mode *adjusted_mode;
3267
3268         if (!i915.fastboot)
3269                 return;
3270
3271         /*
3272          * Update pipe size and adjust fitter if needed: the reason for this is
3273          * that in compute_mode_changes we check the native mode (not the pfit
3274          * mode) to see if we can flip rather than do a full mode set. In the
3275          * fastboot case, we'll flip, but if we don't update the pipesrc and
3276          * pfit state, we'll end up with a big fb scanned out into the wrong
3277          * sized surface.
3278          *
3279          * To fix this properly, we need to hoist the checks up into
3280          * compute_mode_changes (or above), check the actual pfit state and
3281          * whether the platform allows pfit disable with pipe active, and only
3282          * then update the pipesrc and pfit state, even on the flip path.
3283          */
3284
3285         adjusted_mode = &crtc->config->base.adjusted_mode;
3286
3287         I915_WRITE(PIPESRC(crtc->pipe),
3288                    ((adjusted_mode->crtc_hdisplay - 1) << 16) |
3289                    (adjusted_mode->crtc_vdisplay - 1));
3290         if (!crtc->config->pch_pfit.enabled &&
3291             (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) ||
3292              intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
3293                 I915_WRITE(PF_CTL(crtc->pipe), 0);
3294                 I915_WRITE(PF_WIN_POS(crtc->pipe), 0);
3295                 I915_WRITE(PF_WIN_SZ(crtc->pipe), 0);
3296         }
3297         crtc->config->pipe_src_w = adjusted_mode->crtc_hdisplay;
3298         crtc->config->pipe_src_h = adjusted_mode->crtc_vdisplay;
3299 }
3300
3301 static void intel_fdi_normal_train(struct drm_crtc *crtc)
3302 {
3303         struct drm_device *dev = crtc->dev;
3304         struct drm_i915_private *dev_priv = dev->dev_private;
3305         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3306         int pipe = intel_crtc->pipe;
3307         u32 reg, temp;
3308
3309         /* enable normal train */
3310         reg = FDI_TX_CTL(pipe);
3311         temp = I915_READ(reg);
3312         if (IS_IVYBRIDGE(dev)) {
3313                 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
3314                 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
3315         } else {
3316                 temp &= ~FDI_LINK_TRAIN_NONE;
3317                 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
3318         }
3319         I915_WRITE(reg, temp);
3320
3321         reg = FDI_RX_CTL(pipe);
3322         temp = I915_READ(reg);
3323         if (HAS_PCH_CPT(dev)) {
3324                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3325                 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
3326         } else {
3327                 temp &= ~FDI_LINK_TRAIN_NONE;
3328                 temp |= FDI_LINK_TRAIN_NONE;
3329         }
3330         I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
3331
3332         /* wait one idle pattern time */
3333         POSTING_READ(reg);
3334         udelay(1000);
3335
3336         /* IVB wants error correction enabled */
3337         if (IS_IVYBRIDGE(dev))
3338                 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
3339                            FDI_FE_ERRC_ENABLE);
3340 }
3341
3342 /* The FDI link training functions for ILK/Ibexpeak. */
3343 static void ironlake_fdi_link_train(struct drm_crtc *crtc)
3344 {
3345         struct drm_device *dev = crtc->dev;
3346         struct drm_i915_private *dev_priv = dev->dev_private;
3347         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3348         int pipe = intel_crtc->pipe;
3349         u32 reg, temp, tries;
3350
3351         /* FDI needs bits from pipe first */
3352         assert_pipe_enabled(dev_priv, pipe);
3353
3354         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3355            for train result */
3356         reg = FDI_RX_IMR(pipe);
3357         temp = I915_READ(reg);
3358         temp &= ~FDI_RX_SYMBOL_LOCK;
3359         temp &= ~FDI_RX_BIT_LOCK;
3360         I915_WRITE(reg, temp);
3361         I915_READ(reg);
3362         udelay(150);
3363
3364         /* enable CPU FDI TX and PCH FDI RX */
3365         reg = FDI_TX_CTL(pipe);
3366         temp = I915_READ(reg);
3367         temp &= ~FDI_DP_PORT_WIDTH_MASK;
3368         temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
3369         temp &= ~FDI_LINK_TRAIN_NONE;
3370         temp |= FDI_LINK_TRAIN_PATTERN_1;
3371         I915_WRITE(reg, temp | FDI_TX_ENABLE);
3372
3373         reg = FDI_RX_CTL(pipe);
3374         temp = I915_READ(reg);
3375         temp &= ~FDI_LINK_TRAIN_NONE;
3376         temp |= FDI_LINK_TRAIN_PATTERN_1;
3377         I915_WRITE(reg, temp | FDI_RX_ENABLE);
3378
3379         POSTING_READ(reg);
3380         udelay(150);
3381
3382         /* Ironlake workaround, enable clock pointer after FDI enable*/
3383         I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
3384         I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
3385                    FDI_RX_PHASE_SYNC_POINTER_EN);
3386
3387         reg = FDI_RX_IIR(pipe);
3388         for (tries = 0; tries < 5; tries++) {
3389                 temp = I915_READ(reg);
3390                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3391
3392                 if ((temp & FDI_RX_BIT_LOCK)) {
3393                         DRM_DEBUG_KMS("FDI train 1 done.\n");
3394                         I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3395                         break;
3396                 }
3397         }
3398         if (tries == 5)
3399                 DRM_ERROR("FDI train 1 fail!\n");
3400
3401         /* Train 2 */
3402         reg = FDI_TX_CTL(pipe);
3403         temp = I915_READ(reg);
3404         temp &= ~FDI_LINK_TRAIN_NONE;
3405         temp |= FDI_LINK_TRAIN_PATTERN_2;
3406         I915_WRITE(reg, temp);
3407
3408         reg = FDI_RX_CTL(pipe);
3409         temp = I915_READ(reg);
3410         temp &= ~FDI_LINK_TRAIN_NONE;
3411         temp |= FDI_LINK_TRAIN_PATTERN_2;
3412         I915_WRITE(reg, temp);
3413
3414         POSTING_READ(reg);
3415         udelay(150);
3416
3417         reg = FDI_RX_IIR(pipe);
3418         for (tries = 0; tries < 5; tries++) {
3419                 temp = I915_READ(reg);
3420                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3421
3422                 if (temp & FDI_RX_SYMBOL_LOCK) {
3423                         I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3424                         DRM_DEBUG_KMS("FDI train 2 done.\n");
3425                         break;
3426                 }
3427         }
3428         if (tries == 5)
3429                 DRM_ERROR("FDI train 2 fail!\n");
3430
3431         DRM_DEBUG_KMS("FDI train done\n");
3432
3433 }
3434
3435 static const int snb_b_fdi_train_param[] = {
3436         FDI_LINK_TRAIN_400MV_0DB_SNB_B,
3437         FDI_LINK_TRAIN_400MV_6DB_SNB_B,
3438         FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
3439         FDI_LINK_TRAIN_800MV_0DB_SNB_B,
3440 };
3441
3442 /* The FDI link training functions for SNB/Cougarpoint. */
3443 static void gen6_fdi_link_train(struct drm_crtc *crtc)
3444 {
3445         struct drm_device *dev = crtc->dev;
3446         struct drm_i915_private *dev_priv = dev->dev_private;
3447         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3448         int pipe = intel_crtc->pipe;
3449         u32 reg, temp, i, retry;
3450
3451         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3452            for train result */
3453         reg = FDI_RX_IMR(pipe);
3454         temp = I915_READ(reg);
3455         temp &= ~FDI_RX_SYMBOL_LOCK;
3456         temp &= ~FDI_RX_BIT_LOCK;
3457         I915_WRITE(reg, temp);
3458
3459         POSTING_READ(reg);
3460         udelay(150);
3461
3462         /* enable CPU FDI TX and PCH FDI RX */
3463         reg = FDI_TX_CTL(pipe);
3464         temp = I915_READ(reg);
3465         temp &= ~FDI_DP_PORT_WIDTH_MASK;
3466         temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
3467         temp &= ~FDI_LINK_TRAIN_NONE;
3468         temp |= FDI_LINK_TRAIN_PATTERN_1;
3469         temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3470         /* SNB-B */
3471         temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
3472         I915_WRITE(reg, temp | FDI_TX_ENABLE);
3473
3474         I915_WRITE(FDI_RX_MISC(pipe),
3475                    FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
3476
3477         reg = FDI_RX_CTL(pipe);
3478         temp = I915_READ(reg);
3479         if (HAS_PCH_CPT(dev)) {
3480                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3481                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3482         } else {
3483                 temp &= ~FDI_LINK_TRAIN_NONE;
3484                 temp |= FDI_LINK_TRAIN_PATTERN_1;
3485         }
3486         I915_WRITE(reg, temp | FDI_RX_ENABLE);
3487
3488         POSTING_READ(reg);
3489         udelay(150);
3490
3491         for (i = 0; i < 4; i++) {
3492                 reg = FDI_TX_CTL(pipe);
3493                 temp = I915_READ(reg);
3494                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3495                 temp |= snb_b_fdi_train_param[i];
3496                 I915_WRITE(reg, temp);
3497
3498                 POSTING_READ(reg);
3499                 udelay(500);
3500
3501                 for (retry = 0; retry < 5; retry++) {
3502                         reg = FDI_RX_IIR(pipe);
3503                         temp = I915_READ(reg);
3504                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3505                         if (temp & FDI_RX_BIT_LOCK) {
3506                                 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3507                                 DRM_DEBUG_KMS("FDI train 1 done.\n");
3508                                 break;
3509                         }
3510                         udelay(50);
3511                 }
3512                 if (retry < 5)
3513                         break;
3514         }
3515         if (i == 4)
3516                 DRM_ERROR("FDI train 1 fail!\n");
3517
3518         /* Train 2 */
3519         reg = FDI_TX_CTL(pipe);
3520         temp = I915_READ(reg);
3521         temp &= ~FDI_LINK_TRAIN_NONE;
3522         temp |= FDI_LINK_TRAIN_PATTERN_2;
3523         if (IS_GEN6(dev)) {
3524                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3525                 /* SNB-B */
3526                 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
3527         }
3528         I915_WRITE(reg, temp);
3529
3530         reg = FDI_RX_CTL(pipe);
3531         temp = I915_READ(reg);
3532         if (HAS_PCH_CPT(dev)) {
3533                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3534                 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
3535         } else {
3536                 temp &= ~FDI_LINK_TRAIN_NONE;
3537                 temp |= FDI_LINK_TRAIN_PATTERN_2;
3538         }
3539         I915_WRITE(reg, temp);
3540
3541         POSTING_READ(reg);
3542         udelay(150);
3543
3544         for (i = 0; i < 4; i++) {
3545                 reg = FDI_TX_CTL(pipe);
3546                 temp = I915_READ(reg);
3547                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3548                 temp |= snb_b_fdi_train_param[i];
3549                 I915_WRITE(reg, temp);
3550
3551                 POSTING_READ(reg);
3552                 udelay(500);
3553
3554                 for (retry = 0; retry < 5; retry++) {
3555                         reg = FDI_RX_IIR(pipe);
3556                         temp = I915_READ(reg);
3557                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3558                         if (temp & FDI_RX_SYMBOL_LOCK) {
3559                                 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3560                                 DRM_DEBUG_KMS("FDI train 2 done.\n");
3561                                 break;
3562                         }
3563                         udelay(50);
3564                 }
3565                 if (retry < 5)
3566                         break;
3567         }
3568         if (i == 4)
3569                 DRM_ERROR("FDI train 2 fail!\n");
3570
3571         DRM_DEBUG_KMS("FDI train done.\n");
3572 }
3573
3574 /* Manual link training for Ivy Bridge A0 parts */
3575 static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
3576 {
3577         struct drm_device *dev = crtc->dev;
3578         struct drm_i915_private *dev_priv = dev->dev_private;
3579         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3580         int pipe = intel_crtc->pipe;
3581         u32 reg, temp, i, j;
3582
3583         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3584            for train result */
3585         reg = FDI_RX_IMR(pipe);
3586         temp = I915_READ(reg);
3587         temp &= ~FDI_RX_SYMBOL_LOCK;
3588         temp &= ~FDI_RX_BIT_LOCK;
3589         I915_WRITE(reg, temp);
3590
3591         POSTING_READ(reg);
3592         udelay(150);
3593
3594         DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
3595                       I915_READ(FDI_RX_IIR(pipe)));
3596
3597         /* Try each vswing and preemphasis setting twice before moving on */
3598         for (j = 0; j < ARRAY_SIZE(snb_b_fdi_train_param) * 2; j++) {
3599                 /* disable first in case we need to retry */
3600                 reg = FDI_TX_CTL(pipe);
3601                 temp = I915_READ(reg);
3602                 temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
3603                 temp &= ~FDI_TX_ENABLE;
3604                 I915_WRITE(reg, temp);
3605
3606                 reg = FDI_RX_CTL(pipe);
3607                 temp = I915_READ(reg);
3608                 temp &= ~FDI_LINK_TRAIN_AUTO;
3609                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3610                 temp &= ~FDI_RX_ENABLE;
3611                 I915_WRITE(reg, temp);
3612
3613                 /* enable CPU FDI TX and PCH FDI RX */
3614                 reg = FDI_TX_CTL(pipe);
3615                 temp = I915_READ(reg);
3616                 temp &= ~FDI_DP_PORT_WIDTH_MASK;
3617                 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
3618                 temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
3619                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3620                 temp |= snb_b_fdi_train_param[j/2];
3621                 temp |= FDI_COMPOSITE_SYNC;
3622                 I915_WRITE(reg, temp | FDI_TX_ENABLE);
3623
3624                 I915_WRITE(FDI_RX_MISC(pipe),
3625                            FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
3626
3627                 reg = FDI_RX_CTL(pipe);
3628                 temp = I915_READ(reg);
3629                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3630                 temp |= FDI_COMPOSITE_SYNC;
3631                 I915_WRITE(reg, temp | FDI_RX_ENABLE);
3632
3633                 POSTING_READ(reg);
3634                 udelay(1); /* should be 0.5us */
3635
3636                 for (i = 0; i < 4; i++) {
3637                         reg = FDI_RX_IIR(pipe);
3638                         temp = I915_READ(reg);
3639                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3640
3641                         if (temp & FDI_RX_BIT_LOCK ||
3642                             (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
3643                                 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3644                                 DRM_DEBUG_KMS("FDI train 1 done, level %i.\n",
3645                                               i);
3646                                 break;
3647                         }
3648                         udelay(1); /* should be 0.5us */
3649                 }
3650                 if (i == 4) {
3651                         DRM_DEBUG_KMS("FDI train 1 fail on vswing %d\n", j / 2);
3652                         continue;
3653                 }
3654
3655                 /* Train 2 */
3656                 reg = FDI_TX_CTL(pipe);
3657                 temp = I915_READ(reg);
3658                 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
3659                 temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
3660                 I915_WRITE(reg, temp);
3661
3662                 reg = FDI_RX_CTL(pipe);
3663                 temp = I915_READ(reg);
3664                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3665                 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
3666                 I915_WRITE(reg, temp);
3667
3668                 POSTING_READ(reg);
3669                 udelay(2); /* should be 1.5us */
3670
3671                 for (i = 0; i < 4; i++) {
3672                         reg = FDI_RX_IIR(pipe);
3673                         temp = I915_READ(reg);
3674                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3675
3676                         if (temp & FDI_RX_SYMBOL_LOCK ||
3677                             (I915_READ(reg) & FDI_RX_SYMBOL_LOCK)) {
3678                                 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3679                                 DRM_DEBUG_KMS("FDI train 2 done, level %i.\n",
3680                                               i);
3681                                 goto train_done;
3682                         }
3683                         udelay(2); /* should be 1.5us */
3684                 }
3685                 if (i == 4)
3686                         DRM_DEBUG_KMS("FDI train 2 fail on vswing %d\n", j / 2);
3687         }
3688
3689 train_done:
3690         DRM_DEBUG_KMS("FDI train done.\n");
3691 }
3692
3693 static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
3694 {
3695         struct drm_device *dev = intel_crtc->base.dev;
3696         struct drm_i915_private *dev_priv = dev->dev_private;
3697         int pipe = intel_crtc->pipe;
3698         u32 reg, temp;
3699
3700
3701         /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
3702         reg = FDI_RX_CTL(pipe);
3703         temp = I915_READ(reg);
3704         temp &= ~(FDI_DP_PORT_WIDTH_MASK | (0x7 << 16));
3705         temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
3706         temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3707         I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
3708
3709         POSTING_READ(reg);
3710         udelay(200);
3711
3712         /* Switch from Rawclk to PCDclk */
3713         temp = I915_READ(reg);
3714         I915_WRITE(reg, temp | FDI_PCDCLK);
3715
3716         POSTING_READ(reg);
3717         udelay(200);
3718
3719         /* Enable CPU FDI TX PLL, always on for Ironlake */
3720         reg = FDI_TX_CTL(pipe);
3721         temp = I915_READ(reg);
3722         if ((temp & FDI_TX_PLL_ENABLE) == 0) {
3723                 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
3724
3725                 POSTING_READ(reg);
3726                 udelay(100);
3727         }
3728 }
3729
3730 static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
3731 {
3732         struct drm_device *dev = intel_crtc->base.dev;
3733         struct drm_i915_private *dev_priv = dev->dev_private;
3734         int pipe = intel_crtc->pipe;
3735         u32 reg, temp;
3736
3737         /* Switch from PCDclk to Rawclk */
3738         reg = FDI_RX_CTL(pipe);
3739         temp = I915_READ(reg);
3740         I915_WRITE(reg, temp & ~FDI_PCDCLK);
3741
3742         /* Disable CPU FDI TX PLL */
3743         reg = FDI_TX_CTL(pipe);
3744         temp = I915_READ(reg);
3745         I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
3746
3747         POSTING_READ(reg);
3748         udelay(100);
3749
3750         reg = FDI_RX_CTL(pipe);
3751         temp = I915_READ(reg);
3752         I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
3753
3754         /* Wait for the clocks to turn off. */
3755         POSTING_READ(reg);
3756         udelay(100);
3757 }
3758
3759 static void ironlake_fdi_disable(struct drm_crtc *crtc)
3760 {
3761         struct drm_device *dev = crtc->dev;
3762         struct drm_i915_private *dev_priv = dev->dev_private;
3763         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3764         int pipe = intel_crtc->pipe;
3765         u32 reg, temp;
3766
3767         /* disable CPU FDI tx and PCH FDI rx */
3768         reg = FDI_TX_CTL(pipe);
3769         temp = I915_READ(reg);
3770         I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
3771         POSTING_READ(reg);
3772
3773         reg = FDI_RX_CTL(pipe);
3774         temp = I915_READ(reg);
3775         temp &= ~(0x7 << 16);
3776         temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3777         I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
3778
3779         POSTING_READ(reg);
3780         udelay(100);
3781
3782         /* Ironlake workaround, disable clock pointer after downing FDI */
3783         if (HAS_PCH_IBX(dev))
3784                 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
3785
3786         /* still set train pattern 1 */
3787         reg = FDI_TX_CTL(pipe);
3788         temp = I915_READ(reg);
3789         temp &= ~FDI_LINK_TRAIN_NONE;
3790         temp |= FDI_LINK_TRAIN_PATTERN_1;
3791         I915_WRITE(reg, temp);
3792
3793         reg = FDI_RX_CTL(pipe);
3794         temp = I915_READ(reg);
3795         if (HAS_PCH_CPT(dev)) {
3796                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3797                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3798         } else {
3799                 temp &= ~FDI_LINK_TRAIN_NONE;
3800                 temp |= FDI_LINK_TRAIN_PATTERN_1;
3801         }
3802         /* BPC in FDI rx is consistent with that in PIPECONF */
3803         temp &= ~(0x07 << 16);
3804         temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3805         I915_WRITE(reg, temp);
3806
3807         POSTING_READ(reg);
3808         udelay(100);
3809 }
3810
3811 bool intel_has_pending_fb_unpin(struct drm_device *dev)
3812 {
3813         struct intel_crtc *crtc;
3814
3815         /* Note that we don't need to be called with mode_config.lock here
3816          * as our list of CRTC objects is static for the lifetime of the
3817          * device and so cannot disappear as we iterate. Similarly, we can
3818          * happily treat the predicates as racy, atomic checks as userspace
3819          * cannot claim and pin a new fb without at least acquring the
3820          * struct_mutex and so serialising with us.
3821          */
3822         for_each_intel_crtc(dev, crtc) {
3823                 if (atomic_read(&crtc->unpin_work_count) == 0)
3824                         continue;
3825
3826                 if (crtc->unpin_work)
3827                         intel_wait_for_vblank(dev, crtc->pipe);
3828
3829                 return true;
3830         }
3831
3832         return false;
3833 }
3834
3835 static void page_flip_completed(struct intel_crtc *intel_crtc)
3836 {
3837         struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev);
3838         struct intel_unpin_work *work = intel_crtc->unpin_work;
3839
3840         /* ensure that the unpin work is consistent wrt ->pending. */
3841         smp_rmb();
3842         intel_crtc->unpin_work = NULL;
3843
3844         if (work->event)
3845                 drm_send_vblank_event(intel_crtc->base.dev,
3846                                       intel_crtc->pipe,
3847                                       work->event);
3848
3849         drm_crtc_vblank_put(&intel_crtc->base);
3850
3851         wake_up_all(&dev_priv->pending_flip_queue);
3852         queue_work(dev_priv->wq, &work->work);
3853
3854         trace_i915_flip_complete(intel_crtc->plane,
3855                                  work->pending_flip_obj);
3856 }
3857
3858 void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
3859 {
3860         struct drm_device *dev = crtc->dev;
3861         struct drm_i915_private *dev_priv = dev->dev_private;
3862
3863         WARN_ON(waitqueue_active(&dev_priv->pending_flip_queue));
3864         if (WARN_ON(wait_event_timeout(dev_priv->pending_flip_queue,
3865                                        !intel_crtc_has_pending_flip(crtc),
3866                                        60*HZ) == 0)) {
3867                 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3868
3869                 spin_lock_irq(&dev->event_lock);
3870                 if (intel_crtc->unpin_work) {
3871                         WARN_ONCE(1, "Removing stuck page flip\n");
3872                         page_flip_completed(intel_crtc);
3873                 }
3874                 spin_unlock_irq(&dev->event_lock);
3875         }
3876
3877         if (crtc->primary->fb) {
3878                 mutex_lock(&dev->struct_mutex);
3879                 intel_finish_fb(crtc->primary->fb);
3880                 mutex_unlock(&dev->struct_mutex);
3881         }
3882 }
3883
3884 /* Program iCLKIP clock to the desired frequency */
3885 static void lpt_program_iclkip(struct drm_crtc *crtc)
3886 {
3887         struct drm_device *dev = crtc->dev;
3888         struct drm_i915_private *dev_priv = dev->dev_private;
3889         int clock = to_intel_crtc(crtc)->config->base.adjusted_mode.crtc_clock;
3890         u32 divsel, phaseinc, auxdiv, phasedir = 0;
3891         u32 temp;
3892
3893         mutex_lock(&dev_priv->sb_lock);
3894
3895         /* It is necessary to ungate the pixclk gate prior to programming
3896          * the divisors, and gate it back when it is done.
3897          */
3898         I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
3899
3900         /* Disable SSCCTL */
3901         intel_sbi_write(dev_priv, SBI_SSCCTL6,
3902                         intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK) |
3903                                 SBI_SSCCTL_DISABLE,
3904                         SBI_ICLK);
3905
3906         /* 20MHz is a corner case which is out of range for the 7-bit divisor */
3907         if (clock == 20000) {
3908                 auxdiv = 1;
3909                 divsel = 0x41;
3910                 phaseinc = 0x20;
3911         } else {
3912                 /* The iCLK virtual clock root frequency is in MHz,
3913                  * but the adjusted_mode->crtc_clock in in KHz. To get the
3914                  * divisors, it is necessary to divide one by another, so we
3915                  * convert the virtual clock precision to KHz here for higher
3916                  * precision.
3917                  */
3918                 u32 iclk_virtual_root_freq = 172800 * 1000;
3919                 u32 iclk_pi_range = 64;
3920                 u32 desired_divisor, msb_divisor_value, pi_value;
3921
3922                 desired_divisor = (iclk_virtual_root_freq / clock);
3923                 msb_divisor_value = desired_divisor / iclk_pi_range;
3924                 pi_value = desired_divisor % iclk_pi_range;
3925
3926                 auxdiv = 0;
3927                 divsel = msb_divisor_value - 2;
3928                 phaseinc = pi_value;
3929         }
3930
3931         /* This should not happen with any sane values */
3932         WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
3933                 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
3934         WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) &
3935                 ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
3936
3937         DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
3938                         clock,
3939                         auxdiv,
3940                         divsel,
3941                         phasedir,
3942                         phaseinc);
3943
3944         /* Program SSCDIVINTPHASE6 */
3945         temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
3946         temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
3947         temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
3948         temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
3949         temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
3950         temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
3951         temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
3952         intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK);
3953
3954         /* Program SSCAUXDIV */
3955         temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
3956         temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
3957         temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
3958         intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK);
3959
3960         /* Enable modulator and associated divider */
3961         temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
3962         temp &= ~SBI_SSCCTL_DISABLE;
3963         intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
3964
3965         /* Wait for initialization time */
3966         udelay(24);
3967
3968         I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
3969
3970         mutex_unlock(&dev_priv->sb_lock);
3971 }
3972
3973 static void ironlake_pch_transcoder_set_timings(struct intel_crtc *crtc,
3974                                                 enum pipe pch_transcoder)
3975 {
3976         struct drm_device *dev = crtc->base.dev;
3977         struct drm_i915_private *dev_priv = dev->dev_private;
3978         enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
3979
3980         I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder),
3981                    I915_READ(HTOTAL(cpu_transcoder)));
3982         I915_WRITE(PCH_TRANS_HBLANK(pch_transcoder),
3983                    I915_READ(HBLANK(cpu_transcoder)));
3984         I915_WRITE(PCH_TRANS_HSYNC(pch_transcoder),
3985                    I915_READ(HSYNC(cpu_transcoder)));
3986
3987         I915_WRITE(PCH_TRANS_VTOTAL(pch_transcoder),
3988                    I915_READ(VTOTAL(cpu_transcoder)));
3989         I915_WRITE(PCH_TRANS_VBLANK(pch_transcoder),
3990                    I915_READ(VBLANK(cpu_transcoder)));
3991         I915_WRITE(PCH_TRANS_VSYNC(pch_transcoder),
3992                    I915_READ(VSYNC(cpu_transcoder)));
3993         I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder),
3994                    I915_READ(VSYNCSHIFT(cpu_transcoder)));
3995 }
3996
3997 static void cpt_set_fdi_bc_bifurcation(struct drm_device *dev, bool enable)
3998 {
3999         struct drm_i915_private *dev_priv = dev->dev_private;
4000         uint32_t temp;
4001
4002         temp = I915_READ(SOUTH_CHICKEN1);
4003         if (!!(temp & FDI_BC_BIFURCATION_SELECT) == enable)
4004                 return;
4005
4006         WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
4007         WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
4008
4009         temp &= ~FDI_BC_BIFURCATION_SELECT;
4010         if (enable)
4011                 temp |= FDI_BC_BIFURCATION_SELECT;
4012
4013         DRM_DEBUG_KMS("%sabling fdi C rx\n", enable ? "en" : "dis");
4014         I915_WRITE(SOUTH_CHICKEN1, temp);
4015         POSTING_READ(SOUTH_CHICKEN1);
4016 }
4017
4018 static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc *intel_crtc)
4019 {
4020         struct drm_device *dev = intel_crtc->base.dev;
4021
4022         switch (intel_crtc->pipe) {
4023         case PIPE_A:
4024                 break;
4025         case PIPE_B:
4026                 if (intel_crtc->config->fdi_lanes > 2)
4027                         cpt_set_fdi_bc_bifurcation(dev, false);
4028                 else
4029                         cpt_set_fdi_bc_bifurcation(dev, true);
4030
4031                 break;
4032         case PIPE_C:
4033                 cpt_set_fdi_bc_bifurcation(dev, true);
4034
4035                 break;
4036         default:
4037                 BUG();
4038         }
4039 }
4040
4041 /*
4042  * Enable PCH resources required for PCH ports:
4043  *   - PCH PLLs
4044  *   - FDI training & RX/TX
4045  *   - update transcoder timings
4046  *   - DP transcoding bits
4047  *   - transcoder
4048  */
4049 static void ironlake_pch_enable(struct drm_crtc *crtc)
4050 {
4051         struct drm_device *dev = crtc->dev;
4052         struct drm_i915_private *dev_priv = dev->dev_private;
4053         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4054         int pipe = intel_crtc->pipe;
4055         u32 reg, temp;
4056
4057         assert_pch_transcoder_disabled(dev_priv, pipe);
4058
4059         if (IS_IVYBRIDGE(dev))
4060                 ivybridge_update_fdi_bc_bifurcation(intel_crtc);
4061
4062         /* Write the TU size bits before fdi link training, so that error
4063          * detection works. */
4064         I915_WRITE(FDI_RX_TUSIZE1(pipe),
4065                    I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
4066
4067         /* For PCH output, training FDI link */
4068         dev_priv->display.fdi_link_train(crtc);
4069
4070         /* We need to program the right clock selection before writing the pixel
4071          * mutliplier into the DPLL. */
4072         if (HAS_PCH_CPT(dev)) {
4073                 u32 sel;
4074
4075                 temp = I915_READ(PCH_DPLL_SEL);
4076                 temp |= TRANS_DPLL_ENABLE(pipe);
4077                 sel = TRANS_DPLLB_SEL(pipe);
4078                 if (intel_crtc->config->shared_dpll == DPLL_ID_PCH_PLL_B)
4079                         temp |= sel;
4080                 else
4081                         temp &= ~sel;
4082                 I915_WRITE(PCH_DPLL_SEL, temp);
4083         }
4084
4085         /* XXX: pch pll's can be enabled any time before we enable the PCH
4086          * transcoder, and we actually should do this to not upset any PCH
4087          * transcoder that already use the clock when we share it.
4088          *
4089          * Note that enable_shared_dpll tries to do the right thing, but
4090          * get_shared_dpll unconditionally resets the pll - we need that to have
4091          * the right LVDS enable sequence. */
4092         intel_enable_shared_dpll(intel_crtc);
4093
4094         /* set transcoder timing, panel must allow it */
4095         assert_panel_unlocked(dev_priv, pipe);
4096         ironlake_pch_transcoder_set_timings(intel_crtc, pipe);
4097
4098         intel_fdi_normal_train(crtc);
4099
4100         /* For PCH DP, enable TRANS_DP_CTL */
4101         if (HAS_PCH_CPT(dev) && intel_crtc->config->has_dp_encoder) {
4102                 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5;
4103                 reg = TRANS_DP_CTL(pipe);
4104                 temp = I915_READ(reg);
4105                 temp &= ~(TRANS_DP_PORT_SEL_MASK |
4106                           TRANS_DP_SYNC_MASK |
4107                           TRANS_DP_BPC_MASK);
4108                 temp |= TRANS_DP_OUTPUT_ENABLE;
4109                 temp |= bpc << 9; /* same format but at 11:9 */
4110
4111                 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
4112                         temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
4113                 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
4114                         temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
4115
4116                 switch (intel_trans_dp_port_sel(crtc)) {
4117                 case PCH_DP_B:
4118                         temp |= TRANS_DP_PORT_SEL_B;
4119                         break;
4120                 case PCH_DP_C:
4121                         temp |= TRANS_DP_PORT_SEL_C;
4122                         break;
4123                 case PCH_DP_D:
4124                         temp |= TRANS_DP_PORT_SEL_D;
4125                         break;
4126                 default:
4127                         BUG();
4128                 }
4129
4130                 I915_WRITE(reg, temp);
4131         }
4132
4133         ironlake_enable_pch_transcoder(dev_priv, pipe);
4134 }
4135
4136 static void lpt_pch_enable(struct drm_crtc *crtc)
4137 {
4138         struct drm_device *dev = crtc->dev;
4139         struct drm_i915_private *dev_priv = dev->dev_private;
4140         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4141         enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
4142
4143         assert_pch_transcoder_disabled(dev_priv, TRANSCODER_A);
4144
4145         lpt_program_iclkip(crtc);
4146
4147         /* Set transcoder timing. */
4148         ironlake_pch_transcoder_set_timings(intel_crtc, PIPE_A);
4149
4150         lpt_enable_pch_transcoder(dev_priv, cpu_transcoder);
4151 }
4152
4153 struct intel_shared_dpll *intel_get_shared_dpll(struct intel_crtc *crtc,
4154                                                 struct intel_crtc_state *crtc_state)
4155 {
4156         struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
4157         struct intel_shared_dpll *pll;
4158         struct intel_shared_dpll_config *shared_dpll;
4159         enum intel_dpll_id i;
4160
4161         shared_dpll = intel_atomic_get_shared_dpll_state(crtc_state->base.state);
4162
4163         if (HAS_PCH_IBX(dev_priv->dev)) {
4164                 /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */
4165                 i = (enum intel_dpll_id) crtc->pipe;
4166                 pll = &dev_priv->shared_dplls[i];
4167
4168                 DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n",
4169                               crtc->base.base.id, pll->name);
4170
4171                 WARN_ON(shared_dpll[i].crtc_mask);
4172
4173                 goto found;
4174         }
4175
4176         if (IS_BROXTON(dev_priv->dev)) {
4177                 /* PLL is attached to port in bxt */
4178                 struct intel_encoder *encoder;
4179                 struct intel_digital_port *intel_dig_port;
4180
4181                 encoder = intel_ddi_get_crtc_new_encoder(crtc_state);
4182                 if (WARN_ON(!encoder))
4183                         return NULL;
4184
4185                 intel_dig_port = enc_to_dig_port(&encoder->base);
4186                 /* 1:1 mapping between ports and PLLs */
4187                 i = (enum intel_dpll_id)intel_dig_port->port;
4188                 pll = &dev_priv->shared_dplls[i];
4189                 DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n",
4190                         crtc->base.base.id, pll->name);
4191                 WARN_ON(shared_dpll[i].crtc_mask);
4192
4193                 goto found;
4194         }
4195
4196         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
4197                 pll = &dev_priv->shared_dplls[i];
4198
4199                 /* Only want to check enabled timings first */
4200                 if (shared_dpll[i].crtc_mask == 0)
4201                         continue;
4202
4203                 if (memcmp(&crtc_state->dpll_hw_state,
4204                            &shared_dpll[i].hw_state,
4205                            sizeof(crtc_state->dpll_hw_state)) == 0) {
4206                         DRM_DEBUG_KMS("CRTC:%d sharing existing %s (crtc mask 0x%08x, ative %d)\n",
4207                                       crtc->base.base.id, pll->name,
4208                                       shared_dpll[i].crtc_mask,
4209                                       pll->active);
4210                         goto found;
4211                 }
4212         }
4213
4214         /* Ok no matching timings, maybe there's a free one? */
4215         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
4216                 pll = &dev_priv->shared_dplls[i];
4217                 if (shared_dpll[i].crtc_mask == 0) {
4218                         DRM_DEBUG_KMS("CRTC:%d allocated %s\n",
4219                                       crtc->base.base.id, pll->name);
4220                         goto found;
4221                 }
4222         }
4223
4224         return NULL;
4225
4226 found:
4227         if (shared_dpll[i].crtc_mask == 0)
4228                 shared_dpll[i].hw_state =
4229                         crtc_state->dpll_hw_state;
4230
4231         crtc_state->shared_dpll = i;
4232         DRM_DEBUG_DRIVER("using %s for pipe %c\n", pll->name,
4233                          pipe_name(crtc->pipe));
4234
4235         shared_dpll[i].crtc_mask |= 1 << crtc->pipe;
4236
4237         return pll;
4238 }
4239
4240 static void intel_shared_dpll_commit(struct drm_atomic_state *state)
4241 {
4242         struct drm_i915_private *dev_priv = to_i915(state->dev);
4243         struct intel_shared_dpll_config *shared_dpll;
4244         struct intel_shared_dpll *pll;
4245         enum intel_dpll_id i;
4246
4247         if (!to_intel_atomic_state(state)->dpll_set)
4248                 return;
4249
4250         shared_dpll = to_intel_atomic_state(state)->shared_dpll;
4251         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
4252                 pll = &dev_priv->shared_dplls[i];
4253                 pll->config = shared_dpll[i];
4254         }
4255 }
4256
4257 static void cpt_verify_modeset(struct drm_device *dev, int pipe)
4258 {
4259         struct drm_i915_private *dev_priv = dev->dev_private;
4260         int dslreg = PIPEDSL(pipe);
4261         u32 temp;
4262
4263         temp = I915_READ(dslreg);
4264         udelay(500);
4265         if (wait_for(I915_READ(dslreg) != temp, 5)) {
4266                 if (wait_for(I915_READ(dslreg) != temp, 5))
4267                         DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe));
4268         }
4269 }
4270
4271 static int
4272 skl_update_scaler(struct intel_crtc_state *crtc_state, bool force_detach,
4273                   unsigned scaler_user, int *scaler_id, unsigned int rotation,
4274                   int src_w, int src_h, int dst_w, int dst_h)
4275 {
4276         struct intel_crtc_scaler_state *scaler_state =
4277                 &crtc_state->scaler_state;
4278         struct intel_crtc *intel_crtc =
4279                 to_intel_crtc(crtc_state->base.crtc);
4280         int need_scaling;
4281
4282         need_scaling = intel_rotation_90_or_270(rotation) ?
4283                 (src_h != dst_w || src_w != dst_h):
4284                 (src_w != dst_w || src_h != dst_h);
4285
4286         /*
4287          * if plane is being disabled or scaler is no more required or force detach
4288          *  - free scaler binded to this plane/crtc
4289          *  - in order to do this, update crtc->scaler_usage
4290          *
4291          * Here scaler state in crtc_state is set free so that
4292          * scaler can be assigned to other user. Actual register
4293          * update to free the scaler is done in plane/panel-fit programming.
4294          * For this purpose crtc/plane_state->scaler_id isn't reset here.
4295          */
4296         if (force_detach || !need_scaling) {
4297                 if (*scaler_id >= 0) {
4298                         scaler_state->scaler_users &= ~(1 << scaler_user);
4299                         scaler_state->scalers[*scaler_id].in_use = 0;
4300
4301                         DRM_DEBUG_KMS("scaler_user index %u.%u: "
4302                                 "Staged freeing scaler id %d scaler_users = 0x%x\n",
4303                                 intel_crtc->pipe, scaler_user, *scaler_id,
4304                                 scaler_state->scaler_users);
4305                         *scaler_id = -1;
4306                 }
4307                 return 0;
4308         }
4309
4310         /* range checks */
4311         if (src_w < SKL_MIN_SRC_W || src_h < SKL_MIN_SRC_H ||
4312                 dst_w < SKL_MIN_DST_W || dst_h < SKL_MIN_DST_H ||
4313
4314                 src_w > SKL_MAX_SRC_W || src_h > SKL_MAX_SRC_H ||
4315                 dst_w > SKL_MAX_DST_W || dst_h > SKL_MAX_DST_H) {
4316                 DRM_DEBUG_KMS("scaler_user index %u.%u: src %ux%u dst %ux%u "
4317                         "size is out of scaler range\n",
4318                         intel_crtc->pipe, scaler_user, src_w, src_h, dst_w, dst_h);
4319                 return -EINVAL;
4320         }
4321
4322         /* mark this plane as a scaler user in crtc_state */
4323         scaler_state->scaler_users |= (1 << scaler_user);
4324         DRM_DEBUG_KMS("scaler_user index %u.%u: "
4325                 "staged scaling request for %ux%u->%ux%u scaler_users = 0x%x\n",
4326                 intel_crtc->pipe, scaler_user, src_w, src_h, dst_w, dst_h,
4327                 scaler_state->scaler_users);
4328
4329         return 0;
4330 }
4331
4332 /**
4333  * skl_update_scaler_crtc - Stages update to scaler state for a given crtc.
4334  *
4335  * @state: crtc's scaler state
4336  * @force_detach: whether to forcibly disable scaler
4337  *
4338  * Return
4339  *     0 - scaler_usage updated successfully
4340  *    error - requested scaling cannot be supported or other error condition
4341  */
4342 int skl_update_scaler_crtc(struct intel_crtc_state *state, int force_detach)
4343 {
4344         struct intel_crtc *intel_crtc = to_intel_crtc(state->base.crtc);
4345         struct drm_display_mode *adjusted_mode =
4346                 &state->base.adjusted_mode;
4347
4348         DRM_DEBUG_KMS("Updating scaler for [CRTC:%i] scaler_user index %u.%u\n",
4349                       intel_crtc->base.base.id, intel_crtc->pipe, SKL_CRTC_INDEX);
4350
4351         return skl_update_scaler(state, force_detach, SKL_CRTC_INDEX,
4352                 &state->scaler_state.scaler_id, DRM_ROTATE_0,
4353                 state->pipe_src_w, state->pipe_src_h,
4354                 adjusted_mode->hdisplay, adjusted_mode->hdisplay);
4355 }
4356
4357 /**
4358  * skl_update_scaler_plane - Stages update to scaler state for a given plane.
4359  *
4360  * @state: crtc's scaler state
4361  * @plane_state: atomic plane state to update
4362  *
4363  * Return
4364  *     0 - scaler_usage updated successfully
4365  *    error - requested scaling cannot be supported or other error condition
4366  */
4367 static int skl_update_scaler_plane(struct intel_crtc_state *crtc_state,
4368                                    struct intel_plane_state *plane_state)
4369 {
4370
4371         struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
4372         struct intel_plane *intel_plane =
4373                 to_intel_plane(plane_state->base.plane);
4374         struct drm_framebuffer *fb = plane_state->base.fb;
4375         int ret;
4376
4377         bool force_detach = !fb || !plane_state->visible;
4378
4379         DRM_DEBUG_KMS("Updating scaler for [PLANE:%d] scaler_user index %u.%u\n",
4380                       intel_plane->base.base.id, intel_crtc->pipe,
4381                       drm_plane_index(&intel_plane->base));
4382
4383         ret = skl_update_scaler(crtc_state, force_detach,
4384                                 drm_plane_index(&intel_plane->base),
4385                                 &plane_state->scaler_id,
4386                                 plane_state->base.rotation,
4387                                 drm_rect_width(&plane_state->src) >> 16,
4388                                 drm_rect_height(&plane_state->src) >> 16,
4389                                 drm_rect_width(&plane_state->dst),
4390                                 drm_rect_height(&plane_state->dst));
4391
4392         if (ret || plane_state->scaler_id < 0)
4393                 return ret;
4394
4395         /* check colorkey */
4396         if (plane_state->ckey.flags != I915_SET_COLORKEY_NONE) {
4397                 DRM_DEBUG_KMS("[PLANE:%d] scaling with color key not allowed",
4398                               intel_plane->base.base.id);
4399                 return -EINVAL;
4400         }
4401
4402         /* Check src format */
4403         switch (fb->pixel_format) {
4404         case DRM_FORMAT_RGB565:
4405         case DRM_FORMAT_XBGR8888:
4406         case DRM_FORMAT_XRGB8888:
4407         case DRM_FORMAT_ABGR8888:
4408         case DRM_FORMAT_ARGB8888:
4409         case DRM_FORMAT_XRGB2101010:
4410         case DRM_FORMAT_XBGR2101010:
4411         case DRM_FORMAT_YUYV:
4412         case DRM_FORMAT_YVYU:
4413         case DRM_FORMAT_UYVY:
4414         case DRM_FORMAT_VYUY:
4415                 break;
4416         default:
4417                 DRM_DEBUG_KMS("[PLANE:%d] FB:%d unsupported scaling format 0x%x\n",
4418                         intel_plane->base.base.id, fb->base.id, fb->pixel_format);
4419                 return -EINVAL;
4420         }
4421
4422         return 0;
4423 }
4424
4425 static void skylake_pfit_update(struct intel_crtc *crtc, int enable)
4426 {
4427         struct drm_device *dev = crtc->base.dev;
4428         struct drm_i915_private *dev_priv = dev->dev_private;
4429         int pipe = crtc->pipe;
4430         struct intel_crtc_scaler_state *scaler_state =
4431                 &crtc->config->scaler_state;
4432
4433         DRM_DEBUG_KMS("for crtc_state = %p\n", crtc->config);
4434
4435         /* To update pfit, first update scaler state */
4436         skl_update_scaler_crtc(crtc->config, !enable);
4437         intel_atomic_setup_scalers(crtc->base.dev, crtc, crtc->config);
4438         skl_detach_scalers(crtc);
4439         if (!enable)
4440                 return;
4441
4442         if (crtc->config->pch_pfit.enabled) {
4443                 int id;
4444
4445                 if (WARN_ON(crtc->config->scaler_state.scaler_id < 0)) {
4446                         DRM_ERROR("Requesting pfit without getting a scaler first\n");
4447                         return;
4448                 }
4449
4450                 id = scaler_state->scaler_id;
4451                 I915_WRITE(SKL_PS_CTRL(pipe, id), PS_SCALER_EN |
4452                         PS_FILTER_MEDIUM | scaler_state->scalers[id].mode);
4453                 I915_WRITE(SKL_PS_WIN_POS(pipe, id), crtc->config->pch_pfit.pos);
4454                 I915_WRITE(SKL_PS_WIN_SZ(pipe, id), crtc->config->pch_pfit.size);
4455
4456                 DRM_DEBUG_KMS("for crtc_state = %p scaler_id = %d\n", crtc->config, id);
4457         }
4458 }
4459
4460 static void ironlake_pfit_enable(struct intel_crtc *crtc)
4461 {
4462         struct drm_device *dev = crtc->base.dev;
4463         struct drm_i915_private *dev_priv = dev->dev_private;
4464         int pipe = crtc->pipe;
4465
4466         if (crtc->config->pch_pfit.enabled) {
4467                 /* Force use of hard-coded filter coefficients
4468                  * as some pre-programmed values are broken,
4469                  * e.g. x201.
4470                  */
4471                 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
4472                         I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 |
4473                                                  PF_PIPE_SEL_IVB(pipe));
4474                 else
4475                         I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
4476                 I915_WRITE(PF_WIN_POS(pipe), crtc->config->pch_pfit.pos);
4477                 I915_WRITE(PF_WIN_SZ(pipe), crtc->config->pch_pfit.size);
4478         }
4479 }
4480
4481 void hsw_enable_ips(struct intel_crtc *crtc)
4482 {
4483         struct drm_device *dev = crtc->base.dev;
4484         struct drm_i915_private *dev_priv = dev->dev_private;
4485
4486         if (!crtc->config->ips_enabled)
4487                 return;
4488
4489         /* We can only enable IPS after we enable a plane and wait for a vblank */
4490         intel_wait_for_vblank(dev, crtc->pipe);
4491
4492         assert_plane_enabled(dev_priv, crtc->plane);
4493         if (IS_BROADWELL(dev)) {
4494                 mutex_lock(&dev_priv->rps.hw_lock);
4495                 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0xc0000000));
4496                 mutex_unlock(&dev_priv->rps.hw_lock);
4497                 /* Quoting Art Runyan: "its not safe to expect any particular
4498                  * value in IPS_CTL bit 31 after enabling IPS through the
4499                  * mailbox." Moreover, the mailbox may return a bogus state,
4500                  * so we need to just enable it and continue on.
4501                  */
4502         } else {
4503                 I915_WRITE(IPS_CTL, IPS_ENABLE);
4504                 /* The bit only becomes 1 in the next vblank, so this wait here
4505                  * is essentially intel_wait_for_vblank. If we don't have this
4506                  * and don't wait for vblanks until the end of crtc_enable, then
4507                  * the HW state readout code will complain that the expected
4508                  * IPS_CTL value is not the one we read. */
4509                 if (wait_for(I915_READ_NOTRACE(IPS_CTL) & IPS_ENABLE, 50))
4510                         DRM_ERROR("Timed out waiting for IPS enable\n");
4511         }
4512 }
4513
4514 void hsw_disable_ips(struct intel_crtc *crtc)
4515 {
4516         struct drm_device *dev = crtc->base.dev;
4517         struct drm_i915_private *dev_priv = dev->dev_private;
4518
4519         if (!crtc->config->ips_enabled)
4520                 return;
4521
4522         assert_plane_enabled(dev_priv, crtc->plane);
4523         if (IS_BROADWELL(dev)) {
4524                 mutex_lock(&dev_priv->rps.hw_lock);
4525                 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0));
4526                 mutex_unlock(&dev_priv->rps.hw_lock);
4527                 /* wait for pcode to finish disabling IPS, which may take up to 42ms */
4528                 if (wait_for((I915_READ(IPS_CTL) & IPS_ENABLE) == 0, 42))
4529                         DRM_ERROR("Timed out waiting for IPS disable\n");
4530         } else {
4531                 I915_WRITE(IPS_CTL, 0);
4532                 POSTING_READ(IPS_CTL);
4533         }
4534
4535         /* We need to wait for a vblank before we can disable the plane. */
4536         intel_wait_for_vblank(dev, crtc->pipe);
4537 }
4538
4539 /** Loads the palette/gamma unit for the CRTC with the prepared values */
4540 static void intel_crtc_load_lut(struct drm_crtc *crtc)
4541 {
4542         struct drm_device *dev = crtc->dev;
4543         struct drm_i915_private *dev_priv = dev->dev_private;
4544         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4545         enum pipe pipe = intel_crtc->pipe;
4546         int palreg = PALETTE(pipe);
4547         int i;
4548         bool reenable_ips = false;
4549
4550         /* The clocks have to be on to load the palette. */
4551         if (!crtc->state->active)
4552                 return;
4553
4554         if (HAS_GMCH_DISPLAY(dev_priv->dev)) {
4555                 if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI))
4556                         assert_dsi_pll_enabled(dev_priv);
4557                 else
4558                         assert_pll_enabled(dev_priv, pipe);
4559         }
4560
4561         /* use legacy palette for Ironlake */
4562         if (!HAS_GMCH_DISPLAY(dev))
4563                 palreg = LGC_PALETTE(pipe);
4564
4565         /* Workaround : Do not read or write the pipe palette/gamma data while
4566          * GAMMA_MODE is configured for split gamma and IPS_CTL has IPS enabled.
4567          */
4568         if (IS_HASWELL(dev) && intel_crtc->config->ips_enabled &&
4569             ((I915_READ(GAMMA_MODE(pipe)) & GAMMA_MODE_MODE_MASK) ==
4570              GAMMA_MODE_MODE_SPLIT)) {
4571                 hsw_disable_ips(intel_crtc);
4572                 reenable_ips = true;
4573         }
4574
4575         for (i = 0; i < 256; i++) {
4576                 I915_WRITE(palreg + 4 * i,
4577                            (intel_crtc->lut_r[i] << 16) |
4578                            (intel_crtc->lut_g[i] << 8) |
4579                            intel_crtc->lut_b[i]);
4580         }
4581
4582         if (reenable_ips)
4583                 hsw_enable_ips(intel_crtc);
4584 }
4585
4586 static void intel_crtc_dpms_overlay_disable(struct intel_crtc *intel_crtc)
4587 {
4588         if (intel_crtc->overlay) {
4589                 struct drm_device *dev = intel_crtc->base.dev;
4590                 struct drm_i915_private *dev_priv = dev->dev_private;
4591
4592                 mutex_lock(&dev->struct_mutex);
4593                 dev_priv->mm.interruptible = false;
4594                 (void) intel_overlay_switch_off(intel_crtc->overlay);
4595                 dev_priv->mm.interruptible = true;
4596                 mutex_unlock(&dev->struct_mutex);
4597         }
4598
4599         /* Let userspace switch the overlay on again. In most cases userspace
4600          * has to recompute where to put it anyway.
4601          */
4602 }
4603
4604 /**
4605  * intel_post_enable_primary - Perform operations after enabling primary plane
4606  * @crtc: the CRTC whose primary plane was just enabled
4607  *
4608  * Performs potentially sleeping operations that must be done after the primary
4609  * plane is enabled, such as updating FBC and IPS.  Note that this may be
4610  * called due to an explicit primary plane update, or due to an implicit
4611  * re-enable that is caused when a sprite plane is updated to no longer
4612  * completely hide the primary plane.
4613  */
4614 static void
4615 intel_post_enable_primary(struct drm_crtc *crtc)
4616 {
4617         struct drm_device *dev = crtc->dev;
4618         struct drm_i915_private *dev_priv = dev->dev_private;
4619         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4620         int pipe = intel_crtc->pipe;
4621
4622         /*
4623          * BDW signals flip done immediately if the plane
4624          * is disabled, even if the plane enable is already
4625          * armed to occur at the next vblank :(
4626          */
4627         if (IS_BROADWELL(dev))
4628                 intel_wait_for_vblank(dev, pipe);
4629
4630         /*
4631          * FIXME IPS should be fine as long as one plane is
4632          * enabled, but in practice it seems to have problems
4633          * when going from primary only to sprite only and vice
4634          * versa.
4635          */
4636         hsw_enable_ips(intel_crtc);
4637
4638         /*
4639          * Gen2 reports pipe underruns whenever all planes are disabled.
4640          * So don't enable underrun reporting before at least some planes
4641          * are enabled.
4642          * FIXME: Need to fix the logic to work when we turn off all planes
4643          * but leave the pipe running.
4644          */
4645         if (IS_GEN2(dev))
4646                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4647
4648         /* Underruns don't raise interrupts, so check manually. */
4649         if (HAS_GMCH_DISPLAY(dev))
4650                 i9xx_check_fifo_underruns(dev_priv);
4651 }
4652
4653 /**
4654  * intel_pre_disable_primary - Perform operations before disabling primary plane
4655  * @crtc: the CRTC whose primary plane is to be disabled
4656  *
4657  * Performs potentially sleeping operations that must be done before the
4658  * primary plane is disabled, such as updating FBC and IPS.  Note that this may
4659  * be called due to an explicit primary plane update, or due to an implicit
4660  * disable that is caused when a sprite plane completely hides the primary
4661  * plane.
4662  */
4663 static void
4664 intel_pre_disable_primary(struct drm_crtc *crtc)
4665 {
4666         struct drm_device *dev = crtc->dev;
4667         struct drm_i915_private *dev_priv = dev->dev_private;
4668         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4669         int pipe = intel_crtc->pipe;
4670
4671         /*
4672          * Gen2 reports pipe underruns whenever all planes are disabled.
4673          * So diasble underrun reporting before all the planes get disabled.
4674          * FIXME: Need to fix the logic to work when we turn off all planes
4675          * but leave the pipe running.
4676          */
4677         if (IS_GEN2(dev))
4678                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
4679
4680         /*
4681          * Vblank time updates from the shadow to live plane control register
4682          * are blocked if the memory self-refresh mode is active at that
4683          * moment. So to make sure the plane gets truly disabled, disable
4684          * first the self-refresh mode. The self-refresh enable bit in turn
4685          * will be checked/applied by the HW only at the next frame start
4686          * event which is after the vblank start event, so we need to have a
4687          * wait-for-vblank between disabling the plane and the pipe.
4688          */
4689         if (HAS_GMCH_DISPLAY(dev))
4690                 intel_set_memory_cxsr(dev_priv, false);
4691
4692         /*
4693          * FIXME IPS should be fine as long as one plane is
4694          * enabled, but in practice it seems to have problems
4695          * when going from primary only to sprite only and vice
4696          * versa.
4697          */
4698         hsw_disable_ips(intel_crtc);
4699 }
4700
4701 static void intel_post_plane_update(struct intel_crtc *crtc)
4702 {
4703         struct intel_crtc_atomic_commit *atomic = &crtc->atomic;
4704         struct drm_device *dev = crtc->base.dev;
4705         struct drm_plane *plane;
4706
4707         if (atomic->wait_vblank)
4708                 intel_wait_for_vblank(dev, crtc->pipe);
4709
4710         intel_frontbuffer_flip(dev, atomic->fb_bits);
4711
4712         if (atomic->update_fbc) {
4713                 mutex_lock(&dev->struct_mutex);
4714                 intel_fbc_update(dev);
4715                 mutex_unlock(&dev->struct_mutex);
4716         }
4717
4718         if (atomic->post_enable_primary)
4719                 intel_post_enable_primary(&crtc->base);
4720
4721         drm_for_each_plane_mask(plane, dev, atomic->update_sprite_watermarks)
4722                 intel_update_sprite_watermarks(plane, &crtc->base,
4723                                                0, 0, 0, false, false);
4724
4725         memset(atomic, 0, sizeof(*atomic));
4726 }
4727
4728 static void intel_pre_plane_update(struct intel_crtc *crtc)
4729 {
4730         struct drm_device *dev = crtc->base.dev;
4731         struct drm_i915_private *dev_priv = dev->dev_private;
4732         struct intel_crtc_atomic_commit *atomic = &crtc->atomic;
4733         struct drm_plane *p;
4734
4735         /* Track fb's for any planes being disabled */
4736
4737         drm_for_each_plane_mask(p, dev, atomic->disabled_planes) {
4738                 struct intel_plane *plane = to_intel_plane(p);
4739                 unsigned fb_bits = 0;
4740
4741                 switch (p->type) {
4742                 case DRM_PLANE_TYPE_PRIMARY:
4743                         fb_bits = INTEL_FRONTBUFFER_PRIMARY(plane->pipe);
4744                         break;
4745                 case DRM_PLANE_TYPE_CURSOR:
4746                         fb_bits = INTEL_FRONTBUFFER_CURSOR(plane->pipe);
4747                         break;
4748                 case DRM_PLANE_TYPE_OVERLAY:
4749                         fb_bits = INTEL_FRONTBUFFER_SPRITE(plane->pipe);
4750                         break;
4751                 }
4752
4753                 mutex_lock(&dev->struct_mutex);
4754                 i915_gem_track_fb(intel_fb_obj(plane->base.fb), NULL, fb_bits);
4755                 mutex_unlock(&dev->struct_mutex);
4756         }
4757
4758         if (atomic->wait_for_flips)
4759                 intel_crtc_wait_for_pending_flips(&crtc->base);
4760
4761         if (atomic->disable_fbc &&
4762             dev_priv->fbc.crtc == crtc) {
4763                 mutex_lock(&dev->struct_mutex);
4764                 if (dev_priv->fbc.crtc == crtc)
4765                         intel_fbc_disable(dev);
4766                 mutex_unlock(&dev->struct_mutex);
4767         }
4768
4769         if (atomic->pre_disable_primary)
4770                 intel_pre_disable_primary(&crtc->base);
4771 }
4772
4773 static void intel_crtc_disable_planes(struct drm_crtc *crtc, unsigned plane_mask)
4774 {
4775         struct drm_device *dev = crtc->dev;
4776         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4777         struct drm_plane *p;
4778         int pipe = intel_crtc->pipe;
4779
4780         intel_crtc_dpms_overlay_disable(intel_crtc);
4781
4782         drm_for_each_plane_mask(p, dev, plane_mask)
4783                 to_intel_plane(p)->disable_plane(p, crtc);
4784
4785         /*
4786          * FIXME: Once we grow proper nuclear flip support out of this we need
4787          * to compute the mask of flip planes precisely. For the time being
4788          * consider this a flip to a NULL plane.
4789          */
4790         intel_frontbuffer_flip(dev, INTEL_FRONTBUFFER_ALL_MASK(pipe));
4791 }
4792
4793 static void ironlake_crtc_enable(struct drm_crtc *crtc)
4794 {
4795         struct drm_device *dev = crtc->dev;
4796         struct drm_i915_private *dev_priv = dev->dev_private;
4797         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4798         struct intel_encoder *encoder;
4799         int pipe = intel_crtc->pipe;
4800
4801         if (WARN_ON(intel_crtc->active))
4802                 return;
4803
4804         if (intel_crtc->config->has_pch_encoder)
4805                 intel_prepare_shared_dpll(intel_crtc);
4806
4807         if (intel_crtc->config->has_dp_encoder)
4808                 intel_dp_set_m_n(intel_crtc, M1_N1);
4809
4810         intel_set_pipe_timings(intel_crtc);
4811
4812         if (intel_crtc->config->has_pch_encoder) {
4813                 intel_cpu_transcoder_set_m_n(intel_crtc,
4814                                      &intel_crtc->config->fdi_m_n, NULL);
4815         }
4816
4817         ironlake_set_pipeconf(crtc);
4818
4819         intel_crtc->active = true;
4820
4821         intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4822         intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true);
4823
4824         for_each_encoder_on_crtc(dev, crtc, encoder)
4825                 if (encoder->pre_enable)
4826                         encoder->pre_enable(encoder);
4827
4828         if (intel_crtc->config->has_pch_encoder) {
4829                 /* Note: FDI PLL enabling _must_ be done before we enable the
4830                  * cpu pipes, hence this is separate from all the other fdi/pch
4831                  * enabling. */
4832                 ironlake_fdi_pll_enable(intel_crtc);
4833         } else {
4834                 assert_fdi_tx_disabled(dev_priv, pipe);
4835                 assert_fdi_rx_disabled(dev_priv, pipe);
4836         }
4837
4838         ironlake_pfit_enable(intel_crtc);
4839
4840         /*
4841          * On ILK+ LUT must be loaded before the pipe is running but with
4842          * clocks enabled
4843          */
4844         intel_crtc_load_lut(crtc);
4845
4846         intel_update_watermarks(crtc);
4847         intel_enable_pipe(intel_crtc);
4848
4849         if (intel_crtc->config->has_pch_encoder)
4850                 ironlake_pch_enable(crtc);
4851
4852         assert_vblank_disabled(crtc);
4853         drm_crtc_vblank_on(crtc);
4854
4855         for_each_encoder_on_crtc(dev, crtc, encoder)
4856                 encoder->enable(encoder);
4857
4858         if (HAS_PCH_CPT(dev))
4859                 cpt_verify_modeset(dev, intel_crtc->pipe);
4860 }
4861
4862 /* IPS only exists on ULT machines and is tied to pipe A. */
4863 static bool hsw_crtc_supports_ips(struct intel_crtc *crtc)
4864 {
4865         return HAS_IPS(crtc->base.dev) && crtc->pipe == PIPE_A;
4866 }
4867
4868 static void haswell_crtc_enable(struct drm_crtc *crtc)
4869 {
4870         struct drm_device *dev = crtc->dev;
4871         struct drm_i915_private *dev_priv = dev->dev_private;
4872         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4873         struct intel_encoder *encoder;
4874         int pipe = intel_crtc->pipe, hsw_workaround_pipe;
4875         struct intel_crtc_state *pipe_config =
4876                 to_intel_crtc_state(crtc->state);
4877
4878         if (WARN_ON(intel_crtc->active))
4879                 return;
4880
4881         if (intel_crtc_to_shared_dpll(intel_crtc))
4882                 intel_enable_shared_dpll(intel_crtc);
4883
4884         if (intel_crtc->config->has_dp_encoder)
4885                 intel_dp_set_m_n(intel_crtc, M1_N1);
4886
4887         intel_set_pipe_timings(intel_crtc);
4888
4889         if (intel_crtc->config->cpu_transcoder != TRANSCODER_EDP) {
4890                 I915_WRITE(PIPE_MULT(intel_crtc->config->cpu_transcoder),
4891                            intel_crtc->config->pixel_multiplier - 1);
4892         }
4893
4894         if (intel_crtc->config->has_pch_encoder) {
4895                 intel_cpu_transcoder_set_m_n(intel_crtc,
4896                                      &intel_crtc->config->fdi_m_n, NULL);
4897         }
4898
4899         haswell_set_pipeconf(crtc);
4900
4901         intel_set_pipe_csc(crtc);
4902
4903         intel_crtc->active = true;
4904
4905         intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4906         for_each_encoder_on_crtc(dev, crtc, encoder)
4907                 if (encoder->pre_enable)
4908                         encoder->pre_enable(encoder);
4909
4910         if (intel_crtc->config->has_pch_encoder) {
4911                 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
4912                                                       true);
4913                 dev_priv->display.fdi_link_train(crtc);
4914         }
4915
4916         intel_ddi_enable_pipe_clock(intel_crtc);
4917
4918         if (INTEL_INFO(dev)->gen == 9)
4919                 skylake_pfit_update(intel_crtc, 1);
4920         else if (INTEL_INFO(dev)->gen < 9)
4921                 ironlake_pfit_enable(intel_crtc);
4922         else
4923                 MISSING_CASE(INTEL_INFO(dev)->gen);
4924
4925         /*
4926          * On ILK+ LUT must be loaded before the pipe is running but with
4927          * clocks enabled
4928          */
4929         intel_crtc_load_lut(crtc);
4930
4931         intel_ddi_set_pipe_settings(crtc);
4932         intel_ddi_enable_transcoder_func(crtc);
4933
4934         intel_update_watermarks(crtc);
4935         intel_enable_pipe(intel_crtc);
4936
4937         if (intel_crtc->config->has_pch_encoder)
4938                 lpt_pch_enable(crtc);
4939
4940         if (intel_crtc->config->dp_encoder_is_mst)
4941                 intel_ddi_set_vc_payload_alloc(crtc, true);
4942
4943         assert_vblank_disabled(crtc);
4944         drm_crtc_vblank_on(crtc);
4945
4946         for_each_encoder_on_crtc(dev, crtc, encoder) {
4947                 encoder->enable(encoder);
4948                 intel_opregion_notify_encoder(encoder, true);
4949         }
4950
4951         /* If we change the relative order between pipe/planes enabling, we need
4952          * to change the workaround. */
4953         hsw_workaround_pipe = pipe_config->hsw_workaround_pipe;
4954         if (IS_HASWELL(dev) && hsw_workaround_pipe != INVALID_PIPE) {
4955                 intel_wait_for_vblank(dev, hsw_workaround_pipe);
4956                 intel_wait_for_vblank(dev, hsw_workaround_pipe);
4957         }
4958 }
4959
4960 static void ironlake_pfit_disable(struct intel_crtc *crtc)
4961 {
4962         struct drm_device *dev = crtc->base.dev;
4963         struct drm_i915_private *dev_priv = dev->dev_private;
4964         int pipe = crtc->pipe;
4965
4966         /* To avoid upsetting the power well on haswell only disable the pfit if
4967          * it's in use. The hw state code will make sure we get this right. */
4968         if (crtc->config->pch_pfit.enabled) {
4969                 I915_WRITE(PF_CTL(pipe), 0);
4970                 I915_WRITE(PF_WIN_POS(pipe), 0);
4971                 I915_WRITE(PF_WIN_SZ(pipe), 0);
4972         }
4973 }
4974
4975 static void ironlake_crtc_disable(struct drm_crtc *crtc)
4976 {
4977         struct drm_device *dev = crtc->dev;
4978         struct drm_i915_private *dev_priv = dev->dev_private;
4979         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4980         struct intel_encoder *encoder;
4981         int pipe = intel_crtc->pipe;
4982         u32 reg, temp;
4983
4984         for_each_encoder_on_crtc(dev, crtc, encoder)
4985                 encoder->disable(encoder);
4986
4987         drm_crtc_vblank_off(crtc);
4988         assert_vblank_disabled(crtc);
4989
4990         if (intel_crtc->config->has_pch_encoder)
4991                 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false);
4992
4993         intel_disable_pipe(intel_crtc);
4994
4995         ironlake_pfit_disable(intel_crtc);
4996
4997         if (intel_crtc->config->has_pch_encoder)
4998                 ironlake_fdi_disable(crtc);
4999
5000         for_each_encoder_on_crtc(dev, crtc, encoder)
5001                 if (encoder->post_disable)
5002                         encoder->post_disable(encoder);
5003
5004         if (intel_crtc->config->has_pch_encoder) {
5005                 ironlake_disable_pch_transcoder(dev_priv, pipe);
5006
5007                 if (HAS_PCH_CPT(dev)) {
5008                         /* disable TRANS_DP_CTL */
5009                         reg = TRANS_DP_CTL(pipe);
5010                         temp = I915_READ(reg);
5011                         temp &= ~(TRANS_DP_OUTPUT_ENABLE |
5012                                   TRANS_DP_PORT_SEL_MASK);
5013                         temp |= TRANS_DP_PORT_SEL_NONE;
5014                         I915_WRITE(reg, temp);
5015
5016                         /* disable DPLL_SEL */
5017                         temp = I915_READ(PCH_DPLL_SEL);
5018                         temp &= ~(TRANS_DPLL_ENABLE(pipe) | TRANS_DPLLB_SEL(pipe));
5019                         I915_WRITE(PCH_DPLL_SEL, temp);
5020                 }
5021
5022                 ironlake_fdi_pll_disable(intel_crtc);
5023         }
5024 }
5025
5026 static void haswell_crtc_disable(struct drm_crtc *crtc)
5027 {
5028         struct drm_device *dev = crtc->dev;
5029         struct drm_i915_private *dev_priv = dev->dev_private;
5030         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5031         struct intel_encoder *encoder;
5032         enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
5033
5034         for_each_encoder_on_crtc(dev, crtc, encoder) {
5035                 intel_opregion_notify_encoder(encoder, false);
5036                 encoder->disable(encoder);
5037         }
5038
5039         drm_crtc_vblank_off(crtc);
5040         assert_vblank_disabled(crtc);
5041
5042         if (intel_crtc->config->has_pch_encoder)
5043                 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
5044                                                       false);
5045         intel_disable_pipe(intel_crtc);
5046
5047         if (intel_crtc->config->dp_encoder_is_mst)
5048                 intel_ddi_set_vc_payload_alloc(crtc, false);
5049
5050         intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder);
5051
5052         if (INTEL_INFO(dev)->gen == 9)
5053                 skylake_pfit_update(intel_crtc, 0);
5054         else if (INTEL_INFO(dev)->gen < 9)
5055                 ironlake_pfit_disable(intel_crtc);
5056         else
5057                 MISSING_CASE(INTEL_INFO(dev)->gen);
5058
5059         intel_ddi_disable_pipe_clock(intel_crtc);
5060
5061         if (intel_crtc->config->has_pch_encoder) {
5062                 lpt_disable_pch_transcoder(dev_priv);
5063                 intel_ddi_fdi_disable(crtc);
5064         }
5065
5066         for_each_encoder_on_crtc(dev, crtc, encoder)
5067                 if (encoder->post_disable)
5068                         encoder->post_disable(encoder);
5069 }
5070
5071 static void i9xx_pfit_enable(struct intel_crtc *crtc)
5072 {
5073         struct drm_device *dev = crtc->base.dev;
5074         struct drm_i915_private *dev_priv = dev->dev_private;
5075         struct intel_crtc_state *pipe_config = crtc->config;
5076
5077         if (!pipe_config->gmch_pfit.control)
5078                 return;
5079
5080         /*
5081          * The panel fitter should only be adjusted whilst the pipe is disabled,
5082          * according to register description and PRM.
5083          */
5084         WARN_ON(I915_READ(PFIT_CONTROL) & PFIT_ENABLE);
5085         assert_pipe_disabled(dev_priv, crtc->pipe);
5086
5087         I915_WRITE(PFIT_PGM_RATIOS, pipe_config->gmch_pfit.pgm_ratios);
5088         I915_WRITE(PFIT_CONTROL, pipe_config->gmch_pfit.control);
5089
5090         /* Border color in case we don't scale up to the full screen. Black by
5091          * default, change to something else for debugging. */
5092         I915_WRITE(BCLRPAT(crtc->pipe), 0);
5093 }
5094
5095 static enum intel_display_power_domain port_to_power_domain(enum port port)
5096 {
5097         switch (port) {
5098         case PORT_A:
5099                 return POWER_DOMAIN_PORT_DDI_A_4_LANES;
5100         case PORT_B:
5101                 return POWER_DOMAIN_PORT_DDI_B_4_LANES;
5102         case PORT_C:
5103                 return POWER_DOMAIN_PORT_DDI_C_4_LANES;
5104         case PORT_D:
5105                 return POWER_DOMAIN_PORT_DDI_D_4_LANES;
5106         default:
5107                 WARN_ON_ONCE(1);
5108                 return POWER_DOMAIN_PORT_OTHER;
5109         }
5110 }
5111
5112 #define for_each_power_domain(domain, mask)                             \
5113         for ((domain) = 0; (domain) < POWER_DOMAIN_NUM; (domain)++)     \
5114                 if ((1 << (domain)) & (mask))
5115
5116 enum intel_display_power_domain
5117 intel_display_port_power_domain(struct intel_encoder *intel_encoder)
5118 {
5119         struct drm_device *dev = intel_encoder->base.dev;
5120         struct intel_digital_port *intel_dig_port;
5121
5122         switch (intel_encoder->type) {
5123         case INTEL_OUTPUT_UNKNOWN:
5124                 /* Only DDI platforms should ever use this output type */
5125                 WARN_ON_ONCE(!HAS_DDI(dev));
5126         case INTEL_OUTPUT_DISPLAYPORT:
5127         case INTEL_OUTPUT_HDMI:
5128         case INTEL_OUTPUT_EDP:
5129                 intel_dig_port = enc_to_dig_port(&intel_encoder->base);
5130                 return port_to_power_domain(intel_dig_port->port);
5131         case INTEL_OUTPUT_DP_MST:
5132                 intel_dig_port = enc_to_mst(&intel_encoder->base)->primary;
5133                 return port_to_power_domain(intel_dig_port->port);
5134         case INTEL_OUTPUT_ANALOG:
5135                 return POWER_DOMAIN_PORT_CRT;
5136         case INTEL_OUTPUT_DSI:
5137                 return POWER_DOMAIN_PORT_DSI;
5138         default:
5139                 return POWER_DOMAIN_PORT_OTHER;
5140         }
5141 }
5142
5143 static unsigned long get_crtc_power_domains(struct drm_crtc *crtc)
5144 {
5145         struct drm_device *dev = crtc->dev;
5146         struct intel_encoder *intel_encoder;
5147         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5148         enum pipe pipe = intel_crtc->pipe;
5149         unsigned long mask;
5150         enum transcoder transcoder;
5151
5152         transcoder = intel_pipe_to_cpu_transcoder(dev->dev_private, pipe);
5153
5154         mask = BIT(POWER_DOMAIN_PIPE(pipe));
5155         mask |= BIT(POWER_DOMAIN_TRANSCODER(transcoder));
5156         if (intel_crtc->config->pch_pfit.enabled ||
5157             intel_crtc->config->pch_pfit.force_thru)
5158                 mask |= BIT(POWER_DOMAIN_PIPE_PANEL_FITTER(pipe));
5159
5160         for_each_encoder_on_crtc(dev, crtc, intel_encoder)
5161                 mask |= BIT(intel_display_port_power_domain(intel_encoder));
5162
5163         return mask;
5164 }
5165
5166 static void modeset_update_crtc_power_domains(struct drm_atomic_state *state)
5167 {
5168         struct drm_device *dev = state->dev;
5169         struct drm_i915_private *dev_priv = dev->dev_private;
5170         unsigned long pipe_domains[I915_MAX_PIPES] = { 0, };
5171         struct intel_crtc *crtc;
5172
5173         /*
5174          * First get all needed power domains, then put all unneeded, to avoid
5175          * any unnecessary toggling of the power wells.
5176          */
5177         for_each_intel_crtc(dev, crtc) {
5178                 enum intel_display_power_domain domain;
5179
5180                 if (!crtc->base.state->enable)
5181                         continue;
5182
5183                 pipe_domains[crtc->pipe] = get_crtc_power_domains(&crtc->base);
5184
5185                 for_each_power_domain(domain, pipe_domains[crtc->pipe])
5186                         intel_display_power_get(dev_priv, domain);
5187         }
5188
5189         if (dev_priv->display.modeset_commit_cdclk) {
5190                 unsigned int cdclk = to_intel_atomic_state(state)->cdclk;
5191
5192                 if (cdclk != dev_priv->cdclk_freq &&
5193                     !WARN_ON(!state->allow_modeset))
5194                         dev_priv->display.modeset_commit_cdclk(state);
5195         }
5196
5197         for_each_intel_crtc(dev, crtc) {
5198                 enum intel_display_power_domain domain;
5199
5200                 for_each_power_domain(domain, crtc->enabled_power_domains)
5201                         intel_display_power_put(dev_priv, domain);
5202
5203                 crtc->enabled_power_domains = pipe_domains[crtc->pipe];
5204         }
5205
5206         intel_display_set_init_power(dev_priv, false);
5207 }
5208
5209 static void intel_update_max_cdclk(struct drm_device *dev)
5210 {
5211         struct drm_i915_private *dev_priv = dev->dev_private;
5212
5213         if (IS_SKYLAKE(dev)) {
5214                 u32 limit = I915_READ(SKL_DFSM) & SKL_DFSM_CDCLK_LIMIT_MASK;
5215
5216                 if (limit == SKL_DFSM_CDCLK_LIMIT_675)
5217                         dev_priv->max_cdclk_freq = 675000;
5218                 else if (limit == SKL_DFSM_CDCLK_LIMIT_540)
5219                         dev_priv->max_cdclk_freq = 540000;
5220                 else if (limit == SKL_DFSM_CDCLK_LIMIT_450)
5221                         dev_priv->max_cdclk_freq = 450000;
5222                 else
5223                         dev_priv->max_cdclk_freq = 337500;
5224         } else if (IS_BROADWELL(dev))  {
5225                 /*
5226                  * FIXME with extra cooling we can allow
5227                  * 540 MHz for ULX and 675 Mhz for ULT.
5228                  * How can we know if extra cooling is
5229                  * available? PCI ID, VTB, something else?
5230                  */
5231                 if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT)
5232                         dev_priv->max_cdclk_freq = 450000;
5233                 else if (IS_BDW_ULX(dev))
5234                         dev_priv->max_cdclk_freq = 450000;
5235                 else if (IS_BDW_ULT(dev))
5236                         dev_priv->max_cdclk_freq = 540000;
5237                 else
5238                         dev_priv->max_cdclk_freq = 675000;
5239         } else if (IS_CHERRYVIEW(dev)) {
5240                 dev_priv->max_cdclk_freq = 320000;
5241         } else if (IS_VALLEYVIEW(dev)) {
5242                 dev_priv->max_cdclk_freq = 400000;
5243         } else {
5244                 /* otherwise assume cdclk is fixed */
5245                 dev_priv->max_cdclk_freq = dev_priv->cdclk_freq;
5246         }
5247
5248         DRM_DEBUG_DRIVER("Max CD clock rate: %d kHz\n",
5249                          dev_priv->max_cdclk_freq);
5250 }
5251
5252 static void intel_update_cdclk(struct drm_device *dev)
5253 {
5254         struct drm_i915_private *dev_priv = dev->dev_private;
5255
5256         dev_priv->cdclk_freq = dev_priv->display.get_display_clock_speed(dev);
5257         DRM_DEBUG_DRIVER("Current CD clock rate: %d kHz\n",
5258                          dev_priv->cdclk_freq);
5259
5260         /*
5261          * Program the gmbus_freq based on the cdclk frequency.
5262          * BSpec erroneously claims we should aim for 4MHz, but
5263          * in fact 1MHz is the correct frequency.
5264          */
5265         if (IS_VALLEYVIEW(dev)) {
5266                 /*
5267                  * Program the gmbus_freq based on the cdclk frequency.
5268                  * BSpec erroneously claims we should aim for 4MHz, but
5269                  * in fact 1MHz is the correct frequency.
5270                  */
5271                 I915_WRITE(GMBUSFREQ_VLV, DIV_ROUND_UP(dev_priv->cdclk_freq, 1000));
5272         }
5273
5274         if (dev_priv->max_cdclk_freq == 0)
5275                 intel_update_max_cdclk(dev);
5276 }
5277
5278 static void broxton_set_cdclk(struct drm_device *dev, int frequency)
5279 {
5280         struct drm_i915_private *dev_priv = dev->dev_private;
5281         uint32_t divider;
5282         uint32_t ratio;
5283         uint32_t current_freq;
5284         int ret;
5285
5286         /* frequency = 19.2MHz * ratio / 2 / div{1,1.5,2,4} */
5287         switch (frequency) {
5288         case 144000:
5289                 divider = BXT_CDCLK_CD2X_DIV_SEL_4;
5290                 ratio = BXT_DE_PLL_RATIO(60);
5291                 break;
5292         case 288000:
5293                 divider = BXT_CDCLK_CD2X_DIV_SEL_2;
5294                 ratio = BXT_DE_PLL_RATIO(60);
5295                 break;
5296         case 384000:
5297                 divider = BXT_CDCLK_CD2X_DIV_SEL_1_5;
5298                 ratio = BXT_DE_PLL_RATIO(60);
5299                 break;
5300         case 576000:
5301                 divider = BXT_CDCLK_CD2X_DIV_SEL_1;
5302                 ratio = BXT_DE_PLL_RATIO(60);
5303                 break;
5304         case 624000:
5305                 divider = BXT_CDCLK_CD2X_DIV_SEL_1;
5306                 ratio = BXT_DE_PLL_RATIO(65);
5307                 break;
5308         case 19200:
5309                 /*
5310                  * Bypass frequency with DE PLL disabled. Init ratio, divider
5311                  * to suppress GCC warning.
5312                  */
5313                 ratio = 0;
5314                 divider = 0;
5315                 break;
5316         default:
5317                 DRM_ERROR("unsupported CDCLK freq %d", frequency);
5318
5319                 return;
5320         }
5321
5322         mutex_lock(&dev_priv->rps.hw_lock);
5323         /* Inform power controller of upcoming frequency change */
5324         ret = sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ,
5325                                       0x80000000);
5326         mutex_unlock(&dev_priv->rps.hw_lock);
5327
5328         if (ret) {
5329                 DRM_ERROR("PCode CDCLK freq change notify failed (err %d, freq %d)\n",
5330                           ret, frequency);
5331                 return;
5332         }
5333
5334         current_freq = I915_READ(CDCLK_CTL) & CDCLK_FREQ_DECIMAL_MASK;
5335         /* convert from .1 fixpoint MHz with -1MHz offset to kHz */
5336         current_freq = current_freq * 500 + 1000;
5337
5338         /*
5339          * DE PLL has to be disabled when
5340          * - setting to 19.2MHz (bypass, PLL isn't used)
5341          * - before setting to 624MHz (PLL needs toggling)
5342          * - before setting to any frequency from 624MHz (PLL needs toggling)
5343          */
5344         if (frequency == 19200 || frequency == 624000 ||
5345             current_freq == 624000) {
5346                 I915_WRITE(BXT_DE_PLL_ENABLE, ~BXT_DE_PLL_PLL_ENABLE);
5347                 /* Timeout 200us */
5348                 if (wait_for(!(I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_LOCK),
5349                              1))
5350                         DRM_ERROR("timout waiting for DE PLL unlock\n");
5351         }
5352
5353         if (frequency != 19200) {
5354                 uint32_t val;
5355
5356                 val = I915_READ(BXT_DE_PLL_CTL);
5357                 val &= ~BXT_DE_PLL_RATIO_MASK;
5358                 val |= ratio;
5359                 I915_WRITE(BXT_DE_PLL_CTL, val);
5360
5361                 I915_WRITE(BXT_DE_PLL_ENABLE, BXT_DE_PLL_PLL_ENABLE);
5362                 /* Timeout 200us */
5363                 if (wait_for(I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_LOCK, 1))
5364                         DRM_ERROR("timeout waiting for DE PLL lock\n");
5365
5366                 val = I915_READ(CDCLK_CTL);
5367                 val &= ~BXT_CDCLK_CD2X_DIV_SEL_MASK;
5368                 val |= divider;
5369                 /*
5370                  * Disable SSA Precharge when CD clock frequency < 500 MHz,
5371                  * enable otherwise.
5372                  */
5373                 val &= ~BXT_CDCLK_SSA_PRECHARGE_ENABLE;
5374                 if (frequency >= 500000)
5375                         val |= BXT_CDCLK_SSA_PRECHARGE_ENABLE;
5376
5377                 val &= ~CDCLK_FREQ_DECIMAL_MASK;
5378                 /* convert from kHz to .1 fixpoint MHz with -1MHz offset */
5379                 val |= (frequency - 1000) / 500;
5380                 I915_WRITE(CDCLK_CTL, val);
5381         }
5382
5383         mutex_lock(&dev_priv->rps.hw_lock);
5384         ret = sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ,
5385                                       DIV_ROUND_UP(frequency, 25000));
5386         mutex_unlock(&dev_priv->rps.hw_lock);
5387
5388         if (ret) {
5389                 DRM_ERROR("PCode CDCLK freq set failed, (err %d, freq %d)\n",
5390                           ret, frequency);
5391                 return;
5392         }
5393
5394         intel_update_cdclk(dev);
5395 }
5396
5397 void broxton_init_cdclk(struct drm_device *dev)
5398 {
5399         struct drm_i915_private *dev_priv = dev->dev_private;
5400         uint32_t val;
5401
5402         /*
5403          * NDE_RSTWRN_OPT RST PCH Handshake En must always be 0b on BXT
5404          * or else the reset will hang because there is no PCH to respond.
5405          * Move the handshake programming to initialization sequence.
5406          * Previously was left up to BIOS.
5407          */
5408         val = I915_READ(HSW_NDE_RSTWRN_OPT);
5409         val &= ~RESET_PCH_HANDSHAKE_ENABLE;
5410         I915_WRITE(HSW_NDE_RSTWRN_OPT, val);
5411
5412         /* Enable PG1 for cdclk */
5413         intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
5414
5415         /* check if cd clock is enabled */
5416         if (I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_PLL_ENABLE) {
5417                 DRM_DEBUG_KMS("Display already initialized\n");
5418                 return;
5419         }
5420
5421         /*
5422          * FIXME:
5423          * - The initial CDCLK needs to be read from VBT.
5424          *   Need to make this change after VBT has changes for BXT.
5425          * - check if setting the max (or any) cdclk freq is really necessary
5426          *   here, it belongs to modeset time
5427          */
5428         broxton_set_cdclk(dev, 624000);
5429
5430         I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) | DBUF_POWER_REQUEST);
5431         POSTING_READ(DBUF_CTL);
5432
5433         udelay(10);
5434
5435         if (!(I915_READ(DBUF_CTL) & DBUF_POWER_STATE))
5436                 DRM_ERROR("DBuf power enable timeout!\n");
5437 }
5438
5439 void broxton_uninit_cdclk(struct drm_device *dev)
5440 {
5441         struct drm_i915_private *dev_priv = dev->dev_private;
5442
5443         I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) & ~DBUF_POWER_REQUEST);
5444         POSTING_READ(DBUF_CTL);
5445
5446         udelay(10);
5447
5448         if (I915_READ(DBUF_CTL) & DBUF_POWER_STATE)
5449                 DRM_ERROR("DBuf power disable timeout!\n");
5450
5451         /* Set minimum (bypass) frequency, in effect turning off the DE PLL */
5452         broxton_set_cdclk(dev, 19200);
5453
5454         intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS);
5455 }
5456
5457 static const struct skl_cdclk_entry {
5458         unsigned int freq;
5459         unsigned int vco;
5460 } skl_cdclk_frequencies[] = {
5461         { .freq = 308570, .vco = 8640 },
5462         { .freq = 337500, .vco = 8100 },
5463         { .freq = 432000, .vco = 8640 },
5464         { .freq = 450000, .vco = 8100 },
5465         { .freq = 540000, .vco = 8100 },
5466         { .freq = 617140, .vco = 8640 },
5467         { .freq = 675000, .vco = 8100 },
5468 };
5469
5470 static unsigned int skl_cdclk_decimal(unsigned int freq)
5471 {
5472         return (freq - 1000) / 500;
5473 }
5474
5475 static unsigned int skl_cdclk_get_vco(unsigned int freq)
5476 {
5477         unsigned int i;
5478
5479         for (i = 0; i < ARRAY_SIZE(skl_cdclk_frequencies); i++) {
5480                 const struct skl_cdclk_entry *e = &skl_cdclk_frequencies[i];
5481
5482                 if (e->freq == freq)
5483                         return e->vco;
5484         }
5485
5486         return 8100;
5487 }
5488
5489 static void
5490 skl_dpll0_enable(struct drm_i915_private *dev_priv, unsigned int required_vco)
5491 {
5492         unsigned int min_freq;
5493         u32 val;
5494
5495         /* select the minimum CDCLK before enabling DPLL 0 */
5496         val = I915_READ(CDCLK_CTL);
5497         val &= ~CDCLK_FREQ_SEL_MASK | ~CDCLK_FREQ_DECIMAL_MASK;
5498         val |= CDCLK_FREQ_337_308;
5499
5500         if (required_vco == 8640)
5501                 min_freq = 308570;
5502         else
5503                 min_freq = 337500;
5504
5505         val = CDCLK_FREQ_337_308 | skl_cdclk_decimal(min_freq);
5506
5507         I915_WRITE(CDCLK_CTL, val);
5508         POSTING_READ(CDCLK_CTL);
5509
5510         /*
5511          * We always enable DPLL0 with the lowest link rate possible, but still
5512          * taking into account the VCO required to operate the eDP panel at the
5513          * desired frequency. The usual DP link rates operate with a VCO of
5514          * 8100 while the eDP 1.4 alternate link rates need a VCO of 8640.
5515          * The modeset code is responsible for the selection of the exact link
5516          * rate later on, with the constraint of choosing a frequency that
5517          * works with required_vco.
5518          */
5519         val = I915_READ(DPLL_CTRL1);
5520
5521         val &= ~(DPLL_CTRL1_HDMI_MODE(SKL_DPLL0) | DPLL_CTRL1_SSC(SKL_DPLL0) |
5522                  DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0));
5523         val |= DPLL_CTRL1_OVERRIDE(SKL_DPLL0);
5524         if (required_vco == 8640)
5525                 val |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1080,
5526                                             SKL_DPLL0);
5527         else
5528                 val |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_810,
5529                                             SKL_DPLL0);
5530
5531         I915_WRITE(DPLL_CTRL1, val);
5532         POSTING_READ(DPLL_CTRL1);
5533
5534         I915_WRITE(LCPLL1_CTL, I915_READ(LCPLL1_CTL) | LCPLL_PLL_ENABLE);
5535
5536         if (wait_for(I915_READ(LCPLL1_CTL) & LCPLL_PLL_LOCK, 5))
5537                 DRM_ERROR("DPLL0 not locked\n");
5538 }
5539
5540 static bool skl_cdclk_pcu_ready(struct drm_i915_private *dev_priv)
5541 {
5542         int ret;
5543         u32 val;
5544
5545         /* inform PCU we want to change CDCLK */
5546         val = SKL_CDCLK_PREPARE_FOR_CHANGE;
5547         mutex_lock(&dev_priv->rps.hw_lock);
5548         ret = sandybridge_pcode_read(dev_priv, SKL_PCODE_CDCLK_CONTROL, &val);
5549         mutex_unlock(&dev_priv->rps.hw_lock);
5550
5551         return ret == 0 && (val & SKL_CDCLK_READY_FOR_CHANGE);
5552 }
5553
5554 static bool skl_cdclk_wait_for_pcu_ready(struct drm_i915_private *dev_priv)
5555 {
5556         unsigned int i;
5557
5558         for (i = 0; i < 15; i++) {
5559                 if (skl_cdclk_pcu_ready(dev_priv))
5560                         return true;
5561                 udelay(10);
5562         }
5563
5564         return false;
5565 }
5566
5567 static void skl_set_cdclk(struct drm_i915_private *dev_priv, unsigned int freq)
5568 {
5569         struct drm_device *dev = dev_priv->dev;
5570         u32 freq_select, pcu_ack;
5571
5572         DRM_DEBUG_DRIVER("Changing CDCLK to %dKHz\n", freq);
5573
5574         if (!skl_cdclk_wait_for_pcu_ready(dev_priv)) {
5575                 DRM_ERROR("failed to inform PCU about cdclk change\n");
5576                 return;
5577         }
5578
5579         /* set CDCLK_CTL */
5580         switch(freq) {
5581         case 450000:
5582         case 432000:
5583                 freq_select = CDCLK_FREQ_450_432;
5584                 pcu_ack = 1;
5585                 break;
5586         case 540000:
5587                 freq_select = CDCLK_FREQ_540;
5588                 pcu_ack = 2;
5589                 break;
5590         case 308570:
5591         case 337500:
5592         default:
5593                 freq_select = CDCLK_FREQ_337_308;
5594                 pcu_ack = 0;
5595                 break;
5596         case 617140:
5597         case 675000:
5598                 freq_select = CDCLK_FREQ_675_617;
5599                 pcu_ack = 3;
5600                 break;
5601         }
5602
5603         I915_WRITE(CDCLK_CTL, freq_select | skl_cdclk_decimal(freq));
5604         POSTING_READ(CDCLK_CTL);
5605
5606         /* inform PCU of the change */
5607         mutex_lock(&dev_priv->rps.hw_lock);
5608         sandybridge_pcode_write(dev_priv, SKL_PCODE_CDCLK_CONTROL, pcu_ack);
5609         mutex_unlock(&dev_priv->rps.hw_lock);
5610
5611         intel_update_cdclk(dev);
5612 }
5613
5614 void skl_uninit_cdclk(struct drm_i915_private *dev_priv)
5615 {
5616         /* disable DBUF power */
5617         I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) & ~DBUF_POWER_REQUEST);
5618         POSTING_READ(DBUF_CTL);
5619
5620         udelay(10);
5621
5622         if (I915_READ(DBUF_CTL) & DBUF_POWER_STATE)
5623                 DRM_ERROR("DBuf power disable timeout\n");
5624
5625         /* disable DPLL0 */
5626         I915_WRITE(LCPLL1_CTL, I915_READ(LCPLL1_CTL) & ~LCPLL_PLL_ENABLE);
5627         if (wait_for(!(I915_READ(LCPLL1_CTL) & LCPLL_PLL_LOCK), 1))
5628                 DRM_ERROR("Couldn't disable DPLL0\n");
5629
5630         intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS);
5631 }
5632
5633 void skl_init_cdclk(struct drm_i915_private *dev_priv)
5634 {
5635         u32 val;
5636         unsigned int required_vco;
5637
5638         /* enable PCH reset handshake */
5639         val = I915_READ(HSW_NDE_RSTWRN_OPT);
5640         I915_WRITE(HSW_NDE_RSTWRN_OPT, val | RESET_PCH_HANDSHAKE_ENABLE);
5641
5642         /* enable PG1 and Misc I/O */
5643         intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
5644
5645         /* DPLL0 already enabed !? */
5646         if (I915_READ(LCPLL1_CTL) & LCPLL_PLL_ENABLE) {
5647                 DRM_DEBUG_DRIVER("DPLL0 already running\n");
5648                 return;
5649         }
5650
5651         /* enable DPLL0 */
5652         required_vco = skl_cdclk_get_vco(dev_priv->skl_boot_cdclk);
5653         skl_dpll0_enable(dev_priv, required_vco);
5654
5655         /* set CDCLK to the frequency the BIOS chose */
5656         skl_set_cdclk(dev_priv, dev_priv->skl_boot_cdclk);
5657
5658         /* enable DBUF power */
5659         I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) | DBUF_POWER_REQUEST);
5660         POSTING_READ(DBUF_CTL);
5661
5662         udelay(10);
5663
5664         if (!(I915_READ(DBUF_CTL) & DBUF_POWER_STATE))
5665                 DRM_ERROR("DBuf power enable timeout\n");
5666 }
5667
5668 /* returns HPLL frequency in kHz */
5669 static int valleyview_get_vco(struct drm_i915_private *dev_priv)
5670 {
5671         int hpll_freq, vco_freq[] = { 800, 1600, 2000, 2400 };
5672
5673         /* Obtain SKU information */
5674         mutex_lock(&dev_priv->sb_lock);
5675         hpll_freq = vlv_cck_read(dev_priv, CCK_FUSE_REG) &
5676                 CCK_FUSE_HPLL_FREQ_MASK;
5677         mutex_unlock(&dev_priv->sb_lock);
5678
5679         return vco_freq[hpll_freq] * 1000;
5680 }
5681
5682 /* Adjust CDclk dividers to allow high res or save power if possible */
5683 static void valleyview_set_cdclk(struct drm_device *dev, int cdclk)
5684 {
5685         struct drm_i915_private *dev_priv = dev->dev_private;
5686         u32 val, cmd;
5687
5688         WARN_ON(dev_priv->display.get_display_clock_speed(dev)
5689                                         != dev_priv->cdclk_freq);
5690
5691         if (cdclk >= 320000) /* jump to highest voltage for 400MHz too */
5692                 cmd = 2;
5693         else if (cdclk == 266667)
5694                 cmd = 1;
5695         else
5696                 cmd = 0;
5697
5698         mutex_lock(&dev_priv->rps.hw_lock);
5699         val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
5700         val &= ~DSPFREQGUAR_MASK;
5701         val |= (cmd << DSPFREQGUAR_SHIFT);
5702         vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
5703         if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) &
5704                       DSPFREQSTAT_MASK) == (cmd << DSPFREQSTAT_SHIFT),
5705                      50)) {
5706                 DRM_ERROR("timed out waiting for CDclk change\n");
5707         }
5708         mutex_unlock(&dev_priv->rps.hw_lock);
5709
5710         mutex_lock(&dev_priv->sb_lock);
5711
5712         if (cdclk == 400000) {
5713                 u32 divider;
5714
5715                 divider = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, cdclk) - 1;
5716
5717                 /* adjust cdclk divider */
5718                 val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL);
5719                 val &= ~DISPLAY_FREQUENCY_VALUES;
5720                 val |= divider;
5721                 vlv_cck_write(dev_priv, CCK_DISPLAY_CLOCK_CONTROL, val);
5722
5723                 if (wait_for((vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL) &
5724                               DISPLAY_FREQUENCY_STATUS) == (divider << DISPLAY_FREQUENCY_STATUS_SHIFT),
5725                              50))
5726                         DRM_ERROR("timed out waiting for CDclk change\n");
5727         }
5728
5729         /* adjust self-refresh exit latency value */
5730         val = vlv_bunit_read(dev_priv, BUNIT_REG_BISOC);
5731         val &= ~0x7f;
5732
5733         /*
5734          * For high bandwidth configs, we set a higher latency in the bunit
5735          * so that the core display fetch happens in time to avoid underruns.
5736          */
5737         if (cdclk == 400000)
5738                 val |= 4500 / 250; /* 4.5 usec */
5739         else
5740                 val |= 3000 / 250; /* 3.0 usec */
5741         vlv_bunit_write(dev_priv, BUNIT_REG_BISOC, val);
5742
5743         mutex_unlock(&dev_priv->sb_lock);
5744
5745         intel_update_cdclk(dev);
5746 }
5747
5748 static void cherryview_set_cdclk(struct drm_device *dev, int cdclk)
5749 {
5750         struct drm_i915_private *dev_priv = dev->dev_private;
5751         u32 val, cmd;
5752
5753         WARN_ON(dev_priv->display.get_display_clock_speed(dev)
5754                                                 != dev_priv->cdclk_freq);
5755
5756         switch (cdclk) {
5757         case 333333:
5758         case 320000:
5759         case 266667:
5760         case 200000:
5761                 break;
5762         default:
5763                 MISSING_CASE(cdclk);
5764                 return;
5765         }
5766
5767         /*
5768          * Specs are full of misinformation, but testing on actual
5769          * hardware has shown that we just need to write the desired
5770          * CCK divider into the Punit register.
5771          */
5772         cmd = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, cdclk) - 1;
5773
5774         mutex_lock(&dev_priv->rps.hw_lock);
5775         val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
5776         val &= ~DSPFREQGUAR_MASK_CHV;
5777         val |= (cmd << DSPFREQGUAR_SHIFT_CHV);
5778         vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
5779         if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) &
5780                       DSPFREQSTAT_MASK_CHV) == (cmd << DSPFREQSTAT_SHIFT_CHV),
5781                      50)) {
5782                 DRM_ERROR("timed out waiting for CDclk change\n");
5783         }
5784         mutex_unlock(&dev_priv->rps.hw_lock);
5785
5786         intel_update_cdclk(dev);
5787 }
5788
5789 static int valleyview_calc_cdclk(struct drm_i915_private *dev_priv,
5790                                  int max_pixclk)
5791 {
5792         int freq_320 = (dev_priv->hpll_freq <<  1) % 320000 != 0 ? 333333 : 320000;
5793         int limit = IS_CHERRYVIEW(dev_priv) ? 95 : 90;
5794
5795         /*
5796          * Really only a few cases to deal with, as only 4 CDclks are supported:
5797          *   200MHz
5798          *   267MHz
5799          *   320/333MHz (depends on HPLL freq)
5800          *   400MHz (VLV only)
5801          * So we check to see whether we're above 90% (VLV) or 95% (CHV)
5802          * of the lower bin and adjust if needed.
5803          *
5804          * We seem to get an unstable or solid color picture at 200MHz.
5805          * Not sure what's wrong. For now use 200MHz only when all pipes
5806          * are off.
5807          */
5808         if (!IS_CHERRYVIEW(dev_priv) &&
5809             max_pixclk > freq_320*limit/100)
5810                 return 400000;
5811         else if (max_pixclk > 266667*limit/100)
5812                 return freq_320;
5813         else if (max_pixclk > 0)
5814                 return 266667;
5815         else
5816                 return 200000;
5817 }
5818
5819 static int broxton_calc_cdclk(struct drm_i915_private *dev_priv,
5820                               int max_pixclk)
5821 {
5822         /*
5823          * FIXME:
5824          * - remove the guardband, it's not needed on BXT
5825          * - set 19.2MHz bypass frequency if there are no active pipes
5826          */
5827         if (max_pixclk > 576000*9/10)
5828                 return 624000;
5829         else if (max_pixclk > 384000*9/10)
5830                 return 576000;
5831         else if (max_pixclk > 288000*9/10)
5832                 return 384000;
5833         else if (max_pixclk > 144000*9/10)
5834                 return 288000;
5835         else
5836                 return 144000;
5837 }
5838
5839 /* Compute the max pixel clock for new configuration. Uses atomic state if
5840  * that's non-NULL, look at current state otherwise. */
5841 static int intel_mode_max_pixclk(struct drm_device *dev,
5842                                  struct drm_atomic_state *state)
5843 {
5844         struct intel_crtc *intel_crtc;
5845         struct intel_crtc_state *crtc_state;
5846         int max_pixclk = 0;
5847
5848         for_each_intel_crtc(dev, intel_crtc) {
5849                 crtc_state = intel_atomic_get_crtc_state(state, intel_crtc);
5850                 if (IS_ERR(crtc_state))
5851                         return PTR_ERR(crtc_state);
5852
5853                 if (!crtc_state->base.enable)
5854                         continue;
5855
5856                 max_pixclk = max(max_pixclk,
5857                                  crtc_state->base.adjusted_mode.crtc_clock);
5858         }
5859
5860         return max_pixclk;
5861 }
5862
5863 static int valleyview_modeset_calc_cdclk(struct drm_atomic_state *state)
5864 {
5865         struct drm_device *dev = state->dev;
5866         struct drm_i915_private *dev_priv = dev->dev_private;
5867         int max_pixclk = intel_mode_max_pixclk(dev, state);
5868
5869         if (max_pixclk < 0)
5870                 return max_pixclk;
5871
5872         to_intel_atomic_state(state)->cdclk =
5873                 valleyview_calc_cdclk(dev_priv, max_pixclk);
5874
5875         return 0;
5876 }
5877
5878 static int broxton_modeset_calc_cdclk(struct drm_atomic_state *state)
5879 {
5880         struct drm_device *dev = state->dev;
5881         struct drm_i915_private *dev_priv = dev->dev_private;
5882         int max_pixclk = intel_mode_max_pixclk(dev, state);
5883
5884         if (max_pixclk < 0)
5885                 return max_pixclk;
5886
5887         to_intel_atomic_state(state)->cdclk =
5888                 broxton_calc_cdclk(dev_priv, max_pixclk);
5889
5890         return 0;
5891 }
5892
5893 static void vlv_program_pfi_credits(struct drm_i915_private *dev_priv)
5894 {
5895         unsigned int credits, default_credits;
5896
5897         if (IS_CHERRYVIEW(dev_priv))
5898                 default_credits = PFI_CREDIT(12);
5899         else
5900                 default_credits = PFI_CREDIT(8);
5901
5902         if (DIV_ROUND_CLOSEST(dev_priv->cdclk_freq, 1000) >= dev_priv->rps.cz_freq) {
5903                 /* CHV suggested value is 31 or 63 */
5904                 if (IS_CHERRYVIEW(dev_priv))
5905                         credits = PFI_CREDIT_63;
5906                 else
5907                         credits = PFI_CREDIT(15);
5908         } else {
5909                 credits = default_credits;
5910         }
5911
5912         /*
5913          * WA - write default credits before re-programming
5914          * FIXME: should we also set the resend bit here?
5915          */
5916         I915_WRITE(GCI_CONTROL, VGA_FAST_MODE_DISABLE |
5917                    default_credits);
5918
5919         I915_WRITE(GCI_CONTROL, VGA_FAST_MODE_DISABLE |
5920                    credits | PFI_CREDIT_RESEND);
5921
5922         /*
5923          * FIXME is this guaranteed to clear
5924          * immediately or should we poll for it?
5925          */
5926         WARN_ON(I915_READ(GCI_CONTROL) & PFI_CREDIT_RESEND);
5927 }
5928
5929 static void valleyview_modeset_commit_cdclk(struct drm_atomic_state *old_state)
5930 {
5931         struct drm_device *dev = old_state->dev;
5932         unsigned int req_cdclk = to_intel_atomic_state(old_state)->cdclk;
5933         struct drm_i915_private *dev_priv = dev->dev_private;
5934
5935         /*
5936          * FIXME: We can end up here with all power domains off, yet
5937          * with a CDCLK frequency other than the minimum. To account
5938          * for this take the PIPE-A power domain, which covers the HW
5939          * blocks needed for the following programming. This can be
5940          * removed once it's guaranteed that we get here either with
5941          * the minimum CDCLK set, or the required power domains
5942          * enabled.
5943          */
5944         intel_display_power_get(dev_priv, POWER_DOMAIN_PIPE_A);
5945
5946         if (IS_CHERRYVIEW(dev))
5947                 cherryview_set_cdclk(dev, req_cdclk);
5948         else
5949                 valleyview_set_cdclk(dev, req_cdclk);
5950
5951         vlv_program_pfi_credits(dev_priv);
5952
5953         intel_display_power_put(dev_priv, POWER_DOMAIN_PIPE_A);
5954 }
5955
5956 static void valleyview_crtc_enable(struct drm_crtc *crtc)
5957 {
5958         struct drm_device *dev = crtc->dev;
5959         struct drm_i915_private *dev_priv = to_i915(dev);
5960         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5961         struct intel_encoder *encoder;
5962         int pipe = intel_crtc->pipe;
5963         bool is_dsi;
5964
5965         if (WARN_ON(intel_crtc->active))
5966                 return;
5967
5968         is_dsi = intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI);
5969
5970         if (!is_dsi) {
5971                 if (IS_CHERRYVIEW(dev))
5972                         chv_prepare_pll(intel_crtc, intel_crtc->config);
5973                 else
5974                         vlv_prepare_pll(intel_crtc, intel_crtc->config);
5975         }
5976
5977         if (intel_crtc->config->has_dp_encoder)
5978                 intel_dp_set_m_n(intel_crtc, M1_N1);
5979
5980         intel_set_pipe_timings(intel_crtc);
5981
5982         if (IS_CHERRYVIEW(dev) && pipe == PIPE_B) {
5983                 struct drm_i915_private *dev_priv = dev->dev_private;
5984
5985                 I915_WRITE(CHV_BLEND(pipe), CHV_BLEND_LEGACY);
5986                 I915_WRITE(CHV_CANVAS(pipe), 0);
5987         }
5988
5989         i9xx_set_pipeconf(intel_crtc);
5990
5991         intel_crtc->active = true;
5992
5993         intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
5994
5995         for_each_encoder_on_crtc(dev, crtc, encoder)
5996                 if (encoder->pre_pll_enable)
5997                         encoder->pre_pll_enable(encoder);
5998
5999         if (!is_dsi) {
6000                 if (IS_CHERRYVIEW(dev))
6001                         chv_enable_pll(intel_crtc, intel_crtc->config);
6002                 else
6003                         vlv_enable_pll(intel_crtc, intel_crtc->config);
6004         }
6005
6006         for_each_encoder_on_crtc(dev, crtc, encoder)
6007                 if (encoder->pre_enable)
6008                         encoder->pre_enable(encoder);
6009
6010         i9xx_pfit_enable(intel_crtc);
6011
6012         intel_crtc_load_lut(crtc);
6013
6014         intel_update_watermarks(crtc);
6015         intel_enable_pipe(intel_crtc);
6016
6017         assert_vblank_disabled(crtc);
6018         drm_crtc_vblank_on(crtc);
6019
6020         for_each_encoder_on_crtc(dev, crtc, encoder)
6021                 encoder->enable(encoder);
6022 }
6023
6024 static void i9xx_set_pll_dividers(struct intel_crtc *crtc)
6025 {
6026         struct drm_device *dev = crtc->base.dev;
6027         struct drm_i915_private *dev_priv = dev->dev_private;
6028
6029         I915_WRITE(FP0(crtc->pipe), crtc->config->dpll_hw_state.fp0);
6030         I915_WRITE(FP1(crtc->pipe), crtc->config->dpll_hw_state.fp1);
6031 }
6032
6033 static void i9xx_crtc_enable(struct drm_crtc *crtc)
6034 {
6035         struct drm_device *dev = crtc->dev;
6036         struct drm_i915_private *dev_priv = to_i915(dev);
6037         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6038         struct intel_encoder *encoder;
6039         int pipe = intel_crtc->pipe;
6040
6041         if (WARN_ON(intel_crtc->active))
6042                 return;
6043
6044         i9xx_set_pll_dividers(intel_crtc);
6045
6046         if (intel_crtc->config->has_dp_encoder)
6047                 intel_dp_set_m_n(intel_crtc, M1_N1);
6048
6049         intel_set_pipe_timings(intel_crtc);
6050
6051         i9xx_set_pipeconf(intel_crtc);
6052
6053         intel_crtc->active = true;
6054
6055         if (!IS_GEN2(dev))
6056                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
6057
6058         for_each_encoder_on_crtc(dev, crtc, encoder)
6059                 if (encoder->pre_enable)
6060                         encoder->pre_enable(encoder);
6061
6062         i9xx_enable_pll(intel_crtc);
6063
6064         i9xx_pfit_enable(intel_crtc);
6065
6066         intel_crtc_load_lut(crtc);
6067
6068         intel_update_watermarks(crtc);
6069         intel_enable_pipe(intel_crtc);
6070
6071         assert_vblank_disabled(crtc);
6072         drm_crtc_vblank_on(crtc);
6073
6074         for_each_encoder_on_crtc(dev, crtc, encoder)
6075                 encoder->enable(encoder);
6076 }
6077
6078 static void i9xx_pfit_disable(struct intel_crtc *crtc)
6079 {
6080         struct drm_device *dev = crtc->base.dev;
6081         struct drm_i915_private *dev_priv = dev->dev_private;
6082
6083         if (!crtc->config->gmch_pfit.control)
6084                 return;
6085
6086         assert_pipe_disabled(dev_priv, crtc->pipe);
6087
6088         DRM_DEBUG_DRIVER("disabling pfit, current: 0x%08x\n",
6089                          I915_READ(PFIT_CONTROL));
6090         I915_WRITE(PFIT_CONTROL, 0);
6091 }
6092
6093 static void i9xx_crtc_disable(struct drm_crtc *crtc)
6094 {
6095         struct drm_device *dev = crtc->dev;
6096         struct drm_i915_private *dev_priv = dev->dev_private;
6097         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6098         struct intel_encoder *encoder;
6099         int pipe = intel_crtc->pipe;
6100
6101         /*
6102          * On gen2 planes are double buffered but the pipe isn't, so we must
6103          * wait for planes to fully turn off before disabling the pipe.
6104          * We also need to wait on all gmch platforms because of the
6105          * self-refresh mode constraint explained above.
6106          */
6107         intel_wait_for_vblank(dev, pipe);
6108
6109         for_each_encoder_on_crtc(dev, crtc, encoder)
6110                 encoder->disable(encoder);
6111
6112         drm_crtc_vblank_off(crtc);
6113         assert_vblank_disabled(crtc);
6114
6115         intel_disable_pipe(intel_crtc);
6116
6117         i9xx_pfit_disable(intel_crtc);
6118
6119         for_each_encoder_on_crtc(dev, crtc, encoder)
6120                 if (encoder->post_disable)
6121                         encoder->post_disable(encoder);
6122
6123         if (!intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI)) {
6124                 if (IS_CHERRYVIEW(dev))
6125                         chv_disable_pll(dev_priv, pipe);
6126                 else if (IS_VALLEYVIEW(dev))
6127                         vlv_disable_pll(dev_priv, pipe);
6128                 else
6129                         i9xx_disable_pll(intel_crtc);
6130         }
6131
6132         if (!IS_GEN2(dev))
6133                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
6134 }
6135
6136 static void intel_crtc_disable_noatomic(struct drm_crtc *crtc)
6137 {
6138         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6139         struct drm_i915_private *dev_priv = to_i915(crtc->dev);
6140         enum intel_display_power_domain domain;
6141         unsigned long domains;
6142
6143         if (!intel_crtc->active)
6144                 return;
6145
6146         if (to_intel_plane_state(crtc->primary->state)->visible) {
6147                 intel_crtc_wait_for_pending_flips(crtc);
6148                 intel_pre_disable_primary(crtc);
6149         }
6150
6151         intel_crtc_disable_planes(crtc, crtc->state->plane_mask);
6152         dev_priv->display.crtc_disable(crtc);
6153
6154         domains = intel_crtc->enabled_power_domains;
6155         for_each_power_domain(domain, domains)
6156                 intel_display_power_put(dev_priv, domain);
6157         intel_crtc->enabled_power_domains = 0;
6158 }
6159
6160 /*
6161  * turn all crtc's off, but do not adjust state
6162  * This has to be paired with a call to intel_modeset_setup_hw_state.
6163  */
6164 void intel_display_suspend(struct drm_device *dev)
6165 {
6166         struct drm_crtc *crtc;
6167
6168         for_each_crtc(dev, crtc)
6169                 intel_crtc_disable_noatomic(crtc);
6170 }
6171
6172 /* Master function to enable/disable CRTC and corresponding power wells */
6173 int intel_crtc_control(struct drm_crtc *crtc, bool enable)
6174 {
6175         struct drm_device *dev = crtc->dev;
6176         struct drm_mode_config *config = &dev->mode_config;
6177         struct drm_modeset_acquire_ctx *ctx = config->acquire_ctx;
6178         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6179         struct intel_crtc_state *pipe_config;
6180         struct drm_atomic_state *state;
6181         int ret;
6182
6183         if (enable == intel_crtc->active)
6184                 return 0;
6185
6186         if (enable && !crtc->state->enable)
6187                 return 0;
6188
6189         /* this function should be called with drm_modeset_lock_all for now */
6190         if (WARN_ON(!ctx))
6191                 return -EIO;
6192         lockdep_assert_held(&ctx->ww_ctx);
6193
6194         state = drm_atomic_state_alloc(dev);
6195         if (WARN_ON(!state))
6196                 return -ENOMEM;
6197
6198         state->acquire_ctx = ctx;
6199         state->allow_modeset = true;
6200
6201         pipe_config = intel_atomic_get_crtc_state(state, intel_crtc);
6202         if (IS_ERR(pipe_config)) {
6203                 ret = PTR_ERR(pipe_config);
6204                 goto err;
6205         }
6206         pipe_config->base.active = enable;
6207
6208         ret = intel_set_mode(state);
6209         if (!ret)
6210                 return ret;
6211
6212 err:
6213         DRM_ERROR("Updating crtc active failed with %i\n", ret);
6214         drm_atomic_state_free(state);
6215         return ret;
6216 }
6217
6218 /**
6219  * Sets the power management mode of the pipe and plane.
6220  */
6221 void intel_crtc_update_dpms(struct drm_crtc *crtc)
6222 {
6223         struct drm_device *dev = crtc->dev;
6224         struct intel_encoder *intel_encoder;
6225         bool enable = false;
6226
6227         for_each_encoder_on_crtc(dev, crtc, intel_encoder)
6228                 enable |= intel_encoder->connectors_active;
6229
6230         intel_crtc_control(crtc, enable);
6231 }
6232
6233 void intel_encoder_destroy(struct drm_encoder *encoder)
6234 {
6235         struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
6236
6237         drm_encoder_cleanup(encoder);
6238         kfree(intel_encoder);
6239 }
6240
6241 /* Simple dpms helper for encoders with just one connector, no cloning and only
6242  * one kind of off state. It clamps all !ON modes to fully OFF and changes the
6243  * state of the entire output pipe. */
6244 static void intel_encoder_dpms(struct intel_encoder *encoder, int mode)
6245 {
6246         if (mode == DRM_MODE_DPMS_ON) {
6247                 encoder->connectors_active = true;
6248
6249                 intel_crtc_update_dpms(encoder->base.crtc);
6250         } else {
6251                 encoder->connectors_active = false;
6252
6253                 intel_crtc_update_dpms(encoder->base.crtc);
6254         }
6255 }
6256
6257 /* Cross check the actual hw state with our own modeset state tracking (and it's
6258  * internal consistency). */
6259 static void intel_connector_check_state(struct intel_connector *connector)
6260 {
6261         if (connector->get_hw_state(connector)) {
6262                 struct intel_encoder *encoder = connector->encoder;
6263                 struct drm_crtc *crtc;
6264                 bool encoder_enabled;
6265                 enum pipe pipe;
6266
6267                 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
6268                               connector->base.base.id,
6269                               connector->base.name);
6270
6271                 /* there is no real hw state for MST connectors */
6272                 if (connector->mst_port)
6273                         return;
6274
6275                 I915_STATE_WARN(connector->base.dpms == DRM_MODE_DPMS_OFF,
6276                      "wrong connector dpms state\n");
6277                 I915_STATE_WARN(connector->base.encoder != &encoder->base,
6278                      "active connector not linked to encoder\n");
6279
6280                 if (encoder) {
6281                         I915_STATE_WARN(!encoder->connectors_active,
6282                              "encoder->connectors_active not set\n");
6283
6284                         encoder_enabled = encoder->get_hw_state(encoder, &pipe);
6285                         I915_STATE_WARN(!encoder_enabled, "encoder not enabled\n");
6286                         if (I915_STATE_WARN_ON(!encoder->base.crtc))
6287                                 return;
6288
6289                         crtc = encoder->base.crtc;
6290
6291                         I915_STATE_WARN(!crtc->state->enable,
6292                                         "crtc not enabled\n");
6293                         I915_STATE_WARN(!to_intel_crtc(crtc)->active, "crtc not active\n");
6294                         I915_STATE_WARN(pipe != to_intel_crtc(crtc)->pipe,
6295                              "encoder active on the wrong pipe\n");
6296                 }
6297         }
6298 }
6299
6300 int intel_connector_init(struct intel_connector *connector)
6301 {
6302         struct drm_connector_state *connector_state;
6303
6304         connector_state = kzalloc(sizeof *connector_state, GFP_KERNEL);
6305         if (!connector_state)
6306                 return -ENOMEM;
6307
6308         connector->base.state = connector_state;
6309         return 0;
6310 }
6311
6312 struct intel_connector *intel_connector_alloc(void)
6313 {
6314         struct intel_connector *connector;
6315
6316         connector = kzalloc(sizeof *connector, GFP_KERNEL);
6317         if (!connector)
6318                 return NULL;
6319
6320         if (intel_connector_init(connector) < 0) {
6321                 kfree(connector);
6322                 return NULL;
6323         }
6324
6325         return connector;
6326 }
6327
6328 /* Even simpler default implementation, if there's really no special case to
6329  * consider. */
6330 void intel_connector_dpms(struct drm_connector *connector, int mode)
6331 {
6332         /* All the simple cases only support two dpms states. */
6333         if (mode != DRM_MODE_DPMS_ON)
6334                 mode = DRM_MODE_DPMS_OFF;
6335
6336         if (mode == connector->dpms)
6337                 return;
6338
6339         connector->dpms = mode;
6340
6341         /* Only need to change hw state when actually enabled */
6342         if (connector->encoder)
6343                 intel_encoder_dpms(to_intel_encoder(connector->encoder), mode);
6344
6345         intel_modeset_check_state(connector->dev);
6346 }
6347
6348 /* Simple connector->get_hw_state implementation for encoders that support only
6349  * one connector and no cloning and hence the encoder state determines the state
6350  * of the connector. */
6351 bool intel_connector_get_hw_state(struct intel_connector *connector)
6352 {
6353         enum pipe pipe = 0;
6354         struct intel_encoder *encoder = connector->encoder;
6355
6356         return encoder->get_hw_state(encoder, &pipe);
6357 }
6358
6359 static int pipe_required_fdi_lanes(struct intel_crtc_state *crtc_state)
6360 {
6361         if (crtc_state->base.enable && crtc_state->has_pch_encoder)
6362                 return crtc_state->fdi_lanes;
6363
6364         return 0;
6365 }
6366
6367 static int ironlake_check_fdi_lanes(struct drm_device *dev, enum pipe pipe,
6368                                      struct intel_crtc_state *pipe_config)
6369 {
6370         struct drm_atomic_state *state = pipe_config->base.state;
6371         struct intel_crtc *other_crtc;
6372         struct intel_crtc_state *other_crtc_state;
6373
6374         DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n",
6375                       pipe_name(pipe), pipe_config->fdi_lanes);
6376         if (pipe_config->fdi_lanes > 4) {
6377                 DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n",
6378                               pipe_name(pipe), pipe_config->fdi_lanes);
6379                 return -EINVAL;
6380         }
6381
6382         if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
6383                 if (pipe_config->fdi_lanes > 2) {
6384                         DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n",
6385                                       pipe_config->fdi_lanes);
6386                         return -EINVAL;
6387                 } else {
6388                         return 0;
6389                 }
6390         }
6391
6392         if (INTEL_INFO(dev)->num_pipes == 2)
6393                 return 0;
6394
6395         /* Ivybridge 3 pipe is really complicated */
6396         switch (pipe) {
6397         case PIPE_A:
6398                 return 0;
6399         case PIPE_B:
6400                 if (pipe_config->fdi_lanes <= 2)
6401                         return 0;
6402
6403                 other_crtc = to_intel_crtc(intel_get_crtc_for_pipe(dev, PIPE_C));
6404                 other_crtc_state =
6405                         intel_atomic_get_crtc_state(state, other_crtc);
6406                 if (IS_ERR(other_crtc_state))
6407                         return PTR_ERR(other_crtc_state);
6408
6409                 if (pipe_required_fdi_lanes(other_crtc_state) > 0) {
6410                         DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
6411                                       pipe_name(pipe), pipe_config->fdi_lanes);
6412                         return -EINVAL;
6413                 }
6414                 return 0;
6415         case PIPE_C:
6416                 if (pipe_config->fdi_lanes > 2) {
6417                         DRM_DEBUG_KMS("only 2 lanes on pipe %c: required %i lanes\n",
6418                                       pipe_name(pipe), pipe_config->fdi_lanes);
6419                         return -EINVAL;
6420                 }
6421
6422                 other_crtc = to_intel_crtc(intel_get_crtc_for_pipe(dev, PIPE_B));
6423                 other_crtc_state =
6424                         intel_atomic_get_crtc_state(state, other_crtc);
6425                 if (IS_ERR(other_crtc_state))
6426                         return PTR_ERR(other_crtc_state);
6427
6428                 if (pipe_required_fdi_lanes(other_crtc_state) > 2) {
6429                         DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
6430                         return -EINVAL;
6431                 }
6432                 return 0;
6433         default:
6434                 BUG();
6435         }
6436 }
6437
6438 #define RETRY 1
6439 static int ironlake_fdi_compute_config(struct intel_crtc *intel_crtc,
6440                                        struct intel_crtc_state *pipe_config)
6441 {
6442         struct drm_device *dev = intel_crtc->base.dev;
6443         struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
6444         int lane, link_bw, fdi_dotclock, ret;
6445         bool needs_recompute = false;
6446
6447 retry:
6448         /* FDI is a binary signal running at ~2.7GHz, encoding
6449          * each output octet as 10 bits. The actual frequency
6450          * is stored as a divider into a 100MHz clock, and the
6451          * mode pixel clock is stored in units of 1KHz.
6452          * Hence the bw of each lane in terms of the mode signal
6453          * is:
6454          */
6455         link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
6456
6457         fdi_dotclock = adjusted_mode->crtc_clock;
6458
6459         lane = ironlake_get_lanes_required(fdi_dotclock, link_bw,
6460                                            pipe_config->pipe_bpp);
6461
6462         pipe_config->fdi_lanes = lane;
6463
6464         intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock,
6465                                link_bw, &pipe_config->fdi_m_n);
6466
6467         ret = ironlake_check_fdi_lanes(intel_crtc->base.dev,
6468                                        intel_crtc->pipe, pipe_config);
6469         if (ret == -EINVAL && pipe_config->pipe_bpp > 6*3) {
6470                 pipe_config->pipe_bpp -= 2*3;
6471                 DRM_DEBUG_KMS("fdi link bw constraint, reducing pipe bpp to %i\n",
6472                               pipe_config->pipe_bpp);
6473                 needs_recompute = true;
6474                 pipe_config->bw_constrained = true;
6475
6476                 goto retry;
6477         }
6478
6479         if (needs_recompute)
6480                 return RETRY;
6481
6482         return ret;
6483 }
6484
6485 static bool pipe_config_supports_ips(struct drm_i915_private *dev_priv,
6486                                      struct intel_crtc_state *pipe_config)
6487 {
6488         if (pipe_config->pipe_bpp > 24)
6489                 return false;
6490
6491         /* HSW can handle pixel rate up to cdclk? */
6492         if (IS_HASWELL(dev_priv->dev))
6493                 return true;
6494
6495         /*
6496          * We compare against max which means we must take
6497          * the increased cdclk requirement into account when
6498          * calculating the new cdclk.
6499          *
6500          * Should measure whether using a lower cdclk w/o IPS
6501          */
6502         return ilk_pipe_pixel_rate(pipe_config) <=
6503                 dev_priv->max_cdclk_freq * 95 / 100;
6504 }
6505
6506 static void hsw_compute_ips_config(struct intel_crtc *crtc,
6507                                    struct intel_crtc_state *pipe_config)
6508 {
6509         struct drm_device *dev = crtc->base.dev;
6510         struct drm_i915_private *dev_priv = dev->dev_private;
6511
6512         pipe_config->ips_enabled = i915.enable_ips &&
6513                 hsw_crtc_supports_ips(crtc) &&
6514                 pipe_config_supports_ips(dev_priv, pipe_config);
6515 }
6516
6517 static int intel_crtc_compute_config(struct intel_crtc *crtc,
6518                                      struct intel_crtc_state *pipe_config)
6519 {
6520         struct drm_device *dev = crtc->base.dev;
6521         struct drm_i915_private *dev_priv = dev->dev_private;
6522         struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
6523
6524         /* FIXME should check pixel clock limits on all platforms */
6525         if (INTEL_INFO(dev)->gen < 4) {
6526                 int clock_limit = dev_priv->max_cdclk_freq;
6527
6528                 /*
6529                  * Enable pixel doubling when the dot clock
6530                  * is > 90% of the (display) core speed.
6531                  *
6532                  * GDG double wide on either pipe,
6533                  * otherwise pipe A only.
6534                  */
6535                 if ((crtc->pipe == PIPE_A || IS_I915G(dev)) &&
6536                     adjusted_mode->crtc_clock > clock_limit * 9 / 10) {
6537                         clock_limit *= 2;
6538                         pipe_config->double_wide = true;
6539                 }
6540
6541                 if (adjusted_mode->crtc_clock > clock_limit * 9 / 10)
6542                         return -EINVAL;
6543         }
6544
6545         /*
6546          * Pipe horizontal size must be even in:
6547          * - DVO ganged mode
6548          * - LVDS dual channel mode
6549          * - Double wide pipe
6550          */
6551         if ((intel_pipe_will_have_type(pipe_config, INTEL_OUTPUT_LVDS) &&
6552              intel_is_dual_link_lvds(dev)) || pipe_config->double_wide)
6553                 pipe_config->pipe_src_w &= ~1;
6554
6555         /* Cantiga+ cannot handle modes with a hsync front porch of 0.
6556          * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw.
6557          */
6558         if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) &&
6559                 adjusted_mode->hsync_start == adjusted_mode->hdisplay)
6560                 return -EINVAL;
6561
6562         if (HAS_IPS(dev))
6563                 hsw_compute_ips_config(crtc, pipe_config);
6564
6565         if (pipe_config->has_pch_encoder)
6566                 return ironlake_fdi_compute_config(crtc, pipe_config);
6567
6568         return 0;
6569 }
6570
6571 static int skylake_get_display_clock_speed(struct drm_device *dev)
6572 {
6573         struct drm_i915_private *dev_priv = to_i915(dev);
6574         uint32_t lcpll1 = I915_READ(LCPLL1_CTL);
6575         uint32_t cdctl = I915_READ(CDCLK_CTL);
6576         uint32_t linkrate;
6577
6578         if (!(lcpll1 & LCPLL_PLL_ENABLE))
6579                 return 24000; /* 24MHz is the cd freq with NSSC ref */
6580
6581         if ((cdctl & CDCLK_FREQ_SEL_MASK) == CDCLK_FREQ_540)
6582                 return 540000;
6583
6584         linkrate = (I915_READ(DPLL_CTRL1) &
6585                     DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0)) >> 1;
6586
6587         if (linkrate == DPLL_CTRL1_LINK_RATE_2160 ||
6588             linkrate == DPLL_CTRL1_LINK_RATE_1080) {
6589                 /* vco 8640 */
6590                 switch (cdctl & CDCLK_FREQ_SEL_MASK) {
6591                 case CDCLK_FREQ_450_432:
6592                         return 432000;
6593                 case CDCLK_FREQ_337_308:
6594                         return 308570;
6595                 case CDCLK_FREQ_675_617:
6596                         return 617140;
6597                 default:
6598                         WARN(1, "Unknown cd freq selection\n");
6599                 }
6600         } else {
6601                 /* vco 8100 */
6602                 switch (cdctl & CDCLK_FREQ_SEL_MASK) {
6603                 case CDCLK_FREQ_450_432:
6604                         return 450000;
6605                 case CDCLK_FREQ_337_308:
6606                         return 337500;
6607                 case CDCLK_FREQ_675_617:
6608                         return 675000;
6609                 default:
6610                         WARN(1, "Unknown cd freq selection\n");
6611                 }
6612         }
6613
6614         /* error case, do as if DPLL0 isn't enabled */
6615         return 24000;
6616 }
6617
6618 static int broadwell_get_display_clock_speed(struct drm_device *dev)
6619 {
6620         struct drm_i915_private *dev_priv = dev->dev_private;
6621         uint32_t lcpll = I915_READ(LCPLL_CTL);
6622         uint32_t freq = lcpll & LCPLL_CLK_FREQ_MASK;
6623
6624         if (lcpll & LCPLL_CD_SOURCE_FCLK)
6625                 return 800000;
6626         else if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT)
6627                 return 450000;
6628         else if (freq == LCPLL_CLK_FREQ_450)
6629                 return 450000;
6630         else if (freq == LCPLL_CLK_FREQ_54O_BDW)
6631                 return 540000;
6632         else if (freq == LCPLL_CLK_FREQ_337_5_BDW)
6633                 return 337500;
6634         else
6635                 return 675000;
6636 }
6637
6638 static int haswell_get_display_clock_speed(struct drm_device *dev)
6639 {
6640         struct drm_i915_private *dev_priv = dev->dev_private;
6641         uint32_t lcpll = I915_READ(LCPLL_CTL);
6642         uint32_t freq = lcpll & LCPLL_CLK_FREQ_MASK;
6643
6644         if (lcpll & LCPLL_CD_SOURCE_FCLK)
6645                 return 800000;
6646         else if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT)
6647                 return 450000;
6648         else if (freq == LCPLL_CLK_FREQ_450)
6649                 return 450000;
6650         else if (IS_HSW_ULT(dev))
6651                 return 337500;
6652         else
6653                 return 540000;
6654 }
6655
6656 static int valleyview_get_display_clock_speed(struct drm_device *dev)
6657 {
6658         struct drm_i915_private *dev_priv = dev->dev_private;
6659         u32 val;
6660         int divider;
6661
6662         if (dev_priv->hpll_freq == 0)
6663                 dev_priv->hpll_freq = valleyview_get_vco(dev_priv);
6664
6665         mutex_lock(&dev_priv->sb_lock);
6666         val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL);
6667         mutex_unlock(&dev_priv->sb_lock);
6668
6669         divider = val & DISPLAY_FREQUENCY_VALUES;
6670
6671         WARN((val & DISPLAY_FREQUENCY_STATUS) !=
6672              (divider << DISPLAY_FREQUENCY_STATUS_SHIFT),
6673              "cdclk change in progress\n");
6674
6675         return DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, divider + 1);
6676 }
6677
6678 static int ilk_get_display_clock_speed(struct drm_device *dev)
6679 {
6680         return 450000;
6681 }
6682
6683 static int i945_get_display_clock_speed(struct drm_device *dev)
6684 {
6685         return 400000;
6686 }
6687
6688 static int i915_get_display_clock_speed(struct drm_device *dev)
6689 {
6690         return 333333;
6691 }
6692
6693 static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
6694 {
6695         return 200000;
6696 }
6697
6698 static int pnv_get_display_clock_speed(struct drm_device *dev)
6699 {
6700         u16 gcfgc = 0;
6701
6702         pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
6703
6704         switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
6705         case GC_DISPLAY_CLOCK_267_MHZ_PNV:
6706                 return 266667;
6707         case GC_DISPLAY_CLOCK_333_MHZ_PNV:
6708                 return 333333;
6709         case GC_DISPLAY_CLOCK_444_MHZ_PNV:
6710                 return 444444;
6711         case GC_DISPLAY_CLOCK_200_MHZ_PNV:
6712                 return 200000;
6713         default:
6714                 DRM_ERROR("Unknown pnv display core clock 0x%04x\n", gcfgc);
6715         case GC_DISPLAY_CLOCK_133_MHZ_PNV:
6716                 return 133333;
6717         case GC_DISPLAY_CLOCK_167_MHZ_PNV:
6718                 return 166667;
6719         }
6720 }
6721
6722 static int i915gm_get_display_clock_speed(struct drm_device *dev)
6723 {
6724         u16 gcfgc = 0;
6725
6726         pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
6727
6728         if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
6729                 return 133333;
6730         else {
6731                 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
6732                 case GC_DISPLAY_CLOCK_333_MHZ:
6733                         return 333333;
6734                 default:
6735                 case GC_DISPLAY_CLOCK_190_200_MHZ:
6736                         return 190000;
6737                 }
6738         }
6739 }
6740
6741 static int i865_get_display_clock_speed(struct drm_device *dev)
6742 {
6743         return 266667;
6744 }
6745
6746 static int i85x_get_display_clock_speed(struct drm_device *dev)
6747 {
6748         u16 hpllcc = 0;
6749
6750         /*
6751          * 852GM/852GMV only supports 133 MHz and the HPLLCC
6752          * encoding is different :(
6753          * FIXME is this the right way to detect 852GM/852GMV?
6754          */
6755         if (dev->pdev->revision == 0x1)
6756                 return 133333;
6757
6758         pci_bus_read_config_word(dev->pdev->bus,
6759                                  PCI_DEVFN(0, 3), HPLLCC, &hpllcc);
6760
6761         /* Assume that the hardware is in the high speed state.  This
6762          * should be the default.
6763          */
6764         switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
6765         case GC_CLOCK_133_200:
6766         case GC_CLOCK_133_200_2:
6767         case GC_CLOCK_100_200:
6768                 return 200000;
6769         case GC_CLOCK_166_250:
6770                 return 250000;
6771         case GC_CLOCK_100_133:
6772                 return 133333;
6773         case GC_CLOCK_133_266:
6774         case GC_CLOCK_133_266_2:
6775         case GC_CLOCK_166_266:
6776                 return 266667;
6777         }
6778
6779         /* Shouldn't happen */
6780         return 0;
6781 }
6782
6783 static int i830_get_display_clock_speed(struct drm_device *dev)
6784 {
6785         return 133333;
6786 }
6787
6788 static unsigned int intel_hpll_vco(struct drm_device *dev)
6789 {
6790         struct drm_i915_private *dev_priv = dev->dev_private;
6791         static const unsigned int blb_vco[8] = {
6792                 [0] = 3200000,
6793                 [1] = 4000000,
6794                 [2] = 5333333,
6795                 [3] = 4800000,
6796                 [4] = 6400000,
6797         };
6798         static const unsigned int pnv_vco[8] = {
6799                 [0] = 3200000,
6800                 [1] = 4000000,
6801                 [2] = 5333333,
6802                 [3] = 4800000,
6803                 [4] = 2666667,
6804         };
6805         static const unsigned int cl_vco[8] = {
6806                 [0] = 3200000,
6807                 [1] = 4000000,
6808                 [2] = 5333333,
6809                 [3] = 6400000,
6810                 [4] = 3333333,
6811                 [5] = 3566667,
6812                 [6] = 4266667,
6813         };
6814         static const unsigned int elk_vco[8] = {
6815                 [0] = 3200000,
6816                 [1] = 4000000,
6817                 [2] = 5333333,
6818                 [3] = 4800000,
6819         };
6820         static const unsigned int ctg_vco[8] = {
6821                 [0] = 3200000,
6822                 [1] = 4000000,
6823                 [2] = 5333333,
6824                 [3] = 6400000,
6825                 [4] = 2666667,
6826                 [5] = 4266667,
6827         };
6828         const unsigned int *vco_table;
6829         unsigned int vco;
6830         uint8_t tmp = 0;
6831
6832         /* FIXME other chipsets? */
6833         if (IS_GM45(dev))
6834                 vco_table = ctg_vco;
6835         else if (IS_G4X(dev))
6836                 vco_table = elk_vco;
6837         else if (IS_CRESTLINE(dev))
6838                 vco_table = cl_vco;
6839         else if (IS_PINEVIEW(dev))
6840                 vco_table = pnv_vco;
6841         else if (IS_G33(dev))
6842                 vco_table = blb_vco;
6843         else
6844                 return 0;
6845
6846         tmp = I915_READ(IS_MOBILE(dev) ? HPLLVCO_MOBILE : HPLLVCO);
6847
6848         vco = vco_table[tmp & 0x7];
6849         if (vco == 0)
6850                 DRM_ERROR("Bad HPLL VCO (HPLLVCO=0x%02x)\n", tmp);
6851         else
6852                 DRM_DEBUG_KMS("HPLL VCO %u kHz\n", vco);
6853
6854         return vco;
6855 }
6856
6857 static int gm45_get_display_clock_speed(struct drm_device *dev)
6858 {
6859         unsigned int cdclk_sel, vco = intel_hpll_vco(dev);
6860         uint16_t tmp = 0;
6861
6862         pci_read_config_word(dev->pdev, GCFGC, &tmp);
6863
6864         cdclk_sel = (tmp >> 12) & 0x1;
6865
6866         switch (vco) {
6867         case 2666667:
6868         case 4000000:
6869         case 5333333:
6870                 return cdclk_sel ? 333333 : 222222;
6871         case 3200000:
6872                 return cdclk_sel ? 320000 : 228571;
6873         default:
6874                 DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u, CFGC=0x%04x\n", vco, tmp);
6875                 return 222222;
6876         }
6877 }
6878
6879 static int i965gm_get_display_clock_speed(struct drm_device *dev)
6880 {
6881         static const uint8_t div_3200[] = { 16, 10,  8 };
6882         static const uint8_t div_4000[] = { 20, 12, 10 };
6883         static const uint8_t div_5333[] = { 24, 16, 14 };
6884         const uint8_t *div_table;
6885         unsigned int cdclk_sel, vco = intel_hpll_vco(dev);
6886         uint16_t tmp = 0;
6887
6888         pci_read_config_word(dev->pdev, GCFGC, &tmp);
6889
6890         cdclk_sel = ((tmp >> 8) & 0x1f) - 1;
6891
6892         if (cdclk_sel >= ARRAY_SIZE(div_3200))
6893                 goto fail;
6894
6895         switch (vco) {
6896         case 3200000:
6897                 div_table = div_3200;
6898                 break;
6899         case 4000000:
6900                 div_table = div_4000;
6901                 break;
6902         case 5333333:
6903                 div_table = div_5333;
6904                 break;
6905         default:
6906                 goto fail;
6907         }
6908
6909         return DIV_ROUND_CLOSEST(vco, div_table[cdclk_sel]);
6910
6911 fail:
6912         DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u kHz, CFGC=0x%04x\n", vco, tmp);
6913         return 200000;
6914 }
6915
6916 static int g33_get_display_clock_speed(struct drm_device *dev)
6917 {
6918         static const uint8_t div_3200[] = { 12, 10,  8,  7, 5, 16 };
6919         static const uint8_t div_4000[] = { 14, 12, 10,  8, 6, 20 };
6920         static const uint8_t div_4800[] = { 20, 14, 12, 10, 8, 24 };
6921         static const uint8_t div_5333[] = { 20, 16, 12, 12, 8, 28 };
6922         const uint8_t *div_table;
6923         unsigned int cdclk_sel, vco = intel_hpll_vco(dev);
6924         uint16_t tmp = 0;
6925
6926         pci_read_config_word(dev->pdev, GCFGC, &tmp);
6927
6928         cdclk_sel = (tmp >> 4) & 0x7;
6929
6930         if (cdclk_sel >= ARRAY_SIZE(div_3200))
6931                 goto fail;
6932
6933         switch (vco) {
6934         case 3200000:
6935                 div_table = div_3200;
6936                 break;
6937         case 4000000:
6938                 div_table = div_4000;
6939                 break;
6940         case 4800000:
6941                 div_table = div_4800;
6942                 break;
6943         case 5333333:
6944                 div_table = div_5333;
6945                 break;
6946         default:
6947                 goto fail;
6948         }
6949
6950         return DIV_ROUND_CLOSEST(vco, div_table[cdclk_sel]);
6951
6952 fail:
6953         DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u kHz, CFGC=0x%08x\n", vco, tmp);
6954         return 190476;
6955 }
6956
6957 static void
6958 intel_reduce_m_n_ratio(uint32_t *num, uint32_t *den)
6959 {
6960         while (*num > DATA_LINK_M_N_MASK ||
6961                *den > DATA_LINK_M_N_MASK) {
6962                 *num >>= 1;
6963                 *den >>= 1;
6964         }
6965 }
6966
6967 static void compute_m_n(unsigned int m, unsigned int n,
6968                         uint32_t *ret_m, uint32_t *ret_n)
6969 {
6970         *ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX);
6971         *ret_m = div_u64((uint64_t) m * *ret_n, n);
6972         intel_reduce_m_n_ratio(ret_m, ret_n);
6973 }
6974
6975 void
6976 intel_link_compute_m_n(int bits_per_pixel, int nlanes,
6977                        int pixel_clock, int link_clock,
6978                        struct intel_link_m_n *m_n)
6979 {
6980         m_n->tu = 64;
6981
6982         compute_m_n(bits_per_pixel * pixel_clock,
6983                     link_clock * nlanes * 8,
6984                     &m_n->gmch_m, &m_n->gmch_n);
6985
6986         compute_m_n(pixel_clock, link_clock,
6987                     &m_n->link_m, &m_n->link_n);
6988 }
6989
6990 static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
6991 {
6992         if (i915.panel_use_ssc >= 0)
6993                 return i915.panel_use_ssc != 0;
6994         return dev_priv->vbt.lvds_use_ssc
6995                 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
6996 }
6997
6998 static int i9xx_get_refclk(const struct intel_crtc_state *crtc_state,
6999                            int num_connectors)
7000 {
7001         struct drm_device *dev = crtc_state->base.crtc->dev;
7002         struct drm_i915_private *dev_priv = dev->dev_private;
7003         int refclk;
7004
7005         WARN_ON(!crtc_state->base.state);
7006
7007         if (IS_VALLEYVIEW(dev) || IS_BROXTON(dev)) {
7008                 refclk = 100000;
7009         } else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
7010             intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
7011                 refclk = dev_priv->vbt.lvds_ssc_freq;
7012                 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
7013         } else if (!IS_GEN2(dev)) {
7014                 refclk = 96000;
7015         } else {
7016                 refclk = 48000;
7017         }
7018
7019         return refclk;
7020 }
7021
7022 static uint32_t pnv_dpll_compute_fp(struct dpll *dpll)
7023 {
7024         return (1 << dpll->n) << 16 | dpll->m2;
7025 }
7026
7027 static uint32_t i9xx_dpll_compute_fp(struct dpll *dpll)
7028 {
7029         return dpll->n << 16 | dpll->m1 << 8 | dpll->m2;
7030 }
7031
7032 static void i9xx_update_pll_dividers(struct intel_crtc *crtc,
7033                                      struct intel_crtc_state *crtc_state,
7034                                      intel_clock_t *reduced_clock)
7035 {
7036         struct drm_device *dev = crtc->base.dev;
7037         u32 fp, fp2 = 0;
7038
7039         if (IS_PINEVIEW(dev)) {
7040                 fp = pnv_dpll_compute_fp(&crtc_state->dpll);
7041                 if (reduced_clock)
7042                         fp2 = pnv_dpll_compute_fp(reduced_clock);
7043         } else {
7044                 fp = i9xx_dpll_compute_fp(&crtc_state->dpll);
7045                 if (reduced_clock)
7046                         fp2 = i9xx_dpll_compute_fp(reduced_clock);
7047         }
7048
7049         crtc_state->dpll_hw_state.fp0 = fp;
7050
7051         crtc->lowfreq_avail = false;
7052         if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
7053             reduced_clock) {
7054                 crtc_state->dpll_hw_state.fp1 = fp2;
7055                 crtc->lowfreq_avail = true;
7056         } else {
7057                 crtc_state->dpll_hw_state.fp1 = fp;
7058         }
7059 }
7060
7061 static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv, enum pipe
7062                 pipe)
7063 {
7064         u32 reg_val;
7065
7066         /*
7067          * PLLB opamp always calibrates to max value of 0x3f, force enable it
7068          * and set it to a reasonable value instead.
7069          */
7070         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
7071         reg_val &= 0xffffff00;
7072         reg_val |= 0x00000030;
7073         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
7074
7075         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
7076         reg_val &= 0x8cffffff;
7077         reg_val = 0x8c000000;
7078         vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
7079
7080         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
7081         reg_val &= 0xffffff00;
7082         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
7083
7084         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
7085         reg_val &= 0x00ffffff;
7086         reg_val |= 0xb0000000;
7087         vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
7088 }
7089
7090 static void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc,
7091                                          struct intel_link_m_n *m_n)
7092 {
7093         struct drm_device *dev = crtc->base.dev;
7094         struct drm_i915_private *dev_priv = dev->dev_private;
7095         int pipe = crtc->pipe;
7096
7097         I915_WRITE(PCH_TRANS_DATA_M1(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
7098         I915_WRITE(PCH_TRANS_DATA_N1(pipe), m_n->gmch_n);
7099         I915_WRITE(PCH_TRANS_LINK_M1(pipe), m_n->link_m);
7100         I915_WRITE(PCH_TRANS_LINK_N1(pipe), m_n->link_n);
7101 }
7102
7103 static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
7104                                          struct intel_link_m_n *m_n,
7105                                          struct intel_link_m_n *m2_n2)
7106 {
7107         struct drm_device *dev = crtc->base.dev;
7108         struct drm_i915_private *dev_priv = dev->dev_private;
7109         int pipe = crtc->pipe;
7110         enum transcoder transcoder = crtc->config->cpu_transcoder;
7111
7112         if (INTEL_INFO(dev)->gen >= 5) {
7113                 I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m);
7114                 I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n);
7115                 I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m);
7116                 I915_WRITE(PIPE_LINK_N1(transcoder), m_n->link_n);
7117                 /* M2_N2 registers to be set only for gen < 8 (M2_N2 available
7118                  * for gen < 8) and if DRRS is supported (to make sure the
7119                  * registers are not unnecessarily accessed).
7120                  */
7121                 if (m2_n2 && (IS_CHERRYVIEW(dev) || INTEL_INFO(dev)->gen < 8) &&
7122                         crtc->config->has_drrs) {
7123                         I915_WRITE(PIPE_DATA_M2(transcoder),
7124                                         TU_SIZE(m2_n2->tu) | m2_n2->gmch_m);
7125                         I915_WRITE(PIPE_DATA_N2(transcoder), m2_n2->gmch_n);
7126                         I915_WRITE(PIPE_LINK_M2(transcoder), m2_n2->link_m);
7127                         I915_WRITE(PIPE_LINK_N2(transcoder), m2_n2->link_n);
7128                 }
7129         } else {
7130                 I915_WRITE(PIPE_DATA_M_G4X(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
7131                 I915_WRITE(PIPE_DATA_N_G4X(pipe), m_n->gmch_n);
7132                 I915_WRITE(PIPE_LINK_M_G4X(pipe), m_n->link_m);
7133                 I915_WRITE(PIPE_LINK_N_G4X(pipe), m_n->link_n);
7134         }
7135 }
7136
7137 void intel_dp_set_m_n(struct intel_crtc *crtc, enum link_m_n_set m_n)
7138 {
7139         struct intel_link_m_n *dp_m_n, *dp_m2_n2 = NULL;
7140
7141         if (m_n == M1_N1) {
7142                 dp_m_n = &crtc->config->dp_m_n;
7143                 dp_m2_n2 = &crtc->config->dp_m2_n2;
7144         } else if (m_n == M2_N2) {
7145
7146                 /*
7147                  * M2_N2 registers are not supported. Hence m2_n2 divider value
7148                  * needs to be programmed into M1_N1.
7149                  */
7150                 dp_m_n = &crtc->config->dp_m2_n2;
7151         } else {
7152                 DRM_ERROR("Unsupported divider value\n");
7153                 return;
7154         }
7155
7156         if (crtc->config->has_pch_encoder)
7157                 intel_pch_transcoder_set_m_n(crtc, &crtc->config->dp_m_n);
7158         else
7159                 intel_cpu_transcoder_set_m_n(crtc, dp_m_n, dp_m2_n2);
7160 }
7161
7162 static void vlv_update_pll(struct intel_crtc *crtc,
7163                            struct intel_crtc_state *pipe_config)
7164 {
7165         u32 dpll, dpll_md;
7166
7167         /*
7168          * Enable DPIO clock input. We should never disable the reference
7169          * clock for pipe B, since VGA hotplug / manual detection depends
7170          * on it.
7171          */
7172         dpll = DPLL_EXT_BUFFER_ENABLE_VLV | DPLL_REFA_CLK_ENABLE_VLV |
7173                 DPLL_VGA_MODE_DIS | DPLL_INTEGRATED_CLOCK_VLV;
7174         /* We should never disable this, set it here for state tracking */
7175         if (crtc->pipe == PIPE_B)
7176                 dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
7177         dpll |= DPLL_VCO_ENABLE;
7178         pipe_config->dpll_hw_state.dpll = dpll;
7179
7180         dpll_md = (pipe_config->pixel_multiplier - 1)
7181                 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
7182         pipe_config->dpll_hw_state.dpll_md = dpll_md;
7183 }
7184
7185 static void vlv_prepare_pll(struct intel_crtc *crtc,
7186                             const struct intel_crtc_state *pipe_config)
7187 {
7188         struct drm_device *dev = crtc->base.dev;
7189         struct drm_i915_private *dev_priv = dev->dev_private;
7190         int pipe = crtc->pipe;
7191         u32 mdiv;
7192         u32 bestn, bestm1, bestm2, bestp1, bestp2;
7193         u32 coreclk, reg_val;
7194
7195         mutex_lock(&dev_priv->sb_lock);
7196
7197         bestn = pipe_config->dpll.n;
7198         bestm1 = pipe_config->dpll.m1;
7199         bestm2 = pipe_config->dpll.m2;
7200         bestp1 = pipe_config->dpll.p1;
7201         bestp2 = pipe_config->dpll.p2;
7202
7203         /* See eDP HDMI DPIO driver vbios notes doc */
7204
7205         /* PLL B needs special handling */
7206         if (pipe == PIPE_B)
7207                 vlv_pllb_recal_opamp(dev_priv, pipe);
7208
7209         /* Set up Tx target for periodic Rcomp update */
7210         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9_BCAST, 0x0100000f);
7211
7212         /* Disable target IRef on PLL */
7213         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW8(pipe));
7214         reg_val &= 0x00ffffff;
7215         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW8(pipe), reg_val);
7216
7217         /* Disable fast lock */
7218         vlv_dpio_write(dev_priv, pipe, VLV_CMN_DW0, 0x610);
7219
7220         /* Set idtafcrecal before PLL is enabled */
7221         mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
7222         mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
7223         mdiv |= ((bestn << DPIO_N_SHIFT));
7224         mdiv |= (1 << DPIO_K_SHIFT);
7225
7226         /*
7227          * Post divider depends on pixel clock rate, DAC vs digital (and LVDS,
7228          * but we don't support that).
7229          * Note: don't use the DAC post divider as it seems unstable.
7230          */
7231         mdiv |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT);
7232         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
7233
7234         mdiv |= DPIO_ENABLE_CALIBRATION;
7235         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
7236
7237         /* Set HBR and RBR LPF coefficients */
7238         if (pipe_config->port_clock == 162000 ||
7239             intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG) ||
7240             intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI))
7241                 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
7242                                  0x009f0003);
7243         else
7244                 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
7245                                  0x00d0000f);
7246
7247         if (pipe_config->has_dp_encoder) {
7248                 /* Use SSC source */
7249                 if (pipe == PIPE_A)
7250                         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
7251                                          0x0df40000);
7252                 else
7253                         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
7254                                          0x0df70000);
7255         } else { /* HDMI or VGA */
7256                 /* Use bend source */
7257                 if (pipe == PIPE_A)
7258                         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
7259                                          0x0df70000);
7260                 else
7261                         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
7262                                          0x0df40000);
7263         }
7264
7265         coreclk = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW7(pipe));
7266         coreclk = (coreclk & 0x0000ff00) | 0x01c00000;
7267         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
7268             intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))
7269                 coreclk |= 0x01000000;
7270         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW7(pipe), coreclk);
7271
7272         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW11(pipe), 0x87871000);
7273         mutex_unlock(&dev_priv->sb_lock);
7274 }
7275
7276 static void chv_update_pll(struct intel_crtc *crtc,
7277                            struct intel_crtc_state *pipe_config)
7278 {
7279         pipe_config->dpll_hw_state.dpll = DPLL_SSC_REF_CLOCK_CHV |
7280                 DPLL_REFA_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS |
7281                 DPLL_VCO_ENABLE;
7282         if (crtc->pipe != PIPE_A)
7283                 pipe_config->dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
7284
7285         pipe_config->dpll_hw_state.dpll_md =
7286                 (pipe_config->pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
7287 }
7288
7289 static void chv_prepare_pll(struct intel_crtc *crtc,
7290                             const struct intel_crtc_state *pipe_config)
7291 {
7292         struct drm_device *dev = crtc->base.dev;
7293         struct drm_i915_private *dev_priv = dev->dev_private;
7294         int pipe = crtc->pipe;
7295         int dpll_reg = DPLL(crtc->pipe);
7296         enum dpio_channel port = vlv_pipe_to_channel(pipe);
7297         u32 loopfilter, tribuf_calcntr;
7298         u32 bestn, bestm1, bestm2, bestp1, bestp2, bestm2_frac;
7299         u32 dpio_val;
7300         int vco;
7301
7302         bestn = pipe_config->dpll.n;
7303         bestm2_frac = pipe_config->dpll.m2 & 0x3fffff;
7304         bestm1 = pipe_config->dpll.m1;
7305         bestm2 = pipe_config->dpll.m2 >> 22;
7306         bestp1 = pipe_config->dpll.p1;
7307         bestp2 = pipe_config->dpll.p2;
7308         vco = pipe_config->dpll.vco;
7309         dpio_val = 0;
7310         loopfilter = 0;
7311
7312         /*
7313          * Enable Refclk and SSC
7314          */
7315         I915_WRITE(dpll_reg,
7316                    pipe_config->dpll_hw_state.dpll & ~DPLL_VCO_ENABLE);
7317
7318         mutex_lock(&dev_priv->sb_lock);
7319
7320         /* p1 and p2 divider */
7321         vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW13(port),
7322                         5 << DPIO_CHV_S1_DIV_SHIFT |
7323                         bestp1 << DPIO_CHV_P1_DIV_SHIFT |
7324                         bestp2 << DPIO_CHV_P2_DIV_SHIFT |
7325                         1 << DPIO_CHV_K_DIV_SHIFT);
7326
7327         /* Feedback post-divider - m2 */
7328         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW0(port), bestm2);
7329
7330         /* Feedback refclk divider - n and m1 */
7331         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW1(port),
7332                         DPIO_CHV_M1_DIV_BY_2 |
7333                         1 << DPIO_CHV_N_DIV_SHIFT);
7334
7335         /* M2 fraction division */
7336         if (bestm2_frac)
7337                 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW2(port), bestm2_frac);
7338
7339         /* M2 fraction division enable */
7340         dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port));
7341         dpio_val &= ~(DPIO_CHV_FEEDFWD_GAIN_MASK | DPIO_CHV_FRAC_DIV_EN);
7342         dpio_val |= (2 << DPIO_CHV_FEEDFWD_GAIN_SHIFT);
7343         if (bestm2_frac)
7344                 dpio_val |= DPIO_CHV_FRAC_DIV_EN;
7345         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW3(port), dpio_val);
7346
7347         /* Program digital lock detect threshold */
7348         dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW9(port));
7349         dpio_val &= ~(DPIO_CHV_INT_LOCK_THRESHOLD_MASK |
7350                                         DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE);
7351         dpio_val |= (0x5 << DPIO_CHV_INT_LOCK_THRESHOLD_SHIFT);
7352         if (!bestm2_frac)
7353                 dpio_val |= DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE;
7354         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW9(port), dpio_val);
7355
7356         /* Loop filter */
7357         if (vco == 5400000) {
7358                 loopfilter |= (0x3 << DPIO_CHV_PROP_COEFF_SHIFT);
7359                 loopfilter |= (0x8 << DPIO_CHV_INT_COEFF_SHIFT);
7360                 loopfilter |= (0x1 << DPIO_CHV_GAIN_CTRL_SHIFT);
7361                 tribuf_calcntr = 0x9;
7362         } else if (vco <= 6200000) {
7363                 loopfilter |= (0x5 << DPIO_CHV_PROP_COEFF_SHIFT);
7364                 loopfilter |= (0xB << DPIO_CHV_INT_COEFF_SHIFT);
7365                 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
7366                 tribuf_calcntr = 0x9;
7367         } else if (vco <= 6480000) {
7368                 loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT);
7369                 loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT);
7370                 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
7371                 tribuf_calcntr = 0x8;
7372         } else {
7373                 /* Not supported. Apply the same limits as in the max case */
7374                 loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT);
7375                 loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT);
7376                 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
7377                 tribuf_calcntr = 0;
7378         }
7379         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW6(port), loopfilter);
7380
7381         dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW8(port));
7382         dpio_val &= ~DPIO_CHV_TDC_TARGET_CNT_MASK;
7383         dpio_val |= (tribuf_calcntr << DPIO_CHV_TDC_TARGET_CNT_SHIFT);
7384         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW8(port), dpio_val);
7385
7386         /* AFC Recal */
7387         vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port),
7388                         vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)) |
7389                         DPIO_AFC_RECAL);
7390
7391         mutex_unlock(&dev_priv->sb_lock);
7392 }
7393
7394 /**
7395  * vlv_force_pll_on - forcibly enable just the PLL
7396  * @dev_priv: i915 private structure
7397  * @pipe: pipe PLL to enable
7398  * @dpll: PLL configuration
7399  *
7400  * Enable the PLL for @pipe using the supplied @dpll config. To be used
7401  * in cases where we need the PLL enabled even when @pipe is not going to
7402  * be enabled.
7403  */
7404 void vlv_force_pll_on(struct drm_device *dev, enum pipe pipe,
7405                       const struct dpll *dpll)
7406 {
7407         struct intel_crtc *crtc =
7408                 to_intel_crtc(intel_get_crtc_for_pipe(dev, pipe));
7409         struct intel_crtc_state pipe_config = {
7410                 .base.crtc = &crtc->base,
7411                 .pixel_multiplier = 1,
7412                 .dpll = *dpll,
7413         };
7414
7415         if (IS_CHERRYVIEW(dev)) {
7416                 chv_update_pll(crtc, &pipe_config);
7417                 chv_prepare_pll(crtc, &pipe_config);
7418                 chv_enable_pll(crtc, &pipe_config);
7419         } else {
7420                 vlv_update_pll(crtc, &pipe_config);
7421                 vlv_prepare_pll(crtc, &pipe_config);
7422                 vlv_enable_pll(crtc, &pipe_config);
7423         }
7424 }
7425
7426 /**
7427  * vlv_force_pll_off - forcibly disable just the PLL
7428  * @dev_priv: i915 private structure
7429  * @pipe: pipe PLL to disable
7430  *
7431  * Disable the PLL for @pipe. To be used in cases where we need
7432  * the PLL enabled even when @pipe is not going to be enabled.
7433  */
7434 void vlv_force_pll_off(struct drm_device *dev, enum pipe pipe)
7435 {
7436         if (IS_CHERRYVIEW(dev))
7437                 chv_disable_pll(to_i915(dev), pipe);
7438         else
7439                 vlv_disable_pll(to_i915(dev), pipe);
7440 }
7441
7442 static void i9xx_update_pll(struct intel_crtc *crtc,
7443                             struct intel_crtc_state *crtc_state,
7444                             intel_clock_t *reduced_clock,
7445                             int num_connectors)
7446 {
7447         struct drm_device *dev = crtc->base.dev;
7448         struct drm_i915_private *dev_priv = dev->dev_private;
7449         u32 dpll;
7450         bool is_sdvo;
7451         struct dpll *clock = &crtc_state->dpll;
7452
7453         i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock);
7454
7455         is_sdvo = intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_SDVO) ||
7456                 intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_HDMI);
7457
7458         dpll = DPLL_VGA_MODE_DIS;
7459
7460         if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS))
7461                 dpll |= DPLLB_MODE_LVDS;
7462         else
7463                 dpll |= DPLLB_MODE_DAC_SERIAL;
7464
7465         if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
7466                 dpll |= (crtc_state->pixel_multiplier - 1)
7467                         << SDVO_MULTIPLIER_SHIFT_HIRES;
7468         }
7469
7470         if (is_sdvo)
7471                 dpll |= DPLL_SDVO_HIGH_SPEED;
7472
7473         if (crtc_state->has_dp_encoder)
7474                 dpll |= DPLL_SDVO_HIGH_SPEED;
7475
7476         /* compute bitmask from p1 value */
7477         if (IS_PINEVIEW(dev))
7478                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
7479         else {
7480                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
7481                 if (IS_G4X(dev) && reduced_clock)
7482                         dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
7483         }
7484         switch (clock->p2) {
7485         case 5:
7486                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
7487                 break;
7488         case 7:
7489                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
7490                 break;
7491         case 10:
7492                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
7493                 break;
7494         case 14:
7495                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
7496                 break;
7497         }
7498         if (INTEL_INFO(dev)->gen >= 4)
7499                 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
7500
7501         if (crtc_state->sdvo_tv_clock)
7502                 dpll |= PLL_REF_INPUT_TVCLKINBC;
7503         else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
7504                  intel_panel_use_ssc(dev_priv) && num_connectors < 2)
7505                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
7506         else
7507                 dpll |= PLL_REF_INPUT_DREFCLK;
7508
7509         dpll |= DPLL_VCO_ENABLE;
7510         crtc_state->dpll_hw_state.dpll = dpll;
7511
7512         if (INTEL_INFO(dev)->gen >= 4) {
7513                 u32 dpll_md = (crtc_state->pixel_multiplier - 1)
7514                         << DPLL_MD_UDI_MULTIPLIER_SHIFT;
7515                 crtc_state->dpll_hw_state.dpll_md = dpll_md;
7516         }
7517 }
7518
7519 static void i8xx_update_pll(struct intel_crtc *crtc,
7520                             struct intel_crtc_state *crtc_state,
7521                             intel_clock_t *reduced_clock,
7522                             int num_connectors)
7523 {
7524         struct drm_device *dev = crtc->base.dev;
7525         struct drm_i915_private *dev_priv = dev->dev_private;
7526         u32 dpll;
7527         struct dpll *clock = &crtc_state->dpll;
7528
7529         i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock);
7530
7531         dpll = DPLL_VGA_MODE_DIS;
7532
7533         if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
7534                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
7535         } else {
7536                 if (clock->p1 == 2)
7537                         dpll |= PLL_P1_DIVIDE_BY_TWO;
7538                 else
7539                         dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
7540                 if (clock->p2 == 4)
7541                         dpll |= PLL_P2_DIVIDE_BY_4;
7542         }
7543
7544         if (!IS_I830(dev) && intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_DVO))
7545                 dpll |= DPLL_DVO_2X_MODE;
7546
7547         if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
7548                  intel_panel_use_ssc(dev_priv) && num_connectors < 2)
7549                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
7550         else
7551                 dpll |= PLL_REF_INPUT_DREFCLK;
7552
7553         dpll |= DPLL_VCO_ENABLE;
7554         crtc_state->dpll_hw_state.dpll = dpll;
7555 }
7556
7557 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc)
7558 {
7559         struct drm_device *dev = intel_crtc->base.dev;
7560         struct drm_i915_private *dev_priv = dev->dev_private;
7561         enum pipe pipe = intel_crtc->pipe;
7562         enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
7563         struct drm_display_mode *adjusted_mode =
7564                 &intel_crtc->config->base.adjusted_mode;
7565         uint32_t crtc_vtotal, crtc_vblank_end;
7566         int vsyncshift = 0;
7567
7568         /* We need to be careful not to changed the adjusted mode, for otherwise
7569          * the hw state checker will get angry at the mismatch. */
7570         crtc_vtotal = adjusted_mode->crtc_vtotal;
7571         crtc_vblank_end = adjusted_mode->crtc_vblank_end;
7572
7573         if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
7574                 /* the chip adds 2 halflines automatically */
7575                 crtc_vtotal -= 1;
7576                 crtc_vblank_end -= 1;
7577
7578                 if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
7579                         vsyncshift = (adjusted_mode->crtc_htotal - 1) / 2;
7580                 else
7581                         vsyncshift = adjusted_mode->crtc_hsync_start -
7582                                 adjusted_mode->crtc_htotal / 2;
7583                 if (vsyncshift < 0)
7584                         vsyncshift += adjusted_mode->crtc_htotal;
7585         }
7586
7587         if (INTEL_INFO(dev)->gen > 3)
7588                 I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift);
7589
7590         I915_WRITE(HTOTAL(cpu_transcoder),
7591                    (adjusted_mode->crtc_hdisplay - 1) |
7592                    ((adjusted_mode->crtc_htotal - 1) << 16));
7593         I915_WRITE(HBLANK(cpu_transcoder),
7594                    (adjusted_mode->crtc_hblank_start - 1) |
7595                    ((adjusted_mode->crtc_hblank_end - 1) << 16));
7596         I915_WRITE(HSYNC(cpu_transcoder),
7597                    (adjusted_mode->crtc_hsync_start - 1) |
7598                    ((adjusted_mode->crtc_hsync_end - 1) << 16));
7599
7600         I915_WRITE(VTOTAL(cpu_transcoder),
7601                    (adjusted_mode->crtc_vdisplay - 1) |
7602                    ((crtc_vtotal - 1) << 16));
7603         I915_WRITE(VBLANK(cpu_transcoder),
7604                    (adjusted_mode->crtc_vblank_start - 1) |
7605                    ((crtc_vblank_end - 1) << 16));
7606         I915_WRITE(VSYNC(cpu_transcoder),
7607                    (adjusted_mode->crtc_vsync_start - 1) |
7608                    ((adjusted_mode->crtc_vsync_end - 1) << 16));
7609
7610         /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
7611          * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
7612          * documented on the DDI_FUNC_CTL register description, EDP Input Select
7613          * bits. */
7614         if (IS_HASWELL(dev) && cpu_transcoder == TRANSCODER_EDP &&
7615             (pipe == PIPE_B || pipe == PIPE_C))
7616                 I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder)));
7617
7618         /* pipesrc controls the size that is scaled from, which should
7619          * always be the user's requested size.
7620          */
7621         I915_WRITE(PIPESRC(pipe),
7622                    ((intel_crtc->config->pipe_src_w - 1) << 16) |
7623                    (intel_crtc->config->pipe_src_h - 1));
7624 }
7625
7626 static void intel_get_pipe_timings(struct intel_crtc *crtc,
7627                                    struct intel_crtc_state *pipe_config)
7628 {
7629         struct drm_device *dev = crtc->base.dev;
7630         struct drm_i915_private *dev_priv = dev->dev_private;
7631         enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
7632         uint32_t tmp;
7633
7634         tmp = I915_READ(HTOTAL(cpu_transcoder));
7635         pipe_config->base.adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1;
7636         pipe_config->base.adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1;
7637         tmp = I915_READ(HBLANK(cpu_transcoder));
7638         pipe_config->base.adjusted_mode.crtc_hblank_start = (tmp & 0xffff) + 1;
7639         pipe_config->base.adjusted_mode.crtc_hblank_end = ((tmp >> 16) & 0xffff) + 1;
7640         tmp = I915_READ(HSYNC(cpu_transcoder));
7641         pipe_config->base.adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1;
7642         pipe_config->base.adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1;
7643
7644         tmp = I915_READ(VTOTAL(cpu_transcoder));
7645         pipe_config->base.adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1;
7646         pipe_config->base.adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1;
7647         tmp = I915_READ(VBLANK(cpu_transcoder));
7648         pipe_config->base.adjusted_mode.crtc_vblank_start = (tmp & 0xffff) + 1;
7649         pipe_config->base.adjusted_mode.crtc_vblank_end = ((tmp >> 16) & 0xffff) + 1;
7650         tmp = I915_READ(VSYNC(cpu_transcoder));
7651         pipe_config->base.adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1;
7652         pipe_config->base.adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1;
7653
7654         if (I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK) {
7655                 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE;
7656                 pipe_config->base.adjusted_mode.crtc_vtotal += 1;
7657                 pipe_config->base.adjusted_mode.crtc_vblank_end += 1;
7658         }
7659
7660         tmp = I915_READ(PIPESRC(crtc->pipe));
7661         pipe_config->pipe_src_h = (tmp & 0xffff) + 1;
7662         pipe_config->pipe_src_w = ((tmp >> 16) & 0xffff) + 1;
7663
7664         pipe_config->base.mode.vdisplay = pipe_config->pipe_src_h;
7665         pipe_config->base.mode.hdisplay = pipe_config->pipe_src_w;
7666 }
7667
7668 void intel_mode_from_pipe_config(struct drm_display_mode *mode,
7669                                  struct intel_crtc_state *pipe_config)
7670 {
7671         mode->hdisplay = pipe_config->base.adjusted_mode.crtc_hdisplay;
7672         mode->htotal = pipe_config->base.adjusted_mode.crtc_htotal;
7673         mode->hsync_start = pipe_config->base.adjusted_mode.crtc_hsync_start;
7674         mode->hsync_end = pipe_config->base.adjusted_mode.crtc_hsync_end;
7675
7676         mode->vdisplay = pipe_config->base.adjusted_mode.crtc_vdisplay;
7677         mode->vtotal = pipe_config->base.adjusted_mode.crtc_vtotal;
7678         mode->vsync_start = pipe_config->base.adjusted_mode.crtc_vsync_start;
7679         mode->vsync_end = pipe_config->base.adjusted_mode.crtc_vsync_end;
7680
7681         mode->flags = pipe_config->base.adjusted_mode.flags;
7682
7683         mode->clock = pipe_config->base.adjusted_mode.crtc_clock;
7684         mode->flags |= pipe_config->base.adjusted_mode.flags;
7685 }
7686
7687 static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc)
7688 {
7689         struct drm_device *dev = intel_crtc->base.dev;
7690         struct drm_i915_private *dev_priv = dev->dev_private;
7691         uint32_t pipeconf;
7692
7693         pipeconf = 0;
7694
7695         if ((intel_crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
7696             (intel_crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
7697                 pipeconf |= I915_READ(PIPECONF(intel_crtc->pipe)) & PIPECONF_ENABLE;
7698
7699         if (intel_crtc->config->double_wide)
7700                 pipeconf |= PIPECONF_DOUBLE_WIDE;
7701
7702         /* only g4x and later have fancy bpc/dither controls */
7703         if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
7704                 /* Bspec claims that we can't use dithering for 30bpp pipes. */
7705                 if (intel_crtc->config->dither && intel_crtc->config->pipe_bpp != 30)
7706                         pipeconf |= PIPECONF_DITHER_EN |
7707                                     PIPECONF_DITHER_TYPE_SP;
7708
7709                 switch (intel_crtc->config->pipe_bpp) {
7710                 case 18:
7711                         pipeconf |= PIPECONF_6BPC;
7712                         break;
7713                 case 24:
7714                         pipeconf |= PIPECONF_8BPC;
7715                         break;
7716                 case 30:
7717                         pipeconf |= PIPECONF_10BPC;
7718                         break;
7719                 default:
7720                         /* Case prevented by intel_choose_pipe_bpp_dither. */
7721                         BUG();
7722                 }
7723         }
7724
7725         if (HAS_PIPE_CXSR(dev)) {
7726                 if (intel_crtc->lowfreq_avail) {
7727                         DRM_DEBUG_KMS("enabling CxSR downclocking\n");
7728                         pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
7729                 } else {
7730                         DRM_DEBUG_KMS("disabling CxSR downclocking\n");
7731                 }
7732         }
7733
7734         if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) {
7735                 if (INTEL_INFO(dev)->gen < 4 ||
7736                     intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
7737                         pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
7738                 else
7739                         pipeconf |= PIPECONF_INTERLACE_W_SYNC_SHIFT;
7740         } else
7741                 pipeconf |= PIPECONF_PROGRESSIVE;
7742
7743         if (IS_VALLEYVIEW(dev) && intel_crtc->config->limited_color_range)
7744                 pipeconf |= PIPECONF_COLOR_RANGE_SELECT;
7745
7746         I915_WRITE(PIPECONF(intel_crtc->pipe), pipeconf);
7747         POSTING_READ(PIPECONF(intel_crtc->pipe));
7748 }
7749
7750 static int i9xx_crtc_compute_clock(struct intel_crtc *crtc,
7751                                    struct intel_crtc_state *crtc_state)
7752 {
7753         struct drm_device *dev = crtc->base.dev;
7754         struct drm_i915_private *dev_priv = dev->dev_private;
7755         int refclk, num_connectors = 0;
7756         intel_clock_t clock, reduced_clock;
7757         bool ok, has_reduced_clock = false;
7758         bool is_lvds = false, is_dsi = false;
7759         struct intel_encoder *encoder;
7760         const intel_limit_t *limit;
7761         struct drm_atomic_state *state = crtc_state->base.state;
7762         struct drm_connector *connector;
7763         struct drm_connector_state *connector_state;
7764         int i;
7765
7766         memset(&crtc_state->dpll_hw_state, 0,
7767                sizeof(crtc_state->dpll_hw_state));
7768
7769         for_each_connector_in_state(state, connector, connector_state, i) {
7770                 if (connector_state->crtc != &crtc->base)
7771                         continue;
7772
7773                 encoder = to_intel_encoder(connector_state->best_encoder);
7774
7775                 switch (encoder->type) {
7776                 case INTEL_OUTPUT_LVDS:
7777                         is_lvds = true;
7778                         break;
7779                 case INTEL_OUTPUT_DSI:
7780                         is_dsi = true;
7781                         break;
7782                 default:
7783                         break;
7784                 }
7785
7786                 num_connectors++;
7787         }
7788
7789         if (is_dsi)
7790                 return 0;
7791
7792         if (!crtc_state->clock_set) {
7793                 refclk = i9xx_get_refclk(crtc_state, num_connectors);
7794
7795                 /*
7796                  * Returns a set of divisors for the desired target clock with
7797                  * the given refclk, or FALSE.  The returned values represent
7798                  * the clock equation: reflck * (5 * (m1 + 2) + (m2 + 2)) / (n +
7799                  * 2) / p1 / p2.
7800                  */
7801                 limit = intel_limit(crtc_state, refclk);
7802                 ok = dev_priv->display.find_dpll(limit, crtc_state,
7803                                                  crtc_state->port_clock,
7804                                                  refclk, NULL, &clock);
7805                 if (!ok) {
7806                         DRM_ERROR("Couldn't find PLL settings for mode!\n");
7807                         return -EINVAL;
7808                 }
7809
7810                 if (is_lvds && dev_priv->lvds_downclock_avail) {
7811                         /*
7812                          * Ensure we match the reduced clock's P to the target
7813                          * clock.  If the clocks don't match, we can't switch
7814                          * the display clock by using the FP0/FP1. In such case
7815                          * we will disable the LVDS downclock feature.
7816                          */
7817                         has_reduced_clock =
7818                                 dev_priv->display.find_dpll(limit, crtc_state,
7819                                                             dev_priv->lvds_downclock,
7820                                                             refclk, &clock,
7821                                                             &reduced_clock);
7822                 }
7823                 /* Compat-code for transition, will disappear. */
7824                 crtc_state->dpll.n = clock.n;
7825                 crtc_state->dpll.m1 = clock.m1;
7826                 crtc_state->dpll.m2 = clock.m2;
7827                 crtc_state->dpll.p1 = clock.p1;
7828                 crtc_state->dpll.p2 = clock.p2;
7829         }
7830
7831         if (IS_GEN2(dev)) {
7832                 i8xx_update_pll(crtc, crtc_state,
7833                                 has_reduced_clock ? &reduced_clock : NULL,
7834                                 num_connectors);
7835         } else if (IS_CHERRYVIEW(dev)) {
7836                 chv_update_pll(crtc, crtc_state);
7837         } else if (IS_VALLEYVIEW(dev)) {
7838                 vlv_update_pll(crtc, crtc_state);
7839         } else {
7840                 i9xx_update_pll(crtc, crtc_state,
7841                                 has_reduced_clock ? &reduced_clock : NULL,
7842                                 num_connectors);
7843         }
7844
7845         return 0;
7846 }
7847
7848 static void i9xx_get_pfit_config(struct intel_crtc *crtc,
7849                                  struct intel_crtc_state *pipe_config)
7850 {
7851         struct drm_device *dev = crtc->base.dev;
7852         struct drm_i915_private *dev_priv = dev->dev_private;
7853         uint32_t tmp;
7854
7855         if (INTEL_INFO(dev)->gen <= 3 && (IS_I830(dev) || !IS_MOBILE(dev)))
7856                 return;
7857
7858         tmp = I915_READ(PFIT_CONTROL);
7859         if (!(tmp & PFIT_ENABLE))
7860                 return;
7861
7862         /* Check whether the pfit is attached to our pipe. */
7863         if (INTEL_INFO(dev)->gen < 4) {
7864                 if (crtc->pipe != PIPE_B)
7865                         return;
7866         } else {
7867                 if ((tmp & PFIT_PIPE_MASK) != (crtc->pipe << PFIT_PIPE_SHIFT))
7868                         return;
7869         }
7870
7871         pipe_config->gmch_pfit.control = tmp;
7872         pipe_config->gmch_pfit.pgm_ratios = I915_READ(PFIT_PGM_RATIOS);
7873         if (INTEL_INFO(dev)->gen < 5)
7874                 pipe_config->gmch_pfit.lvds_border_bits =
7875                         I915_READ(LVDS) & LVDS_BORDER_ENABLE;
7876 }
7877
7878 static void vlv_crtc_clock_get(struct intel_crtc *crtc,
7879                                struct intel_crtc_state *pipe_config)
7880 {
7881         struct drm_device *dev = crtc->base.dev;
7882         struct drm_i915_private *dev_priv = dev->dev_private;
7883         int pipe = pipe_config->cpu_transcoder;
7884         intel_clock_t clock;
7885         u32 mdiv;
7886         int refclk = 100000;
7887
7888         /* In case of MIPI DPLL will not even be used */
7889         if (!(pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE))
7890                 return;
7891
7892         mutex_lock(&dev_priv->sb_lock);
7893         mdiv = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW3(pipe));
7894         mutex_unlock(&dev_priv->sb_lock);
7895
7896         clock.m1 = (mdiv >> DPIO_M1DIV_SHIFT) & 7;
7897         clock.m2 = mdiv & DPIO_M2DIV_MASK;
7898         clock.n = (mdiv >> DPIO_N_SHIFT) & 0xf;
7899         clock.p1 = (mdiv >> DPIO_P1_SHIFT) & 7;
7900         clock.p2 = (mdiv >> DPIO_P2_SHIFT) & 0x1f;
7901
7902         vlv_clock(refclk, &clock);
7903
7904         /* clock.dot is the fast clock */
7905         pipe_config->port_clock = clock.dot / 5;
7906 }
7907
7908 static void
7909 i9xx_get_initial_plane_config(struct intel_crtc *crtc,
7910                               struct intel_initial_plane_config *plane_config)
7911 {
7912         struct drm_device *dev = crtc->base.dev;
7913         struct drm_i915_private *dev_priv = dev->dev_private;
7914         u32 val, base, offset;
7915         int pipe = crtc->pipe, plane = crtc->plane;
7916         int fourcc, pixel_format;
7917         unsigned int aligned_height;
7918         struct drm_framebuffer *fb;
7919         struct intel_framebuffer *intel_fb;
7920
7921         val = I915_READ(DSPCNTR(plane));
7922         if (!(val & DISPLAY_PLANE_ENABLE))
7923                 return;
7924
7925         intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
7926         if (!intel_fb) {
7927                 DRM_DEBUG_KMS("failed to alloc fb\n");
7928                 return;
7929         }
7930
7931         fb = &intel_fb->base;
7932
7933         if (INTEL_INFO(dev)->gen >= 4) {
7934                 if (val & DISPPLANE_TILED) {
7935                         plane_config->tiling = I915_TILING_X;
7936                         fb->modifier[0] = I915_FORMAT_MOD_X_TILED;
7937                 }
7938         }
7939
7940         pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
7941         fourcc = i9xx_format_to_fourcc(pixel_format);
7942         fb->pixel_format = fourcc;
7943         fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
7944
7945         if (INTEL_INFO(dev)->gen >= 4) {
7946                 if (plane_config->tiling)
7947                         offset = I915_READ(DSPTILEOFF(plane));
7948                 else
7949                         offset = I915_READ(DSPLINOFF(plane));
7950                 base = I915_READ(DSPSURF(plane)) & 0xfffff000;
7951         } else {
7952                 base = I915_READ(DSPADDR(plane));
7953         }
7954         plane_config->base = base;
7955
7956         val = I915_READ(PIPESRC(pipe));
7957         fb->width = ((val >> 16) & 0xfff) + 1;
7958         fb->height = ((val >> 0) & 0xfff) + 1;
7959
7960         val = I915_READ(DSPSTRIDE(pipe));
7961         fb->pitches[0] = val & 0xffffffc0;
7962
7963         aligned_height = intel_fb_align_height(dev, fb->height,
7964                                                fb->pixel_format,
7965                                                fb->modifier[0]);
7966
7967         plane_config->size = fb->pitches[0] * aligned_height;
7968
7969         DRM_DEBUG_KMS("pipe/plane %c/%d with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
7970                       pipe_name(pipe), plane, fb->width, fb->height,
7971                       fb->bits_per_pixel, base, fb->pitches[0],
7972                       plane_config->size);
7973
7974         plane_config->fb = intel_fb;
7975 }
7976
7977 static void chv_crtc_clock_get(struct intel_crtc *crtc,
7978                                struct intel_crtc_state *pipe_config)
7979 {
7980         struct drm_device *dev = crtc->base.dev;
7981         struct drm_i915_private *dev_priv = dev->dev_private;
7982         int pipe = pipe_config->cpu_transcoder;
7983         enum dpio_channel port = vlv_pipe_to_channel(pipe);
7984         intel_clock_t clock;
7985         u32 cmn_dw13, pll_dw0, pll_dw1, pll_dw2;
7986         int refclk = 100000;
7987
7988         mutex_lock(&dev_priv->sb_lock);
7989         cmn_dw13 = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW13(port));
7990         pll_dw0 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW0(port));
7991         pll_dw1 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW1(port));
7992         pll_dw2 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW2(port));
7993         mutex_unlock(&dev_priv->sb_lock);
7994
7995         clock.m1 = (pll_dw1 & 0x7) == DPIO_CHV_M1_DIV_BY_2 ? 2 : 0;
7996         clock.m2 = ((pll_dw0 & 0xff) << 22) | (pll_dw2 & 0x3fffff);
7997         clock.n = (pll_dw1 >> DPIO_CHV_N_DIV_SHIFT) & 0xf;
7998         clock.p1 = (cmn_dw13 >> DPIO_CHV_P1_DIV_SHIFT) & 0x7;
7999         clock.p2 = (cmn_dw13 >> DPIO_CHV_P2_DIV_SHIFT) & 0x1f;
8000
8001         chv_clock(refclk, &clock);
8002
8003         /* clock.dot is the fast clock */
8004         pipe_config->port_clock = clock.dot / 5;
8005 }
8006
8007 static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
8008                                  struct intel_crtc_state *pipe_config)
8009 {
8010         struct drm_device *dev = crtc->base.dev;
8011         struct drm_i915_private *dev_priv = dev->dev_private;
8012         uint32_t tmp;
8013
8014         if (!intel_display_power_is_enabled(dev_priv,
8015                                             POWER_DOMAIN_PIPE(crtc->pipe)))
8016                 return false;
8017
8018         pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
8019         pipe_config->shared_dpll = DPLL_ID_PRIVATE;
8020
8021         tmp = I915_READ(PIPECONF(crtc->pipe));
8022         if (!(tmp & PIPECONF_ENABLE))
8023                 return false;
8024
8025         if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
8026                 switch (tmp & PIPECONF_BPC_MASK) {
8027                 case PIPECONF_6BPC:
8028                         pipe_config->pipe_bpp = 18;
8029                         break;
8030                 case PIPECONF_8BPC:
8031                         pipe_config->pipe_bpp = 24;
8032                         break;
8033                 case PIPECONF_10BPC:
8034                         pipe_config->pipe_bpp = 30;
8035                         break;
8036                 default:
8037                         break;
8038                 }
8039         }
8040
8041         if (IS_VALLEYVIEW(dev) && (tmp & PIPECONF_COLOR_RANGE_SELECT))
8042                 pipe_config->limited_color_range = true;
8043
8044         if (INTEL_INFO(dev)->gen < 4)
8045                 pipe_config->double_wide = tmp & PIPECONF_DOUBLE_WIDE;
8046
8047         intel_get_pipe_timings(crtc, pipe_config);
8048
8049         i9xx_get_pfit_config(crtc, pipe_config);
8050
8051         if (INTEL_INFO(dev)->gen >= 4) {
8052                 tmp = I915_READ(DPLL_MD(crtc->pipe));
8053                 pipe_config->pixel_multiplier =
8054                         ((tmp & DPLL_MD_UDI_MULTIPLIER_MASK)
8055                          >> DPLL_MD_UDI_MULTIPLIER_SHIFT) + 1;
8056                 pipe_config->dpll_hw_state.dpll_md = tmp;
8057         } else if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
8058                 tmp = I915_READ(DPLL(crtc->pipe));
8059                 pipe_config->pixel_multiplier =
8060                         ((tmp & SDVO_MULTIPLIER_MASK)
8061                          >> SDVO_MULTIPLIER_SHIFT_HIRES) + 1;
8062         } else {
8063                 /* Note that on i915G/GM the pixel multiplier is in the sdvo
8064                  * port and will be fixed up in the encoder->get_config
8065                  * function. */
8066                 pipe_config->pixel_multiplier = 1;
8067         }
8068         pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(crtc->pipe));
8069         if (!IS_VALLEYVIEW(dev)) {
8070                 /*
8071                  * DPLL_DVO_2X_MODE must be enabled for both DPLLs
8072                  * on 830. Filter it out here so that we don't
8073                  * report errors due to that.
8074                  */
8075                 if (IS_I830(dev))
8076                         pipe_config->dpll_hw_state.dpll &= ~DPLL_DVO_2X_MODE;
8077
8078                 pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(crtc->pipe));
8079                 pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(crtc->pipe));
8080         } else {
8081                 /* Mask out read-only status bits. */
8082                 pipe_config->dpll_hw_state.dpll &= ~(DPLL_LOCK_VLV |
8083                                                      DPLL_PORTC_READY_MASK |
8084                                                      DPLL_PORTB_READY_MASK);
8085         }
8086
8087         if (IS_CHERRYVIEW(dev))
8088                 chv_crtc_clock_get(crtc, pipe_config);
8089         else if (IS_VALLEYVIEW(dev))
8090                 vlv_crtc_clock_get(crtc, pipe_config);
8091         else
8092                 i9xx_crtc_clock_get(crtc, pipe_config);
8093
8094         return true;
8095 }
8096
8097 static void ironlake_init_pch_refclk(struct drm_device *dev)
8098 {
8099         struct drm_i915_private *dev_priv = dev->dev_private;
8100         struct intel_encoder *encoder;
8101         u32 val, final;
8102         bool has_lvds = false;
8103         bool has_cpu_edp = false;
8104         bool has_panel = false;
8105         bool has_ck505 = false;
8106         bool can_ssc = false;
8107
8108         /* We need to take the global config into account */
8109         for_each_intel_encoder(dev, encoder) {
8110                 switch (encoder->type) {
8111                 case INTEL_OUTPUT_LVDS:
8112                         has_panel = true;
8113                         has_lvds = true;
8114                         break;
8115                 case INTEL_OUTPUT_EDP:
8116                         has_panel = true;
8117                         if (enc_to_dig_port(&encoder->base)->port == PORT_A)
8118                                 has_cpu_edp = true;
8119                         break;
8120                 default:
8121                         break;
8122                 }
8123         }
8124
8125         if (HAS_PCH_IBX(dev)) {
8126                 has_ck505 = dev_priv->vbt.display_clock_mode;
8127                 can_ssc = has_ck505;
8128         } else {
8129                 has_ck505 = false;
8130                 can_ssc = true;
8131         }
8132
8133         DRM_DEBUG_KMS("has_panel %d has_lvds %d has_ck505 %d\n",
8134                       has_panel, has_lvds, has_ck505);
8135
8136         /* Ironlake: try to setup display ref clock before DPLL
8137          * enabling. This is only under driver's control after
8138          * PCH B stepping, previous chipset stepping should be
8139          * ignoring this setting.
8140          */
8141         val = I915_READ(PCH_DREF_CONTROL);
8142
8143         /* As we must carefully and slowly disable/enable each source in turn,
8144          * compute the final state we want first and check if we need to
8145          * make any changes at all.
8146          */
8147         final = val;
8148         final &= ~DREF_NONSPREAD_SOURCE_MASK;
8149         if (has_ck505)
8150                 final |= DREF_NONSPREAD_CK505_ENABLE;
8151         else
8152                 final |= DREF_NONSPREAD_SOURCE_ENABLE;
8153
8154         final &= ~DREF_SSC_SOURCE_MASK;
8155         final &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
8156         final &= ~DREF_SSC1_ENABLE;
8157
8158         if (has_panel) {
8159                 final |= DREF_SSC_SOURCE_ENABLE;
8160
8161                 if (intel_panel_use_ssc(dev_priv) && can_ssc)
8162                         final |= DREF_SSC1_ENABLE;
8163
8164                 if (has_cpu_edp) {
8165                         if (intel_panel_use_ssc(dev_priv) && can_ssc)
8166                                 final |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
8167                         else
8168                                 final |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
8169                 } else
8170                         final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
8171         } else {
8172                 final |= DREF_SSC_SOURCE_DISABLE;
8173                 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
8174         }
8175
8176         if (final == val)
8177                 return;
8178
8179         /* Always enable nonspread source */
8180         val &= ~DREF_NONSPREAD_SOURCE_MASK;
8181
8182         if (has_ck505)
8183                 val |= DREF_NONSPREAD_CK505_ENABLE;
8184         else
8185                 val |= DREF_NONSPREAD_SOURCE_ENABLE;
8186
8187         if (has_panel) {
8188                 val &= ~DREF_SSC_SOURCE_MASK;
8189                 val |= DREF_SSC_SOURCE_ENABLE;
8190
8191                 /* SSC must be turned on before enabling the CPU output  */
8192                 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
8193                         DRM_DEBUG_KMS("Using SSC on panel\n");
8194                         val |= DREF_SSC1_ENABLE;
8195                 } else
8196                         val &= ~DREF_SSC1_ENABLE;
8197
8198                 /* Get SSC going before enabling the outputs */
8199                 I915_WRITE(PCH_DREF_CONTROL, val);
8200                 POSTING_READ(PCH_DREF_CONTROL);
8201                 udelay(200);
8202
8203                 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
8204
8205                 /* Enable CPU source on CPU attached eDP */
8206                 if (has_cpu_edp) {
8207                         if (intel_panel_use_ssc(dev_priv) && can_ssc) {
8208                                 DRM_DEBUG_KMS("Using SSC on eDP\n");
8209                                 val |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
8210                         } else
8211                                 val |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
8212                 } else
8213                         val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
8214
8215                 I915_WRITE(PCH_DREF_CONTROL, val);
8216                 POSTING_READ(PCH_DREF_CONTROL);
8217                 udelay(200);
8218         } else {
8219                 DRM_DEBUG_KMS("Disabling SSC entirely\n");
8220
8221                 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
8222
8223                 /* Turn off CPU output */
8224                 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
8225
8226                 I915_WRITE(PCH_DREF_CONTROL, val);
8227                 POSTING_READ(PCH_DREF_CONTROL);
8228                 udelay(200);
8229
8230                 /* Turn off the SSC source */
8231                 val &= ~DREF_SSC_SOURCE_MASK;
8232                 val |= DREF_SSC_SOURCE_DISABLE;
8233
8234                 /* Turn off SSC1 */
8235                 val &= ~DREF_SSC1_ENABLE;
8236
8237                 I915_WRITE(PCH_DREF_CONTROL, val);
8238                 POSTING_READ(PCH_DREF_CONTROL);
8239                 udelay(200);
8240         }
8241
8242         BUG_ON(val != final);
8243 }
8244
8245 static void lpt_reset_fdi_mphy(struct drm_i915_private *dev_priv)
8246 {
8247         uint32_t tmp;
8248
8249         tmp = I915_READ(SOUTH_CHICKEN2);
8250         tmp |= FDI_MPHY_IOSFSB_RESET_CTL;
8251         I915_WRITE(SOUTH_CHICKEN2, tmp);
8252
8253         if (wait_for_atomic_us(I915_READ(SOUTH_CHICKEN2) &
8254                                FDI_MPHY_IOSFSB_RESET_STATUS, 100))
8255                 DRM_ERROR("FDI mPHY reset assert timeout\n");
8256
8257         tmp = I915_READ(SOUTH_CHICKEN2);
8258         tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL;
8259         I915_WRITE(SOUTH_CHICKEN2, tmp);
8260
8261         if (wait_for_atomic_us((I915_READ(SOUTH_CHICKEN2) &
8262                                 FDI_MPHY_IOSFSB_RESET_STATUS) == 0, 100))
8263                 DRM_ERROR("FDI mPHY reset de-assert timeout\n");
8264 }
8265
8266 /* WaMPhyProgramming:hsw */
8267 static void lpt_program_fdi_mphy(struct drm_i915_private *dev_priv)
8268 {
8269         uint32_t tmp;
8270
8271         tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY);
8272         tmp &= ~(0xFF << 24);
8273         tmp |= (0x12 << 24);
8274         intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY);
8275
8276         tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY);
8277         tmp |= (1 << 11);
8278         intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY);
8279
8280         tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY);
8281         tmp |= (1 << 11);
8282         intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY);
8283
8284         tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY);
8285         tmp |= (1 << 24) | (1 << 21) | (1 << 18);
8286         intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY);
8287
8288         tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY);
8289         tmp |= (1 << 24) | (1 << 21) | (1 << 18);
8290         intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY);
8291
8292         tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY);
8293         tmp &= ~(7 << 13);
8294         tmp |= (5 << 13);
8295         intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY);
8296
8297         tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY);
8298         tmp &= ~(7 << 13);
8299         tmp |= (5 << 13);
8300         intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY);
8301
8302         tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY);
8303         tmp &= ~0xFF;
8304         tmp |= 0x1C;
8305         intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY);
8306
8307         tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY);
8308         tmp &= ~0xFF;
8309         tmp |= 0x1C;
8310         intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY);
8311
8312         tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY);
8313         tmp &= ~(0xFF << 16);
8314         tmp |= (0x1C << 16);
8315         intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY);
8316
8317         tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY);
8318         tmp &= ~(0xFF << 16);
8319         tmp |= (0x1C << 16);
8320         intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY);
8321
8322         tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY);
8323         tmp |= (1 << 27);
8324         intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY);
8325
8326         tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY);
8327         tmp |= (1 << 27);
8328         intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY);
8329
8330         tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY);
8331         tmp &= ~(0xF << 28);
8332         tmp |= (4 << 28);
8333         intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY);
8334
8335         tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY);
8336         tmp &= ~(0xF << 28);
8337         tmp |= (4 << 28);
8338         intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY);
8339 }
8340
8341 /* Implements 3 different sequences from BSpec chapter "Display iCLK
8342  * Programming" based on the parameters passed:
8343  * - Sequence to enable CLKOUT_DP
8344  * - Sequence to enable CLKOUT_DP without spread
8345  * - Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O
8346  */
8347 static void lpt_enable_clkout_dp(struct drm_device *dev, bool with_spread,
8348                                  bool with_fdi)
8349 {
8350         struct drm_i915_private *dev_priv = dev->dev_private;
8351         uint32_t reg, tmp;
8352
8353         if (WARN(with_fdi && !with_spread, "FDI requires downspread\n"))
8354                 with_spread = true;
8355         if (WARN(dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE &&
8356                  with_fdi, "LP PCH doesn't have FDI\n"))
8357                 with_fdi = false;
8358
8359         mutex_lock(&dev_priv->sb_lock);
8360
8361         tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
8362         tmp &= ~SBI_SSCCTL_DISABLE;
8363         tmp |= SBI_SSCCTL_PATHALT;
8364         intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
8365
8366         udelay(24);
8367
8368         if (with_spread) {
8369                 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
8370                 tmp &= ~SBI_SSCCTL_PATHALT;
8371                 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
8372
8373                 if (with_fdi) {
8374                         lpt_reset_fdi_mphy(dev_priv);
8375                         lpt_program_fdi_mphy(dev_priv);
8376                 }
8377         }
8378
8379         reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ?
8380                SBI_GEN0 : SBI_DBUFF0;
8381         tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
8382         tmp |= SBI_GEN0_CFG_BUFFENABLE_DISABLE;
8383         intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
8384
8385         mutex_unlock(&dev_priv->sb_lock);
8386 }
8387
8388 /* Sequence to disable CLKOUT_DP */
8389 static void lpt_disable_clkout_dp(struct drm_device *dev)
8390 {
8391         struct drm_i915_private *dev_priv = dev->dev_private;
8392         uint32_t reg, tmp;
8393
8394         mutex_lock(&dev_priv->sb_lock);
8395
8396         reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ?
8397                SBI_GEN0 : SBI_DBUFF0;
8398         tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
8399         tmp &= ~SBI_GEN0_CFG_BUFFENABLE_DISABLE;
8400         intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
8401
8402         tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
8403         if (!(tmp & SBI_SSCCTL_DISABLE)) {
8404                 if (!(tmp & SBI_SSCCTL_PATHALT)) {
8405                         tmp |= SBI_SSCCTL_PATHALT;
8406                         intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
8407                         udelay(32);
8408                 }
8409                 tmp |= SBI_SSCCTL_DISABLE;
8410                 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
8411         }
8412
8413         mutex_unlock(&dev_priv->sb_lock);
8414 }
8415
8416 static void lpt_init_pch_refclk(struct drm_device *dev)
8417 {
8418         struct intel_encoder *encoder;
8419         bool has_vga = false;
8420
8421         for_each_intel_encoder(dev, encoder) {
8422                 switch (encoder->type) {
8423                 case INTEL_OUTPUT_ANALOG:
8424                         has_vga = true;
8425                         break;
8426                 default:
8427                         break;
8428                 }
8429         }
8430
8431         if (has_vga)
8432                 lpt_enable_clkout_dp(dev, true, true);
8433         else
8434                 lpt_disable_clkout_dp(dev);
8435 }
8436
8437 /*
8438  * Initialize reference clocks when the driver loads
8439  */
8440 void intel_init_pch_refclk(struct drm_device *dev)
8441 {
8442         if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
8443                 ironlake_init_pch_refclk(dev);
8444         else if (HAS_PCH_LPT(dev))
8445                 lpt_init_pch_refclk(dev);
8446 }
8447
8448 static int ironlake_get_refclk(struct intel_crtc_state *crtc_state)
8449 {
8450         struct drm_device *dev = crtc_state->base.crtc->dev;
8451         struct drm_i915_private *dev_priv = dev->dev_private;
8452         struct drm_atomic_state *state = crtc_state->base.state;
8453         struct drm_connector *connector;
8454         struct drm_connector_state *connector_state;
8455         struct intel_encoder *encoder;
8456         int num_connectors = 0, i;
8457         bool is_lvds = false;
8458
8459         for_each_connector_in_state(state, connector, connector_state, i) {
8460                 if (connector_state->crtc != crtc_state->base.crtc)
8461                         continue;
8462
8463                 encoder = to_intel_encoder(connector_state->best_encoder);
8464
8465                 switch (encoder->type) {
8466                 case INTEL_OUTPUT_LVDS:
8467                         is_lvds = true;
8468                         break;
8469                 default:
8470                         break;
8471                 }
8472                 num_connectors++;
8473         }
8474
8475         if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
8476                 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n",
8477                               dev_priv->vbt.lvds_ssc_freq);
8478                 return dev_priv->vbt.lvds_ssc_freq;
8479         }
8480
8481         return 120000;
8482 }
8483
8484 static void ironlake_set_pipeconf(struct drm_crtc *crtc)
8485 {
8486         struct drm_i915_private *dev_priv = crtc->dev->dev_private;
8487         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8488         int pipe = intel_crtc->pipe;
8489         uint32_t val;
8490
8491         val = 0;
8492
8493         switch (intel_crtc->config->pipe_bpp) {
8494         case 18:
8495                 val |= PIPECONF_6BPC;
8496                 break;
8497         case 24:
8498                 val |= PIPECONF_8BPC;
8499                 break;
8500         case 30:
8501                 val |= PIPECONF_10BPC;
8502                 break;
8503         case 36:
8504                 val |= PIPECONF_12BPC;
8505                 break;
8506         default:
8507                 /* Case prevented by intel_choose_pipe_bpp_dither. */
8508                 BUG();
8509         }
8510
8511         if (intel_crtc->config->dither)
8512                 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
8513
8514         if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
8515                 val |= PIPECONF_INTERLACED_ILK;
8516         else
8517                 val |= PIPECONF_PROGRESSIVE;
8518
8519         if (intel_crtc->config->limited_color_range)
8520                 val |= PIPECONF_COLOR_RANGE_SELECT;
8521
8522         I915_WRITE(PIPECONF(pipe), val);
8523         POSTING_READ(PIPECONF(pipe));
8524 }
8525
8526 /*
8527  * Set up the pipe CSC unit.
8528  *
8529  * Currently only full range RGB to limited range RGB conversion
8530  * is supported, but eventually this should handle various
8531  * RGB<->YCbCr scenarios as well.
8532  */
8533 static void intel_set_pipe_csc(struct drm_crtc *crtc)
8534 {
8535         struct drm_device *dev = crtc->dev;
8536         struct drm_i915_private *dev_priv = dev->dev_private;
8537         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8538         int pipe = intel_crtc->pipe;
8539         uint16_t coeff = 0x7800; /* 1.0 */
8540
8541         /*
8542          * TODO: Check what kind of values actually come out of the pipe
8543          * with these coeff/postoff values and adjust to get the best
8544          * accuracy. Perhaps we even need to take the bpc value into
8545          * consideration.
8546          */
8547
8548         if (intel_crtc->config->limited_color_range)
8549                 coeff = ((235 - 16) * (1 << 12) / 255) & 0xff8; /* 0.xxx... */
8550
8551         /*
8552          * GY/GU and RY/RU should be the other way around according
8553          * to BSpec, but reality doesn't agree. Just set them up in
8554          * a way that results in the correct picture.
8555          */
8556         I915_WRITE(PIPE_CSC_COEFF_RY_GY(pipe), coeff << 16);
8557         I915_WRITE(PIPE_CSC_COEFF_BY(pipe), 0);
8558
8559         I915_WRITE(PIPE_CSC_COEFF_RU_GU(pipe), coeff);
8560         I915_WRITE(PIPE_CSC_COEFF_BU(pipe), 0);
8561
8562         I915_WRITE(PIPE_CSC_COEFF_RV_GV(pipe), 0);
8563         I915_WRITE(PIPE_CSC_COEFF_BV(pipe), coeff << 16);
8564
8565         I915_WRITE(PIPE_CSC_PREOFF_HI(pipe), 0);
8566         I915_WRITE(PIPE_CSC_PREOFF_ME(pipe), 0);
8567         I915_WRITE(PIPE_CSC_PREOFF_LO(pipe), 0);
8568
8569         if (INTEL_INFO(dev)->gen > 6) {
8570                 uint16_t postoff = 0;
8571
8572                 if (intel_crtc->config->limited_color_range)
8573                         postoff = (16 * (1 << 12) / 255) & 0x1fff;
8574
8575                 I915_WRITE(PIPE_CSC_POSTOFF_HI(pipe), postoff);
8576                 I915_WRITE(PIPE_CSC_POSTOFF_ME(pipe), postoff);
8577                 I915_WRITE(PIPE_CSC_POSTOFF_LO(pipe), postoff);
8578
8579                 I915_WRITE(PIPE_CSC_MODE(pipe), 0);
8580         } else {
8581                 uint32_t mode = CSC_MODE_YUV_TO_RGB;
8582
8583                 if (intel_crtc->config->limited_color_range)
8584                         mode |= CSC_BLACK_SCREEN_OFFSET;
8585
8586                 I915_WRITE(PIPE_CSC_MODE(pipe), mode);
8587         }
8588 }
8589
8590 static void haswell_set_pipeconf(struct drm_crtc *crtc)
8591 {
8592         struct drm_device *dev = crtc->dev;
8593         struct drm_i915_private *dev_priv = dev->dev_private;
8594         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8595         enum pipe pipe = intel_crtc->pipe;
8596         enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
8597         uint32_t val;
8598
8599         val = 0;
8600
8601         if (IS_HASWELL(dev) && intel_crtc->config->dither)
8602                 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
8603
8604         if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
8605                 val |= PIPECONF_INTERLACED_ILK;
8606         else
8607                 val |= PIPECONF_PROGRESSIVE;
8608
8609         I915_WRITE(PIPECONF(cpu_transcoder), val);
8610         POSTING_READ(PIPECONF(cpu_transcoder));
8611
8612         I915_WRITE(GAMMA_MODE(intel_crtc->pipe), GAMMA_MODE_MODE_8BIT);
8613         POSTING_READ(GAMMA_MODE(intel_crtc->pipe));
8614
8615         if (IS_BROADWELL(dev) || INTEL_INFO(dev)->gen >= 9) {
8616                 val = 0;
8617
8618                 switch (intel_crtc->config->pipe_bpp) {
8619                 case 18:
8620                         val |= PIPEMISC_DITHER_6_BPC;
8621                         break;
8622                 case 24:
8623                         val |= PIPEMISC_DITHER_8_BPC;
8624                         break;
8625                 case 30:
8626                         val |= PIPEMISC_DITHER_10_BPC;
8627                         break;
8628                 case 36:
8629                         val |= PIPEMISC_DITHER_12_BPC;
8630                         break;
8631                 default:
8632                         /* Case prevented by pipe_config_set_bpp. */
8633                         BUG();
8634                 }
8635
8636                 if (intel_crtc->config->dither)
8637                         val |= PIPEMISC_DITHER_ENABLE | PIPEMISC_DITHER_TYPE_SP;
8638
8639                 I915_WRITE(PIPEMISC(pipe), val);
8640         }
8641 }
8642
8643 static bool ironlake_compute_clocks(struct drm_crtc *crtc,
8644                                     struct intel_crtc_state *crtc_state,
8645                                     intel_clock_t *clock,
8646                                     bool *has_reduced_clock,
8647                                     intel_clock_t *reduced_clock)
8648 {
8649         struct drm_device *dev = crtc->dev;
8650         struct drm_i915_private *dev_priv = dev->dev_private;
8651         int refclk;
8652         const intel_limit_t *limit;
8653         bool ret, is_lvds = false;
8654
8655         is_lvds = intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS);
8656
8657         refclk = ironlake_get_refclk(crtc_state);
8658
8659         /*
8660          * Returns a set of divisors for the desired target clock with the given
8661          * refclk, or FALSE.  The returned values represent the clock equation:
8662          * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
8663          */
8664         limit = intel_limit(crtc_state, refclk);
8665         ret = dev_priv->display.find_dpll(limit, crtc_state,
8666                                           crtc_state->port_clock,
8667                                           refclk, NULL, clock);
8668         if (!ret)
8669                 return false;
8670
8671         if (is_lvds && dev_priv->lvds_downclock_avail) {
8672                 /*
8673                  * Ensure we match the reduced clock's P to the target clock.
8674                  * If the clocks don't match, we can't switch the display clock
8675                  * by using the FP0/FP1. In such case we will disable the LVDS
8676                  * downclock feature.
8677                 */
8678                 *has_reduced_clock =
8679                         dev_priv->display.find_dpll(limit, crtc_state,
8680                                                     dev_priv->lvds_downclock,
8681                                                     refclk, clock,
8682                                                     reduced_clock);
8683         }
8684
8685         return true;
8686 }
8687
8688 int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp)
8689 {
8690         /*
8691          * Account for spread spectrum to avoid
8692          * oversubscribing the link. Max center spread
8693          * is 2.5%; use 5% for safety's sake.
8694          */
8695         u32 bps = target_clock * bpp * 21 / 20;
8696         return DIV_ROUND_UP(bps, link_bw * 8);
8697 }
8698
8699 static bool ironlake_needs_fb_cb_tune(struct dpll *dpll, int factor)
8700 {
8701         return i9xx_dpll_compute_m(dpll) < factor * dpll->n;
8702 }
8703
8704 static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc,
8705                                       struct intel_crtc_state *crtc_state,
8706                                       u32 *fp,
8707                                       intel_clock_t *reduced_clock, u32 *fp2)
8708 {
8709         struct drm_crtc *crtc = &intel_crtc->base;
8710         struct drm_device *dev = crtc->dev;
8711         struct drm_i915_private *dev_priv = dev->dev_private;
8712         struct drm_atomic_state *state = crtc_state->base.state;
8713         struct drm_connector *connector;
8714         struct drm_connector_state *connector_state;
8715         struct intel_encoder *encoder;
8716         uint32_t dpll;
8717         int factor, num_connectors = 0, i;
8718         bool is_lvds = false, is_sdvo = false;
8719
8720         for_each_connector_in_state(state, connector, connector_state, i) {
8721                 if (connector_state->crtc != crtc_state->base.crtc)
8722                         continue;
8723
8724                 encoder = to_intel_encoder(connector_state->best_encoder);
8725
8726                 switch (encoder->type) {
8727                 case INTEL_OUTPUT_LVDS:
8728                         is_lvds = true;
8729                         break;
8730                 case INTEL_OUTPUT_SDVO:
8731                 case INTEL_OUTPUT_HDMI:
8732                         is_sdvo = true;
8733                         break;
8734                 default:
8735                         break;
8736                 }
8737
8738                 num_connectors++;
8739         }
8740
8741         /* Enable autotuning of the PLL clock (if permissible) */
8742         factor = 21;
8743         if (is_lvds) {
8744                 if ((intel_panel_use_ssc(dev_priv) &&
8745                      dev_priv->vbt.lvds_ssc_freq == 100000) ||
8746                     (HAS_PCH_IBX(dev) && intel_is_dual_link_lvds(dev)))
8747                         factor = 25;
8748         } else if (crtc_state->sdvo_tv_clock)
8749                 factor = 20;
8750
8751         if (ironlake_needs_fb_cb_tune(&crtc_state->dpll, factor))
8752                 *fp |= FP_CB_TUNE;
8753
8754         if (fp2 && (reduced_clock->m < factor * reduced_clock->n))
8755                 *fp2 |= FP_CB_TUNE;
8756
8757         dpll = 0;
8758
8759         if (is_lvds)
8760                 dpll |= DPLLB_MODE_LVDS;
8761         else
8762                 dpll |= DPLLB_MODE_DAC_SERIAL;
8763
8764         dpll |= (crtc_state->pixel_multiplier - 1)
8765                 << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
8766
8767         if (is_sdvo)
8768                 dpll |= DPLL_SDVO_HIGH_SPEED;
8769         if (crtc_state->has_dp_encoder)
8770                 dpll |= DPLL_SDVO_HIGH_SPEED;
8771
8772         /* compute bitmask from p1 value */
8773         dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
8774         /* also FPA1 */
8775         dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
8776
8777         switch (crtc_state->dpll.p2) {
8778         case 5:
8779                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
8780                 break;
8781         case 7:
8782                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
8783                 break;
8784         case 10:
8785                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
8786                 break;
8787         case 14:
8788                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
8789                 break;
8790         }
8791
8792         if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
8793                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
8794         else
8795                 dpll |= PLL_REF_INPUT_DREFCLK;
8796
8797         return dpll | DPLL_VCO_ENABLE;
8798 }
8799
8800 static int ironlake_crtc_compute_clock(struct intel_crtc *crtc,
8801                                        struct intel_crtc_state *crtc_state)
8802 {
8803         struct drm_device *dev = crtc->base.dev;
8804         intel_clock_t clock, reduced_clock;
8805         u32 dpll = 0, fp = 0, fp2 = 0;
8806         bool ok, has_reduced_clock = false;
8807         bool is_lvds = false;
8808         struct intel_shared_dpll *pll;
8809
8810         memset(&crtc_state->dpll_hw_state, 0,
8811                sizeof(crtc_state->dpll_hw_state));
8812
8813         is_lvds = intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS);
8814
8815         WARN(!(HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)),
8816              "Unexpected PCH type %d\n", INTEL_PCH_TYPE(dev));
8817
8818         ok = ironlake_compute_clocks(&crtc->base, crtc_state, &clock,
8819                                      &has_reduced_clock, &reduced_clock);
8820         if (!ok && !crtc_state->clock_set) {
8821                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
8822                 return -EINVAL;
8823         }
8824         /* Compat-code for transition, will disappear. */
8825         if (!crtc_state->clock_set) {
8826                 crtc_state->dpll.n = clock.n;
8827                 crtc_state->dpll.m1 = clock.m1;
8828                 crtc_state->dpll.m2 = clock.m2;
8829                 crtc_state->dpll.p1 = clock.p1;
8830                 crtc_state->dpll.p2 = clock.p2;
8831         }
8832
8833         /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
8834         if (crtc_state->has_pch_encoder) {
8835                 fp = i9xx_dpll_compute_fp(&crtc_state->dpll);
8836                 if (has_reduced_clock)
8837                         fp2 = i9xx_dpll_compute_fp(&reduced_clock);
8838
8839                 dpll = ironlake_compute_dpll(crtc, crtc_state,
8840                                              &fp, &reduced_clock,
8841                                              has_reduced_clock ? &fp2 : NULL);
8842
8843                 crtc_state->dpll_hw_state.dpll = dpll;
8844                 crtc_state->dpll_hw_state.fp0 = fp;
8845                 if (has_reduced_clock)
8846                         crtc_state->dpll_hw_state.fp1 = fp2;
8847                 else
8848                         crtc_state->dpll_hw_state.fp1 = fp;
8849
8850                 pll = intel_get_shared_dpll(crtc, crtc_state);
8851                 if (pll == NULL) {
8852                         DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
8853                                          pipe_name(crtc->pipe));
8854                         return -EINVAL;
8855                 }
8856         }
8857
8858         if (is_lvds && has_reduced_clock)
8859                 crtc->lowfreq_avail = true;
8860         else
8861                 crtc->lowfreq_avail = false;
8862
8863         return 0;
8864 }
8865
8866 static void intel_pch_transcoder_get_m_n(struct intel_crtc *crtc,
8867                                          struct intel_link_m_n *m_n)
8868 {
8869         struct drm_device *dev = crtc->base.dev;
8870         struct drm_i915_private *dev_priv = dev->dev_private;
8871         enum pipe pipe = crtc->pipe;
8872
8873         m_n->link_m = I915_READ(PCH_TRANS_LINK_M1(pipe));
8874         m_n->link_n = I915_READ(PCH_TRANS_LINK_N1(pipe));
8875         m_n->gmch_m = I915_READ(PCH_TRANS_DATA_M1(pipe))
8876                 & ~TU_SIZE_MASK;
8877         m_n->gmch_n = I915_READ(PCH_TRANS_DATA_N1(pipe));
8878         m_n->tu = ((I915_READ(PCH_TRANS_DATA_M1(pipe))
8879                     & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
8880 }
8881
8882 static void intel_cpu_transcoder_get_m_n(struct intel_crtc *crtc,
8883                                          enum transcoder transcoder,
8884                                          struct intel_link_m_n *m_n,
8885                                          struct intel_link_m_n *m2_n2)
8886 {
8887         struct drm_device *dev = crtc->base.dev;
8888         struct drm_i915_private *dev_priv = dev->dev_private;
8889         enum pipe pipe = crtc->pipe;
8890
8891         if (INTEL_INFO(dev)->gen >= 5) {
8892                 m_n->link_m = I915_READ(PIPE_LINK_M1(transcoder));
8893                 m_n->link_n = I915_READ(PIPE_LINK_N1(transcoder));
8894                 m_n->gmch_m = I915_READ(PIPE_DATA_M1(transcoder))
8895                         & ~TU_SIZE_MASK;
8896                 m_n->gmch_n = I915_READ(PIPE_DATA_N1(transcoder));
8897                 m_n->tu = ((I915_READ(PIPE_DATA_M1(transcoder))
8898                             & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
8899                 /* Read M2_N2 registers only for gen < 8 (M2_N2 available for
8900                  * gen < 8) and if DRRS is supported (to make sure the
8901                  * registers are not unnecessarily read).
8902                  */
8903                 if (m2_n2 && INTEL_INFO(dev)->gen < 8 &&
8904                         crtc->config->has_drrs) {
8905                         m2_n2->link_m = I915_READ(PIPE_LINK_M2(transcoder));
8906                         m2_n2->link_n = I915_READ(PIPE_LINK_N2(transcoder));
8907                         m2_n2->gmch_m = I915_READ(PIPE_DATA_M2(transcoder))
8908                                         & ~TU_SIZE_MASK;
8909                         m2_n2->gmch_n = I915_READ(PIPE_DATA_N2(transcoder));
8910                         m2_n2->tu = ((I915_READ(PIPE_DATA_M2(transcoder))
8911                                         & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
8912                 }
8913         } else {
8914                 m_n->link_m = I915_READ(PIPE_LINK_M_G4X(pipe));
8915                 m_n->link_n = I915_READ(PIPE_LINK_N_G4X(pipe));
8916                 m_n->gmch_m = I915_READ(PIPE_DATA_M_G4X(pipe))
8917                         & ~TU_SIZE_MASK;
8918                 m_n->gmch_n = I915_READ(PIPE_DATA_N_G4X(pipe));
8919                 m_n->tu = ((I915_READ(PIPE_DATA_M_G4X(pipe))
8920                             & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
8921         }
8922 }
8923
8924 void intel_dp_get_m_n(struct intel_crtc *crtc,
8925                       struct intel_crtc_state *pipe_config)
8926 {
8927         if (pipe_config->has_pch_encoder)
8928                 intel_pch_transcoder_get_m_n(crtc, &pipe_config->dp_m_n);
8929         else
8930                 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
8931                                              &pipe_config->dp_m_n,
8932                                              &pipe_config->dp_m2_n2);
8933 }
8934
8935 static void ironlake_get_fdi_m_n_config(struct intel_crtc *crtc,
8936                                         struct intel_crtc_state *pipe_config)
8937 {
8938         intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
8939                                      &pipe_config->fdi_m_n, NULL);
8940 }
8941
8942 static void skylake_get_pfit_config(struct intel_crtc *crtc,
8943                                     struct intel_crtc_state *pipe_config)
8944 {
8945         struct drm_device *dev = crtc->base.dev;
8946         struct drm_i915_private *dev_priv = dev->dev_private;
8947         struct intel_crtc_scaler_state *scaler_state = &pipe_config->scaler_state;
8948         uint32_t ps_ctrl = 0;
8949         int id = -1;
8950         int i;
8951
8952         /* find scaler attached to this pipe */
8953         for (i = 0; i < crtc->num_scalers; i++) {
8954                 ps_ctrl = I915_READ(SKL_PS_CTRL(crtc->pipe, i));
8955                 if (ps_ctrl & PS_SCALER_EN && !(ps_ctrl & PS_PLANE_SEL_MASK)) {
8956                         id = i;
8957                         pipe_config->pch_pfit.enabled = true;
8958                         pipe_config->pch_pfit.pos = I915_READ(SKL_PS_WIN_POS(crtc->pipe, i));
8959                         pipe_config->pch_pfit.size = I915_READ(SKL_PS_WIN_SZ(crtc->pipe, i));
8960                         break;
8961                 }
8962         }
8963
8964         scaler_state->scaler_id = id;
8965         if (id >= 0) {
8966                 scaler_state->scaler_users |= (1 << SKL_CRTC_INDEX);
8967         } else {
8968                 scaler_state->scaler_users &= ~(1 << SKL_CRTC_INDEX);
8969         }
8970 }
8971
8972 static void
8973 skylake_get_initial_plane_config(struct intel_crtc *crtc,
8974                                  struct intel_initial_plane_config *plane_config)
8975 {
8976         struct drm_device *dev = crtc->base.dev;
8977         struct drm_i915_private *dev_priv = dev->dev_private;
8978         u32 val, base, offset, stride_mult, tiling;
8979         int pipe = crtc->pipe;
8980         int fourcc, pixel_format;
8981         unsigned int aligned_height;
8982         struct drm_framebuffer *fb;
8983         struct intel_framebuffer *intel_fb;
8984
8985         intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
8986         if (!intel_fb) {
8987                 DRM_DEBUG_KMS("failed to alloc fb\n");
8988                 return;
8989         }
8990
8991         fb = &intel_fb->base;
8992
8993         val = I915_READ(PLANE_CTL(pipe, 0));
8994         if (!(val & PLANE_CTL_ENABLE))
8995                 goto error;
8996
8997         pixel_format = val & PLANE_CTL_FORMAT_MASK;
8998         fourcc = skl_format_to_fourcc(pixel_format,
8999                                       val & PLANE_CTL_ORDER_RGBX,
9000                                       val & PLANE_CTL_ALPHA_MASK);
9001         fb->pixel_format = fourcc;
9002         fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
9003
9004         tiling = val & PLANE_CTL_TILED_MASK;
9005         switch (tiling) {
9006         case PLANE_CTL_TILED_LINEAR:
9007                 fb->modifier[0] = DRM_FORMAT_MOD_NONE;
9008                 break;
9009         case PLANE_CTL_TILED_X:
9010                 plane_config->tiling = I915_TILING_X;
9011                 fb->modifier[0] = I915_FORMAT_MOD_X_TILED;
9012                 break;
9013         case PLANE_CTL_TILED_Y:
9014                 fb->modifier[0] = I915_FORMAT_MOD_Y_TILED;
9015                 break;
9016         case PLANE_CTL_TILED_YF:
9017                 fb->modifier[0] = I915_FORMAT_MOD_Yf_TILED;
9018                 break;
9019         default:
9020                 MISSING_CASE(tiling);
9021                 goto error;
9022         }
9023
9024         base = I915_READ(PLANE_SURF(pipe, 0)) & 0xfffff000;
9025         plane_config->base = base;
9026
9027         offset = I915_READ(PLANE_OFFSET(pipe, 0));
9028
9029         val = I915_READ(PLANE_SIZE(pipe, 0));
9030         fb->height = ((val >> 16) & 0xfff) + 1;
9031         fb->width = ((val >> 0) & 0x1fff) + 1;
9032
9033         val = I915_READ(PLANE_STRIDE(pipe, 0));
9034         stride_mult = intel_fb_stride_alignment(dev, fb->modifier[0],
9035                                                 fb->pixel_format);
9036         fb->pitches[0] = (val & 0x3ff) * stride_mult;
9037
9038         aligned_height = intel_fb_align_height(dev, fb->height,
9039                                                fb->pixel_format,
9040                                                fb->modifier[0]);
9041
9042         plane_config->size = fb->pitches[0] * aligned_height;
9043
9044         DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
9045                       pipe_name(pipe), fb->width, fb->height,
9046                       fb->bits_per_pixel, base, fb->pitches[0],
9047                       plane_config->size);
9048
9049         plane_config->fb = intel_fb;
9050         return;
9051
9052 error:
9053         kfree(fb);
9054 }
9055
9056 static void ironlake_get_pfit_config(struct intel_crtc *crtc,
9057                                      struct intel_crtc_state *pipe_config)
9058 {
9059         struct drm_device *dev = crtc->base.dev;
9060         struct drm_i915_private *dev_priv = dev->dev_private;
9061         uint32_t tmp;
9062
9063         tmp = I915_READ(PF_CTL(crtc->pipe));
9064
9065         if (tmp & PF_ENABLE) {
9066                 pipe_config->pch_pfit.enabled = true;
9067                 pipe_config->pch_pfit.pos = I915_READ(PF_WIN_POS(crtc->pipe));
9068                 pipe_config->pch_pfit.size = I915_READ(PF_WIN_SZ(crtc->pipe));
9069
9070                 /* We currently do not free assignements of panel fitters on
9071                  * ivb/hsw (since we don't use the higher upscaling modes which
9072                  * differentiates them) so just WARN about this case for now. */
9073                 if (IS_GEN7(dev)) {
9074                         WARN_ON((tmp & PF_PIPE_SEL_MASK_IVB) !=
9075                                 PF_PIPE_SEL_IVB(crtc->pipe));
9076                 }
9077         }
9078 }
9079
9080 static void
9081 ironlake_get_initial_plane_config(struct intel_crtc *crtc,
9082                                   struct intel_initial_plane_config *plane_config)
9083 {
9084         struct drm_device *dev = crtc->base.dev;
9085         struct drm_i915_private *dev_priv = dev->dev_private;
9086         u32 val, base, offset;
9087         int pipe = crtc->pipe;
9088         int fourcc, pixel_format;
9089         unsigned int aligned_height;
9090         struct drm_framebuffer *fb;
9091         struct intel_framebuffer *intel_fb;
9092
9093         val = I915_READ(DSPCNTR(pipe));
9094         if (!(val & DISPLAY_PLANE_ENABLE))
9095                 return;
9096
9097         intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
9098         if (!intel_fb) {
9099                 DRM_DEBUG_KMS("failed to alloc fb\n");
9100                 return;
9101         }
9102
9103         fb = &intel_fb->base;
9104
9105         if (INTEL_INFO(dev)->gen >= 4) {
9106                 if (val & DISPPLANE_TILED) {
9107                         plane_config->tiling = I915_TILING_X;
9108                         fb->modifier[0] = I915_FORMAT_MOD_X_TILED;
9109                 }
9110         }
9111
9112         pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
9113         fourcc = i9xx_format_to_fourcc(pixel_format);
9114         fb->pixel_format = fourcc;
9115         fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
9116
9117         base = I915_READ(DSPSURF(pipe)) & 0xfffff000;
9118         if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
9119                 offset = I915_READ(DSPOFFSET(pipe));
9120         } else {
9121                 if (plane_config->tiling)
9122                         offset = I915_READ(DSPTILEOFF(pipe));
9123                 else
9124                         offset = I915_READ(DSPLINOFF(pipe));
9125         }
9126         plane_config->base = base;
9127
9128         val = I915_READ(PIPESRC(pipe));
9129         fb->width = ((val >> 16) & 0xfff) + 1;
9130         fb->height = ((val >> 0) & 0xfff) + 1;
9131
9132         val = I915_READ(DSPSTRIDE(pipe));
9133         fb->pitches[0] = val & 0xffffffc0;
9134
9135         aligned_height = intel_fb_align_height(dev, fb->height,
9136                                                fb->pixel_format,
9137                                                fb->modifier[0]);
9138
9139         plane_config->size = fb->pitches[0] * aligned_height;
9140
9141         DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
9142                       pipe_name(pipe), fb->width, fb->height,
9143                       fb->bits_per_pixel, base, fb->pitches[0],
9144                       plane_config->size);
9145
9146         plane_config->fb = intel_fb;
9147 }
9148
9149 static bool ironlake_get_pipe_config(struct intel_crtc *crtc,
9150                                      struct intel_crtc_state *pipe_config)
9151 {
9152         struct drm_device *dev = crtc->base.dev;
9153         struct drm_i915_private *dev_priv = dev->dev_private;
9154         uint32_t tmp;
9155
9156         if (!intel_display_power_is_enabled(dev_priv,
9157                                             POWER_DOMAIN_PIPE(crtc->pipe)))
9158                 return false;
9159
9160         pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
9161         pipe_config->shared_dpll = DPLL_ID_PRIVATE;
9162
9163         tmp = I915_READ(PIPECONF(crtc->pipe));
9164         if (!(tmp & PIPECONF_ENABLE))
9165                 return false;
9166
9167         switch (tmp & PIPECONF_BPC_MASK) {
9168         case PIPECONF_6BPC:
9169                 pipe_config->pipe_bpp = 18;
9170                 break;
9171         case PIPECONF_8BPC:
9172                 pipe_config->pipe_bpp = 24;
9173                 break;
9174         case PIPECONF_10BPC:
9175                 pipe_config->pipe_bpp = 30;
9176                 break;
9177         case PIPECONF_12BPC:
9178                 pipe_config->pipe_bpp = 36;
9179                 break;
9180         default:
9181                 break;
9182         }
9183
9184         if (tmp & PIPECONF_COLOR_RANGE_SELECT)
9185                 pipe_config->limited_color_range = true;
9186
9187         if (I915_READ(PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) {
9188                 struct intel_shared_dpll *pll;
9189
9190                 pipe_config->has_pch_encoder = true;
9191
9192                 tmp = I915_READ(FDI_RX_CTL(crtc->pipe));
9193                 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
9194                                           FDI_DP_PORT_WIDTH_SHIFT) + 1;
9195
9196                 ironlake_get_fdi_m_n_config(crtc, pipe_config);
9197
9198                 if (HAS_PCH_IBX(dev_priv->dev)) {
9199                         pipe_config->shared_dpll =
9200                                 (enum intel_dpll_id) crtc->pipe;
9201                 } else {
9202                         tmp = I915_READ(PCH_DPLL_SEL);
9203                         if (tmp & TRANS_DPLLB_SEL(crtc->pipe))
9204                                 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_B;
9205                         else
9206                                 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_A;
9207                 }
9208
9209                 pll = &dev_priv->shared_dplls[pipe_config->shared_dpll];
9210
9211                 WARN_ON(!pll->get_hw_state(dev_priv, pll,
9212                                            &pipe_config->dpll_hw_state));
9213
9214                 tmp = pipe_config->dpll_hw_state.dpll;
9215                 pipe_config->pixel_multiplier =
9216                         ((tmp & PLL_REF_SDVO_HDMI_MULTIPLIER_MASK)
9217                          >> PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT) + 1;
9218
9219                 ironlake_pch_clock_get(crtc, pipe_config);
9220         } else {
9221                 pipe_config->pixel_multiplier = 1;
9222         }
9223
9224         intel_get_pipe_timings(crtc, pipe_config);
9225
9226         ironlake_get_pfit_config(crtc, pipe_config);
9227
9228         return true;
9229 }
9230
9231 static void assert_can_disable_lcpll(struct drm_i915_private *dev_priv)
9232 {
9233         struct drm_device *dev = dev_priv->dev;
9234         struct intel_crtc *crtc;
9235
9236         for_each_intel_crtc(dev, crtc)
9237                 I915_STATE_WARN(crtc->active, "CRTC for pipe %c enabled\n",
9238                      pipe_name(crtc->pipe));
9239
9240         I915_STATE_WARN(I915_READ(HSW_PWR_WELL_DRIVER), "Power well on\n");
9241         I915_STATE_WARN(I915_READ(SPLL_CTL) & SPLL_PLL_ENABLE, "SPLL enabled\n");
9242         I915_STATE_WARN(I915_READ(WRPLL_CTL1) & WRPLL_PLL_ENABLE, "WRPLL1 enabled\n");
9243         I915_STATE_WARN(I915_READ(WRPLL_CTL2) & WRPLL_PLL_ENABLE, "WRPLL2 enabled\n");
9244         I915_STATE_WARN(I915_READ(PCH_PP_STATUS) & PP_ON, "Panel power on\n");
9245         I915_STATE_WARN(I915_READ(BLC_PWM_CPU_CTL2) & BLM_PWM_ENABLE,
9246              "CPU PWM1 enabled\n");
9247         if (IS_HASWELL(dev))
9248                 I915_STATE_WARN(I915_READ(HSW_BLC_PWM2_CTL) & BLM_PWM_ENABLE,
9249                      "CPU PWM2 enabled\n");
9250         I915_STATE_WARN(I915_READ(BLC_PWM_PCH_CTL1) & BLM_PCH_PWM_ENABLE,
9251              "PCH PWM1 enabled\n");
9252         I915_STATE_WARN(I915_READ(UTIL_PIN_CTL) & UTIL_PIN_ENABLE,
9253              "Utility pin enabled\n");
9254         I915_STATE_WARN(I915_READ(PCH_GTC_CTL) & PCH_GTC_ENABLE, "PCH GTC enabled\n");
9255
9256         /*
9257          * In theory we can still leave IRQs enabled, as long as only the HPD
9258          * interrupts remain enabled. We used to check for that, but since it's
9259          * gen-specific and since we only disable LCPLL after we fully disable
9260          * the interrupts, the check below should be enough.
9261          */
9262         I915_STATE_WARN(intel_irqs_enabled(dev_priv), "IRQs enabled\n");
9263 }
9264
9265 static uint32_t hsw_read_dcomp(struct drm_i915_private *dev_priv)
9266 {
9267         struct drm_device *dev = dev_priv->dev;
9268
9269         if (IS_HASWELL(dev))
9270                 return I915_READ(D_COMP_HSW);
9271         else
9272                 return I915_READ(D_COMP_BDW);
9273 }
9274
9275 static void hsw_write_dcomp(struct drm_i915_private *dev_priv, uint32_t val)
9276 {
9277         struct drm_device *dev = dev_priv->dev;
9278
9279         if (IS_HASWELL(dev)) {
9280                 mutex_lock(&dev_priv->rps.hw_lock);
9281                 if (sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_D_COMP,
9282                                             val))
9283                         DRM_ERROR("Failed to write to D_COMP\n");
9284                 mutex_unlock(&dev_priv->rps.hw_lock);
9285         } else {
9286                 I915_WRITE(D_COMP_BDW, val);
9287                 POSTING_READ(D_COMP_BDW);
9288         }
9289 }
9290
9291 /*
9292  * This function implements pieces of two sequences from BSpec:
9293  * - Sequence for display software to disable LCPLL
9294  * - Sequence for display software to allow package C8+
9295  * The steps implemented here are just the steps that actually touch the LCPLL
9296  * register. Callers should take care of disabling all the display engine
9297  * functions, doing the mode unset, fixing interrupts, etc.
9298  */
9299 static void hsw_disable_lcpll(struct drm_i915_private *dev_priv,
9300                               bool switch_to_fclk, bool allow_power_down)
9301 {
9302         uint32_t val;
9303
9304         assert_can_disable_lcpll(dev_priv);
9305
9306         val = I915_READ(LCPLL_CTL);
9307
9308         if (switch_to_fclk) {
9309                 val |= LCPLL_CD_SOURCE_FCLK;
9310                 I915_WRITE(LCPLL_CTL, val);
9311
9312                 if (wait_for_atomic_us(I915_READ(LCPLL_CTL) &
9313                                        LCPLL_CD_SOURCE_FCLK_DONE, 1))
9314                         DRM_ERROR("Switching to FCLK failed\n");
9315
9316                 val = I915_READ(LCPLL_CTL);
9317         }
9318
9319         val |= LCPLL_PLL_DISABLE;
9320         I915_WRITE(LCPLL_CTL, val);
9321         POSTING_READ(LCPLL_CTL);
9322
9323         if (wait_for((I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK) == 0, 1))
9324                 DRM_ERROR("LCPLL still locked\n");
9325
9326         val = hsw_read_dcomp(dev_priv);
9327         val |= D_COMP_COMP_DISABLE;
9328         hsw_write_dcomp(dev_priv, val);
9329         ndelay(100);
9330
9331         if (wait_for((hsw_read_dcomp(dev_priv) & D_COMP_RCOMP_IN_PROGRESS) == 0,
9332                      1))
9333                 DRM_ERROR("D_COMP RCOMP still in progress\n");
9334
9335         if (allow_power_down) {
9336                 val = I915_READ(LCPLL_CTL);
9337                 val |= LCPLL_POWER_DOWN_ALLOW;
9338                 I915_WRITE(LCPLL_CTL, val);
9339                 POSTING_READ(LCPLL_CTL);
9340         }
9341 }
9342
9343 /*
9344  * Fully restores LCPLL, disallowing power down and switching back to LCPLL
9345  * source.
9346  */
9347 static void hsw_restore_lcpll(struct drm_i915_private *dev_priv)
9348 {
9349         uint32_t val;
9350
9351         val = I915_READ(LCPLL_CTL);
9352
9353         if ((val & (LCPLL_PLL_LOCK | LCPLL_PLL_DISABLE | LCPLL_CD_SOURCE_FCLK |
9354                     LCPLL_POWER_DOWN_ALLOW)) == LCPLL_PLL_LOCK)
9355                 return;
9356
9357         /*
9358          * Make sure we're not on PC8 state before disabling PC8, otherwise
9359          * we'll hang the machine. To prevent PC8 state, just enable force_wake.
9360          */
9361         intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
9362
9363         if (val & LCPLL_POWER_DOWN_ALLOW) {
9364                 val &= ~LCPLL_POWER_DOWN_ALLOW;
9365                 I915_WRITE(LCPLL_CTL, val);
9366                 POSTING_READ(LCPLL_CTL);
9367         }
9368
9369         val = hsw_read_dcomp(dev_priv);
9370         val |= D_COMP_COMP_FORCE;
9371         val &= ~D_COMP_COMP_DISABLE;
9372         hsw_write_dcomp(dev_priv, val);
9373
9374         val = I915_READ(LCPLL_CTL);
9375         val &= ~LCPLL_PLL_DISABLE;
9376         I915_WRITE(LCPLL_CTL, val);
9377
9378         if (wait_for(I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK, 5))
9379                 DRM_ERROR("LCPLL not locked yet\n");
9380
9381         if (val & LCPLL_CD_SOURCE_FCLK) {
9382                 val = I915_READ(LCPLL_CTL);
9383                 val &= ~LCPLL_CD_SOURCE_FCLK;
9384                 I915_WRITE(LCPLL_CTL, val);
9385
9386                 if (wait_for_atomic_us((I915_READ(LCPLL_CTL) &
9387                                         LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1))
9388                         DRM_ERROR("Switching back to LCPLL failed\n");
9389         }
9390
9391         intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
9392         intel_update_cdclk(dev_priv->dev);
9393 }
9394
9395 /*
9396  * Package states C8 and deeper are really deep PC states that can only be
9397  * reached when all the devices on the system allow it, so even if the graphics
9398  * device allows PC8+, it doesn't mean the system will actually get to these
9399  * states. Our driver only allows PC8+ when going into runtime PM.
9400  *
9401  * The requirements for PC8+ are that all the outputs are disabled, the power
9402  * well is disabled and most interrupts are disabled, and these are also
9403  * requirements for runtime PM. When these conditions are met, we manually do
9404  * the other conditions: disable the interrupts, clocks and switch LCPLL refclk
9405  * to Fclk. If we're in PC8+ and we get an non-hotplug interrupt, we can hard
9406  * hang the machine.
9407  *
9408  * When we really reach PC8 or deeper states (not just when we allow it) we lose
9409  * the state of some registers, so when we come back from PC8+ we need to
9410  * restore this state. We don't get into PC8+ if we're not in RC6, so we don't
9411  * need to take care of the registers kept by RC6. Notice that this happens even
9412  * if we don't put the device in PCI D3 state (which is what currently happens
9413  * because of the runtime PM support).
9414  *
9415  * For more, read "Display Sequences for Package C8" on the hardware
9416  * documentation.
9417  */
9418 void hsw_enable_pc8(struct drm_i915_private *dev_priv)
9419 {
9420         struct drm_device *dev = dev_priv->dev;
9421         uint32_t val;
9422
9423         DRM_DEBUG_KMS("Enabling package C8+\n");
9424
9425         if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
9426                 val = I915_READ(SOUTH_DSPCLK_GATE_D);
9427                 val &= ~PCH_LP_PARTITION_LEVEL_DISABLE;
9428                 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
9429         }
9430
9431         lpt_disable_clkout_dp(dev);
9432         hsw_disable_lcpll(dev_priv, true, true);
9433 }
9434
9435 void hsw_disable_pc8(struct drm_i915_private *dev_priv)
9436 {
9437         struct drm_device *dev = dev_priv->dev;
9438         uint32_t val;
9439
9440         DRM_DEBUG_KMS("Disabling package C8+\n");
9441
9442         hsw_restore_lcpll(dev_priv);
9443         lpt_init_pch_refclk(dev);
9444
9445         if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
9446                 val = I915_READ(SOUTH_DSPCLK_GATE_D);
9447                 val |= PCH_LP_PARTITION_LEVEL_DISABLE;
9448                 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
9449         }
9450
9451         intel_prepare_ddi(dev);
9452 }
9453
9454 static void broxton_modeset_commit_cdclk(struct drm_atomic_state *old_state)
9455 {
9456         struct drm_device *dev = old_state->dev;
9457         unsigned int req_cdclk = to_intel_atomic_state(old_state)->cdclk;
9458
9459         broxton_set_cdclk(dev, req_cdclk);
9460 }
9461
9462 /* compute the max rate for new configuration */
9463 static int ilk_max_pixel_rate(struct drm_atomic_state *state)
9464 {
9465         struct intel_crtc *intel_crtc;
9466         struct intel_crtc_state *crtc_state;
9467         int max_pixel_rate = 0;
9468
9469         for_each_intel_crtc(state->dev, intel_crtc) {
9470                 int pixel_rate;
9471
9472                 crtc_state = intel_atomic_get_crtc_state(state, intel_crtc);
9473                 if (IS_ERR(crtc_state))
9474                         return PTR_ERR(crtc_state);
9475
9476                 if (!crtc_state->base.enable)
9477                         continue;
9478
9479                 pixel_rate = ilk_pipe_pixel_rate(crtc_state);
9480
9481                 /* pixel rate mustn't exceed 95% of cdclk with IPS on BDW */
9482                 if (IS_BROADWELL(state->dev) && crtc_state->ips_enabled)
9483                         pixel_rate = DIV_ROUND_UP(pixel_rate * 100, 95);
9484
9485                 max_pixel_rate = max(max_pixel_rate, pixel_rate);
9486         }
9487
9488         return max_pixel_rate;
9489 }
9490
9491 static void broadwell_set_cdclk(struct drm_device *dev, int cdclk)
9492 {
9493         struct drm_i915_private *dev_priv = dev->dev_private;
9494         uint32_t val, data;
9495         int ret;
9496
9497         if (WARN((I915_READ(LCPLL_CTL) &
9498                   (LCPLL_PLL_DISABLE | LCPLL_PLL_LOCK |
9499                    LCPLL_CD_CLOCK_DISABLE | LCPLL_ROOT_CD_CLOCK_DISABLE |
9500                    LCPLL_CD2X_CLOCK_DISABLE | LCPLL_POWER_DOWN_ALLOW |
9501                    LCPLL_CD_SOURCE_FCLK)) != LCPLL_PLL_LOCK,
9502                  "trying to change cdclk frequency with cdclk not enabled\n"))
9503                 return;
9504
9505         mutex_lock(&dev_priv->rps.hw_lock);
9506         ret = sandybridge_pcode_write(dev_priv,
9507                                       BDW_PCODE_DISPLAY_FREQ_CHANGE_REQ, 0x0);
9508         mutex_unlock(&dev_priv->rps.hw_lock);
9509         if (ret) {
9510                 DRM_ERROR("failed to inform pcode about cdclk change\n");
9511                 return;
9512         }
9513
9514         val = I915_READ(LCPLL_CTL);
9515         val |= LCPLL_CD_SOURCE_FCLK;
9516         I915_WRITE(LCPLL_CTL, val);
9517
9518         if (wait_for_atomic_us(I915_READ(LCPLL_CTL) &
9519                                LCPLL_CD_SOURCE_FCLK_DONE, 1))
9520                 DRM_ERROR("Switching to FCLK failed\n");
9521
9522         val = I915_READ(LCPLL_CTL);
9523         val &= ~LCPLL_CLK_FREQ_MASK;
9524
9525         switch (cdclk) {
9526         case 450000:
9527                 val |= LCPLL_CLK_FREQ_450;
9528                 data = 0;
9529                 break;
9530         case 540000:
9531                 val |= LCPLL_CLK_FREQ_54O_BDW;
9532                 data = 1;
9533                 break;
9534         case 337500:
9535                 val |= LCPLL_CLK_FREQ_337_5_BDW;
9536                 data = 2;
9537                 break;
9538         case 675000:
9539                 val |= LCPLL_CLK_FREQ_675_BDW;
9540                 data = 3;
9541                 break;
9542         default:
9543                 WARN(1, "invalid cdclk frequency\n");
9544                 return;
9545         }
9546
9547         I915_WRITE(LCPLL_CTL, val);
9548
9549         val = I915_READ(LCPLL_CTL);
9550         val &= ~LCPLL_CD_SOURCE_FCLK;
9551         I915_WRITE(LCPLL_CTL, val);
9552
9553         if (wait_for_atomic_us((I915_READ(LCPLL_CTL) &
9554                                 LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1))
9555                 DRM_ERROR("Switching back to LCPLL failed\n");
9556
9557         mutex_lock(&dev_priv->rps.hw_lock);
9558         sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ, data);
9559         mutex_unlock(&dev_priv->rps.hw_lock);
9560
9561         intel_update_cdclk(dev);
9562
9563         WARN(cdclk != dev_priv->cdclk_freq,
9564              "cdclk requested %d kHz but got %d kHz\n",
9565              cdclk, dev_priv->cdclk_freq);
9566 }
9567
9568 static int broadwell_modeset_calc_cdclk(struct drm_atomic_state *state)
9569 {
9570         struct drm_i915_private *dev_priv = to_i915(state->dev);
9571         int max_pixclk = ilk_max_pixel_rate(state);
9572         int cdclk;
9573
9574         /*
9575          * FIXME should also account for plane ratio
9576          * once 64bpp pixel formats are supported.
9577          */
9578         if (max_pixclk > 540000)
9579                 cdclk = 675000;
9580         else if (max_pixclk > 450000)
9581                 cdclk = 540000;
9582         else if (max_pixclk > 337500)
9583                 cdclk = 450000;
9584         else
9585                 cdclk = 337500;
9586
9587         /*
9588          * FIXME move the cdclk caclulation to
9589          * compute_config() so we can fail gracegully.
9590          */
9591         if (cdclk > dev_priv->max_cdclk_freq) {
9592                 DRM_ERROR("requested cdclk (%d kHz) exceeds max (%d kHz)\n",
9593                           cdclk, dev_priv->max_cdclk_freq);
9594                 cdclk = dev_priv->max_cdclk_freq;
9595         }
9596
9597         to_intel_atomic_state(state)->cdclk = cdclk;
9598
9599         return 0;
9600 }
9601
9602 static void broadwell_modeset_commit_cdclk(struct drm_atomic_state *old_state)
9603 {
9604         struct drm_device *dev = old_state->dev;
9605         unsigned int req_cdclk = to_intel_atomic_state(old_state)->cdclk;
9606
9607         broadwell_set_cdclk(dev, req_cdclk);
9608 }
9609
9610 static int haswell_crtc_compute_clock(struct intel_crtc *crtc,
9611                                       struct intel_crtc_state *crtc_state)
9612 {
9613         if (!intel_ddi_pll_select(crtc, crtc_state))
9614                 return -EINVAL;
9615
9616         crtc->lowfreq_avail = false;
9617
9618         return 0;
9619 }
9620
9621 static void bxt_get_ddi_pll(struct drm_i915_private *dev_priv,
9622                                 enum port port,
9623                                 struct intel_crtc_state *pipe_config)
9624 {
9625         switch (port) {
9626         case PORT_A:
9627                 pipe_config->ddi_pll_sel = SKL_DPLL0;
9628                 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL1;
9629                 break;
9630         case PORT_B:
9631                 pipe_config->ddi_pll_sel = SKL_DPLL1;
9632                 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL2;
9633                 break;
9634         case PORT_C:
9635                 pipe_config->ddi_pll_sel = SKL_DPLL2;
9636                 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL3;
9637                 break;
9638         default:
9639                 DRM_ERROR("Incorrect port type\n");
9640         }
9641 }
9642
9643 static void skylake_get_ddi_pll(struct drm_i915_private *dev_priv,
9644                                 enum port port,
9645                                 struct intel_crtc_state *pipe_config)
9646 {
9647         u32 temp, dpll_ctl1;
9648
9649         temp = I915_READ(DPLL_CTRL2) & DPLL_CTRL2_DDI_CLK_SEL_MASK(port);
9650         pipe_config->ddi_pll_sel = temp >> (port * 3 + 1);
9651
9652         switch (pipe_config->ddi_pll_sel) {
9653         case SKL_DPLL0:
9654                 /*
9655                  * On SKL the eDP DPLL (DPLL0 as we don't use SSC) is not part
9656                  * of the shared DPLL framework and thus needs to be read out
9657                  * separately
9658                  */
9659                 dpll_ctl1 = I915_READ(DPLL_CTRL1);
9660                 pipe_config->dpll_hw_state.ctrl1 = dpll_ctl1 & 0x3f;
9661                 break;
9662         case SKL_DPLL1:
9663                 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL1;
9664                 break;
9665         case SKL_DPLL2:
9666                 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL2;
9667                 break;
9668         case SKL_DPLL3:
9669                 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL3;
9670                 break;
9671         }
9672 }
9673
9674 static void haswell_get_ddi_pll(struct drm_i915_private *dev_priv,
9675                                 enum port port,
9676                                 struct intel_crtc_state *pipe_config)
9677 {
9678         pipe_config->ddi_pll_sel = I915_READ(PORT_CLK_SEL(port));
9679
9680         switch (pipe_config->ddi_pll_sel) {
9681         case PORT_CLK_SEL_WRPLL1:
9682                 pipe_config->shared_dpll = DPLL_ID_WRPLL1;
9683                 break;
9684         case PORT_CLK_SEL_WRPLL2:
9685                 pipe_config->shared_dpll = DPLL_ID_WRPLL2;
9686                 break;
9687         }
9688 }
9689
9690 static void haswell_get_ddi_port_state(struct intel_crtc *crtc,
9691                                        struct intel_crtc_state *pipe_config)
9692 {
9693         struct drm_device *dev = crtc->base.dev;
9694         struct drm_i915_private *dev_priv = dev->dev_private;
9695         struct intel_shared_dpll *pll;
9696         enum port port;
9697         uint32_t tmp;
9698
9699         tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe_config->cpu_transcoder));
9700
9701         port = (tmp & TRANS_DDI_PORT_MASK) >> TRANS_DDI_PORT_SHIFT;
9702
9703         if (IS_SKYLAKE(dev))
9704                 skylake_get_ddi_pll(dev_priv, port, pipe_config);
9705         else if (IS_BROXTON(dev))
9706                 bxt_get_ddi_pll(dev_priv, port, pipe_config);
9707         else
9708                 haswell_get_ddi_pll(dev_priv, port, pipe_config);
9709
9710         if (pipe_config->shared_dpll >= 0) {
9711                 pll = &dev_priv->shared_dplls[pipe_config->shared_dpll];
9712
9713                 WARN_ON(!pll->get_hw_state(dev_priv, pll,
9714                                            &pipe_config->dpll_hw_state));
9715         }
9716
9717         /*
9718          * Haswell has only FDI/PCH transcoder A. It is which is connected to
9719          * DDI E. So just check whether this pipe is wired to DDI E and whether
9720          * the PCH transcoder is on.
9721          */
9722         if (INTEL_INFO(dev)->gen < 9 &&
9723             (port == PORT_E) && I915_READ(LPT_TRANSCONF) & TRANS_ENABLE) {
9724                 pipe_config->has_pch_encoder = true;
9725
9726                 tmp = I915_READ(FDI_RX_CTL(PIPE_A));
9727                 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
9728                                           FDI_DP_PORT_WIDTH_SHIFT) + 1;
9729
9730                 ironlake_get_fdi_m_n_config(crtc, pipe_config);
9731         }
9732 }
9733
9734 static bool haswell_get_pipe_config(struct intel_crtc *crtc,
9735                                     struct intel_crtc_state *pipe_config)
9736 {
9737         struct drm_device *dev = crtc->base.dev;
9738         struct drm_i915_private *dev_priv = dev->dev_private;
9739         enum intel_display_power_domain pfit_domain;
9740         uint32_t tmp;
9741
9742         if (!intel_display_power_is_enabled(dev_priv,
9743                                          POWER_DOMAIN_PIPE(crtc->pipe)))
9744                 return false;
9745
9746         pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
9747         pipe_config->shared_dpll = DPLL_ID_PRIVATE;
9748
9749         tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
9750         if (tmp & TRANS_DDI_FUNC_ENABLE) {
9751                 enum pipe trans_edp_pipe;
9752                 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
9753                 default:
9754                         WARN(1, "unknown pipe linked to edp transcoder\n");
9755                 case TRANS_DDI_EDP_INPUT_A_ONOFF:
9756                 case TRANS_DDI_EDP_INPUT_A_ON:
9757                         trans_edp_pipe = PIPE_A;
9758                         break;
9759                 case TRANS_DDI_EDP_INPUT_B_ONOFF:
9760                         trans_edp_pipe = PIPE_B;
9761                         break;
9762                 case TRANS_DDI_EDP_INPUT_C_ONOFF:
9763                         trans_edp_pipe = PIPE_C;
9764                         break;
9765                 }
9766
9767                 if (trans_edp_pipe == crtc->pipe)
9768                         pipe_config->cpu_transcoder = TRANSCODER_EDP;
9769         }
9770
9771         if (!intel_display_power_is_enabled(dev_priv,
9772                         POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder)))
9773                 return false;
9774
9775         tmp = I915_READ(PIPECONF(pipe_config->cpu_transcoder));
9776         if (!(tmp & PIPECONF_ENABLE))
9777                 return false;
9778
9779         haswell_get_ddi_port_state(crtc, pipe_config);
9780
9781         intel_get_pipe_timings(crtc, pipe_config);
9782
9783         if (INTEL_INFO(dev)->gen >= 9) {
9784                 skl_init_scalers(dev, crtc, pipe_config);
9785         }
9786
9787         pfit_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe);
9788
9789         if (INTEL_INFO(dev)->gen >= 9) {
9790                 pipe_config->scaler_state.scaler_id = -1;
9791                 pipe_config->scaler_state.scaler_users &= ~(1 << SKL_CRTC_INDEX);
9792         }
9793
9794         if (intel_display_power_is_enabled(dev_priv, pfit_domain)) {
9795                 if (INTEL_INFO(dev)->gen == 9)
9796                         skylake_get_pfit_config(crtc, pipe_config);
9797                 else if (INTEL_INFO(dev)->gen < 9)
9798                         ironlake_get_pfit_config(crtc, pipe_config);
9799                 else
9800                         MISSING_CASE(INTEL_INFO(dev)->gen);
9801         }
9802
9803         if (IS_HASWELL(dev))
9804                 pipe_config->ips_enabled = hsw_crtc_supports_ips(crtc) &&
9805                         (I915_READ(IPS_CTL) & IPS_ENABLE);
9806
9807         if (pipe_config->cpu_transcoder != TRANSCODER_EDP) {
9808                 pipe_config->pixel_multiplier =
9809                         I915_READ(PIPE_MULT(pipe_config->cpu_transcoder)) + 1;
9810         } else {
9811                 pipe_config->pixel_multiplier = 1;
9812         }
9813
9814         return true;
9815 }
9816
9817 static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
9818 {
9819         struct drm_device *dev = crtc->dev;
9820         struct drm_i915_private *dev_priv = dev->dev_private;
9821         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9822         uint32_t cntl = 0, size = 0;
9823
9824         if (base) {
9825                 unsigned int width = intel_crtc->base.cursor->state->crtc_w;
9826                 unsigned int height = intel_crtc->base.cursor->state->crtc_h;
9827                 unsigned int stride = roundup_pow_of_two(width) * 4;
9828
9829                 switch (stride) {
9830                 default:
9831                         WARN_ONCE(1, "Invalid cursor width/stride, width=%u, stride=%u\n",
9832                                   width, stride);
9833                         stride = 256;
9834                         /* fallthrough */
9835                 case 256:
9836                 case 512:
9837                 case 1024:
9838                 case 2048:
9839                         break;
9840                 }
9841
9842                 cntl |= CURSOR_ENABLE |
9843                         CURSOR_GAMMA_ENABLE |
9844                         CURSOR_FORMAT_ARGB |
9845                         CURSOR_STRIDE(stride);
9846
9847                 size = (height << 12) | width;
9848         }
9849
9850         if (intel_crtc->cursor_cntl != 0 &&
9851             (intel_crtc->cursor_base != base ||
9852              intel_crtc->cursor_size != size ||
9853              intel_crtc->cursor_cntl != cntl)) {
9854                 /* On these chipsets we can only modify the base/size/stride
9855                  * whilst the cursor is disabled.
9856                  */
9857                 I915_WRITE(_CURACNTR, 0);
9858                 POSTING_READ(_CURACNTR);
9859                 intel_crtc->cursor_cntl = 0;
9860         }
9861
9862         if (intel_crtc->cursor_base != base) {
9863                 I915_WRITE(_CURABASE, base);
9864                 intel_crtc->cursor_base = base;
9865         }
9866
9867         if (intel_crtc->cursor_size != size) {
9868                 I915_WRITE(CURSIZE, size);
9869                 intel_crtc->cursor_size = size;
9870         }
9871
9872         if (intel_crtc->cursor_cntl != cntl) {
9873                 I915_WRITE(_CURACNTR, cntl);
9874                 POSTING_READ(_CURACNTR);
9875                 intel_crtc->cursor_cntl = cntl;
9876         }
9877 }
9878
9879 static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
9880 {
9881         struct drm_device *dev = crtc->dev;
9882         struct drm_i915_private *dev_priv = dev->dev_private;
9883         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9884         int pipe = intel_crtc->pipe;
9885         uint32_t cntl;
9886
9887         cntl = 0;
9888         if (base) {
9889                 cntl = MCURSOR_GAMMA_ENABLE;
9890                 switch (intel_crtc->base.cursor->state->crtc_w) {
9891                         case 64:
9892                                 cntl |= CURSOR_MODE_64_ARGB_AX;
9893                                 break;
9894                         case 128:
9895                                 cntl |= CURSOR_MODE_128_ARGB_AX;
9896                                 break;
9897                         case 256:
9898                                 cntl |= CURSOR_MODE_256_ARGB_AX;
9899                                 break;
9900                         default:
9901                                 MISSING_CASE(intel_crtc->base.cursor->state->crtc_w);
9902                                 return;
9903                 }
9904                 cntl |= pipe << 28; /* Connect to correct pipe */
9905
9906                 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
9907                         cntl |= CURSOR_PIPE_CSC_ENABLE;
9908         }
9909
9910         if (crtc->cursor->state->rotation == BIT(DRM_ROTATE_180))
9911                 cntl |= CURSOR_ROTATE_180;
9912
9913         if (intel_crtc->cursor_cntl != cntl) {
9914                 I915_WRITE(CURCNTR(pipe), cntl);
9915                 POSTING_READ(CURCNTR(pipe));
9916                 intel_crtc->cursor_cntl = cntl;
9917         }
9918
9919         /* and commit changes on next vblank */
9920         I915_WRITE(CURBASE(pipe), base);
9921         POSTING_READ(CURBASE(pipe));
9922
9923         intel_crtc->cursor_base = base;
9924 }
9925
9926 /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
9927 static void intel_crtc_update_cursor(struct drm_crtc *crtc,
9928                                      bool on)
9929 {
9930         struct drm_device *dev = crtc->dev;
9931         struct drm_i915_private *dev_priv = dev->dev_private;
9932         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9933         int pipe = intel_crtc->pipe;
9934         int x = crtc->cursor_x;
9935         int y = crtc->cursor_y;
9936         u32 base = 0, pos = 0;
9937
9938         if (on)
9939                 base = intel_crtc->cursor_addr;
9940
9941         if (x >= intel_crtc->config->pipe_src_w)
9942                 base = 0;
9943
9944         if (y >= intel_crtc->config->pipe_src_h)
9945                 base = 0;
9946
9947         if (x < 0) {
9948                 if (x + intel_crtc->base.cursor->state->crtc_w <= 0)
9949                         base = 0;
9950
9951                 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
9952                 x = -x;
9953         }
9954         pos |= x << CURSOR_X_SHIFT;
9955
9956         if (y < 0) {
9957                 if (y + intel_crtc->base.cursor->state->crtc_h <= 0)
9958                         base = 0;
9959
9960                 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
9961                 y = -y;
9962         }
9963         pos |= y << CURSOR_Y_SHIFT;
9964
9965         if (base == 0 && intel_crtc->cursor_base == 0)
9966                 return;
9967
9968         I915_WRITE(CURPOS(pipe), pos);
9969
9970         /* ILK+ do this automagically */
9971         if (HAS_GMCH_DISPLAY(dev) &&
9972             crtc->cursor->state->rotation == BIT(DRM_ROTATE_180)) {
9973                 base += (intel_crtc->base.cursor->state->crtc_h *
9974                         intel_crtc->base.cursor->state->crtc_w - 1) * 4;
9975         }
9976
9977         if (IS_845G(dev) || IS_I865G(dev))
9978                 i845_update_cursor(crtc, base);
9979         else
9980                 i9xx_update_cursor(crtc, base);
9981 }
9982
9983 static bool cursor_size_ok(struct drm_device *dev,
9984                            uint32_t width, uint32_t height)
9985 {
9986         if (width == 0 || height == 0)
9987                 return false;
9988
9989         /*
9990          * 845g/865g are special in that they are only limited by
9991          * the width of their cursors, the height is arbitrary up to
9992          * the precision of the register. Everything else requires
9993          * square cursors, limited to a few power-of-two sizes.
9994          */
9995         if (IS_845G(dev) || IS_I865G(dev)) {
9996                 if ((width & 63) != 0)
9997                         return false;
9998
9999                 if (width > (IS_845G(dev) ? 64 : 512))
10000                         return false;
10001
10002                 if (height > 1023)
10003                         return false;
10004         } else {
10005                 switch (width | height) {
10006                 case 256:
10007                 case 128:
10008                         if (IS_GEN2(dev))
10009                                 return false;
10010                 case 64:
10011                         break;
10012                 default:
10013                         return false;
10014                 }
10015         }
10016
10017         return true;
10018 }
10019
10020 static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
10021                                  u16 *blue, uint32_t start, uint32_t size)
10022 {
10023         int end = (start + size > 256) ? 256 : start + size, i;
10024         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10025
10026         for (i = start; i < end; i++) {
10027                 intel_crtc->lut_r[i] = red[i] >> 8;
10028                 intel_crtc->lut_g[i] = green[i] >> 8;
10029                 intel_crtc->lut_b[i] = blue[i] >> 8;
10030         }
10031
10032         intel_crtc_load_lut(crtc);
10033 }
10034
10035 /* VESA 640x480x72Hz mode to set on the pipe */
10036 static struct drm_display_mode load_detect_mode = {
10037         DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
10038                  704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
10039 };
10040
10041 struct drm_framebuffer *
10042 __intel_framebuffer_create(struct drm_device *dev,
10043                            struct drm_mode_fb_cmd2 *mode_cmd,
10044                            struct drm_i915_gem_object *obj)
10045 {
10046         struct intel_framebuffer *intel_fb;
10047         int ret;
10048
10049         intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
10050         if (!intel_fb) {
10051                 drm_gem_object_unreference(&obj->base);
10052                 return ERR_PTR(-ENOMEM);
10053         }
10054
10055         ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
10056         if (ret)
10057                 goto err;
10058
10059         return &intel_fb->base;
10060 err:
10061         drm_gem_object_unreference(&obj->base);
10062         kfree(intel_fb);
10063
10064         return ERR_PTR(ret);
10065 }
10066
10067 static struct drm_framebuffer *
10068 intel_framebuffer_create(struct drm_device *dev,
10069                          struct drm_mode_fb_cmd2 *mode_cmd,
10070                          struct drm_i915_gem_object *obj)
10071 {
10072         struct drm_framebuffer *fb;
10073         int ret;
10074
10075         ret = i915_mutex_lock_interruptible(dev);
10076         if (ret)
10077                 return ERR_PTR(ret);
10078         fb = __intel_framebuffer_create(dev, mode_cmd, obj);
10079         mutex_unlock(&dev->struct_mutex);
10080
10081         return fb;
10082 }
10083
10084 static u32
10085 intel_framebuffer_pitch_for_width(int width, int bpp)
10086 {
10087         u32 pitch = DIV_ROUND_UP(width * bpp, 8);
10088         return ALIGN(pitch, 64);
10089 }
10090
10091 static u32
10092 intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
10093 {
10094         u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
10095         return PAGE_ALIGN(pitch * mode->vdisplay);
10096 }
10097
10098 static struct drm_framebuffer *
10099 intel_framebuffer_create_for_mode(struct drm_device *dev,
10100                                   struct drm_display_mode *mode,
10101                                   int depth, int bpp)
10102 {
10103         struct drm_i915_gem_object *obj;
10104         struct drm_mode_fb_cmd2 mode_cmd = { 0 };
10105
10106         obj = i915_gem_alloc_object(dev,
10107                                     intel_framebuffer_size_for_mode(mode, bpp));
10108         if (obj == NULL)
10109                 return ERR_PTR(-ENOMEM);
10110
10111         mode_cmd.width = mode->hdisplay;
10112         mode_cmd.height = mode->vdisplay;
10113         mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
10114                                                                 bpp);
10115         mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth);
10116
10117         return intel_framebuffer_create(dev, &mode_cmd, obj);
10118 }
10119
10120 static struct drm_framebuffer *
10121 mode_fits_in_fbdev(struct drm_device *dev,
10122                    struct drm_display_mode *mode)
10123 {
10124 #ifdef CONFIG_DRM_I915_FBDEV
10125         struct drm_i915_private *dev_priv = dev->dev_private;
10126         struct drm_i915_gem_object *obj;
10127         struct drm_framebuffer *fb;
10128
10129         if (!dev_priv->fbdev)
10130                 return NULL;
10131
10132         if (!dev_priv->fbdev->fb)
10133                 return NULL;
10134
10135         obj = dev_priv->fbdev->fb->obj;
10136         BUG_ON(!obj);
10137
10138         fb = &dev_priv->fbdev->fb->base;
10139         if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
10140                                                                fb->bits_per_pixel))
10141                 return NULL;
10142
10143         if (obj->base.size < mode->vdisplay * fb->pitches[0])
10144                 return NULL;
10145
10146         return fb;
10147 #else
10148         return NULL;
10149 #endif
10150 }
10151
10152 static int intel_modeset_setup_plane_state(struct drm_atomic_state *state,
10153                                            struct drm_crtc *crtc,
10154                                            struct drm_display_mode *mode,
10155                                            struct drm_framebuffer *fb,
10156                                            int x, int y)
10157 {
10158         struct drm_plane_state *plane_state;
10159         int hdisplay, vdisplay;
10160         int ret;
10161
10162         plane_state = drm_atomic_get_plane_state(state, crtc->primary);
10163         if (IS_ERR(plane_state))
10164                 return PTR_ERR(plane_state);
10165
10166         if (mode)
10167                 drm_crtc_get_hv_timing(mode, &hdisplay, &vdisplay);
10168         else
10169                 hdisplay = vdisplay = 0;
10170
10171         ret = drm_atomic_set_crtc_for_plane(plane_state, fb ? crtc : NULL);
10172         if (ret)
10173                 return ret;
10174         drm_atomic_set_fb_for_plane(plane_state, fb);
10175         plane_state->crtc_x = 0;
10176         plane_state->crtc_y = 0;
10177         plane_state->crtc_w = hdisplay;
10178         plane_state->crtc_h = vdisplay;
10179         plane_state->src_x = x << 16;
10180         plane_state->src_y = y << 16;
10181         plane_state->src_w = hdisplay << 16;
10182         plane_state->src_h = vdisplay << 16;
10183
10184         return 0;
10185 }
10186
10187 bool intel_get_load_detect_pipe(struct drm_connector *connector,
10188                                 struct drm_display_mode *mode,
10189                                 struct intel_load_detect_pipe *old,
10190                                 struct drm_modeset_acquire_ctx *ctx)
10191 {
10192         struct intel_crtc *intel_crtc;
10193         struct intel_encoder *intel_encoder =
10194                 intel_attached_encoder(connector);
10195         struct drm_crtc *possible_crtc;
10196         struct drm_encoder *encoder = &intel_encoder->base;
10197         struct drm_crtc *crtc = NULL;
10198         struct drm_device *dev = encoder->dev;
10199         struct drm_framebuffer *fb;
10200         struct drm_mode_config *config = &dev->mode_config;
10201         struct drm_atomic_state *state = NULL;
10202         struct drm_connector_state *connector_state;
10203         struct intel_crtc_state *crtc_state;
10204         int ret, i = -1;
10205
10206         DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
10207                       connector->base.id, connector->name,
10208                       encoder->base.id, encoder->name);
10209
10210 retry:
10211         ret = drm_modeset_lock(&config->connection_mutex, ctx);
10212         if (ret)
10213                 goto fail_unlock;
10214
10215         /*
10216          * Algorithm gets a little messy:
10217          *
10218          *   - if the connector already has an assigned crtc, use it (but make
10219          *     sure it's on first)
10220          *
10221          *   - try to find the first unused crtc that can drive this connector,
10222          *     and use that if we find one
10223          */
10224
10225         /* See if we already have a CRTC for this connector */
10226         if (encoder->crtc) {
10227                 crtc = encoder->crtc;
10228
10229                 ret = drm_modeset_lock(&crtc->mutex, ctx);
10230                 if (ret)
10231                         goto fail_unlock;
10232                 ret = drm_modeset_lock(&crtc->primary->mutex, ctx);
10233                 if (ret)
10234                         goto fail_unlock;
10235
10236                 old->dpms_mode = connector->dpms;
10237                 old->load_detect_temp = false;
10238
10239                 /* Make sure the crtc and connector are running */
10240                 if (connector->dpms != DRM_MODE_DPMS_ON)
10241                         connector->funcs->dpms(connector, DRM_MODE_DPMS_ON);
10242
10243                 return true;
10244         }
10245
10246         /* Find an unused one (if possible) */
10247         for_each_crtc(dev, possible_crtc) {
10248                 i++;
10249                 if (!(encoder->possible_crtcs & (1 << i)))
10250                         continue;
10251                 if (possible_crtc->state->enable)
10252                         continue;
10253                 /* This can occur when applying the pipe A quirk on resume. */
10254                 if (to_intel_crtc(possible_crtc)->new_enabled)
10255                         continue;
10256
10257                 crtc = possible_crtc;
10258                 break;
10259         }
10260
10261         /*
10262          * If we didn't find an unused CRTC, don't use any.
10263          */
10264         if (!crtc) {
10265                 DRM_DEBUG_KMS("no pipe available for load-detect\n");
10266                 goto fail_unlock;
10267         }
10268
10269         ret = drm_modeset_lock(&crtc->mutex, ctx);
10270         if (ret)
10271                 goto fail_unlock;
10272         ret = drm_modeset_lock(&crtc->primary->mutex, ctx);
10273         if (ret)
10274                 goto fail_unlock;
10275         intel_encoder->new_crtc = to_intel_crtc(crtc);
10276         to_intel_connector(connector)->new_encoder = intel_encoder;
10277
10278         intel_crtc = to_intel_crtc(crtc);
10279         intel_crtc->new_enabled = true;
10280         old->dpms_mode = connector->dpms;
10281         old->load_detect_temp = true;
10282         old->release_fb = NULL;
10283
10284         state = drm_atomic_state_alloc(dev);
10285         if (!state)
10286                 return false;
10287
10288         state->acquire_ctx = ctx;
10289
10290         connector_state = drm_atomic_get_connector_state(state, connector);
10291         if (IS_ERR(connector_state)) {
10292                 ret = PTR_ERR(connector_state);
10293                 goto fail;
10294         }
10295
10296         connector_state->crtc = crtc;
10297         connector_state->best_encoder = &intel_encoder->base;
10298
10299         crtc_state = intel_atomic_get_crtc_state(state, intel_crtc);
10300         if (IS_ERR(crtc_state)) {
10301                 ret = PTR_ERR(crtc_state);
10302                 goto fail;
10303         }
10304
10305         crtc_state->base.active = crtc_state->base.enable = true;
10306
10307         if (!mode)
10308                 mode = &load_detect_mode;
10309
10310         /* We need a framebuffer large enough to accommodate all accesses
10311          * that the plane may generate whilst we perform load detection.
10312          * We can not rely on the fbcon either being present (we get called
10313          * during its initialisation to detect all boot displays, or it may
10314          * not even exist) or that it is large enough to satisfy the
10315          * requested mode.
10316          */
10317         fb = mode_fits_in_fbdev(dev, mode);
10318         if (fb == NULL) {
10319                 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
10320                 fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
10321                 old->release_fb = fb;
10322         } else
10323                 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
10324         if (IS_ERR(fb)) {
10325                 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
10326                 goto fail;
10327         }
10328
10329         ret = intel_modeset_setup_plane_state(state, crtc, mode, fb, 0, 0);
10330         if (ret)
10331                 goto fail;
10332
10333         drm_mode_copy(&crtc_state->base.mode, mode);
10334
10335         if (intel_set_mode(state)) {
10336                 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
10337                 if (old->release_fb)
10338                         old->release_fb->funcs->destroy(old->release_fb);
10339                 goto fail;
10340         }
10341         crtc->primary->crtc = crtc;
10342
10343         /* let the connector get through one full cycle before testing */
10344         intel_wait_for_vblank(dev, intel_crtc->pipe);
10345         return true;
10346
10347  fail:
10348         intel_crtc->new_enabled = crtc->state->enable;
10349 fail_unlock:
10350         drm_atomic_state_free(state);
10351         state = NULL;
10352
10353         if (ret == -EDEADLK) {
10354                 drm_modeset_backoff(ctx);
10355                 goto retry;
10356         }
10357
10358         return false;
10359 }
10360
10361 void intel_release_load_detect_pipe(struct drm_connector *connector,
10362                                     struct intel_load_detect_pipe *old,
10363                                     struct drm_modeset_acquire_ctx *ctx)
10364 {
10365         struct drm_device *dev = connector->dev;
10366         struct intel_encoder *intel_encoder =
10367                 intel_attached_encoder(connector);
10368         struct drm_encoder *encoder = &intel_encoder->base;
10369         struct drm_crtc *crtc = encoder->crtc;
10370         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10371         struct drm_atomic_state *state;
10372         struct drm_connector_state *connector_state;
10373         struct intel_crtc_state *crtc_state;
10374         int ret;
10375
10376         DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
10377                       connector->base.id, connector->name,
10378                       encoder->base.id, encoder->name);
10379
10380         if (old->load_detect_temp) {
10381                 state = drm_atomic_state_alloc(dev);
10382                 if (!state)
10383                         goto fail;
10384
10385                 state->acquire_ctx = ctx;
10386
10387                 connector_state = drm_atomic_get_connector_state(state, connector);
10388                 if (IS_ERR(connector_state))
10389                         goto fail;
10390
10391                 crtc_state = intel_atomic_get_crtc_state(state, intel_crtc);
10392                 if (IS_ERR(crtc_state))
10393                         goto fail;
10394
10395                 to_intel_connector(connector)->new_encoder = NULL;
10396                 intel_encoder->new_crtc = NULL;
10397                 intel_crtc->new_enabled = false;
10398
10399                 connector_state->best_encoder = NULL;
10400                 connector_state->crtc = NULL;
10401
10402                 crtc_state->base.enable = crtc_state->base.active = false;
10403
10404                 ret = intel_modeset_setup_plane_state(state, crtc, NULL, NULL,
10405                                                       0, 0);
10406                 if (ret)
10407                         goto fail;
10408
10409                 ret = intel_set_mode(state);
10410                 if (ret)
10411                         goto fail;
10412
10413                 if (old->release_fb) {
10414                         drm_framebuffer_unregister_private(old->release_fb);
10415                         drm_framebuffer_unreference(old->release_fb);
10416                 }
10417
10418                 return;
10419         }
10420
10421         /* Switch crtc and encoder back off if necessary */
10422         if (old->dpms_mode != DRM_MODE_DPMS_ON)
10423                 connector->funcs->dpms(connector, old->dpms_mode);
10424
10425         return;
10426 fail:
10427         DRM_DEBUG_KMS("Couldn't release load detect pipe.\n");
10428         drm_atomic_state_free(state);
10429 }
10430
10431 static int i9xx_pll_refclk(struct drm_device *dev,
10432                            const struct intel_crtc_state *pipe_config)
10433 {
10434         struct drm_i915_private *dev_priv = dev->dev_private;
10435         u32 dpll = pipe_config->dpll_hw_state.dpll;
10436
10437         if ((dpll & PLL_REF_INPUT_MASK) == PLLB_REF_INPUT_SPREADSPECTRUMIN)
10438                 return dev_priv->vbt.lvds_ssc_freq;
10439         else if (HAS_PCH_SPLIT(dev))
10440                 return 120000;
10441         else if (!IS_GEN2(dev))
10442                 return 96000;
10443         else
10444                 return 48000;
10445 }
10446
10447 /* Returns the clock of the currently programmed mode of the given pipe. */
10448 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
10449                                 struct intel_crtc_state *pipe_config)
10450 {
10451         struct drm_device *dev = crtc->base.dev;
10452         struct drm_i915_private *dev_priv = dev->dev_private;
10453         int pipe = pipe_config->cpu_transcoder;
10454         u32 dpll = pipe_config->dpll_hw_state.dpll;
10455         u32 fp;
10456         intel_clock_t clock;
10457         int refclk = i9xx_pll_refclk(dev, pipe_config);
10458
10459         if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
10460                 fp = pipe_config->dpll_hw_state.fp0;
10461         else
10462                 fp = pipe_config->dpll_hw_state.fp1;
10463
10464         clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
10465         if (IS_PINEVIEW(dev)) {
10466                 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
10467                 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
10468         } else {
10469                 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
10470                 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
10471         }
10472
10473         if (!IS_GEN2(dev)) {
10474                 if (IS_PINEVIEW(dev))
10475                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
10476                                 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
10477                 else
10478                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
10479                                DPLL_FPA01_P1_POST_DIV_SHIFT);
10480
10481                 switch (dpll & DPLL_MODE_MASK) {
10482                 case DPLLB_MODE_DAC_SERIAL:
10483                         clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
10484                                 5 : 10;
10485                         break;
10486                 case DPLLB_MODE_LVDS:
10487                         clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
10488                                 7 : 14;
10489                         break;
10490                 default:
10491                         DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
10492                                   "mode\n", (int)(dpll & DPLL_MODE_MASK));
10493                         return;
10494                 }
10495
10496                 if (IS_PINEVIEW(dev))
10497                         pineview_clock(refclk, &clock);
10498                 else
10499                         i9xx_clock(refclk, &clock);
10500         } else {
10501                 u32 lvds = IS_I830(dev) ? 0 : I915_READ(LVDS);
10502                 bool is_lvds = (pipe == 1) && (lvds & LVDS_PORT_EN);
10503
10504                 if (is_lvds) {
10505                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
10506                                        DPLL_FPA01_P1_POST_DIV_SHIFT);
10507
10508                         if (lvds & LVDS_CLKB_POWER_UP)
10509                                 clock.p2 = 7;
10510                         else
10511                                 clock.p2 = 14;
10512                 } else {
10513                         if (dpll & PLL_P1_DIVIDE_BY_TWO)
10514                                 clock.p1 = 2;
10515                         else {
10516                                 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
10517                                             DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
10518                         }
10519                         if (dpll & PLL_P2_DIVIDE_BY_4)
10520                                 clock.p2 = 4;
10521                         else
10522                                 clock.p2 = 2;
10523                 }
10524
10525                 i9xx_clock(refclk, &clock);
10526         }
10527
10528         /*
10529          * This value includes pixel_multiplier. We will use
10530          * port_clock to compute adjusted_mode.crtc_clock in the
10531          * encoder's get_config() function.
10532          */
10533         pipe_config->port_clock = clock.dot;
10534 }
10535
10536 int intel_dotclock_calculate(int link_freq,
10537                              const struct intel_link_m_n *m_n)
10538 {
10539         /*
10540          * The calculation for the data clock is:
10541          * pixel_clock = ((m/n)*(link_clock * nr_lanes))/bpp
10542          * But we want to avoid losing precison if possible, so:
10543          * pixel_clock = ((m * link_clock * nr_lanes)/(n*bpp))
10544          *
10545          * and the link clock is simpler:
10546          * link_clock = (m * link_clock) / n
10547          */
10548
10549         if (!m_n->link_n)
10550                 return 0;
10551
10552         return div_u64((u64)m_n->link_m * link_freq, m_n->link_n);
10553 }
10554
10555 static void ironlake_pch_clock_get(struct intel_crtc *crtc,
10556                                    struct intel_crtc_state *pipe_config)
10557 {
10558         struct drm_device *dev = crtc->base.dev;
10559
10560         /* read out port_clock from the DPLL */
10561         i9xx_crtc_clock_get(crtc, pipe_config);
10562
10563         /*
10564          * This value does not include pixel_multiplier.
10565          * We will check that port_clock and adjusted_mode.crtc_clock
10566          * agree once we know their relationship in the encoder's
10567          * get_config() function.
10568          */
10569         pipe_config->base.adjusted_mode.crtc_clock =
10570                 intel_dotclock_calculate(intel_fdi_link_freq(dev) * 10000,
10571                                          &pipe_config->fdi_m_n);
10572 }
10573
10574 /** Returns the currently programmed mode of the given pipe. */
10575 struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
10576                                              struct drm_crtc *crtc)
10577 {
10578         struct drm_i915_private *dev_priv = dev->dev_private;
10579         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10580         enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
10581         struct drm_display_mode *mode;
10582         struct intel_crtc_state pipe_config;
10583         int htot = I915_READ(HTOTAL(cpu_transcoder));
10584         int hsync = I915_READ(HSYNC(cpu_transcoder));
10585         int vtot = I915_READ(VTOTAL(cpu_transcoder));
10586         int vsync = I915_READ(VSYNC(cpu_transcoder));
10587         enum pipe pipe = intel_crtc->pipe;
10588
10589         mode = kzalloc(sizeof(*mode), GFP_KERNEL);
10590         if (!mode)
10591                 return NULL;
10592
10593         /*
10594          * Construct a pipe_config sufficient for getting the clock info
10595          * back out of crtc_clock_get.
10596          *
10597          * Note, if LVDS ever uses a non-1 pixel multiplier, we'll need
10598          * to use a real value here instead.
10599          */
10600         pipe_config.cpu_transcoder = (enum transcoder) pipe;
10601         pipe_config.pixel_multiplier = 1;
10602         pipe_config.dpll_hw_state.dpll = I915_READ(DPLL(pipe));
10603         pipe_config.dpll_hw_state.fp0 = I915_READ(FP0(pipe));
10604         pipe_config.dpll_hw_state.fp1 = I915_READ(FP1(pipe));
10605         i9xx_crtc_clock_get(intel_crtc, &pipe_config);
10606
10607         mode->clock = pipe_config.port_clock / pipe_config.pixel_multiplier;
10608         mode->hdisplay = (htot & 0xffff) + 1;
10609         mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
10610         mode->hsync_start = (hsync & 0xffff) + 1;
10611         mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
10612         mode->vdisplay = (vtot & 0xffff) + 1;
10613         mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
10614         mode->vsync_start = (vsync & 0xffff) + 1;
10615         mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
10616
10617         drm_mode_set_name(mode);
10618
10619         return mode;
10620 }
10621
10622 static void intel_decrease_pllclock(struct drm_crtc *crtc)
10623 {
10624         struct drm_device *dev = crtc->dev;
10625         struct drm_i915_private *dev_priv = dev->dev_private;
10626         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10627
10628         if (!HAS_GMCH_DISPLAY(dev))
10629                 return;
10630
10631         if (!dev_priv->lvds_downclock_avail)
10632                 return;
10633
10634         /*
10635          * Since this is called by a timer, we should never get here in
10636          * the manual case.
10637          */
10638         if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
10639                 int pipe = intel_crtc->pipe;
10640                 int dpll_reg = DPLL(pipe);
10641                 int dpll;
10642
10643                 DRM_DEBUG_DRIVER("downclocking LVDS\n");
10644
10645                 assert_panel_unlocked(dev_priv, pipe);
10646
10647                 dpll = I915_READ(dpll_reg);
10648                 dpll |= DISPLAY_RATE_SELECT_FPA1;
10649                 I915_WRITE(dpll_reg, dpll);
10650                 intel_wait_for_vblank(dev, pipe);
10651                 dpll = I915_READ(dpll_reg);
10652                 if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
10653                         DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
10654         }
10655
10656 }
10657
10658 void intel_mark_busy(struct drm_device *dev)
10659 {
10660         struct drm_i915_private *dev_priv = dev->dev_private;
10661
10662         if (dev_priv->mm.busy)
10663                 return;
10664
10665         intel_runtime_pm_get(dev_priv);
10666         i915_update_gfx_val(dev_priv);
10667         if (INTEL_INFO(dev)->gen >= 6)
10668                 gen6_rps_busy(dev_priv);
10669         dev_priv->mm.busy = true;
10670 }
10671
10672 void intel_mark_idle(struct drm_device *dev)
10673 {
10674         struct drm_i915_private *dev_priv = dev->dev_private;
10675         struct drm_crtc *crtc;
10676
10677         if (!dev_priv->mm.busy)
10678                 return;
10679
10680         dev_priv->mm.busy = false;
10681
10682         for_each_crtc(dev, crtc) {
10683                 if (!crtc->primary->fb)
10684                         continue;
10685
10686                 intel_decrease_pllclock(crtc);
10687         }
10688
10689         if (INTEL_INFO(dev)->gen >= 6)
10690                 gen6_rps_idle(dev->dev_private);
10691
10692         intel_runtime_pm_put(dev_priv);
10693 }
10694
10695 static void intel_crtc_destroy(struct drm_crtc *crtc)
10696 {
10697         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10698         struct drm_device *dev = crtc->dev;
10699         struct intel_unpin_work *work;
10700
10701         spin_lock_irq(&dev->event_lock);
10702         work = intel_crtc->unpin_work;
10703         intel_crtc->unpin_work = NULL;
10704         spin_unlock_irq(&dev->event_lock);
10705
10706         if (work) {
10707                 cancel_work_sync(&work->work);
10708                 kfree(work);
10709         }
10710
10711         drm_crtc_cleanup(crtc);
10712
10713         kfree(intel_crtc);
10714 }
10715
10716 static void intel_unpin_work_fn(struct work_struct *__work)
10717 {
10718         struct intel_unpin_work *work =
10719                 container_of(__work, struct intel_unpin_work, work);
10720         struct drm_device *dev = work->crtc->dev;
10721         enum pipe pipe = to_intel_crtc(work->crtc)->pipe;
10722
10723         mutex_lock(&dev->struct_mutex);
10724         intel_unpin_fb_obj(work->old_fb, work->crtc->primary->state);
10725         drm_gem_object_unreference(&work->pending_flip_obj->base);
10726
10727         intel_fbc_update(dev);
10728
10729         if (work->flip_queued_req)
10730                 i915_gem_request_assign(&work->flip_queued_req, NULL);
10731         mutex_unlock(&dev->struct_mutex);
10732
10733         intel_frontbuffer_flip_complete(dev, INTEL_FRONTBUFFER_PRIMARY(pipe));
10734         drm_framebuffer_unreference(work->old_fb);
10735
10736         BUG_ON(atomic_read(&to_intel_crtc(work->crtc)->unpin_work_count) == 0);
10737         atomic_dec(&to_intel_crtc(work->crtc)->unpin_work_count);
10738
10739         kfree(work);
10740 }
10741
10742 static void do_intel_finish_page_flip(struct drm_device *dev,
10743                                       struct drm_crtc *crtc)
10744 {
10745         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10746         struct intel_unpin_work *work;
10747         unsigned long flags;
10748
10749         /* Ignore early vblank irqs */
10750         if (intel_crtc == NULL)
10751                 return;
10752
10753         /*
10754          * This is called both by irq handlers and the reset code (to complete
10755          * lost pageflips) so needs the full irqsave spinlocks.
10756          */
10757         spin_lock_irqsave(&dev->event_lock, flags);
10758         work = intel_crtc->unpin_work;
10759
10760         /* Ensure we don't miss a work->pending update ... */
10761         smp_rmb();
10762
10763         if (work == NULL || atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) {
10764                 spin_unlock_irqrestore(&dev->event_lock, flags);
10765                 return;
10766         }
10767
10768         page_flip_completed(intel_crtc);
10769
10770         spin_unlock_irqrestore(&dev->event_lock, flags);
10771 }
10772
10773 void intel_finish_page_flip(struct drm_device *dev, int pipe)
10774 {
10775         struct drm_i915_private *dev_priv = dev->dev_private;
10776         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
10777
10778         do_intel_finish_page_flip(dev, crtc);
10779 }
10780
10781 void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
10782 {
10783         struct drm_i915_private *dev_priv = dev->dev_private;
10784         struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
10785
10786         do_intel_finish_page_flip(dev, crtc);
10787 }
10788
10789 /* Is 'a' after or equal to 'b'? */
10790 static bool g4x_flip_count_after_eq(u32 a, u32 b)
10791 {
10792         return !((a - b) & 0x80000000);
10793 }
10794
10795 static bool page_flip_finished(struct intel_crtc *crtc)
10796 {
10797         struct drm_device *dev = crtc->base.dev;
10798         struct drm_i915_private *dev_priv = dev->dev_private;
10799
10800         if (i915_reset_in_progress(&dev_priv->gpu_error) ||
10801             crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
10802                 return true;
10803
10804         /*
10805          * The relevant registers doen't exist on pre-ctg.
10806          * As the flip done interrupt doesn't trigger for mmio
10807          * flips on gmch platforms, a flip count check isn't
10808          * really needed there. But since ctg has the registers,
10809          * include it in the check anyway.
10810          */
10811         if (INTEL_INFO(dev)->gen < 5 && !IS_G4X(dev))
10812                 return true;
10813
10814         /*
10815          * A DSPSURFLIVE check isn't enough in case the mmio and CS flips
10816          * used the same base address. In that case the mmio flip might
10817          * have completed, but the CS hasn't even executed the flip yet.
10818          *
10819          * A flip count check isn't enough as the CS might have updated
10820          * the base address just after start of vblank, but before we
10821          * managed to process the interrupt. This means we'd complete the
10822          * CS flip too soon.
10823          *
10824          * Combining both checks should get us a good enough result. It may
10825          * still happen that the CS flip has been executed, but has not
10826          * yet actually completed. But in case the base address is the same
10827          * anyway, we don't really care.
10828          */
10829         return (I915_READ(DSPSURFLIVE(crtc->plane)) & ~0xfff) ==
10830                 crtc->unpin_work->gtt_offset &&
10831                 g4x_flip_count_after_eq(I915_READ(PIPE_FLIPCOUNT_GM45(crtc->pipe)),
10832                                     crtc->unpin_work->flip_count);
10833 }
10834
10835 void intel_prepare_page_flip(struct drm_device *dev, int plane)
10836 {
10837         struct drm_i915_private *dev_priv = dev->dev_private;
10838         struct intel_crtc *intel_crtc =
10839                 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
10840         unsigned long flags;
10841
10842
10843         /*
10844          * This is called both by irq handlers and the reset code (to complete
10845          * lost pageflips) so needs the full irqsave spinlocks.
10846          *
10847          * NB: An MMIO update of the plane base pointer will also
10848          * generate a page-flip completion irq, i.e. every modeset
10849          * is also accompanied by a spurious intel_prepare_page_flip().
10850          */
10851         spin_lock_irqsave(&dev->event_lock, flags);
10852         if (intel_crtc->unpin_work && page_flip_finished(intel_crtc))
10853                 atomic_inc_not_zero(&intel_crtc->unpin_work->pending);
10854         spin_unlock_irqrestore(&dev->event_lock, flags);
10855 }
10856
10857 static inline void intel_mark_page_flip_active(struct intel_crtc *intel_crtc)
10858 {
10859         /* Ensure that the work item is consistent when activating it ... */
10860         smp_wmb();
10861         atomic_set(&intel_crtc->unpin_work->pending, INTEL_FLIP_PENDING);
10862         /* and that it is marked active as soon as the irq could fire. */
10863         smp_wmb();
10864 }
10865
10866 static int intel_gen2_queue_flip(struct drm_device *dev,
10867                                  struct drm_crtc *crtc,
10868                                  struct drm_framebuffer *fb,
10869                                  struct drm_i915_gem_object *obj,
10870                                  struct intel_engine_cs *ring,
10871                                  uint32_t flags)
10872 {
10873         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10874         u32 flip_mask;
10875         int ret;
10876
10877         ret = intel_ring_begin(ring, 6);
10878         if (ret)
10879                 return ret;
10880
10881         /* Can't queue multiple flips, so wait for the previous
10882          * one to finish before executing the next.
10883          */
10884         if (intel_crtc->plane)
10885                 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
10886         else
10887                 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
10888         intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
10889         intel_ring_emit(ring, MI_NOOP);
10890         intel_ring_emit(ring, MI_DISPLAY_FLIP |
10891                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
10892         intel_ring_emit(ring, fb->pitches[0]);
10893         intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
10894         intel_ring_emit(ring, 0); /* aux display base address, unused */
10895
10896         intel_mark_page_flip_active(intel_crtc);
10897         __intel_ring_advance(ring);
10898         return 0;
10899 }
10900
10901 static int intel_gen3_queue_flip(struct drm_device *dev,
10902                                  struct drm_crtc *crtc,
10903                                  struct drm_framebuffer *fb,
10904                                  struct drm_i915_gem_object *obj,
10905                                  struct intel_engine_cs *ring,
10906                                  uint32_t flags)
10907 {
10908         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10909         u32 flip_mask;
10910         int ret;
10911
10912         ret = intel_ring_begin(ring, 6);
10913         if (ret)
10914                 return ret;
10915
10916         if (intel_crtc->plane)
10917                 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
10918         else
10919                 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
10920         intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
10921         intel_ring_emit(ring, MI_NOOP);
10922         intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 |
10923                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
10924         intel_ring_emit(ring, fb->pitches[0]);
10925         intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
10926         intel_ring_emit(ring, MI_NOOP);
10927
10928         intel_mark_page_flip_active(intel_crtc);
10929         __intel_ring_advance(ring);
10930         return 0;
10931 }
10932
10933 static int intel_gen4_queue_flip(struct drm_device *dev,
10934                                  struct drm_crtc *crtc,
10935                                  struct drm_framebuffer *fb,
10936                                  struct drm_i915_gem_object *obj,
10937                                  struct intel_engine_cs *ring,
10938                                  uint32_t flags)
10939 {
10940         struct drm_i915_private *dev_priv = dev->dev_private;
10941         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10942         uint32_t pf, pipesrc;
10943         int ret;
10944
10945         ret = intel_ring_begin(ring, 4);
10946         if (ret)
10947                 return ret;
10948
10949         /* i965+ uses the linear or tiled offsets from the
10950          * Display Registers (which do not change across a page-flip)
10951          * so we need only reprogram the base address.
10952          */
10953         intel_ring_emit(ring, MI_DISPLAY_FLIP |
10954                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
10955         intel_ring_emit(ring, fb->pitches[0]);
10956         intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset |
10957                         obj->tiling_mode);
10958
10959         /* XXX Enabling the panel-fitter across page-flip is so far
10960          * untested on non-native modes, so ignore it for now.
10961          * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
10962          */
10963         pf = 0;
10964         pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
10965         intel_ring_emit(ring, pf | pipesrc);
10966
10967         intel_mark_page_flip_active(intel_crtc);
10968         __intel_ring_advance(ring);
10969         return 0;
10970 }
10971
10972 static int intel_gen6_queue_flip(struct drm_device *dev,
10973                                  struct drm_crtc *crtc,
10974                                  struct drm_framebuffer *fb,
10975                                  struct drm_i915_gem_object *obj,
10976                                  struct intel_engine_cs *ring,
10977                                  uint32_t flags)
10978 {
10979         struct drm_i915_private *dev_priv = dev->dev_private;
10980         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10981         uint32_t pf, pipesrc;
10982         int ret;
10983
10984         ret = intel_ring_begin(ring, 4);
10985         if (ret)
10986                 return ret;
10987
10988         intel_ring_emit(ring, MI_DISPLAY_FLIP |
10989                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
10990         intel_ring_emit(ring, fb->pitches[0] | obj->tiling_mode);
10991         intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
10992
10993         /* Contrary to the suggestions in the documentation,
10994          * "Enable Panel Fitter" does not seem to be required when page
10995          * flipping with a non-native mode, and worse causes a normal
10996          * modeset to fail.
10997          * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
10998          */
10999         pf = 0;
11000         pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
11001         intel_ring_emit(ring, pf | pipesrc);
11002
11003         intel_mark_page_flip_active(intel_crtc);
11004         __intel_ring_advance(ring);
11005         return 0;
11006 }
11007
11008 static int intel_gen7_queue_flip(struct drm_device *dev,
11009                                  struct drm_crtc *crtc,
11010                                  struct drm_framebuffer *fb,
11011                                  struct drm_i915_gem_object *obj,
11012                                  struct intel_engine_cs *ring,
11013                                  uint32_t flags)
11014 {
11015         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11016         uint32_t plane_bit = 0;
11017         int len, ret;
11018
11019         switch (intel_crtc->plane) {
11020         case PLANE_A:
11021                 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A;
11022                 break;
11023         case PLANE_B:
11024                 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B;
11025                 break;
11026         case PLANE_C:
11027                 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C;
11028                 break;
11029         default:
11030                 WARN_ONCE(1, "unknown plane in flip command\n");
11031                 return -ENODEV;
11032         }
11033
11034         len = 4;
11035         if (ring->id == RCS) {
11036                 len += 6;
11037                 /*
11038                  * On Gen 8, SRM is now taking an extra dword to accommodate
11039                  * 48bits addresses, and we need a NOOP for the batch size to
11040                  * stay even.
11041                  */
11042                 if (IS_GEN8(dev))
11043                         len += 2;
11044         }
11045
11046         /*
11047          * BSpec MI_DISPLAY_FLIP for IVB:
11048          * "The full packet must be contained within the same cache line."
11049          *
11050          * Currently the LRI+SRM+MI_DISPLAY_FLIP all fit within the same
11051          * cacheline, if we ever start emitting more commands before
11052          * the MI_DISPLAY_FLIP we may need to first emit everything else,
11053          * then do the cacheline alignment, and finally emit the
11054          * MI_DISPLAY_FLIP.
11055          */
11056         ret = intel_ring_cacheline_align(ring);
11057         if (ret)
11058                 return ret;
11059
11060         ret = intel_ring_begin(ring, len);
11061         if (ret)
11062                 return ret;
11063
11064         /* Unmask the flip-done completion message. Note that the bspec says that
11065          * we should do this for both the BCS and RCS, and that we must not unmask
11066          * more than one flip event at any time (or ensure that one flip message
11067          * can be sent by waiting for flip-done prior to queueing new flips).
11068          * Experimentation says that BCS works despite DERRMR masking all
11069          * flip-done completion events and that unmasking all planes at once
11070          * for the RCS also doesn't appear to drop events. Setting the DERRMR
11071          * to zero does lead to lockups within MI_DISPLAY_FLIP.
11072          */
11073         if (ring->id == RCS) {
11074                 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
11075                 intel_ring_emit(ring, DERRMR);
11076                 intel_ring_emit(ring, ~(DERRMR_PIPEA_PRI_FLIP_DONE |
11077                                         DERRMR_PIPEB_PRI_FLIP_DONE |
11078                                         DERRMR_PIPEC_PRI_FLIP_DONE));
11079                 if (IS_GEN8(dev))
11080                         intel_ring_emit(ring, MI_STORE_REGISTER_MEM_GEN8(1) |
11081                                               MI_SRM_LRM_GLOBAL_GTT);
11082                 else
11083                         intel_ring_emit(ring, MI_STORE_REGISTER_MEM(1) |
11084                                               MI_SRM_LRM_GLOBAL_GTT);
11085                 intel_ring_emit(ring, DERRMR);
11086                 intel_ring_emit(ring, ring->scratch.gtt_offset + 256);
11087                 if (IS_GEN8(dev)) {
11088                         intel_ring_emit(ring, 0);
11089                         intel_ring_emit(ring, MI_NOOP);
11090                 }
11091         }
11092
11093         intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit);
11094         intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode));
11095         intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
11096         intel_ring_emit(ring, (MI_NOOP));
11097
11098         intel_mark_page_flip_active(intel_crtc);
11099         __intel_ring_advance(ring);
11100         return 0;
11101 }
11102
11103 static bool use_mmio_flip(struct intel_engine_cs *ring,
11104                           struct drm_i915_gem_object *obj)
11105 {
11106         /*
11107          * This is not being used for older platforms, because
11108          * non-availability of flip done interrupt forces us to use
11109          * CS flips. Older platforms derive flip done using some clever
11110          * tricks involving the flip_pending status bits and vblank irqs.
11111          * So using MMIO flips there would disrupt this mechanism.
11112          */
11113
11114         if (ring == NULL)
11115                 return true;
11116
11117         if (INTEL_INFO(ring->dev)->gen < 5)
11118                 return false;
11119
11120         if (i915.use_mmio_flip < 0)
11121                 return false;
11122         else if (i915.use_mmio_flip > 0)
11123                 return true;
11124         else if (i915.enable_execlists)
11125                 return true;
11126         else
11127                 return ring != i915_gem_request_get_ring(obj->last_write_req);
11128 }
11129
11130 static void skl_do_mmio_flip(struct intel_crtc *intel_crtc)
11131 {
11132         struct drm_device *dev = intel_crtc->base.dev;
11133         struct drm_i915_private *dev_priv = dev->dev_private;
11134         struct drm_framebuffer *fb = intel_crtc->base.primary->fb;
11135         const enum pipe pipe = intel_crtc->pipe;
11136         u32 ctl, stride;
11137
11138         ctl = I915_READ(PLANE_CTL(pipe, 0));
11139         ctl &= ~PLANE_CTL_TILED_MASK;
11140         switch (fb->modifier[0]) {
11141         case DRM_FORMAT_MOD_NONE:
11142                 break;
11143         case I915_FORMAT_MOD_X_TILED:
11144                 ctl |= PLANE_CTL_TILED_X;
11145                 break;
11146         case I915_FORMAT_MOD_Y_TILED:
11147                 ctl |= PLANE_CTL_TILED_Y;
11148                 break;
11149         case I915_FORMAT_MOD_Yf_TILED:
11150                 ctl |= PLANE_CTL_TILED_YF;
11151                 break;
11152         default:
11153                 MISSING_CASE(fb->modifier[0]);
11154         }
11155
11156         /*
11157          * The stride is either expressed as a multiple of 64 bytes chunks for
11158          * linear buffers or in number of tiles for tiled buffers.
11159          */
11160         stride = fb->pitches[0] /
11161                  intel_fb_stride_alignment(dev, fb->modifier[0],
11162                                            fb->pixel_format);
11163
11164         /*
11165          * Both PLANE_CTL and PLANE_STRIDE are not updated on vblank but on
11166          * PLANE_SURF updates, the update is then guaranteed to be atomic.
11167          */
11168         I915_WRITE(PLANE_CTL(pipe, 0), ctl);
11169         I915_WRITE(PLANE_STRIDE(pipe, 0), stride);
11170
11171         I915_WRITE(PLANE_SURF(pipe, 0), intel_crtc->unpin_work->gtt_offset);
11172         POSTING_READ(PLANE_SURF(pipe, 0));
11173 }
11174
11175 static void ilk_do_mmio_flip(struct intel_crtc *intel_crtc)
11176 {
11177         struct drm_device *dev = intel_crtc->base.dev;
11178         struct drm_i915_private *dev_priv = dev->dev_private;
11179         struct intel_framebuffer *intel_fb =
11180                 to_intel_framebuffer(intel_crtc->base.primary->fb);
11181         struct drm_i915_gem_object *obj = intel_fb->obj;
11182         u32 dspcntr;
11183         u32 reg;
11184
11185         reg = DSPCNTR(intel_crtc->plane);
11186         dspcntr = I915_READ(reg);
11187
11188         if (obj->tiling_mode != I915_TILING_NONE)
11189                 dspcntr |= DISPPLANE_TILED;
11190         else
11191                 dspcntr &= ~DISPPLANE_TILED;
11192
11193         I915_WRITE(reg, dspcntr);
11194
11195         I915_WRITE(DSPSURF(intel_crtc->plane),
11196                    intel_crtc->unpin_work->gtt_offset);
11197         POSTING_READ(DSPSURF(intel_crtc->plane));
11198
11199 }
11200
11201 /*
11202  * XXX: This is the temporary way to update the plane registers until we get
11203  * around to using the usual plane update functions for MMIO flips
11204  */
11205 static void intel_do_mmio_flip(struct intel_crtc *intel_crtc)
11206 {
11207         struct drm_device *dev = intel_crtc->base.dev;
11208         bool atomic_update;
11209         u32 start_vbl_count;
11210
11211         intel_mark_page_flip_active(intel_crtc);
11212
11213         atomic_update = intel_pipe_update_start(intel_crtc, &start_vbl_count);
11214
11215         if (INTEL_INFO(dev)->gen >= 9)
11216                 skl_do_mmio_flip(intel_crtc);
11217         else
11218                 /* use_mmio_flip() retricts MMIO flips to ilk+ */
11219                 ilk_do_mmio_flip(intel_crtc);
11220
11221         if (atomic_update)
11222                 intel_pipe_update_end(intel_crtc, start_vbl_count);
11223 }
11224
11225 static void intel_mmio_flip_work_func(struct work_struct *work)
11226 {
11227         struct intel_mmio_flip *mmio_flip =
11228                 container_of(work, struct intel_mmio_flip, work);
11229
11230         if (mmio_flip->req)
11231                 WARN_ON(__i915_wait_request(mmio_flip->req,
11232                                             mmio_flip->crtc->reset_counter,
11233                                             false, NULL,
11234                                             &mmio_flip->i915->rps.mmioflips));
11235
11236         intel_do_mmio_flip(mmio_flip->crtc);
11237
11238         i915_gem_request_unreference__unlocked(mmio_flip->req);
11239         kfree(mmio_flip);
11240 }
11241
11242 static int intel_queue_mmio_flip(struct drm_device *dev,
11243                                  struct drm_crtc *crtc,
11244                                  struct drm_framebuffer *fb,
11245                                  struct drm_i915_gem_object *obj,
11246                                  struct intel_engine_cs *ring,
11247                                  uint32_t flags)
11248 {
11249         struct intel_mmio_flip *mmio_flip;
11250
11251         mmio_flip = kmalloc(sizeof(*mmio_flip), GFP_KERNEL);
11252         if (mmio_flip == NULL)
11253                 return -ENOMEM;
11254
11255         mmio_flip->i915 = to_i915(dev);
11256         mmio_flip->req = i915_gem_request_reference(obj->last_write_req);
11257         mmio_flip->crtc = to_intel_crtc(crtc);
11258
11259         INIT_WORK(&mmio_flip->work, intel_mmio_flip_work_func);
11260         schedule_work(&mmio_flip->work);
11261
11262         return 0;
11263 }
11264
11265 static int intel_default_queue_flip(struct drm_device *dev,
11266                                     struct drm_crtc *crtc,
11267                                     struct drm_framebuffer *fb,
11268                                     struct drm_i915_gem_object *obj,
11269                                     struct intel_engine_cs *ring,
11270                                     uint32_t flags)
11271 {
11272         return -ENODEV;
11273 }
11274
11275 static bool __intel_pageflip_stall_check(struct drm_device *dev,
11276                                          struct drm_crtc *crtc)
11277 {
11278         struct drm_i915_private *dev_priv = dev->dev_private;
11279         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11280         struct intel_unpin_work *work = intel_crtc->unpin_work;
11281         u32 addr;
11282
11283         if (atomic_read(&work->pending) >= INTEL_FLIP_COMPLETE)
11284                 return true;
11285
11286         if (!work->enable_stall_check)
11287                 return false;
11288
11289         if (work->flip_ready_vblank == 0) {
11290                 if (work->flip_queued_req &&
11291                     !i915_gem_request_completed(work->flip_queued_req, true))
11292                         return false;
11293
11294                 work->flip_ready_vblank = drm_crtc_vblank_count(crtc);
11295         }
11296
11297         if (drm_crtc_vblank_count(crtc) - work->flip_ready_vblank < 3)
11298                 return false;
11299
11300         /* Potential stall - if we see that the flip has happened,
11301          * assume a missed interrupt. */
11302         if (INTEL_INFO(dev)->gen >= 4)
11303                 addr = I915_HI_DISPBASE(I915_READ(DSPSURF(intel_crtc->plane)));
11304         else
11305                 addr = I915_READ(DSPADDR(intel_crtc->plane));
11306
11307         /* There is a potential issue here with a false positive after a flip
11308          * to the same address. We could address this by checking for a
11309          * non-incrementing frame counter.
11310          */
11311         return addr == work->gtt_offset;
11312 }
11313
11314 void intel_check_page_flip(struct drm_device *dev, int pipe)
11315 {
11316         struct drm_i915_private *dev_priv = dev->dev_private;
11317         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
11318         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11319         struct intel_unpin_work *work;
11320
11321         WARN_ON(!in_interrupt());
11322
11323         if (crtc == NULL)
11324                 return;
11325
11326         spin_lock(&dev->event_lock);
11327         work = intel_crtc->unpin_work;
11328         if (work != NULL && __intel_pageflip_stall_check(dev, crtc)) {
11329                 WARN_ONCE(1, "Kicking stuck page flip: queued at %d, now %d\n",
11330                          work->flip_queued_vblank, drm_vblank_count(dev, pipe));
11331                 page_flip_completed(intel_crtc);
11332                 work = NULL;
11333         }
11334         if (work != NULL &&
11335             drm_vblank_count(dev, pipe) - work->flip_queued_vblank > 1)
11336                 intel_queue_rps_boost_for_request(dev, work->flip_queued_req);
11337         spin_unlock(&dev->event_lock);
11338 }
11339
11340 static int intel_crtc_page_flip(struct drm_crtc *crtc,
11341                                 struct drm_framebuffer *fb,
11342                                 struct drm_pending_vblank_event *event,
11343                                 uint32_t page_flip_flags)
11344 {
11345         struct drm_device *dev = crtc->dev;
11346         struct drm_i915_private *dev_priv = dev->dev_private;
11347         struct drm_framebuffer *old_fb = crtc->primary->fb;
11348         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
11349         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11350         struct drm_plane *primary = crtc->primary;
11351         enum pipe pipe = intel_crtc->pipe;
11352         struct intel_unpin_work *work;
11353         struct intel_engine_cs *ring;
11354         bool mmio_flip;
11355         int ret;
11356
11357         /*
11358          * drm_mode_page_flip_ioctl() should already catch this, but double
11359          * check to be safe.  In the future we may enable pageflipping from
11360          * a disabled primary plane.
11361          */
11362         if (WARN_ON(intel_fb_obj(old_fb) == NULL))
11363                 return -EBUSY;
11364
11365         /* Can't change pixel format via MI display flips. */
11366         if (fb->pixel_format != crtc->primary->fb->pixel_format)
11367                 return -EINVAL;
11368
11369         /*
11370          * TILEOFF/LINOFF registers can't be changed via MI display flips.
11371          * Note that pitch changes could also affect these register.
11372          */
11373         if (INTEL_INFO(dev)->gen > 3 &&
11374             (fb->offsets[0] != crtc->primary->fb->offsets[0] ||
11375              fb->pitches[0] != crtc->primary->fb->pitches[0]))
11376                 return -EINVAL;
11377
11378         if (i915_terminally_wedged(&dev_priv->gpu_error))
11379                 goto out_hang;
11380
11381         work = kzalloc(sizeof(*work), GFP_KERNEL);
11382         if (work == NULL)
11383                 return -ENOMEM;
11384
11385         work->event = event;
11386         work->crtc = crtc;
11387         work->old_fb = old_fb;
11388         INIT_WORK(&work->work, intel_unpin_work_fn);
11389
11390         ret = drm_crtc_vblank_get(crtc);
11391         if (ret)
11392                 goto free_work;
11393
11394         /* We borrow the event spin lock for protecting unpin_work */
11395         spin_lock_irq(&dev->event_lock);
11396         if (intel_crtc->unpin_work) {
11397                 /* Before declaring the flip queue wedged, check if
11398                  * the hardware completed the operation behind our backs.
11399                  */
11400                 if (__intel_pageflip_stall_check(dev, crtc)) {
11401                         DRM_DEBUG_DRIVER("flip queue: previous flip completed, continuing\n");
11402                         page_flip_completed(intel_crtc);
11403                 } else {
11404                         DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
11405                         spin_unlock_irq(&dev->event_lock);
11406
11407                         drm_crtc_vblank_put(crtc);
11408                         kfree(work);
11409                         return -EBUSY;
11410                 }
11411         }
11412         intel_crtc->unpin_work = work;
11413         spin_unlock_irq(&dev->event_lock);
11414
11415         if (atomic_read(&intel_crtc->unpin_work_count) >= 2)
11416                 flush_workqueue(dev_priv->wq);
11417
11418         /* Reference the objects for the scheduled work. */
11419         drm_framebuffer_reference(work->old_fb);
11420         drm_gem_object_reference(&obj->base);
11421
11422         crtc->primary->fb = fb;
11423         update_state_fb(crtc->primary);
11424
11425         work->pending_flip_obj = obj;
11426
11427         ret = i915_mutex_lock_interruptible(dev);
11428         if (ret)
11429                 goto cleanup;
11430
11431         atomic_inc(&intel_crtc->unpin_work_count);
11432         intel_crtc->reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
11433
11434         if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev))
11435                 work->flip_count = I915_READ(PIPE_FLIPCOUNT_GM45(pipe)) + 1;
11436
11437         if (IS_VALLEYVIEW(dev)) {
11438                 ring = &dev_priv->ring[BCS];
11439                 if (obj->tiling_mode != intel_fb_obj(work->old_fb)->tiling_mode)
11440                         /* vlv: DISPLAY_FLIP fails to change tiling */
11441                         ring = NULL;
11442         } else if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) {
11443                 ring = &dev_priv->ring[BCS];
11444         } else if (INTEL_INFO(dev)->gen >= 7) {
11445                 ring = i915_gem_request_get_ring(obj->last_write_req);
11446                 if (ring == NULL || ring->id != RCS)
11447                         ring = &dev_priv->ring[BCS];
11448         } else {
11449                 ring = &dev_priv->ring[RCS];
11450         }
11451
11452         mmio_flip = use_mmio_flip(ring, obj);
11453
11454         /* When using CS flips, we want to emit semaphores between rings.
11455          * However, when using mmio flips we will create a task to do the
11456          * synchronisation, so all we want here is to pin the framebuffer
11457          * into the display plane and skip any waits.
11458          */
11459         ret = intel_pin_and_fence_fb_obj(crtc->primary, fb,
11460                                          crtc->primary->state,
11461                                          mmio_flip ? i915_gem_request_get_ring(obj->last_write_req) : ring);
11462         if (ret)
11463                 goto cleanup_pending;
11464
11465         work->gtt_offset = intel_plane_obj_offset(to_intel_plane(primary), obj)
11466                                                   + intel_crtc->dspaddr_offset;
11467
11468         if (mmio_flip) {
11469                 ret = intel_queue_mmio_flip(dev, crtc, fb, obj, ring,
11470                                             page_flip_flags);
11471                 if (ret)
11472                         goto cleanup_unpin;
11473
11474                 i915_gem_request_assign(&work->flip_queued_req,
11475                                         obj->last_write_req);
11476         } else {
11477                 if (obj->last_write_req) {
11478                         ret = i915_gem_check_olr(obj->last_write_req);
11479                         if (ret)
11480                                 goto cleanup_unpin;
11481                 }
11482
11483                 ret = dev_priv->display.queue_flip(dev, crtc, fb, obj, ring,
11484                                                    page_flip_flags);
11485                 if (ret)
11486                         goto cleanup_unpin;
11487
11488                 i915_gem_request_assign(&work->flip_queued_req,
11489                                         intel_ring_get_request(ring));
11490         }
11491
11492         work->flip_queued_vblank = drm_crtc_vblank_count(crtc);
11493         work->enable_stall_check = true;
11494
11495         i915_gem_track_fb(intel_fb_obj(work->old_fb), obj,
11496                           INTEL_FRONTBUFFER_PRIMARY(pipe));
11497
11498         intel_fbc_disable(dev);
11499         intel_frontbuffer_flip_prepare(dev, INTEL_FRONTBUFFER_PRIMARY(pipe));
11500         mutex_unlock(&dev->struct_mutex);
11501
11502         trace_i915_flip_request(intel_crtc->plane, obj);
11503
11504         return 0;
11505
11506 cleanup_unpin:
11507         intel_unpin_fb_obj(fb, crtc->primary->state);
11508 cleanup_pending:
11509         atomic_dec(&intel_crtc->unpin_work_count);
11510         mutex_unlock(&dev->struct_mutex);
11511 cleanup:
11512         crtc->primary->fb = old_fb;
11513         update_state_fb(crtc->primary);
11514
11515         drm_gem_object_unreference_unlocked(&obj->base);
11516         drm_framebuffer_unreference(work->old_fb);
11517
11518         spin_lock_irq(&dev->event_lock);
11519         intel_crtc->unpin_work = NULL;
11520         spin_unlock_irq(&dev->event_lock);
11521
11522         drm_crtc_vblank_put(crtc);
11523 free_work:
11524         kfree(work);
11525
11526         if (ret == -EIO) {
11527                 struct drm_atomic_state *state;
11528                 struct drm_plane_state *plane_state;
11529
11530 out_hang:
11531                 state = drm_atomic_state_alloc(dev);
11532                 if (!state)
11533                         return -ENOMEM;
11534                 state->acquire_ctx = drm_modeset_legacy_acquire_ctx(crtc);
11535
11536 retry:
11537                 plane_state = drm_atomic_get_plane_state(state, primary);
11538                 ret = PTR_ERR_OR_ZERO(plane_state);
11539                 if (!ret) {
11540                         drm_atomic_set_fb_for_plane(plane_state, fb);
11541
11542                         ret = drm_atomic_set_crtc_for_plane(plane_state, crtc);
11543                         if (!ret)
11544                                 ret = drm_atomic_commit(state);
11545                 }
11546
11547                 if (ret == -EDEADLK) {
11548                         drm_modeset_backoff(state->acquire_ctx);
11549                         drm_atomic_state_clear(state);
11550                         goto retry;
11551                 }
11552
11553                 if (ret)
11554                         drm_atomic_state_free(state);
11555
11556                 if (ret == 0 && event) {
11557                         spin_lock_irq(&dev->event_lock);
11558                         drm_send_vblank_event(dev, pipe, event);
11559                         spin_unlock_irq(&dev->event_lock);
11560                 }
11561         }
11562         return ret;
11563 }
11564
11565
11566 /**
11567  * intel_wm_need_update - Check whether watermarks need updating
11568  * @plane: drm plane
11569  * @state: new plane state
11570  *
11571  * Check current plane state versus the new one to determine whether
11572  * watermarks need to be recalculated.
11573  *
11574  * Returns true or false.
11575  */
11576 static bool intel_wm_need_update(struct drm_plane *plane,
11577                                  struct drm_plane_state *state)
11578 {
11579         /* Update watermarks on tiling changes. */
11580         if (!plane->state->fb || !state->fb ||
11581             plane->state->fb->modifier[0] != state->fb->modifier[0] ||
11582             plane->state->rotation != state->rotation)
11583                 return true;
11584
11585         if (plane->state->crtc_w != state->crtc_w)
11586                 return true;
11587
11588         return false;
11589 }
11590
11591 int intel_plane_atomic_calc_changes(struct drm_crtc_state *crtc_state,
11592                                     struct drm_plane_state *plane_state)
11593 {
11594         struct drm_crtc *crtc = crtc_state->crtc;
11595         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11596         struct drm_plane *plane = plane_state->plane;
11597         struct drm_device *dev = crtc->dev;
11598         struct drm_i915_private *dev_priv = dev->dev_private;
11599         struct intel_plane_state *old_plane_state =
11600                 to_intel_plane_state(plane->state);
11601         int idx = intel_crtc->base.base.id, ret;
11602         int i = drm_plane_index(plane);
11603         bool mode_changed = needs_modeset(crtc_state);
11604         bool was_crtc_enabled = crtc->state->active;
11605         bool is_crtc_enabled = crtc_state->active;
11606
11607         bool turn_off, turn_on, visible, was_visible;
11608         struct drm_framebuffer *fb = plane_state->fb;
11609
11610         if (crtc_state && INTEL_INFO(dev)->gen >= 9 &&
11611             plane->type != DRM_PLANE_TYPE_CURSOR) {
11612                 ret = skl_update_scaler_plane(
11613                         to_intel_crtc_state(crtc_state),
11614                         to_intel_plane_state(plane_state));
11615                 if (ret)
11616                         return ret;
11617         }
11618
11619         /*
11620          * Disabling a plane is always okay; we just need to update
11621          * fb tracking in a special way since cleanup_fb() won't
11622          * get called by the plane helpers.
11623          */
11624         if (old_plane_state->base.fb && !fb)
11625                 intel_crtc->atomic.disabled_planes |= 1 << i;
11626
11627         was_visible = old_plane_state->visible;
11628         visible = to_intel_plane_state(plane_state)->visible;
11629
11630         if (!was_crtc_enabled && WARN_ON(was_visible))
11631                 was_visible = false;
11632
11633         if (!is_crtc_enabled && WARN_ON(visible))
11634                 visible = false;
11635
11636         if (!was_visible && !visible)
11637                 return 0;
11638
11639         turn_off = was_visible && (!visible || mode_changed);
11640         turn_on = visible && (!was_visible || mode_changed);
11641
11642         DRM_DEBUG_ATOMIC("[CRTC:%i] has [PLANE:%i] with fb %i\n", idx,
11643                          plane->base.id, fb ? fb->base.id : -1);
11644
11645         DRM_DEBUG_ATOMIC("[PLANE:%i] visible %i -> %i, off %i, on %i, ms %i\n",
11646                          plane->base.id, was_visible, visible,
11647                          turn_off, turn_on, mode_changed);
11648
11649         if (intel_wm_need_update(plane, plane_state))
11650                 intel_crtc->atomic.update_wm = true;
11651
11652         switch (plane->type) {
11653         case DRM_PLANE_TYPE_PRIMARY:
11654                 if (visible)
11655                         intel_crtc->atomic.fb_bits |=
11656                             INTEL_FRONTBUFFER_PRIMARY(intel_crtc->pipe);
11657
11658                 intel_crtc->atomic.wait_for_flips = true;
11659                 intel_crtc->atomic.pre_disable_primary = turn_off;
11660                 intel_crtc->atomic.post_enable_primary = turn_on;
11661
11662                 if (turn_off)
11663                         intel_crtc->atomic.disable_fbc = true;
11664
11665                 /*
11666                  * FBC does not work on some platforms for rotated
11667                  * planes, so disable it when rotation is not 0 and
11668                  * update it when rotation is set back to 0.
11669                  *
11670                  * FIXME: This is redundant with the fbc update done in
11671                  * the primary plane enable function except that that
11672                  * one is done too late. We eventually need to unify
11673                  * this.
11674                  */
11675
11676                 if (visible &&
11677                     INTEL_INFO(dev)->gen <= 4 && !IS_G4X(dev) &&
11678                     dev_priv->fbc.crtc == intel_crtc &&
11679                     plane_state->rotation != BIT(DRM_ROTATE_0))
11680                         intel_crtc->atomic.disable_fbc = true;
11681
11682                 /*
11683                  * BDW signals flip done immediately if the plane
11684                  * is disabled, even if the plane enable is already
11685                  * armed to occur at the next vblank :(
11686                  */
11687                 if (turn_on && IS_BROADWELL(dev))
11688                         intel_crtc->atomic.wait_vblank = true;
11689
11690                 intel_crtc->atomic.update_fbc |= visible || mode_changed;
11691                 break;
11692         case DRM_PLANE_TYPE_CURSOR:
11693                 if (visible)
11694                         intel_crtc->atomic.fb_bits |=
11695                             INTEL_FRONTBUFFER_CURSOR(intel_crtc->pipe);
11696                 break;
11697         case DRM_PLANE_TYPE_OVERLAY:
11698                 /*
11699                  * 'prepare' is never called when plane is being disabled, so
11700                  * we need to handle frontbuffer tracking as a special case
11701                  */
11702                 if (visible)
11703                         intel_crtc->atomic.fb_bits |=
11704                             INTEL_FRONTBUFFER_SPRITE(intel_crtc->pipe);
11705
11706                 if (turn_off && !mode_changed) {
11707                         intel_crtc->atomic.wait_vblank = true;
11708                         intel_crtc->atomic.update_sprite_watermarks |=
11709                                 1 << i;
11710                 }
11711                 break;
11712         }
11713         return 0;
11714 }
11715
11716 static bool encoders_cloneable(const struct intel_encoder *a,
11717                                const struct intel_encoder *b)
11718 {
11719         /* masks could be asymmetric, so check both ways */
11720         return a == b || (a->cloneable & (1 << b->type) &&
11721                           b->cloneable & (1 << a->type));
11722 }
11723
11724 static bool check_single_encoder_cloning(struct drm_atomic_state *state,
11725                                          struct intel_crtc *crtc,
11726                                          struct intel_encoder *encoder)
11727 {
11728         struct intel_encoder *source_encoder;
11729         struct drm_connector *connector;
11730         struct drm_connector_state *connector_state;
11731         int i;
11732
11733         for_each_connector_in_state(state, connector, connector_state, i) {
11734                 if (connector_state->crtc != &crtc->base)
11735                         continue;
11736
11737                 source_encoder =
11738                         to_intel_encoder(connector_state->best_encoder);
11739                 if (!encoders_cloneable(encoder, source_encoder))
11740                         return false;
11741         }
11742
11743         return true;
11744 }
11745
11746 static bool check_encoder_cloning(struct drm_atomic_state *state,
11747                                   struct intel_crtc *crtc)
11748 {
11749         struct intel_encoder *encoder;
11750         struct drm_connector *connector;
11751         struct drm_connector_state *connector_state;
11752         int i;
11753
11754         for_each_connector_in_state(state, connector, connector_state, i) {
11755                 if (connector_state->crtc != &crtc->base)
11756                         continue;
11757
11758                 encoder = to_intel_encoder(connector_state->best_encoder);
11759                 if (!check_single_encoder_cloning(state, crtc, encoder))
11760                         return false;
11761         }
11762
11763         return true;
11764 }
11765
11766 static void intel_crtc_check_initial_planes(struct drm_crtc *crtc,
11767                                             struct drm_crtc_state *crtc_state)
11768 {
11769         struct intel_crtc_state *pipe_config =
11770                 to_intel_crtc_state(crtc_state);
11771         struct drm_plane *p;
11772         unsigned visible_mask = 0;
11773
11774         drm_for_each_plane_mask(p, crtc->dev, crtc_state->plane_mask) {
11775                 struct drm_plane_state *plane_state =
11776                         drm_atomic_get_existing_plane_state(crtc_state->state, p);
11777
11778                 if (WARN_ON(!plane_state))
11779                         continue;
11780
11781                 if (!plane_state->fb)
11782                         crtc_state->plane_mask &=
11783                                 ~(1 << drm_plane_index(p));
11784                 else if (to_intel_plane_state(plane_state)->visible)
11785                         visible_mask |= 1 << drm_plane_index(p);
11786         }
11787
11788         if (!visible_mask)
11789                 return;
11790
11791         pipe_config->quirks &= ~PIPE_CONFIG_QUIRK_INITIAL_PLANES;
11792 }
11793
11794 static int intel_crtc_atomic_check(struct drm_crtc *crtc,
11795                                    struct drm_crtc_state *crtc_state)
11796 {
11797         struct drm_device *dev = crtc->dev;
11798         struct drm_i915_private *dev_priv = dev->dev_private;
11799         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11800         struct intel_crtc_state *pipe_config =
11801                 to_intel_crtc_state(crtc_state);
11802         struct drm_atomic_state *state = crtc_state->state;
11803         int ret, idx = crtc->base.id;
11804         bool mode_changed = needs_modeset(crtc_state);
11805
11806         if (mode_changed && !check_encoder_cloning(state, intel_crtc)) {
11807                 DRM_DEBUG_KMS("rejecting invalid cloning configuration\n");
11808                 return -EINVAL;
11809         }
11810
11811         I915_STATE_WARN(crtc->state->active != intel_crtc->active,
11812                 "[CRTC:%i] mismatch between state->active(%i) and crtc->active(%i)\n",
11813                 idx, crtc->state->active, intel_crtc->active);
11814
11815         /* plane mask is fixed up after all initial planes are calculated */
11816         if (pipe_config->quirks & PIPE_CONFIG_QUIRK_INITIAL_PLANES)
11817                 intel_crtc_check_initial_planes(crtc, crtc_state);
11818
11819         if (mode_changed)
11820                 intel_crtc->atomic.update_wm = !crtc_state->active;
11821
11822         if (mode_changed && crtc_state->enable &&
11823             dev_priv->display.crtc_compute_clock &&
11824             !WARN_ON(pipe_config->shared_dpll != DPLL_ID_PRIVATE)) {
11825                 ret = dev_priv->display.crtc_compute_clock(intel_crtc,
11826                                                            pipe_config);
11827                 if (ret)
11828                         return ret;
11829         }
11830
11831         return intel_atomic_setup_scalers(dev, intel_crtc, pipe_config);
11832 }
11833
11834 static const struct drm_crtc_helper_funcs intel_helper_funcs = {
11835         .mode_set_base_atomic = intel_pipe_set_base_atomic,
11836         .load_lut = intel_crtc_load_lut,
11837         .atomic_begin = intel_begin_crtc_commit,
11838         .atomic_flush = intel_finish_crtc_commit,
11839         .atomic_check = intel_crtc_atomic_check,
11840 };
11841
11842 /**
11843  * intel_modeset_update_staged_output_state
11844  *
11845  * Updates the staged output configuration state, e.g. after we've read out the
11846  * current hw state.
11847  */
11848 static void intel_modeset_update_staged_output_state(struct drm_device *dev)
11849 {
11850         struct intel_crtc *crtc;
11851         struct intel_encoder *encoder;
11852         struct intel_connector *connector;
11853
11854         for_each_intel_connector(dev, connector) {
11855                 connector->new_encoder =
11856                         to_intel_encoder(connector->base.encoder);
11857         }
11858
11859         for_each_intel_encoder(dev, encoder) {
11860                 encoder->new_crtc =
11861                         to_intel_crtc(encoder->base.crtc);
11862         }
11863
11864         for_each_intel_crtc(dev, crtc) {
11865                 crtc->new_enabled = crtc->base.state->enable;
11866         }
11867 }
11868
11869 /* Transitional helper to copy current connector/encoder state to
11870  * connector->state. This is needed so that code that is partially
11871  * converted to atomic does the right thing.
11872  */
11873 static void intel_modeset_update_connector_atomic_state(struct drm_device *dev)
11874 {
11875         struct intel_connector *connector;
11876
11877         for_each_intel_connector(dev, connector) {
11878                 if (connector->base.encoder) {
11879                         connector->base.state->best_encoder =
11880                                 connector->base.encoder;
11881                         connector->base.state->crtc =
11882                                 connector->base.encoder->crtc;
11883                 } else {
11884                         connector->base.state->best_encoder = NULL;
11885                         connector->base.state->crtc = NULL;
11886                 }
11887         }
11888 }
11889
11890 static void
11891 connected_sink_compute_bpp(struct intel_connector *connector,
11892                            struct intel_crtc_state *pipe_config)
11893 {
11894         int bpp = pipe_config->pipe_bpp;
11895
11896         DRM_DEBUG_KMS("[CONNECTOR:%d:%s] checking for sink bpp constrains\n",
11897                 connector->base.base.id,
11898                 connector->base.name);
11899
11900         /* Don't use an invalid EDID bpc value */
11901         if (connector->base.display_info.bpc &&
11902             connector->base.display_info.bpc * 3 < bpp) {
11903                 DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n",
11904                               bpp, connector->base.display_info.bpc*3);
11905                 pipe_config->pipe_bpp = connector->base.display_info.bpc*3;
11906         }
11907
11908         /* Clamp bpp to 8 on screens without EDID 1.4 */
11909         if (connector->base.display_info.bpc == 0 && bpp > 24) {
11910                 DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of 24\n",
11911                               bpp);
11912                 pipe_config->pipe_bpp = 24;
11913         }
11914 }
11915
11916 static int
11917 compute_baseline_pipe_bpp(struct intel_crtc *crtc,
11918                           struct intel_crtc_state *pipe_config)
11919 {
11920         struct drm_device *dev = crtc->base.dev;
11921         struct drm_atomic_state *state;
11922         struct drm_connector *connector;
11923         struct drm_connector_state *connector_state;
11924         int bpp, i;
11925
11926         if ((IS_G4X(dev) || IS_VALLEYVIEW(dev)))
11927                 bpp = 10*3;
11928         else if (INTEL_INFO(dev)->gen >= 5)
11929                 bpp = 12*3;
11930         else
11931                 bpp = 8*3;
11932
11933
11934         pipe_config->pipe_bpp = bpp;
11935
11936         state = pipe_config->base.state;
11937
11938         /* Clamp display bpp to EDID value */
11939         for_each_connector_in_state(state, connector, connector_state, i) {
11940                 if (connector_state->crtc != &crtc->base)
11941                         continue;
11942
11943                 connected_sink_compute_bpp(to_intel_connector(connector),
11944                                            pipe_config);
11945         }
11946
11947         return bpp;
11948 }
11949
11950 static void intel_dump_crtc_timings(const struct drm_display_mode *mode)
11951 {
11952         DRM_DEBUG_KMS("crtc timings: %d %d %d %d %d %d %d %d %d, "
11953                         "type: 0x%x flags: 0x%x\n",
11954                 mode->crtc_clock,
11955                 mode->crtc_hdisplay, mode->crtc_hsync_start,
11956                 mode->crtc_hsync_end, mode->crtc_htotal,
11957                 mode->crtc_vdisplay, mode->crtc_vsync_start,
11958                 mode->crtc_vsync_end, mode->crtc_vtotal, mode->type, mode->flags);
11959 }
11960
11961 static void intel_dump_pipe_config(struct intel_crtc *crtc,
11962                                    struct intel_crtc_state *pipe_config,
11963                                    const char *context)
11964 {
11965         struct drm_device *dev = crtc->base.dev;
11966         struct drm_plane *plane;
11967         struct intel_plane *intel_plane;
11968         struct intel_plane_state *state;
11969         struct drm_framebuffer *fb;
11970
11971         DRM_DEBUG_KMS("[CRTC:%d]%s config %p for pipe %c\n", crtc->base.base.id,
11972                       context, pipe_config, pipe_name(crtc->pipe));
11973
11974         DRM_DEBUG_KMS("cpu_transcoder: %c\n", transcoder_name(pipe_config->cpu_transcoder));
11975         DRM_DEBUG_KMS("pipe bpp: %i, dithering: %i\n",
11976                       pipe_config->pipe_bpp, pipe_config->dither);
11977         DRM_DEBUG_KMS("fdi/pch: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
11978                       pipe_config->has_pch_encoder,
11979                       pipe_config->fdi_lanes,
11980                       pipe_config->fdi_m_n.gmch_m, pipe_config->fdi_m_n.gmch_n,
11981                       pipe_config->fdi_m_n.link_m, pipe_config->fdi_m_n.link_n,
11982                       pipe_config->fdi_m_n.tu);
11983         DRM_DEBUG_KMS("dp: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
11984                       pipe_config->has_dp_encoder,
11985                       pipe_config->dp_m_n.gmch_m, pipe_config->dp_m_n.gmch_n,
11986                       pipe_config->dp_m_n.link_m, pipe_config->dp_m_n.link_n,
11987                       pipe_config->dp_m_n.tu);
11988
11989         DRM_DEBUG_KMS("dp: %i, gmch_m2: %u, gmch_n2: %u, link_m2: %u, link_n2: %u, tu2: %u\n",
11990                       pipe_config->has_dp_encoder,
11991                       pipe_config->dp_m2_n2.gmch_m,
11992                       pipe_config->dp_m2_n2.gmch_n,
11993                       pipe_config->dp_m2_n2.link_m,
11994                       pipe_config->dp_m2_n2.link_n,
11995                       pipe_config->dp_m2_n2.tu);
11996
11997         DRM_DEBUG_KMS("audio: %i, infoframes: %i\n",
11998                       pipe_config->has_audio,
11999                       pipe_config->has_infoframe);
12000
12001         DRM_DEBUG_KMS("requested mode:\n");
12002         drm_mode_debug_printmodeline(&pipe_config->base.mode);
12003         DRM_DEBUG_KMS("adjusted mode:\n");
12004         drm_mode_debug_printmodeline(&pipe_config->base.adjusted_mode);
12005         intel_dump_crtc_timings(&pipe_config->base.adjusted_mode);
12006         DRM_DEBUG_KMS("port clock: %d\n", pipe_config->port_clock);
12007         DRM_DEBUG_KMS("pipe src size: %dx%d\n",
12008                       pipe_config->pipe_src_w, pipe_config->pipe_src_h);
12009         DRM_DEBUG_KMS("num_scalers: %d, scaler_users: 0x%x, scaler_id: %d\n",
12010                       crtc->num_scalers,
12011                       pipe_config->scaler_state.scaler_users,
12012                       pipe_config->scaler_state.scaler_id);
12013         DRM_DEBUG_KMS("gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n",
12014                       pipe_config->gmch_pfit.control,
12015                       pipe_config->gmch_pfit.pgm_ratios,
12016                       pipe_config->gmch_pfit.lvds_border_bits);
12017         DRM_DEBUG_KMS("pch pfit: pos: 0x%08x, size: 0x%08x, %s\n",
12018                       pipe_config->pch_pfit.pos,
12019                       pipe_config->pch_pfit.size,
12020                       pipe_config->pch_pfit.enabled ? "enabled" : "disabled");
12021         DRM_DEBUG_KMS("ips: %i\n", pipe_config->ips_enabled);
12022         DRM_DEBUG_KMS("double wide: %i\n", pipe_config->double_wide);
12023
12024         if (IS_BROXTON(dev)) {
12025                 DRM_DEBUG_KMS("ddi_pll_sel: %u; dpll_hw_state: ebb0: 0x%x, "
12026                               "pll0: 0x%x, pll1: 0x%x, pll2: 0x%x, pll3: 0x%x, "
12027                               "pll6: 0x%x, pll8: 0x%x, pcsdw12: 0x%x\n",
12028                               pipe_config->ddi_pll_sel,
12029                               pipe_config->dpll_hw_state.ebb0,
12030                               pipe_config->dpll_hw_state.pll0,
12031                               pipe_config->dpll_hw_state.pll1,
12032                               pipe_config->dpll_hw_state.pll2,
12033                               pipe_config->dpll_hw_state.pll3,
12034                               pipe_config->dpll_hw_state.pll6,
12035                               pipe_config->dpll_hw_state.pll8,
12036                               pipe_config->dpll_hw_state.pcsdw12);
12037         } else if (IS_SKYLAKE(dev)) {
12038                 DRM_DEBUG_KMS("ddi_pll_sel: %u; dpll_hw_state: "
12039                               "ctrl1: 0x%x, cfgcr1: 0x%x, cfgcr2: 0x%x\n",
12040                               pipe_config->ddi_pll_sel,
12041                               pipe_config->dpll_hw_state.ctrl1,
12042                               pipe_config->dpll_hw_state.cfgcr1,
12043                               pipe_config->dpll_hw_state.cfgcr2);
12044         } else if (HAS_DDI(dev)) {
12045                 DRM_DEBUG_KMS("ddi_pll_sel: %u; dpll_hw_state: wrpll: 0x%x\n",
12046                               pipe_config->ddi_pll_sel,
12047                               pipe_config->dpll_hw_state.wrpll);
12048         } else {
12049                 DRM_DEBUG_KMS("dpll_hw_state: dpll: 0x%x, dpll_md: 0x%x, "
12050                               "fp0: 0x%x, fp1: 0x%x\n",
12051                               pipe_config->dpll_hw_state.dpll,
12052                               pipe_config->dpll_hw_state.dpll_md,
12053                               pipe_config->dpll_hw_state.fp0,
12054                               pipe_config->dpll_hw_state.fp1);
12055         }
12056
12057         DRM_DEBUG_KMS("planes on this crtc\n");
12058         list_for_each_entry(plane, &dev->mode_config.plane_list, head) {
12059                 intel_plane = to_intel_plane(plane);
12060                 if (intel_plane->pipe != crtc->pipe)
12061                         continue;
12062
12063                 state = to_intel_plane_state(plane->state);
12064                 fb = state->base.fb;
12065                 if (!fb) {
12066                         DRM_DEBUG_KMS("%s PLANE:%d plane: %u.%u idx: %d "
12067                                 "disabled, scaler_id = %d\n",
12068                                 plane->type == DRM_PLANE_TYPE_CURSOR ? "CURSOR" : "STANDARD",
12069                                 plane->base.id, intel_plane->pipe,
12070                                 (crtc->base.primary == plane) ? 0 : intel_plane->plane + 1,
12071                                 drm_plane_index(plane), state->scaler_id);
12072                         continue;
12073                 }
12074
12075                 DRM_DEBUG_KMS("%s PLANE:%d plane: %u.%u idx: %d enabled",
12076                         plane->type == DRM_PLANE_TYPE_CURSOR ? "CURSOR" : "STANDARD",
12077                         plane->base.id, intel_plane->pipe,
12078                         crtc->base.primary == plane ? 0 : intel_plane->plane + 1,
12079                         drm_plane_index(plane));
12080                 DRM_DEBUG_KMS("\tFB:%d, fb = %ux%u format = 0x%x",
12081                         fb->base.id, fb->width, fb->height, fb->pixel_format);
12082                 DRM_DEBUG_KMS("\tscaler:%d src (%u, %u) %ux%u dst (%u, %u) %ux%u\n",
12083                         state->scaler_id,
12084                         state->src.x1 >> 16, state->src.y1 >> 16,
12085                         drm_rect_width(&state->src) >> 16,
12086                         drm_rect_height(&state->src) >> 16,
12087                         state->dst.x1, state->dst.y1,
12088                         drm_rect_width(&state->dst), drm_rect_height(&state->dst));
12089         }
12090 }
12091
12092 static bool check_digital_port_conflicts(struct drm_atomic_state *state)
12093 {
12094         struct drm_device *dev = state->dev;
12095         struct intel_encoder *encoder;
12096         struct drm_connector *connector;
12097         struct drm_connector_state *connector_state;
12098         unsigned int used_ports = 0;
12099         int i;
12100
12101         /*
12102          * Walk the connector list instead of the encoder
12103          * list to detect the problem on ddi platforms
12104          * where there's just one encoder per digital port.
12105          */
12106         for_each_connector_in_state(state, connector, connector_state, i) {
12107                 if (!connector_state->best_encoder)
12108                         continue;
12109
12110                 encoder = to_intel_encoder(connector_state->best_encoder);
12111
12112                 WARN_ON(!connector_state->crtc);
12113
12114                 switch (encoder->type) {
12115                         unsigned int port_mask;
12116                 case INTEL_OUTPUT_UNKNOWN:
12117                         if (WARN_ON(!HAS_DDI(dev)))
12118                                 break;
12119                 case INTEL_OUTPUT_DISPLAYPORT:
12120                 case INTEL_OUTPUT_HDMI:
12121                 case INTEL_OUTPUT_EDP:
12122                         port_mask = 1 << enc_to_dig_port(&encoder->base)->port;
12123
12124                         /* the same port mustn't appear more than once */
12125                         if (used_ports & port_mask)
12126                                 return false;
12127
12128                         used_ports |= port_mask;
12129                 default:
12130                         break;
12131                 }
12132         }
12133
12134         return true;
12135 }
12136
12137 static void
12138 clear_intel_crtc_state(struct intel_crtc_state *crtc_state)
12139 {
12140         struct drm_crtc_state tmp_state;
12141         struct intel_crtc_scaler_state scaler_state;
12142         struct intel_dpll_hw_state dpll_hw_state;
12143         enum intel_dpll_id shared_dpll;
12144         uint32_t ddi_pll_sel;
12145
12146         /* FIXME: before the switch to atomic started, a new pipe_config was
12147          * kzalloc'd. Code that depends on any field being zero should be
12148          * fixed, so that the crtc_state can be safely duplicated. For now,
12149          * only fields that are know to not cause problems are preserved. */
12150
12151         tmp_state = crtc_state->base;
12152         scaler_state = crtc_state->scaler_state;
12153         shared_dpll = crtc_state->shared_dpll;
12154         dpll_hw_state = crtc_state->dpll_hw_state;
12155         ddi_pll_sel = crtc_state->ddi_pll_sel;
12156
12157         memset(crtc_state, 0, sizeof *crtc_state);
12158
12159         crtc_state->base = tmp_state;
12160         crtc_state->scaler_state = scaler_state;
12161         crtc_state->shared_dpll = shared_dpll;
12162         crtc_state->dpll_hw_state = dpll_hw_state;
12163         crtc_state->ddi_pll_sel = ddi_pll_sel;
12164 }
12165
12166 static int
12167 intel_modeset_pipe_config(struct drm_crtc *crtc,
12168                           struct intel_crtc_state *pipe_config)
12169 {
12170         struct drm_atomic_state *state = pipe_config->base.state;
12171         struct intel_encoder *encoder;
12172         struct drm_connector *connector;
12173         struct drm_connector_state *connector_state;
12174         int base_bpp, ret = -EINVAL;
12175         int i;
12176         bool retry = true;
12177
12178         clear_intel_crtc_state(pipe_config);
12179
12180         pipe_config->cpu_transcoder =
12181                 (enum transcoder) to_intel_crtc(crtc)->pipe;
12182
12183         /*
12184          * Sanitize sync polarity flags based on requested ones. If neither
12185          * positive or negative polarity is requested, treat this as meaning
12186          * negative polarity.
12187          */
12188         if (!(pipe_config->base.adjusted_mode.flags &
12189               (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NHSYNC)))
12190                 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NHSYNC;
12191
12192         if (!(pipe_config->base.adjusted_mode.flags &
12193               (DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC)))
12194                 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NVSYNC;
12195
12196         /* Compute a starting value for pipe_config->pipe_bpp taking the source
12197          * plane pixel format and any sink constraints into account. Returns the
12198          * source plane bpp so that dithering can be selected on mismatches
12199          * after encoders and crtc also have had their say. */
12200         base_bpp = compute_baseline_pipe_bpp(to_intel_crtc(crtc),
12201                                              pipe_config);
12202         if (base_bpp < 0)
12203                 goto fail;
12204
12205         /*
12206          * Determine the real pipe dimensions. Note that stereo modes can
12207          * increase the actual pipe size due to the frame doubling and
12208          * insertion of additional space for blanks between the frame. This
12209          * is stored in the crtc timings. We use the requested mode to do this
12210          * computation to clearly distinguish it from the adjusted mode, which
12211          * can be changed by the connectors in the below retry loop.
12212          */
12213         drm_crtc_get_hv_timing(&pipe_config->base.mode,
12214                                &pipe_config->pipe_src_w,
12215                                &pipe_config->pipe_src_h);
12216
12217 encoder_retry:
12218         /* Ensure the port clock defaults are reset when retrying. */
12219         pipe_config->port_clock = 0;
12220         pipe_config->pixel_multiplier = 1;
12221
12222         /* Fill in default crtc timings, allow encoders to overwrite them. */
12223         drm_mode_set_crtcinfo(&pipe_config->base.adjusted_mode,
12224                               CRTC_STEREO_DOUBLE);
12225
12226         /* Pass our mode to the connectors and the CRTC to give them a chance to
12227          * adjust it according to limitations or connector properties, and also
12228          * a chance to reject the mode entirely.
12229          */
12230         for_each_connector_in_state(state, connector, connector_state, i) {
12231                 if (connector_state->crtc != crtc)
12232                         continue;
12233
12234                 encoder = to_intel_encoder(connector_state->best_encoder);
12235
12236                 if (!(encoder->compute_config(encoder, pipe_config))) {
12237                         DRM_DEBUG_KMS("Encoder config failure\n");
12238                         goto fail;
12239                 }
12240         }
12241
12242         /* Set default port clock if not overwritten by the encoder. Needs to be
12243          * done afterwards in case the encoder adjusts the mode. */
12244         if (!pipe_config->port_clock)
12245                 pipe_config->port_clock = pipe_config->base.adjusted_mode.crtc_clock
12246                         * pipe_config->pixel_multiplier;
12247
12248         ret = intel_crtc_compute_config(to_intel_crtc(crtc), pipe_config);
12249         if (ret < 0) {
12250                 DRM_DEBUG_KMS("CRTC fixup failed\n");
12251                 goto fail;
12252         }
12253
12254         if (ret == RETRY) {
12255                 if (WARN(!retry, "loop in pipe configuration computation\n")) {
12256                         ret = -EINVAL;
12257                         goto fail;
12258                 }
12259
12260                 DRM_DEBUG_KMS("CRTC bw constrained, retrying\n");
12261                 retry = false;
12262                 goto encoder_retry;
12263         }
12264
12265         pipe_config->dither = pipe_config->pipe_bpp != base_bpp;
12266         DRM_DEBUG_KMS("plane bpp: %i, pipe bpp: %i, dithering: %i\n",
12267                       base_bpp, pipe_config->pipe_bpp, pipe_config->dither);
12268
12269         /* Check if we need to force a modeset */
12270         if (pipe_config->has_audio !=
12271             to_intel_crtc_state(crtc->state)->has_audio) {
12272                 pipe_config->base.mode_changed = true;
12273                 ret = drm_atomic_add_affected_planes(state, crtc);
12274         }
12275
12276         /*
12277          * Note we have an issue here with infoframes: current code
12278          * only updates them on the full mode set path per hw
12279          * requirements.  So here we should be checking for any
12280          * required changes and forcing a mode set.
12281          */
12282 fail:
12283         return ret;
12284 }
12285
12286 static bool intel_crtc_in_use(struct drm_crtc *crtc)
12287 {
12288         struct drm_encoder *encoder;
12289         struct drm_device *dev = crtc->dev;
12290
12291         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head)
12292                 if (encoder->crtc == crtc)
12293                         return true;
12294
12295         return false;
12296 }
12297
12298 static void
12299 intel_modeset_update_state(struct drm_atomic_state *state)
12300 {
12301         struct drm_device *dev = state->dev;
12302         struct intel_encoder *intel_encoder;
12303         struct drm_crtc *crtc;
12304         struct drm_crtc_state *crtc_state;
12305         struct drm_connector *connector;
12306
12307         intel_shared_dpll_commit(state);
12308
12309         for_each_intel_encoder(dev, intel_encoder) {
12310                 if (!intel_encoder->base.crtc)
12311                         continue;
12312
12313                 crtc = intel_encoder->base.crtc;
12314                 crtc_state = drm_atomic_get_existing_crtc_state(state, crtc);
12315                 if (!crtc_state || !needs_modeset(crtc->state))
12316                         continue;
12317
12318                 intel_encoder->connectors_active = false;
12319         }
12320
12321         drm_atomic_helper_update_legacy_modeset_state(state->dev, state);
12322         intel_modeset_update_staged_output_state(state->dev);
12323
12324         /* Double check state. */
12325         for_each_crtc(dev, crtc) {
12326                 WARN_ON(crtc->state->enable != intel_crtc_in_use(crtc));
12327
12328                 to_intel_crtc(crtc)->config = to_intel_crtc_state(crtc->state);
12329
12330                 /* Update hwmode for vblank functions */
12331                 if (crtc->state->active)
12332                         crtc->hwmode = crtc->state->adjusted_mode;
12333                 else
12334                         crtc->hwmode.crtc_clock = 0;
12335         }
12336
12337         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
12338                 if (!connector->encoder || !connector->encoder->crtc)
12339                         continue;
12340
12341                 crtc = connector->encoder->crtc;
12342                 crtc_state = drm_atomic_get_existing_crtc_state(state, crtc);
12343                 if (!crtc_state || !needs_modeset(crtc->state))
12344                         continue;
12345
12346                 if (crtc->state->active) {
12347                         struct drm_property *dpms_property =
12348                                 dev->mode_config.dpms_property;
12349
12350                         connector->dpms = DRM_MODE_DPMS_ON;
12351                         drm_object_property_set_value(&connector->base, dpms_property, DRM_MODE_DPMS_ON);
12352
12353                         intel_encoder = to_intel_encoder(connector->encoder);
12354                         intel_encoder->connectors_active = true;
12355                 } else
12356                         connector->dpms = DRM_MODE_DPMS_OFF;
12357         }
12358 }
12359
12360 static bool intel_fuzzy_clock_check(int clock1, int clock2)
12361 {
12362         int diff;
12363
12364         if (clock1 == clock2)
12365                 return true;
12366
12367         if (!clock1 || !clock2)
12368                 return false;
12369
12370         diff = abs(clock1 - clock2);
12371
12372         if (((((diff + clock1 + clock2) * 100)) / (clock1 + clock2)) < 105)
12373                 return true;
12374
12375         return false;
12376 }
12377
12378 #define for_each_intel_crtc_masked(dev, mask, intel_crtc) \
12379         list_for_each_entry((intel_crtc), \
12380                             &(dev)->mode_config.crtc_list, \
12381                             base.head) \
12382                 if (mask & (1 <<(intel_crtc)->pipe))
12383
12384 static bool
12385 intel_pipe_config_compare(struct drm_device *dev,
12386                           struct intel_crtc_state *current_config,
12387                           struct intel_crtc_state *pipe_config)
12388 {
12389 #define PIPE_CONF_CHECK_X(name) \
12390         if (current_config->name != pipe_config->name) { \
12391                 DRM_ERROR("mismatch in " #name " " \
12392                           "(expected 0x%08x, found 0x%08x)\n", \
12393                           current_config->name, \
12394                           pipe_config->name); \
12395                 return false; \
12396         }
12397
12398 #define PIPE_CONF_CHECK_I(name) \
12399         if (current_config->name != pipe_config->name) { \
12400                 DRM_ERROR("mismatch in " #name " " \
12401                           "(expected %i, found %i)\n", \
12402                           current_config->name, \
12403                           pipe_config->name); \
12404                 return false; \
12405         }
12406
12407 /* This is required for BDW+ where there is only one set of registers for
12408  * switching between high and low RR.
12409  * This macro can be used whenever a comparison has to be made between one
12410  * hw state and multiple sw state variables.
12411  */
12412 #define PIPE_CONF_CHECK_I_ALT(name, alt_name) \
12413         if ((current_config->name != pipe_config->name) && \
12414                 (current_config->alt_name != pipe_config->name)) { \
12415                         DRM_ERROR("mismatch in " #name " " \
12416                                   "(expected %i or %i, found %i)\n", \
12417                                   current_config->name, \
12418                                   current_config->alt_name, \
12419                                   pipe_config->name); \
12420                         return false; \
12421         }
12422
12423 #define PIPE_CONF_CHECK_FLAGS(name, mask)       \
12424         if ((current_config->name ^ pipe_config->name) & (mask)) { \
12425                 DRM_ERROR("mismatch in " #name "(" #mask ") "      \
12426                           "(expected %i, found %i)\n", \
12427                           current_config->name & (mask), \
12428                           pipe_config->name & (mask)); \
12429                 return false; \
12430         }
12431
12432 #define PIPE_CONF_CHECK_CLOCK_FUZZY(name) \
12433         if (!intel_fuzzy_clock_check(current_config->name, pipe_config->name)) { \
12434                 DRM_ERROR("mismatch in " #name " " \
12435                           "(expected %i, found %i)\n", \
12436                           current_config->name, \
12437                           pipe_config->name); \
12438                 return false; \
12439         }
12440
12441 #define PIPE_CONF_QUIRK(quirk)  \
12442         ((current_config->quirks | pipe_config->quirks) & (quirk))
12443
12444         PIPE_CONF_CHECK_I(cpu_transcoder);
12445
12446         PIPE_CONF_CHECK_I(has_pch_encoder);
12447         PIPE_CONF_CHECK_I(fdi_lanes);
12448         PIPE_CONF_CHECK_I(fdi_m_n.gmch_m);
12449         PIPE_CONF_CHECK_I(fdi_m_n.gmch_n);
12450         PIPE_CONF_CHECK_I(fdi_m_n.link_m);
12451         PIPE_CONF_CHECK_I(fdi_m_n.link_n);
12452         PIPE_CONF_CHECK_I(fdi_m_n.tu);
12453
12454         PIPE_CONF_CHECK_I(has_dp_encoder);
12455
12456         if (INTEL_INFO(dev)->gen < 8) {
12457                 PIPE_CONF_CHECK_I(dp_m_n.gmch_m);
12458                 PIPE_CONF_CHECK_I(dp_m_n.gmch_n);
12459                 PIPE_CONF_CHECK_I(dp_m_n.link_m);
12460                 PIPE_CONF_CHECK_I(dp_m_n.link_n);
12461                 PIPE_CONF_CHECK_I(dp_m_n.tu);
12462
12463                 if (current_config->has_drrs) {
12464                         PIPE_CONF_CHECK_I(dp_m2_n2.gmch_m);
12465                         PIPE_CONF_CHECK_I(dp_m2_n2.gmch_n);
12466                         PIPE_CONF_CHECK_I(dp_m2_n2.link_m);
12467                         PIPE_CONF_CHECK_I(dp_m2_n2.link_n);
12468                         PIPE_CONF_CHECK_I(dp_m2_n2.tu);
12469                 }
12470         } else {
12471                 PIPE_CONF_CHECK_I_ALT(dp_m_n.gmch_m, dp_m2_n2.gmch_m);
12472                 PIPE_CONF_CHECK_I_ALT(dp_m_n.gmch_n, dp_m2_n2.gmch_n);
12473                 PIPE_CONF_CHECK_I_ALT(dp_m_n.link_m, dp_m2_n2.link_m);
12474                 PIPE_CONF_CHECK_I_ALT(dp_m_n.link_n, dp_m2_n2.link_n);
12475                 PIPE_CONF_CHECK_I_ALT(dp_m_n.tu, dp_m2_n2.tu);
12476         }
12477
12478         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hdisplay);
12479         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_htotal);
12480         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_start);
12481         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_end);
12482         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_start);
12483         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_end);
12484
12485         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vdisplay);
12486         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vtotal);
12487         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_start);
12488         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_end);
12489         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_start);
12490         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_end);
12491
12492         PIPE_CONF_CHECK_I(pixel_multiplier);
12493         PIPE_CONF_CHECK_I(has_hdmi_sink);
12494         if ((INTEL_INFO(dev)->gen < 8 && !IS_HASWELL(dev)) ||
12495             IS_VALLEYVIEW(dev))
12496                 PIPE_CONF_CHECK_I(limited_color_range);
12497         PIPE_CONF_CHECK_I(has_infoframe);
12498
12499         PIPE_CONF_CHECK_I(has_audio);
12500
12501         PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
12502                               DRM_MODE_FLAG_INTERLACE);
12503
12504         if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) {
12505                 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
12506                                       DRM_MODE_FLAG_PHSYNC);
12507                 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
12508                                       DRM_MODE_FLAG_NHSYNC);
12509                 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
12510                                       DRM_MODE_FLAG_PVSYNC);
12511                 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
12512                                       DRM_MODE_FLAG_NVSYNC);
12513         }
12514
12515         PIPE_CONF_CHECK_I(pipe_src_w);
12516         PIPE_CONF_CHECK_I(pipe_src_h);
12517
12518         /*
12519          * FIXME: BIOS likes to set up a cloned config with lvds+external
12520          * screen. Since we don't yet re-compute the pipe config when moving
12521          * just the lvds port away to another pipe the sw tracking won't match.
12522          *
12523          * Proper atomic modesets with recomputed global state will fix this.
12524          * Until then just don't check gmch state for inherited modes.
12525          */
12526         if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_INHERITED_MODE)) {
12527                 PIPE_CONF_CHECK_I(gmch_pfit.control);
12528                 /* pfit ratios are autocomputed by the hw on gen4+ */
12529                 if (INTEL_INFO(dev)->gen < 4)
12530                         PIPE_CONF_CHECK_I(gmch_pfit.pgm_ratios);
12531                 PIPE_CONF_CHECK_I(gmch_pfit.lvds_border_bits);
12532         }
12533
12534         PIPE_CONF_CHECK_I(pch_pfit.enabled);
12535         if (current_config->pch_pfit.enabled) {
12536                 PIPE_CONF_CHECK_I(pch_pfit.pos);
12537                 PIPE_CONF_CHECK_I(pch_pfit.size);
12538         }
12539
12540         PIPE_CONF_CHECK_I(scaler_state.scaler_id);
12541
12542         /* BDW+ don't expose a synchronous way to read the state */
12543         if (IS_HASWELL(dev))
12544                 PIPE_CONF_CHECK_I(ips_enabled);
12545
12546         PIPE_CONF_CHECK_I(double_wide);
12547
12548         PIPE_CONF_CHECK_X(ddi_pll_sel);
12549
12550         PIPE_CONF_CHECK_I(shared_dpll);
12551         PIPE_CONF_CHECK_X(dpll_hw_state.dpll);
12552         PIPE_CONF_CHECK_X(dpll_hw_state.dpll_md);
12553         PIPE_CONF_CHECK_X(dpll_hw_state.fp0);
12554         PIPE_CONF_CHECK_X(dpll_hw_state.fp1);
12555         PIPE_CONF_CHECK_X(dpll_hw_state.wrpll);
12556         PIPE_CONF_CHECK_X(dpll_hw_state.ctrl1);
12557         PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr1);
12558         PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr2);
12559
12560         if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5)
12561                 PIPE_CONF_CHECK_I(pipe_bpp);
12562
12563         PIPE_CONF_CHECK_CLOCK_FUZZY(base.adjusted_mode.crtc_clock);
12564         PIPE_CONF_CHECK_CLOCK_FUZZY(port_clock);
12565
12566 #undef PIPE_CONF_CHECK_X
12567 #undef PIPE_CONF_CHECK_I
12568 #undef PIPE_CONF_CHECK_I_ALT
12569 #undef PIPE_CONF_CHECK_FLAGS
12570 #undef PIPE_CONF_CHECK_CLOCK_FUZZY
12571 #undef PIPE_CONF_QUIRK
12572
12573         return true;
12574 }
12575
12576 static void check_wm_state(struct drm_device *dev)
12577 {
12578         struct drm_i915_private *dev_priv = dev->dev_private;
12579         struct skl_ddb_allocation hw_ddb, *sw_ddb;
12580         struct intel_crtc *intel_crtc;
12581         int plane;
12582
12583         if (INTEL_INFO(dev)->gen < 9)
12584                 return;
12585
12586         skl_ddb_get_hw_state(dev_priv, &hw_ddb);
12587         sw_ddb = &dev_priv->wm.skl_hw.ddb;
12588
12589         for_each_intel_crtc(dev, intel_crtc) {
12590                 struct skl_ddb_entry *hw_entry, *sw_entry;
12591                 const enum pipe pipe = intel_crtc->pipe;
12592
12593                 if (!intel_crtc->active)
12594                         continue;
12595
12596                 /* planes */
12597                 for_each_plane(dev_priv, pipe, plane) {
12598                         hw_entry = &hw_ddb.plane[pipe][plane];
12599                         sw_entry = &sw_ddb->plane[pipe][plane];
12600
12601                         if (skl_ddb_entry_equal(hw_entry, sw_entry))
12602                                 continue;
12603
12604                         DRM_ERROR("mismatch in DDB state pipe %c plane %d "
12605                                   "(expected (%u,%u), found (%u,%u))\n",
12606                                   pipe_name(pipe), plane + 1,
12607                                   sw_entry->start, sw_entry->end,
12608                                   hw_entry->start, hw_entry->end);
12609                 }
12610
12611                 /* cursor */
12612                 hw_entry = &hw_ddb.cursor[pipe];
12613                 sw_entry = &sw_ddb->cursor[pipe];
12614
12615                 if (skl_ddb_entry_equal(hw_entry, sw_entry))
12616                         continue;
12617
12618                 DRM_ERROR("mismatch in DDB state pipe %c cursor "
12619                           "(expected (%u,%u), found (%u,%u))\n",
12620                           pipe_name(pipe),
12621                           sw_entry->start, sw_entry->end,
12622                           hw_entry->start, hw_entry->end);
12623         }
12624 }
12625
12626 static void
12627 check_connector_state(struct drm_device *dev)
12628 {
12629         struct intel_connector *connector;
12630
12631         for_each_intel_connector(dev, connector) {
12632                 /* This also checks the encoder/connector hw state with the
12633                  * ->get_hw_state callbacks. */
12634                 intel_connector_check_state(connector);
12635
12636                 I915_STATE_WARN(&connector->new_encoder->base != connector->base.encoder,
12637                      "connector's staged encoder doesn't match current encoder\n");
12638         }
12639 }
12640
12641 static void
12642 check_encoder_state(struct drm_device *dev)
12643 {
12644         struct intel_encoder *encoder;
12645         struct intel_connector *connector;
12646
12647         for_each_intel_encoder(dev, encoder) {
12648                 bool enabled = false;
12649                 bool active = false;
12650                 enum pipe pipe, tracked_pipe;
12651
12652                 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
12653                               encoder->base.base.id,
12654                               encoder->base.name);
12655
12656                 I915_STATE_WARN(&encoder->new_crtc->base != encoder->base.crtc,
12657                      "encoder's stage crtc doesn't match current crtc\n");
12658                 I915_STATE_WARN(encoder->connectors_active && !encoder->base.crtc,
12659                      "encoder's active_connectors set, but no crtc\n");
12660
12661                 for_each_intel_connector(dev, connector) {
12662                         if (connector->base.encoder != &encoder->base)
12663                                 continue;
12664                         enabled = true;
12665                         if (connector->base.dpms != DRM_MODE_DPMS_OFF)
12666                                 active = true;
12667                 }
12668                 /*
12669                  * for MST connectors if we unplug the connector is gone
12670                  * away but the encoder is still connected to a crtc
12671                  * until a modeset happens in response to the hotplug.
12672                  */
12673                 if (!enabled && encoder->base.encoder_type == DRM_MODE_ENCODER_DPMST)
12674                         continue;
12675
12676                 I915_STATE_WARN(!!encoder->base.crtc != enabled,
12677                      "encoder's enabled state mismatch "
12678                      "(expected %i, found %i)\n",
12679                      !!encoder->base.crtc, enabled);
12680                 I915_STATE_WARN(active && !encoder->base.crtc,
12681                      "active encoder with no crtc\n");
12682
12683                 I915_STATE_WARN(encoder->connectors_active != active,
12684                      "encoder's computed active state doesn't match tracked active state "
12685                      "(expected %i, found %i)\n", active, encoder->connectors_active);
12686
12687                 active = encoder->get_hw_state(encoder, &pipe);
12688                 I915_STATE_WARN(active != encoder->connectors_active,
12689                      "encoder's hw state doesn't match sw tracking "
12690                      "(expected %i, found %i)\n",
12691                      encoder->connectors_active, active);
12692
12693                 if (!encoder->base.crtc)
12694                         continue;
12695
12696                 tracked_pipe = to_intel_crtc(encoder->base.crtc)->pipe;
12697                 I915_STATE_WARN(active && pipe != tracked_pipe,
12698                      "active encoder's pipe doesn't match"
12699                      "(expected %i, found %i)\n",
12700                      tracked_pipe, pipe);
12701
12702         }
12703 }
12704
12705 static void
12706 check_crtc_state(struct drm_device *dev)
12707 {
12708         struct drm_i915_private *dev_priv = dev->dev_private;
12709         struct intel_crtc *crtc;
12710         struct intel_encoder *encoder;
12711         struct intel_crtc_state pipe_config;
12712
12713         for_each_intel_crtc(dev, crtc) {
12714                 bool enabled = false;
12715                 bool active = false;
12716
12717                 memset(&pipe_config, 0, sizeof(pipe_config));
12718
12719                 DRM_DEBUG_KMS("[CRTC:%d]\n",
12720                               crtc->base.base.id);
12721
12722                 I915_STATE_WARN(crtc->active && !crtc->base.state->enable,
12723                      "active crtc, but not enabled in sw tracking\n");
12724
12725                 for_each_intel_encoder(dev, encoder) {
12726                         if (encoder->base.crtc != &crtc->base)
12727                                 continue;
12728                         enabled = true;
12729                         if (encoder->connectors_active)
12730                                 active = true;
12731                 }
12732
12733                 I915_STATE_WARN(active != crtc->active,
12734                      "crtc's computed active state doesn't match tracked active state "
12735                      "(expected %i, found %i)\n", active, crtc->active);
12736                 I915_STATE_WARN(enabled != crtc->base.state->enable,
12737                      "crtc's computed enabled state doesn't match tracked enabled state "
12738                      "(expected %i, found %i)\n", enabled,
12739                                 crtc->base.state->enable);
12740
12741                 active = dev_priv->display.get_pipe_config(crtc,
12742                                                            &pipe_config);
12743
12744                 /* hw state is inconsistent with the pipe quirk */
12745                 if ((crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
12746                     (crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
12747                         active = crtc->active;
12748
12749                 for_each_intel_encoder(dev, encoder) {
12750                         enum pipe pipe;
12751                         if (encoder->base.crtc != &crtc->base)
12752                                 continue;
12753                         if (encoder->get_hw_state(encoder, &pipe))
12754                                 encoder->get_config(encoder, &pipe_config);
12755                 }
12756
12757                 I915_STATE_WARN(crtc->active != active,
12758                      "crtc active state doesn't match with hw state "
12759                      "(expected %i, found %i)\n", crtc->active, active);
12760
12761                 I915_STATE_WARN(crtc->active != crtc->base.state->active,
12762                      "transitional active state does not match atomic hw state "
12763                      "(expected %i, found %i)\n", crtc->base.state->active, crtc->active);
12764
12765                 if (active &&
12766                     !intel_pipe_config_compare(dev, crtc->config, &pipe_config)) {
12767                         I915_STATE_WARN(1, "pipe state doesn't match!\n");
12768                         intel_dump_pipe_config(crtc, &pipe_config,
12769                                                "[hw state]");
12770                         intel_dump_pipe_config(crtc, crtc->config,
12771                                                "[sw state]");
12772                 }
12773         }
12774 }
12775
12776 static void
12777 check_shared_dpll_state(struct drm_device *dev)
12778 {
12779         struct drm_i915_private *dev_priv = dev->dev_private;
12780         struct intel_crtc *crtc;
12781         struct intel_dpll_hw_state dpll_hw_state;
12782         int i;
12783
12784         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
12785                 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
12786                 int enabled_crtcs = 0, active_crtcs = 0;
12787                 bool active;
12788
12789                 memset(&dpll_hw_state, 0, sizeof(dpll_hw_state));
12790
12791                 DRM_DEBUG_KMS("%s\n", pll->name);
12792
12793                 active = pll->get_hw_state(dev_priv, pll, &dpll_hw_state);
12794
12795                 I915_STATE_WARN(pll->active > hweight32(pll->config.crtc_mask),
12796                      "more active pll users than references: %i vs %i\n",
12797                      pll->active, hweight32(pll->config.crtc_mask));
12798                 I915_STATE_WARN(pll->active && !pll->on,
12799                      "pll in active use but not on in sw tracking\n");
12800                 I915_STATE_WARN(pll->on && !pll->active,
12801                      "pll in on but not on in use in sw tracking\n");
12802                 I915_STATE_WARN(pll->on != active,
12803                      "pll on state mismatch (expected %i, found %i)\n",
12804                      pll->on, active);
12805
12806                 for_each_intel_crtc(dev, crtc) {
12807                         if (crtc->base.state->enable && intel_crtc_to_shared_dpll(crtc) == pll)
12808                                 enabled_crtcs++;
12809                         if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll)
12810                                 active_crtcs++;
12811                 }
12812                 I915_STATE_WARN(pll->active != active_crtcs,
12813                      "pll active crtcs mismatch (expected %i, found %i)\n",
12814                      pll->active, active_crtcs);
12815                 I915_STATE_WARN(hweight32(pll->config.crtc_mask) != enabled_crtcs,
12816                      "pll enabled crtcs mismatch (expected %i, found %i)\n",
12817                      hweight32(pll->config.crtc_mask), enabled_crtcs);
12818
12819                 I915_STATE_WARN(pll->on && memcmp(&pll->config.hw_state, &dpll_hw_state,
12820                                        sizeof(dpll_hw_state)),
12821                      "pll hw state mismatch\n");
12822         }
12823 }
12824
12825 void
12826 intel_modeset_check_state(struct drm_device *dev)
12827 {
12828         check_wm_state(dev);
12829         check_connector_state(dev);
12830         check_encoder_state(dev);
12831         check_crtc_state(dev);
12832         check_shared_dpll_state(dev);
12833 }
12834
12835 void ironlake_check_encoder_dotclock(const struct intel_crtc_state *pipe_config,
12836                                      int dotclock)
12837 {
12838         /*
12839          * FDI already provided one idea for the dotclock.
12840          * Yell if the encoder disagrees.
12841          */
12842         WARN(!intel_fuzzy_clock_check(pipe_config->base.adjusted_mode.crtc_clock, dotclock),
12843              "FDI dotclock and encoder dotclock mismatch, fdi: %i, encoder: %i\n",
12844              pipe_config->base.adjusted_mode.crtc_clock, dotclock);
12845 }
12846
12847 static void update_scanline_offset(struct intel_crtc *crtc)
12848 {
12849         struct drm_device *dev = crtc->base.dev;
12850
12851         /*
12852          * The scanline counter increments at the leading edge of hsync.
12853          *
12854          * On most platforms it starts counting from vtotal-1 on the
12855          * first active line. That means the scanline counter value is
12856          * always one less than what we would expect. Ie. just after
12857          * start of vblank, which also occurs at start of hsync (on the
12858          * last active line), the scanline counter will read vblank_start-1.
12859          *
12860          * On gen2 the scanline counter starts counting from 1 instead
12861          * of vtotal-1, so we have to subtract one (or rather add vtotal-1
12862          * to keep the value positive), instead of adding one.
12863          *
12864          * On HSW+ the behaviour of the scanline counter depends on the output
12865          * type. For DP ports it behaves like most other platforms, but on HDMI
12866          * there's an extra 1 line difference. So we need to add two instead of
12867          * one to the value.
12868          */
12869         if (IS_GEN2(dev)) {
12870                 const struct drm_display_mode *mode = &crtc->config->base.adjusted_mode;
12871                 int vtotal;
12872
12873                 vtotal = mode->crtc_vtotal;
12874                 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
12875                         vtotal /= 2;
12876
12877                 crtc->scanline_offset = vtotal - 1;
12878         } else if (HAS_DDI(dev) &&
12879                    intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI)) {
12880                 crtc->scanline_offset = 2;
12881         } else
12882                 crtc->scanline_offset = 1;
12883 }
12884
12885 static void intel_modeset_clear_plls(struct drm_atomic_state *state)
12886 {
12887         struct drm_device *dev = state->dev;
12888         struct drm_i915_private *dev_priv = to_i915(dev);
12889         struct intel_shared_dpll_config *shared_dpll = NULL;
12890         struct intel_crtc *intel_crtc;
12891         struct intel_crtc_state *intel_crtc_state;
12892         struct drm_crtc *crtc;
12893         struct drm_crtc_state *crtc_state;
12894         int i;
12895
12896         if (!dev_priv->display.crtc_compute_clock)
12897                 return;
12898
12899         for_each_crtc_in_state(state, crtc, crtc_state, i) {
12900                 int dpll;
12901
12902                 intel_crtc = to_intel_crtc(crtc);
12903                 intel_crtc_state = to_intel_crtc_state(crtc_state);
12904                 dpll = intel_crtc_state->shared_dpll;
12905
12906                 if (!needs_modeset(crtc_state) || dpll == DPLL_ID_PRIVATE)
12907                         continue;
12908
12909                 intel_crtc_state->shared_dpll = DPLL_ID_PRIVATE;
12910
12911                 if (!shared_dpll)
12912                         shared_dpll = intel_atomic_get_shared_dpll_state(state);
12913
12914                 shared_dpll[dpll].crtc_mask &= ~(1 << intel_crtc->pipe);
12915         }
12916 }
12917
12918 /*
12919  * This implements the workaround described in the "notes" section of the mode
12920  * set sequence documentation. When going from no pipes or single pipe to
12921  * multiple pipes, and planes are enabled after the pipe, we need to wait at
12922  * least 2 vblanks on the first pipe before enabling planes on the second pipe.
12923  */
12924 static int haswell_mode_set_planes_workaround(struct drm_atomic_state *state)
12925 {
12926         struct drm_crtc_state *crtc_state;
12927         struct intel_crtc *intel_crtc;
12928         struct drm_crtc *crtc;
12929         struct intel_crtc_state *first_crtc_state = NULL;
12930         struct intel_crtc_state *other_crtc_state = NULL;
12931         enum pipe first_pipe = INVALID_PIPE, enabled_pipe = INVALID_PIPE;
12932         int i;
12933
12934         /* look at all crtc's that are going to be enabled in during modeset */
12935         for_each_crtc_in_state(state, crtc, crtc_state, i) {
12936                 intel_crtc = to_intel_crtc(crtc);
12937
12938                 if (!crtc_state->active || !needs_modeset(crtc_state))
12939                         continue;
12940
12941                 if (first_crtc_state) {
12942                         other_crtc_state = to_intel_crtc_state(crtc_state);
12943                         break;
12944                 } else {
12945                         first_crtc_state = to_intel_crtc_state(crtc_state);
12946                         first_pipe = intel_crtc->pipe;
12947                 }
12948         }
12949
12950         /* No workaround needed? */
12951         if (!first_crtc_state)
12952                 return 0;
12953
12954         /* w/a possibly needed, check how many crtc's are already enabled. */
12955         for_each_intel_crtc(state->dev, intel_crtc) {
12956                 struct intel_crtc_state *pipe_config;
12957
12958                 pipe_config = intel_atomic_get_crtc_state(state, intel_crtc);
12959                 if (IS_ERR(pipe_config))
12960                         return PTR_ERR(pipe_config);
12961
12962                 pipe_config->hsw_workaround_pipe = INVALID_PIPE;
12963
12964                 if (!pipe_config->base.active ||
12965                     needs_modeset(&pipe_config->base))
12966                         continue;
12967
12968                 /* 2 or more enabled crtcs means no need for w/a */
12969                 if (enabled_pipe != INVALID_PIPE)
12970                         return 0;
12971
12972                 enabled_pipe = intel_crtc->pipe;
12973         }
12974
12975         if (enabled_pipe != INVALID_PIPE)
12976                 first_crtc_state->hsw_workaround_pipe = enabled_pipe;
12977         else if (other_crtc_state)
12978                 other_crtc_state->hsw_workaround_pipe = first_pipe;
12979
12980         return 0;
12981 }
12982
12983 static int intel_modeset_all_pipes(struct drm_atomic_state *state)
12984 {
12985         struct drm_crtc *crtc;
12986         struct drm_crtc_state *crtc_state;
12987         int ret = 0;
12988
12989         /* add all active pipes to the state */
12990         for_each_crtc(state->dev, crtc) {
12991                 crtc_state = drm_atomic_get_crtc_state(state, crtc);
12992                 if (IS_ERR(crtc_state))
12993                         return PTR_ERR(crtc_state);
12994
12995                 if (!crtc_state->active || needs_modeset(crtc_state))
12996                         continue;
12997
12998                 crtc_state->mode_changed = true;
12999
13000                 ret = drm_atomic_add_affected_connectors(state, crtc);
13001                 if (ret)
13002                         break;
13003
13004                 ret = drm_atomic_add_affected_planes(state, crtc);
13005                 if (ret)
13006                         break;
13007         }
13008
13009         return ret;
13010 }
13011
13012
13013 /* Code that should eventually be part of atomic_check() */
13014 static int intel_modeset_checks(struct drm_atomic_state *state)
13015 {
13016         struct drm_device *dev = state->dev;
13017         struct drm_i915_private *dev_priv = dev->dev_private;
13018         int ret;
13019
13020         if (!check_digital_port_conflicts(state)) {
13021                 DRM_DEBUG_KMS("rejecting conflicting digital port configuration\n");
13022                 return -EINVAL;
13023         }
13024
13025         /*
13026          * See if the config requires any additional preparation, e.g.
13027          * to adjust global state with pipes off.  We need to do this
13028          * here so we can get the modeset_pipe updated config for the new
13029          * mode set on this crtc.  For other crtcs we need to use the
13030          * adjusted_mode bits in the crtc directly.
13031          */
13032         if (dev_priv->display.modeset_calc_cdclk) {
13033                 unsigned int cdclk;
13034
13035                 ret = dev_priv->display.modeset_calc_cdclk(state);
13036
13037                 cdclk = to_intel_atomic_state(state)->cdclk;
13038                 if (!ret && cdclk != dev_priv->cdclk_freq)
13039                         ret = intel_modeset_all_pipes(state);
13040
13041                 if (ret < 0)
13042                         return ret;
13043         } else
13044                 to_intel_atomic_state(state)->cdclk = dev_priv->cdclk_freq;
13045
13046         intel_modeset_clear_plls(state);
13047
13048         if (IS_HASWELL(dev))
13049                 return haswell_mode_set_planes_workaround(state);
13050
13051         return 0;
13052 }
13053
13054 static int
13055 intel_modeset_compute_config(struct drm_atomic_state *state)
13056 {
13057         struct drm_crtc *crtc;
13058         struct drm_crtc_state *crtc_state;
13059         int ret, i;
13060         bool any_ms = false;
13061
13062         ret = drm_atomic_helper_check_modeset(state->dev, state);
13063         if (ret)
13064                 return ret;
13065
13066         for_each_crtc_in_state(state, crtc, crtc_state, i) {
13067                 if (!crtc_state->enable) {
13068                         if (needs_modeset(crtc_state))
13069                                 any_ms = true;
13070                         continue;
13071                 }
13072
13073                 if (to_intel_crtc_state(crtc_state)->quirks &
13074                     PIPE_CONFIG_QUIRK_INITIAL_PLANES) {
13075                         ret = drm_atomic_add_affected_planes(state, crtc);
13076                         if (ret)
13077                                 return ret;
13078
13079                         /*
13080                          * We ought to handle i915.fastboot here.
13081                          * If no modeset is required and the primary plane has
13082                          * a fb, update the members of crtc_state as needed,
13083                          * and run the necessary updates during vblank evasion.
13084                          */
13085                 }
13086
13087                 if (!needs_modeset(crtc_state)) {
13088                         ret = drm_atomic_add_affected_connectors(state, crtc);
13089                         if (ret)
13090                                 return ret;
13091                 }
13092
13093                 ret = intel_modeset_pipe_config(crtc,
13094                                         to_intel_crtc_state(crtc_state));
13095                 if (ret)
13096                         return ret;
13097
13098                 if (needs_modeset(crtc_state))
13099                         any_ms = true;
13100
13101                 intel_dump_pipe_config(to_intel_crtc(crtc),
13102                                        to_intel_crtc_state(crtc_state),
13103                                        "[modeset]");
13104         }
13105
13106         if (any_ms) {
13107                 ret = intel_modeset_checks(state);
13108
13109                 if (ret)
13110                         return ret;
13111         } else
13112                 to_intel_atomic_state(state)->cdclk =
13113                         to_i915(state->dev)->cdclk_freq;
13114
13115         return drm_atomic_helper_check_planes(state->dev, state);
13116 }
13117
13118 static int __intel_set_mode(struct drm_atomic_state *state)
13119 {
13120         struct drm_device *dev = state->dev;
13121         struct drm_i915_private *dev_priv = dev->dev_private;
13122         struct drm_crtc *crtc;
13123         struct drm_crtc_state *crtc_state;
13124         int ret = 0;
13125         int i;
13126         bool any_ms = false;
13127
13128         ret = drm_atomic_helper_prepare_planes(dev, state);
13129         if (ret)
13130                 return ret;
13131
13132         drm_atomic_helper_swap_state(dev, state);
13133
13134         for_each_crtc_in_state(state, crtc, crtc_state, i) {
13135                 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
13136
13137                 if (!needs_modeset(crtc->state))
13138                         continue;
13139
13140                 any_ms = true;
13141                 intel_pre_plane_update(intel_crtc);
13142
13143                 if (crtc_state->active) {
13144                         intel_crtc_disable_planes(crtc, crtc_state->plane_mask);
13145                         dev_priv->display.crtc_disable(crtc);
13146                         intel_crtc->active = false;
13147                         intel_disable_shared_dpll(intel_crtc);
13148                 }
13149         }
13150
13151         /* Only after disabling all output pipelines that will be changed can we
13152          * update the the output configuration. */
13153         intel_modeset_update_state(state);
13154
13155         /* The state has been swaped above, so state actually contains the
13156          * old state now. */
13157         if (any_ms)
13158                 modeset_update_crtc_power_domains(state);
13159
13160         /* Now enable the clocks, plane, pipe, and connectors that we set up. */
13161         for_each_crtc_in_state(state, crtc, crtc_state, i) {
13162                 if (needs_modeset(crtc->state) && crtc->state->active) {
13163                         update_scanline_offset(to_intel_crtc(crtc));
13164                         dev_priv->display.crtc_enable(crtc);
13165                 }
13166
13167                 drm_atomic_helper_commit_planes_on_crtc(crtc_state);
13168         }
13169
13170         /* FIXME: add subpixel order */
13171
13172         drm_atomic_helper_cleanup_planes(dev, state);
13173
13174         drm_atomic_state_free(state);
13175
13176         return 0;
13177 }
13178
13179 static int intel_set_mode_checked(struct drm_atomic_state *state)
13180 {
13181         struct drm_device *dev = state->dev;
13182         int ret;
13183
13184         ret = __intel_set_mode(state);
13185         if (ret == 0)
13186                 intel_modeset_check_state(dev);
13187
13188         return ret;
13189 }
13190
13191 static int intel_set_mode(struct drm_atomic_state *state)
13192 {
13193         int ret;
13194
13195         ret = intel_modeset_compute_config(state);
13196         if (ret)
13197                 return ret;
13198
13199         return intel_set_mode_checked(state);
13200 }
13201
13202 void intel_crtc_restore_mode(struct drm_crtc *crtc)
13203 {
13204         struct drm_device *dev = crtc->dev;
13205         struct drm_atomic_state *state;
13206         struct intel_encoder *encoder;
13207         struct intel_connector *connector;
13208         struct drm_connector_state *connector_state;
13209         struct intel_crtc_state *crtc_state;
13210         int ret;
13211
13212         state = drm_atomic_state_alloc(dev);
13213         if (!state) {
13214                 DRM_DEBUG_KMS("[CRTC:%d] mode restore failed, out of memory",
13215                               crtc->base.id);
13216                 return;
13217         }
13218
13219         state->acquire_ctx = dev->mode_config.acquire_ctx;
13220
13221         /* The force restore path in the HW readout code relies on the staged
13222          * config still keeping the user requested config while the actual
13223          * state has been overwritten by the configuration read from HW. We
13224          * need to copy the staged config to the atomic state, otherwise the
13225          * mode set will just reapply the state the HW is already in. */
13226         for_each_intel_encoder(dev, encoder) {
13227                 if (&encoder->new_crtc->base != crtc)
13228                         continue;
13229
13230                 for_each_intel_connector(dev, connector) {
13231                         if (connector->new_encoder != encoder)
13232                                 continue;
13233
13234                         connector_state = drm_atomic_get_connector_state(state, &connector->base);
13235                         if (IS_ERR(connector_state)) {
13236                                 DRM_DEBUG_KMS("Failed to add [CONNECTOR:%d:%s] to state: %ld\n",
13237                                               connector->base.base.id,
13238                                               connector->base.name,
13239                                               PTR_ERR(connector_state));
13240                                 continue;
13241                         }
13242
13243                         connector_state->crtc = crtc;
13244                         connector_state->best_encoder = &encoder->base;
13245                 }
13246         }
13247
13248         crtc_state = intel_atomic_get_crtc_state(state, to_intel_crtc(crtc));
13249         if (IS_ERR(crtc_state)) {
13250                 DRM_DEBUG_KMS("Failed to add [CRTC:%d] to state: %ld\n",
13251                               crtc->base.id, PTR_ERR(crtc_state));
13252                 drm_atomic_state_free(state);
13253                 return;
13254         }
13255
13256         crtc_state->base.active = crtc_state->base.enable =
13257                 to_intel_crtc(crtc)->new_enabled;
13258
13259         drm_mode_copy(&crtc_state->base.mode, &crtc->mode);
13260
13261         intel_modeset_setup_plane_state(state, crtc, &crtc->mode,
13262                                         crtc->primary->fb, crtc->x, crtc->y);
13263
13264         ret = intel_set_mode(state);
13265         if (ret)
13266                 drm_atomic_state_free(state);
13267 }
13268
13269 #undef for_each_intel_crtc_masked
13270
13271 static bool intel_connector_in_mode_set(struct intel_connector *connector,
13272                                         struct drm_mode_set *set)
13273 {
13274         int ro;
13275
13276         for (ro = 0; ro < set->num_connectors; ro++)
13277                 if (set->connectors[ro] == &connector->base)
13278                         return true;
13279
13280         return false;
13281 }
13282
13283 static int
13284 intel_modeset_stage_output_state(struct drm_device *dev,
13285                                  struct drm_mode_set *set,
13286                                  struct drm_atomic_state *state)
13287 {
13288         struct intel_connector *connector;
13289         struct drm_connector *drm_connector;
13290         struct drm_connector_state *connector_state;
13291         struct drm_crtc *crtc;
13292         struct drm_crtc_state *crtc_state;
13293         int i, ret;
13294
13295         /* The upper layers ensure that we either disable a crtc or have a list
13296          * of connectors. For paranoia, double-check this. */
13297         WARN_ON(!set->fb && (set->num_connectors != 0));
13298         WARN_ON(set->fb && (set->num_connectors == 0));
13299
13300         for_each_intel_connector(dev, connector) {
13301                 bool in_mode_set = intel_connector_in_mode_set(connector, set);
13302
13303                 if (!in_mode_set && connector->base.state->crtc != set->crtc)
13304                         continue;
13305
13306                 connector_state =
13307                         drm_atomic_get_connector_state(state, &connector->base);
13308                 if (IS_ERR(connector_state))
13309                         return PTR_ERR(connector_state);
13310
13311                 if (in_mode_set) {
13312                         int pipe = to_intel_crtc(set->crtc)->pipe;
13313                         connector_state->best_encoder =
13314                                 &intel_find_encoder(connector, pipe)->base;
13315                 }
13316
13317                 if (connector->base.state->crtc != set->crtc)
13318                         continue;
13319
13320                 /* If we disable the crtc, disable all its connectors. Also, if
13321                  * the connector is on the changing crtc but not on the new
13322                  * connector list, disable it. */
13323                 if (!set->fb || !in_mode_set) {
13324                         connector_state->best_encoder = NULL;
13325
13326                         DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [NOCRTC]\n",
13327                                 connector->base.base.id,
13328                                 connector->base.name);
13329                 }
13330         }
13331         /* connector->new_encoder is now updated for all connectors. */
13332
13333         for_each_connector_in_state(state, drm_connector, connector_state, i) {
13334                 connector = to_intel_connector(drm_connector);
13335
13336                 if (!connector_state->best_encoder) {
13337                         ret = drm_atomic_set_crtc_for_connector(connector_state,
13338                                                                 NULL);
13339                         if (ret)
13340                                 return ret;
13341
13342                         continue;
13343                 }
13344
13345                 if (intel_connector_in_mode_set(connector, set)) {
13346                         struct drm_crtc *crtc = connector->base.state->crtc;
13347
13348                         /* If this connector was in a previous crtc, add it
13349                          * to the state. We might need to disable it. */
13350                         if (crtc) {
13351                                 crtc_state =
13352                                         drm_atomic_get_crtc_state(state, crtc);
13353                                 if (IS_ERR(crtc_state))
13354                                         return PTR_ERR(crtc_state);
13355                         }
13356
13357                         ret = drm_atomic_set_crtc_for_connector(connector_state,
13358                                                                 set->crtc);
13359                         if (ret)
13360                                 return ret;
13361                 }
13362
13363                 /* Make sure the new CRTC will work with the encoder */
13364                 if (!drm_encoder_crtc_ok(connector_state->best_encoder,
13365                                          connector_state->crtc)) {
13366                         return -EINVAL;
13367                 }
13368
13369                 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [CRTC:%d]\n",
13370                         connector->base.base.id,
13371                         connector->base.name,
13372                         connector_state->crtc->base.id);
13373
13374                 if (connector_state->best_encoder != &connector->encoder->base)
13375                         connector->encoder =
13376                                 to_intel_encoder(connector_state->best_encoder);
13377         }
13378
13379         for_each_crtc_in_state(state, crtc, crtc_state, i) {
13380                 bool has_connectors;
13381
13382                 ret = drm_atomic_add_affected_connectors(state, crtc);
13383                 if (ret)
13384                         return ret;
13385
13386                 has_connectors = !!drm_atomic_connectors_for_crtc(state, crtc);
13387                 if (has_connectors != crtc_state->enable)
13388                         crtc_state->enable =
13389                         crtc_state->active = has_connectors;
13390         }
13391
13392         ret = intel_modeset_setup_plane_state(state, set->crtc, set->mode,
13393                                               set->fb, set->x, set->y);
13394         if (ret)
13395                 return ret;
13396
13397         crtc_state = drm_atomic_get_crtc_state(state, set->crtc);
13398         if (IS_ERR(crtc_state))
13399                 return PTR_ERR(crtc_state);
13400
13401         ret = drm_atomic_set_mode_for_crtc(crtc_state, set->mode);
13402         if (ret)
13403                 return ret;
13404
13405         if (set->num_connectors)
13406                 crtc_state->active = true;
13407
13408         return 0;
13409 }
13410
13411 static int intel_crtc_set_config(struct drm_mode_set *set)
13412 {
13413         struct drm_device *dev;
13414         struct drm_atomic_state *state = NULL;
13415         int ret;
13416
13417         BUG_ON(!set);
13418         BUG_ON(!set->crtc);
13419         BUG_ON(!set->crtc->helper_private);
13420
13421         /* Enforce sane interface api - has been abused by the fb helper. */
13422         BUG_ON(!set->mode && set->fb);
13423         BUG_ON(set->fb && set->num_connectors == 0);
13424
13425         if (set->fb) {
13426                 DRM_DEBUG_KMS("[CRTC:%d] [FB:%d] #connectors=%d (x y) (%i %i)\n",
13427                                 set->crtc->base.id, set->fb->base.id,
13428                                 (int)set->num_connectors, set->x, set->y);
13429         } else {
13430                 DRM_DEBUG_KMS("[CRTC:%d] [NOFB]\n", set->crtc->base.id);
13431         }
13432
13433         dev = set->crtc->dev;
13434
13435         state = drm_atomic_state_alloc(dev);
13436         if (!state)
13437                 return -ENOMEM;
13438
13439         state->acquire_ctx = dev->mode_config.acquire_ctx;
13440
13441         ret = intel_modeset_stage_output_state(dev, set, state);
13442         if (ret)
13443                 goto out;
13444
13445         ret = intel_modeset_compute_config(state);
13446         if (ret)
13447                 goto out;
13448
13449         intel_update_pipe_size(to_intel_crtc(set->crtc));
13450
13451         ret = intel_set_mode_checked(state);
13452         if (ret) {
13453                 DRM_DEBUG_KMS("failed to set mode on [CRTC:%d], err = %d\n",
13454                               set->crtc->base.id, ret);
13455         }
13456
13457 out:
13458         if (ret)
13459                 drm_atomic_state_free(state);
13460         return ret;
13461 }
13462
13463 static const struct drm_crtc_funcs intel_crtc_funcs = {
13464         .gamma_set = intel_crtc_gamma_set,
13465         .set_config = intel_crtc_set_config,
13466         .destroy = intel_crtc_destroy,
13467         .page_flip = intel_crtc_page_flip,
13468         .atomic_duplicate_state = intel_crtc_duplicate_state,
13469         .atomic_destroy_state = intel_crtc_destroy_state,
13470 };
13471
13472 static bool ibx_pch_dpll_get_hw_state(struct drm_i915_private *dev_priv,
13473                                       struct intel_shared_dpll *pll,
13474                                       struct intel_dpll_hw_state *hw_state)
13475 {
13476         uint32_t val;
13477
13478         if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_PLLS))
13479                 return false;
13480
13481         val = I915_READ(PCH_DPLL(pll->id));
13482         hw_state->dpll = val;
13483         hw_state->fp0 = I915_READ(PCH_FP0(pll->id));
13484         hw_state->fp1 = I915_READ(PCH_FP1(pll->id));
13485
13486         return val & DPLL_VCO_ENABLE;
13487 }
13488
13489 static void ibx_pch_dpll_mode_set(struct drm_i915_private *dev_priv,
13490                                   struct intel_shared_dpll *pll)
13491 {
13492         I915_WRITE(PCH_FP0(pll->id), pll->config.hw_state.fp0);
13493         I915_WRITE(PCH_FP1(pll->id), pll->config.hw_state.fp1);
13494 }
13495
13496 static void ibx_pch_dpll_enable(struct drm_i915_private *dev_priv,
13497                                 struct intel_shared_dpll *pll)
13498 {
13499         /* PCH refclock must be enabled first */
13500         ibx_assert_pch_refclk_enabled(dev_priv);
13501
13502         I915_WRITE(PCH_DPLL(pll->id), pll->config.hw_state.dpll);
13503
13504         /* Wait for the clocks to stabilize. */
13505         POSTING_READ(PCH_DPLL(pll->id));
13506         udelay(150);
13507
13508         /* The pixel multiplier can only be updated once the
13509          * DPLL is enabled and the clocks are stable.
13510          *
13511          * So write it again.
13512          */
13513         I915_WRITE(PCH_DPLL(pll->id), pll->config.hw_state.dpll);
13514         POSTING_READ(PCH_DPLL(pll->id));
13515         udelay(200);
13516 }
13517
13518 static void ibx_pch_dpll_disable(struct drm_i915_private *dev_priv,
13519                                  struct intel_shared_dpll *pll)
13520 {
13521         struct drm_device *dev = dev_priv->dev;
13522         struct intel_crtc *crtc;
13523
13524         /* Make sure no transcoder isn't still depending on us. */
13525         for_each_intel_crtc(dev, crtc) {
13526                 if (intel_crtc_to_shared_dpll(crtc) == pll)
13527                         assert_pch_transcoder_disabled(dev_priv, crtc->pipe);
13528         }
13529
13530         I915_WRITE(PCH_DPLL(pll->id), 0);
13531         POSTING_READ(PCH_DPLL(pll->id));
13532         udelay(200);
13533 }
13534
13535 static char *ibx_pch_dpll_names[] = {
13536         "PCH DPLL A",
13537         "PCH DPLL B",
13538 };
13539
13540 static void ibx_pch_dpll_init(struct drm_device *dev)
13541 {
13542         struct drm_i915_private *dev_priv = dev->dev_private;
13543         int i;
13544
13545         dev_priv->num_shared_dpll = 2;
13546
13547         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
13548                 dev_priv->shared_dplls[i].id = i;
13549                 dev_priv->shared_dplls[i].name = ibx_pch_dpll_names[i];
13550                 dev_priv->shared_dplls[i].mode_set = ibx_pch_dpll_mode_set;
13551                 dev_priv->shared_dplls[i].enable = ibx_pch_dpll_enable;
13552                 dev_priv->shared_dplls[i].disable = ibx_pch_dpll_disable;
13553                 dev_priv->shared_dplls[i].get_hw_state =
13554                         ibx_pch_dpll_get_hw_state;
13555         }
13556 }
13557
13558 static void intel_shared_dpll_init(struct drm_device *dev)
13559 {
13560         struct drm_i915_private *dev_priv = dev->dev_private;
13561
13562         intel_update_cdclk(dev);
13563
13564         if (HAS_DDI(dev))
13565                 intel_ddi_pll_init(dev);
13566         else if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
13567                 ibx_pch_dpll_init(dev);
13568         else
13569                 dev_priv->num_shared_dpll = 0;
13570
13571         BUG_ON(dev_priv->num_shared_dpll > I915_NUM_PLLS);
13572 }
13573
13574 /**
13575  * intel_prepare_plane_fb - Prepare fb for usage on plane
13576  * @plane: drm plane to prepare for
13577  * @fb: framebuffer to prepare for presentation
13578  *
13579  * Prepares a framebuffer for usage on a display plane.  Generally this
13580  * involves pinning the underlying object and updating the frontbuffer tracking
13581  * bits.  Some older platforms need special physical address handling for
13582  * cursor planes.
13583  *
13584  * Returns 0 on success, negative error code on failure.
13585  */
13586 int
13587 intel_prepare_plane_fb(struct drm_plane *plane,
13588                        struct drm_framebuffer *fb,
13589                        const struct drm_plane_state *new_state)
13590 {
13591         struct drm_device *dev = plane->dev;
13592         struct intel_plane *intel_plane = to_intel_plane(plane);
13593         enum pipe pipe = intel_plane->pipe;
13594         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
13595         struct drm_i915_gem_object *old_obj = intel_fb_obj(plane->fb);
13596         unsigned frontbuffer_bits = 0;
13597         int ret = 0;
13598
13599         if (!obj)
13600                 return 0;
13601
13602         switch (plane->type) {
13603         case DRM_PLANE_TYPE_PRIMARY:
13604                 frontbuffer_bits = INTEL_FRONTBUFFER_PRIMARY(pipe);
13605                 break;
13606         case DRM_PLANE_TYPE_CURSOR:
13607                 frontbuffer_bits = INTEL_FRONTBUFFER_CURSOR(pipe);
13608                 break;
13609         case DRM_PLANE_TYPE_OVERLAY:
13610                 frontbuffer_bits = INTEL_FRONTBUFFER_SPRITE(pipe);
13611                 break;
13612         }
13613
13614         mutex_lock(&dev->struct_mutex);
13615
13616         if (plane->type == DRM_PLANE_TYPE_CURSOR &&
13617             INTEL_INFO(dev)->cursor_needs_physical) {
13618                 int align = IS_I830(dev) ? 16 * 1024 : 256;
13619                 ret = i915_gem_object_attach_phys(obj, align);
13620                 if (ret)
13621                         DRM_DEBUG_KMS("failed to attach phys object\n");
13622         } else {
13623                 ret = intel_pin_and_fence_fb_obj(plane, fb, new_state, NULL);
13624         }
13625
13626         if (ret == 0)
13627                 i915_gem_track_fb(old_obj, obj, frontbuffer_bits);
13628
13629         mutex_unlock(&dev->struct_mutex);
13630
13631         return ret;
13632 }
13633
13634 /**
13635  * intel_cleanup_plane_fb - Cleans up an fb after plane use
13636  * @plane: drm plane to clean up for
13637  * @fb: old framebuffer that was on plane
13638  *
13639  * Cleans up a framebuffer that has just been removed from a plane.
13640  */
13641 void
13642 intel_cleanup_plane_fb(struct drm_plane *plane,
13643                        struct drm_framebuffer *fb,
13644                        const struct drm_plane_state *old_state)
13645 {
13646         struct drm_device *dev = plane->dev;
13647         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
13648
13649         if (WARN_ON(!obj))
13650                 return;
13651
13652         if (plane->type != DRM_PLANE_TYPE_CURSOR ||
13653             !INTEL_INFO(dev)->cursor_needs_physical) {
13654                 mutex_lock(&dev->struct_mutex);
13655                 intel_unpin_fb_obj(fb, old_state);
13656                 mutex_unlock(&dev->struct_mutex);
13657         }
13658 }
13659
13660 int
13661 skl_max_scale(struct intel_crtc *intel_crtc, struct intel_crtc_state *crtc_state)
13662 {
13663         int max_scale;
13664         struct drm_device *dev;
13665         struct drm_i915_private *dev_priv;
13666         int crtc_clock, cdclk;
13667
13668         if (!intel_crtc || !crtc_state)
13669                 return DRM_PLANE_HELPER_NO_SCALING;
13670
13671         dev = intel_crtc->base.dev;
13672         dev_priv = dev->dev_private;
13673         crtc_clock = crtc_state->base.adjusted_mode.crtc_clock;
13674         cdclk = to_intel_atomic_state(crtc_state->base.state)->cdclk;
13675
13676         if (!crtc_clock || !cdclk)
13677                 return DRM_PLANE_HELPER_NO_SCALING;
13678
13679         /*
13680          * skl max scale is lower of:
13681          *    close to 3 but not 3, -1 is for that purpose
13682          *            or
13683          *    cdclk/crtc_clock
13684          */
13685         max_scale = min((1 << 16) * 3 - 1, (1 << 8) * ((cdclk << 8) / crtc_clock));
13686
13687         return max_scale;
13688 }
13689
13690 static int
13691 intel_check_primary_plane(struct drm_plane *plane,
13692                           struct intel_crtc_state *crtc_state,
13693                           struct intel_plane_state *state)
13694 {
13695         struct drm_crtc *crtc = state->base.crtc;
13696         struct drm_framebuffer *fb = state->base.fb;
13697         int min_scale = DRM_PLANE_HELPER_NO_SCALING;
13698         int max_scale = DRM_PLANE_HELPER_NO_SCALING;
13699         bool can_position = false;
13700
13701         /* use scaler when colorkey is not required */
13702         if (INTEL_INFO(plane->dev)->gen >= 9 &&
13703             state->ckey.flags == I915_SET_COLORKEY_NONE) {
13704                 min_scale = 1;
13705                 max_scale = skl_max_scale(to_intel_crtc(crtc), crtc_state);
13706                 can_position = true;
13707         }
13708
13709         return drm_plane_helper_check_update(plane, crtc, fb, &state->src,
13710                                              &state->dst, &state->clip,
13711                                              min_scale, max_scale,
13712                                              can_position, true,
13713                                              &state->visible);
13714 }
13715
13716 static void
13717 intel_commit_primary_plane(struct drm_plane *plane,
13718                            struct intel_plane_state *state)
13719 {
13720         struct drm_crtc *crtc = state->base.crtc;
13721         struct drm_framebuffer *fb = state->base.fb;
13722         struct drm_device *dev = plane->dev;
13723         struct drm_i915_private *dev_priv = dev->dev_private;
13724         struct intel_crtc *intel_crtc;
13725         struct drm_rect *src = &state->src;
13726
13727         crtc = crtc ? crtc : plane->crtc;
13728         intel_crtc = to_intel_crtc(crtc);
13729
13730         plane->fb = fb;
13731         crtc->x = src->x1 >> 16;
13732         crtc->y = src->y1 >> 16;
13733
13734         if (!crtc->state->active)
13735                 return;
13736
13737         if (state->visible)
13738                 /* FIXME: kill this fastboot hack */
13739                 intel_update_pipe_size(intel_crtc);
13740
13741         dev_priv->display.update_primary_plane(crtc, fb, crtc->x, crtc->y);
13742 }
13743
13744 static void
13745 intel_disable_primary_plane(struct drm_plane *plane,
13746                             struct drm_crtc *crtc)
13747 {
13748         struct drm_device *dev = plane->dev;
13749         struct drm_i915_private *dev_priv = dev->dev_private;
13750
13751         dev_priv->display.update_primary_plane(crtc, NULL, 0, 0);
13752 }
13753
13754 static void intel_begin_crtc_commit(struct drm_crtc *crtc)
13755 {
13756         struct drm_device *dev = crtc->dev;
13757         struct drm_i915_private *dev_priv = dev->dev_private;
13758         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
13759
13760         if (!needs_modeset(crtc->state))
13761                 intel_pre_plane_update(intel_crtc);
13762
13763         if (intel_crtc->atomic.update_wm)
13764                 intel_update_watermarks(crtc);
13765
13766         intel_runtime_pm_get(dev_priv);
13767
13768         /* Perform vblank evasion around commit operation */
13769         if (crtc->state->active)
13770                 intel_crtc->atomic.evade =
13771                         intel_pipe_update_start(intel_crtc,
13772                                                 &intel_crtc->atomic.start_vbl_count);
13773
13774         if (!needs_modeset(crtc->state) && INTEL_INFO(dev)->gen >= 9)
13775                 skl_detach_scalers(intel_crtc);
13776 }
13777
13778 static void intel_finish_crtc_commit(struct drm_crtc *crtc)
13779 {
13780         struct drm_device *dev = crtc->dev;
13781         struct drm_i915_private *dev_priv = dev->dev_private;
13782         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
13783
13784         if (intel_crtc->atomic.evade)
13785                 intel_pipe_update_end(intel_crtc,
13786                                       intel_crtc->atomic.start_vbl_count);
13787
13788         intel_runtime_pm_put(dev_priv);
13789
13790         intel_post_plane_update(intel_crtc);
13791 }
13792
13793 /**
13794  * intel_plane_destroy - destroy a plane
13795  * @plane: plane to destroy
13796  *
13797  * Common destruction function for all types of planes (primary, cursor,
13798  * sprite).
13799  */
13800 void intel_plane_destroy(struct drm_plane *plane)
13801 {
13802         struct intel_plane *intel_plane = to_intel_plane(plane);
13803         drm_plane_cleanup(plane);
13804         kfree(intel_plane);
13805 }
13806
13807 const struct drm_plane_funcs intel_plane_funcs = {
13808         .update_plane = drm_atomic_helper_update_plane,
13809         .disable_plane = drm_atomic_helper_disable_plane,
13810         .destroy = intel_plane_destroy,
13811         .set_property = drm_atomic_helper_plane_set_property,
13812         .atomic_get_property = intel_plane_atomic_get_property,
13813         .atomic_set_property = intel_plane_atomic_set_property,
13814         .atomic_duplicate_state = intel_plane_duplicate_state,
13815         .atomic_destroy_state = intel_plane_destroy_state,
13816
13817 };
13818
13819 static struct drm_plane *intel_primary_plane_create(struct drm_device *dev,
13820                                                     int pipe)
13821 {
13822         struct intel_plane *primary;
13823         struct intel_plane_state *state;
13824         const uint32_t *intel_primary_formats;
13825         int num_formats;
13826
13827         primary = kzalloc(sizeof(*primary), GFP_KERNEL);
13828         if (primary == NULL)
13829                 return NULL;
13830
13831         state = intel_create_plane_state(&primary->base);
13832         if (!state) {
13833                 kfree(primary);
13834                 return NULL;
13835         }
13836         primary->base.state = &state->base;
13837
13838         primary->can_scale = false;
13839         primary->max_downscale = 1;
13840         if (INTEL_INFO(dev)->gen >= 9) {
13841                 primary->can_scale = true;
13842                 state->scaler_id = -1;
13843         }
13844         primary->pipe = pipe;
13845         primary->plane = pipe;
13846         primary->check_plane = intel_check_primary_plane;
13847         primary->commit_plane = intel_commit_primary_plane;
13848         primary->disable_plane = intel_disable_primary_plane;
13849         if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4)
13850                 primary->plane = !pipe;
13851
13852         if (INTEL_INFO(dev)->gen >= 9) {
13853                 intel_primary_formats = skl_primary_formats;
13854                 num_formats = ARRAY_SIZE(skl_primary_formats);
13855         } else if (INTEL_INFO(dev)->gen >= 4) {
13856                 intel_primary_formats = i965_primary_formats;
13857                 num_formats = ARRAY_SIZE(i965_primary_formats);
13858         } else {
13859                 intel_primary_formats = i8xx_primary_formats;
13860                 num_formats = ARRAY_SIZE(i8xx_primary_formats);
13861         }
13862
13863         drm_universal_plane_init(dev, &primary->base, 0,
13864                                  &intel_plane_funcs,
13865                                  intel_primary_formats, num_formats,
13866                                  DRM_PLANE_TYPE_PRIMARY);
13867
13868         if (INTEL_INFO(dev)->gen >= 4)
13869                 intel_create_rotation_property(dev, primary);
13870
13871         drm_plane_helper_add(&primary->base, &intel_plane_helper_funcs);
13872
13873         return &primary->base;
13874 }
13875
13876 void intel_create_rotation_property(struct drm_device *dev, struct intel_plane *plane)
13877 {
13878         if (!dev->mode_config.rotation_property) {
13879                 unsigned long flags = BIT(DRM_ROTATE_0) |
13880                         BIT(DRM_ROTATE_180);
13881
13882                 if (INTEL_INFO(dev)->gen >= 9)
13883                         flags |= BIT(DRM_ROTATE_90) | BIT(DRM_ROTATE_270);
13884
13885                 dev->mode_config.rotation_property =
13886                         drm_mode_create_rotation_property(dev, flags);
13887         }
13888         if (dev->mode_config.rotation_property)
13889                 drm_object_attach_property(&plane->base.base,
13890                                 dev->mode_config.rotation_property,
13891                                 plane->base.state->rotation);
13892 }
13893
13894 static int
13895 intel_check_cursor_plane(struct drm_plane *plane,
13896                          struct intel_crtc_state *crtc_state,
13897                          struct intel_plane_state *state)
13898 {
13899         struct drm_crtc *crtc = crtc_state->base.crtc;
13900         struct drm_framebuffer *fb = state->base.fb;
13901         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
13902         unsigned stride;
13903         int ret;
13904
13905         ret = drm_plane_helper_check_update(plane, crtc, fb, &state->src,
13906                                             &state->dst, &state->clip,
13907                                             DRM_PLANE_HELPER_NO_SCALING,
13908                                             DRM_PLANE_HELPER_NO_SCALING,
13909                                             true, true, &state->visible);
13910         if (ret)
13911                 return ret;
13912
13913         /* if we want to turn off the cursor ignore width and height */
13914         if (!obj)
13915                 return 0;
13916
13917         /* Check for which cursor types we support */
13918         if (!cursor_size_ok(plane->dev, state->base.crtc_w, state->base.crtc_h)) {
13919                 DRM_DEBUG("Cursor dimension %dx%d not supported\n",
13920                           state->base.crtc_w, state->base.crtc_h);
13921                 return -EINVAL;
13922         }
13923
13924         stride = roundup_pow_of_two(state->base.crtc_w) * 4;
13925         if (obj->base.size < stride * state->base.crtc_h) {
13926                 DRM_DEBUG_KMS("buffer is too small\n");
13927                 return -ENOMEM;
13928         }
13929
13930         if (fb->modifier[0] != DRM_FORMAT_MOD_NONE) {
13931                 DRM_DEBUG_KMS("cursor cannot be tiled\n");
13932                 return -EINVAL;
13933         }
13934
13935         return 0;
13936 }
13937
13938 static void
13939 intel_disable_cursor_plane(struct drm_plane *plane,
13940                            struct drm_crtc *crtc)
13941 {
13942         intel_crtc_update_cursor(crtc, false);
13943 }
13944
13945 static void
13946 intel_commit_cursor_plane(struct drm_plane *plane,
13947                           struct intel_plane_state *state)
13948 {
13949         struct drm_crtc *crtc = state->base.crtc;
13950         struct drm_device *dev = plane->dev;
13951         struct intel_crtc *intel_crtc;
13952         struct drm_i915_gem_object *obj = intel_fb_obj(state->base.fb);
13953         uint32_t addr;
13954
13955         crtc = crtc ? crtc : plane->crtc;
13956         intel_crtc = to_intel_crtc(crtc);
13957
13958         plane->fb = state->base.fb;
13959         crtc->cursor_x = state->base.crtc_x;
13960         crtc->cursor_y = state->base.crtc_y;
13961
13962         if (intel_crtc->cursor_bo == obj)
13963                 goto update;
13964
13965         if (!obj)
13966                 addr = 0;
13967         else if (!INTEL_INFO(dev)->cursor_needs_physical)
13968                 addr = i915_gem_obj_ggtt_offset(obj);
13969         else
13970                 addr = obj->phys_handle->busaddr;
13971
13972         intel_crtc->cursor_addr = addr;
13973         intel_crtc->cursor_bo = obj;
13974
13975 update:
13976         if (crtc->state->active)
13977                 intel_crtc_update_cursor(crtc, state->visible);
13978 }
13979
13980 static struct drm_plane *intel_cursor_plane_create(struct drm_device *dev,
13981                                                    int pipe)
13982 {
13983         struct intel_plane *cursor;
13984         struct intel_plane_state *state;
13985
13986         cursor = kzalloc(sizeof(*cursor), GFP_KERNEL);
13987         if (cursor == NULL)
13988                 return NULL;
13989
13990         state = intel_create_plane_state(&cursor->base);
13991         if (!state) {
13992                 kfree(cursor);
13993                 return NULL;
13994         }
13995         cursor->base.state = &state->base;
13996
13997         cursor->can_scale = false;
13998         cursor->max_downscale = 1;
13999         cursor->pipe = pipe;
14000         cursor->plane = pipe;
14001         cursor->check_plane = intel_check_cursor_plane;
14002         cursor->commit_plane = intel_commit_cursor_plane;
14003         cursor->disable_plane = intel_disable_cursor_plane;
14004
14005         drm_universal_plane_init(dev, &cursor->base, 0,
14006                                  &intel_plane_funcs,
14007                                  intel_cursor_formats,
14008                                  ARRAY_SIZE(intel_cursor_formats),
14009                                  DRM_PLANE_TYPE_CURSOR);
14010
14011         if (INTEL_INFO(dev)->gen >= 4) {
14012                 if (!dev->mode_config.rotation_property)
14013                         dev->mode_config.rotation_property =
14014                                 drm_mode_create_rotation_property(dev,
14015                                                         BIT(DRM_ROTATE_0) |
14016                                                         BIT(DRM_ROTATE_180));
14017                 if (dev->mode_config.rotation_property)
14018                         drm_object_attach_property(&cursor->base.base,
14019                                 dev->mode_config.rotation_property,
14020                                 state->base.rotation);
14021         }
14022
14023         if (INTEL_INFO(dev)->gen >=9)
14024                 state->scaler_id = -1;
14025
14026         drm_plane_helper_add(&cursor->base, &intel_plane_helper_funcs);
14027
14028         return &cursor->base;
14029 }
14030
14031 static void skl_init_scalers(struct drm_device *dev, struct intel_crtc *intel_crtc,
14032         struct intel_crtc_state *crtc_state)
14033 {
14034         int i;
14035         struct intel_scaler *intel_scaler;
14036         struct intel_crtc_scaler_state *scaler_state = &crtc_state->scaler_state;
14037
14038         for (i = 0; i < intel_crtc->num_scalers; i++) {
14039                 intel_scaler = &scaler_state->scalers[i];
14040                 intel_scaler->in_use = 0;
14041                 intel_scaler->mode = PS_SCALER_MODE_DYN;
14042         }
14043
14044         scaler_state->scaler_id = -1;
14045 }
14046
14047 static void intel_crtc_init(struct drm_device *dev, int pipe)
14048 {
14049         struct drm_i915_private *dev_priv = dev->dev_private;
14050         struct intel_crtc *intel_crtc;
14051         struct intel_crtc_state *crtc_state = NULL;
14052         struct drm_plane *primary = NULL;
14053         struct drm_plane *cursor = NULL;
14054         int i, ret;
14055
14056         intel_crtc = kzalloc(sizeof(*intel_crtc), GFP_KERNEL);
14057         if (intel_crtc == NULL)
14058                 return;
14059
14060         crtc_state = kzalloc(sizeof(*crtc_state), GFP_KERNEL);
14061         if (!crtc_state)
14062                 goto fail;
14063         intel_crtc->config = crtc_state;
14064         intel_crtc->base.state = &crtc_state->base;
14065         crtc_state->base.crtc = &intel_crtc->base;
14066
14067         /* initialize shared scalers */
14068         if (INTEL_INFO(dev)->gen >= 9) {
14069                 if (pipe == PIPE_C)
14070                         intel_crtc->num_scalers = 1;
14071                 else
14072                         intel_crtc->num_scalers = SKL_NUM_SCALERS;
14073
14074                 skl_init_scalers(dev, intel_crtc, crtc_state);
14075         }
14076
14077         primary = intel_primary_plane_create(dev, pipe);
14078         if (!primary)
14079                 goto fail;
14080
14081         cursor = intel_cursor_plane_create(dev, pipe);
14082         if (!cursor)
14083                 goto fail;
14084
14085         ret = drm_crtc_init_with_planes(dev, &intel_crtc->base, primary,
14086                                         cursor, &intel_crtc_funcs);
14087         if (ret)
14088                 goto fail;
14089
14090         drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
14091         for (i = 0; i < 256; i++) {
14092                 intel_crtc->lut_r[i] = i;
14093                 intel_crtc->lut_g[i] = i;
14094                 intel_crtc->lut_b[i] = i;
14095         }
14096
14097         /*
14098          * On gen2/3 only plane A can do fbc, but the panel fitter and lvds port
14099          * is hooked to pipe B. Hence we want plane A feeding pipe B.
14100          */
14101         intel_crtc->pipe = pipe;
14102         intel_crtc->plane = pipe;
14103         if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4) {
14104                 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
14105                 intel_crtc->plane = !pipe;
14106         }
14107
14108         intel_crtc->cursor_base = ~0;
14109         intel_crtc->cursor_cntl = ~0;
14110         intel_crtc->cursor_size = ~0;
14111
14112         BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
14113                dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
14114         dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
14115         dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
14116
14117         drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
14118
14119         WARN_ON(drm_crtc_index(&intel_crtc->base) != intel_crtc->pipe);
14120         return;
14121
14122 fail:
14123         if (primary)
14124                 drm_plane_cleanup(primary);
14125         if (cursor)
14126                 drm_plane_cleanup(cursor);
14127         kfree(crtc_state);
14128         kfree(intel_crtc);
14129 }
14130
14131 enum pipe intel_get_pipe_from_connector(struct intel_connector *connector)
14132 {
14133         struct drm_encoder *encoder = connector->base.encoder;
14134         struct drm_device *dev = connector->base.dev;
14135
14136         WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex));
14137
14138         if (!encoder || WARN_ON(!encoder->crtc))
14139                 return INVALID_PIPE;
14140
14141         return to_intel_crtc(encoder->crtc)->pipe;
14142 }
14143
14144 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
14145                                 struct drm_file *file)
14146 {
14147         struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
14148         struct drm_crtc *drmmode_crtc;
14149         struct intel_crtc *crtc;
14150
14151         drmmode_crtc = drm_crtc_find(dev, pipe_from_crtc_id->crtc_id);
14152
14153         if (!drmmode_crtc) {
14154                 DRM_ERROR("no such CRTC id\n");
14155                 return -ENOENT;
14156         }
14157
14158         crtc = to_intel_crtc(drmmode_crtc);
14159         pipe_from_crtc_id->pipe = crtc->pipe;
14160
14161         return 0;
14162 }
14163
14164 static int intel_encoder_clones(struct intel_encoder *encoder)
14165 {
14166         struct drm_device *dev = encoder->base.dev;
14167         struct intel_encoder *source_encoder;
14168         int index_mask = 0;
14169         int entry = 0;
14170
14171         for_each_intel_encoder(dev, source_encoder) {
14172                 if (encoders_cloneable(encoder, source_encoder))
14173                         index_mask |= (1 << entry);
14174
14175                 entry++;
14176         }
14177
14178         return index_mask;
14179 }
14180
14181 static bool has_edp_a(struct drm_device *dev)
14182 {
14183         struct drm_i915_private *dev_priv = dev->dev_private;
14184
14185         if (!IS_MOBILE(dev))
14186                 return false;
14187
14188         if ((I915_READ(DP_A) & DP_DETECTED) == 0)
14189                 return false;
14190
14191         if (IS_GEN5(dev) && (I915_READ(FUSE_STRAP) & ILK_eDP_A_DISABLE))
14192                 return false;
14193
14194         return true;
14195 }
14196
14197 static bool intel_crt_present(struct drm_device *dev)
14198 {
14199         struct drm_i915_private *dev_priv = dev->dev_private;
14200
14201         if (INTEL_INFO(dev)->gen >= 9)
14202                 return false;
14203
14204         if (IS_HSW_ULT(dev) || IS_BDW_ULT(dev))
14205                 return false;
14206
14207         if (IS_CHERRYVIEW(dev))
14208                 return false;
14209
14210         if (IS_VALLEYVIEW(dev) && !dev_priv->vbt.int_crt_support)
14211                 return false;
14212
14213         return true;
14214 }
14215
14216 static void intel_setup_outputs(struct drm_device *dev)
14217 {
14218         struct drm_i915_private *dev_priv = dev->dev_private;
14219         struct intel_encoder *encoder;
14220         bool dpd_is_edp = false;
14221
14222         intel_lvds_init(dev);
14223
14224         if (intel_crt_present(dev))
14225                 intel_crt_init(dev);
14226
14227         if (IS_BROXTON(dev)) {
14228                 /*
14229                  * FIXME: Broxton doesn't support port detection via the
14230                  * DDI_BUF_CTL_A or SFUSE_STRAP registers, find another way to
14231                  * detect the ports.
14232                  */
14233                 intel_ddi_init(dev, PORT_A);
14234                 intel_ddi_init(dev, PORT_B);
14235                 intel_ddi_init(dev, PORT_C);
14236         } else if (HAS_DDI(dev)) {
14237                 int found;
14238
14239                 /*
14240                  * Haswell uses DDI functions to detect digital outputs.
14241                  * On SKL pre-D0 the strap isn't connected, so we assume
14242                  * it's there.
14243                  */
14244                 found = I915_READ(DDI_BUF_CTL_A) & DDI_INIT_DISPLAY_DETECTED;
14245                 /* WaIgnoreDDIAStrap: skl */
14246                 if (found ||
14247                     (IS_SKYLAKE(dev) && INTEL_REVID(dev) < SKL_REVID_D0))
14248                         intel_ddi_init(dev, PORT_A);
14249
14250                 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
14251                  * register */
14252                 found = I915_READ(SFUSE_STRAP);
14253
14254                 if (found & SFUSE_STRAP_DDIB_DETECTED)
14255                         intel_ddi_init(dev, PORT_B);
14256                 if (found & SFUSE_STRAP_DDIC_DETECTED)
14257                         intel_ddi_init(dev, PORT_C);
14258                 if (found & SFUSE_STRAP_DDID_DETECTED)
14259                         intel_ddi_init(dev, PORT_D);
14260         } else if (HAS_PCH_SPLIT(dev)) {
14261                 int found;
14262                 dpd_is_edp = intel_dp_is_edp(dev, PORT_D);
14263
14264                 if (has_edp_a(dev))
14265                         intel_dp_init(dev, DP_A, PORT_A);
14266
14267                 if (I915_READ(PCH_HDMIB) & SDVO_DETECTED) {
14268                         /* PCH SDVOB multiplex with HDMIB */
14269                         found = intel_sdvo_init(dev, PCH_SDVOB, true);
14270                         if (!found)
14271                                 intel_hdmi_init(dev, PCH_HDMIB, PORT_B);
14272                         if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
14273                                 intel_dp_init(dev, PCH_DP_B, PORT_B);
14274                 }
14275
14276                 if (I915_READ(PCH_HDMIC) & SDVO_DETECTED)
14277                         intel_hdmi_init(dev, PCH_HDMIC, PORT_C);
14278
14279                 if (!dpd_is_edp && I915_READ(PCH_HDMID) & SDVO_DETECTED)
14280                         intel_hdmi_init(dev, PCH_HDMID, PORT_D);
14281
14282                 if (I915_READ(PCH_DP_C) & DP_DETECTED)
14283                         intel_dp_init(dev, PCH_DP_C, PORT_C);
14284
14285                 if (I915_READ(PCH_DP_D) & DP_DETECTED)
14286                         intel_dp_init(dev, PCH_DP_D, PORT_D);
14287         } else if (IS_VALLEYVIEW(dev)) {
14288                 /*
14289                  * The DP_DETECTED bit is the latched state of the DDC
14290                  * SDA pin at boot. However since eDP doesn't require DDC
14291                  * (no way to plug in a DP->HDMI dongle) the DDC pins for
14292                  * eDP ports may have been muxed to an alternate function.
14293                  * Thus we can't rely on the DP_DETECTED bit alone to detect
14294                  * eDP ports. Consult the VBT as well as DP_DETECTED to
14295                  * detect eDP ports.
14296                  */
14297                 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIB) & SDVO_DETECTED &&
14298                     !intel_dp_is_edp(dev, PORT_B))
14299                         intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIB,
14300                                         PORT_B);
14301                 if (I915_READ(VLV_DISPLAY_BASE + DP_B) & DP_DETECTED ||
14302                     intel_dp_is_edp(dev, PORT_B))
14303                         intel_dp_init(dev, VLV_DISPLAY_BASE + DP_B, PORT_B);
14304
14305                 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIC) & SDVO_DETECTED &&
14306                     !intel_dp_is_edp(dev, PORT_C))
14307                         intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIC,
14308                                         PORT_C);
14309                 if (I915_READ(VLV_DISPLAY_BASE + DP_C) & DP_DETECTED ||
14310                     intel_dp_is_edp(dev, PORT_C))
14311                         intel_dp_init(dev, VLV_DISPLAY_BASE + DP_C, PORT_C);
14312
14313                 if (IS_CHERRYVIEW(dev)) {
14314                         if (I915_READ(VLV_DISPLAY_BASE + CHV_HDMID) & SDVO_DETECTED)
14315                                 intel_hdmi_init(dev, VLV_DISPLAY_BASE + CHV_HDMID,
14316                                                 PORT_D);
14317                         /* eDP not supported on port D, so don't check VBT */
14318                         if (I915_READ(VLV_DISPLAY_BASE + DP_D) & DP_DETECTED)
14319                                 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_D, PORT_D);
14320                 }
14321
14322                 intel_dsi_init(dev);
14323         } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
14324                 bool found = false;
14325
14326                 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
14327                         DRM_DEBUG_KMS("probing SDVOB\n");
14328                         found = intel_sdvo_init(dev, GEN3_SDVOB, true);
14329                         if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) {
14330                                 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
14331                                 intel_hdmi_init(dev, GEN4_HDMIB, PORT_B);
14332                         }
14333
14334                         if (!found && SUPPORTS_INTEGRATED_DP(dev))
14335                                 intel_dp_init(dev, DP_B, PORT_B);
14336                 }
14337
14338                 /* Before G4X SDVOC doesn't have its own detect register */
14339
14340                 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
14341                         DRM_DEBUG_KMS("probing SDVOC\n");
14342                         found = intel_sdvo_init(dev, GEN3_SDVOC, false);
14343                 }
14344
14345                 if (!found && (I915_READ(GEN3_SDVOC) & SDVO_DETECTED)) {
14346
14347                         if (SUPPORTS_INTEGRATED_HDMI(dev)) {
14348                                 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
14349                                 intel_hdmi_init(dev, GEN4_HDMIC, PORT_C);
14350                         }
14351                         if (SUPPORTS_INTEGRATED_DP(dev))
14352                                 intel_dp_init(dev, DP_C, PORT_C);
14353                 }
14354
14355                 if (SUPPORTS_INTEGRATED_DP(dev) &&
14356                     (I915_READ(DP_D) & DP_DETECTED))
14357                         intel_dp_init(dev, DP_D, PORT_D);
14358         } else if (IS_GEN2(dev))
14359                 intel_dvo_init(dev);
14360
14361         if (SUPPORTS_TV(dev))
14362                 intel_tv_init(dev);
14363
14364         intel_psr_init(dev);
14365
14366         for_each_intel_encoder(dev, encoder) {
14367                 encoder->base.possible_crtcs = encoder->crtc_mask;
14368                 encoder->base.possible_clones =
14369                         intel_encoder_clones(encoder);
14370         }
14371
14372         intel_init_pch_refclk(dev);
14373
14374         drm_helper_move_panel_connectors_to_head(dev);
14375 }
14376
14377 static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
14378 {
14379         struct drm_device *dev = fb->dev;
14380         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
14381
14382         drm_framebuffer_cleanup(fb);
14383         mutex_lock(&dev->struct_mutex);
14384         WARN_ON(!intel_fb->obj->framebuffer_references--);
14385         drm_gem_object_unreference(&intel_fb->obj->base);
14386         mutex_unlock(&dev->struct_mutex);
14387         kfree(intel_fb);
14388 }
14389
14390 static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
14391                                                 struct drm_file *file,
14392                                                 unsigned int *handle)
14393 {
14394         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
14395         struct drm_i915_gem_object *obj = intel_fb->obj;
14396
14397         return drm_gem_handle_create(file, &obj->base, handle);
14398 }
14399
14400 static const struct drm_framebuffer_funcs intel_fb_funcs = {
14401         .destroy = intel_user_framebuffer_destroy,
14402         .create_handle = intel_user_framebuffer_create_handle,
14403 };
14404
14405 static
14406 u32 intel_fb_pitch_limit(struct drm_device *dev, uint64_t fb_modifier,
14407                          uint32_t pixel_format)
14408 {
14409         u32 gen = INTEL_INFO(dev)->gen;
14410
14411         if (gen >= 9) {
14412                 /* "The stride in bytes must not exceed the of the size of 8K
14413                  *  pixels and 32K bytes."
14414                  */
14415                  return min(8192*drm_format_plane_cpp(pixel_format, 0), 32768);
14416         } else if (gen >= 5 && !IS_VALLEYVIEW(dev)) {
14417                 return 32*1024;
14418         } else if (gen >= 4) {
14419                 if (fb_modifier == I915_FORMAT_MOD_X_TILED)
14420                         return 16*1024;
14421                 else
14422                         return 32*1024;
14423         } else if (gen >= 3) {
14424                 if (fb_modifier == I915_FORMAT_MOD_X_TILED)
14425                         return 8*1024;
14426                 else
14427                         return 16*1024;
14428         } else {
14429                 /* XXX DSPC is limited to 4k tiled */
14430                 return 8*1024;
14431         }
14432 }
14433
14434 static int intel_framebuffer_init(struct drm_device *dev,
14435                                   struct intel_framebuffer *intel_fb,
14436                                   struct drm_mode_fb_cmd2 *mode_cmd,
14437                                   struct drm_i915_gem_object *obj)
14438 {
14439         unsigned int aligned_height;
14440         int ret;
14441         u32 pitch_limit, stride_alignment;
14442
14443         WARN_ON(!mutex_is_locked(&dev->struct_mutex));
14444
14445         if (mode_cmd->flags & DRM_MODE_FB_MODIFIERS) {
14446                 /* Enforce that fb modifier and tiling mode match, but only for
14447                  * X-tiled. This is needed for FBC. */
14448                 if (!!(obj->tiling_mode == I915_TILING_X) !=
14449                     !!(mode_cmd->modifier[0] == I915_FORMAT_MOD_X_TILED)) {
14450                         DRM_DEBUG("tiling_mode doesn't match fb modifier\n");
14451                         return -EINVAL;
14452                 }
14453         } else {
14454                 if (obj->tiling_mode == I915_TILING_X)
14455                         mode_cmd->modifier[0] = I915_FORMAT_MOD_X_TILED;
14456                 else if (obj->tiling_mode == I915_TILING_Y) {
14457                         DRM_DEBUG("No Y tiling for legacy addfb\n");
14458                         return -EINVAL;
14459                 }
14460         }
14461
14462         /* Passed in modifier sanity checking. */
14463         switch (mode_cmd->modifier[0]) {
14464         case I915_FORMAT_MOD_Y_TILED:
14465         case I915_FORMAT_MOD_Yf_TILED:
14466                 if (INTEL_INFO(dev)->gen < 9) {
14467                         DRM_DEBUG("Unsupported tiling 0x%llx!\n",
14468                                   mode_cmd->modifier[0]);
14469                         return -EINVAL;
14470                 }
14471         case DRM_FORMAT_MOD_NONE:
14472         case I915_FORMAT_MOD_X_TILED:
14473                 break;
14474         default:
14475                 DRM_DEBUG("Unsupported fb modifier 0x%llx!\n",
14476                           mode_cmd->modifier[0]);
14477                 return -EINVAL;
14478         }
14479
14480         stride_alignment = intel_fb_stride_alignment(dev, mode_cmd->modifier[0],
14481                                                      mode_cmd->pixel_format);
14482         if (mode_cmd->pitches[0] & (stride_alignment - 1)) {
14483                 DRM_DEBUG("pitch (%d) must be at least %u byte aligned\n",
14484                           mode_cmd->pitches[0], stride_alignment);
14485                 return -EINVAL;
14486         }
14487
14488         pitch_limit = intel_fb_pitch_limit(dev, mode_cmd->modifier[0],
14489                                            mode_cmd->pixel_format);
14490         if (mode_cmd->pitches[0] > pitch_limit) {
14491                 DRM_DEBUG("%s pitch (%u) must be at less than %d\n",
14492                           mode_cmd->modifier[0] != DRM_FORMAT_MOD_NONE ?
14493                           "tiled" : "linear",
14494                           mode_cmd->pitches[0], pitch_limit);
14495                 return -EINVAL;
14496         }
14497
14498         if (mode_cmd->modifier[0] == I915_FORMAT_MOD_X_TILED &&
14499             mode_cmd->pitches[0] != obj->stride) {
14500                 DRM_DEBUG("pitch (%d) must match tiling stride (%d)\n",
14501                           mode_cmd->pitches[0], obj->stride);
14502                 return -EINVAL;
14503         }
14504
14505         /* Reject formats not supported by any plane early. */
14506         switch (mode_cmd->pixel_format) {
14507         case DRM_FORMAT_C8:
14508         case DRM_FORMAT_RGB565:
14509         case DRM_FORMAT_XRGB8888:
14510         case DRM_FORMAT_ARGB8888:
14511                 break;
14512         case DRM_FORMAT_XRGB1555:
14513                 if (INTEL_INFO(dev)->gen > 3) {
14514                         DRM_DEBUG("unsupported pixel format: %s\n",
14515                                   drm_get_format_name(mode_cmd->pixel_format));
14516                         return -EINVAL;
14517                 }
14518                 break;
14519         case DRM_FORMAT_ABGR8888:
14520                 if (!IS_VALLEYVIEW(dev) && INTEL_INFO(dev)->gen < 9) {
14521                         DRM_DEBUG("unsupported pixel format: %s\n",
14522                                   drm_get_format_name(mode_cmd->pixel_format));
14523                         return -EINVAL;
14524                 }
14525                 break;
14526         case DRM_FORMAT_XBGR8888:
14527         case DRM_FORMAT_XRGB2101010:
14528         case DRM_FORMAT_XBGR2101010:
14529                 if (INTEL_INFO(dev)->gen < 4) {
14530                         DRM_DEBUG("unsupported pixel format: %s\n",
14531                                   drm_get_format_name(mode_cmd->pixel_format));
14532                         return -EINVAL;
14533                 }
14534                 break;
14535         case DRM_FORMAT_ABGR2101010:
14536                 if (!IS_VALLEYVIEW(dev)) {
14537                         DRM_DEBUG("unsupported pixel format: %s\n",
14538                                   drm_get_format_name(mode_cmd->pixel_format));
14539                         return -EINVAL;
14540                 }
14541                 break;
14542         case DRM_FORMAT_YUYV:
14543         case DRM_FORMAT_UYVY:
14544         case DRM_FORMAT_YVYU:
14545         case DRM_FORMAT_VYUY:
14546                 if (INTEL_INFO(dev)->gen < 5) {
14547                         DRM_DEBUG("unsupported pixel format: %s\n",
14548                                   drm_get_format_name(mode_cmd->pixel_format));
14549                         return -EINVAL;
14550                 }
14551                 break;
14552         default:
14553                 DRM_DEBUG("unsupported pixel format: %s\n",
14554                           drm_get_format_name(mode_cmd->pixel_format));
14555                 return -EINVAL;
14556         }
14557
14558         /* FIXME need to adjust LINOFF/TILEOFF accordingly. */
14559         if (mode_cmd->offsets[0] != 0)
14560                 return -EINVAL;
14561
14562         aligned_height = intel_fb_align_height(dev, mode_cmd->height,
14563                                                mode_cmd->pixel_format,
14564                                                mode_cmd->modifier[0]);
14565         /* FIXME drm helper for size checks (especially planar formats)? */
14566         if (obj->base.size < aligned_height * mode_cmd->pitches[0])
14567                 return -EINVAL;
14568
14569         drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
14570         intel_fb->obj = obj;
14571         intel_fb->obj->framebuffer_references++;
14572
14573         ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
14574         if (ret) {
14575                 DRM_ERROR("framebuffer init failed %d\n", ret);
14576                 return ret;
14577         }
14578
14579         return 0;
14580 }
14581
14582 static struct drm_framebuffer *
14583 intel_user_framebuffer_create(struct drm_device *dev,
14584                               struct drm_file *filp,
14585                               struct drm_mode_fb_cmd2 *mode_cmd)
14586 {
14587         struct drm_i915_gem_object *obj;
14588
14589         obj = to_intel_bo(drm_gem_object_lookup(dev, filp,
14590                                                 mode_cmd->handles[0]));
14591         if (&obj->base == NULL)
14592                 return ERR_PTR(-ENOENT);
14593
14594         return intel_framebuffer_create(dev, mode_cmd, obj);
14595 }
14596
14597 #ifndef CONFIG_DRM_I915_FBDEV
14598 static inline void intel_fbdev_output_poll_changed(struct drm_device *dev)
14599 {
14600 }
14601 #endif
14602
14603 static const struct drm_mode_config_funcs intel_mode_funcs = {
14604         .fb_create = intel_user_framebuffer_create,
14605         .output_poll_changed = intel_fbdev_output_poll_changed,
14606         .atomic_check = intel_atomic_check,
14607         .atomic_commit = intel_atomic_commit,
14608         .atomic_state_alloc = intel_atomic_state_alloc,
14609         .atomic_state_clear = intel_atomic_state_clear,
14610 };
14611
14612 /* Set up chip specific display functions */
14613 static void intel_init_display(struct drm_device *dev)
14614 {
14615         struct drm_i915_private *dev_priv = dev->dev_private;
14616
14617         if (HAS_PCH_SPLIT(dev) || IS_G4X(dev))
14618                 dev_priv->display.find_dpll = g4x_find_best_dpll;
14619         else if (IS_CHERRYVIEW(dev))
14620                 dev_priv->display.find_dpll = chv_find_best_dpll;
14621         else if (IS_VALLEYVIEW(dev))
14622                 dev_priv->display.find_dpll = vlv_find_best_dpll;
14623         else if (IS_PINEVIEW(dev))
14624                 dev_priv->display.find_dpll = pnv_find_best_dpll;
14625         else
14626                 dev_priv->display.find_dpll = i9xx_find_best_dpll;
14627
14628         if (INTEL_INFO(dev)->gen >= 9) {
14629                 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
14630                 dev_priv->display.get_initial_plane_config =
14631                         skylake_get_initial_plane_config;
14632                 dev_priv->display.crtc_compute_clock =
14633                         haswell_crtc_compute_clock;
14634                 dev_priv->display.crtc_enable = haswell_crtc_enable;
14635                 dev_priv->display.crtc_disable = haswell_crtc_disable;
14636                 dev_priv->display.update_primary_plane =
14637                         skylake_update_primary_plane;
14638         } else if (HAS_DDI(dev)) {
14639                 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
14640                 dev_priv->display.get_initial_plane_config =
14641                         ironlake_get_initial_plane_config;
14642                 dev_priv->display.crtc_compute_clock =
14643                         haswell_crtc_compute_clock;
14644                 dev_priv->display.crtc_enable = haswell_crtc_enable;
14645                 dev_priv->display.crtc_disable = haswell_crtc_disable;
14646                 dev_priv->display.update_primary_plane =
14647                         ironlake_update_primary_plane;
14648         } else if (HAS_PCH_SPLIT(dev)) {
14649                 dev_priv->display.get_pipe_config = ironlake_get_pipe_config;
14650                 dev_priv->display.get_initial_plane_config =
14651                         ironlake_get_initial_plane_config;
14652                 dev_priv->display.crtc_compute_clock =
14653                         ironlake_crtc_compute_clock;
14654                 dev_priv->display.crtc_enable = ironlake_crtc_enable;
14655                 dev_priv->display.crtc_disable = ironlake_crtc_disable;
14656                 dev_priv->display.update_primary_plane =
14657                         ironlake_update_primary_plane;
14658         } else if (IS_VALLEYVIEW(dev)) {
14659                 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
14660                 dev_priv->display.get_initial_plane_config =
14661                         i9xx_get_initial_plane_config;
14662                 dev_priv->display.crtc_compute_clock = i9xx_crtc_compute_clock;
14663                 dev_priv->display.crtc_enable = valleyview_crtc_enable;
14664                 dev_priv->display.crtc_disable = i9xx_crtc_disable;
14665                 dev_priv->display.update_primary_plane =
14666                         i9xx_update_primary_plane;
14667         } else {
14668                 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
14669                 dev_priv->display.get_initial_plane_config =
14670                         i9xx_get_initial_plane_config;
14671                 dev_priv->display.crtc_compute_clock = i9xx_crtc_compute_clock;
14672                 dev_priv->display.crtc_enable = i9xx_crtc_enable;
14673                 dev_priv->display.crtc_disable = i9xx_crtc_disable;
14674                 dev_priv->display.update_primary_plane =
14675                         i9xx_update_primary_plane;
14676         }
14677
14678         /* Returns the core display clock speed */
14679         if (IS_SKYLAKE(dev))
14680                 dev_priv->display.get_display_clock_speed =
14681                         skylake_get_display_clock_speed;
14682         else if (IS_BROADWELL(dev))
14683                 dev_priv->display.get_display_clock_speed =
14684                         broadwell_get_display_clock_speed;
14685         else if (IS_HASWELL(dev))
14686                 dev_priv->display.get_display_clock_speed =
14687                         haswell_get_display_clock_speed;
14688         else if (IS_VALLEYVIEW(dev))
14689                 dev_priv->display.get_display_clock_speed =
14690                         valleyview_get_display_clock_speed;
14691         else if (IS_GEN5(dev))
14692                 dev_priv->display.get_display_clock_speed =
14693                         ilk_get_display_clock_speed;
14694         else if (IS_I945G(dev) || IS_BROADWATER(dev) ||
14695                  IS_GEN6(dev) || IS_IVYBRIDGE(dev))
14696                 dev_priv->display.get_display_clock_speed =
14697                         i945_get_display_clock_speed;
14698         else if (IS_GM45(dev))
14699                 dev_priv->display.get_display_clock_speed =
14700                         gm45_get_display_clock_speed;
14701         else if (IS_CRESTLINE(dev))
14702                 dev_priv->display.get_display_clock_speed =
14703                         i965gm_get_display_clock_speed;
14704         else if (IS_PINEVIEW(dev))
14705                 dev_priv->display.get_display_clock_speed =
14706                         pnv_get_display_clock_speed;
14707         else if (IS_G33(dev) || IS_G4X(dev))
14708                 dev_priv->display.get_display_clock_speed =
14709                         g33_get_display_clock_speed;
14710         else if (IS_I915G(dev))
14711                 dev_priv->display.get_display_clock_speed =
14712                         i915_get_display_clock_speed;
14713         else if (IS_I945GM(dev) || IS_845G(dev))
14714                 dev_priv->display.get_display_clock_speed =
14715                         i9xx_misc_get_display_clock_speed;
14716         else if (IS_PINEVIEW(dev))
14717                 dev_priv->display.get_display_clock_speed =
14718                         pnv_get_display_clock_speed;
14719         else if (IS_I915GM(dev))
14720                 dev_priv->display.get_display_clock_speed =
14721                         i915gm_get_display_clock_speed;
14722         else if (IS_I865G(dev))
14723                 dev_priv->display.get_display_clock_speed =
14724                         i865_get_display_clock_speed;
14725         else if (IS_I85X(dev))
14726                 dev_priv->display.get_display_clock_speed =
14727                         i85x_get_display_clock_speed;
14728         else { /* 830 */
14729                 WARN(!IS_I830(dev), "Unknown platform. Assuming 133 MHz CDCLK\n");
14730                 dev_priv->display.get_display_clock_speed =
14731                         i830_get_display_clock_speed;
14732         }
14733
14734         if (IS_GEN5(dev)) {
14735                 dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
14736         } else if (IS_GEN6(dev)) {
14737                 dev_priv->display.fdi_link_train = gen6_fdi_link_train;
14738         } else if (IS_IVYBRIDGE(dev)) {
14739                 /* FIXME: detect B0+ stepping and use auto training */
14740                 dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
14741         } else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
14742                 dev_priv->display.fdi_link_train = hsw_fdi_link_train;
14743                 if (IS_BROADWELL(dev)) {
14744                         dev_priv->display.modeset_commit_cdclk =
14745                                 broadwell_modeset_commit_cdclk;
14746                         dev_priv->display.modeset_calc_cdclk =
14747                                 broadwell_modeset_calc_cdclk;
14748                 }
14749         } else if (IS_VALLEYVIEW(dev)) {
14750                 dev_priv->display.modeset_commit_cdclk =
14751                         valleyview_modeset_commit_cdclk;
14752                 dev_priv->display.modeset_calc_cdclk =
14753                         valleyview_modeset_calc_cdclk;
14754         } else if (IS_BROXTON(dev)) {
14755                 dev_priv->display.modeset_commit_cdclk =
14756                         broxton_modeset_commit_cdclk;
14757                 dev_priv->display.modeset_calc_cdclk =
14758                         broxton_modeset_calc_cdclk;
14759         }
14760
14761         switch (INTEL_INFO(dev)->gen) {
14762         case 2:
14763                 dev_priv->display.queue_flip = intel_gen2_queue_flip;
14764                 break;
14765
14766         case 3:
14767                 dev_priv->display.queue_flip = intel_gen3_queue_flip;
14768                 break;
14769
14770         case 4:
14771         case 5:
14772                 dev_priv->display.queue_flip = intel_gen4_queue_flip;
14773                 break;
14774
14775         case 6:
14776                 dev_priv->display.queue_flip = intel_gen6_queue_flip;
14777                 break;
14778         case 7:
14779         case 8: /* FIXME(BDW): Check that the gen8 RCS flip works. */
14780                 dev_priv->display.queue_flip = intel_gen7_queue_flip;
14781                 break;
14782         case 9:
14783                 /* Drop through - unsupported since execlist only. */
14784         default:
14785                 /* Default just returns -ENODEV to indicate unsupported */
14786                 dev_priv->display.queue_flip = intel_default_queue_flip;
14787         }
14788
14789         intel_panel_init_backlight_funcs(dev);
14790
14791         mutex_init(&dev_priv->pps_mutex);
14792 }
14793
14794 /*
14795  * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
14796  * resume, or other times.  This quirk makes sure that's the case for
14797  * affected systems.
14798  */
14799 static void quirk_pipea_force(struct drm_device *dev)
14800 {
14801         struct drm_i915_private *dev_priv = dev->dev_private;
14802
14803         dev_priv->quirks |= QUIRK_PIPEA_FORCE;
14804         DRM_INFO("applying pipe a force quirk\n");
14805 }
14806
14807 static void quirk_pipeb_force(struct drm_device *dev)
14808 {
14809         struct drm_i915_private *dev_priv = dev->dev_private;
14810
14811         dev_priv->quirks |= QUIRK_PIPEB_FORCE;
14812         DRM_INFO("applying pipe b force quirk\n");
14813 }
14814
14815 /*
14816  * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
14817  */
14818 static void quirk_ssc_force_disable(struct drm_device *dev)
14819 {
14820         struct drm_i915_private *dev_priv = dev->dev_private;
14821         dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
14822         DRM_INFO("applying lvds SSC disable quirk\n");
14823 }
14824
14825 /*
14826  * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
14827  * brightness value
14828  */
14829 static void quirk_invert_brightness(struct drm_device *dev)
14830 {
14831         struct drm_i915_private *dev_priv = dev->dev_private;
14832         dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS;
14833         DRM_INFO("applying inverted panel brightness quirk\n");
14834 }
14835
14836 /* Some VBT's incorrectly indicate no backlight is present */
14837 static void quirk_backlight_present(struct drm_device *dev)
14838 {
14839         struct drm_i915_private *dev_priv = dev->dev_private;
14840         dev_priv->quirks |= QUIRK_BACKLIGHT_PRESENT;
14841         DRM_INFO("applying backlight present quirk\n");
14842 }
14843
14844 struct intel_quirk {
14845         int device;
14846         int subsystem_vendor;
14847         int subsystem_device;
14848         void (*hook)(struct drm_device *dev);
14849 };
14850
14851 /* For systems that don't have a meaningful PCI subdevice/subvendor ID */
14852 struct intel_dmi_quirk {
14853         void (*hook)(struct drm_device *dev);
14854         const struct dmi_system_id (*dmi_id_list)[];
14855 };
14856
14857 static int intel_dmi_reverse_brightness(const struct dmi_system_id *id)
14858 {
14859         DRM_INFO("Backlight polarity reversed on %s\n", id->ident);
14860         return 1;
14861 }
14862
14863 static const struct intel_dmi_quirk intel_dmi_quirks[] = {
14864         {
14865                 .dmi_id_list = &(const struct dmi_system_id[]) {
14866                         {
14867                                 .callback = intel_dmi_reverse_brightness,
14868                                 .ident = "NCR Corporation",
14869                                 .matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"),
14870                                             DMI_MATCH(DMI_PRODUCT_NAME, ""),
14871                                 },
14872                         },
14873                         { }  /* terminating entry */
14874                 },
14875                 .hook = quirk_invert_brightness,
14876         },
14877 };
14878
14879 static struct intel_quirk intel_quirks[] = {
14880         /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
14881         { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
14882
14883         /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
14884         { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
14885
14886         /* 830 needs to leave pipe A & dpll A up */
14887         { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
14888
14889         /* 830 needs to leave pipe B & dpll B up */
14890         { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipeb_force },
14891
14892         /* Lenovo U160 cannot use SSC on LVDS */
14893         { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
14894
14895         /* Sony Vaio Y cannot use SSC on LVDS */
14896         { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
14897
14898         /* Acer Aspire 5734Z must invert backlight brightness */
14899         { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness },
14900
14901         /* Acer/eMachines G725 */
14902         { 0x2a42, 0x1025, 0x0210, quirk_invert_brightness },
14903
14904         /* Acer/eMachines e725 */
14905         { 0x2a42, 0x1025, 0x0212, quirk_invert_brightness },
14906
14907         /* Acer/Packard Bell NCL20 */
14908         { 0x2a42, 0x1025, 0x034b, quirk_invert_brightness },
14909
14910         /* Acer Aspire 4736Z */
14911         { 0x2a42, 0x1025, 0x0260, quirk_invert_brightness },
14912
14913         /* Acer Aspire 5336 */
14914         { 0x2a42, 0x1025, 0x048a, quirk_invert_brightness },
14915
14916         /* Acer C720 and C720P Chromebooks (Celeron 2955U) have backlights */
14917         { 0x0a06, 0x1025, 0x0a11, quirk_backlight_present },
14918
14919         /* Acer C720 Chromebook (Core i3 4005U) */
14920         { 0x0a16, 0x1025, 0x0a11, quirk_backlight_present },
14921
14922         /* Apple Macbook 2,1 (Core 2 T7400) */
14923         { 0x27a2, 0x8086, 0x7270, quirk_backlight_present },
14924
14925         /* Toshiba CB35 Chromebook (Celeron 2955U) */
14926         { 0x0a06, 0x1179, 0x0a88, quirk_backlight_present },
14927
14928         /* HP Chromebook 14 (Celeron 2955U) */
14929         { 0x0a06, 0x103c, 0x21ed, quirk_backlight_present },
14930
14931         /* Dell Chromebook 11 */
14932         { 0x0a06, 0x1028, 0x0a35, quirk_backlight_present },
14933 };
14934
14935 static void intel_init_quirks(struct drm_device *dev)
14936 {
14937         struct pci_dev *d = dev->pdev;
14938         int i;
14939
14940         for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
14941                 struct intel_quirk *q = &intel_quirks[i];
14942
14943                 if (d->device == q->device &&
14944                     (d->subsystem_vendor == q->subsystem_vendor ||
14945                      q->subsystem_vendor == PCI_ANY_ID) &&
14946                     (d->subsystem_device == q->subsystem_device ||
14947                      q->subsystem_device == PCI_ANY_ID))
14948                         q->hook(dev);
14949         }
14950         for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) {
14951                 if (dmi_check_system(*intel_dmi_quirks[i].dmi_id_list) != 0)
14952                         intel_dmi_quirks[i].hook(dev);
14953         }
14954 }
14955
14956 /* Disable the VGA plane that we never use */
14957 static void i915_disable_vga(struct drm_device *dev)
14958 {
14959         struct drm_i915_private *dev_priv = dev->dev_private;
14960         u8 sr1;
14961         u32 vga_reg = i915_vgacntrl_reg(dev);
14962
14963         /* WaEnableVGAAccessThroughIOPort:ctg,elk,ilk,snb,ivb,vlv,hsw */
14964         vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
14965         outb(SR01, VGA_SR_INDEX);
14966         sr1 = inb(VGA_SR_DATA);
14967         outb(sr1 | 1<<5, VGA_SR_DATA);
14968         vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
14969         udelay(300);
14970
14971         I915_WRITE(vga_reg, VGA_DISP_DISABLE);
14972         POSTING_READ(vga_reg);
14973 }
14974
14975 void intel_modeset_init_hw(struct drm_device *dev)
14976 {
14977         intel_update_cdclk(dev);
14978         intel_prepare_ddi(dev);
14979         intel_init_clock_gating(dev);
14980         intel_enable_gt_powersave(dev);
14981 }
14982
14983 void intel_modeset_init(struct drm_device *dev)
14984 {
14985         struct drm_i915_private *dev_priv = dev->dev_private;
14986         int sprite, ret;
14987         enum pipe pipe;
14988         struct intel_crtc *crtc;
14989
14990         drm_mode_config_init(dev);
14991
14992         dev->mode_config.min_width = 0;
14993         dev->mode_config.min_height = 0;
14994
14995         dev->mode_config.preferred_depth = 24;
14996         dev->mode_config.prefer_shadow = 1;
14997
14998         dev->mode_config.allow_fb_modifiers = true;
14999
15000         dev->mode_config.funcs = &intel_mode_funcs;
15001
15002         intel_init_quirks(dev);
15003
15004         intel_init_pm(dev);
15005
15006         if (INTEL_INFO(dev)->num_pipes == 0)
15007                 return;
15008
15009         intel_init_display(dev);
15010         intel_init_audio(dev);
15011
15012         if (IS_GEN2(dev)) {
15013                 dev->mode_config.max_width = 2048;
15014                 dev->mode_config.max_height = 2048;
15015         } else if (IS_GEN3(dev)) {
15016                 dev->mode_config.max_width = 4096;
15017                 dev->mode_config.max_height = 4096;
15018         } else {
15019                 dev->mode_config.max_width = 8192;
15020                 dev->mode_config.max_height = 8192;
15021         }
15022
15023         if (IS_845G(dev) || IS_I865G(dev)) {
15024                 dev->mode_config.cursor_width = IS_845G(dev) ? 64 : 512;
15025                 dev->mode_config.cursor_height = 1023;
15026         } else if (IS_GEN2(dev)) {
15027                 dev->mode_config.cursor_width = GEN2_CURSOR_WIDTH;
15028                 dev->mode_config.cursor_height = GEN2_CURSOR_HEIGHT;
15029         } else {
15030                 dev->mode_config.cursor_width = MAX_CURSOR_WIDTH;
15031                 dev->mode_config.cursor_height = MAX_CURSOR_HEIGHT;
15032         }
15033
15034         dev->mode_config.fb_base = dev_priv->gtt.mappable_base;
15035
15036         DRM_DEBUG_KMS("%d display pipe%s available.\n",
15037                       INTEL_INFO(dev)->num_pipes,
15038                       INTEL_INFO(dev)->num_pipes > 1 ? "s" : "");
15039
15040         for_each_pipe(dev_priv, pipe) {
15041                 intel_crtc_init(dev, pipe);
15042                 for_each_sprite(dev_priv, pipe, sprite) {
15043                         ret = intel_plane_init(dev, pipe, sprite);
15044                         if (ret)
15045                                 DRM_DEBUG_KMS("pipe %c sprite %c init failed: %d\n",
15046                                               pipe_name(pipe), sprite_name(pipe, sprite), ret);
15047                 }
15048         }
15049
15050         intel_init_dpio(dev);
15051
15052         intel_shared_dpll_init(dev);
15053
15054         /* Just disable it once at startup */
15055         i915_disable_vga(dev);
15056         intel_setup_outputs(dev);
15057
15058         /* Just in case the BIOS is doing something questionable. */
15059         intel_fbc_disable(dev);
15060
15061         drm_modeset_lock_all(dev);
15062         intel_modeset_setup_hw_state(dev, false);
15063         drm_modeset_unlock_all(dev);
15064
15065         for_each_intel_crtc(dev, crtc) {
15066                 if (!crtc->active)
15067                         continue;
15068
15069                 /*
15070                  * Note that reserving the BIOS fb up front prevents us
15071                  * from stuffing other stolen allocations like the ring
15072                  * on top.  This prevents some ugliness at boot time, and
15073                  * can even allow for smooth boot transitions if the BIOS
15074                  * fb is large enough for the active pipe configuration.
15075                  */
15076                 if (dev_priv->display.get_initial_plane_config) {
15077                         dev_priv->display.get_initial_plane_config(crtc,
15078                                                            &crtc->plane_config);
15079                         /*
15080                          * If the fb is shared between multiple heads, we'll
15081                          * just get the first one.
15082                          */
15083                         intel_find_initial_plane_obj(crtc, &crtc->plane_config);
15084                 }
15085         }
15086 }
15087
15088 static void intel_enable_pipe_a(struct drm_device *dev)
15089 {
15090         struct intel_connector *connector;
15091         struct drm_connector *crt = NULL;
15092         struct intel_load_detect_pipe load_detect_temp;
15093         struct drm_modeset_acquire_ctx *ctx = dev->mode_config.acquire_ctx;
15094
15095         /* We can't just switch on the pipe A, we need to set things up with a
15096          * proper mode and output configuration. As a gross hack, enable pipe A
15097          * by enabling the load detect pipe once. */
15098         for_each_intel_connector(dev, connector) {
15099                 if (connector->encoder->type == INTEL_OUTPUT_ANALOG) {
15100                         crt = &connector->base;
15101                         break;
15102                 }
15103         }
15104
15105         if (!crt)
15106                 return;
15107
15108         if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp, ctx))
15109                 intel_release_load_detect_pipe(crt, &load_detect_temp, ctx);
15110 }
15111
15112 static bool
15113 intel_check_plane_mapping(struct intel_crtc *crtc)
15114 {
15115         struct drm_device *dev = crtc->base.dev;
15116         struct drm_i915_private *dev_priv = dev->dev_private;
15117         u32 reg, val;
15118
15119         if (INTEL_INFO(dev)->num_pipes == 1)
15120                 return true;
15121
15122         reg = DSPCNTR(!crtc->plane);
15123         val = I915_READ(reg);
15124
15125         if ((val & DISPLAY_PLANE_ENABLE) &&
15126             (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe))
15127                 return false;
15128
15129         return true;
15130 }
15131
15132 static void intel_sanitize_crtc(struct intel_crtc *crtc)
15133 {
15134         struct drm_device *dev = crtc->base.dev;
15135         struct drm_i915_private *dev_priv = dev->dev_private;
15136         struct intel_encoder *encoder;
15137         u32 reg;
15138         bool enable;
15139
15140         /* Clear any frame start delays used for debugging left by the BIOS */
15141         reg = PIPECONF(crtc->config->cpu_transcoder);
15142         I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
15143
15144         /* restore vblank interrupts to correct state */
15145         drm_crtc_vblank_reset(&crtc->base);
15146         if (crtc->active) {
15147                 update_scanline_offset(crtc);
15148                 drm_crtc_vblank_on(&crtc->base);
15149         }
15150
15151         /* We need to sanitize the plane -> pipe mapping first because this will
15152          * disable the crtc (and hence change the state) if it is wrong. Note
15153          * that gen4+ has a fixed plane -> pipe mapping.  */
15154         if (INTEL_INFO(dev)->gen < 4 && !intel_check_plane_mapping(crtc)) {
15155                 bool plane;
15156
15157                 DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n",
15158                               crtc->base.base.id);
15159
15160                 /* Pipe has the wrong plane attached and the plane is active.
15161                  * Temporarily change the plane mapping and disable everything
15162                  * ...  */
15163                 plane = crtc->plane;
15164                 to_intel_plane_state(crtc->base.primary->state)->visible = true;
15165                 crtc->plane = !plane;
15166                 intel_crtc_disable_noatomic(&crtc->base);
15167                 crtc->plane = plane;
15168         }
15169
15170         if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
15171             crtc->pipe == PIPE_A && !crtc->active) {
15172                 /* BIOS forgot to enable pipe A, this mostly happens after
15173                  * resume. Force-enable the pipe to fix this, the update_dpms
15174                  * call below we restore the pipe to the right state, but leave
15175                  * the required bits on. */
15176                 intel_enable_pipe_a(dev);
15177         }
15178
15179         /* Adjust the state of the output pipe according to whether we
15180          * have active connectors/encoders. */
15181         enable = false;
15182         for_each_encoder_on_crtc(dev, &crtc->base, encoder)
15183                 enable |= encoder->connectors_active;
15184
15185         if (!enable)
15186                 intel_crtc_disable_noatomic(&crtc->base);
15187
15188         if (crtc->active != crtc->base.state->active) {
15189
15190                 /* This can happen either due to bugs in the get_hw_state
15191                  * functions or because of calls to intel_crtc_disable_noatomic,
15192                  * or because the pipe is force-enabled due to the
15193                  * pipe A quirk. */
15194                 DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was %s, now %s\n",
15195                               crtc->base.base.id,
15196                               crtc->base.state->enable ? "enabled" : "disabled",
15197                               crtc->active ? "enabled" : "disabled");
15198
15199                 crtc->base.state->enable = crtc->active;
15200                 crtc->base.state->active = crtc->active;
15201                 crtc->base.enabled = crtc->active;
15202
15203                 /* Because we only establish the connector -> encoder ->
15204                  * crtc links if something is active, this means the
15205                  * crtc is now deactivated. Break the links. connector
15206                  * -> encoder links are only establish when things are
15207                  *  actually up, hence no need to break them. */
15208                 WARN_ON(crtc->active);
15209
15210                 for_each_encoder_on_crtc(dev, &crtc->base, encoder) {
15211                         WARN_ON(encoder->connectors_active);
15212                         encoder->base.crtc = NULL;
15213                 }
15214         }
15215
15216         if (crtc->active || HAS_GMCH_DISPLAY(dev)) {
15217                 /*
15218                  * We start out with underrun reporting disabled to avoid races.
15219                  * For correct bookkeeping mark this on active crtcs.
15220                  *
15221                  * Also on gmch platforms we dont have any hardware bits to
15222                  * disable the underrun reporting. Which means we need to start
15223                  * out with underrun reporting disabled also on inactive pipes,
15224                  * since otherwise we'll complain about the garbage we read when
15225                  * e.g. coming up after runtime pm.
15226                  *
15227                  * No protection against concurrent access is required - at
15228                  * worst a fifo underrun happens which also sets this to false.
15229                  */
15230                 crtc->cpu_fifo_underrun_disabled = true;
15231                 crtc->pch_fifo_underrun_disabled = true;
15232         }
15233 }
15234
15235 static void intel_sanitize_encoder(struct intel_encoder *encoder)
15236 {
15237         struct intel_connector *connector;
15238         struct drm_device *dev = encoder->base.dev;
15239
15240         /* We need to check both for a crtc link (meaning that the
15241          * encoder is active and trying to read from a pipe) and the
15242          * pipe itself being active. */
15243         bool has_active_crtc = encoder->base.crtc &&
15244                 to_intel_crtc(encoder->base.crtc)->active;
15245
15246         if (encoder->connectors_active && !has_active_crtc) {
15247                 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
15248                               encoder->base.base.id,
15249                               encoder->base.name);
15250
15251                 /* Connector is active, but has no active pipe. This is
15252                  * fallout from our resume register restoring. Disable
15253                  * the encoder manually again. */
15254                 if (encoder->base.crtc) {
15255                         DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
15256                                       encoder->base.base.id,
15257                                       encoder->base.name);
15258                         encoder->disable(encoder);
15259                         if (encoder->post_disable)
15260                                 encoder->post_disable(encoder);
15261                 }
15262                 encoder->base.crtc = NULL;
15263                 encoder->connectors_active = false;
15264
15265                 /* Inconsistent output/port/pipe state happens presumably due to
15266                  * a bug in one of the get_hw_state functions. Or someplace else
15267                  * in our code, like the register restore mess on resume. Clamp
15268                  * things to off as a safer default. */
15269                 for_each_intel_connector(dev, connector) {
15270                         if (connector->encoder != encoder)
15271                                 continue;
15272                         connector->base.dpms = DRM_MODE_DPMS_OFF;
15273                         connector->base.encoder = NULL;
15274                 }
15275         }
15276         /* Enabled encoders without active connectors will be fixed in
15277          * the crtc fixup. */
15278 }
15279
15280 void i915_redisable_vga_power_on(struct drm_device *dev)
15281 {
15282         struct drm_i915_private *dev_priv = dev->dev_private;
15283         u32 vga_reg = i915_vgacntrl_reg(dev);
15284
15285         if (!(I915_READ(vga_reg) & VGA_DISP_DISABLE)) {
15286                 DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n");
15287                 i915_disable_vga(dev);
15288         }
15289 }
15290
15291 void i915_redisable_vga(struct drm_device *dev)
15292 {
15293         struct drm_i915_private *dev_priv = dev->dev_private;
15294
15295         /* This function can be called both from intel_modeset_setup_hw_state or
15296          * at a very early point in our resume sequence, where the power well
15297          * structures are not yet restored. Since this function is at a very
15298          * paranoid "someone might have enabled VGA while we were not looking"
15299          * level, just check if the power well is enabled instead of trying to
15300          * follow the "don't touch the power well if we don't need it" policy
15301          * the rest of the driver uses. */
15302         if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_VGA))
15303                 return;
15304
15305         i915_redisable_vga_power_on(dev);
15306 }
15307
15308 static bool primary_get_hw_state(struct intel_crtc *crtc)
15309 {
15310         struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
15311
15312         return !!(I915_READ(DSPCNTR(crtc->plane)) & DISPLAY_PLANE_ENABLE);
15313 }
15314
15315 static void readout_plane_state(struct intel_crtc *crtc,
15316                                 struct intel_crtc_state *crtc_state)
15317 {
15318         struct intel_plane *p;
15319         struct drm_plane_state *drm_plane_state;
15320         bool active = crtc_state->base.active;
15321
15322         if (active) {
15323                 crtc_state->quirks |= PIPE_CONFIG_QUIRK_INITIAL_PLANES;
15324
15325                 /* apply to previous sw state too */
15326                 to_intel_crtc_state(crtc->base.state)->quirks |=
15327                         PIPE_CONFIG_QUIRK_INITIAL_PLANES;
15328         }
15329
15330         for_each_intel_plane(crtc->base.dev, p) {
15331                 bool visible = active;
15332
15333                 if (crtc->pipe != p->pipe)
15334                         continue;
15335
15336                 drm_plane_state = p->base.state;
15337                 if (active && p->base.type == DRM_PLANE_TYPE_PRIMARY) {
15338                         visible = primary_get_hw_state(crtc);
15339                         to_intel_plane_state(drm_plane_state)->visible = visible;
15340                 } else {
15341                         /*
15342                          * unknown state, assume it's off to force a transition
15343                          * to on when calculating state changes.
15344                          */
15345                         to_intel_plane_state(drm_plane_state)->visible = false;
15346                 }
15347
15348                 if (visible) {
15349                         crtc_state->base.plane_mask |=
15350                                 1 << drm_plane_index(&p->base);
15351                 } else if (crtc_state->base.state) {
15352                         /* Make this unconditional for atomic hw readout. */
15353                         crtc_state->base.plane_mask &=
15354                                 ~(1 << drm_plane_index(&p->base));
15355                 }
15356         }
15357 }
15358
15359 static void intel_modeset_readout_hw_state(struct drm_device *dev)
15360 {
15361         struct drm_i915_private *dev_priv = dev->dev_private;
15362         enum pipe pipe;
15363         struct intel_crtc *crtc;
15364         struct intel_encoder *encoder;
15365         struct intel_connector *connector;
15366         int i;
15367
15368         for_each_intel_crtc(dev, crtc) {
15369                 memset(crtc->config, 0, sizeof(*crtc->config));
15370                 crtc->config->base.crtc = &crtc->base;
15371
15372                 crtc->config->quirks |= PIPE_CONFIG_QUIRK_INHERITED_MODE;
15373
15374                 crtc->active = dev_priv->display.get_pipe_config(crtc,
15375                                                                  crtc->config);
15376
15377                 crtc->base.state->enable = crtc->active;
15378                 crtc->base.state->active = crtc->active;
15379                 crtc->base.enabled = crtc->active;
15380                 crtc->base.hwmode = crtc->config->base.adjusted_mode;
15381
15382                 readout_plane_state(crtc, to_intel_crtc_state(crtc->base.state));
15383
15384                 DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n",
15385                               crtc->base.base.id,
15386                               crtc->active ? "enabled" : "disabled");
15387         }
15388
15389         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
15390                 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
15391
15392                 pll->on = pll->get_hw_state(dev_priv, pll,
15393                                             &pll->config.hw_state);
15394                 pll->active = 0;
15395                 pll->config.crtc_mask = 0;
15396                 for_each_intel_crtc(dev, crtc) {
15397                         if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll) {
15398                                 pll->active++;
15399                                 pll->config.crtc_mask |= 1 << crtc->pipe;
15400                         }
15401                 }
15402
15403                 DRM_DEBUG_KMS("%s hw state readout: crtc_mask 0x%08x, on %i\n",
15404                               pll->name, pll->config.crtc_mask, pll->on);
15405
15406                 if (pll->config.crtc_mask)
15407                         intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
15408         }
15409
15410         for_each_intel_encoder(dev, encoder) {
15411                 pipe = 0;
15412
15413                 if (encoder->get_hw_state(encoder, &pipe)) {
15414                         crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
15415                         encoder->base.crtc = &crtc->base;
15416                         encoder->get_config(encoder, crtc->config);
15417                 } else {
15418                         encoder->base.crtc = NULL;
15419                 }
15420
15421                 encoder->connectors_active = false;
15422                 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe %c\n",
15423                               encoder->base.base.id,
15424                               encoder->base.name,
15425                               encoder->base.crtc ? "enabled" : "disabled",
15426                               pipe_name(pipe));
15427         }
15428
15429         for_each_intel_connector(dev, connector) {
15430                 if (connector->get_hw_state(connector)) {
15431                         connector->base.dpms = DRM_MODE_DPMS_ON;
15432                         connector->encoder->connectors_active = true;
15433                         connector->base.encoder = &connector->encoder->base;
15434                 } else {
15435                         connector->base.dpms = DRM_MODE_DPMS_OFF;
15436                         connector->base.encoder = NULL;
15437                 }
15438                 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
15439                               connector->base.base.id,
15440                               connector->base.name,
15441                               connector->base.encoder ? "enabled" : "disabled");
15442         }
15443 }
15444
15445 /* Scan out the current hw modeset state, sanitizes it and maps it into the drm
15446  * and i915 state tracking structures. */
15447 void intel_modeset_setup_hw_state(struct drm_device *dev,
15448                                   bool force_restore)
15449 {
15450         struct drm_i915_private *dev_priv = dev->dev_private;
15451         enum pipe pipe;
15452         struct intel_crtc *crtc;
15453         struct intel_encoder *encoder;
15454         int i;
15455
15456         intel_modeset_readout_hw_state(dev);
15457
15458         /*
15459          * Now that we have the config, copy it to each CRTC struct
15460          * Note that this could go away if we move to using crtc_config
15461          * checking everywhere.
15462          */
15463         for_each_intel_crtc(dev, crtc) {
15464                 if (crtc->active && i915.fastboot) {
15465                         intel_mode_from_pipe_config(&crtc->base.mode,
15466                                                     crtc->config);
15467                         DRM_DEBUG_KMS("[CRTC:%d] found active mode: ",
15468                                       crtc->base.base.id);
15469                         drm_mode_debug_printmodeline(&crtc->base.mode);
15470                 }
15471         }
15472
15473         /* HW state is read out, now we need to sanitize this mess. */
15474         for_each_intel_encoder(dev, encoder) {
15475                 intel_sanitize_encoder(encoder);
15476         }
15477
15478         for_each_pipe(dev_priv, pipe) {
15479                 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
15480                 intel_sanitize_crtc(crtc);
15481                 intel_dump_pipe_config(crtc, crtc->config,
15482                                        "[setup_hw_state]");
15483         }
15484
15485         intel_modeset_update_connector_atomic_state(dev);
15486
15487         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
15488                 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
15489
15490                 if (!pll->on || pll->active)
15491                         continue;
15492
15493                 DRM_DEBUG_KMS("%s enabled but not in use, disabling\n", pll->name);
15494
15495                 pll->disable(dev_priv, pll);
15496                 pll->on = false;
15497         }
15498
15499         if (IS_GEN9(dev))
15500                 skl_wm_get_hw_state(dev);
15501         else if (HAS_PCH_SPLIT(dev))
15502                 ilk_wm_get_hw_state(dev);
15503
15504         if (force_restore) {
15505                 i915_redisable_vga(dev);
15506
15507                 /*
15508                  * We need to use raw interfaces for restoring state to avoid
15509                  * checking (bogus) intermediate states.
15510                  */
15511                 for_each_pipe(dev_priv, pipe) {
15512                         struct drm_crtc *crtc =
15513                                 dev_priv->pipe_to_crtc_mapping[pipe];
15514
15515                         intel_crtc_restore_mode(crtc);
15516                 }
15517         } else {
15518                 intel_modeset_update_staged_output_state(dev);
15519         }
15520
15521         intel_modeset_check_state(dev);
15522 }
15523
15524 void intel_modeset_gem_init(struct drm_device *dev)
15525 {
15526         struct drm_i915_private *dev_priv = dev->dev_private;
15527         struct drm_crtc *c;
15528         struct drm_i915_gem_object *obj;
15529         int ret;
15530
15531         mutex_lock(&dev->struct_mutex);
15532         intel_init_gt_powersave(dev);
15533         mutex_unlock(&dev->struct_mutex);
15534
15535         /*
15536          * There may be no VBT; and if the BIOS enabled SSC we can
15537          * just keep using it to avoid unnecessary flicker.  Whereas if the
15538          * BIOS isn't using it, don't assume it will work even if the VBT
15539          * indicates as much.
15540          */
15541         if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
15542                 dev_priv->vbt.lvds_use_ssc = !!(I915_READ(PCH_DREF_CONTROL) &
15543                                                 DREF_SSC1_ENABLE);
15544
15545         intel_modeset_init_hw(dev);
15546
15547         intel_setup_overlay(dev);
15548
15549         /*
15550          * Make sure any fbs we allocated at startup are properly
15551          * pinned & fenced.  When we do the allocation it's too early
15552          * for this.
15553          */
15554         for_each_crtc(dev, c) {
15555                 obj = intel_fb_obj(c->primary->fb);
15556                 if (obj == NULL)
15557                         continue;
15558
15559                 mutex_lock(&dev->struct_mutex);
15560                 ret = intel_pin_and_fence_fb_obj(c->primary,
15561                                                  c->primary->fb,
15562                                                  c->primary->state,
15563                                                  NULL);
15564                 mutex_unlock(&dev->struct_mutex);
15565                 if (ret) {
15566                         DRM_ERROR("failed to pin boot fb on pipe %d\n",
15567                                   to_intel_crtc(c)->pipe);
15568                         drm_framebuffer_unreference(c->primary->fb);
15569                         c->primary->fb = NULL;
15570                         c->primary->crtc = c->primary->state->crtc = NULL;
15571                         update_state_fb(c->primary);
15572                         c->state->plane_mask &= ~(1 << drm_plane_index(c->primary));
15573                 }
15574         }
15575
15576         intel_backlight_register(dev);
15577 }
15578
15579 void intel_connector_unregister(struct intel_connector *intel_connector)
15580 {
15581         struct drm_connector *connector = &intel_connector->base;
15582
15583         intel_panel_destroy_backlight(connector);
15584         drm_connector_unregister(connector);
15585 }
15586
15587 void intel_modeset_cleanup(struct drm_device *dev)
15588 {
15589         struct drm_i915_private *dev_priv = dev->dev_private;
15590         struct drm_connector *connector;
15591
15592         intel_disable_gt_powersave(dev);
15593
15594         intel_backlight_unregister(dev);
15595
15596         /*
15597          * Interrupts and polling as the first thing to avoid creating havoc.
15598          * Too much stuff here (turning of connectors, ...) would
15599          * experience fancy races otherwise.
15600          */
15601         intel_irq_uninstall(dev_priv);
15602
15603         /*
15604          * Due to the hpd irq storm handling the hotplug work can re-arm the
15605          * poll handlers. Hence disable polling after hpd handling is shut down.
15606          */
15607         drm_kms_helper_poll_fini(dev);
15608
15609         mutex_lock(&dev->struct_mutex);
15610
15611         intel_unregister_dsm_handler();
15612
15613         intel_fbc_disable(dev);
15614
15615         mutex_unlock(&dev->struct_mutex);
15616
15617         /* flush any delayed tasks or pending work */
15618         flush_scheduled_work();
15619
15620         /* destroy the backlight and sysfs files before encoders/connectors */
15621         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
15622                 struct intel_connector *intel_connector;
15623
15624                 intel_connector = to_intel_connector(connector);
15625                 intel_connector->unregister(intel_connector);
15626         }
15627
15628         drm_mode_config_cleanup(dev);
15629
15630         intel_cleanup_overlay(dev);
15631
15632         mutex_lock(&dev->struct_mutex);
15633         intel_cleanup_gt_powersave(dev);
15634         mutex_unlock(&dev->struct_mutex);
15635 }
15636
15637 /*
15638  * Return which encoder is currently attached for connector.
15639  */
15640 struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
15641 {
15642         return &intel_attached_encoder(connector)->base;
15643 }
15644
15645 void intel_connector_attach_encoder(struct intel_connector *connector,
15646                                     struct intel_encoder *encoder)
15647 {
15648         connector->encoder = encoder;
15649         drm_mode_connector_attach_encoder(&connector->base,
15650                                           &encoder->base);
15651 }
15652
15653 /*
15654  * set vga decode state - true == enable VGA decode
15655  */
15656 int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
15657 {
15658         struct drm_i915_private *dev_priv = dev->dev_private;
15659         unsigned reg = INTEL_INFO(dev)->gen >= 6 ? SNB_GMCH_CTRL : INTEL_GMCH_CTRL;
15660         u16 gmch_ctrl;
15661
15662         if (pci_read_config_word(dev_priv->bridge_dev, reg, &gmch_ctrl)) {
15663                 DRM_ERROR("failed to read control word\n");
15664                 return -EIO;
15665         }
15666
15667         if (!!(gmch_ctrl & INTEL_GMCH_VGA_DISABLE) == !state)
15668                 return 0;
15669
15670         if (state)
15671                 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
15672         else
15673                 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
15674
15675         if (pci_write_config_word(dev_priv->bridge_dev, reg, gmch_ctrl)) {
15676                 DRM_ERROR("failed to write control word\n");
15677                 return -EIO;
15678         }
15679
15680         return 0;
15681 }
15682
15683 struct intel_display_error_state {
15684
15685         u32 power_well_driver;
15686
15687         int num_transcoders;
15688
15689         struct intel_cursor_error_state {
15690                 u32 control;
15691                 u32 position;
15692                 u32 base;
15693                 u32 size;
15694         } cursor[I915_MAX_PIPES];
15695
15696         struct intel_pipe_error_state {
15697                 bool power_domain_on;
15698                 u32 source;
15699                 u32 stat;
15700         } pipe[I915_MAX_PIPES];
15701
15702         struct intel_plane_error_state {
15703                 u32 control;
15704                 u32 stride;
15705                 u32 size;
15706                 u32 pos;
15707                 u32 addr;
15708                 u32 surface;
15709                 u32 tile_offset;
15710         } plane[I915_MAX_PIPES];
15711
15712         struct intel_transcoder_error_state {
15713                 bool power_domain_on;
15714                 enum transcoder cpu_transcoder;
15715
15716                 u32 conf;
15717
15718                 u32 htotal;
15719                 u32 hblank;
15720                 u32 hsync;
15721                 u32 vtotal;
15722                 u32 vblank;
15723                 u32 vsync;
15724         } transcoder[4];
15725 };
15726
15727 struct intel_display_error_state *
15728 intel_display_capture_error_state(struct drm_device *dev)
15729 {
15730         struct drm_i915_private *dev_priv = dev->dev_private;
15731         struct intel_display_error_state *error;
15732         int transcoders[] = {
15733                 TRANSCODER_A,
15734                 TRANSCODER_B,
15735                 TRANSCODER_C,
15736                 TRANSCODER_EDP,
15737         };
15738         int i;
15739
15740         if (INTEL_INFO(dev)->num_pipes == 0)
15741                 return NULL;
15742
15743         error = kzalloc(sizeof(*error), GFP_ATOMIC);
15744         if (error == NULL)
15745                 return NULL;
15746
15747         if (IS_HASWELL(dev) || IS_BROADWELL(dev))
15748                 error->power_well_driver = I915_READ(HSW_PWR_WELL_DRIVER);
15749
15750         for_each_pipe(dev_priv, i) {
15751                 error->pipe[i].power_domain_on =
15752                         __intel_display_power_is_enabled(dev_priv,
15753                                                          POWER_DOMAIN_PIPE(i));
15754                 if (!error->pipe[i].power_domain_on)
15755                         continue;
15756
15757                 error->cursor[i].control = I915_READ(CURCNTR(i));
15758                 error->cursor[i].position = I915_READ(CURPOS(i));
15759                 error->cursor[i].base = I915_READ(CURBASE(i));
15760
15761                 error->plane[i].control = I915_READ(DSPCNTR(i));
15762                 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
15763                 if (INTEL_INFO(dev)->gen <= 3) {
15764                         error->plane[i].size = I915_READ(DSPSIZE(i));
15765                         error->plane[i].pos = I915_READ(DSPPOS(i));
15766                 }
15767                 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
15768                         error->plane[i].addr = I915_READ(DSPADDR(i));
15769                 if (INTEL_INFO(dev)->gen >= 4) {
15770                         error->plane[i].surface = I915_READ(DSPSURF(i));
15771                         error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
15772                 }
15773
15774                 error->pipe[i].source = I915_READ(PIPESRC(i));
15775
15776                 if (HAS_GMCH_DISPLAY(dev))
15777                         error->pipe[i].stat = I915_READ(PIPESTAT(i));
15778         }
15779
15780         error->num_transcoders = INTEL_INFO(dev)->num_pipes;
15781         if (HAS_DDI(dev_priv->dev))
15782                 error->num_transcoders++; /* Account for eDP. */
15783
15784         for (i = 0; i < error->num_transcoders; i++) {
15785                 enum transcoder cpu_transcoder = transcoders[i];
15786
15787                 error->transcoder[i].power_domain_on =
15788                         __intel_display_power_is_enabled(dev_priv,
15789                                 POWER_DOMAIN_TRANSCODER(cpu_transcoder));
15790                 if (!error->transcoder[i].power_domain_on)
15791                         continue;
15792
15793                 error->transcoder[i].cpu_transcoder = cpu_transcoder;
15794
15795                 error->transcoder[i].conf = I915_READ(PIPECONF(cpu_transcoder));
15796                 error->transcoder[i].htotal = I915_READ(HTOTAL(cpu_transcoder));
15797                 error->transcoder[i].hblank = I915_READ(HBLANK(cpu_transcoder));
15798                 error->transcoder[i].hsync = I915_READ(HSYNC(cpu_transcoder));
15799                 error->transcoder[i].vtotal = I915_READ(VTOTAL(cpu_transcoder));
15800                 error->transcoder[i].vblank = I915_READ(VBLANK(cpu_transcoder));
15801                 error->transcoder[i].vsync = I915_READ(VSYNC(cpu_transcoder));
15802         }
15803
15804         return error;
15805 }
15806
15807 #define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__)
15808
15809 void
15810 intel_display_print_error_state(struct drm_i915_error_state_buf *m,
15811                                 struct drm_device *dev,
15812                                 struct intel_display_error_state *error)
15813 {
15814         struct drm_i915_private *dev_priv = dev->dev_private;
15815         int i;
15816
15817         if (!error)
15818                 return;
15819
15820         err_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev)->num_pipes);
15821         if (IS_HASWELL(dev) || IS_BROADWELL(dev))
15822                 err_printf(m, "PWR_WELL_CTL2: %08x\n",
15823                            error->power_well_driver);
15824         for_each_pipe(dev_priv, i) {
15825                 err_printf(m, "Pipe [%d]:\n", i);
15826                 err_printf(m, "  Power: %s\n",
15827                            error->pipe[i].power_domain_on ? "on" : "off");
15828                 err_printf(m, "  SRC: %08x\n", error->pipe[i].source);
15829                 err_printf(m, "  STAT: %08x\n", error->pipe[i].stat);
15830
15831                 err_printf(m, "Plane [%d]:\n", i);
15832                 err_printf(m, "  CNTR: %08x\n", error->plane[i].control);
15833                 err_printf(m, "  STRIDE: %08x\n", error->plane[i].stride);
15834                 if (INTEL_INFO(dev)->gen <= 3) {
15835                         err_printf(m, "  SIZE: %08x\n", error->plane[i].size);
15836                         err_printf(m, "  POS: %08x\n", error->plane[i].pos);
15837                 }
15838                 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
15839                         err_printf(m, "  ADDR: %08x\n", error->plane[i].addr);
15840                 if (INTEL_INFO(dev)->gen >= 4) {
15841                         err_printf(m, "  SURF: %08x\n", error->plane[i].surface);
15842                         err_printf(m, "  TILEOFF: %08x\n", error->plane[i].tile_offset);
15843                 }
15844
15845                 err_printf(m, "Cursor [%d]:\n", i);
15846                 err_printf(m, "  CNTR: %08x\n", error->cursor[i].control);
15847                 err_printf(m, "  POS: %08x\n", error->cursor[i].position);
15848                 err_printf(m, "  BASE: %08x\n", error->cursor[i].base);
15849         }
15850
15851         for (i = 0; i < error->num_transcoders; i++) {
15852                 err_printf(m, "CPU transcoder: %c\n",
15853                            transcoder_name(error->transcoder[i].cpu_transcoder));
15854                 err_printf(m, "  Power: %s\n",
15855                            error->transcoder[i].power_domain_on ? "on" : "off");
15856                 err_printf(m, "  CONF: %08x\n", error->transcoder[i].conf);
15857                 err_printf(m, "  HTOTAL: %08x\n", error->transcoder[i].htotal);
15858                 err_printf(m, "  HBLANK: %08x\n", error->transcoder[i].hblank);
15859                 err_printf(m, "  HSYNC: %08x\n", error->transcoder[i].hsync);
15860                 err_printf(m, "  VTOTAL: %08x\n", error->transcoder[i].vtotal);
15861                 err_printf(m, "  VBLANK: %08x\n", error->transcoder[i].vblank);
15862                 err_printf(m, "  VSYNC: %08x\n", error->transcoder[i].vsync);
15863         }
15864 }
15865
15866 void intel_modeset_preclose(struct drm_device *dev, struct drm_file *file)
15867 {
15868         struct intel_crtc *crtc;
15869
15870         for_each_intel_crtc(dev, crtc) {
15871                 struct intel_unpin_work *work;
15872
15873                 spin_lock_irq(&dev->event_lock);
15874
15875                 work = crtc->unpin_work;
15876
15877                 if (work && work->event &&
15878                     work->event->base.file_priv == file) {
15879                         kfree(work->event);
15880                         work->event = NULL;
15881                 }
15882
15883                 spin_unlock_irq(&dev->event_lock);
15884         }
15885 }