drivers/gpu/drm/i915/intel_ringbuffer.c

   1 /*
   2  * Copyright © 2008-2010 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *    Eric Anholt <[email protected]>
  25  *    Zou Nan hai <[email protected]>
  26  *    Xiang Hai hao<[email protected]>
  27  *
  28  */
  29
  30 #include <drm/drmP.h>
  31 #include "i915_drv.h"
  32 #include <drm/i915_drm.h>
  33 #include "i915_trace.h"
  34 #include "intel_drv.h"
  35
  36 bool
  37 intel_ring_initialized(struct intel_engine_cs *ring)
  38 {
  39         struct drm_device *dev = ring->dev;
  40
  41         if (!dev)
  42                 return false;
  43
  44         if (i915.enable_execlists) {
  45                 struct intel_context *dctx = ring->default_context;
  46                 struct intel_ringbuffer *ringbuf = dctx->engine[ring->id].ringbuf;
  47
  48                 return ringbuf->obj;
  49         } else
  50                 return ring->buffer && ring->buffer->obj;
  51 }
  52
  53 int __intel_ring_space(int head, int tail, int size)
  54 {
  55         int space = head - tail;
  56         if (space <= 0)
  57                 space += size;
  58         return space - I915_RING_FREE_SPACE;
  59 }
  60
  61 void intel_ring_update_space(struct intel_ringbuffer *ringbuf)
  62 {
  63         if (ringbuf->last_retired_head != -1) {
  64                 ringbuf->head = ringbuf->last_retired_head;
  65                 ringbuf->last_retired_head = -1;
  66         }
  67
  68         ringbuf->space = __intel_ring_space(ringbuf->head & HEAD_ADDR,
  69                                             ringbuf->tail, ringbuf->size);
  70 }
  71
  72 int intel_ring_space(struct intel_ringbuffer *ringbuf)
  73 {
  74         intel_ring_update_space(ringbuf);
  75         return ringbuf->space;
  76 }
  77
  78 bool intel_ring_stopped(struct intel_engine_cs *ring)
  79 {
  80         struct drm_i915_private *dev_priv = ring->dev->dev_private;
  81         return dev_priv->gpu_error.stop_rings & intel_ring_flag(ring);
  82 }
  83
  84 void __intel_ring_advance(struct intel_engine_cs *ring)
  85 {
  86         struct intel_ringbuffer *ringbuf = ring->buffer;
  87         ringbuf->tail &= ringbuf->size - 1;
  88         if (intel_ring_stopped(ring))
  89                 return;
  90         ring->write_tail(ring, ringbuf->tail);
  91 }
  92
  93 static int
  94 gen2_render_ring_flush(struct intel_engine_cs *ring,
  95                        u32      invalidate_domains,
  96                        u32      flush_domains)
  97 {
  98         u32 cmd;
  99         int ret;
 100
 101         cmd = MI_FLUSH;
 102         if (((invalidate_domains|flush_domains) & I915_GEM_DOMAIN_RENDER) == 0)
 103                 cmd |= MI_NO_WRITE_FLUSH;
 104
 105         if (invalidate_domains & I915_GEM_DOMAIN_SAMPLER)
 106                 cmd |= MI_READ_FLUSH;
 107
 108         ret = intel_ring_begin(ring, 2);
 109         if (ret)
 110                 return ret;
 111
 112         intel_ring_emit(ring, cmd);
 113         intel_ring_emit(ring, MI_NOOP);
 114         intel_ring_advance(ring);
 115
 116         return 0;
 117 }
 118
 119 static int
 120 gen4_render_ring_flush(struct intel_engine_cs *ring,
 121                        u32      invalidate_domains,
 122                        u32      flush_domains)
 123 {
 124         struct drm_device *dev = ring->dev;
 125         u32 cmd;
 126         int ret;
 127
 128         /*
 129          * read/write caches:
 130          *
 131          * I915_GEM_DOMAIN_RENDER is always invalidated, but is
 132          * only flushed if MI_NO_WRITE_FLUSH is unset.  On 965, it is
 133          * also flushed at 2d versus 3d pipeline switches.
 134          *
 135          * read-only caches:
 136          *
 137          * I915_GEM_DOMAIN_SAMPLER is flushed on pre-965 if
 138          * MI_READ_FLUSH is set, and is always flushed on 965.
 139          *
 140          * I915_GEM_DOMAIN_COMMAND may not exist?
 141          *
 142          * I915_GEM_DOMAIN_INSTRUCTION, which exists on 965, is
 143          * invalidated when MI_EXE_FLUSH is set.
 144          *
 145          * I915_GEM_DOMAIN_VERTEX, which exists on 965, is
 146          * invalidated with every MI_FLUSH.
 147          *
 148          * TLBs:
 149          *
 150          * On 965, TLBs associated with I915_GEM_DOMAIN_COMMAND
 151          * and I915_GEM_DOMAIN_CPU in are invalidated at PTE write and
 152          * I915_GEM_DOMAIN_RENDER and I915_GEM_DOMAIN_SAMPLER
 153          * are flushed at any MI_FLUSH.
 154          */
 155
 156         cmd = MI_FLUSH | MI_NO_WRITE_FLUSH;
 157         if ((invalidate_domains|flush_domains) & I915_GEM_DOMAIN_RENDER)
 158                 cmd &= ~MI_NO_WRITE_FLUSH;
 159         if (invalidate_domains & I915_GEM_DOMAIN_INSTRUCTION)
 160                 cmd |= MI_EXE_FLUSH;
 161
 162         if (invalidate_domains & I915_GEM_DOMAIN_COMMAND &&
 163             (IS_G4X(dev) || IS_GEN5(dev)))
 164                 cmd |= MI_INVALIDATE_ISP;
 165
 166         ret = intel_ring_begin(ring, 2);
 167         if (ret)
 168                 return ret;
 169
 170         intel_ring_emit(ring, cmd);
 171         intel_ring_emit(ring, MI_NOOP);
 172         intel_ring_advance(ring);
 173
 174         return 0;
 175 }
 176
 177 /**
 178  * Emits a PIPE_CONTROL with a non-zero post-sync operation, for
 179  * implementing two workarounds on gen6.  From section 1.4.7.1
 180  * "PIPE_CONTROL" of the Sandy Bridge PRM volume 2 part 1:
 181  *
 182  * [DevSNB-C+{W/A}] Before any depth stall flush (including those
 183  * produced by non-pipelined state commands), software needs to first
 184  * send a PIPE_CONTROL with no bits set except Post-Sync Operation !=
 185  * 0.
 186  *
 187  * [Dev-SNB{W/A}]: Before a PIPE_CONTROL with Write Cache Flush Enable
 188  * =1, a PIPE_CONTROL with any non-zero post-sync-op is required.
 189  *
 190  * And the workaround for these two requires this workaround first:
 191  *
 192  * [Dev-SNB{W/A}]: Pipe-control with CS-stall bit set must be sent
 193  * BEFORE the pipe-control with a post-sync op and no write-cache
 194  * flushes.
 195  *
 196  * And this last workaround is tricky because of the requirements on
 197  * that bit.  From section 1.4.7.2.3 "Stall" of the Sandy Bridge PRM
 198  * volume 2 part 1:
 199  *
 200  *     "1 of the following must also be set:
 201  *      - Render Target Cache Flush Enable ([12] of DW1)
 202  *      - Depth Cache Flush Enable ([0] of DW1)
 203  *      - Stall at Pixel Scoreboard ([1] of DW1)
 204  *      - Depth Stall ([13] of DW1)
 205  *      - Post-Sync Operation ([13] of DW1)
 206  *      - Notify Enable ([8] of DW1)"
 207  *
 208  * The cache flushes require the workaround flush that triggered this
 209  * one, so we can't use it.  Depth stall would trigger the same.
 210  * Post-sync nonzero is what triggered this second workaround, so we
 211  * can't use that one either.  Notify enable is IRQs, which aren't
 212  * really our business.  That leaves only stall at scoreboard.
 213  */
 214 static int
 215 intel_emit_post_sync_nonzero_flush(struct intel_engine_cs *ring)
 216 {
 217         u32 scratch_addr = ring->scratch.gtt_offset + 2 * CACHELINE_BYTES;
 218         int ret;
 219
 220
 221         ret = intel_ring_begin(ring, 6);
 222         if (ret)
 223                 return ret;
 224
 225         intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(5));
 226         intel_ring_emit(ring, PIPE_CONTROL_CS_STALL |
 227                         PIPE_CONTROL_STALL_AT_SCOREBOARD);
 228         intel_ring_emit(ring, scratch_addr | PIPE_CONTROL_GLOBAL_GTT); /* address */
 229         intel_ring_emit(ring, 0); /* low dword */
 230         intel_ring_emit(ring, 0); /* high dword */
 231         intel_ring_emit(ring, MI_NOOP);
 232         intel_ring_advance(ring);
 233
 234         ret = intel_ring_begin(ring, 6);
 235         if (ret)
 236                 return ret;
 237
 238         intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(5));
 239         intel_ring_emit(ring, PIPE_CONTROL_QW_WRITE);
 240         intel_ring_emit(ring, scratch_addr | PIPE_CONTROL_GLOBAL_GTT); /* address */
 241         intel_ring_emit(ring, 0);
 242         intel_ring_emit(ring, 0);
 243         intel_ring_emit(ring, MI_NOOP);
 244         intel_ring_advance(ring);
 245
 246         return 0;
 247 }
 248
 249 static int
 250 gen6_render_ring_flush(struct intel_engine_cs *ring,
 251                          u32 invalidate_domains, u32 flush_domains)
 252 {
 253         u32 flags = 0;
 254         u32 scratch_addr = ring->scratch.gtt_offset + 2 * CACHELINE_BYTES;
 255         int ret;
 256
 257         /* Force SNB workarounds for PIPE_CONTROL flushes */
 258         ret = intel_emit_post_sync_nonzero_flush(ring);
 259         if (ret)
 260                 return ret;
 261
 262         /* Just flush everything.  Experiments have shown that reducing the
 263          * number of bits based on the write domains has little performance
 264          * impact.
 265          */
 266         if (flush_domains) {
 267                 flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH;
 268                 flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH;
 269                 /*
 270                  * Ensure that any following seqno writes only happen
 271                  * when the render cache is indeed flushed.
 272                  */
 273                 flags |= PIPE_CONTROL_CS_STALL;
 274         }
 275         if (invalidate_domains) {
 276                 flags |= PIPE_CONTROL_TLB_INVALIDATE;
 277                 flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE;
 278                 flags |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE;
 279                 flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE;
 280                 flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE;
 281                 flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE;
 282                 /*
 283                  * TLB invalidate requires a post-sync write.
 284                  */
 285                 flags |= PIPE_CONTROL_QW_WRITE | PIPE_CONTROL_CS_STALL;
 286         }
 287
 288         ret = intel_ring_begin(ring, 4);
 289         if (ret)
 290                 return ret;
 291
 292         intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4));
 293         intel_ring_emit(ring, flags);
 294         intel_ring_emit(ring, scratch_addr | PIPE_CONTROL_GLOBAL_GTT);
 295         intel_ring_emit(ring, 0);
 296         intel_ring_advance(ring);
 297
 298         return 0;
 299 }
 300
 301 static int
 302 gen7_render_ring_cs_stall_wa(struct intel_engine_cs *ring)
 303 {
 304         int ret;
 305
 306         ret = intel_ring_begin(ring, 4);
 307         if (ret)
 308                 return ret;
 309
 310         intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4));
 311         intel_ring_emit(ring, PIPE_CONTROL_CS_STALL |
 312                               PIPE_CONTROL_STALL_AT_SCOREBOARD);
 313         intel_ring_emit(ring, 0);
 314         intel_ring_emit(ring, 0);
 315         intel_ring_advance(ring);
 316
 317         return 0;
 318 }
 319
 320 static int gen7_ring_fbc_flush(struct intel_engine_cs *ring, u32 value)
 321 {
 322         int ret;
 323
 324         if (!ring->fbc_dirty)
 325                 return 0;
 326
 327         ret = intel_ring_begin(ring, 6);
 328         if (ret)
 329                 return ret;
 330         /* WaFbcNukeOn3DBlt:ivb/hsw */
 331         intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
 332         intel_ring_emit(ring, MSG_FBC_REND_STATE);
 333         intel_ring_emit(ring, value);
 334         intel_ring_emit(ring, MI_STORE_REGISTER_MEM(1) | MI_SRM_LRM_GLOBAL_GTT);
 335         intel_ring_emit(ring, MSG_FBC_REND_STATE);
 336         intel_ring_emit(ring, ring->scratch.gtt_offset + 256);
 337         intel_ring_advance(ring);
 338
 339         ring->fbc_dirty = false;
 340         return 0;
 341 }
 342
 343 static int
 344 gen7_render_ring_flush(struct intel_engine_cs *ring,
 345                        u32 invalidate_domains, u32 flush_domains)
 346 {
 347         u32 flags = 0;
 348         u32 scratch_addr = ring->scratch.gtt_offset + 2 * CACHELINE_BYTES;
 349         int ret;
 350
 351         /*
 352          * Ensure that any following seqno writes only happen when the render
 353          * cache is indeed flushed.
 354          *
 355          * Workaround: 4th PIPE_CONTROL command (except the ones with only
 356          * read-cache invalidate bits set) must have the CS_STALL bit set. We
 357          * don't try to be clever and just set it unconditionally.
 358          */
 359         flags |= PIPE_CONTROL_CS_STALL;
 360
 361         /* Just flush everything.  Experiments have shown that reducing the
 362          * number of bits based on the write domains has little performance
 363          * impact.
 364          */
 365         if (flush_domains) {
 366                 flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH;
 367                 flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH;
 368         }
 369         if (invalidate_domains) {
 370                 flags |= PIPE_CONTROL_TLB_INVALIDATE;
 371                 flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE;
 372                 flags |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE;
 373                 flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE;
 374                 flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE;
 375                 flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE;
 376                 flags |= PIPE_CONTROL_MEDIA_STATE_CLEAR;
 377                 /*
 378                  * TLB invalidate requires a post-sync write.
 379                  */
 380                 flags |= PIPE_CONTROL_QW_WRITE;
 381                 flags |= PIPE_CONTROL_GLOBAL_GTT_IVB;
 382
 383                 flags |= PIPE_CONTROL_STALL_AT_SCOREBOARD;
 384
 385                 /* Workaround: we must issue a pipe_control with CS-stall bit
 386                  * set before a pipe_control command that has the state cache
 387                  * invalidate bit set. */
 388                 gen7_render_ring_cs_stall_wa(ring);
 389         }
 390
 391         ret = intel_ring_begin(ring, 4);
 392         if (ret)
 393                 return ret;
 394
 395         intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4));
 396         intel_ring_emit(ring, flags);
 397         intel_ring_emit(ring, scratch_addr);
 398         intel_ring_emit(ring, 0);
 399         intel_ring_advance(ring);
 400
 401         if (!invalidate_domains && flush_domains)
 402                 return gen7_ring_fbc_flush(ring, FBC_REND_NUKE);
 403
 404         return 0;
 405 }
 406
 407 static int
 408 gen8_emit_pipe_control(struct intel_engine_cs *ring,
 409                        u32 flags, u32 scratch_addr)
 410 {
 411         int ret;
 412
 413         ret = intel_ring_begin(ring, 6);
 414         if (ret)
 415                 return ret;
 416
 417         intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(6));
 418         intel_ring_emit(ring, flags);
 419         intel_ring_emit(ring, scratch_addr);
 420         intel_ring_emit(ring, 0);
 421         intel_ring_emit(ring, 0);
 422         intel_ring_emit(ring, 0);
 423         intel_ring_advance(ring);
 424
 425         return 0;
 426 }
 427
 428 static int
 429 gen8_render_ring_flush(struct intel_engine_cs *ring,
 430                        u32 invalidate_domains, u32 flush_domains)
 431 {
 432         u32 flags = 0;
 433         u32 scratch_addr = ring->scratch.gtt_offset + 2 * CACHELINE_BYTES;
 434         int ret;
 435
 436         flags |= PIPE_CONTROL_CS_STALL;
 437
 438         if (flush_domains) {
 439                 flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH;
 440                 flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH;
 441         }
 442         if (invalidate_domains) {
 443                 flags |= PIPE_CONTROL_TLB_INVALIDATE;
 444                 flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE;
 445                 flags |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE;
 446                 flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE;
 447                 flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE;
 448                 flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE;
 449                 flags |= PIPE_CONTROL_QW_WRITE;
 450                 flags |= PIPE_CONTROL_GLOBAL_GTT_IVB;
 451
 452                 /* WaCsStallBeforeStateCacheInvalidate:bdw,chv */
 453                 ret = gen8_emit_pipe_control(ring,
 454                                              PIPE_CONTROL_CS_STALL |
 455                                              PIPE_CONTROL_STALL_AT_SCOREBOARD,
 456                                              0);
 457                 if (ret)
 458                         return ret;
 459         }
 460
 461         ret = gen8_emit_pipe_control(ring, flags, scratch_addr);
 462         if (ret)
 463                 return ret;
 464
 465         if (!invalidate_domains && flush_domains)
 466                 return gen7_ring_fbc_flush(ring, FBC_REND_NUKE);
 467
 468         return 0;
 469 }
 470
 471 static void ring_write_tail(struct intel_engine_cs *ring,
 472                             u32 value)
 473 {
 474         struct drm_i915_private *dev_priv = ring->dev->dev_private;
 475         I915_WRITE_TAIL(ring, value);
 476 }
 477
 478 u64 intel_ring_get_active_head(struct intel_engine_cs *ring)
 479 {
 480         struct drm_i915_private *dev_priv = ring->dev->dev_private;
 481         u64 acthd;
 482
 483         if (INTEL_INFO(ring->dev)->gen >= 8)
 484                 acthd = I915_READ64_2x32(RING_ACTHD(ring->mmio_base),
 485                                          RING_ACTHD_UDW(ring->mmio_base));
 486         else if (INTEL_INFO(ring->dev)->gen >= 4)
 487                 acthd = I915_READ(RING_ACTHD(ring->mmio_base));
 488         else
 489                 acthd = I915_READ(ACTHD);
 490
 491         return acthd;
 492 }
 493
 494 static void ring_setup_phys_status_page(struct intel_engine_cs *ring)
 495 {
 496         struct drm_i915_private *dev_priv = ring->dev->dev_private;
 497         u32 addr;
 498
 499         addr = dev_priv->status_page_dmah->busaddr;
 500         if (INTEL_INFO(ring->dev)->gen >= 4)
 501                 addr |= (dev_priv->status_page_dmah->busaddr >> 28) & 0xf0;
 502         I915_WRITE(HWS_PGA, addr);
 503 }
 504
 505 static bool stop_ring(struct intel_engine_cs *ring)
 506 {
 507         struct drm_i915_private *dev_priv = to_i915(ring->dev);
 508
 509         if (!IS_GEN2(ring->dev)) {
 510                 I915_WRITE_MODE(ring, _MASKED_BIT_ENABLE(STOP_RING));
 511                 if (wait_for((I915_READ_MODE(ring) & MODE_IDLE) != 0, 1000)) {
 512                         DRM_ERROR("%s : timed out trying to stop ring\n", ring->name);
 513                         /* Sometimes we observe that the idle flag is not
 514                          * set even though the ring is empty. So double
 515                          * check before giving up.
 516                          */
 517                         if (I915_READ_HEAD(ring) != I915_READ_TAIL(ring))
 518                                 return false;
 519                 }
 520         }
 521
 522         I915_WRITE_CTL(ring, 0);
 523         I915_WRITE_HEAD(ring, 0);
 524         ring->write_tail(ring, 0);
 525
 526         if (!IS_GEN2(ring->dev)) {
 527                 (void)I915_READ_CTL(ring);
 528                 I915_WRITE_MODE(ring, _MASKED_BIT_DISABLE(STOP_RING));
 529         }
 530
 531         return (I915_READ_HEAD(ring) & HEAD_ADDR) == 0;
 532 }
 533
 534 static int init_ring_common(struct intel_engine_cs *ring)
 535 {
 536         struct drm_device *dev = ring->dev;
 537         struct drm_i915_private *dev_priv = dev->dev_private;
 538         struct intel_ringbuffer *ringbuf = ring->buffer;
 539         struct drm_i915_gem_object *obj = ringbuf->obj;
 540         int ret = 0;
 541
 542         gen6_gt_force_wake_get(dev_priv, FORCEWAKE_ALL);
 543
 544         if (!stop_ring(ring)) {
 545                 /* G45 ring initialization often fails to reset head to zero */
 546                 DRM_DEBUG_KMS("%s head not reset to zero "
 547                               "ctl %08x head %08x tail %08x start %08x\n",
 548                               ring->name,
 549                               I915_READ_CTL(ring),
 550                               I915_READ_HEAD(ring),
 551                               I915_READ_TAIL(ring),
 552                               I915_READ_START(ring));
 553
 554                 if (!stop_ring(ring)) {
 555                         DRM_ERROR("failed to set %s head to zero "
 556                                   "ctl %08x head %08x tail %08x start %08x\n",
 557                                   ring->name,
 558                                   I915_READ_CTL(ring),
 559                                   I915_READ_HEAD(ring),
 560                                   I915_READ_TAIL(ring),
 561                                   I915_READ_START(ring));
 562                         ret = -EIO;
 563                         goto out;
 564                 }
 565         }
 566
 567         if (I915_NEED_GFX_HWS(dev))
 568                 intel_ring_setup_status_page(ring);
 569         else
 570                 ring_setup_phys_status_page(ring);
 571
 572         /* Enforce ordering by reading HEAD register back */
 573         I915_READ_HEAD(ring);
 574
 575         /* Initialize the ring. This must happen _after_ we've cleared the ring
 576          * registers with the above sequence (the readback of the HEAD registers
 577          * also enforces ordering), otherwise the hw might lose the new ring
 578          * register values. */
 579         I915_WRITE_START(ring, i915_gem_obj_ggtt_offset(obj));
 580
 581         /* WaClearRingBufHeadRegAtInit:ctg,elk */
 582         if (I915_READ_HEAD(ring))
 583                 DRM_DEBUG("%s initialization failed [head=%08x], fudging\n",
 584                           ring->name, I915_READ_HEAD(ring));
 585         I915_WRITE_HEAD(ring, 0);
 586         (void)I915_READ_HEAD(ring);
 587
 588         I915_WRITE_CTL(ring,
 589                         ((ringbuf->size - PAGE_SIZE) & RING_NR_PAGES)
 590                         | RING_VALID);
 591
 592         /* If the head is still not zero, the ring is dead */
 593         if (wait_for((I915_READ_CTL(ring) & RING_VALID) != 0 &&
 594                      I915_READ_START(ring) == i915_gem_obj_ggtt_offset(obj) &&
 595                      (I915_READ_HEAD(ring) & HEAD_ADDR) == 0, 50)) {
 596                 DRM_ERROR("%s initialization failed "
 597                           "ctl %08x (valid? %d) head %08x tail %08x start %08x [expected %08lx]\n",
 598                           ring->name,
 599                           I915_READ_CTL(ring), I915_READ_CTL(ring) & RING_VALID,
 600                           I915_READ_HEAD(ring), I915_READ_TAIL(ring),
 601                           I915_READ_START(ring), (unsigned long)i915_gem_obj_ggtt_offset(obj));
 602                 ret = -EIO;
 603                 goto out;
 604         }
 605
 606         ringbuf->last_retired_head = -1;
 607         ringbuf->head = I915_READ_HEAD(ring);
 608         ringbuf->tail = I915_READ_TAIL(ring) & TAIL_ADDR;
 609         intel_ring_update_space(ringbuf);
 610
 611         memset(&ring->hangcheck, 0, sizeof(ring->hangcheck));
 612
 613 out:
 614         gen6_gt_force_wake_put(dev_priv, FORCEWAKE_ALL);
 615
 616         return ret;
 617 }
 618
 619 void
 620 intel_fini_pipe_control(struct intel_engine_cs *ring)
 621 {
 622         struct drm_device *dev = ring->dev;
 623
 624         if (ring->scratch.obj == NULL)
 625                 return;
 626
 627         if (INTEL_INFO(dev)->gen >= 5) {
 628                 kunmap(sg_page(ring->scratch.obj->pages->sgl));
 629                 i915_gem_object_ggtt_unpin(ring->scratch.obj);
 630         }
 631
 632         drm_gem_object_unreference(&ring->scratch.obj->base);
 633         ring->scratch.obj = NULL;
 634 }
 635
 636 int
 637 intel_init_pipe_control(struct intel_engine_cs *ring)
 638 {
 639         int ret;
 640
 641         WARN_ON(ring->scratch.obj);
 642
 643         ring->scratch.obj = i915_gem_alloc_object(ring->dev, 4096);
 644         if (ring->scratch.obj == NULL) {
 645                 DRM_ERROR("Failed to allocate seqno page\n");
 646                 ret = -ENOMEM;
 647                 goto err;
 648         }
 649
 650         ret = i915_gem_object_set_cache_level(ring->scratch.obj, I915_CACHE_LLC);
 651         if (ret)
 652                 goto err_unref;
 653
 654         ret = i915_gem_obj_ggtt_pin(ring->scratch.obj, 4096, 0);
 655         if (ret)
 656                 goto err_unref;
 657
 658         ring->scratch.gtt_offset = i915_gem_obj_ggtt_offset(ring->scratch.obj);
 659         ring->scratch.cpu_page = kmap(sg_page(ring->scratch.obj->pages->sgl));
 660         if (ring->scratch.cpu_page == NULL) {
 661                 ret = -ENOMEM;
 662                 goto err_unpin;
 663         }
 664
 665         DRM_DEBUG_DRIVER("%s pipe control offset: 0x%08x\n",
 666                          ring->name, ring->scratch.gtt_offset);
 667         return 0;
 668
 669 err_unpin:
 670         i915_gem_object_ggtt_unpin(ring->scratch.obj);
 671 err_unref:
 672         drm_gem_object_unreference(&ring->scratch.obj->base);
 673 err:
 674         return ret;
 675 }
 676
 677 static int intel_ring_workarounds_emit(struct intel_engine_cs *ring,
 678                                        struct intel_context *ctx)
 679 {
 680         int ret, i;
 681         struct drm_device *dev = ring->dev;
 682         struct drm_i915_private *dev_priv = dev->dev_private;
 683         struct i915_workarounds *w = &dev_priv->workarounds;
 684
 685         if (WARN_ON_ONCE(w->count == 0))
 686                 return 0;
 687
 688         ring->gpu_caches_dirty = true;
 689         ret = intel_ring_flush_all_caches(ring);
 690         if (ret)
 691                 return ret;
 692
 693         ret = intel_ring_begin(ring, (w->count * 2 + 2));
 694         if (ret)
 695                 return ret;
 696
 697         intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(w->count));
 698         for (i = 0; i < w->count; i++) {
 699                 intel_ring_emit(ring, w->reg[i].addr);
 700                 intel_ring_emit(ring, w->reg[i].value);
 701         }
 702         intel_ring_emit(ring, MI_NOOP);
 703
 704         intel_ring_advance(ring);
 705
 706         ring->gpu_caches_dirty = true;
 707         ret = intel_ring_flush_all_caches(ring);
 708         if (ret)
 709                 return ret;
 710
 711         DRM_DEBUG_DRIVER("Number of Workarounds emitted: %d\n", w->count);
 712
 713         return 0;
 714 }
 715
 716 static int intel_rcs_ctx_init(struct intel_engine_cs *ring,
 717                               struct intel_context *ctx)
 718 {
 719         int ret;
 720
 721         ret = intel_ring_workarounds_emit(ring, ctx);
 722         if (ret != 0)
 723                 return ret;
 724
 725         ret = i915_gem_render_state_init(ring);
 726         if (ret)
 727                 DRM_ERROR("init render state: %d\n", ret);
 728
 729         return ret;
 730 }
 731
 732 static int wa_add(struct drm_i915_private *dev_priv,
 733                   const u32 addr, const u32 mask, const u32 val)
 734 {
 735         const u32 idx = dev_priv->workarounds.count;
 736
 737         if (WARN_ON(idx >= I915_MAX_WA_REGS))
 738                 return -ENOSPC;
 739
 740         dev_priv->workarounds.reg[idx].addr = addr;
 741         dev_priv->workarounds.reg[idx].value = val;
 742         dev_priv->workarounds.reg[idx].mask = mask;
 743
 744         dev_priv->workarounds.count++;
 745
 746         return 0;
 747 }
 748
 749 #define WA_REG(addr, mask, val) { \
 750                 const int r = wa_add(dev_priv, (addr), (mask), (val)); \
 751                 if (r) \
 752                         return r; \
 753         }
 754
 755 #define WA_SET_BIT_MASKED(addr, mask) \
 756         WA_REG(addr, (mask), _MASKED_BIT_ENABLE(mask))
 757
 758 #define WA_CLR_BIT_MASKED(addr, mask) \
 759         WA_REG(addr, (mask), _MASKED_BIT_DISABLE(mask))
 760
 761 #define WA_SET_FIELD_MASKED(addr, mask, value) \
 762         WA_REG(addr, mask, _MASKED_FIELD(mask, value))
 763
 764 #define WA_SET_BIT(addr, mask) WA_REG(addr, mask, I915_READ(addr) | (mask))
 765 #define WA_CLR_BIT(addr, mask) WA_REG(addr, mask, I915_READ(addr) & ~(mask))
 766
 767 #define WA_WRITE(addr, val) WA_REG(addr, 0xffffffff, val)
 768
 769 static int bdw_init_workarounds(struct intel_engine_cs *ring)
 770 {
 771         struct drm_device *dev = ring->dev;
 772         struct drm_i915_private *dev_priv = dev->dev_private;
 773
 774         /* WaDisablePartialInstShootdown:bdw */
 775         /* WaDisableThreadStallDopClockGating:bdw (pre-production) */
 776         WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN,
 777                           PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE |
 778                           STALL_DOP_GATING_DISABLE);
 779
 780         /* WaDisableDopClockGating:bdw */
 781         WA_SET_BIT_MASKED(GEN7_ROW_CHICKEN2,
 782                           DOP_CLOCK_GATING_DISABLE);
 783
 784         WA_SET_BIT_MASKED(HALF_SLICE_CHICKEN3,
 785                           GEN8_SAMPLER_POWER_BYPASS_DIS);
 786
 787         /* Use Force Non-Coherent whenever executing a 3D context. This is a
 788          * workaround for for a possible hang in the unlikely event a TLB
 789          * invalidation occurs during a PSD flush.
 790          */
 791         /* WaForceEnableNonCoherent:bdw */
 792         /* WaHdcDisableFetchWhenMasked:bdw */
 793         /* WaDisableFenceDestinationToSLM:bdw (GT3 pre-production) */
 794         WA_SET_BIT_MASKED(HDC_CHICKEN0,
 795                           HDC_FORCE_NON_COHERENT |
 796                           HDC_DONOT_FETCH_MEM_WHEN_MASKED |
 797                           (IS_BDW_GT3(dev) ? HDC_FENCE_DEST_SLM_DISABLE : 0));
 798
 799         /* Wa4x4STCOptimizationDisable:bdw */
 800         WA_SET_BIT_MASKED(CACHE_MODE_1,
 801                           GEN8_4x4_STC_OPTIMIZATION_DISABLE);
 802
 803         /*
 804          * BSpec recommends 8x4 when MSAA is used,
 805          * however in practice 16x4 seems fastest.
 806          *
 807          * Note that PS/WM thread counts depend on the WIZ hashing
 808          * disable bit, which we don't touch here, but it's good
 809          * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
 810          */
 811         WA_SET_FIELD_MASKED(GEN7_GT_MODE,
 812                             GEN6_WIZ_HASHING_MASK,
 813                             GEN6_WIZ_HASHING_16x4);
 814
 815         return 0;
 816 }
 817
 818 static int chv_init_workarounds(struct intel_engine_cs *ring)
 819 {
 820         struct drm_device *dev = ring->dev;
 821         struct drm_i915_private *dev_priv = dev->dev_private;
 822
 823         /* WaDisablePartialInstShootdown:chv */
 824         /* WaDisableThreadStallDopClockGating:chv */
 825         WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN,
 826                           PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE |
 827                           STALL_DOP_GATING_DISABLE);
 828
 829         /* Use Force Non-Coherent whenever executing a 3D context. This is a
 830          * workaround for a possible hang in the unlikely event a TLB
 831          * invalidation occurs during a PSD flush.
 832          */
 833         /* WaForceEnableNonCoherent:chv */
 834         /* WaHdcDisableFetchWhenMasked:chv */
 835         WA_SET_BIT_MASKED(HDC_CHICKEN0,
 836                           HDC_FORCE_NON_COHERENT |
 837                           HDC_DONOT_FETCH_MEM_WHEN_MASKED);
 838
 839         return 0;
 840 }
 841
 842 int init_workarounds_ring(struct intel_engine_cs *ring)
 843 {
 844         struct drm_device *dev = ring->dev;
 845         struct drm_i915_private *dev_priv = dev->dev_private;
 846
 847         WARN_ON(ring->id != RCS);
 848
 849         dev_priv->workarounds.count = 0;
 850
 851         if (IS_BROADWELL(dev))
 852                 return bdw_init_workarounds(ring);
 853
 854         if (IS_CHERRYVIEW(dev))
 855                 return chv_init_workarounds(ring);
 856
 857         return 0;
 858 }
 859
 860 static int init_render_ring(struct intel_engine_cs *ring)
 861 {
 862         struct drm_device *dev = ring->dev;
 863         struct drm_i915_private *dev_priv = dev->dev_private;
 864         int ret = init_ring_common(ring);
 865         if (ret)
 866                 return ret;
 867
 868         /* WaTimedSingleVertexDispatch:cl,bw,ctg,elk,ilk,snb */
 869         if (INTEL_INFO(dev)->gen >= 4 && INTEL_INFO(dev)->gen < 7)
 870                 I915_WRITE(MI_MODE, _MASKED_BIT_ENABLE(VS_TIMER_DISPATCH));
 871
 872         /* We need to disable the AsyncFlip performance optimisations in order
 873          * to use MI_WAIT_FOR_EVENT within the CS. It should already be
 874          * programmed to '1' on all products.
 875          *
 876          * WaDisableAsyncFlipPerfMode:snb,ivb,hsw,vlv,bdw,chv
 877          */
 878         if (INTEL_INFO(dev)->gen >= 6 && INTEL_INFO(dev)->gen < 9)
 879                 I915_WRITE(MI_MODE, _MASKED_BIT_ENABLE(ASYNC_FLIP_PERF_DISABLE));
 880
 881         /* Required for the hardware to program scanline values for waiting */
 882         /* WaEnableFlushTlbInvalidationMode:snb */
 883         if (INTEL_INFO(dev)->gen == 6)
 884                 I915_WRITE(GFX_MODE,
 885                            _MASKED_BIT_ENABLE(GFX_TLB_INVALIDATE_EXPLICIT));
 886
 887         /* WaBCSVCSTlbInvalidationMode:ivb,vlv,hsw */
 888         if (IS_GEN7(dev))
 889                 I915_WRITE(GFX_MODE_GEN7,
 890                            _MASKED_BIT_ENABLE(GFX_TLB_INVALIDATE_EXPLICIT) |
 891                            _MASKED_BIT_ENABLE(GFX_REPLAY_MODE));
 892
 893         if (IS_GEN6(dev)) {
 894                 /* From the Sandybridge PRM, volume 1 part 3, page 24:
 895                  * "If this bit is set, STCunit will have LRA as replacement
 896                  *  policy. [...] This bit must be reset.  LRA replacement
 897                  *  policy is not supported."
 898                  */
 899                 I915_WRITE(CACHE_MODE_0,
 900                            _MASKED_BIT_DISABLE(CM0_STC_EVICT_DISABLE_LRA_SNB));
 901         }
 902
 903         if (INTEL_INFO(dev)->gen >= 6)
 904                 I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_FORCE_ORDERING));
 905
 906         if (HAS_L3_DPF(dev))
 907                 I915_WRITE_IMR(ring, ~GT_PARITY_ERROR(dev));
 908
 909         return init_workarounds_ring(ring);
 910 }
 911
 912 static void render_ring_cleanup(struct intel_engine_cs *ring)
 913 {
 914         struct drm_device *dev = ring->dev;
 915         struct drm_i915_private *dev_priv = dev->dev_private;
 916
 917         if (dev_priv->semaphore_obj) {
 918                 i915_gem_object_ggtt_unpin(dev_priv->semaphore_obj);
 919                 drm_gem_object_unreference(&dev_priv->semaphore_obj->base);
 920                 dev_priv->semaphore_obj = NULL;
 921         }
 922
 923         intel_fini_pipe_control(ring);
 924 }
 925
 926 static int gen8_rcs_signal(struct intel_engine_cs *signaller,
 927                            unsigned int num_dwords)
 928 {
 929 #define MBOX_UPDATE_DWORDS 8
 930         struct drm_device *dev = signaller->dev;
 931         struct drm_i915_private *dev_priv = dev->dev_private;
 932         struct intel_engine_cs *waiter;
 933         int i, ret, num_rings;
 934
 935         num_rings = hweight32(INTEL_INFO(dev)->ring_mask);
 936         num_dwords += (num_rings-1) * MBOX_UPDATE_DWORDS;
 937 #undef MBOX_UPDATE_DWORDS
 938
 939         ret = intel_ring_begin(signaller, num_dwords);
 940         if (ret)
 941                 return ret;
 942
 943         for_each_ring(waiter, dev_priv, i) {
 944                 u32 seqno;
 945                 u64 gtt_offset = signaller->semaphore.signal_ggtt[i];
 946                 if (gtt_offset == MI_SEMAPHORE_SYNC_INVALID)
 947                         continue;
 948
 949                 seqno = i915_gem_request_get_seqno(
 950                                            signaller->outstanding_lazy_request);
 951                 intel_ring_emit(signaller, GFX_OP_PIPE_CONTROL(6));
 952                 intel_ring_emit(signaller, PIPE_CONTROL_GLOBAL_GTT_IVB |
 953                                            PIPE_CONTROL_QW_WRITE |
 954                                            PIPE_CONTROL_FLUSH_ENABLE);
 955                 intel_ring_emit(signaller, lower_32_bits(gtt_offset));
 956                 intel_ring_emit(signaller, upper_32_bits(gtt_offset));
 957                 intel_ring_emit(signaller, seqno);
 958                 intel_ring_emit(signaller, 0);
 959                 intel_ring_emit(signaller, MI_SEMAPHORE_SIGNAL |
 960                                            MI_SEMAPHORE_TARGET(waiter->id));
 961                 intel_ring_emit(signaller, 0);
 962         }
 963
 964         return 0;
 965 }
 966
 967 static int gen8_xcs_signal(struct intel_engine_cs *signaller,
 968                            unsigned int num_dwords)
 969 {
 970 #define MBOX_UPDATE_DWORDS 6
 971         struct drm_device *dev = signaller->dev;
 972         struct drm_i915_private *dev_priv = dev->dev_private;
 973         struct intel_engine_cs *waiter;
 974         int i, ret, num_rings;
 975
 976         num_rings = hweight32(INTEL_INFO(dev)->ring_mask);
 977         num_dwords += (num_rings-1) * MBOX_UPDATE_DWORDS;
 978 #undef MBOX_UPDATE_DWORDS
 979
 980         ret = intel_ring_begin(signaller, num_dwords);
 981         if (ret)
 982                 return ret;
 983
 984         for_each_ring(waiter, dev_priv, i) {
 985                 u32 seqno;
 986                 u64 gtt_offset = signaller->semaphore.signal_ggtt[i];
 987                 if (gtt_offset == MI_SEMAPHORE_SYNC_INVALID)
 988                         continue;
 989
 990                 seqno = i915_gem_request_get_seqno(
 991                                            signaller->outstanding_lazy_request);
 992                 intel_ring_emit(signaller, (MI_FLUSH_DW + 1) |
 993                                            MI_FLUSH_DW_OP_STOREDW);
 994                 intel_ring_emit(signaller, lower_32_bits(gtt_offset) |
 995                                            MI_FLUSH_DW_USE_GTT);
 996                 intel_ring_emit(signaller, upper_32_bits(gtt_offset));
 997                 intel_ring_emit(signaller, seqno);
 998                 intel_ring_emit(signaller, MI_SEMAPHORE_SIGNAL |
 999                                            MI_SEMAPHORE_TARGET(waiter->id));
1000                 intel_ring_emit(signaller, 0);
1001         }
1002
1003         return 0;
1004 }
1005
1006 static int gen6_signal(struct intel_engine_cs *signaller,
1007                        unsigned int num_dwords)
1008 {
1009         struct drm_device *dev = signaller->dev;
1010         struct drm_i915_private *dev_priv = dev->dev_private;
1011         struct intel_engine_cs *useless;
1012         int i, ret, num_rings;
1013
1014 #define MBOX_UPDATE_DWORDS 3
1015         num_rings = hweight32(INTEL_INFO(dev)->ring_mask);
1016         num_dwords += round_up((num_rings-1) * MBOX_UPDATE_DWORDS, 2);
1017 #undef MBOX_UPDATE_DWORDS
1018
1019         ret = intel_ring_begin(signaller, num_dwords);
1020         if (ret)
1021                 return ret;
1022
1023         for_each_ring(useless, dev_priv, i) {
1024                 u32 mbox_reg = signaller->semaphore.mbox.signal[i];
1025                 if (mbox_reg != GEN6_NOSYNC) {
1026                         u32 seqno = i915_gem_request_get_seqno(
1027                                            signaller->outstanding_lazy_request);
1028                         intel_ring_emit(signaller, MI_LOAD_REGISTER_IMM(1));
1029                         intel_ring_emit(signaller, mbox_reg);
1030                         intel_ring_emit(signaller, seqno);
1031                 }
1032         }
1033
1034         /* If num_dwords was rounded, make sure the tail pointer is correct */
1035         if (num_rings % 2 == 0)
1036                 intel_ring_emit(signaller, MI_NOOP);
1037
1038         return 0;
1039 }
1040
1041 /**
1042  * gen6_add_request - Update the semaphore mailbox registers
1043  *
1044  * @ring - ring that is adding a request
1045  * @seqno - return seqno stuck into the ring
1046  *
1047  * Update the mailbox registers in the *other* rings with the current seqno.
1048  * This acts like a signal in the canonical semaphore.
1049  */
1050 static int
1051 gen6_add_request(struct intel_engine_cs *ring)
1052 {
1053         int ret;
1054
1055         if (ring->semaphore.signal)
1056                 ret = ring->semaphore.signal(ring, 4);
1057         else
1058                 ret = intel_ring_begin(ring, 4);
1059
1060         if (ret)
1061                 return ret;
1062
1063         intel_ring_emit(ring, MI_STORE_DWORD_INDEX);
1064         intel_ring_emit(ring, I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
1065         intel_ring_emit(ring,
1066                     i915_gem_request_get_seqno(ring->outstanding_lazy_request));
1067         intel_ring_emit(ring, MI_USER_INTERRUPT);
1068         __intel_ring_advance(ring);
1069
1070         return 0;
1071 }
1072
1073 static inline bool i915_gem_has_seqno_wrapped(struct drm_device *dev,
1074                                               u32 seqno)
1075 {
1076         struct drm_i915_private *dev_priv = dev->dev_private;
1077         return dev_priv->last_seqno < seqno;
1078 }
1079
1080 /**
1081  * intel_ring_sync - sync the waiter to the signaller on seqno
1082  *
1083  * @waiter - ring that is waiting
1084  * @signaller - ring which has, or will signal
1085  * @seqno - seqno which the waiter will block on
1086  */
1087
1088 static int
1089 gen8_ring_sync(struct intel_engine_cs *waiter,
1090                struct intel_engine_cs *signaller,
1091                u32 seqno)
1092 {
1093         struct drm_i915_private *dev_priv = waiter->dev->dev_private;
1094         int ret;
1095
1096         ret = intel_ring_begin(waiter, 4);
1097         if (ret)
1098                 return ret;
1099
1100         intel_ring_emit(waiter, MI_SEMAPHORE_WAIT |
1101                                 MI_SEMAPHORE_GLOBAL_GTT |
1102                                 MI_SEMAPHORE_POLL |
1103                                 MI_SEMAPHORE_SAD_GTE_SDD);
1104         intel_ring_emit(waiter, seqno);
1105         intel_ring_emit(waiter,
1106                         lower_32_bits(GEN8_WAIT_OFFSET(waiter, signaller->id)));
1107         intel_ring_emit(waiter,
1108                         upper_32_bits(GEN8_WAIT_OFFSET(waiter, signaller->id)));
1109         intel_ring_advance(waiter);
1110         return 0;
1111 }
1112
1113 static int
1114 gen6_ring_sync(struct intel_engine_cs *waiter,
1115                struct intel_engine_cs *signaller,
1116                u32 seqno)
1117 {
1118         u32 dw1 = MI_SEMAPHORE_MBOX |
1119                   MI_SEMAPHORE_COMPARE |
1120                   MI_SEMAPHORE_REGISTER;
1121         u32 wait_mbox = signaller->semaphore.mbox.wait[waiter->id];
1122         int ret;
1123
1124         /* Throughout all of the GEM code, seqno passed implies our current
1125          * seqno is >= the last seqno executed. However for hardware the
1126          * comparison is strictly greater than.
1127          */
1128         seqno -= 1;
1129
1130         WARN_ON(wait_mbox == MI_SEMAPHORE_SYNC_INVALID);
1131
1132         ret = intel_ring_begin(waiter, 4);
1133         if (ret)
1134                 return ret;
1135
1136         /* If seqno wrap happened, omit the wait with no-ops */
1137         if (likely(!i915_gem_has_seqno_wrapped(waiter->dev, seqno))) {
1138                 intel_ring_emit(waiter, dw1 | wait_mbox);
1139                 intel_ring_emit(waiter, seqno);
1140                 intel_ring_emit(waiter, 0);
1141                 intel_ring_emit(waiter, MI_NOOP);
1142         } else {
1143                 intel_ring_emit(waiter, MI_NOOP);
1144                 intel_ring_emit(waiter, MI_NOOP);
1145                 intel_ring_emit(waiter, MI_NOOP);
1146                 intel_ring_emit(waiter, MI_NOOP);
1147         }
1148         intel_ring_advance(waiter);
1149
1150         return 0;
1151 }
1152
1153 #define PIPE_CONTROL_FLUSH(ring__, addr__)                                      \
1154 do {                                                                    \
1155         intel_ring_emit(ring__, GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE |                \
1156                  PIPE_CONTROL_DEPTH_STALL);                             \
1157         intel_ring_emit(ring__, (addr__) | PIPE_CONTROL_GLOBAL_GTT);                    \
1158         intel_ring_emit(ring__, 0);                                                     \
1159         intel_ring_emit(ring__, 0);                                                     \
1160 } while (0)
1161
1162 static int
1163 pc_render_add_request(struct intel_engine_cs *ring)
1164 {
1165         u32 scratch_addr = ring->scratch.gtt_offset + 2 * CACHELINE_BYTES;
1166         int ret;
1167
1168         /* For Ironlake, MI_USER_INTERRUPT was deprecated and apparently
1169          * incoherent with writes to memory, i.e. completely fubar,
1170          * so we need to use PIPE_NOTIFY instead.
1171          *
1172          * However, we also need to workaround the qword write
1173          * incoherence by flushing the 6 PIPE_NOTIFY buffers out to
1174          * memory before requesting an interrupt.
1175          */
1176         ret = intel_ring_begin(ring, 32);
1177         if (ret)
1178                 return ret;
1179
1180         intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE |
1181                         PIPE_CONTROL_WRITE_FLUSH |
1182                         PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE);
1183         intel_ring_emit(ring, ring->scratch.gtt_offset | PIPE_CONTROL_GLOBAL_GTT);
1184         intel_ring_emit(ring,
1185                     i915_gem_request_get_seqno(ring->outstanding_lazy_request));
1186         intel_ring_emit(ring, 0);
1187         PIPE_CONTROL_FLUSH(ring, scratch_addr);
1188         scratch_addr += 2 * CACHELINE_BYTES; /* write to separate cachelines */
1189         PIPE_CONTROL_FLUSH(ring, scratch_addr);
1190         scratch_addr += 2 * CACHELINE_BYTES;
1191         PIPE_CONTROL_FLUSH(ring, scratch_addr);
1192         scratch_addr += 2 * CACHELINE_BYTES;
1193         PIPE_CONTROL_FLUSH(ring, scratch_addr);
1194         scratch_addr += 2 * CACHELINE_BYTES;
1195         PIPE_CONTROL_FLUSH(ring, scratch_addr);
1196         scratch_addr += 2 * CACHELINE_BYTES;
1197         PIPE_CONTROL_FLUSH(ring, scratch_addr);
1198
1199         intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE |
1200                         PIPE_CONTROL_WRITE_FLUSH |
1201                         PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE |
1202                         PIPE_CONTROL_NOTIFY);
1203         intel_ring_emit(ring, ring->scratch.gtt_offset | PIPE_CONTROL_GLOBAL_GTT);
1204         intel_ring_emit(ring,
1205                     i915_gem_request_get_seqno(ring->outstanding_lazy_request));
1206         intel_ring_emit(ring, 0);
1207         __intel_ring_advance(ring);
1208
1209         return 0;
1210 }
1211
1212 static u32
1213 gen6_ring_get_seqno(struct intel_engine_cs *ring, bool lazy_coherency)
1214 {
1215         /* Workaround to force correct ordering between irq and seqno writes on
1216          * ivb (and maybe also on snb) by reading from a CS register (like
1217          * ACTHD) before reading the status page. */
1218         if (!lazy_coherency) {
1219                 struct drm_i915_private *dev_priv = ring->dev->dev_private;
1220                 POSTING_READ(RING_ACTHD(ring->mmio_base));
1221         }
1222
1223         return intel_read_status_page(ring, I915_GEM_HWS_INDEX);
1224 }
1225
1226 static u32
1227 ring_get_seqno(struct intel_engine_cs *ring, bool lazy_coherency)
1228 {
1229         return intel_read_status_page(ring, I915_GEM_HWS_INDEX);
1230 }
1231
1232 static void
1233 ring_set_seqno(struct intel_engine_cs *ring, u32 seqno)
1234 {
1235         intel_write_status_page(ring, I915_GEM_HWS_INDEX, seqno);
1236 }
1237
1238 static u32
1239 pc_render_get_seqno(struct intel_engine_cs *ring, bool lazy_coherency)
1240 {
1241         return ring->scratch.cpu_page[0];
1242 }
1243
1244 static void
1245 pc_render_set_seqno(struct intel_engine_cs *ring, u32 seqno)
1246 {
1247         ring->scratch.cpu_page[0] = seqno;
1248 }
1249
1250 static bool
1251 gen5_ring_get_irq(struct intel_engine_cs *ring)
1252 {
1253         struct drm_device *dev = ring->dev;
1254         struct drm_i915_private *dev_priv = dev->dev_private;
1255         unsigned long flags;
1256
1257         if (WARN_ON(!intel_irqs_enabled(dev_priv)))
1258                 return false;
1259
1260         spin_lock_irqsave(&dev_priv->irq_lock, flags);
1261         if (ring->irq_refcount++ == 0)
1262                 gen5_enable_gt_irq(dev_priv, ring->irq_enable_mask);
1263         spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1264
1265         return true;
1266 }
1267
1268 static void
1269 gen5_ring_put_irq(struct intel_engine_cs *ring)
1270 {
1271         struct drm_device *dev = ring->dev;
1272         struct drm_i915_private *dev_priv = dev->dev_private;
1273         unsigned long flags;
1274
1275         spin_lock_irqsave(&dev_priv->irq_lock, flags);
1276         if (--ring->irq_refcount == 0)
1277                 gen5_disable_gt_irq(dev_priv, ring->irq_enable_mask);
1278         spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1279 }
1280
1281 static bool
1282 i9xx_ring_get_irq(struct intel_engine_cs *ring)
1283 {
1284         struct drm_device *dev = ring->dev;
1285         struct drm_i915_private *dev_priv = dev->dev_private;
1286         unsigned long flags;
1287
1288         if (!intel_irqs_enabled(dev_priv))
1289                 return false;
1290
1291         spin_lock_irqsave(&dev_priv->irq_lock, flags);
1292         if (ring->irq_refcount++ == 0) {
1293                 dev_priv->irq_mask &= ~ring->irq_enable_mask;
1294                 I915_WRITE(IMR, dev_priv->irq_mask);
1295                 POSTING_READ(IMR);
1296         }
1297         spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1298
1299         return true;
1300 }
1301
1302 static void
1303 i9xx_ring_put_irq(struct intel_engine_cs *ring)
1304 {
1305         struct drm_device *dev = ring->dev;
1306         struct drm_i915_private *dev_priv = dev->dev_private;
1307         unsigned long flags;
1308
1309         spin_lock_irqsave(&dev_priv->irq_lock, flags);
1310         if (--ring->irq_refcount == 0) {
1311                 dev_priv->irq_mask |= ring->irq_enable_mask;
1312                 I915_WRITE(IMR, dev_priv->irq_mask);
1313                 POSTING_READ(IMR);
1314         }
1315         spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1316 }
1317
1318 static bool
1319 i8xx_ring_get_irq(struct intel_engine_cs *ring)
1320 {
1321         struct drm_device *dev = ring->dev;
1322         struct drm_i915_private *dev_priv = dev->dev_private;
1323         unsigned long flags;
1324
1325         if (!intel_irqs_enabled(dev_priv))
1326                 return false;
1327
1328         spin_lock_irqsave(&dev_priv->irq_lock, flags);
1329         if (ring->irq_refcount++ == 0) {
1330                 dev_priv->irq_mask &= ~ring->irq_enable_mask;
1331                 I915_WRITE16(IMR, dev_priv->irq_mask);
1332                 POSTING_READ16(IMR);
1333         }
1334         spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1335
1336         return true;
1337 }
1338
1339 static void
1340 i8xx_ring_put_irq(struct intel_engine_cs *ring)
1341 {
1342         struct drm_device *dev = ring->dev;
1343         struct drm_i915_private *dev_priv = dev->dev_private;
1344         unsigned long flags;
1345
1346         spin_lock_irqsave(&dev_priv->irq_lock, flags);
1347         if (--ring->irq_refcount == 0) {
1348                 dev_priv->irq_mask |= ring->irq_enable_mask;
1349                 I915_WRITE16(IMR, dev_priv->irq_mask);
1350                 POSTING_READ16(IMR);
1351         }
1352         spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1353 }
1354
1355 void intel_ring_setup_status_page(struct intel_engine_cs *ring)
1356 {
1357         struct drm_device *dev = ring->dev;
1358         struct drm_i915_private *dev_priv = ring->dev->dev_private;
1359         u32 mmio = 0;
1360
1361         /* The ring status page addresses are no longer next to the rest of
1362          * the ring registers as of gen7.
1363          */
1364         if (IS_GEN7(dev)) {
1365                 switch (ring->id) {
1366                 case RCS:
1367                         mmio = RENDER_HWS_PGA_GEN7;
1368                         break;
1369                 case BCS:
1370                         mmio = BLT_HWS_PGA_GEN7;
1371                         break;
1372                 /*
1373                  * VCS2 actually doesn't exist on Gen7. Only shut up
1374                  * gcc switch check warning
1375                  */
1376                 case VCS2:
1377                 case VCS:
1378                         mmio = BSD_HWS_PGA_GEN7;
1379                         break;
1380                 case VECS:
1381                         mmio = VEBOX_HWS_PGA_GEN7;
1382                         break;
1383                 }
1384         } else if (IS_GEN6(ring->dev)) {
1385                 mmio = RING_HWS_PGA_GEN6(ring->mmio_base);
1386         } else {
1387                 /* XXX: gen8 returns to sanity */
1388                 mmio = RING_HWS_PGA(ring->mmio_base);
1389         }
1390
1391         I915_WRITE(mmio, (u32)ring->status_page.gfx_addr);
1392         POSTING_READ(mmio);
1393
1394         /*
1395          * Flush the TLB for this page
1396          *
1397          * FIXME: These two bits have disappeared on gen8, so a question
1398          * arises: do we still need this and if so how should we go about
1399          * invalidating the TLB?
1400          */
1401         if (INTEL_INFO(dev)->gen >= 6 && INTEL_INFO(dev)->gen < 8) {
1402                 u32 reg = RING_INSTPM(ring->mmio_base);
1403
1404                 /* ring should be idle before issuing a sync flush*/
1405                 WARN_ON((I915_READ_MODE(ring) & MODE_IDLE) == 0);
1406
1407                 I915_WRITE(reg,
1408                            _MASKED_BIT_ENABLE(INSTPM_TLB_INVALIDATE |
1409                                               INSTPM_SYNC_FLUSH));
1410                 if (wait_for((I915_READ(reg) & INSTPM_SYNC_FLUSH) == 0,
1411                              1000))
1412                         DRM_ERROR("%s: wait for SyncFlush to complete for TLB invalidation timed out\n",
1413                                   ring->name);
1414         }
1415 }
1416
1417 static int
1418 bsd_ring_flush(struct intel_engine_cs *ring,
1419                u32     invalidate_domains,
1420                u32     flush_domains)
1421 {
1422         int ret;
1423
1424         ret = intel_ring_begin(ring, 2);
1425         if (ret)
1426                 return ret;
1427
1428         intel_ring_emit(ring, MI_FLUSH);
1429         intel_ring_emit(ring, MI_NOOP);
1430         intel_ring_advance(ring);
1431         return 0;
1432 }
1433
1434 static int
1435 i9xx_add_request(struct intel_engine_cs *ring)
1436 {
1437         int ret;
1438
1439         ret = intel_ring_begin(ring, 4);
1440         if (ret)
1441                 return ret;
1442
1443         intel_ring_emit(ring, MI_STORE_DWORD_INDEX);
1444         intel_ring_emit(ring, I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
1445         intel_ring_emit(ring,
1446                     i915_gem_request_get_seqno(ring->outstanding_lazy_request));
1447         intel_ring_emit(ring, MI_USER_INTERRUPT);
1448         __intel_ring_advance(ring);
1449
1450         return 0;
1451 }
1452
1453 static bool
1454 gen6_ring_get_irq(struct intel_engine_cs *ring)
1455 {
1456         struct drm_device *dev = ring->dev;
1457         struct drm_i915_private *dev_priv = dev->dev_private;
1458         unsigned long flags;
1459
1460         if (WARN_ON(!intel_irqs_enabled(dev_priv)))
1461                 return false;
1462
1463         spin_lock_irqsave(&dev_priv->irq_lock, flags);
1464         if (ring->irq_refcount++ == 0) {
1465                 if (HAS_L3_DPF(dev) && ring->id == RCS)
1466                         I915_WRITE_IMR(ring,
1467                                        ~(ring->irq_enable_mask |
1468                                          GT_PARITY_ERROR(dev)));
1469                 else
1470                         I915_WRITE_IMR(ring, ~ring->irq_enable_mask);
1471                 gen5_enable_gt_irq(dev_priv, ring->irq_enable_mask);
1472         }
1473         spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1474
1475         return true;
1476 }
1477
1478 static void
1479 gen6_ring_put_irq(struct intel_engine_cs *ring)
1480 {
1481         struct drm_device *dev = ring->dev;
1482         struct drm_i915_private *dev_priv = dev->dev_private;
1483         unsigned long flags;
1484
1485         spin_lock_irqsave(&dev_priv->irq_lock, flags);
1486         if (--ring->irq_refcount == 0) {
1487                 if (HAS_L3_DPF(dev) && ring->id == RCS)
1488                         I915_WRITE_IMR(ring, ~GT_PARITY_ERROR(dev));
1489                 else
1490                         I915_WRITE_IMR(ring, ~0);
1491                 gen5_disable_gt_irq(dev_priv, ring->irq_enable_mask);
1492         }
1493         spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1494 }
1495
1496 static bool
1497 hsw_vebox_get_irq(struct intel_engine_cs *ring)
1498 {
1499         struct drm_device *dev = ring->dev;
1500         struct drm_i915_private *dev_priv = dev->dev_private;
1501         unsigned long flags;
1502
1503         if (WARN_ON(!intel_irqs_enabled(dev_priv)))
1504                 return false;
1505
1506         spin_lock_irqsave(&dev_priv->irq_lock, flags);
1507         if (ring->irq_refcount++ == 0) {
1508                 I915_WRITE_IMR(ring, ~ring->irq_enable_mask);
1509                 gen6_enable_pm_irq(dev_priv, ring->irq_enable_mask);
1510         }
1511         spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1512
1513         return true;
1514 }
1515
1516 static void
1517 hsw_vebox_put_irq(struct intel_engine_cs *ring)
1518 {
1519         struct drm_device *dev = ring->dev;
1520         struct drm_i915_private *dev_priv = dev->dev_private;
1521         unsigned long flags;
1522
1523         spin_lock_irqsave(&dev_priv->irq_lock, flags);
1524         if (--ring->irq_refcount == 0) {
1525                 I915_WRITE_IMR(ring, ~0);
1526                 gen6_disable_pm_irq(dev_priv, ring->irq_enable_mask);
1527         }
1528         spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1529 }
1530
1531 static bool
1532 gen8_ring_get_irq(struct intel_engine_cs *ring)
1533 {
1534         struct drm_device *dev = ring->dev;
1535         struct drm_i915_private *dev_priv = dev->dev_private;
1536         unsigned long flags;
1537
1538         if (WARN_ON(!intel_irqs_enabled(dev_priv)))
1539                 return false;
1540
1541         spin_lock_irqsave(&dev_priv->irq_lock, flags);
1542         if (ring->irq_refcount++ == 0) {
1543                 if (HAS_L3_DPF(dev) && ring->id == RCS) {
1544                         I915_WRITE_IMR(ring,
1545                                        ~(ring->irq_enable_mask |
1546                                          GT_RENDER_L3_PARITY_ERROR_INTERRUPT));
1547                 } else {
1548                         I915_WRITE_IMR(ring, ~ring->irq_enable_mask);
1549                 }
1550                 POSTING_READ(RING_IMR(ring->mmio_base));
1551         }
1552         spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1553
1554         return true;
1555 }
1556
1557 static void
1558 gen8_ring_put_irq(struct intel_engine_cs *ring)
1559 {
1560         struct drm_device *dev = ring->dev;
1561         struct drm_i915_private *dev_priv = dev->dev_private;
1562         unsigned long flags;
1563
1564         spin_lock_irqsave(&dev_priv->irq_lock, flags);
1565         if (--ring->irq_refcount == 0) {
1566                 if (HAS_L3_DPF(dev) && ring->id == RCS) {
1567                         I915_WRITE_IMR(ring,
1568                                        ~GT_RENDER_L3_PARITY_ERROR_INTERRUPT);
1569                 } else {
1570                         I915_WRITE_IMR(ring, ~0);
1571                 }
1572                 POSTING_READ(RING_IMR(ring->mmio_base));
1573         }
1574         spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1575 }
1576
1577 static int
1578 i965_dispatch_execbuffer(struct intel_engine_cs *ring,
1579                          u64 offset, u32 length,
1580                          unsigned flags)
1581 {
1582         int ret;
1583
1584         ret = intel_ring_begin(ring, 2);
1585         if (ret)
1586                 return ret;
1587
1588         intel_ring_emit(ring,
1589                         MI_BATCH_BUFFER_START |
1590                         MI_BATCH_GTT |
1591                         (flags & I915_DISPATCH_SECURE ? 0 : MI_BATCH_NON_SECURE_I965));
1592         intel_ring_emit(ring, offset);
1593         intel_ring_advance(ring);
1594
1595         return 0;
1596 }
1597
1598 /* Just userspace ABI convention to limit the wa batch bo to a resonable size */
1599 #define I830_BATCH_LIMIT (256*1024)
1600 #define I830_TLB_ENTRIES (2)
1601 #define I830_WA_SIZE max(I830_TLB_ENTRIES*4096, I830_BATCH_LIMIT)
1602 static int
1603 i830_dispatch_execbuffer(struct intel_engine_cs *ring,
1604                                 u64 offset, u32 len,
1605                                 unsigned flags)
1606 {
1607         u32 cs_offset = ring->scratch.gtt_offset;
1608         int ret;
1609
1610         ret = intel_ring_begin(ring, 6);
1611         if (ret)
1612                 return ret;
1613
1614         /* Evict the invalid PTE TLBs */
1615         intel_ring_emit(ring, COLOR_BLT_CMD | BLT_WRITE_RGBA);
1616         intel_ring_emit(ring, BLT_DEPTH_32 | BLT_ROP_COLOR_COPY | 4096);
1617         intel_ring_emit(ring, I830_TLB_ENTRIES << 16 | 4); /* load each page */
1618         intel_ring_emit(ring, cs_offset);
1619         intel_ring_emit(ring, 0xdeadbeef);
1620         intel_ring_emit(ring, MI_NOOP);
1621         intel_ring_advance(ring);
1622
1623         if ((flags & I915_DISPATCH_PINNED) == 0) {
1624                 if (len > I830_BATCH_LIMIT)
1625                         return -ENOSPC;
1626
1627                 ret = intel_ring_begin(ring, 6 + 2);
1628                 if (ret)
1629                         return ret;
1630
1631                 /* Blit the batch (which has now all relocs applied) to the
1632                  * stable batch scratch bo area (so that the CS never
1633                  * stumbles over its tlb invalidation bug) ...
1634                  */
1635                 intel_ring_emit(ring, SRC_COPY_BLT_CMD | BLT_WRITE_RGBA);
1636                 intel_ring_emit(ring, BLT_DEPTH_32 | BLT_ROP_SRC_COPY | 4096);
1637                 intel_ring_emit(ring, DIV_ROUND_UP(len, 4096) << 16 | 4096);
1638                 intel_ring_emit(ring, cs_offset);
1639                 intel_ring_emit(ring, 4096);
1640                 intel_ring_emit(ring, offset);
1641
1642                 intel_ring_emit(ring, MI_FLUSH);
1643                 intel_ring_emit(ring, MI_NOOP);
1644                 intel_ring_advance(ring);
1645
1646                 /* ... and execute it. */
1647                 offset = cs_offset;
1648         }
1649
1650         ret = intel_ring_begin(ring, 4);
1651         if (ret)
1652                 return ret;
1653
1654         intel_ring_emit(ring, MI_BATCH_BUFFER);
1655         intel_ring_emit(ring, offset | (flags & I915_DISPATCH_SECURE ? 0 : MI_BATCH_NON_SECURE));
1656         intel_ring_emit(ring, offset + len - 8);
1657         intel_ring_emit(ring, MI_NOOP);
1658         intel_ring_advance(ring);
1659
1660         return 0;
1661 }
1662
1663 static int
1664 i915_dispatch_execbuffer(struct intel_engine_cs *ring,
1665                          u64 offset, u32 len,
1666                          unsigned flags)
1667 {
1668         int ret;
1669
1670         ret = intel_ring_begin(ring, 2);
1671         if (ret)
1672                 return ret;
1673
1674         intel_ring_emit(ring, MI_BATCH_BUFFER_START | MI_BATCH_GTT);
1675         intel_ring_emit(ring, offset | (flags & I915_DISPATCH_SECURE ? 0 : MI_BATCH_NON_SECURE));
1676         intel_ring_advance(ring);
1677
1678         return 0;
1679 }
1680
1681 static void cleanup_status_page(struct intel_engine_cs *ring)
1682 {
1683         struct drm_i915_gem_object *obj;
1684
1685         obj = ring->status_page.obj;
1686         if (obj == NULL)
1687                 return;
1688
1689         kunmap(sg_page(obj->pages->sgl));
1690         i915_gem_object_ggtt_unpin(obj);
1691         drm_gem_object_unreference(&obj->base);
1692         ring->status_page.obj = NULL;
1693 }
1694
1695 static int init_status_page(struct intel_engine_cs *ring)
1696 {
1697         struct drm_i915_gem_object *obj;
1698
1699         if ((obj = ring->status_page.obj) == NULL) {
1700                 unsigned flags;
1701                 int ret;
1702
1703                 obj = i915_gem_alloc_object(ring->dev, 4096);
1704                 if (obj == NULL) {
1705                         DRM_ERROR("Failed to allocate status page\n");
1706                         return -ENOMEM;
1707                 }
1708
1709                 ret = i915_gem_object_set_cache_level(obj, I915_CACHE_LLC);
1710                 if (ret)
1711                         goto err_unref;
1712
1713                 flags = 0;
1714                 if (!HAS_LLC(ring->dev))
1715                         /* On g33, we cannot place HWS above 256MiB, so
1716                          * restrict its pinning to the low mappable arena.
1717                          * Though this restriction is not documented for
1718                          * gen4, gen5, or byt, they also behave similarly
1719                          * and hang if the HWS is placed at the top of the
1720                          * GTT. To generalise, it appears that all !llc
1721                          * platforms have issues with us placing the HWS
1722                          * above the mappable region (even though we never
1723                          * actualy map it).
1724                          */
1725                         flags |= PIN_MAPPABLE;
1726                 ret = i915_gem_obj_ggtt_pin(obj, 4096, flags);
1727                 if (ret) {
1728 err_unref:
1729                         drm_gem_object_unreference(&obj->base);
1730                         return ret;
1731                 }
1732
1733                 ring->status_page.obj = obj;
1734         }
1735
1736         ring->status_page.gfx_addr = i915_gem_obj_ggtt_offset(obj);
1737         ring->status_page.page_addr = kmap(sg_page(obj->pages->sgl));
1738         memset(ring->status_page.page_addr, 0, PAGE_SIZE);
1739
1740         DRM_DEBUG_DRIVER("%s hws offset: 0x%08x\n",
1741                         ring->name, ring->status_page.gfx_addr);
1742
1743         return 0;
1744 }
1745
1746 static int init_phys_status_page(struct intel_engine_cs *ring)
1747 {
1748         struct drm_i915_private *dev_priv = ring->dev->dev_private;
1749
1750         if (!dev_priv->status_page_dmah) {
1751                 dev_priv->status_page_dmah =
1752                         drm_pci_alloc(ring->dev, PAGE_SIZE, PAGE_SIZE);
1753                 if (!dev_priv->status_page_dmah)
1754                         return -ENOMEM;
1755         }
1756
1757         ring->status_page.page_addr = dev_priv->status_page_dmah->vaddr;
1758         memset(ring->status_page.page_addr, 0, PAGE_SIZE);
1759
1760         return 0;
1761 }
1762
1763 void intel_unpin_ringbuffer_obj(struct intel_ringbuffer *ringbuf)
1764 {
1765         iounmap(ringbuf->virtual_start);
1766         ringbuf->virtual_start = NULL;
1767         i915_gem_object_ggtt_unpin(ringbuf->obj);
1768 }
1769
1770 int intel_pin_and_map_ringbuffer_obj(struct drm_device *dev,
1771                                      struct intel_ringbuffer *ringbuf)
1772 {
1773         struct drm_i915_private *dev_priv = to_i915(dev);
1774         struct drm_i915_gem_object *obj = ringbuf->obj;
1775         int ret;
1776
1777         ret = i915_gem_obj_ggtt_pin(obj, PAGE_SIZE, PIN_MAPPABLE);
1778         if (ret)
1779                 return ret;
1780
1781         ret = i915_gem_object_set_to_gtt_domain(obj, true);
1782         if (ret) {
1783                 i915_gem_object_ggtt_unpin(obj);
1784                 return ret;
1785         }
1786
1787         ringbuf->virtual_start = ioremap_wc(dev_priv->gtt.mappable_base +
1788                         i915_gem_obj_ggtt_offset(obj), ringbuf->size);
1789         if (ringbuf->virtual_start == NULL) {
1790                 i915_gem_object_ggtt_unpin(obj);
1791                 return -EINVAL;
1792         }
1793
1794         return 0;
1795 }
1796
1797 void intel_destroy_ringbuffer_obj(struct intel_ringbuffer *ringbuf)
1798 {
1799         drm_gem_object_unreference(&ringbuf->obj->base);
1800         ringbuf->obj = NULL;
1801 }
1802
1803 int intel_alloc_ringbuffer_obj(struct drm_device *dev,
1804                                struct intel_ringbuffer *ringbuf)
1805 {
1806         struct drm_i915_gem_object *obj;
1807
1808         obj = NULL;
1809         if (!HAS_LLC(dev))
1810                 obj = i915_gem_object_create_stolen(dev, ringbuf->size);
1811         if (obj == NULL)
1812                 obj = i915_gem_alloc_object(dev, ringbuf->size);
1813         if (obj == NULL)
1814                 return -ENOMEM;
1815
1816         /* mark ring buffers as read-only from GPU side by default */
1817         obj->gt_ro = 1;
1818
1819         ringbuf->obj = obj;
1820
1821         return 0;
1822 }
1823
1824 static int intel_init_ring_buffer(struct drm_device *dev,
1825                                   struct intel_engine_cs *ring)
1826 {
1827         struct intel_ringbuffer *ringbuf;
1828         int ret;
1829
1830         WARN_ON(ring->buffer);
1831
1832         ringbuf = kzalloc(sizeof(*ringbuf), GFP_KERNEL);
1833         if (!ringbuf)
1834                 return -ENOMEM;
1835         ring->buffer = ringbuf;
1836
1837         ring->dev = dev;
1838         INIT_LIST_HEAD(&ring->active_list);
1839         INIT_LIST_HEAD(&ring->request_list);
1840         INIT_LIST_HEAD(&ring->execlist_queue);
1841         ringbuf->size = 32 * PAGE_SIZE;
1842         ringbuf->ring = ring;
1843         memset(ring->semaphore.sync_seqno, 0, sizeof(ring->semaphore.sync_seqno));
1844
1845         init_waitqueue_head(&ring->irq_queue);
1846
1847         if (I915_NEED_GFX_HWS(dev)) {
1848                 ret = init_status_page(ring);
1849                 if (ret)
1850                         goto error;
1851         } else {
1852                 BUG_ON(ring->id != RCS);
1853                 ret = init_phys_status_page(ring);
1854                 if (ret)
1855                         goto error;
1856         }
1857
1858         WARN_ON(ringbuf->obj);
1859
1860         ret = intel_alloc_ringbuffer_obj(dev, ringbuf);
1861         if (ret) {
1862                 DRM_ERROR("Failed to allocate ringbuffer %s: %d\n",
1863                                 ring->name, ret);
1864                 goto error;
1865         }
1866
1867         ret = intel_pin_and_map_ringbuffer_obj(dev, ringbuf);
1868         if (ret) {
1869                 DRM_ERROR("Failed to pin and map ringbuffer %s: %d\n",
1870                                 ring->name, ret);
1871                 intel_destroy_ringbuffer_obj(ringbuf);
1872                 goto error;
1873         }
1874
1875         /* Workaround an erratum on the i830 which causes a hang if
1876          * the TAIL pointer points to within the last 2 cachelines
1877          * of the buffer.
1878          */
1879         ringbuf->effective_size = ringbuf->size;
1880         if (IS_I830(dev) || IS_845G(dev))
1881                 ringbuf->effective_size -= 2 * CACHELINE_BYTES;
1882
1883         ret = i915_cmd_parser_init_ring(ring);
1884         if (ret)
1885                 goto error;
1886
1887         return 0;
1888
1889 error:
1890         kfree(ringbuf);
1891         ring->buffer = NULL;
1892         return ret;
1893 }
1894
1895 void intel_cleanup_ring_buffer(struct intel_engine_cs *ring)
1896 {
1897         struct drm_i915_private *dev_priv;
1898         struct intel_ringbuffer *ringbuf;
1899
1900         if (!intel_ring_initialized(ring))
1901                 return;
1902
1903         dev_priv = to_i915(ring->dev);
1904         ringbuf = ring->buffer;
1905
1906         intel_stop_ring_buffer(ring);
1907         WARN_ON(!IS_GEN2(ring->dev) && (I915_READ_MODE(ring) & MODE_IDLE) == 0);
1908
1909         intel_unpin_ringbuffer_obj(ringbuf);
1910         intel_destroy_ringbuffer_obj(ringbuf);
1911         i915_gem_request_assign(&ring->outstanding_lazy_request, NULL);
1912
1913         if (ring->cleanup)
1914                 ring->cleanup(ring);
1915
1916         cleanup_status_page(ring);
1917
1918         i915_cmd_parser_fini_ring(ring);
1919
1920         kfree(ringbuf);
1921         ring->buffer = NULL;
1922 }
1923
1924 static int intel_ring_wait_request(struct intel_engine_cs *ring, int n)
1925 {
1926         struct intel_ringbuffer *ringbuf = ring->buffer;
1927         struct drm_i915_gem_request *request;
1928         int ret;
1929
1930         if (intel_ring_space(ringbuf) >= n)
1931                 return 0;
1932
1933         list_for_each_entry(request, &ring->request_list, list) {
1934                 if (__intel_ring_space(request->tail, ringbuf->tail,
1935                                        ringbuf->size) >= n) {
1936                         break;
1937                 }
1938         }
1939
1940         if (&request->list == &ring->request_list)
1941                 return -ENOSPC;
1942
1943         ret = i915_wait_request(request);
1944         if (ret)
1945                 return ret;
1946
1947         i915_gem_retire_requests_ring(ring);
1948
1949         return 0;
1950 }
1951
1952 static int ring_wait_for_space(struct intel_engine_cs *ring, int n)
1953 {
1954         struct drm_device *dev = ring->dev;
1955         struct drm_i915_private *dev_priv = dev->dev_private;
1956         struct intel_ringbuffer *ringbuf = ring->buffer;
1957         unsigned long end;
1958         int ret;
1959
1960         ret = intel_ring_wait_request(ring, n);
1961         if (ret != -ENOSPC)
1962                 return ret;
1963
1964         /* force the tail write in case we have been skipping them */
1965         __intel_ring_advance(ring);
1966
1967         /* With GEM the hangcheck timer should kick us out of the loop,
1968          * leaving it early runs the risk of corrupting GEM state (due
1969          * to running on almost untested codepaths). But on resume
1970          * timers don't work yet, so prevent a complete hang in that
1971          * case by choosing an insanely large timeout. */
1972         end = jiffies + 60 * HZ;
1973
1974         ret = 0;
1975         trace_i915_ring_wait_begin(ring);
1976         do {
1977                 if (intel_ring_space(ringbuf) >= n)
1978                         break;
1979                 ringbuf->head = I915_READ_HEAD(ring);
1980                 if (intel_ring_space(ringbuf) >= n)
1981                         break;
1982
1983                 msleep(1);
1984
1985                 if (dev_priv->mm.interruptible && signal_pending(current)) {
1986                         ret = -ERESTARTSYS;
1987                         break;
1988                 }
1989
1990                 ret = i915_gem_check_wedge(&dev_priv->gpu_error,
1991                                            dev_priv->mm.interruptible);
1992                 if (ret)
1993                         break;
1994
1995                 if (time_after(jiffies, end)) {
1996                         ret = -EBUSY;
1997                         break;
1998                 }
1999         } while (1);
2000         trace_i915_ring_wait_end(ring);
2001         return ret;
2002 }
2003
2004 static int intel_wrap_ring_buffer(struct intel_engine_cs *ring)
2005 {
2006         uint32_t __iomem *virt;
2007         struct intel_ringbuffer *ringbuf = ring->buffer;
2008         int rem = ringbuf->size - ringbuf->tail;
2009
2010         if (ringbuf->space < rem) {
2011                 int ret = ring_wait_for_space(ring, rem);
2012                 if (ret)
2013                         return ret;
2014         }
2015
2016         virt = ringbuf->virtual_start + ringbuf->tail;
2017         rem /= 4;
2018         while (rem--)
2019                 iowrite32(MI_NOOP, virt++);
2020
2021         ringbuf->tail = 0;
2022         intel_ring_update_space(ringbuf);
2023
2024         return 0;
2025 }
2026
2027 int intel_ring_idle(struct intel_engine_cs *ring)
2028 {
2029         struct drm_i915_gem_request *req;
2030         int ret;
2031
2032         /* We need to add any requests required to flush the objects and ring */
2033         if (ring->outstanding_lazy_request) {
2034                 ret = i915_add_request(ring);
2035                 if (ret)
2036                         return ret;
2037         }
2038
2039         /* Wait upon the last request to be completed */
2040         if (list_empty(&ring->request_list))
2041                 return 0;
2042
2043         req = list_entry(ring->request_list.prev,
2044                            struct drm_i915_gem_request,
2045                            list);
2046
2047         return i915_wait_request(req);
2048 }
2049
2050 static int
2051 intel_ring_alloc_request(struct intel_engine_cs *ring)
2052 {
2053         int ret;
2054         struct drm_i915_gem_request *request;
2055         struct drm_i915_private *dev_private = ring->dev->dev_private;
2056
2057         if (ring->outstanding_lazy_request)
2058                 return 0;
2059
2060         request = kzalloc(sizeof(*request), GFP_KERNEL);
2061         if (request == NULL)
2062                 return -ENOMEM;
2063
2064         kref_init(&request->ref);
2065         request->ring = ring;
2066         request->uniq = dev_private->request_uniq++;
2067
2068         ret = i915_gem_get_seqno(ring->dev, &request->seqno);
2069         if (ret) {
2070                 kfree(request);
2071                 return ret;
2072         }
2073
2074         ring->outstanding_lazy_request = request;
2075         return 0;
2076 }
2077
2078 static int __intel_ring_prepare(struct intel_engine_cs *ring,
2079                                 int bytes)
2080 {
2081         struct intel_ringbuffer *ringbuf = ring->buffer;
2082         int ret;
2083
2084         if (unlikely(ringbuf->tail + bytes > ringbuf->effective_size)) {
2085                 ret = intel_wrap_ring_buffer(ring);
2086                 if (unlikely(ret))
2087                         return ret;
2088         }
2089
2090         if (unlikely(ringbuf->space < bytes)) {
2091                 ret = ring_wait_for_space(ring, bytes);
2092                 if (unlikely(ret))
2093                         return ret;
2094         }
2095
2096         return 0;
2097 }
2098
2099 int intel_ring_begin(struct intel_engine_cs *ring,
2100                      int num_dwords)
2101 {
2102         struct drm_i915_private *dev_priv = ring->dev->dev_private;
2103         int ret;
2104
2105         ret = i915_gem_check_wedge(&dev_priv->gpu_error,
2106                                    dev_priv->mm.interruptible);
2107         if (ret)
2108                 return ret;
2109
2110         ret = __intel_ring_prepare(ring, num_dwords * sizeof(uint32_t));
2111         if (ret)
2112                 return ret;
2113
2114         /* Preallocate the olr before touching the ring */
2115         ret = intel_ring_alloc_request(ring);
2116         if (ret)
2117                 return ret;
2118
2119         ring->buffer->space -= num_dwords * sizeof(uint32_t);
2120         return 0;
2121 }
2122
2123 /* Align the ring tail to a cacheline boundary */
2124 int intel_ring_cacheline_align(struct intel_engine_cs *ring)
2125 {
2126         int num_dwords = (ring->buffer->tail & (CACHELINE_BYTES - 1)) / sizeof(uint32_t);
2127         int ret;
2128
2129         if (num_dwords == 0)
2130                 return 0;
2131
2132         num_dwords = CACHELINE_BYTES / sizeof(uint32_t) - num_dwords;
2133         ret = intel_ring_begin(ring, num_dwords);
2134         if (ret)
2135                 return ret;
2136
2137         while (num_dwords--)
2138                 intel_ring_emit(ring, MI_NOOP);
2139
2140         intel_ring_advance(ring);
2141
2142         return 0;
2143 }
2144
2145 void intel_ring_init_seqno(struct intel_engine_cs *ring, u32 seqno)
2146 {
2147         struct drm_device *dev = ring->dev;
2148         struct drm_i915_private *dev_priv = dev->dev_private;
2149
2150         BUG_ON(ring->outstanding_lazy_request);
2151
2152         if (INTEL_INFO(dev)->gen == 6 || INTEL_INFO(dev)->gen == 7) {
2153                 I915_WRITE(RING_SYNC_0(ring->mmio_base), 0);
2154                 I915_WRITE(RING_SYNC_1(ring->mmio_base), 0);
2155                 if (HAS_VEBOX(dev))
2156                         I915_WRITE(RING_SYNC_2(ring->mmio_base), 0);
2157         }
2158
2159         ring->set_seqno(ring, seqno);
2160         ring->hangcheck.seqno = seqno;
2161 }
2162
2163 static void gen6_bsd_ring_write_tail(struct intel_engine_cs *ring,
2164                                      u32 value)
2165 {
2166         struct drm_i915_private *dev_priv = ring->dev->dev_private;
2167
2168        /* Every tail move must follow the sequence below */
2169
2170         /* Disable notification that the ring is IDLE. The GT
2171          * will then assume that it is busy and bring it out of rc6.
2172          */
2173         I915_WRITE(GEN6_BSD_SLEEP_PSMI_CONTROL,
2174                    _MASKED_BIT_ENABLE(GEN6_BSD_SLEEP_MSG_DISABLE));
2175
2176         /* Clear the context id. Here be magic! */
2177         I915_WRITE64(GEN6_BSD_RNCID, 0x0);
2178
2179         /* Wait for the ring not to be idle, i.e. for it to wake up. */
2180         if (wait_for((I915_READ(GEN6_BSD_SLEEP_PSMI_CONTROL) &
2181                       GEN6_BSD_SLEEP_INDICATOR) == 0,
2182                      50))
2183                 DRM_ERROR("timed out waiting for the BSD ring to wake up\n");
2184
2185         /* Now that the ring is fully powered up, update the tail */
2186         I915_WRITE_TAIL(ring, value);
2187         POSTING_READ(RING_TAIL(ring->mmio_base));
2188
2189         /* Let the ring send IDLE messages to the GT again,
2190          * and so let it sleep to conserve power when idle.
2191          */
2192         I915_WRITE(GEN6_BSD_SLEEP_PSMI_CONTROL,
2193                    _MASKED_BIT_DISABLE(GEN6_BSD_SLEEP_MSG_DISABLE));
2194 }
2195
2196 static int gen6_bsd_ring_flush(struct intel_engine_cs *ring,
2197                                u32 invalidate, u32 flush)
2198 {
2199         uint32_t cmd;
2200         int ret;
2201
2202         ret = intel_ring_begin(ring, 4);
2203         if (ret)
2204                 return ret;
2205
2206         cmd = MI_FLUSH_DW;
2207         if (INTEL_INFO(ring->dev)->gen >= 8)
2208                 cmd += 1;
2209         /*
2210          * Bspec vol 1c.5 - video engine command streamer:
2211          * "If ENABLED, all TLBs will be invalidated once the flush
2212          * operation is complete. This bit is only valid when the
2213          * Post-Sync Operation field is a value of 1h or 3h."
2214          */
2215         if (invalidate & I915_GEM_GPU_DOMAINS)
2216                 cmd |= MI_INVALIDATE_TLB | MI_INVALIDATE_BSD |
2217                         MI_FLUSH_DW_STORE_INDEX | MI_FLUSH_DW_OP_STOREDW;
2218         intel_ring_emit(ring, cmd);
2219         intel_ring_emit(ring, I915_GEM_HWS_SCRATCH_ADDR | MI_FLUSH_DW_USE_GTT);
2220         if (INTEL_INFO(ring->dev)->gen >= 8) {
2221                 intel_ring_emit(ring, 0); /* upper addr */
2222                 intel_ring_emit(ring, 0); /* value */
2223         } else  {
2224                 intel_ring_emit(ring, 0);
2225                 intel_ring_emit(ring, MI_NOOP);
2226         }
2227         intel_ring_advance(ring);
2228         return 0;
2229 }
2230
2231 static int
2232 gen8_ring_dispatch_execbuffer(struct intel_engine_cs *ring,
2233                               u64 offset, u32 len,
2234                               unsigned flags)
2235 {
2236         bool ppgtt = USES_PPGTT(ring->dev) && !(flags & I915_DISPATCH_SECURE);
2237         int ret;
2238
2239         ret = intel_ring_begin(ring, 4);
2240         if (ret)
2241                 return ret;
2242
2243         /* FIXME(BDW): Address space and security selectors. */
2244         intel_ring_emit(ring, MI_BATCH_BUFFER_START_GEN8 | (ppgtt<<8));
2245         intel_ring_emit(ring, lower_32_bits(offset));
2246         intel_ring_emit(ring, upper_32_bits(offset));
2247         intel_ring_emit(ring, MI_NOOP);
2248         intel_ring_advance(ring);
2249
2250         return 0;
2251 }
2252
2253 static int
2254 hsw_ring_dispatch_execbuffer(struct intel_engine_cs *ring,
2255                               u64 offset, u32 len,
2256                               unsigned flags)
2257 {
2258         int ret;
2259
2260         ret = intel_ring_begin(ring, 2);
2261         if (ret)
2262                 return ret;
2263
2264         intel_ring_emit(ring,
2265                         MI_BATCH_BUFFER_START |
2266                         (flags & I915_DISPATCH_SECURE ?
2267                          0 : MI_BATCH_PPGTT_HSW | MI_BATCH_NON_SECURE_HSW));
2268         /* bit0-7 is the length on GEN6+ */
2269         intel_ring_emit(ring, offset);
2270         intel_ring_advance(ring);
2271
2272         return 0;
2273 }
2274
2275 static int
2276 gen6_ring_dispatch_execbuffer(struct intel_engine_cs *ring,
2277                               u64 offset, u32 len,
2278                               unsigned flags)
2279 {
2280         int ret;
2281
2282         ret = intel_ring_begin(ring, 2);
2283         if (ret)
2284                 return ret;
2285
2286         intel_ring_emit(ring,
2287                         MI_BATCH_BUFFER_START |
2288                         (flags & I915_DISPATCH_SECURE ? 0 : MI_BATCH_NON_SECURE_I965));
2289         /* bit0-7 is the length on GEN6+ */
2290         intel_ring_emit(ring, offset);
2291         intel_ring_advance(ring);
2292
2293         return 0;
2294 }
2295
2296 /* Blitter support (SandyBridge+) */
2297
2298 static int gen6_ring_flush(struct intel_engine_cs *ring,
2299                            u32 invalidate, u32 flush)
2300 {
2301         struct drm_device *dev = ring->dev;
2302         struct drm_i915_private *dev_priv = dev->dev_private;
2303         uint32_t cmd;
2304         int ret;
2305
2306         ret = intel_ring_begin(ring, 4);
2307         if (ret)
2308                 return ret;
2309
2310         cmd = MI_FLUSH_DW;
2311         if (INTEL_INFO(ring->dev)->gen >= 8)
2312                 cmd += 1;
2313         /*
2314          * Bspec vol 1c.3 - blitter engine command streamer:
2315          * "If ENABLED, all TLBs will be invalidated once the flush
2316          * operation is complete. This bit is only valid when the
2317          * Post-Sync Operation field is a value of 1h or 3h."
2318          */
2319         if (invalidate & I915_GEM_DOMAIN_RENDER)
2320                 cmd |= MI_INVALIDATE_TLB | MI_FLUSH_DW_STORE_INDEX |
2321                         MI_FLUSH_DW_OP_STOREDW;
2322         intel_ring_emit(ring, cmd);
2323         intel_ring_emit(ring, I915_GEM_HWS_SCRATCH_ADDR | MI_FLUSH_DW_USE_GTT);
2324         if (INTEL_INFO(ring->dev)->gen >= 8) {
2325                 intel_ring_emit(ring, 0); /* upper addr */
2326                 intel_ring_emit(ring, 0); /* value */
2327         } else  {
2328                 intel_ring_emit(ring, 0);
2329                 intel_ring_emit(ring, MI_NOOP);
2330         }
2331         intel_ring_advance(ring);
2332
2333         if (!invalidate && flush) {
2334                 if (IS_GEN7(dev))
2335                         return gen7_ring_fbc_flush(ring, FBC_REND_CACHE_CLEAN);
2336                 else if (IS_BROADWELL(dev))
2337                         dev_priv->fbc.need_sw_cache_clean = true;
2338         }
2339
2340         return 0;
2341 }
2342
2343 int intel_init_render_ring_buffer(struct drm_device *dev)
2344 {
2345         struct drm_i915_private *dev_priv = dev->dev_private;
2346         struct intel_engine_cs *ring = &dev_priv->ring[RCS];
2347         struct drm_i915_gem_object *obj;
2348         int ret;
2349
2350         ring->name = "render ring";
2351         ring->id = RCS;
2352         ring->mmio_base = RENDER_RING_BASE;
2353
2354         if (INTEL_INFO(dev)->gen >= 8) {
2355                 if (i915_semaphore_is_enabled(dev)) {
2356                         obj = i915_gem_alloc_object(dev, 4096);
2357                         if (obj == NULL) {
2358                                 DRM_ERROR("Failed to allocate semaphore bo. Disabling semaphores\n");
2359                                 i915.semaphores = 0;
2360                         } else {
2361                                 i915_gem_object_set_cache_level(obj, I915_CACHE_LLC);
2362                                 ret = i915_gem_obj_ggtt_pin(obj, 0, PIN_NONBLOCK);
2363                                 if (ret != 0) {
2364                                         drm_gem_object_unreference(&obj->base);
2365                                         DRM_ERROR("Failed to pin semaphore bo. Disabling semaphores\n");
2366                                         i915.semaphores = 0;
2367                                 } else
2368                                         dev_priv->semaphore_obj = obj;
2369                         }
2370                 }
2371
2372                 ring->init_context = intel_rcs_ctx_init;
2373                 ring->add_request = gen6_add_request;
2374                 ring->flush = gen8_render_ring_flush;
2375                 ring->irq_get = gen8_ring_get_irq;
2376                 ring->irq_put = gen8_ring_put_irq;
2377                 ring->irq_enable_mask = GT_RENDER_USER_INTERRUPT;
2378                 ring->get_seqno = gen6_ring_get_seqno;
2379                 ring->set_seqno = ring_set_seqno;
2380                 if (i915_semaphore_is_enabled(dev)) {
2381                         WARN_ON(!dev_priv->semaphore_obj);
2382                         ring->semaphore.sync_to = gen8_ring_sync;
2383                         ring->semaphore.signal = gen8_rcs_signal;
2384                         GEN8_RING_SEMAPHORE_INIT;
2385                 }
2386         } else if (INTEL_INFO(dev)->gen >= 6) {
2387                 ring->add_request = gen6_add_request;
2388                 ring->flush = gen7_render_ring_flush;
2389                 if (INTEL_INFO(dev)->gen == 6)
2390                         ring->flush = gen6_render_ring_flush;
2391                 ring->irq_get = gen6_ring_get_irq;
2392                 ring->irq_put = gen6_ring_put_irq;
2393                 ring->irq_enable_mask = GT_RENDER_USER_INTERRUPT;
2394                 ring->get_seqno = gen6_ring_get_seqno;
2395                 ring->set_seqno = ring_set_seqno;
2396                 if (i915_semaphore_is_enabled(dev)) {
2397                         ring->semaphore.sync_to = gen6_ring_sync;
2398                         ring->semaphore.signal = gen6_signal;
2399                         /*
2400                          * The current semaphore is only applied on pre-gen8
2401                          * platform.  And there is no VCS2 ring on the pre-gen8
2402                          * platform. So the semaphore between RCS and VCS2 is
2403                          * initialized as INVALID.  Gen8 will initialize the
2404                          * sema between VCS2 and RCS later.
2405                          */
2406                         ring->semaphore.mbox.wait[RCS] = MI_SEMAPHORE_SYNC_INVALID;
2407                         ring->semaphore.mbox.wait[VCS] = MI_SEMAPHORE_SYNC_RV;
2408                         ring->semaphore.mbox.wait[BCS] = MI_SEMAPHORE_SYNC_RB;
2409                         ring->semaphore.mbox.wait[VECS] = MI_SEMAPHORE_SYNC_RVE;
2410                         ring->semaphore.mbox.wait[VCS2] = MI_SEMAPHORE_SYNC_INVALID;
2411                         ring->semaphore.mbox.signal[RCS] = GEN6_NOSYNC;
2412                         ring->semaphore.mbox.signal[VCS] = GEN6_VRSYNC;
2413                         ring->semaphore.mbox.signal[BCS] = GEN6_BRSYNC;
2414                         ring->semaphore.mbox.signal[VECS] = GEN6_VERSYNC;
2415                         ring->semaphore.mbox.signal[VCS2] = GEN6_NOSYNC;
2416                 }
2417         } else if (IS_GEN5(dev)) {
2418                 ring->add_request = pc_render_add_request;
2419                 ring->flush = gen4_render_ring_flush;
2420                 ring->get_seqno = pc_render_get_seqno;
2421                 ring->set_seqno = pc_render_set_seqno;
2422                 ring->irq_get = gen5_ring_get_irq;
2423                 ring->irq_put = gen5_ring_put_irq;
2424                 ring->irq_enable_mask = GT_RENDER_USER_INTERRUPT |
2425                                         GT_RENDER_PIPECTL_NOTIFY_INTERRUPT;
2426         } else {
2427                 ring->add_request = i9xx_add_request;
2428                 if (INTEL_INFO(dev)->gen < 4)
2429                         ring->flush = gen2_render_ring_flush;
2430                 else
2431                         ring->flush = gen4_render_ring_flush;
2432                 ring->get_seqno = ring_get_seqno;
2433                 ring->set_seqno = ring_set_seqno;
2434                 if (IS_GEN2(dev)) {
2435                         ring->irq_get = i8xx_ring_get_irq;
2436                         ring->irq_put = i8xx_ring_put_irq;
2437                 } else {
2438                         ring->irq_get = i9xx_ring_get_irq;
2439                         ring->irq_put = i9xx_ring_put_irq;
2440                 }
2441                 ring->irq_enable_mask = I915_USER_INTERRUPT;
2442         }
2443         ring->write_tail = ring_write_tail;
2444
2445         if (IS_HASWELL(dev))
2446                 ring->dispatch_execbuffer = hsw_ring_dispatch_execbuffer;
2447         else if (IS_GEN8(dev))
2448                 ring->dispatch_execbuffer = gen8_ring_dispatch_execbuffer;
2449         else if (INTEL_INFO(dev)->gen >= 6)
2450                 ring->dispatch_execbuffer = gen6_ring_dispatch_execbuffer;
2451         else if (INTEL_INFO(dev)->gen >= 4)
2452                 ring->dispatch_execbuffer = i965_dispatch_execbuffer;
2453         else if (IS_I830(dev) || IS_845G(dev))
2454                 ring->dispatch_execbuffer = i830_dispatch_execbuffer;
2455         else
2456                 ring->dispatch_execbuffer = i915_dispatch_execbuffer;
2457         ring->init_hw = init_render_ring;
2458         ring->cleanup = render_ring_cleanup;
2459
2460         /* Workaround batchbuffer to combat CS tlb bug. */
2461         if (HAS_BROKEN_CS_TLB(dev)) {
2462                 obj = i915_gem_alloc_object(dev, I830_WA_SIZE);
2463                 if (obj == NULL) {
2464                         DRM_ERROR("Failed to allocate batch bo\n");
2465                         return -ENOMEM;
2466                 }
2467
2468                 ret = i915_gem_obj_ggtt_pin(obj, 0, 0);
2469                 if (ret != 0) {
2470                         drm_gem_object_unreference(&obj->base);
2471                         DRM_ERROR("Failed to ping batch bo\n");
2472                         return ret;
2473                 }
2474
2475                 ring->scratch.obj = obj;
2476                 ring->scratch.gtt_offset = i915_gem_obj_ggtt_offset(obj);
2477         }
2478
2479         ret = intel_init_ring_buffer(dev, ring);
2480         if (ret)
2481                 return ret;
2482
2483         if (INTEL_INFO(dev)->gen >= 5) {
2484                 ret = intel_init_pipe_control(ring);
2485                 if (ret)
2486                         return ret;
2487         }
2488
2489         return 0;
2490 }
2491
2492 int intel_init_bsd_ring_buffer(struct drm_device *dev)
2493 {
2494         struct drm_i915_private *dev_priv = dev->dev_private;
2495         struct intel_engine_cs *ring = &dev_priv->ring[VCS];
2496
2497         ring->name = "bsd ring";
2498         ring->id = VCS;
2499
2500         ring->write_tail = ring_write_tail;
2501         if (INTEL_INFO(dev)->gen >= 6) {
2502                 ring->mmio_base = GEN6_BSD_RING_BASE;
2503                 /* gen6 bsd needs a special wa for tail updates */
2504                 if (IS_GEN6(dev))
2505                         ring->write_tail = gen6_bsd_ring_write_tail;
2506                 ring->flush = gen6_bsd_ring_flush;
2507                 ring->add_request = gen6_add_request;
2508                 ring->get_seqno = gen6_ring_get_seqno;
2509                 ring->set_seqno = ring_set_seqno;
2510                 if (INTEL_INFO(dev)->gen >= 8) {
2511                         ring->irq_enable_mask =
2512                                 GT_RENDER_USER_INTERRUPT << GEN8_VCS1_IRQ_SHIFT;
2513                         ring->irq_get = gen8_ring_get_irq;
2514                         ring->irq_put = gen8_ring_put_irq;
2515                         ring->dispatch_execbuffer =
2516                                 gen8_ring_dispatch_execbuffer;
2517                         if (i915_semaphore_is_enabled(dev)) {
2518                                 ring->semaphore.sync_to = gen8_ring_sync;
2519                                 ring->semaphore.signal = gen8_xcs_signal;
2520                                 GEN8_RING_SEMAPHORE_INIT;
2521                         }
2522                 } else {
2523                         ring->irq_enable_mask = GT_BSD_USER_INTERRUPT;
2524                         ring->irq_get = gen6_ring_get_irq;
2525                         ring->irq_put = gen6_ring_put_irq;
2526                         ring->dispatch_execbuffer =
2527                                 gen6_ring_dispatch_execbuffer;
2528                         if (i915_semaphore_is_enabled(dev)) {
2529                                 ring->semaphore.sync_to = gen6_ring_sync;
2530                                 ring->semaphore.signal = gen6_signal;
2531                                 ring->semaphore.mbox.wait[RCS] = MI_SEMAPHORE_SYNC_VR;
2532                                 ring->semaphore.mbox.wait[VCS] = MI_SEMAPHORE_SYNC_INVALID;
2533                                 ring->semaphore.mbox.wait[BCS] = MI_SEMAPHORE_SYNC_VB;
2534                                 ring->semaphore.mbox.wait[VECS] = MI_SEMAPHORE_SYNC_VVE;
2535                                 ring->semaphore.mbox.wait[VCS2] = MI_SEMAPHORE_SYNC_INVALID;
2536                                 ring->semaphore.mbox.signal[RCS] = GEN6_RVSYNC;
2537                                 ring->semaphore.mbox.signal[VCS] = GEN6_NOSYNC;
2538                                 ring->semaphore.mbox.signal[BCS] = GEN6_BVSYNC;
2539                                 ring->semaphore.mbox.signal[VECS] = GEN6_VEVSYNC;
2540                                 ring->semaphore.mbox.signal[VCS2] = GEN6_NOSYNC;
2541                         }
2542                 }
2543         } else {
2544                 ring->mmio_base = BSD_RING_BASE;
2545                 ring->flush = bsd_ring_flush;
2546                 ring->add_request = i9xx_add_request;
2547                 ring->get_seqno = ring_get_seqno;
2548                 ring->set_seqno = ring_set_seqno;
2549                 if (IS_GEN5(dev)) {
2550                         ring->irq_enable_mask = ILK_BSD_USER_INTERRUPT;
2551                         ring->irq_get = gen5_ring_get_irq;
2552                         ring->irq_put = gen5_ring_put_irq;
2553                 } else {
2554                         ring->irq_enable_mask = I915_BSD_USER_INTERRUPT;
2555                         ring->irq_get = i9xx_ring_get_irq;
2556                         ring->irq_put = i9xx_ring_put_irq;
2557                 }
2558                 ring->dispatch_execbuffer = i965_dispatch_execbuffer;
2559         }
2560         ring->init_hw = init_ring_common;
2561
2562         return intel_init_ring_buffer(dev, ring);
2563 }
2564
2565 /**
2566  * Initialize the second BSD ring for Broadwell GT3.
2567  * It is noted that this only exists on Broadwell GT3.
2568  */
2569 int intel_init_bsd2_ring_buffer(struct drm_device *dev)
2570 {
2571         struct drm_i915_private *dev_priv = dev->dev_private;
2572         struct intel_engine_cs *ring = &dev_priv->ring[VCS2];
2573
2574         if ((INTEL_INFO(dev)->gen != 8)) {
2575                 DRM_ERROR("No dual-BSD ring on non-BDW machine\n");
2576                 return -EINVAL;
2577         }
2578
2579         ring->name = "bsd2 ring";
2580         ring->id = VCS2;
2581
2582         ring->write_tail = ring_write_tail;
2583         ring->mmio_base = GEN8_BSD2_RING_BASE;
2584         ring->flush = gen6_bsd_ring_flush;
2585         ring->add_request = gen6_add_request;
2586         ring->get_seqno = gen6_ring_get_seqno;
2587         ring->set_seqno = ring_set_seqno;
2588         ring->irq_enable_mask =
2589                         GT_RENDER_USER_INTERRUPT << GEN8_VCS2_IRQ_SHIFT;
2590         ring->irq_get = gen8_ring_get_irq;
2591         ring->irq_put = gen8_ring_put_irq;
2592         ring->dispatch_execbuffer =
2593                         gen8_ring_dispatch_execbuffer;
2594         if (i915_semaphore_is_enabled(dev)) {
2595                 ring->semaphore.sync_to = gen8_ring_sync;
2596                 ring->semaphore.signal = gen8_xcs_signal;
2597                 GEN8_RING_SEMAPHORE_INIT;
2598         }
2599         ring->init_hw = init_ring_common;
2600
2601         return intel_init_ring_buffer(dev, ring);
2602 }
2603
2604 int intel_init_blt_ring_buffer(struct drm_device *dev)
2605 {
2606         struct drm_i915_private *dev_priv = dev->dev_private;
2607         struct intel_engine_cs *ring = &dev_priv->ring[BCS];
2608
2609         ring->name = "blitter ring";
2610         ring->id = BCS;
2611
2612         ring->mmio_base = BLT_RING_BASE;
2613         ring->write_tail = ring_write_tail;
2614         ring->flush = gen6_ring_flush;
2615         ring->add_request = gen6_add_request;
2616         ring->get_seqno = gen6_ring_get_seqno;
2617         ring->set_seqno = ring_set_seqno;
2618         if (INTEL_INFO(dev)->gen >= 8) {
2619                 ring->irq_enable_mask =
2620                         GT_RENDER_USER_INTERRUPT << GEN8_BCS_IRQ_SHIFT;
2621                 ring->irq_get = gen8_ring_get_irq;
2622                 ring->irq_put = gen8_ring_put_irq;
2623                 ring->dispatch_execbuffer = gen8_ring_dispatch_execbuffer;
2624                 if (i915_semaphore_is_enabled(dev)) {
2625                         ring->semaphore.sync_to = gen8_ring_sync;
2626                         ring->semaphore.signal = gen8_xcs_signal;
2627                         GEN8_RING_SEMAPHORE_INIT;
2628                 }
2629         } else {
2630                 ring->irq_enable_mask = GT_BLT_USER_INTERRUPT;
2631                 ring->irq_get = gen6_ring_get_irq;
2632                 ring->irq_put = gen6_ring_put_irq;
2633                 ring->dispatch_execbuffer = gen6_ring_dispatch_execbuffer;
2634                 if (i915_semaphore_is_enabled(dev)) {
2635                         ring->semaphore.signal = gen6_signal;
2636                         ring->semaphore.sync_to = gen6_ring_sync;
2637                         /*
2638                          * The current semaphore is only applied on pre-gen8
2639                          * platform.  And there is no VCS2 ring on the pre-gen8
2640                          * platform. So the semaphore between BCS and VCS2 is
2641                          * initialized as INVALID.  Gen8 will initialize the
2642                          * sema between BCS and VCS2 later.
2643                          */
2644                         ring->semaphore.mbox.wait[RCS] = MI_SEMAPHORE_SYNC_BR;
2645                         ring->semaphore.mbox.wait[VCS] = MI_SEMAPHORE_SYNC_BV;
2646                         ring->semaphore.mbox.wait[BCS] = MI_SEMAPHORE_SYNC_INVALID;
2647                         ring->semaphore.mbox.wait[VECS] = MI_SEMAPHORE_SYNC_BVE;
2648                         ring->semaphore.mbox.wait[VCS2] = MI_SEMAPHORE_SYNC_INVALID;
2649                         ring->semaphore.mbox.signal[RCS] = GEN6_RBSYNC;
2650                         ring->semaphore.mbox.signal[VCS] = GEN6_VBSYNC;
2651                         ring->semaphore.mbox.signal[BCS] = GEN6_NOSYNC;
2652                         ring->semaphore.mbox.signal[VECS] = GEN6_VEBSYNC;
2653                         ring->semaphore.mbox.signal[VCS2] = GEN6_NOSYNC;
2654                 }
2655         }
2656         ring->init_hw = init_ring_common;
2657
2658         return intel_init_ring_buffer(dev, ring);
2659 }
2660
2661 int intel_init_vebox_ring_buffer(struct drm_device *dev)
2662 {
2663         struct drm_i915_private *dev_priv = dev->dev_private;
2664         struct intel_engine_cs *ring = &dev_priv->ring[VECS];
2665
2666         ring->name = "video enhancement ring";
2667         ring->id = VECS;
2668
2669         ring->mmio_base = VEBOX_RING_BASE;
2670         ring->write_tail = ring_write_tail;
2671         ring->flush = gen6_ring_flush;
2672         ring->add_request = gen6_add_request;
2673         ring->get_seqno = gen6_ring_get_seqno;
2674         ring->set_seqno = ring_set_seqno;
2675
2676         if (INTEL_INFO(dev)->gen >= 8) {
2677                 ring->irq_enable_mask =
2678                         GT_RENDER_USER_INTERRUPT << GEN8_VECS_IRQ_SHIFT;
2679                 ring->irq_get = gen8_ring_get_irq;
2680                 ring->irq_put = gen8_ring_put_irq;
2681                 ring->dispatch_execbuffer = gen8_ring_dispatch_execbuffer;
2682                 if (i915_semaphore_is_enabled(dev)) {
2683                         ring->semaphore.sync_to = gen8_ring_sync;
2684                         ring->semaphore.signal = gen8_xcs_signal;
2685                         GEN8_RING_SEMAPHORE_INIT;
2686                 }
2687         } else {
2688                 ring->irq_enable_mask = PM_VEBOX_USER_INTERRUPT;
2689                 ring->irq_get = hsw_vebox_get_irq;
2690                 ring->irq_put = hsw_vebox_put_irq;
2691                 ring->dispatch_execbuffer = gen6_ring_dispatch_execbuffer;
2692                 if (i915_semaphore_is_enabled(dev)) {
2693                         ring->semaphore.sync_to = gen6_ring_sync;
2694                         ring->semaphore.signal = gen6_signal;
2695                         ring->semaphore.mbox.wait[RCS] = MI_SEMAPHORE_SYNC_VER;
2696                         ring->semaphore.mbox.wait[VCS] = MI_SEMAPHORE_SYNC_VEV;
2697                         ring->semaphore.mbox.wait[BCS] = MI_SEMAPHORE_SYNC_VEB;
2698                         ring->semaphore.mbox.wait[VECS] = MI_SEMAPHORE_SYNC_INVALID;
2699                         ring->semaphore.mbox.wait[VCS2] = MI_SEMAPHORE_SYNC_INVALID;
2700                         ring->semaphore.mbox.signal[RCS] = GEN6_RVESYNC;
2701                         ring->semaphore.mbox.signal[VCS] = GEN6_VVESYNC;
2702                         ring->semaphore.mbox.signal[BCS] = GEN6_BVESYNC;
2703                         ring->semaphore.mbox.signal[VECS] = GEN6_NOSYNC;
2704                         ring->semaphore.mbox.signal[VCS2] = GEN6_NOSYNC;
2705                 }
2706         }
2707         ring->init_hw = init_ring_common;
2708
2709         return intel_init_ring_buffer(dev, ring);
2710 }
2711
2712 int
2713 intel_ring_flush_all_caches(struct intel_engine_cs *ring)
2714 {
2715         int ret;
2716
2717         if (!ring->gpu_caches_dirty)
2718                 return 0;
2719
2720         ret = ring->flush(ring, 0, I915_GEM_GPU_DOMAINS);
2721         if (ret)
2722                 return ret;
2723
2724         trace_i915_gem_ring_flush(ring, 0, I915_GEM_GPU_DOMAINS);
2725
2726         ring->gpu_caches_dirty = false;
2727         return 0;
2728 }
2729
2730 int
2731 intel_ring_invalidate_all_caches(struct intel_engine_cs *ring)
2732 {
2733         uint32_t flush_domains;
2734         int ret;
2735
2736         flush_domains = 0;
2737         if (ring->gpu_caches_dirty)
2738                 flush_domains = I915_GEM_GPU_DOMAINS;
2739
2740         ret = ring->flush(ring, I915_GEM_GPU_DOMAINS, flush_domains);
2741         if (ret)
2742                 return ret;
2743
2744         trace_i915_gem_ring_flush(ring, I915_GEM_GPU_DOMAINS, flush_domains);
2745
2746         ring->gpu_caches_dirty = false;
2747         return 0;
2748 }
2749
2750 void
2751 intel_stop_ring_buffer(struct intel_engine_cs *ring)
2752 {
2753         int ret;
2754
2755         if (!intel_ring_initialized(ring))
2756                 return;
2757
2758         ret = intel_ring_idle(ring);
2759         if (ret && !i915_reset_in_progress(&to_i915(ring->dev)->gpu_error))
2760                 DRM_ERROR("failed to quiesce %s whilst cleaning up: %d\n",
2761                           ring->name, ret);
2762
2763         stop_ring(ring);
2764 }