drivers/net/can/flexcan.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 //
   3 // flexcan.c - FLEXCAN CAN controller driver
   4 //
   5 // Copyright (c) 2005-2006 Varma Electronics Oy
   6 // Copyright (c) 2009 Sascha Hauer, Pengutronix
   7 // Copyright (c) 2010-2017 Pengutronix, Marc Kleine-Budde <[email protected]>
   8 // Copyright (c) 2014 David Jander, Protonic Holland
   9 //
  10 // Based on code originally by Andrey Volkov <[email protected]>
  11
  12 #include <linux/netdevice.h>
  13 #include <linux/can.h>
  14 #include <linux/can/dev.h>
  15 #include <linux/can/error.h>
  16 #include <linux/can/led.h>
  17 #include <linux/can/rx-offload.h>
  18 #include <linux/clk.h>
  19 #include <linux/delay.h>
  20 #include <linux/interrupt.h>
  21 #include <linux/io.h>
  22 #include <linux/mfd/syscon.h>
  23 #include <linux/module.h>
  24 #include <linux/of.h>
  25 #include <linux/of_device.h>
  26 #include <linux/platform_device.h>
  27 #include <linux/pm_runtime.h>
  28 #include <linux/regulator/consumer.h>
  29 #include <linux/regmap.h>
  30
  31 #define DRV_NAME                        "flexcan"
  32
  33 /* 8 for RX fifo and 2 error handling */
  34 #define FLEXCAN_NAPI_WEIGHT             (8 + 2)
  35
  36 /* FLEXCAN module configuration register (CANMCR) bits */
  37 #define FLEXCAN_MCR_MDIS                BIT(31)
  38 #define FLEXCAN_MCR_FRZ                 BIT(30)
  39 #define FLEXCAN_MCR_FEN                 BIT(29)
  40 #define FLEXCAN_MCR_HALT                BIT(28)
  41 #define FLEXCAN_MCR_NOT_RDY             BIT(27)
  42 #define FLEXCAN_MCR_WAK_MSK             BIT(26)
  43 #define FLEXCAN_MCR_SOFTRST             BIT(25)
  44 #define FLEXCAN_MCR_FRZ_ACK             BIT(24)
  45 #define FLEXCAN_MCR_SUPV                BIT(23)
  46 #define FLEXCAN_MCR_SLF_WAK             BIT(22)
  47 #define FLEXCAN_MCR_WRN_EN              BIT(21)
  48 #define FLEXCAN_MCR_LPM_ACK             BIT(20)
  49 #define FLEXCAN_MCR_WAK_SRC             BIT(19)
  50 #define FLEXCAN_MCR_DOZE                BIT(18)
  51 #define FLEXCAN_MCR_SRX_DIS             BIT(17)
  52 #define FLEXCAN_MCR_IRMQ                BIT(16)
  53 #define FLEXCAN_MCR_LPRIO_EN            BIT(13)
  54 #define FLEXCAN_MCR_AEN                 BIT(12)
  55 /* MCR_MAXMB: maximum used MBs is MAXMB + 1 */
  56 #define FLEXCAN_MCR_MAXMB(x)            ((x) & 0x7f)
  57 #define FLEXCAN_MCR_IDAM_A              (0x0 << 8)
  58 #define FLEXCAN_MCR_IDAM_B              (0x1 << 8)
  59 #define FLEXCAN_MCR_IDAM_C              (0x2 << 8)
  60 #define FLEXCAN_MCR_IDAM_D              (0x3 << 8)
  61
  62 /* FLEXCAN control register (CANCTRL) bits */
  63 #define FLEXCAN_CTRL_PRESDIV(x)         (((x) & 0xff) << 24)
  64 #define FLEXCAN_CTRL_RJW(x)             (((x) & 0x03) << 22)
  65 #define FLEXCAN_CTRL_PSEG1(x)           (((x) & 0x07) << 19)
  66 #define FLEXCAN_CTRL_PSEG2(x)           (((x) & 0x07) << 16)
  67 #define FLEXCAN_CTRL_BOFF_MSK           BIT(15)
  68 #define FLEXCAN_CTRL_ERR_MSK            BIT(14)
  69 #define FLEXCAN_CTRL_CLK_SRC            BIT(13)
  70 #define FLEXCAN_CTRL_LPB                BIT(12)
  71 #define FLEXCAN_CTRL_TWRN_MSK           BIT(11)
  72 #define FLEXCAN_CTRL_RWRN_MSK           BIT(10)
  73 #define FLEXCAN_CTRL_SMP                BIT(7)
  74 #define FLEXCAN_CTRL_BOFF_REC           BIT(6)
  75 #define FLEXCAN_CTRL_TSYN               BIT(5)
  76 #define FLEXCAN_CTRL_LBUF               BIT(4)
  77 #define FLEXCAN_CTRL_LOM                BIT(3)
  78 #define FLEXCAN_CTRL_PROPSEG(x)         ((x) & 0x07)
  79 #define FLEXCAN_CTRL_ERR_BUS            (FLEXCAN_CTRL_ERR_MSK)
  80 #define FLEXCAN_CTRL_ERR_STATE \
  81         (FLEXCAN_CTRL_TWRN_MSK | FLEXCAN_CTRL_RWRN_MSK | \
  82          FLEXCAN_CTRL_BOFF_MSK)
  83 #define FLEXCAN_CTRL_ERR_ALL \
  84         (FLEXCAN_CTRL_ERR_BUS | FLEXCAN_CTRL_ERR_STATE)
  85
  86 /* FLEXCAN control register 2 (CTRL2) bits */
  87 #define FLEXCAN_CTRL2_ECRWRE            BIT(29)
  88 #define FLEXCAN_CTRL2_WRMFRZ            BIT(28)
  89 #define FLEXCAN_CTRL2_RFFN(x)           (((x) & 0x0f) << 24)
  90 #define FLEXCAN_CTRL2_TASD(x)           (((x) & 0x1f) << 19)
  91 #define FLEXCAN_CTRL2_MRP               BIT(18)
  92 #define FLEXCAN_CTRL2_RRS               BIT(17)
  93 #define FLEXCAN_CTRL2_EACEN             BIT(16)
  94
  95 /* FLEXCAN memory error control register (MECR) bits */
  96 #define FLEXCAN_MECR_ECRWRDIS           BIT(31)
  97 #define FLEXCAN_MECR_HANCEI_MSK         BIT(19)
  98 #define FLEXCAN_MECR_FANCEI_MSK         BIT(18)
  99 #define FLEXCAN_MECR_CEI_MSK            BIT(16)
 100 #define FLEXCAN_MECR_HAERRIE            BIT(15)
 101 #define FLEXCAN_MECR_FAERRIE            BIT(14)
 102 #define FLEXCAN_MECR_EXTERRIE           BIT(13)
 103 #define FLEXCAN_MECR_RERRDIS            BIT(9)
 104 #define FLEXCAN_MECR_ECCDIS             BIT(8)
 105 #define FLEXCAN_MECR_NCEFAFRZ           BIT(7)
 106
 107 /* FLEXCAN error and status register (ESR) bits */
 108 #define FLEXCAN_ESR_TWRN_INT            BIT(17)
 109 #define FLEXCAN_ESR_RWRN_INT            BIT(16)
 110 #define FLEXCAN_ESR_BIT1_ERR            BIT(15)
 111 #define FLEXCAN_ESR_BIT0_ERR            BIT(14)
 112 #define FLEXCAN_ESR_ACK_ERR             BIT(13)
 113 #define FLEXCAN_ESR_CRC_ERR             BIT(12)
 114 #define FLEXCAN_ESR_FRM_ERR             BIT(11)
 115 #define FLEXCAN_ESR_STF_ERR             BIT(10)
 116 #define FLEXCAN_ESR_TX_WRN              BIT(9)
 117 #define FLEXCAN_ESR_RX_WRN              BIT(8)
 118 #define FLEXCAN_ESR_IDLE                BIT(7)
 119 #define FLEXCAN_ESR_TXRX                BIT(6)
 120 #define FLEXCAN_EST_FLT_CONF_SHIFT      (4)
 121 #define FLEXCAN_ESR_FLT_CONF_MASK       (0x3 << FLEXCAN_EST_FLT_CONF_SHIFT)
 122 #define FLEXCAN_ESR_FLT_CONF_ACTIVE     (0x0 << FLEXCAN_EST_FLT_CONF_SHIFT)
 123 #define FLEXCAN_ESR_FLT_CONF_PASSIVE    (0x1 << FLEXCAN_EST_FLT_CONF_SHIFT)
 124 #define FLEXCAN_ESR_BOFF_INT            BIT(2)
 125 #define FLEXCAN_ESR_ERR_INT             BIT(1)
 126 #define FLEXCAN_ESR_WAK_INT             BIT(0)
 127 #define FLEXCAN_ESR_ERR_BUS \
 128         (FLEXCAN_ESR_BIT1_ERR | FLEXCAN_ESR_BIT0_ERR | \
 129          FLEXCAN_ESR_ACK_ERR | FLEXCAN_ESR_CRC_ERR | \
 130          FLEXCAN_ESR_FRM_ERR | FLEXCAN_ESR_STF_ERR)
 131 #define FLEXCAN_ESR_ERR_STATE \
 132         (FLEXCAN_ESR_TWRN_INT | FLEXCAN_ESR_RWRN_INT | FLEXCAN_ESR_BOFF_INT)
 133 #define FLEXCAN_ESR_ERR_ALL \
 134         (FLEXCAN_ESR_ERR_BUS | FLEXCAN_ESR_ERR_STATE)
 135 #define FLEXCAN_ESR_ALL_INT \
 136         (FLEXCAN_ESR_TWRN_INT | FLEXCAN_ESR_RWRN_INT | \
 137          FLEXCAN_ESR_BOFF_INT | FLEXCAN_ESR_ERR_INT | \
 138          FLEXCAN_ESR_WAK_INT)
 139
 140 /* FLEXCAN interrupt flag register (IFLAG) bits */
 141 /* Errata ERR005829 step7: Reserve first valid MB */
 142 #define FLEXCAN_TX_MB_RESERVED_OFF_FIFO         8
 143 #define FLEXCAN_TX_MB_RESERVED_OFF_TIMESTAMP    0
 144 #define FLEXCAN_RX_MB_OFF_TIMESTAMP_FIRST       (FLEXCAN_TX_MB_RESERVED_OFF_TIMESTAMP + 1)
 145 #define FLEXCAN_IFLAG_MB(x)             BIT_ULL(x)
 146 #define FLEXCAN_IFLAG_RX_FIFO_OVERFLOW  BIT(7)
 147 #define FLEXCAN_IFLAG_RX_FIFO_WARN      BIT(6)
 148 #define FLEXCAN_IFLAG_RX_FIFO_AVAILABLE BIT(5)
 149
 150 /* FLEXCAN message buffers */
 151 #define FLEXCAN_MB_CODE_MASK            (0xf << 24)
 152 #define FLEXCAN_MB_CODE_RX_BUSY_BIT     (0x1 << 24)
 153 #define FLEXCAN_MB_CODE_RX_INACTIVE     (0x0 << 24)
 154 #define FLEXCAN_MB_CODE_RX_EMPTY        (0x4 << 24)
 155 #define FLEXCAN_MB_CODE_RX_FULL         (0x2 << 24)
 156 #define FLEXCAN_MB_CODE_RX_OVERRUN      (0x6 << 24)
 157 #define FLEXCAN_MB_CODE_RX_RANSWER      (0xa << 24)
 158
 159 #define FLEXCAN_MB_CODE_TX_INACTIVE     (0x8 << 24)
 160 #define FLEXCAN_MB_CODE_TX_ABORT        (0x9 << 24)
 161 #define FLEXCAN_MB_CODE_TX_DATA         (0xc << 24)
 162 #define FLEXCAN_MB_CODE_TX_TANSWER      (0xe << 24)
 163
 164 #define FLEXCAN_MB_CNT_SRR              BIT(22)
 165 #define FLEXCAN_MB_CNT_IDE              BIT(21)
 166 #define FLEXCAN_MB_CNT_RTR              BIT(20)
 167 #define FLEXCAN_MB_CNT_LENGTH(x)        (((x) & 0xf) << 16)
 168 #define FLEXCAN_MB_CNT_TIMESTAMP(x)     ((x) & 0xffff)
 169
 170 #define FLEXCAN_TIMEOUT_US              (250)
 171
 172 /* FLEXCAN hardware feature flags
 173  *
 174  * Below is some version info we got:
 175  *    SOC   Version   IP-Version  Glitch- [TR]WRN_INT IRQ Err Memory err RTR re-
 176  *                                Filter? connected?  Passive detection  ception in MB
 177  *   MX25  FlexCAN2  03.00.00.00     no        no        no       no        no
 178  *   MX28  FlexCAN2  03.00.04.00    yes       yes        no       no        no
 179  *   MX35  FlexCAN2  03.00.00.00     no        no        no       no        no
 180  *   MX53  FlexCAN2  03.00.00.00    yes        no        no       no        no
 181  *   MX6s  FlexCAN3  10.00.12.00    yes       yes        no       no       yes
 182  *   VF610 FlexCAN3  ?               no       yes        no      yes       yes?
 183  * LS1021A FlexCAN2  03.00.04.00     no       yes        no       no       yes
 184  *
 185  * Some SOCs do not have the RX_WARN & TX_WARN interrupt line connected.
 186  */
 187 #define FLEXCAN_QUIRK_BROKEN_WERR_STATE BIT(1) /* [TR]WRN_INT not connected */
 188 #define FLEXCAN_QUIRK_DISABLE_RXFG      BIT(2) /* Disable RX FIFO Global mask */
 189 #define FLEXCAN_QUIRK_ENABLE_EACEN_RRS  BIT(3) /* Enable EACEN and RRS bit in ctrl2 */
 190 #define FLEXCAN_QUIRK_DISABLE_MECR      BIT(4) /* Disable Memory error detection */
 191 #define FLEXCAN_QUIRK_USE_OFF_TIMESTAMP BIT(5) /* Use timestamp based offloading */
 192 #define FLEXCAN_QUIRK_BROKEN_PERR_STATE BIT(6) /* No interrupt for error passive */
 193 #define FLEXCAN_QUIRK_DEFAULT_BIG_ENDIAN        BIT(7) /* default to BE register access */
 194 #define FLEXCAN_QUIRK_SETUP_STOP_MODE           BIT(8) /* Setup stop mode to support wakeup */
 195
 196 /* Structure of the message buffer */
 197 struct flexcan_mb {
 198         u32 can_ctrl;
 199         u32 can_id;
 200         u32 data[];
 201 };
 202
 203 /* Structure of the hardware registers */
 204 struct flexcan_regs {
 205         u32 mcr;                /* 0x00 */
 206         u32 ctrl;               /* 0x04 */
 207         u32 timer;              /* 0x08 */
 208         u32 _reserved1;         /* 0x0c */
 209         u32 rxgmask;            /* 0x10 */
 210         u32 rx14mask;           /* 0x14 */
 211         u32 rx15mask;           /* 0x18 */
 212         u32 ecr;                /* 0x1c */
 213         u32 esr;                /* 0x20 */
 214         u32 imask2;             /* 0x24 */
 215         u32 imask1;             /* 0x28 */
 216         u32 iflag2;             /* 0x2c */
 217         u32 iflag1;             /* 0x30 */
 218         union {                 /* 0x34 */
 219                 u32 gfwr_mx28;  /* MX28, MX53 */
 220                 u32 ctrl2;      /* MX6, VF610 */
 221         };
 222         u32 esr2;               /* 0x38 */
 223         u32 imeur;              /* 0x3c */
 224         u32 lrfr;               /* 0x40 */
 225         u32 crcr;               /* 0x44 */
 226         u32 rxfgmask;           /* 0x48 */
 227         u32 rxfir;              /* 0x4c */
 228         u32 _reserved3[12];     /* 0x50 */
 229         u8 mb[2][512];          /* 0x80 */
 230         /* FIFO-mode:
 231          *                      MB
 232          * 0x080...0x08f        0       RX message buffer
 233          * 0x090...0x0df        1-5     reserverd
 234          * 0x0e0...0x0ff        6-7     8 entry ID table
 235          *                              (mx25, mx28, mx35, mx53)
 236          * 0x0e0...0x2df        6-7..37 8..128 entry ID table
 237          *                              size conf'ed via ctrl2::RFFN
 238          *                              (mx6, vf610)
 239          */
 240         u32 _reserved4[256];    /* 0x480 */
 241         u32 rximr[64];          /* 0x880 */
 242         u32 _reserved5[24];     /* 0x980 */
 243         u32 gfwr_mx6;           /* 0x9e0 - MX6 */
 244         u32 _reserved6[63];     /* 0x9e4 */
 245         u32 mecr;               /* 0xae0 */
 246         u32 erriar;             /* 0xae4 */
 247         u32 erridpr;            /* 0xae8 */
 248         u32 errippr;            /* 0xaec */
 249         u32 rerrar;             /* 0xaf0 */
 250         u32 rerrdr;             /* 0xaf4 */
 251         u32 rerrsynr;           /* 0xaf8 */
 252         u32 errsr;              /* 0xafc */
 253 };
 254
 255 struct flexcan_devtype_data {
 256         u32 quirks;             /* quirks needed for different IP cores */
 257 };
 258
 259 struct flexcan_stop_mode {
 260         struct regmap *gpr;
 261         u8 req_gpr;
 262         u8 req_bit;
 263         u8 ack_gpr;
 264         u8 ack_bit;
 265 };
 266
 267 struct flexcan_priv {
 268         struct can_priv can;
 269         struct can_rx_offload offload;
 270         struct device *dev;
 271
 272         struct flexcan_regs __iomem *regs;
 273         struct flexcan_mb __iomem *tx_mb;
 274         struct flexcan_mb __iomem *tx_mb_reserved;
 275         u8 tx_mb_idx;
 276         u8 mb_count;
 277         u8 mb_size;
 278         u8 clk_src;     /* clock source of CAN Protocol Engine */
 279
 280         u64 rx_mask;
 281         u64 tx_mask;
 282         u32 reg_ctrl_default;
 283
 284         struct clk *clk_ipg;
 285         struct clk *clk_per;
 286         const struct flexcan_devtype_data *devtype_data;
 287         struct regulator *reg_xceiver;
 288         struct flexcan_stop_mode stm;
 289
 290         /* Read and Write APIs */
 291         u32 (*read)(void __iomem *addr);
 292         void (*write)(u32 val, void __iomem *addr);
 293 };
 294
 295 static const struct flexcan_devtype_data fsl_p1010_devtype_data = {
 296         .quirks = FLEXCAN_QUIRK_BROKEN_WERR_STATE |
 297                 FLEXCAN_QUIRK_BROKEN_PERR_STATE |
 298                 FLEXCAN_QUIRK_DEFAULT_BIG_ENDIAN,
 299 };
 300
 301 static const struct flexcan_devtype_data fsl_imx25_devtype_data = {
 302         .quirks = FLEXCAN_QUIRK_BROKEN_WERR_STATE |
 303                 FLEXCAN_QUIRK_BROKEN_PERR_STATE,
 304 };
 305
 306 static const struct flexcan_devtype_data fsl_imx28_devtype_data = {
 307         .quirks = FLEXCAN_QUIRK_BROKEN_PERR_STATE,
 308 };
 309
 310 static const struct flexcan_devtype_data fsl_imx6q_devtype_data = {
 311         .quirks = FLEXCAN_QUIRK_DISABLE_RXFG | FLEXCAN_QUIRK_ENABLE_EACEN_RRS |
 312                 FLEXCAN_QUIRK_USE_OFF_TIMESTAMP | FLEXCAN_QUIRK_BROKEN_PERR_STATE |
 313                 FLEXCAN_QUIRK_SETUP_STOP_MODE,
 314 };
 315
 316 static const struct flexcan_devtype_data fsl_vf610_devtype_data = {
 317         .quirks = FLEXCAN_QUIRK_DISABLE_RXFG | FLEXCAN_QUIRK_ENABLE_EACEN_RRS |
 318                 FLEXCAN_QUIRK_DISABLE_MECR | FLEXCAN_QUIRK_USE_OFF_TIMESTAMP |
 319                 FLEXCAN_QUIRK_BROKEN_PERR_STATE,
 320 };
 321
 322 static const struct flexcan_devtype_data fsl_ls1021a_r2_devtype_data = {
 323         .quirks = FLEXCAN_QUIRK_DISABLE_RXFG | FLEXCAN_QUIRK_ENABLE_EACEN_RRS |
 324                 FLEXCAN_QUIRK_DISABLE_MECR | FLEXCAN_QUIRK_BROKEN_PERR_STATE |
 325                 FLEXCAN_QUIRK_USE_OFF_TIMESTAMP,
 326 };
 327
 328 static const struct can_bittiming_const flexcan_bittiming_const = {
 329         .name = DRV_NAME,
 330         .tseg1_min = 4,
 331         .tseg1_max = 16,
 332         .tseg2_min = 2,
 333         .tseg2_max = 8,
 334         .sjw_max = 4,
 335         .brp_min = 1,
 336         .brp_max = 256,
 337         .brp_inc = 1,
 338 };
 339
 340 /* FlexCAN module is essentially modelled as a little-endian IP in most
 341  * SoCs, i.e the registers as well as the message buffer areas are
 342  * implemented in a little-endian fashion.
 343  *
 344  * However there are some SoCs (e.g. LS1021A) which implement the FlexCAN
 345  * module in a big-endian fashion (i.e the registers as well as the
 346  * message buffer areas are implemented in a big-endian way).
 347  *
 348  * In addition, the FlexCAN module can be found on SoCs having ARM or
 349  * PPC cores. So, we need to abstract off the register read/write
 350  * functions, ensuring that these cater to all the combinations of module
 351  * endianness and underlying CPU endianness.
 352  */
 353 static inline u32 flexcan_read_be(void __iomem *addr)
 354 {
 355         return ioread32be(addr);
 356 }
 357
 358 static inline void flexcan_write_be(u32 val, void __iomem *addr)
 359 {
 360         iowrite32be(val, addr);
 361 }
 362
 363 static inline u32 flexcan_read_le(void __iomem *addr)
 364 {
 365         return ioread32(addr);
 366 }
 367
 368 static inline void flexcan_write_le(u32 val, void __iomem *addr)
 369 {
 370         iowrite32(val, addr);
 371 }
 372
 373 static struct flexcan_mb __iomem *flexcan_get_mb(const struct flexcan_priv *priv,
 374                                                  u8 mb_index)
 375 {
 376         u8 bank_size;
 377         bool bank;
 378
 379         if (WARN_ON(mb_index >= priv->mb_count))
 380                 return NULL;
 381
 382         bank_size = sizeof(priv->regs->mb[0]) / priv->mb_size;
 383
 384         bank = mb_index >= bank_size;
 385         if (bank)
 386                 mb_index -= bank_size;
 387
 388         return (struct flexcan_mb __iomem *)
 389                 (&priv->regs->mb[bank][priv->mb_size * mb_index]);
 390 }
 391
 392 static int flexcan_low_power_enter_ack(struct flexcan_priv *priv)
 393 {
 394         struct flexcan_regs __iomem *regs = priv->regs;
 395         unsigned int timeout = FLEXCAN_TIMEOUT_US / 10;
 396
 397         while (timeout-- && !(priv->read(&regs->mcr) & FLEXCAN_MCR_LPM_ACK))
 398                 udelay(10);
 399
 400         if (!(priv->read(&regs->mcr) & FLEXCAN_MCR_LPM_ACK))
 401                 return -ETIMEDOUT;
 402
 403         return 0;
 404 }
 405
 406 static int flexcan_low_power_exit_ack(struct flexcan_priv *priv)
 407 {
 408         struct flexcan_regs __iomem *regs = priv->regs;
 409         unsigned int timeout = FLEXCAN_TIMEOUT_US / 10;
 410
 411         while (timeout-- && (priv->read(&regs->mcr) & FLEXCAN_MCR_LPM_ACK))
 412                 udelay(10);
 413
 414         if (priv->read(&regs->mcr) & FLEXCAN_MCR_LPM_ACK)
 415                 return -ETIMEDOUT;
 416
 417         return 0;
 418 }
 419
 420 static void flexcan_enable_wakeup_irq(struct flexcan_priv *priv, bool enable)
 421 {
 422         struct flexcan_regs __iomem *regs = priv->regs;
 423         u32 reg_mcr;
 424
 425         reg_mcr = priv->read(&regs->mcr);
 426
 427         if (enable)
 428                 reg_mcr |= FLEXCAN_MCR_WAK_MSK;
 429         else
 430                 reg_mcr &= ~FLEXCAN_MCR_WAK_MSK;
 431
 432         priv->write(reg_mcr, &regs->mcr);
 433 }
 434
 435 static inline int flexcan_enter_stop_mode(struct flexcan_priv *priv)
 436 {
 437         struct flexcan_regs __iomem *regs = priv->regs;
 438         u32 reg_mcr;
 439
 440         reg_mcr = priv->read(&regs->mcr);
 441         reg_mcr |= FLEXCAN_MCR_SLF_WAK;
 442         priv->write(reg_mcr, &regs->mcr);
 443
 444         /* enable stop request */
 445         regmap_update_bits(priv->stm.gpr, priv->stm.req_gpr,
 446                            1 << priv->stm.req_bit, 1 << priv->stm.req_bit);
 447
 448         return flexcan_low_power_enter_ack(priv);
 449 }
 450
 451 static inline int flexcan_exit_stop_mode(struct flexcan_priv *priv)
 452 {
 453         struct flexcan_regs __iomem *regs = priv->regs;
 454         u32 reg_mcr;
 455
 456         /* remove stop request */
 457         regmap_update_bits(priv->stm.gpr, priv->stm.req_gpr,
 458                            1 << priv->stm.req_bit, 0);
 459
 460
 461         reg_mcr = priv->read(&regs->mcr);
 462         reg_mcr &= ~FLEXCAN_MCR_SLF_WAK;
 463         priv->write(reg_mcr, &regs->mcr);
 464
 465         return flexcan_low_power_exit_ack(priv);
 466 }
 467
 468 static inline void flexcan_error_irq_enable(const struct flexcan_priv *priv)
 469 {
 470         struct flexcan_regs __iomem *regs = priv->regs;
 471         u32 reg_ctrl = (priv->reg_ctrl_default | FLEXCAN_CTRL_ERR_MSK);
 472
 473         priv->write(reg_ctrl, &regs->ctrl);
 474 }
 475
 476 static inline void flexcan_error_irq_disable(const struct flexcan_priv *priv)
 477 {
 478         struct flexcan_regs __iomem *regs = priv->regs;
 479         u32 reg_ctrl = (priv->reg_ctrl_default & ~FLEXCAN_CTRL_ERR_MSK);
 480
 481         priv->write(reg_ctrl, &regs->ctrl);
 482 }
 483
 484 static int flexcan_clks_enable(const struct flexcan_priv *priv)
 485 {
 486         int err;
 487
 488         err = clk_prepare_enable(priv->clk_ipg);
 489         if (err)
 490                 return err;
 491
 492         err = clk_prepare_enable(priv->clk_per);
 493         if (err)
 494                 clk_disable_unprepare(priv->clk_ipg);
 495
 496         return err;
 497 }
 498
 499 static void flexcan_clks_disable(const struct flexcan_priv *priv)
 500 {
 501         clk_disable_unprepare(priv->clk_per);
 502         clk_disable_unprepare(priv->clk_ipg);
 503 }
 504
 505 static inline int flexcan_transceiver_enable(const struct flexcan_priv *priv)
 506 {
 507         if (!priv->reg_xceiver)
 508                 return 0;
 509
 510         return regulator_enable(priv->reg_xceiver);
 511 }
 512
 513 static inline int flexcan_transceiver_disable(const struct flexcan_priv *priv)
 514 {
 515         if (!priv->reg_xceiver)
 516                 return 0;
 517
 518         return regulator_disable(priv->reg_xceiver);
 519 }
 520
 521 static int flexcan_chip_enable(struct flexcan_priv *priv)
 522 {
 523         struct flexcan_regs __iomem *regs = priv->regs;
 524         u32 reg;
 525
 526         reg = priv->read(&regs->mcr);
 527         reg &= ~FLEXCAN_MCR_MDIS;
 528         priv->write(reg, &regs->mcr);
 529
 530         return flexcan_low_power_exit_ack(priv);
 531 }
 532
 533 static int flexcan_chip_disable(struct flexcan_priv *priv)
 534 {
 535         struct flexcan_regs __iomem *regs = priv->regs;
 536         u32 reg;
 537
 538         reg = priv->read(&regs->mcr);
 539         reg |= FLEXCAN_MCR_MDIS;
 540         priv->write(reg, &regs->mcr);
 541
 542         return flexcan_low_power_enter_ack(priv);
 543 }
 544
 545 static int flexcan_chip_freeze(struct flexcan_priv *priv)
 546 {
 547         struct flexcan_regs __iomem *regs = priv->regs;
 548         unsigned int timeout = 1000 * 1000 * 10 / priv->can.bittiming.bitrate;
 549         u32 reg;
 550
 551         reg = priv->read(&regs->mcr);
 552         reg |= FLEXCAN_MCR_HALT;
 553         priv->write(reg, &regs->mcr);
 554
 555         while (timeout-- && !(priv->read(&regs->mcr) & FLEXCAN_MCR_FRZ_ACK))
 556                 udelay(100);
 557
 558         if (!(priv->read(&regs->mcr) & FLEXCAN_MCR_FRZ_ACK))
 559                 return -ETIMEDOUT;
 560
 561         return 0;
 562 }
 563
 564 static int flexcan_chip_unfreeze(struct flexcan_priv *priv)
 565 {
 566         struct flexcan_regs __iomem *regs = priv->regs;
 567         unsigned int timeout = FLEXCAN_TIMEOUT_US / 10;
 568         u32 reg;
 569
 570         reg = priv->read(&regs->mcr);
 571         reg &= ~FLEXCAN_MCR_HALT;
 572         priv->write(reg, &regs->mcr);
 573
 574         while (timeout-- && (priv->read(&regs->mcr) & FLEXCAN_MCR_FRZ_ACK))
 575                 udelay(10);
 576
 577         if (priv->read(&regs->mcr) & FLEXCAN_MCR_FRZ_ACK)
 578                 return -ETIMEDOUT;
 579
 580         return 0;
 581 }
 582
 583 static int flexcan_chip_softreset(struct flexcan_priv *priv)
 584 {
 585         struct flexcan_regs __iomem *regs = priv->regs;
 586         unsigned int timeout = FLEXCAN_TIMEOUT_US / 10;
 587
 588         priv->write(FLEXCAN_MCR_SOFTRST, &regs->mcr);
 589         while (timeout-- && (priv->read(&regs->mcr) & FLEXCAN_MCR_SOFTRST))
 590                 udelay(10);
 591
 592         if (priv->read(&regs->mcr) & FLEXCAN_MCR_SOFTRST)
 593                 return -ETIMEDOUT;
 594
 595         return 0;
 596 }
 597
 598 static int __flexcan_get_berr_counter(const struct net_device *dev,
 599                                       struct can_berr_counter *bec)
 600 {
 601         const struct flexcan_priv *priv = netdev_priv(dev);
 602         struct flexcan_regs __iomem *regs = priv->regs;
 603         u32 reg = priv->read(&regs->ecr);
 604
 605         bec->txerr = (reg >> 0) & 0xff;
 606         bec->rxerr = (reg >> 8) & 0xff;
 607
 608         return 0;
 609 }
 610
 611 static int flexcan_get_berr_counter(const struct net_device *dev,
 612                                     struct can_berr_counter *bec)
 613 {
 614         const struct flexcan_priv *priv = netdev_priv(dev);
 615         int err;
 616
 617         err = pm_runtime_get_sync(priv->dev);
 618         if (err < 0)
 619                 return err;
 620
 621         err = __flexcan_get_berr_counter(dev, bec);
 622
 623         pm_runtime_put(priv->dev);
 624
 625         return err;
 626 }
 627
 628 static netdev_tx_t flexcan_start_xmit(struct sk_buff *skb, struct net_device *dev)
 629 {
 630         const struct flexcan_priv *priv = netdev_priv(dev);
 631         struct can_frame *cf = (struct can_frame *)skb->data;
 632         u32 can_id;
 633         u32 data;
 634         u32 ctrl = FLEXCAN_MB_CODE_TX_DATA | (cf->can_dlc << 16);
 635         int i;
 636
 637         if (can_dropped_invalid_skb(dev, skb))
 638                 return NETDEV_TX_OK;
 639
 640         netif_stop_queue(dev);
 641
 642         if (cf->can_id & CAN_EFF_FLAG) {
 643                 can_id = cf->can_id & CAN_EFF_MASK;
 644                 ctrl |= FLEXCAN_MB_CNT_IDE | FLEXCAN_MB_CNT_SRR;
 645         } else {
 646                 can_id = (cf->can_id & CAN_SFF_MASK) << 18;
 647         }
 648
 649         if (cf->can_id & CAN_RTR_FLAG)
 650                 ctrl |= FLEXCAN_MB_CNT_RTR;
 651
 652         for (i = 0; i < cf->can_dlc; i += sizeof(u32)) {
 653                 data = be32_to_cpup((__be32 *)&cf->data[i]);
 654                 priv->write(data, &priv->tx_mb->data[i / sizeof(u32)]);
 655         }
 656
 657         can_put_echo_skb(skb, dev, 0);
 658
 659         priv->write(can_id, &priv->tx_mb->can_id);
 660         priv->write(ctrl, &priv->tx_mb->can_ctrl);
 661
 662         /* Errata ERR005829 step8:
 663          * Write twice INACTIVE(0x8) code to first MB.
 664          */
 665         priv->write(FLEXCAN_MB_CODE_TX_INACTIVE,
 666                     &priv->tx_mb_reserved->can_ctrl);
 667         priv->write(FLEXCAN_MB_CODE_TX_INACTIVE,
 668                     &priv->tx_mb_reserved->can_ctrl);
 669
 670         return NETDEV_TX_OK;
 671 }
 672
 673 static void flexcan_irq_bus_err(struct net_device *dev, u32 reg_esr)
 674 {
 675         struct flexcan_priv *priv = netdev_priv(dev);
 676         struct flexcan_regs __iomem *regs = priv->regs;
 677         struct sk_buff *skb;
 678         struct can_frame *cf;
 679         bool rx_errors = false, tx_errors = false;
 680         u32 timestamp;
 681         int err;
 682
 683         timestamp = priv->read(&regs->timer) << 16;
 684
 685         skb = alloc_can_err_skb(dev, &cf);
 686         if (unlikely(!skb))
 687                 return;
 688
 689         cf->can_id |= CAN_ERR_PROT | CAN_ERR_BUSERROR;
 690
 691         if (reg_esr & FLEXCAN_ESR_BIT1_ERR) {
 692                 netdev_dbg(dev, "BIT1_ERR irq\n");
 693                 cf->data[2] |= CAN_ERR_PROT_BIT1;
 694                 tx_errors = true;
 695         }
 696         if (reg_esr & FLEXCAN_ESR_BIT0_ERR) {
 697                 netdev_dbg(dev, "BIT0_ERR irq\n");
 698                 cf->data[2] |= CAN_ERR_PROT_BIT0;
 699                 tx_errors = true;
 700         }
 701         if (reg_esr & FLEXCAN_ESR_ACK_ERR) {
 702                 netdev_dbg(dev, "ACK_ERR irq\n");
 703                 cf->can_id |= CAN_ERR_ACK;
 704                 cf->data[3] = CAN_ERR_PROT_LOC_ACK;
 705                 tx_errors = true;
 706         }
 707         if (reg_esr & FLEXCAN_ESR_CRC_ERR) {
 708                 netdev_dbg(dev, "CRC_ERR irq\n");
 709                 cf->data[2] |= CAN_ERR_PROT_BIT;
 710                 cf->data[3] = CAN_ERR_PROT_LOC_CRC_SEQ;
 711                 rx_errors = true;
 712         }
 713         if (reg_esr & FLEXCAN_ESR_FRM_ERR) {
 714                 netdev_dbg(dev, "FRM_ERR irq\n");
 715                 cf->data[2] |= CAN_ERR_PROT_FORM;
 716                 rx_errors = true;
 717         }
 718         if (reg_esr & FLEXCAN_ESR_STF_ERR) {
 719                 netdev_dbg(dev, "STF_ERR irq\n");
 720                 cf->data[2] |= CAN_ERR_PROT_STUFF;
 721                 rx_errors = true;
 722         }
 723
 724         priv->can.can_stats.bus_error++;
 725         if (rx_errors)
 726                 dev->stats.rx_errors++;
 727         if (tx_errors)
 728                 dev->stats.tx_errors++;
 729
 730         err = can_rx_offload_queue_sorted(&priv->offload, skb, timestamp);
 731         if (err)
 732                 dev->stats.rx_fifo_errors++;
 733 }
 734
 735 static void flexcan_irq_state(struct net_device *dev, u32 reg_esr)
 736 {
 737         struct flexcan_priv *priv = netdev_priv(dev);
 738         struct flexcan_regs __iomem *regs = priv->regs;
 739         struct sk_buff *skb;
 740         struct can_frame *cf;
 741         enum can_state new_state, rx_state, tx_state;
 742         int flt;
 743         struct can_berr_counter bec;
 744         u32 timestamp;
 745         int err;
 746
 747         flt = reg_esr & FLEXCAN_ESR_FLT_CONF_MASK;
 748         if (likely(flt == FLEXCAN_ESR_FLT_CONF_ACTIVE)) {
 749                 tx_state = unlikely(reg_esr & FLEXCAN_ESR_TX_WRN) ?
 750                         CAN_STATE_ERROR_WARNING : CAN_STATE_ERROR_ACTIVE;
 751                 rx_state = unlikely(reg_esr & FLEXCAN_ESR_RX_WRN) ?
 752                         CAN_STATE_ERROR_WARNING : CAN_STATE_ERROR_ACTIVE;
 753                 new_state = max(tx_state, rx_state);
 754         } else {
 755                 __flexcan_get_berr_counter(dev, &bec);
 756                 new_state = flt == FLEXCAN_ESR_FLT_CONF_PASSIVE ?
 757                         CAN_STATE_ERROR_PASSIVE : CAN_STATE_BUS_OFF;
 758                 rx_state = bec.rxerr >= bec.txerr ? new_state : 0;
 759                 tx_state = bec.rxerr <= bec.txerr ? new_state : 0;
 760         }
 761
 762         /* state hasn't changed */
 763         if (likely(new_state == priv->can.state))
 764                 return;
 765
 766         timestamp = priv->read(&regs->timer) << 16;
 767
 768         skb = alloc_can_err_skb(dev, &cf);
 769         if (unlikely(!skb))
 770                 return;
 771
 772         can_change_state(dev, cf, tx_state, rx_state);
 773
 774         if (unlikely(new_state == CAN_STATE_BUS_OFF))
 775                 can_bus_off(dev);
 776
 777         err = can_rx_offload_queue_sorted(&priv->offload, skb, timestamp);
 778         if (err)
 779                 dev->stats.rx_fifo_errors++;
 780 }
 781
 782 static inline u64 flexcan_read64_mask(struct flexcan_priv *priv, void __iomem *addr, u64 mask)
 783 {
 784         u64 reg = 0;
 785
 786         if (upper_32_bits(mask))
 787                 reg = (u64)priv->read(addr - 4) << 32;
 788         if (lower_32_bits(mask))
 789                 reg |= priv->read(addr);
 790
 791         return reg & mask;
 792 }
 793
 794 static inline void flexcan_write64(struct flexcan_priv *priv, u64 val, void __iomem *addr)
 795 {
 796         if (upper_32_bits(val))
 797                 priv->write(upper_32_bits(val), addr - 4);
 798         if (lower_32_bits(val))
 799                 priv->write(lower_32_bits(val), addr);
 800 }
 801
 802 static inline u64 flexcan_read_reg_iflag_rx(struct flexcan_priv *priv)
 803 {
 804         return flexcan_read64_mask(priv, &priv->regs->iflag1, priv->rx_mask);
 805 }
 806
 807 static inline u64 flexcan_read_reg_iflag_tx(struct flexcan_priv *priv)
 808 {
 809         return flexcan_read64_mask(priv, &priv->regs->iflag1, priv->tx_mask);
 810 }
 811
 812 static inline struct flexcan_priv *rx_offload_to_priv(struct can_rx_offload *offload)
 813 {
 814         return container_of(offload, struct flexcan_priv, offload);
 815 }
 816
 817 static struct sk_buff *flexcan_mailbox_read(struct can_rx_offload *offload,
 818                                             unsigned int n, u32 *timestamp,
 819                                             bool drop)
 820 {
 821         struct flexcan_priv *priv = rx_offload_to_priv(offload);
 822         struct flexcan_regs __iomem *regs = priv->regs;
 823         struct flexcan_mb __iomem *mb;
 824         struct sk_buff *skb;
 825         struct can_frame *cf;
 826         u32 reg_ctrl, reg_id, reg_iflag1;
 827         int i;
 828
 829         if (unlikely(drop)) {
 830                 skb = ERR_PTR(-ENOBUFS);
 831                 goto mark_as_read;
 832         }
 833
 834         mb = flexcan_get_mb(priv, n);
 835
 836         if (priv->devtype_data->quirks & FLEXCAN_QUIRK_USE_OFF_TIMESTAMP) {
 837                 u32 code;
 838
 839                 do {
 840                         reg_ctrl = priv->read(&mb->can_ctrl);
 841                 } while (reg_ctrl & FLEXCAN_MB_CODE_RX_BUSY_BIT);
 842
 843                 /* is this MB empty? */
 844                 code = reg_ctrl & FLEXCAN_MB_CODE_MASK;
 845                 if ((code != FLEXCAN_MB_CODE_RX_FULL) &&
 846                     (code != FLEXCAN_MB_CODE_RX_OVERRUN))
 847                         return NULL;
 848
 849                 if (code == FLEXCAN_MB_CODE_RX_OVERRUN) {
 850                         /* This MB was overrun, we lost data */
 851                         offload->dev->stats.rx_over_errors++;
 852                         offload->dev->stats.rx_errors++;
 853                 }
 854         } else {
 855                 reg_iflag1 = priv->read(&regs->iflag1);
 856                 if (!(reg_iflag1 & FLEXCAN_IFLAG_RX_FIFO_AVAILABLE))
 857                         return NULL;
 858
 859                 reg_ctrl = priv->read(&mb->can_ctrl);
 860         }
 861
 862         skb = alloc_can_skb(offload->dev, &cf);
 863         if (!skb) {
 864                 skb = ERR_PTR(-ENOMEM);
 865                 goto mark_as_read;
 866         }
 867
 868         /* increase timstamp to full 32 bit */
 869         *timestamp = reg_ctrl << 16;
 870
 871         reg_id = priv->read(&mb->can_id);
 872         if (reg_ctrl & FLEXCAN_MB_CNT_IDE)
 873                 cf->can_id = ((reg_id >> 0) & CAN_EFF_MASK) | CAN_EFF_FLAG;
 874         else
 875                 cf->can_id = (reg_id >> 18) & CAN_SFF_MASK;
 876
 877         if (reg_ctrl & FLEXCAN_MB_CNT_RTR)
 878                 cf->can_id |= CAN_RTR_FLAG;
 879         cf->can_dlc = get_can_dlc((reg_ctrl >> 16) & 0xf);
 880
 881         for (i = 0; i < cf->can_dlc; i += sizeof(u32)) {
 882                 __be32 data = cpu_to_be32(priv->read(&mb->data[i / sizeof(u32)]));
 883                 *(__be32 *)(cf->data + i) = data;
 884         }
 885
 886  mark_as_read:
 887         if (priv->devtype_data->quirks & FLEXCAN_QUIRK_USE_OFF_TIMESTAMP)
 888                 flexcan_write64(priv, FLEXCAN_IFLAG_MB(n), &regs->iflag1);
 889         else
 890                 priv->write(FLEXCAN_IFLAG_RX_FIFO_AVAILABLE, &regs->iflag1);
 891
 892         /* Read the Free Running Timer. It is optional but recommended
 893          * to unlock Mailbox as soon as possible and make it available
 894          * for reception.
 895          */
 896         priv->read(&regs->timer);
 897
 898         return skb;
 899 }
 900
 901 static irqreturn_t flexcan_irq(int irq, void *dev_id)
 902 {
 903         struct net_device *dev = dev_id;
 904         struct net_device_stats *stats = &dev->stats;
 905         struct flexcan_priv *priv = netdev_priv(dev);
 906         struct flexcan_regs __iomem *regs = priv->regs;
 907         irqreturn_t handled = IRQ_NONE;
 908         u64 reg_iflag_tx;
 909         u32 reg_esr;
 910         enum can_state last_state = priv->can.state;
 911
 912         /* reception interrupt */
 913         if (priv->devtype_data->quirks & FLEXCAN_QUIRK_USE_OFF_TIMESTAMP) {
 914                 u64 reg_iflag_rx;
 915                 int ret;
 916
 917                 while ((reg_iflag_rx = flexcan_read_reg_iflag_rx(priv))) {
 918                         handled = IRQ_HANDLED;
 919                         ret = can_rx_offload_irq_offload_timestamp(&priv->offload,
 920                                                                    reg_iflag_rx);
 921                         if (!ret)
 922                                 break;
 923                 }
 924         } else {
 925                 u32 reg_iflag1;
 926
 927                 reg_iflag1 = priv->read(&regs->iflag1);
 928                 if (reg_iflag1 & FLEXCAN_IFLAG_RX_FIFO_AVAILABLE) {
 929                         handled = IRQ_HANDLED;
 930                         can_rx_offload_irq_offload_fifo(&priv->offload);
 931                 }
 932
 933                 /* FIFO overflow interrupt */
 934                 if (reg_iflag1 & FLEXCAN_IFLAG_RX_FIFO_OVERFLOW) {
 935                         handled = IRQ_HANDLED;
 936                         priv->write(FLEXCAN_IFLAG_RX_FIFO_OVERFLOW,
 937                                     &regs->iflag1);
 938                         dev->stats.rx_over_errors++;
 939                         dev->stats.rx_errors++;
 940                 }
 941         }
 942
 943         reg_iflag_tx = flexcan_read_reg_iflag_tx(priv);
 944
 945         /* transmission complete interrupt */
 946         if (reg_iflag_tx & priv->tx_mask) {
 947                 u32 reg_ctrl = priv->read(&priv->tx_mb->can_ctrl);
 948
 949                 handled = IRQ_HANDLED;
 950                 stats->tx_bytes += can_rx_offload_get_echo_skb(&priv->offload,
 951                                                                0, reg_ctrl << 16);
 952                 stats->tx_packets++;
 953                 can_led_event(dev, CAN_LED_EVENT_TX);
 954
 955                 /* after sending a RTR frame MB is in RX mode */
 956                 priv->write(FLEXCAN_MB_CODE_TX_INACTIVE,
 957                             &priv->tx_mb->can_ctrl);
 958                 flexcan_write64(priv, priv->tx_mask, &regs->iflag1);
 959                 netif_wake_queue(dev);
 960         }
 961
 962         reg_esr = priv->read(&regs->esr);
 963
 964         /* ACK all bus error and state change IRQ sources */
 965         if (reg_esr & FLEXCAN_ESR_ALL_INT) {
 966                 handled = IRQ_HANDLED;
 967                 priv->write(reg_esr & FLEXCAN_ESR_ALL_INT, &regs->esr);
 968         }
 969
 970         /* state change interrupt or broken error state quirk fix is enabled */
 971         if ((reg_esr & FLEXCAN_ESR_ERR_STATE) ||
 972             (priv->devtype_data->quirks & (FLEXCAN_QUIRK_BROKEN_WERR_STATE |
 973                                            FLEXCAN_QUIRK_BROKEN_PERR_STATE)))
 974                 flexcan_irq_state(dev, reg_esr);
 975
 976         /* bus error IRQ - handle if bus error reporting is activated */
 977         if ((reg_esr & FLEXCAN_ESR_ERR_BUS) &&
 978             (priv->can.ctrlmode & CAN_CTRLMODE_BERR_REPORTING))
 979                 flexcan_irq_bus_err(dev, reg_esr);
 980
 981         /* availability of error interrupt among state transitions in case
 982          * bus error reporting is de-activated and
 983          * FLEXCAN_QUIRK_BROKEN_PERR_STATE is enabled:
 984          *  +--------------------------------------------------------------+
 985          *  | +----------------------------------------------+ [stopped /  |
 986          *  | |                                              |  sleeping] -+
 987          *  +-+-> active <-> warning <-> passive -> bus off -+
 988          *        ___________^^^^^^^^^^^^_______________________________
 989          *        disabled(1)  enabled             disabled
 990          *
 991          * (1): enabled if FLEXCAN_QUIRK_BROKEN_WERR_STATE is enabled
 992          */
 993         if ((last_state != priv->can.state) &&
 994             (priv->devtype_data->quirks & FLEXCAN_QUIRK_BROKEN_PERR_STATE) &&
 995             !(priv->can.ctrlmode & CAN_CTRLMODE_BERR_REPORTING)) {
 996                 switch (priv->can.state) {
 997                 case CAN_STATE_ERROR_ACTIVE:
 998                         if (priv->devtype_data->quirks &
 999                             FLEXCAN_QUIRK_BROKEN_WERR_STATE)
1000                                 flexcan_error_irq_enable(priv);
1001                         else
1002                                 flexcan_error_irq_disable(priv);
1003                         break;
1004
1005                 case CAN_STATE_ERROR_WARNING:
1006                         flexcan_error_irq_enable(priv);
1007                         break;
1008
1009                 case CAN_STATE_ERROR_PASSIVE:
1010                 case CAN_STATE_BUS_OFF:
1011                         flexcan_error_irq_disable(priv);
1012                         break;
1013
1014                 default:
1015                         break;
1016                 }
1017         }
1018
1019         return handled;
1020 }
1021
1022 static void flexcan_set_bittiming(struct net_device *dev)
1023 {
1024         const struct flexcan_priv *priv = netdev_priv(dev);
1025         const struct can_bittiming *bt = &priv->can.bittiming;
1026         struct flexcan_regs __iomem *regs = priv->regs;
1027         u32 reg;
1028
1029         reg = priv->read(&regs->ctrl);
1030         reg &= ~(FLEXCAN_CTRL_PRESDIV(0xff) |
1031                  FLEXCAN_CTRL_RJW(0x3) |
1032                  FLEXCAN_CTRL_PSEG1(0x7) |
1033                  FLEXCAN_CTRL_PSEG2(0x7) |
1034                  FLEXCAN_CTRL_PROPSEG(0x7) |
1035                  FLEXCAN_CTRL_LPB |
1036                  FLEXCAN_CTRL_SMP |
1037                  FLEXCAN_CTRL_LOM);
1038
1039         reg |= FLEXCAN_CTRL_PRESDIV(bt->brp - 1) |
1040                 FLEXCAN_CTRL_PSEG1(bt->phase_seg1 - 1) |
1041                 FLEXCAN_CTRL_PSEG2(bt->phase_seg2 - 1) |
1042                 FLEXCAN_CTRL_RJW(bt->sjw - 1) |
1043                 FLEXCAN_CTRL_PROPSEG(bt->prop_seg - 1);
1044
1045         if (priv->can.ctrlmode & CAN_CTRLMODE_LOOPBACK)
1046                 reg |= FLEXCAN_CTRL_LPB;
1047         if (priv->can.ctrlmode & CAN_CTRLMODE_LISTENONLY)
1048                 reg |= FLEXCAN_CTRL_LOM;
1049         if (priv->can.ctrlmode & CAN_CTRLMODE_3_SAMPLES)
1050                 reg |= FLEXCAN_CTRL_SMP;
1051
1052         netdev_dbg(dev, "writing ctrl=0x%08x\n", reg);
1053         priv->write(reg, &regs->ctrl);
1054
1055         /* print chip status */
1056         netdev_dbg(dev, "%s: mcr=0x%08x ctrl=0x%08x\n", __func__,
1057                    priv->read(&regs->mcr), priv->read(&regs->ctrl));
1058 }
1059
1060 /* flexcan_chip_start
1061  *
1062  * this functions is entered with clocks enabled
1063  *
1064  */
1065 static int flexcan_chip_start(struct net_device *dev)
1066 {
1067         struct flexcan_priv *priv = netdev_priv(dev);
1068         struct flexcan_regs __iomem *regs = priv->regs;
1069         u32 reg_mcr, reg_ctrl, reg_ctrl2, reg_mecr;
1070         u64 reg_imask;
1071         int err, i;
1072         struct flexcan_mb __iomem *mb;
1073
1074         /* enable module */
1075         err = flexcan_chip_enable(priv);
1076         if (err)
1077                 return err;
1078
1079         /* soft reset */
1080         err = flexcan_chip_softreset(priv);
1081         if (err)
1082                 goto out_chip_disable;
1083
1084         flexcan_set_bittiming(dev);
1085
1086         /* MCR
1087          *
1088          * enable freeze
1089          * halt now
1090          * only supervisor access
1091          * enable warning int
1092          * enable individual RX masking
1093          * choose format C
1094          * set max mailbox number
1095          */
1096         reg_mcr = priv->read(&regs->mcr);
1097         reg_mcr &= ~FLEXCAN_MCR_MAXMB(0xff);
1098         reg_mcr |= FLEXCAN_MCR_FRZ | FLEXCAN_MCR_HALT | FLEXCAN_MCR_SUPV |
1099                 FLEXCAN_MCR_WRN_EN | FLEXCAN_MCR_IRMQ | FLEXCAN_MCR_IDAM_C |
1100                 FLEXCAN_MCR_MAXMB(priv->tx_mb_idx);
1101
1102         /* MCR
1103          *
1104          * FIFO:
1105          * - disable for timestamp mode
1106          * - enable for FIFO mode
1107          */
1108         if (priv->devtype_data->quirks & FLEXCAN_QUIRK_USE_OFF_TIMESTAMP)
1109                 reg_mcr &= ~FLEXCAN_MCR_FEN;
1110         else
1111                 reg_mcr |= FLEXCAN_MCR_FEN;
1112
1113         /* MCR
1114          *
1115          * NOTE: In loopback mode, the CAN_MCR[SRXDIS] cannot be
1116          *       asserted because this will impede the self reception
1117          *       of a transmitted message. This is not documented in
1118          *       earlier versions of flexcan block guide.
1119          *
1120          * Self Reception:
1121          * - enable Self Reception for loopback mode
1122          *   (by clearing "Self Reception Disable" bit)
1123          * - disable for normal operation
1124          */
1125         if (priv->can.ctrlmode & CAN_CTRLMODE_LOOPBACK)
1126                 reg_mcr &= ~FLEXCAN_MCR_SRX_DIS;
1127         else
1128                 reg_mcr |= FLEXCAN_MCR_SRX_DIS;
1129
1130         netdev_dbg(dev, "%s: writing mcr=0x%08x", __func__, reg_mcr);
1131         priv->write(reg_mcr, &regs->mcr);
1132
1133         /* CTRL
1134          *
1135          * disable timer sync feature
1136          *
1137          * disable auto busoff recovery
1138          * transmit lowest buffer first
1139          *
1140          * enable tx and rx warning interrupt
1141          * enable bus off interrupt
1142          * (== FLEXCAN_CTRL_ERR_STATE)
1143          */
1144         reg_ctrl = priv->read(&regs->ctrl);
1145         reg_ctrl &= ~FLEXCAN_CTRL_TSYN;
1146         reg_ctrl |= FLEXCAN_CTRL_BOFF_REC | FLEXCAN_CTRL_LBUF |
1147                 FLEXCAN_CTRL_ERR_STATE;
1148
1149         /* enable the "error interrupt" (FLEXCAN_CTRL_ERR_MSK),
1150          * on most Flexcan cores, too. Otherwise we don't get
1151          * any error warning or passive interrupts.
1152          */
1153         if (priv->devtype_data->quirks & FLEXCAN_QUIRK_BROKEN_WERR_STATE ||
1154             priv->can.ctrlmode & CAN_CTRLMODE_BERR_REPORTING)
1155                 reg_ctrl |= FLEXCAN_CTRL_ERR_MSK;
1156         else
1157                 reg_ctrl &= ~FLEXCAN_CTRL_ERR_MSK;
1158
1159         /* save for later use */
1160         priv->reg_ctrl_default = reg_ctrl;
1161         /* leave interrupts disabled for now */
1162         reg_ctrl &= ~FLEXCAN_CTRL_ERR_ALL;
1163         netdev_dbg(dev, "%s: writing ctrl=0x%08x", __func__, reg_ctrl);
1164         priv->write(reg_ctrl, &regs->ctrl);
1165
1166         if ((priv->devtype_data->quirks & FLEXCAN_QUIRK_ENABLE_EACEN_RRS)) {
1167                 reg_ctrl2 = priv->read(&regs->ctrl2);
1168                 reg_ctrl2 |= FLEXCAN_CTRL2_EACEN | FLEXCAN_CTRL2_RRS;
1169                 priv->write(reg_ctrl2, &regs->ctrl2);
1170         }
1171
1172         if (priv->devtype_data->quirks & FLEXCAN_QUIRK_USE_OFF_TIMESTAMP) {
1173                 for (i = priv->offload.mb_first; i <= priv->offload.mb_last; i++) {
1174                         mb = flexcan_get_mb(priv, i);
1175                         priv->write(FLEXCAN_MB_CODE_RX_EMPTY,
1176                                     &mb->can_ctrl);
1177                 }
1178         } else {
1179                 /* clear and invalidate unused mailboxes first */
1180                 for (i = FLEXCAN_TX_MB_RESERVED_OFF_FIFO; i < priv->mb_count; i++) {
1181                         mb = flexcan_get_mb(priv, i);
1182                         priv->write(FLEXCAN_MB_CODE_RX_INACTIVE,
1183                                     &mb->can_ctrl);
1184                 }
1185         }
1186
1187         /* Errata ERR005829: mark first TX mailbox as INACTIVE */
1188         priv->write(FLEXCAN_MB_CODE_TX_INACTIVE,
1189                     &priv->tx_mb_reserved->can_ctrl);
1190
1191         /* mark TX mailbox as INACTIVE */
1192         priv->write(FLEXCAN_MB_CODE_TX_INACTIVE,
1193                     &priv->tx_mb->can_ctrl);
1194
1195         /* acceptance mask/acceptance code (accept everything) */
1196         priv->write(0x0, &regs->rxgmask);
1197         priv->write(0x0, &regs->rx14mask);
1198         priv->write(0x0, &regs->rx15mask);
1199
1200         if (priv->devtype_data->quirks & FLEXCAN_QUIRK_DISABLE_RXFG)
1201                 priv->write(0x0, &regs->rxfgmask);
1202
1203         /* clear acceptance filters */
1204         for (i = 0; i < priv->mb_count; i++)
1205                 priv->write(0, &regs->rximr[i]);
1206
1207         /* On Vybrid, disable memory error detection interrupts
1208          * and freeze mode.
1209          * This also works around errata e5295 which generates
1210          * false positive memory errors and put the device in
1211          * freeze mode.
1212          */
1213         if (priv->devtype_data->quirks & FLEXCAN_QUIRK_DISABLE_MECR) {
1214                 /* Follow the protocol as described in "Detection
1215                  * and Correction of Memory Errors" to write to
1216                  * MECR register
1217                  */
1218                 reg_ctrl2 = priv->read(&regs->ctrl2);
1219                 reg_ctrl2 |= FLEXCAN_CTRL2_ECRWRE;
1220                 priv->write(reg_ctrl2, &regs->ctrl2);
1221
1222                 reg_mecr = priv->read(&regs->mecr);
1223                 reg_mecr &= ~FLEXCAN_MECR_ECRWRDIS;
1224                 priv->write(reg_mecr, &regs->mecr);
1225                 reg_mecr |= FLEXCAN_MECR_ECCDIS;
1226                 reg_mecr &= ~(FLEXCAN_MECR_NCEFAFRZ | FLEXCAN_MECR_HANCEI_MSK |
1227                               FLEXCAN_MECR_FANCEI_MSK);
1228                 priv->write(reg_mecr, &regs->mecr);
1229         }
1230
1231         err = flexcan_transceiver_enable(priv);
1232         if (err)
1233                 goto out_chip_disable;
1234
1235         /* synchronize with the can bus */
1236         err = flexcan_chip_unfreeze(priv);
1237         if (err)
1238                 goto out_transceiver_disable;
1239
1240         priv->can.state = CAN_STATE_ERROR_ACTIVE;
1241
1242         /* enable interrupts atomically */
1243         disable_irq(dev->irq);
1244         priv->write(priv->reg_ctrl_default, &regs->ctrl);
1245         reg_imask = priv->rx_mask | priv->tx_mask;
1246         priv->write(upper_32_bits(reg_imask), &regs->imask2);
1247         priv->write(lower_32_bits(reg_imask), &regs->imask1);
1248         enable_irq(dev->irq);
1249
1250         /* print chip status */
1251         netdev_dbg(dev, "%s: reading mcr=0x%08x ctrl=0x%08x\n", __func__,
1252                    priv->read(&regs->mcr), priv->read(&regs->ctrl));
1253
1254         return 0;
1255
1256  out_transceiver_disable:
1257         flexcan_transceiver_disable(priv);
1258  out_chip_disable:
1259         flexcan_chip_disable(priv);
1260         return err;
1261 }
1262
1263 /* flexcan_chip_stop
1264  *
1265  * this functions is entered with clocks enabled
1266  */
1267 static void flexcan_chip_stop(struct net_device *dev)
1268 {
1269         struct flexcan_priv *priv = netdev_priv(dev);
1270         struct flexcan_regs __iomem *regs = priv->regs;
1271
1272         /* freeze + disable module */
1273         flexcan_chip_freeze(priv);
1274         flexcan_chip_disable(priv);
1275
1276         /* Disable all interrupts */
1277         priv->write(0, &regs->imask2);
1278         priv->write(0, &regs->imask1);
1279         priv->write(priv->reg_ctrl_default & ~FLEXCAN_CTRL_ERR_ALL,
1280                     &regs->ctrl);
1281
1282         flexcan_transceiver_disable(priv);
1283         priv->can.state = CAN_STATE_STOPPED;
1284 }
1285
1286 static int flexcan_open(struct net_device *dev)
1287 {
1288         struct flexcan_priv *priv = netdev_priv(dev);
1289         int err;
1290
1291         err = pm_runtime_get_sync(priv->dev);
1292         if (err < 0)
1293                 return err;
1294
1295         err = open_candev(dev);
1296         if (err)
1297                 goto out_runtime_put;
1298
1299         err = request_irq(dev->irq, flexcan_irq, IRQF_SHARED, dev->name, dev);
1300         if (err)
1301                 goto out_close;
1302
1303         priv->mb_size = sizeof(struct flexcan_mb) + CAN_MAX_DLEN;
1304         priv->mb_count = (sizeof(priv->regs->mb[0]) / priv->mb_size) +
1305                          (sizeof(priv->regs->mb[1]) / priv->mb_size);
1306
1307         if (priv->devtype_data->quirks & FLEXCAN_QUIRK_USE_OFF_TIMESTAMP)
1308                 priv->tx_mb_reserved =
1309                         flexcan_get_mb(priv, FLEXCAN_TX_MB_RESERVED_OFF_TIMESTAMP);
1310         else
1311                 priv->tx_mb_reserved =
1312                         flexcan_get_mb(priv, FLEXCAN_TX_MB_RESERVED_OFF_FIFO);
1313         priv->tx_mb_idx = priv->mb_count - 1;
1314         priv->tx_mb = flexcan_get_mb(priv, priv->tx_mb_idx);
1315         priv->tx_mask = FLEXCAN_IFLAG_MB(priv->tx_mb_idx);
1316
1317         priv->offload.mailbox_read = flexcan_mailbox_read;
1318
1319         if (priv->devtype_data->quirks & FLEXCAN_QUIRK_USE_OFF_TIMESTAMP) {
1320                 priv->offload.mb_first = FLEXCAN_RX_MB_OFF_TIMESTAMP_FIRST;
1321                 priv->offload.mb_last = priv->mb_count - 2;
1322
1323                 priv->rx_mask = GENMASK_ULL(priv->offload.mb_last,
1324                                             priv->offload.mb_first);
1325                 err = can_rx_offload_add_timestamp(dev, &priv->offload);
1326         } else {
1327                 priv->rx_mask = FLEXCAN_IFLAG_RX_FIFO_OVERFLOW |
1328                         FLEXCAN_IFLAG_RX_FIFO_AVAILABLE;
1329                 err = can_rx_offload_add_fifo(dev, &priv->offload,
1330                                               FLEXCAN_NAPI_WEIGHT);
1331         }
1332         if (err)
1333                 goto out_free_irq;
1334
1335         /* start chip and queuing */
1336         err = flexcan_chip_start(dev);
1337         if (err)
1338                 goto out_offload_del;
1339
1340         can_led_event(dev, CAN_LED_EVENT_OPEN);
1341
1342         can_rx_offload_enable(&priv->offload);
1343         netif_start_queue(dev);
1344
1345         return 0;
1346
1347  out_offload_del:
1348         can_rx_offload_del(&priv->offload);
1349  out_free_irq:
1350         free_irq(dev->irq, dev);
1351  out_close:
1352         close_candev(dev);
1353  out_runtime_put:
1354         pm_runtime_put(priv->dev);
1355
1356         return err;
1357 }
1358
1359 static int flexcan_close(struct net_device *dev)
1360 {
1361         struct flexcan_priv *priv = netdev_priv(dev);
1362
1363         netif_stop_queue(dev);
1364         can_rx_offload_disable(&priv->offload);
1365         flexcan_chip_stop(dev);
1366
1367         can_rx_offload_del(&priv->offload);
1368         free_irq(dev->irq, dev);
1369
1370         close_candev(dev);
1371         pm_runtime_put(priv->dev);
1372
1373         can_led_event(dev, CAN_LED_EVENT_STOP);
1374
1375         return 0;
1376 }
1377
1378 static int flexcan_set_mode(struct net_device *dev, enum can_mode mode)
1379 {
1380         int err;
1381
1382         switch (mode) {
1383         case CAN_MODE_START:
1384                 err = flexcan_chip_start(dev);
1385                 if (err)
1386                         return err;
1387
1388                 netif_wake_queue(dev);
1389                 break;
1390
1391         default:
1392                 return -EOPNOTSUPP;
1393         }
1394
1395         return 0;
1396 }
1397
1398 static const struct net_device_ops flexcan_netdev_ops = {
1399         .ndo_open       = flexcan_open,
1400         .ndo_stop       = flexcan_close,
1401         .ndo_start_xmit = flexcan_start_xmit,
1402         .ndo_change_mtu = can_change_mtu,
1403 };
1404
1405 static int register_flexcandev(struct net_device *dev)
1406 {
1407         struct flexcan_priv *priv = netdev_priv(dev);
1408         struct flexcan_regs __iomem *regs = priv->regs;
1409         u32 reg, err;
1410
1411         err = flexcan_clks_enable(priv);
1412         if (err)
1413                 return err;
1414
1415         /* select "bus clock", chip must be disabled */
1416         err = flexcan_chip_disable(priv);
1417         if (err)
1418                 goto out_clks_disable;
1419
1420         reg = priv->read(&regs->ctrl);
1421         if (priv->clk_src)
1422                 reg |= FLEXCAN_CTRL_CLK_SRC;
1423         else
1424                 reg &= ~FLEXCAN_CTRL_CLK_SRC;
1425         priv->write(reg, &regs->ctrl);
1426
1427         err = flexcan_chip_enable(priv);
1428         if (err)
1429                 goto out_chip_disable;
1430
1431         /* set freeze, halt and activate FIFO, restrict register access */
1432         reg = priv->read(&regs->mcr);
1433         reg |= FLEXCAN_MCR_FRZ | FLEXCAN_MCR_HALT |
1434                 FLEXCAN_MCR_FEN | FLEXCAN_MCR_SUPV;
1435         priv->write(reg, &regs->mcr);
1436
1437         /* Currently we only support newer versions of this core
1438          * featuring a RX hardware FIFO (although this driver doesn't
1439          * make use of it on some cores). Older cores, found on some
1440          * Coldfire derivates are not tested.
1441          */
1442         reg = priv->read(&regs->mcr);
1443         if (!(reg & FLEXCAN_MCR_FEN)) {
1444                 netdev_err(dev, "Could not enable RX FIFO, unsupported core\n");
1445                 err = -ENODEV;
1446                 goto out_chip_disable;
1447         }
1448
1449         err = register_candev(dev);
1450         if (err)
1451                 goto out_chip_disable;
1452
1453         /* Disable core and let pm_runtime_put() disable the clocks.
1454          * If CONFIG_PM is not enabled, the clocks will stay powered.
1455          */
1456         flexcan_chip_disable(priv);
1457         pm_runtime_put(priv->dev);
1458
1459         return 0;
1460
1461  out_chip_disable:
1462         flexcan_chip_disable(priv);
1463  out_clks_disable:
1464         flexcan_clks_disable(priv);
1465         return err;
1466 }
1467
1468 static void unregister_flexcandev(struct net_device *dev)
1469 {
1470         unregister_candev(dev);
1471 }
1472
1473 static int flexcan_setup_stop_mode(struct platform_device *pdev)
1474 {
1475         struct net_device *dev = platform_get_drvdata(pdev);
1476         struct device_node *np = pdev->dev.of_node;
1477         struct device_node *gpr_np;
1478         struct flexcan_priv *priv;
1479         phandle phandle;
1480         u32 out_val[5];
1481         int ret;
1482
1483         if (!np)
1484                 return -EINVAL;
1485
1486         /* stop mode property format is:
1487          * <&gpr req_gpr req_bit ack_gpr ack_bit>.
1488          */
1489         ret = of_property_read_u32_array(np, "fsl,stop-mode", out_val,
1490                                          ARRAY_SIZE(out_val));
1491         if (ret) {
1492                 dev_dbg(&pdev->dev, "no stop-mode property\n");
1493                 return ret;
1494         }
1495         phandle = *out_val;
1496
1497         gpr_np = of_find_node_by_phandle(phandle);
1498         if (!gpr_np) {
1499                 dev_dbg(&pdev->dev, "could not find gpr node by phandle\n");
1500                 return -ENODEV;
1501         }
1502
1503         priv = netdev_priv(dev);
1504         priv->stm.gpr = syscon_node_to_regmap(gpr_np);
1505         if (IS_ERR(priv->stm.gpr)) {
1506                 dev_dbg(&pdev->dev, "could not find gpr regmap\n");
1507                 ret = PTR_ERR(priv->stm.gpr);
1508                 goto out_put_node;
1509         }
1510
1511         priv->stm.req_gpr = out_val[1];
1512         priv->stm.req_bit = out_val[2];
1513         priv->stm.ack_gpr = out_val[3];
1514         priv->stm.ack_bit = out_val[4];
1515
1516         dev_dbg(&pdev->dev,
1517                 "gpr %s req_gpr=0x02%x req_bit=%u ack_gpr=0x02%x ack_bit=%u\n",
1518                 gpr_np->full_name, priv->stm.req_gpr, priv->stm.req_bit,
1519                 priv->stm.ack_gpr, priv->stm.ack_bit);
1520
1521         device_set_wakeup_capable(&pdev->dev, true);
1522
1523         if (of_property_read_bool(np, "wakeup-source"))
1524                 device_set_wakeup_enable(&pdev->dev, true);
1525
1526         return 0;
1527
1528 out_put_node:
1529         of_node_put(gpr_np);
1530         return ret;
1531 }
1532
1533 static const struct of_device_id flexcan_of_match[] = {
1534         { .compatible = "fsl,imx6q-flexcan", .data = &fsl_imx6q_devtype_data, },
1535         { .compatible = "fsl,imx28-flexcan", .data = &fsl_imx28_devtype_data, },
1536         { .compatible = "fsl,imx53-flexcan", .data = &fsl_imx25_devtype_data, },
1537         { .compatible = "fsl,imx35-flexcan", .data = &fsl_imx25_devtype_data, },
1538         { .compatible = "fsl,imx25-flexcan", .data = &fsl_imx25_devtype_data, },
1539         { .compatible = "fsl,p1010-flexcan", .data = &fsl_p1010_devtype_data, },
1540         { .compatible = "fsl,vf610-flexcan", .data = &fsl_vf610_devtype_data, },
1541         { .compatible = "fsl,ls1021ar2-flexcan", .data = &fsl_ls1021a_r2_devtype_data, },
1542         { /* sentinel */ },
1543 };
1544 MODULE_DEVICE_TABLE(of, flexcan_of_match);
1545
1546 static const struct platform_device_id flexcan_id_table[] = {
1547         { .name = "flexcan", .driver_data = (kernel_ulong_t)&fsl_p1010_devtype_data, },
1548         { /* sentinel */ },
1549 };
1550 MODULE_DEVICE_TABLE(platform, flexcan_id_table);
1551
1552 static int flexcan_probe(struct platform_device *pdev)
1553 {
1554         const struct of_device_id *of_id;
1555         const struct flexcan_devtype_data *devtype_data;
1556         struct net_device *dev;
1557         struct flexcan_priv *priv;
1558         struct regulator *reg_xceiver;
1559         struct clk *clk_ipg = NULL, *clk_per = NULL;
1560         struct flexcan_regs __iomem *regs;
1561         int err, irq;
1562         u8 clk_src = 1;
1563         u32 clock_freq = 0;
1564
1565         reg_xceiver = devm_regulator_get(&pdev->dev, "xceiver");
1566         if (PTR_ERR(reg_xceiver) == -EPROBE_DEFER)
1567                 return -EPROBE_DEFER;
1568         else if (IS_ERR(reg_xceiver))
1569                 reg_xceiver = NULL;
1570
1571         if (pdev->dev.of_node) {
1572                 of_property_read_u32(pdev->dev.of_node,
1573                                      "clock-frequency", &clock_freq);
1574                 of_property_read_u8(pdev->dev.of_node,
1575                                     "fsl,clk-source", &clk_src);
1576         }
1577
1578         if (!clock_freq) {
1579                 clk_ipg = devm_clk_get(&pdev->dev, "ipg");
1580                 if (IS_ERR(clk_ipg)) {
1581                         dev_err(&pdev->dev, "no ipg clock defined\n");
1582                         return PTR_ERR(clk_ipg);
1583                 }
1584
1585                 clk_per = devm_clk_get(&pdev->dev, "per");
1586                 if (IS_ERR(clk_per)) {
1587                         dev_err(&pdev->dev, "no per clock defined\n");
1588                         return PTR_ERR(clk_per);
1589                 }
1590                 clock_freq = clk_get_rate(clk_per);
1591         }
1592
1593         irq = platform_get_irq(pdev, 0);
1594         if (irq <= 0)
1595                 return -ENODEV;
1596
1597         regs = devm_platform_ioremap_resource(pdev, 0);
1598         if (IS_ERR(regs))
1599                 return PTR_ERR(regs);
1600
1601         of_id = of_match_device(flexcan_of_match, &pdev->dev);
1602         if (of_id) {
1603                 devtype_data = of_id->data;
1604         } else if (platform_get_device_id(pdev)->driver_data) {
1605                 devtype_data = (struct flexcan_devtype_data *)
1606                         platform_get_device_id(pdev)->driver_data;
1607         } else {
1608                 return -ENODEV;
1609         }
1610
1611         dev = alloc_candev(sizeof(struct flexcan_priv), 1);
1612         if (!dev)
1613                 return -ENOMEM;
1614
1615         platform_set_drvdata(pdev, dev);
1616         SET_NETDEV_DEV(dev, &pdev->dev);
1617
1618         dev->netdev_ops = &flexcan_netdev_ops;
1619         dev->irq = irq;
1620         dev->flags |= IFF_ECHO;
1621
1622         priv = netdev_priv(dev);
1623
1624         if (of_property_read_bool(pdev->dev.of_node, "big-endian") ||
1625             devtype_data->quirks & FLEXCAN_QUIRK_DEFAULT_BIG_ENDIAN) {
1626                 priv->read = flexcan_read_be;
1627                 priv->write = flexcan_write_be;
1628         } else {
1629                 priv->read = flexcan_read_le;
1630                 priv->write = flexcan_write_le;
1631         }
1632
1633         priv->dev = &pdev->dev;
1634         priv->can.clock.freq = clock_freq;
1635         priv->can.bittiming_const = &flexcan_bittiming_const;
1636         priv->can.do_set_mode = flexcan_set_mode;
1637         priv->can.do_get_berr_counter = flexcan_get_berr_counter;
1638         priv->can.ctrlmode_supported = CAN_CTRLMODE_LOOPBACK |
1639                 CAN_CTRLMODE_LISTENONLY | CAN_CTRLMODE_3_SAMPLES |
1640                 CAN_CTRLMODE_BERR_REPORTING;
1641         priv->regs = regs;
1642         priv->clk_ipg = clk_ipg;
1643         priv->clk_per = clk_per;
1644         priv->clk_src = clk_src;
1645         priv->devtype_data = devtype_data;
1646         priv->reg_xceiver = reg_xceiver;
1647
1648         pm_runtime_get_noresume(&pdev->dev);
1649         pm_runtime_set_active(&pdev->dev);
1650         pm_runtime_enable(&pdev->dev);
1651
1652         err = register_flexcandev(dev);
1653         if (err) {
1654                 dev_err(&pdev->dev, "registering netdev failed\n");
1655                 goto failed_register;
1656         }
1657
1658         devm_can_led_init(dev);
1659
1660         if (priv->devtype_data->quirks & FLEXCAN_QUIRK_SETUP_STOP_MODE) {
1661                 err = flexcan_setup_stop_mode(pdev);
1662                 if (err)
1663                         dev_dbg(&pdev->dev, "failed to setup stop-mode\n");
1664         }
1665
1666         return 0;
1667
1668  failed_register:
1669         free_candev(dev);
1670         return err;
1671 }
1672
1673 static int flexcan_remove(struct platform_device *pdev)
1674 {
1675         struct net_device *dev = platform_get_drvdata(pdev);
1676
1677         unregister_flexcandev(dev);
1678         pm_runtime_disable(&pdev->dev);
1679         free_candev(dev);
1680
1681         return 0;
1682 }
1683
1684 static int __maybe_unused flexcan_suspend(struct device *device)
1685 {
1686         struct net_device *dev = dev_get_drvdata(device);
1687         struct flexcan_priv *priv = netdev_priv(dev);
1688         int err = 0;
1689
1690         if (netif_running(dev)) {
1691                 /* if wakeup is enabled, enter stop mode
1692                  * else enter disabled mode.
1693                  */
1694                 if (device_may_wakeup(device)) {
1695                         enable_irq_wake(dev->irq);
1696                         err = flexcan_enter_stop_mode(priv);
1697                         if (err)
1698                                 return err;
1699                 } else {
1700                         err = flexcan_chip_disable(priv);
1701                         if (err)
1702                                 return err;
1703
1704                         err = pm_runtime_force_suspend(device);
1705                 }
1706                 netif_stop_queue(dev);
1707                 netif_device_detach(dev);
1708         }
1709         priv->can.state = CAN_STATE_SLEEPING;
1710
1711         return err;
1712 }
1713
1714 static int __maybe_unused flexcan_resume(struct device *device)
1715 {
1716         struct net_device *dev = dev_get_drvdata(device);
1717         struct flexcan_priv *priv = netdev_priv(dev);
1718         int err = 0;
1719
1720         priv->can.state = CAN_STATE_ERROR_ACTIVE;
1721         if (netif_running(dev)) {
1722                 netif_device_attach(dev);
1723                 netif_start_queue(dev);
1724                 if (device_may_wakeup(device)) {
1725                         disable_irq_wake(dev->irq);
1726                         err = flexcan_exit_stop_mode(priv);
1727                         if (err)
1728                                 return err;
1729                 } else {
1730                         err = pm_runtime_force_resume(device);
1731                         if (err)
1732                                 return err;
1733
1734                         err = flexcan_chip_enable(priv);
1735                 }
1736         }
1737
1738         return err;
1739 }
1740
1741 static int __maybe_unused flexcan_runtime_suspend(struct device *device)
1742 {
1743         struct net_device *dev = dev_get_drvdata(device);
1744         struct flexcan_priv *priv = netdev_priv(dev);
1745
1746         flexcan_clks_disable(priv);
1747
1748         return 0;
1749 }
1750
1751 static int __maybe_unused flexcan_runtime_resume(struct device *device)
1752 {
1753         struct net_device *dev = dev_get_drvdata(device);
1754         struct flexcan_priv *priv = netdev_priv(dev);
1755
1756         return flexcan_clks_enable(priv);
1757 }
1758
1759 static int __maybe_unused flexcan_noirq_suspend(struct device *device)
1760 {
1761         struct net_device *dev = dev_get_drvdata(device);
1762         struct flexcan_priv *priv = netdev_priv(dev);
1763
1764         if (netif_running(dev) && device_may_wakeup(device))
1765                 flexcan_enable_wakeup_irq(priv, true);
1766
1767         return 0;
1768 }
1769
1770 static int __maybe_unused flexcan_noirq_resume(struct device *device)
1771 {
1772         struct net_device *dev = dev_get_drvdata(device);
1773         struct flexcan_priv *priv = netdev_priv(dev);
1774
1775         if (netif_running(dev) && device_may_wakeup(device))
1776                 flexcan_enable_wakeup_irq(priv, false);
1777
1778         return 0;
1779 }
1780
1781 static const struct dev_pm_ops flexcan_pm_ops = {
1782         SET_SYSTEM_SLEEP_PM_OPS(flexcan_suspend, flexcan_resume)
1783         SET_RUNTIME_PM_OPS(flexcan_runtime_suspend, flexcan_runtime_resume, NULL)
1784         SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(flexcan_noirq_suspend, flexcan_noirq_resume)
1785 };
1786
1787 static struct platform_driver flexcan_driver = {
1788         .driver = {
1789                 .name = DRV_NAME,
1790                 .pm = &flexcan_pm_ops,
1791                 .of_match_table = flexcan_of_match,
1792         },
1793         .probe = flexcan_probe,
1794         .remove = flexcan_remove,
1795         .id_table = flexcan_id_table,
1796 };
1797
1798 module_platform_driver(flexcan_driver);
1799
1800 MODULE_AUTHOR("Sascha Hauer <[email protected]>, "
1801               "Marc Kleine-Budde <[email protected]>");
1802 MODULE_LICENSE("GPL v2");
1803 MODULE_DESCRIPTION("CAN port driver for flexcan based chip");