drivers/clk/ti/clk-54xx.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * OMAP5 Clock init
   4  *
   5  * Copyright (C) 2013 Texas Instruments, Inc.
   6  *
   7  * Tero Kristo ([email protected])
   8  */
   9
  10 #include <linux/kernel.h>
  11 #include <linux/list.h>
  12 #include <linux/clk.h>
  13 #include <linux/clkdev.h>
  14 #include <linux/io.h>
  15 #include <linux/clk/ti.h>
  16 #include <dt-bindings/clock/omap5.h>
  17
  18 #include "clock.h"
  19
  20 #define OMAP5_DPLL_ABE_DEFFREQ                          98304000
  21
  22 /*
  23  * OMAP543x TRM, section "3.6.3.9.5 DPLL_USB Preferred Settings"
  24  * states it must be at 960MHz
  25  */
  26 #define OMAP5_DPLL_USB_DEFFREQ                          960000000
  27
  28 static const struct omap_clkctrl_reg_data omap5_mpu_clkctrl_regs[] __initconst = {
  29         { OMAP5_MPU_CLKCTRL, NULL, 0, "dpll_mpu_m2_ck" },
  30         { 0 },
  31 };
  32
  33 static const struct omap_clkctrl_reg_data omap5_dsp_clkctrl_regs[] __initconst = {
  34         { OMAP5_MMU_DSP_CLKCTRL, NULL, CLKF_HW_SUP | CLKF_NO_IDLEST, "dpll_iva_h11x2_ck" },
  35         { 0 },
  36 };
  37
  38 static const char * const omap5_dmic_gfclk_parents[] __initconst = {
  39         "abe_cm:clk:0018:26",
  40         "pad_clks_ck",
  41         "slimbus_clk",
  42         NULL,
  43 };
  44
  45 static const char * const omap5_dmic_sync_mux_ck_parents[] __initconst = {
  46         "abe_24m_fclk",
  47         "dss_syc_gfclk_div",
  48         "func_24m_clk",
  49         NULL,
  50 };
  51
  52 static const struct omap_clkctrl_bit_data omap5_dmic_bit_data[] __initconst = {
  53         { 24, TI_CLK_MUX, omap5_dmic_gfclk_parents, NULL },
  54         { 26, TI_CLK_MUX, omap5_dmic_sync_mux_ck_parents, NULL },
  55         { 0 },
  56 };
  57
  58 static const char * const omap5_mcbsp1_gfclk_parents[] __initconst = {
  59         "abe_cm:clk:0028:26",
  60         "pad_clks_ck",
  61         "slimbus_clk",
  62         NULL,
  63 };
  64
  65 static const struct omap_clkctrl_bit_data omap5_mcbsp1_bit_data[] __initconst = {
  66         { 24, TI_CLK_MUX, omap5_mcbsp1_gfclk_parents, NULL },
  67         { 26, TI_CLK_MUX, omap5_dmic_sync_mux_ck_parents, NULL },
  68         { 0 },
  69 };
  70
  71 static const char * const omap5_mcbsp2_gfclk_parents[] __initconst = {
  72         "abe_cm:clk:0030:26",
  73         "pad_clks_ck",
  74         "slimbus_clk",
  75         NULL,
  76 };
  77
  78 static const struct omap_clkctrl_bit_data omap5_mcbsp2_bit_data[] __initconst = {
  79         { 24, TI_CLK_MUX, omap5_mcbsp2_gfclk_parents, NULL },
  80         { 26, TI_CLK_MUX, omap5_dmic_sync_mux_ck_parents, NULL },
  81         { 0 },
  82 };
  83
  84 static const char * const omap5_mcbsp3_gfclk_parents[] __initconst = {
  85         "abe_cm:clk:0038:26",
  86         "pad_clks_ck",
  87         "slimbus_clk",
  88         NULL,
  89 };
  90
  91 static const struct omap_clkctrl_bit_data omap5_mcbsp3_bit_data[] __initconst = {
  92         { 24, TI_CLK_MUX, omap5_mcbsp3_gfclk_parents, NULL },
  93         { 26, TI_CLK_MUX, omap5_dmic_sync_mux_ck_parents, NULL },
  94         { 0 },
  95 };
  96
  97 static const char * const omap5_timer5_gfclk_mux_parents[] __initconst = {
  98         "dss_syc_gfclk_div",
  99         "sys_32k_ck",
 100         NULL,
 101 };
 102
 103 static const struct omap_clkctrl_bit_data omap5_timer5_bit_data[] __initconst = {
 104         { 24, TI_CLK_MUX, omap5_timer5_gfclk_mux_parents, NULL },
 105         { 0 },
 106 };
 107
 108 static const struct omap_clkctrl_bit_data omap5_timer6_bit_data[] __initconst = {
 109         { 24, TI_CLK_MUX, omap5_timer5_gfclk_mux_parents, NULL },
 110         { 0 },
 111 };
 112
 113 static const struct omap_clkctrl_bit_data omap5_timer7_bit_data[] __initconst = {
 114         { 24, TI_CLK_MUX, omap5_timer5_gfclk_mux_parents, NULL },
 115         { 0 },
 116 };
 117
 118 static const struct omap_clkctrl_bit_data omap5_timer8_bit_data[] __initconst = {
 119         { 24, TI_CLK_MUX, omap5_timer5_gfclk_mux_parents, NULL },
 120         { 0 },
 121 };
 122
 123 static const struct omap_clkctrl_reg_data omap5_abe_clkctrl_regs[] __initconst = {
 124         { OMAP5_L4_ABE_CLKCTRL, NULL, 0, "abe_iclk" },
 125         { OMAP5_MCPDM_CLKCTRL, NULL, CLKF_SW_SUP, "pad_clks_ck" },
 126         { OMAP5_DMIC_CLKCTRL, omap5_dmic_bit_data, CLKF_SW_SUP, "abe_cm:clk:0018:24" },
 127         { OMAP5_MCBSP1_CLKCTRL, omap5_mcbsp1_bit_data, CLKF_SW_SUP, "abe_cm:clk:0028:24" },
 128         { OMAP5_MCBSP2_CLKCTRL, omap5_mcbsp2_bit_data, CLKF_SW_SUP, "abe_cm:clk:0030:24" },
 129         { OMAP5_MCBSP3_CLKCTRL, omap5_mcbsp3_bit_data, CLKF_SW_SUP, "abe_cm:clk:0038:24" },
 130         { OMAP5_TIMER5_CLKCTRL, omap5_timer5_bit_data, CLKF_SW_SUP, "abe_cm:clk:0048:24" },
 131         { OMAP5_TIMER6_CLKCTRL, omap5_timer6_bit_data, CLKF_SW_SUP, "abe_cm:clk:0050:24" },
 132         { OMAP5_TIMER7_CLKCTRL, omap5_timer7_bit_data, CLKF_SW_SUP, "abe_cm:clk:0058:24" },
 133         { OMAP5_TIMER8_CLKCTRL, omap5_timer8_bit_data, CLKF_SW_SUP, "abe_cm:clk:0060:24" },
 134         { 0 },
 135 };
 136
 137 static const struct omap_clkctrl_reg_data omap5_l3main1_clkctrl_regs[] __initconst = {
 138         { OMAP5_L3_MAIN_1_CLKCTRL, NULL, 0, "l3_iclk_div" },
 139         { 0 },
 140 };
 141
 142 static const struct omap_clkctrl_reg_data omap5_l3main2_clkctrl_regs[] __initconst = {
 143         { OMAP5_L3_MAIN_2_CLKCTRL, NULL, 0, "l3_iclk_div" },
 144         { 0 },
 145 };
 146
 147 static const struct omap_clkctrl_reg_data omap5_ipu_clkctrl_regs[] __initconst = {
 148         { OMAP5_MMU_IPU_CLKCTRL, NULL, CLKF_HW_SUP | CLKF_NO_IDLEST, "dpll_core_h22x2_ck" },
 149         { 0 },
 150 };
 151
 152 static const struct omap_clkctrl_reg_data omap5_dma_clkctrl_regs[] __initconst = {
 153         { OMAP5_DMA_SYSTEM_CLKCTRL, NULL, 0, "l3_iclk_div" },
 154         { 0 },
 155 };
 156
 157 static const struct omap_clkctrl_reg_data omap5_emif_clkctrl_regs[] __initconst = {
 158         { OMAP5_DMM_CLKCTRL, NULL, 0, "l3_iclk_div" },
 159         { OMAP5_EMIF1_CLKCTRL, NULL, CLKF_HW_SUP, "dpll_core_h11x2_ck" },
 160         { OMAP5_EMIF2_CLKCTRL, NULL, CLKF_HW_SUP, "dpll_core_h11x2_ck" },
 161         { 0 },
 162 };
 163
 164 static const struct omap_clkctrl_reg_data omap5_l4cfg_clkctrl_regs[] __initconst = {
 165         { OMAP5_L4_CFG_CLKCTRL, NULL, 0, "l4_root_clk_div" },
 166         { OMAP5_SPINLOCK_CLKCTRL, NULL, 0, "l4_root_clk_div" },
 167         { OMAP5_MAILBOX_CLKCTRL, NULL, 0, "l4_root_clk_div" },
 168         { 0 },
 169 };
 170
 171 static const struct omap_clkctrl_reg_data omap5_l3instr_clkctrl_regs[] __initconst = {
 172         { OMAP5_L3_MAIN_3_CLKCTRL, NULL, CLKF_HW_SUP, "l3_iclk_div" },
 173         { OMAP5_L3_INSTR_CLKCTRL, NULL, CLKF_HW_SUP, "l3_iclk_div" },
 174         { 0 },
 175 };
 176
 177 static const char * const omap5_timer10_gfclk_mux_parents[] __initconst = {
 178         "sys_clkin",
 179         "sys_32k_ck",
 180         NULL,
 181 };
 182
 183 static const struct omap_clkctrl_bit_data omap5_timer10_bit_data[] __initconst = {
 184         { 24, TI_CLK_MUX, omap5_timer10_gfclk_mux_parents, NULL },
 185         { 0 },
 186 };
 187
 188 static const struct omap_clkctrl_bit_data omap5_timer11_bit_data[] __initconst = {
 189         { 24, TI_CLK_MUX, omap5_timer10_gfclk_mux_parents, NULL },
 190         { 0 },
 191 };
 192
 193 static const struct omap_clkctrl_bit_data omap5_timer2_bit_data[] __initconst = {
 194         { 24, TI_CLK_MUX, omap5_timer10_gfclk_mux_parents, NULL },
 195         { 0 },
 196 };
 197
 198 static const struct omap_clkctrl_bit_data omap5_timer3_bit_data[] __initconst = {
 199         { 24, TI_CLK_MUX, omap5_timer10_gfclk_mux_parents, NULL },
 200         { 0 },
 201 };
 202
 203 static const struct omap_clkctrl_bit_data omap5_timer4_bit_data[] __initconst = {
 204         { 24, TI_CLK_MUX, omap5_timer10_gfclk_mux_parents, NULL },
 205         { 0 },
 206 };
 207
 208 static const struct omap_clkctrl_bit_data omap5_timer9_bit_data[] __initconst = {
 209         { 24, TI_CLK_MUX, omap5_timer10_gfclk_mux_parents, NULL },
 210         { 0 },
 211 };
 212
 213 static const char * const omap5_gpio2_dbclk_parents[] __initconst = {
 214         "sys_32k_ck",
 215         NULL,
 216 };
 217
 218 static const struct omap_clkctrl_bit_data omap5_gpio2_bit_data[] __initconst = {
 219         { 8, TI_CLK_GATE, omap5_gpio2_dbclk_parents, NULL },
 220         { 0 },
 221 };
 222
 223 static const struct omap_clkctrl_bit_data omap5_gpio3_bit_data[] __initconst = {
 224         { 8, TI_CLK_GATE, omap5_gpio2_dbclk_parents, NULL },
 225         { 0 },
 226 };
 227
 228 static const struct omap_clkctrl_bit_data omap5_gpio4_bit_data[] __initconst = {
 229         { 8, TI_CLK_GATE, omap5_gpio2_dbclk_parents, NULL },
 230         { 0 },
 231 };
 232
 233 static const struct omap_clkctrl_bit_data omap5_gpio5_bit_data[] __initconst = {
 234         { 8, TI_CLK_GATE, omap5_gpio2_dbclk_parents, NULL },
 235         { 0 },
 236 };
 237
 238 static const struct omap_clkctrl_bit_data omap5_gpio6_bit_data[] __initconst = {
 239         { 8, TI_CLK_GATE, omap5_gpio2_dbclk_parents, NULL },
 240         { 0 },
 241 };
 242
 243 static const struct omap_clkctrl_bit_data omap5_gpio7_bit_data[] __initconst = {
 244         { 8, TI_CLK_GATE, omap5_gpio2_dbclk_parents, NULL },
 245         { 0 },
 246 };
 247
 248 static const struct omap_clkctrl_bit_data omap5_gpio8_bit_data[] __initconst = {
 249         { 8, TI_CLK_GATE, omap5_gpio2_dbclk_parents, NULL },
 250         { 0 },
 251 };
 252
 253 static const struct omap_clkctrl_reg_data omap5_l4per_clkctrl_regs[] __initconst = {
 254         { OMAP5_TIMER10_CLKCTRL, omap5_timer10_bit_data, CLKF_SW_SUP, "l4per_cm:clk:0008:24" },
 255         { OMAP5_TIMER11_CLKCTRL, omap5_timer11_bit_data, CLKF_SW_SUP, "l4per_cm:clk:0010:24" },
 256         { OMAP5_TIMER2_CLKCTRL, omap5_timer2_bit_data, CLKF_SW_SUP, "l4per_cm:clk:0018:24" },
 257         { OMAP5_TIMER3_CLKCTRL, omap5_timer3_bit_data, CLKF_SW_SUP, "l4per_cm:clk:0020:24" },
 258         { OMAP5_TIMER4_CLKCTRL, omap5_timer4_bit_data, CLKF_SW_SUP, "l4per_cm:clk:0028:24" },
 259         { OMAP5_TIMER9_CLKCTRL, omap5_timer9_bit_data, CLKF_SW_SUP, "l4per_cm:clk:0030:24" },
 260         { OMAP5_GPIO2_CLKCTRL, omap5_gpio2_bit_data, CLKF_HW_SUP, "l4_root_clk_div" },
 261         { OMAP5_GPIO3_CLKCTRL, omap5_gpio3_bit_data, CLKF_HW_SUP, "l4_root_clk_div" },
 262         { OMAP5_GPIO4_CLKCTRL, omap5_gpio4_bit_data, CLKF_HW_SUP, "l4_root_clk_div" },
 263         { OMAP5_GPIO5_CLKCTRL, omap5_gpio5_bit_data, CLKF_HW_SUP, "l4_root_clk_div" },
 264         { OMAP5_GPIO6_CLKCTRL, omap5_gpio6_bit_data, CLKF_HW_SUP, "l4_root_clk_div" },
 265         { OMAP5_I2C1_CLKCTRL, NULL, CLKF_SW_SUP, "func_96m_fclk" },
 266         { OMAP5_I2C2_CLKCTRL, NULL, CLKF_SW_SUP, "func_96m_fclk" },
 267         { OMAP5_I2C3_CLKCTRL, NULL, CLKF_SW_SUP, "func_96m_fclk" },
 268         { OMAP5_I2C4_CLKCTRL, NULL, CLKF_SW_SUP, "func_96m_fclk" },
 269         { OMAP5_L4_PER_CLKCTRL, NULL, 0, "l4_root_clk_div" },
 270         { OMAP5_MCSPI1_CLKCTRL, NULL, CLKF_SW_SUP, "func_48m_fclk" },
 271         { OMAP5_MCSPI2_CLKCTRL, NULL, CLKF_SW_SUP, "func_48m_fclk" },
 272         { OMAP5_MCSPI3_CLKCTRL, NULL, CLKF_SW_SUP, "func_48m_fclk" },
 273         { OMAP5_MCSPI4_CLKCTRL, NULL, CLKF_SW_SUP, "func_48m_fclk" },
 274         { OMAP5_GPIO7_CLKCTRL, omap5_gpio7_bit_data, CLKF_HW_SUP, "l4_root_clk_div" },
 275         { OMAP5_GPIO8_CLKCTRL, omap5_gpio8_bit_data, CLKF_HW_SUP, "l4_root_clk_div" },
 276         { OMAP5_MMC3_CLKCTRL, NULL, CLKF_SW_SUP, "func_48m_fclk" },
 277         { OMAP5_MMC4_CLKCTRL, NULL, CLKF_SW_SUP, "func_48m_fclk" },
 278         { OMAP5_UART1_CLKCTRL, NULL, CLKF_SW_SUP, "func_48m_fclk" },
 279         { OMAP5_UART2_CLKCTRL, NULL, CLKF_SW_SUP, "func_48m_fclk" },
 280         { OMAP5_UART3_CLKCTRL, NULL, CLKF_SW_SUP, "func_48m_fclk" },
 281         { OMAP5_UART4_CLKCTRL, NULL, CLKF_SW_SUP, "func_48m_fclk" },
 282         { OMAP5_MMC5_CLKCTRL, NULL, CLKF_SW_SUP, "func_96m_fclk" },
 283         { OMAP5_I2C5_CLKCTRL, NULL, CLKF_SW_SUP, "func_96m_fclk" },
 284         { OMAP5_UART5_CLKCTRL, NULL, CLKF_SW_SUP, "func_48m_fclk" },
 285         { OMAP5_UART6_CLKCTRL, NULL, CLKF_SW_SUP, "func_48m_fclk" },
 286         { 0 },
 287 };
 288
 289 static const struct omap_clkctrl_reg_data omap5_iva_clkctrl_regs[] __initconst = {
 290         { OMAP5_IVA_CLKCTRL, NULL, CLKF_HW_SUP, "dpll_iva_h12x2_ck" },
 291         { OMAP5_SL2IF_CLKCTRL, NULL, CLKF_HW_SUP, "dpll_iva_h12x2_ck" },
 292         { 0 },
 293 };
 294
 295 static const char * const omap5_dss_dss_clk_parents[] __initconst = {
 296         "dpll_per_h12x2_ck",
 297         NULL,
 298 };
 299
 300 static const char * const omap5_dss_48mhz_clk_parents[] __initconst = {
 301         "func_48m_fclk",
 302         NULL,
 303 };
 304
 305 static const char * const omap5_dss_sys_clk_parents[] __initconst = {
 306         "dss_syc_gfclk_div",
 307         NULL,
 308 };
 309
 310 static const struct omap_clkctrl_bit_data omap5_dss_core_bit_data[] __initconst = {
 311         { 8, TI_CLK_GATE, omap5_dss_dss_clk_parents, NULL },
 312         { 9, TI_CLK_GATE, omap5_dss_48mhz_clk_parents, NULL },
 313         { 10, TI_CLK_GATE, omap5_dss_sys_clk_parents, NULL },
 314         { 11, TI_CLK_GATE, omap5_gpio2_dbclk_parents, NULL },
 315         { 0 },
 316 };
 317
 318 static const struct omap_clkctrl_reg_data omap5_dss_clkctrl_regs[] __initconst = {
 319         { OMAP5_DSS_CORE_CLKCTRL, omap5_dss_core_bit_data, CLKF_SW_SUP, "dss_cm:clk:0000:8" },
 320         { 0 },
 321 };
 322
 323 static const char * const omap5_gpu_core_mux_parents[] __initconst = {
 324         "dpll_core_h14x2_ck",
 325         "dpll_per_h14x2_ck",
 326         NULL,
 327 };
 328
 329 static const char * const omap5_gpu_hyd_mux_parents[] __initconst = {
 330         "dpll_core_h14x2_ck",
 331         "dpll_per_h14x2_ck",
 332         NULL,
 333 };
 334
 335 static const char * const omap5_gpu_sys_clk_parents[] __initconst = {
 336         "sys_clkin",
 337         NULL,
 338 };
 339
 340 static const struct omap_clkctrl_div_data omap5_gpu_sys_clk_data __initconst = {
 341         .max_div = 2,
 342 };
 343
 344 static const struct omap_clkctrl_bit_data omap5_gpu_core_bit_data[] __initconst = {
 345         { 24, TI_CLK_MUX, omap5_gpu_core_mux_parents, NULL },
 346         { 25, TI_CLK_MUX, omap5_gpu_hyd_mux_parents, NULL },
 347         { 26, TI_CLK_DIVIDER, omap5_gpu_sys_clk_parents, &omap5_gpu_sys_clk_data },
 348         { 0 },
 349 };
 350
 351 static const struct omap_clkctrl_reg_data omap5_gpu_clkctrl_regs[] __initconst = {
 352         { OMAP5_GPU_CLKCTRL, omap5_gpu_core_bit_data, CLKF_SW_SUP, "gpu_cm:clk:0000:24" },
 353         { 0 },
 354 };
 355
 356 static const char * const omap5_mmc1_fclk_mux_parents[] __initconst = {
 357         "func_128m_clk",
 358         "dpll_per_m2x2_ck",
 359         NULL,
 360 };
 361
 362 static const char * const omap5_mmc1_fclk_parents[] __initconst = {
 363         "l3init_cm:clk:0008:24",
 364         NULL,
 365 };
 366
 367 static const struct omap_clkctrl_div_data omap5_mmc1_fclk_data __initconst = {
 368         .max_div = 2,
 369 };
 370
 371 static const struct omap_clkctrl_bit_data omap5_mmc1_bit_data[] __initconst = {
 372         { 8, TI_CLK_GATE, omap5_gpio2_dbclk_parents, NULL },
 373         { 24, TI_CLK_MUX, omap5_mmc1_fclk_mux_parents, NULL },
 374         { 25, TI_CLK_DIVIDER, omap5_mmc1_fclk_parents, &omap5_mmc1_fclk_data },
 375         { 0 },
 376 };
 377
 378 static const char * const omap5_mmc2_fclk_parents[] __initconst = {
 379         "l3init_cm:clk:0010:24",
 380         NULL,
 381 };
 382
 383 static const struct omap_clkctrl_div_data omap5_mmc2_fclk_data __initconst = {
 384         .max_div = 2,
 385 };
 386
 387 static const struct omap_clkctrl_bit_data omap5_mmc2_bit_data[] __initconst = {
 388         { 24, TI_CLK_MUX, omap5_mmc1_fclk_mux_parents, NULL },
 389         { 25, TI_CLK_DIVIDER, omap5_mmc2_fclk_parents, &omap5_mmc2_fclk_data },
 390         { 0 },
 391 };
 392
 393 static const char * const omap5_usb_host_hs_hsic60m_p3_clk_parents[] __initconst = {
 394         "l3init_60m_fclk",
 395         NULL,
 396 };
 397
 398 static const char * const omap5_usb_host_hs_hsic480m_p3_clk_parents[] __initconst = {
 399         "dpll_usb_m2_ck",
 400         NULL,
 401 };
 402
 403 static const char * const omap5_usb_host_hs_utmi_p1_clk_parents[] __initconst = {
 404         "l3init_cm:clk:0038:24",
 405         NULL,
 406 };
 407
 408 static const char * const omap5_usb_host_hs_utmi_p2_clk_parents[] __initconst = {
 409         "l3init_cm:clk:0038:25",
 410         NULL,
 411 };
 412
 413 static const char * const omap5_utmi_p1_gfclk_parents[] __initconst = {
 414         "l3init_60m_fclk",
 415         "xclk60mhsp1_ck",
 416         NULL,
 417 };
 418
 419 static const char * const omap5_utmi_p2_gfclk_parents[] __initconst = {
 420         "l3init_60m_fclk",
 421         "xclk60mhsp2_ck",
 422         NULL,
 423 };
 424
 425 static const struct omap_clkctrl_bit_data omap5_usb_host_hs_bit_data[] __initconst = {
 426         { 6, TI_CLK_GATE, omap5_usb_host_hs_hsic60m_p3_clk_parents, NULL },
 427         { 7, TI_CLK_GATE, omap5_usb_host_hs_hsic480m_p3_clk_parents, NULL },
 428         { 8, TI_CLK_GATE, omap5_usb_host_hs_utmi_p1_clk_parents, NULL },
 429         { 9, TI_CLK_GATE, omap5_usb_host_hs_utmi_p2_clk_parents, NULL },
 430         { 10, TI_CLK_GATE, omap5_usb_host_hs_hsic60m_p3_clk_parents, NULL },
 431         { 11, TI_CLK_GATE, omap5_usb_host_hs_hsic60m_p3_clk_parents, NULL },
 432         { 12, TI_CLK_GATE, omap5_usb_host_hs_hsic60m_p3_clk_parents, NULL },
 433         { 13, TI_CLK_GATE, omap5_usb_host_hs_hsic480m_p3_clk_parents, NULL },
 434         { 14, TI_CLK_GATE, omap5_usb_host_hs_hsic480m_p3_clk_parents, NULL },
 435         { 24, TI_CLK_MUX, omap5_utmi_p1_gfclk_parents, NULL },
 436         { 25, TI_CLK_MUX, omap5_utmi_p2_gfclk_parents, NULL },
 437         { 0 },
 438 };
 439
 440 static const struct omap_clkctrl_bit_data omap5_usb_tll_hs_bit_data[] __initconst = {
 441         { 8, TI_CLK_GATE, omap5_usb_host_hs_hsic60m_p3_clk_parents, NULL },
 442         { 9, TI_CLK_GATE, omap5_usb_host_hs_hsic60m_p3_clk_parents, NULL },
 443         { 10, TI_CLK_GATE, omap5_usb_host_hs_hsic60m_p3_clk_parents, NULL },
 444         { 0 },
 445 };
 446
 447 static const char * const omap5_sata_ref_clk_parents[] __initconst = {
 448         "sys_clkin",
 449         NULL,
 450 };
 451
 452 static const struct omap_clkctrl_bit_data omap5_sata_bit_data[] __initconst = {
 453         { 8, TI_CLK_GATE, omap5_sata_ref_clk_parents, NULL },
 454         { 0 },
 455 };
 456
 457 static const char * const omap5_usb_otg_ss_refclk960m_parents[] __initconst = {
 458         "dpll_usb_clkdcoldo",
 459         NULL,
 460 };
 461
 462 static const struct omap_clkctrl_bit_data omap5_usb_otg_ss_bit_data[] __initconst = {
 463         { 8, TI_CLK_GATE, omap5_usb_otg_ss_refclk960m_parents, NULL },
 464         { 0 },
 465 };
 466
 467 static const struct omap_clkctrl_reg_data omap5_l3init_clkctrl_regs[] __initconst = {
 468         { OMAP5_MMC1_CLKCTRL, omap5_mmc1_bit_data, CLKF_SW_SUP, "l3init_cm:clk:0008:25" },
 469         { OMAP5_MMC2_CLKCTRL, omap5_mmc2_bit_data, CLKF_SW_SUP, "l3init_cm:clk:0010:25" },
 470         { OMAP5_USB_HOST_HS_CLKCTRL, omap5_usb_host_hs_bit_data, CLKF_SW_SUP, "l3init_60m_fclk" },
 471         { OMAP5_USB_TLL_HS_CLKCTRL, omap5_usb_tll_hs_bit_data, CLKF_HW_SUP, "l4_root_clk_div" },
 472         { OMAP5_SATA_CLKCTRL, omap5_sata_bit_data, CLKF_SW_SUP, "func_48m_fclk" },
 473         { OMAP5_OCP2SCP1_CLKCTRL, NULL, CLKF_HW_SUP, "l4_root_clk_div" },
 474         { OMAP5_OCP2SCP3_CLKCTRL, NULL, CLKF_HW_SUP, "l4_root_clk_div" },
 475         { OMAP5_USB_OTG_SS_CLKCTRL, omap5_usb_otg_ss_bit_data, CLKF_HW_SUP, "dpll_core_h13x2_ck" },
 476         { 0 },
 477 };
 478
 479 static const struct omap_clkctrl_bit_data omap5_gpio1_bit_data[] __initconst = {
 480         { 8, TI_CLK_GATE, omap5_gpio2_dbclk_parents, NULL },
 481         { 0 },
 482 };
 483
 484 static const struct omap_clkctrl_bit_data omap5_timer1_bit_data[] __initconst = {
 485         { 24, TI_CLK_MUX, omap5_timer10_gfclk_mux_parents, NULL },
 486         { 0 },
 487 };
 488
 489 static const struct omap_clkctrl_reg_data omap5_wkupaon_clkctrl_regs[] __initconst = {
 490         { OMAP5_L4_WKUP_CLKCTRL, NULL, 0, "wkupaon_iclk_mux" },
 491         { OMAP5_WD_TIMER2_CLKCTRL, NULL, CLKF_SW_SUP, "sys_32k_ck" },
 492         { OMAP5_GPIO1_CLKCTRL, omap5_gpio1_bit_data, CLKF_HW_SUP, "wkupaon_iclk_mux" },
 493         { OMAP5_TIMER1_CLKCTRL, omap5_timer1_bit_data, CLKF_SW_SUP, "wkupaon_cm:clk:0020:24" },
 494         { OMAP5_COUNTER_32K_CLKCTRL, NULL, 0, "wkupaon_iclk_mux" },
 495         { OMAP5_KBD_CLKCTRL, NULL, CLKF_SW_SUP, "sys_32k_ck" },
 496         { 0 },
 497 };
 498
 499 const struct omap_clkctrl_data omap5_clkctrl_data[] __initconst = {
 500         { 0x4a004320, omap5_mpu_clkctrl_regs },
 501         { 0x4a004420, omap5_dsp_clkctrl_regs },
 502         { 0x4a004520, omap5_abe_clkctrl_regs },
 503         { 0x4a008720, omap5_l3main1_clkctrl_regs },
 504         { 0x4a008820, omap5_l3main2_clkctrl_regs },
 505         { 0x4a008920, omap5_ipu_clkctrl_regs },
 506         { 0x4a008a20, omap5_dma_clkctrl_regs },
 507         { 0x4a008b20, omap5_emif_clkctrl_regs },
 508         { 0x4a008d20, omap5_l4cfg_clkctrl_regs },
 509         { 0x4a008e20, omap5_l3instr_clkctrl_regs },
 510         { 0x4a009020, omap5_l4per_clkctrl_regs },
 511         { 0x4a009220, omap5_iva_clkctrl_regs },
 512         { 0x4a009420, omap5_dss_clkctrl_regs },
 513         { 0x4a009520, omap5_gpu_clkctrl_regs },
 514         { 0x4a009620, omap5_l3init_clkctrl_regs },
 515         { 0x4ae07920, omap5_wkupaon_clkctrl_regs },
 516         { 0 },
 517 };
 518
 519 static struct ti_dt_clk omap54xx_clks[] = {
 520         DT_CLK(NULL, "timer_32k_ck", "sys_32k_ck"),
 521         DT_CLK(NULL, "sys_clkin_ck", "sys_clkin"),
 522         DT_CLK(NULL, "dmic_gfclk", "abe_cm:0018:24"),
 523         DT_CLK(NULL, "dmic_sync_mux_ck", "abe_cm:0018:26"),
 524         DT_CLK(NULL, "dss_32khz_clk", "dss_cm:0000:11"),
 525         DT_CLK(NULL, "dss_48mhz_clk", "dss_cm:0000:9"),
 526         DT_CLK(NULL, "dss_dss_clk", "dss_cm:0000:8"),
 527         DT_CLK(NULL, "dss_sys_clk", "dss_cm:0000:10"),
 528         DT_CLK(NULL, "gpio1_dbclk", "wkupaon_cm:0018:8"),
 529         DT_CLK(NULL, "gpio2_dbclk", "l4per_cm:0040:8"),
 530         DT_CLK(NULL, "gpio3_dbclk", "l4per_cm:0048:8"),
 531         DT_CLK(NULL, "gpio4_dbclk", "l4per_cm:0050:8"),
 532         DT_CLK(NULL, "gpio5_dbclk", "l4per_cm:0058:8"),
 533         DT_CLK(NULL, "gpio6_dbclk", "l4per_cm:0060:8"),
 534         DT_CLK(NULL, "gpio7_dbclk", "l4per_cm:00f0:8"),
 535         DT_CLK(NULL, "gpio8_dbclk", "l4per_cm:00f8:8"),
 536         DT_CLK(NULL, "mcbsp1_gfclk", "abe_cm:0028:24"),
 537         DT_CLK(NULL, "mcbsp1_sync_mux_ck", "abe_cm:0028:26"),
 538         DT_CLK(NULL, "mcbsp2_gfclk", "abe_cm:0030:24"),
 539         DT_CLK(NULL, "mcbsp2_sync_mux_ck", "abe_cm:0030:26"),
 540         DT_CLK(NULL, "mcbsp3_gfclk", "abe_cm:0038:24"),
 541         DT_CLK(NULL, "mcbsp3_sync_mux_ck", "abe_cm:0038:26"),
 542         DT_CLK(NULL, "mmc1_32khz_clk", "l3init_cm:0008:8"),
 543         DT_CLK(NULL, "mmc1_fclk", "l3init_cm:0008:25"),
 544         DT_CLK(NULL, "mmc1_fclk_mux", "l3init_cm:0008:24"),
 545         DT_CLK(NULL, "mmc2_fclk", "l3init_cm:0010:25"),
 546         DT_CLK(NULL, "mmc2_fclk_mux", "l3init_cm:0010:24"),
 547         DT_CLK(NULL, "sata_ref_clk", "l3init_cm:0068:8"),
 548         DT_CLK(NULL, "timer10_gfclk_mux", "l4per_cm:0008:24"),
 549         DT_CLK(NULL, "timer11_gfclk_mux", "l4per_cm:0010:24"),
 550         DT_CLK(NULL, "timer1_gfclk_mux", "wkupaon_cm:0020:24"),
 551         DT_CLK(NULL, "timer2_gfclk_mux", "l4per_cm:0018:24"),
 552         DT_CLK(NULL, "timer3_gfclk_mux", "l4per_cm:0020:24"),
 553         DT_CLK(NULL, "timer4_gfclk_mux", "l4per_cm:0028:24"),
 554         DT_CLK(NULL, "timer5_gfclk_mux", "abe_cm:0048:24"),
 555         DT_CLK(NULL, "timer6_gfclk_mux", "abe_cm:0050:24"),
 556         DT_CLK(NULL, "timer7_gfclk_mux", "abe_cm:0058:24"),
 557         DT_CLK(NULL, "timer8_gfclk_mux", "abe_cm:0060:24"),
 558         DT_CLK(NULL, "timer9_gfclk_mux", "l4per_cm:0030:24"),
 559         DT_CLK(NULL, "usb_host_hs_hsic480m_p1_clk", "l3init_cm:0038:13"),
 560         DT_CLK(NULL, "usb_host_hs_hsic480m_p2_clk", "l3init_cm:0038:14"),
 561         DT_CLK(NULL, "usb_host_hs_hsic480m_p3_clk", "l3init_cm:0038:7"),
 562         DT_CLK(NULL, "usb_host_hs_hsic60m_p1_clk", "l3init_cm:0038:11"),
 563         DT_CLK(NULL, "usb_host_hs_hsic60m_p2_clk", "l3init_cm:0038:12"),
 564         DT_CLK(NULL, "usb_host_hs_hsic60m_p3_clk", "l3init_cm:0038:6"),
 565         DT_CLK(NULL, "usb_host_hs_utmi_p1_clk", "l3init_cm:0038:8"),
 566         DT_CLK(NULL, "usb_host_hs_utmi_p2_clk", "l3init_cm:0038:9"),
 567         DT_CLK(NULL, "usb_host_hs_utmi_p3_clk", "l3init_cm:0038:10"),
 568         DT_CLK(NULL, "usb_otg_ss_refclk960m", "l3init_cm:00d0:8"),
 569         DT_CLK(NULL, "usb_tll_hs_usb_ch0_clk", "l3init_cm:0048:8"),
 570         DT_CLK(NULL, "usb_tll_hs_usb_ch1_clk", "l3init_cm:0048:9"),
 571         DT_CLK(NULL, "usb_tll_hs_usb_ch2_clk", "l3init_cm:0048:10"),
 572         DT_CLK(NULL, "utmi_p1_gfclk", "l3init_cm:0038:24"),
 573         DT_CLK(NULL, "utmi_p2_gfclk", "l3init_cm:0038:25"),
 574         { .node_name = NULL },
 575 };
 576
 577 int __init omap5xxx_dt_clk_init(void)
 578 {
 579         int rc;
 580         struct clk *abe_dpll_ref, *abe_dpll, *sys_32k_ck, *usb_dpll;
 581
 582         ti_dt_clocks_register(omap54xx_clks);
 583
 584         omap2_clk_disable_autoidle_all();
 585
 586         ti_clk_add_aliases();
 587
 588         abe_dpll_ref = clk_get_sys(NULL, "abe_dpll_clk_mux");
 589         sys_32k_ck = clk_get_sys(NULL, "sys_32k_ck");
 590         rc = clk_set_parent(abe_dpll_ref, sys_32k_ck);
 591         abe_dpll = clk_get_sys(NULL, "dpll_abe_ck");
 592         if (!rc)
 593                 rc = clk_set_rate(abe_dpll, OMAP5_DPLL_ABE_DEFFREQ);
 594         if (rc)
 595                 pr_err("%s: failed to configure ABE DPLL!\n", __func__);
 596
 597         abe_dpll = clk_get_sys(NULL, "dpll_abe_m2x2_ck");
 598         if (!rc)
 599                 rc = clk_set_rate(abe_dpll, OMAP5_DPLL_ABE_DEFFREQ * 2);
 600         if (rc)
 601                 pr_err("%s: failed to configure ABE m2x2 DPLL!\n", __func__);
 602
 603         usb_dpll = clk_get_sys(NULL, "dpll_usb_ck");
 604         rc = clk_set_rate(usb_dpll, OMAP5_DPLL_USB_DEFFREQ);
 605         if (rc)
 606                 pr_err("%s: failed to configure USB DPLL!\n", __func__);
 607
 608         usb_dpll = clk_get_sys(NULL, "dpll_usb_m2_ck");
 609         rc = clk_set_rate(usb_dpll, OMAP5_DPLL_USB_DEFFREQ/2);
 610         if (rc)
 611                 pr_err("%s: failed to set USB_DPLL M2 OUT\n", __func__);
 612
 613         return 0;
 614 }