drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c

   1 /*
   2  * Copyright 2019 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23
  24 #include <linux/delay.h>
  25 #include <linux/firmware.h>
  26 #include <linux/module.h>
  27 #include <linux/pci.h>
  28
  29 #include "amdgpu.h"
  30 #include "amdgpu_ucode.h"
  31 #include "amdgpu_trace.h"
  32
  33 #include "gc/gc_10_1_0_offset.h"
  34 #include "gc/gc_10_1_0_sh_mask.h"
  35 #include "ivsrcid/sdma0/irqsrcs_sdma0_5_0.h"
  36 #include "ivsrcid/sdma1/irqsrcs_sdma1_5_0.h"
  37
  38 #include "soc15_common.h"
  39 #include "soc15.h"
  40 #include "navi10_sdma_pkt_open.h"
  41 #include "nbio_v2_3.h"
  42 #include "sdma_common.h"
  43 #include "sdma_v5_0.h"
  44
  45 MODULE_FIRMWARE("amdgpu/navi10_sdma.bin");
  46 MODULE_FIRMWARE("amdgpu/navi10_sdma1.bin");
  47
  48 MODULE_FIRMWARE("amdgpu/navi14_sdma.bin");
  49 MODULE_FIRMWARE("amdgpu/navi14_sdma1.bin");
  50
  51 MODULE_FIRMWARE("amdgpu/navi12_sdma.bin");
  52 MODULE_FIRMWARE("amdgpu/navi12_sdma1.bin");
  53
  54 MODULE_FIRMWARE("amdgpu/cyan_skillfish2_sdma.bin");
  55 MODULE_FIRMWARE("amdgpu/cyan_skillfish2_sdma1.bin");
  56
  57 #define SDMA1_REG_OFFSET 0x600
  58 #define SDMA0_HYP_DEC_REG_START 0x5880
  59 #define SDMA0_HYP_DEC_REG_END 0x5893
  60 #define SDMA1_HYP_DEC_REG_OFFSET 0x20
  61
  62 static void sdma_v5_0_set_ring_funcs(struct amdgpu_device *adev);
  63 static void sdma_v5_0_set_buffer_funcs(struct amdgpu_device *adev);
  64 static void sdma_v5_0_set_vm_pte_funcs(struct amdgpu_device *adev);
  65 static void sdma_v5_0_set_irq_funcs(struct amdgpu_device *adev);
  66
  67 static const struct soc15_reg_golden golden_settings_sdma_5[] = {
  68         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_CHICKEN_BITS, 0xffbf1f0f, 0x03ab0107),
  69         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_GFX_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
  70         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_PAGE_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
  71         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC0_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
  72         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC1_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
  73         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC2_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
  74         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC3_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
  75         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC4_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
  76         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC5_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
  77         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC6_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
  78         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC7_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
  79         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_UTCL1_PAGE, 0x00ffffff, 0x000c5c00),
  80         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_CHICKEN_BITS, 0xffbf1f0f, 0x03ab0107),
  81         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_GFX_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
  82         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_PAGE_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
  83         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC0_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
  84         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC1_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
  85         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC2_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
  86         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC3_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
  87         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC4_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
  88         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC5_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
  89         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC6_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
  90         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC7_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
  91         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_UTCL1_PAGE, 0x00ffffff, 0x000c5c00)
  92 };
  93
  94 static const struct soc15_reg_golden golden_settings_sdma_5_sriov[] = {
  95         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_GFX_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
  96         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_PAGE_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
  97         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC0_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
  98         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC1_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
  99         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC2_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
 100         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC3_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
 101         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC4_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
 102         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC5_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
 103         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC6_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
 104         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC7_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
 105         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_GFX_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
 106         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_PAGE_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
 107         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC0_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
 108         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC1_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
 109         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC2_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
 110         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC3_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
 111         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC4_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
 112         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC5_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
 113         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC6_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
 114         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC7_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
 115 };
 116
 117 static const struct soc15_reg_golden golden_settings_sdma_nv10[] = {
 118         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC3_RB_WPTR_POLL_CNTL, 0x0000fff0, 0x00403000),
 119         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC3_RB_WPTR_POLL_CNTL, 0x0000fff0, 0x00403000),
 120 };
 121
 122 static const struct soc15_reg_golden golden_settings_sdma_nv14[] = {
 123         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC3_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
 124         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC3_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
 125 };
 126
 127 static const struct soc15_reg_golden golden_settings_sdma_nv12[] = {
 128         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC3_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
 129         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_GB_ADDR_CONFIG, 0x001877ff, 0x00000044),
 130         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_GB_ADDR_CONFIG_READ, 0x001877ff, 0x00000044),
 131         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_GB_ADDR_CONFIG, 0x001877ff, 0x00000044),
 132         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_GB_ADDR_CONFIG_READ, 0x001877ff, 0x00000044),
 133         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC3_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
 134 };
 135
 136 static const struct soc15_reg_golden golden_settings_sdma_cyan_skillfish[] = {
 137         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_CHICKEN_BITS, 0xffbf1f0f, 0x03ab0107),
 138         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_GB_ADDR_CONFIG, 0x001877ff, 0x00000044),
 139         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_GB_ADDR_CONFIG_READ, 0x001877ff, 0x00000044),
 140         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_GFX_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
 141         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_PAGE_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
 142         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC0_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
 143         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC1_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
 144         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC2_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
 145         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC3_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
 146         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC4_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
 147         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC5_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
 148         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC6_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
 149         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC7_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
 150         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_UTCL1_PAGE, 0x007fffff, 0x004c5c00),
 151         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_CHICKEN_BITS, 0xffbf1f0f, 0x03ab0107),
 152         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_GB_ADDR_CONFIG, 0x001877ff, 0x00000044),
 153         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_GB_ADDR_CONFIG_READ, 0x001877ff, 0x00000044),
 154         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_GFX_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
 155         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_PAGE_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
 156         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC0_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
 157         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC1_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
 158         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC2_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
 159         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC3_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
 160         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC4_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
 161         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC5_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
 162         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC6_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
 163         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC7_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
 164         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_UTCL1_PAGE, 0x007fffff, 0x004c5c00)
 165 };
 166
 167 static u32 sdma_v5_0_get_reg_offset(struct amdgpu_device *adev, u32 instance, u32 internal_offset)
 168 {
 169         u32 base;
 170
 171         if (internal_offset >= SDMA0_HYP_DEC_REG_START &&
 172             internal_offset <= SDMA0_HYP_DEC_REG_END) {
 173                 base = adev->reg_offset[GC_HWIP][0][1];
 174                 if (instance == 1)
 175                         internal_offset += SDMA1_HYP_DEC_REG_OFFSET;
 176         } else {
 177                 base = adev->reg_offset[GC_HWIP][0][0];
 178                 if (instance == 1)
 179                         internal_offset += SDMA1_REG_OFFSET;
 180         }
 181
 182         return base + internal_offset;
 183 }
 184
 185 static void sdma_v5_0_init_golden_registers(struct amdgpu_device *adev)
 186 {
 187         switch (adev->ip_versions[SDMA0_HWIP][0]) {
 188         case IP_VERSION(5, 0, 0):
 189                 soc15_program_register_sequence(adev,
 190                                                 golden_settings_sdma_5,
 191                                                 (const u32)ARRAY_SIZE(golden_settings_sdma_5));
 192                 soc15_program_register_sequence(adev,
 193                                                 golden_settings_sdma_nv10,
 194                                                 (const u32)ARRAY_SIZE(golden_settings_sdma_nv10));
 195                 break;
 196         case IP_VERSION(5, 0, 2):
 197                 soc15_program_register_sequence(adev,
 198                                                 golden_settings_sdma_5,
 199                                                 (const u32)ARRAY_SIZE(golden_settings_sdma_5));
 200                 soc15_program_register_sequence(adev,
 201                                                 golden_settings_sdma_nv14,
 202                                                 (const u32)ARRAY_SIZE(golden_settings_sdma_nv14));
 203                 break;
 204         case IP_VERSION(5, 0, 5):
 205                 if (amdgpu_sriov_vf(adev))
 206                         soc15_program_register_sequence(adev,
 207                                                         golden_settings_sdma_5_sriov,
 208                                                         (const u32)ARRAY_SIZE(golden_settings_sdma_5_sriov));
 209                 else
 210                         soc15_program_register_sequence(adev,
 211                                                         golden_settings_sdma_5,
 212                                                         (const u32)ARRAY_SIZE(golden_settings_sdma_5));
 213                 soc15_program_register_sequence(adev,
 214                                                 golden_settings_sdma_nv12,
 215                                                 (const u32)ARRAY_SIZE(golden_settings_sdma_nv12));
 216                 break;
 217         case IP_VERSION(5, 0, 1):
 218                 soc15_program_register_sequence(adev,
 219                                                 golden_settings_sdma_cyan_skillfish,
 220                                                 (const u32)ARRAY_SIZE(golden_settings_sdma_cyan_skillfish));
 221                 break;
 222         default:
 223                 break;
 224         }
 225 }
 226
 227 /**
 228  * sdma_v5_0_init_microcode - load ucode images from disk
 229  *
 230  * @adev: amdgpu_device pointer
 231  *
 232  * Use the firmware interface to load the ucode images into
 233  * the driver (not loaded into hw).
 234  * Returns 0 on success, error on failure.
 235  */
 236
 237 // emulation only, won't work on real chip
 238 // navi10 real chip need to use PSP to load firmware
 239 static int sdma_v5_0_init_microcode(struct amdgpu_device *adev)
 240 {       int ret, i;
 241
 242         if (amdgpu_sriov_vf(adev) && (adev->ip_versions[SDMA0_HWIP][0] == IP_VERSION(5, 0, 5)))
 243                 return 0;
 244
 245         for (i = 0; i < adev->sdma.num_instances; i++) {
 246                 ret = amdgpu_sdma_init_microcode(adev, i, false);
 247                 if (ret)
 248                         return ret;
 249         }
 250
 251         return ret;
 252 }
 253
 254 static unsigned sdma_v5_0_ring_init_cond_exec(struct amdgpu_ring *ring)
 255 {
 256         unsigned ret;
 257
 258         amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_COND_EXE));
 259         amdgpu_ring_write(ring, lower_32_bits(ring->cond_exe_gpu_addr));
 260         amdgpu_ring_write(ring, upper_32_bits(ring->cond_exe_gpu_addr));
 261         amdgpu_ring_write(ring, 1);
 262         ret = ring->wptr & ring->buf_mask;/* this is the offset we need patch later */
 263         amdgpu_ring_write(ring, 0x55aa55aa);/* insert dummy here and patch it later */
 264
 265         return ret;
 266 }
 267
 268 static void sdma_v5_0_ring_patch_cond_exec(struct amdgpu_ring *ring,
 269                                            unsigned offset)
 270 {
 271         unsigned cur;
 272
 273         BUG_ON(offset > ring->buf_mask);
 274         BUG_ON(ring->ring[offset] != 0x55aa55aa);
 275
 276         cur = (ring->wptr - 1) & ring->buf_mask;
 277         if (cur > offset)
 278                 ring->ring[offset] = cur - offset;
 279         else
 280                 ring->ring[offset] = (ring->buf_mask + 1) - offset + cur;
 281 }
 282
 283 /**
 284  * sdma_v5_0_ring_get_rptr - get the current read pointer
 285  *
 286  * @ring: amdgpu ring pointer
 287  *
 288  * Get the current rptr from the hardware (NAVI10+).
 289  */
 290 static uint64_t sdma_v5_0_ring_get_rptr(struct amdgpu_ring *ring)
 291 {
 292         u64 *rptr;
 293
 294         /* XXX check if swapping is necessary on BE */
 295         rptr = (u64 *)ring->rptr_cpu_addr;
 296
 297         DRM_DEBUG("rptr before shift == 0x%016llx\n", *rptr);
 298         return ((*rptr) >> 2);
 299 }
 300
 301 /**
 302  * sdma_v5_0_ring_get_wptr - get the current write pointer
 303  *
 304  * @ring: amdgpu ring pointer
 305  *
 306  * Get the current wptr from the hardware (NAVI10+).
 307  */
 308 static uint64_t sdma_v5_0_ring_get_wptr(struct amdgpu_ring *ring)
 309 {
 310         struct amdgpu_device *adev = ring->adev;
 311         u64 wptr;
 312
 313         if (ring->use_doorbell) {
 314                 /* XXX check if swapping is necessary on BE */
 315                 wptr = READ_ONCE(*((u64 *)ring->wptr_cpu_addr));
 316                 DRM_DEBUG("wptr/doorbell before shift == 0x%016llx\n", wptr);
 317         } else {
 318                 wptr = RREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, ring->me, mmSDMA0_GFX_RB_WPTR_HI));
 319                 wptr = wptr << 32;
 320                 wptr |= RREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, ring->me, mmSDMA0_GFX_RB_WPTR));
 321                 DRM_DEBUG("wptr before shift [%i] wptr == 0x%016llx\n", ring->me, wptr);
 322         }
 323
 324         return wptr >> 2;
 325 }
 326
 327 /**
 328  * sdma_v5_0_ring_set_wptr - commit the write pointer
 329  *
 330  * @ring: amdgpu ring pointer
 331  *
 332  * Write the wptr back to the hardware (NAVI10+).
 333  */
 334 static void sdma_v5_0_ring_set_wptr(struct amdgpu_ring *ring)
 335 {
 336         struct amdgpu_device *adev = ring->adev;
 337         uint32_t *wptr_saved;
 338         uint32_t *is_queue_unmap;
 339         uint64_t aggregated_db_index;
 340         uint32_t mqd_size = adev->mqds[AMDGPU_HW_IP_DMA].mqd_size;
 341
 342         DRM_DEBUG("Setting write pointer\n");
 343         if (ring->is_mes_queue) {
 344                 wptr_saved = (uint32_t *)(ring->mqd_ptr + mqd_size);
 345                 is_queue_unmap = (uint32_t *)(ring->mqd_ptr + mqd_size +
 346                                               sizeof(uint32_t));
 347                 aggregated_db_index =
 348                         amdgpu_mes_get_aggregated_doorbell_index(adev,
 349                         AMDGPU_MES_PRIORITY_LEVEL_NORMAL);
 350
 351                 atomic64_set((atomic64_t *)ring->wptr_cpu_addr,
 352                              ring->wptr << 2);
 353                 *wptr_saved = ring->wptr << 2;
 354                 if (*is_queue_unmap) {
 355                         WDOORBELL64(aggregated_db_index, ring->wptr << 2);
 356                         DRM_DEBUG("calling WDOORBELL64(0x%08x, 0x%016llx)\n",
 357                                         ring->doorbell_index, ring->wptr << 2);
 358                         WDOORBELL64(ring->doorbell_index, ring->wptr << 2);
 359                 } else {
 360                         DRM_DEBUG("calling WDOORBELL64(0x%08x, 0x%016llx)\n",
 361                                         ring->doorbell_index, ring->wptr << 2);
 362                         WDOORBELL64(ring->doorbell_index, ring->wptr << 2);
 363
 364                         if (*is_queue_unmap)
 365                                 WDOORBELL64(aggregated_db_index,
 366                                             ring->wptr << 2);
 367                 }
 368         } else {
 369                 if (ring->use_doorbell) {
 370                         DRM_DEBUG("Using doorbell -- "
 371                                   "wptr_offs == 0x%08x "
 372                                   "lower_32_bits(ring->wptr) << 2 == 0x%08x "
 373                                   "upper_32_bits(ring->wptr) << 2 == 0x%08x\n",
 374                                   ring->wptr_offs,
 375                                   lower_32_bits(ring->wptr << 2),
 376                                   upper_32_bits(ring->wptr << 2));
 377                         /* XXX check if swapping is necessary on BE */
 378                         atomic64_set((atomic64_t *)ring->wptr_cpu_addr,
 379                                      ring->wptr << 2);
 380                         DRM_DEBUG("calling WDOORBELL64(0x%08x, 0x%016llx)\n",
 381                                   ring->doorbell_index, ring->wptr << 2);
 382                         WDOORBELL64(ring->doorbell_index, ring->wptr << 2);
 383                 } else {
 384                         DRM_DEBUG("Not using doorbell -- "
 385                                   "mmSDMA%i_GFX_RB_WPTR == 0x%08x "
 386                                   "mmSDMA%i_GFX_RB_WPTR_HI == 0x%08x\n",
 387                                   ring->me,
 388                                   lower_32_bits(ring->wptr << 2),
 389                                   ring->me,
 390                                   upper_32_bits(ring->wptr << 2));
 391                         WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev,
 392                                              ring->me, mmSDMA0_GFX_RB_WPTR),
 393                                         lower_32_bits(ring->wptr << 2));
 394                         WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev,
 395                                              ring->me, mmSDMA0_GFX_RB_WPTR_HI),
 396                                         upper_32_bits(ring->wptr << 2));
 397                 }
 398         }
 399 }
 400
 401 static void sdma_v5_0_ring_insert_nop(struct amdgpu_ring *ring, uint32_t count)
 402 {
 403         struct amdgpu_sdma_instance *sdma = amdgpu_sdma_get_instance_from_ring(ring);
 404         int i;
 405
 406         for (i = 0; i < count; i++)
 407                 if (sdma && sdma->burst_nop && (i == 0))
 408                         amdgpu_ring_write(ring, ring->funcs->nop |
 409                                 SDMA_PKT_NOP_HEADER_COUNT(count - 1));
 410                 else
 411                         amdgpu_ring_write(ring, ring->funcs->nop);
 412 }
 413
 414 /**
 415  * sdma_v5_0_ring_emit_ib - Schedule an IB on the DMA engine
 416  *
 417  * @ring: amdgpu ring pointer
 418  * @job: job to retrieve vmid from
 419  * @ib: IB object to schedule
 420  * @flags: unused
 421  *
 422  * Schedule an IB in the DMA ring (NAVI10).
 423  */
 424 static void sdma_v5_0_ring_emit_ib(struct amdgpu_ring *ring,
 425                                    struct amdgpu_job *job,
 426                                    struct amdgpu_ib *ib,
 427                                    uint32_t flags)
 428 {
 429         unsigned vmid = AMDGPU_JOB_GET_VMID(job);
 430         uint64_t csa_mc_addr = amdgpu_sdma_get_csa_mc_addr(ring, vmid);
 431
 432         /* An IB packet must end on a 8 DW boundary--the next dword
 433          * must be on a 8-dword boundary. Our IB packet below is 6
 434          * dwords long, thus add x number of NOPs, such that, in
 435          * modular arithmetic,
 436          * wptr + 6 + x = 8k, k >= 0, which in C is,
 437          * (wptr + 6 + x) % 8 = 0.
 438          * The expression below, is a solution of x.
 439          */
 440         sdma_v5_0_ring_insert_nop(ring, (2 - lower_32_bits(ring->wptr)) & 7);
 441
 442         amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_INDIRECT) |
 443                           SDMA_PKT_INDIRECT_HEADER_VMID(vmid & 0xf));
 444         /* base must be 32 byte aligned */
 445         amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr) & 0xffffffe0);
 446         amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr));
 447         amdgpu_ring_write(ring, ib->length_dw);
 448         amdgpu_ring_write(ring, lower_32_bits(csa_mc_addr));
 449         amdgpu_ring_write(ring, upper_32_bits(csa_mc_addr));
 450 }
 451
 452 /**
 453  * sdma_v5_0_ring_emit_mem_sync - flush the IB by graphics cache rinse
 454  *
 455  * @ring: amdgpu ring pointer
 456  *
 457  * flush the IB by graphics cache rinse.
 458  */
 459 static void sdma_v5_0_ring_emit_mem_sync(struct amdgpu_ring *ring)
 460 {
 461         uint32_t gcr_cntl = SDMA_GCR_GL2_INV | SDMA_GCR_GL2_WB | SDMA_GCR_GLM_INV |
 462                             SDMA_GCR_GL1_INV | SDMA_GCR_GLV_INV | SDMA_GCR_GLK_INV |
 463                             SDMA_GCR_GLI_INV(1);
 464
 465         /* flush entire cache L0/L1/L2, this can be optimized by performance requirement */
 466         amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_GCR_REQ));
 467         amdgpu_ring_write(ring, SDMA_PKT_GCR_REQ_PAYLOAD1_BASE_VA_31_7(0));
 468         amdgpu_ring_write(ring, SDMA_PKT_GCR_REQ_PAYLOAD2_GCR_CONTROL_15_0(gcr_cntl) |
 469                           SDMA_PKT_GCR_REQ_PAYLOAD2_BASE_VA_47_32(0));
 470         amdgpu_ring_write(ring, SDMA_PKT_GCR_REQ_PAYLOAD3_LIMIT_VA_31_7(0) |
 471                           SDMA_PKT_GCR_REQ_PAYLOAD3_GCR_CONTROL_18_16(gcr_cntl >> 16));
 472         amdgpu_ring_write(ring, SDMA_PKT_GCR_REQ_PAYLOAD4_LIMIT_VA_47_32(0) |
 473                           SDMA_PKT_GCR_REQ_PAYLOAD4_VMID(0));
 474 }
 475
 476 /**
 477  * sdma_v5_0_ring_emit_hdp_flush - emit an hdp flush on the DMA ring
 478  *
 479  * @ring: amdgpu ring pointer
 480  *
 481  * Emit an hdp flush packet on the requested DMA ring.
 482  */
 483 static void sdma_v5_0_ring_emit_hdp_flush(struct amdgpu_ring *ring)
 484 {
 485         struct amdgpu_device *adev = ring->adev;
 486         u32 ref_and_mask = 0;
 487         const struct nbio_hdp_flush_reg *nbio_hf_reg = adev->nbio.hdp_flush_reg;
 488
 489         if (ring->me == 0)
 490                 ref_and_mask = nbio_hf_reg->ref_and_mask_sdma0;
 491         else
 492                 ref_and_mask = nbio_hf_reg->ref_and_mask_sdma1;
 493
 494         amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_POLL_REGMEM) |
 495                           SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(1) |
 496                           SDMA_PKT_POLL_REGMEM_HEADER_FUNC(3)); /* == */
 497         amdgpu_ring_write(ring, (adev->nbio.funcs->get_hdp_flush_done_offset(adev)) << 2);
 498         amdgpu_ring_write(ring, (adev->nbio.funcs->get_hdp_flush_req_offset(adev)) << 2);
 499         amdgpu_ring_write(ring, ref_and_mask); /* reference */
 500         amdgpu_ring_write(ring, ref_and_mask); /* mask */
 501         amdgpu_ring_write(ring, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) |
 502                           SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(10)); /* retry count, poll interval */
 503 }
 504
 505 /**
 506  * sdma_v5_0_ring_emit_fence - emit a fence on the DMA ring
 507  *
 508  * @ring: amdgpu ring pointer
 509  * @addr: address
 510  * @seq: sequence number
 511  * @flags: fence related flags
 512  *
 513  * Add a DMA fence packet to the ring to write
 514  * the fence seq number and DMA trap packet to generate
 515  * an interrupt if needed (NAVI10).
 516  */
 517 static void sdma_v5_0_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq,
 518                                       unsigned flags)
 519 {
 520         bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT;
 521         /* write the fence */
 522         amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_FENCE) |
 523                           SDMA_PKT_FENCE_HEADER_MTYPE(0x3)); /* Ucached(UC) */
 524         /* zero in first two bits */
 525         BUG_ON(addr & 0x3);
 526         amdgpu_ring_write(ring, lower_32_bits(addr));
 527         amdgpu_ring_write(ring, upper_32_bits(addr));
 528         amdgpu_ring_write(ring, lower_32_bits(seq));
 529
 530         /* optionally write high bits as well */
 531         if (write64bit) {
 532                 addr += 4;
 533                 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_FENCE) |
 534                                   SDMA_PKT_FENCE_HEADER_MTYPE(0x3));
 535                 /* zero in first two bits */
 536                 BUG_ON(addr & 0x3);
 537                 amdgpu_ring_write(ring, lower_32_bits(addr));
 538                 amdgpu_ring_write(ring, upper_32_bits(addr));
 539                 amdgpu_ring_write(ring, upper_32_bits(seq));
 540         }
 541
 542         if (flags & AMDGPU_FENCE_FLAG_INT) {
 543                 uint32_t ctx = ring->is_mes_queue ?
 544                         (ring->hw_queue_id | AMDGPU_FENCE_MES_QUEUE_FLAG) : 0;
 545                 /* generate an interrupt */
 546                 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_TRAP));
 547                 amdgpu_ring_write(ring, SDMA_PKT_TRAP_INT_CONTEXT_INT_CONTEXT(ctx));
 548         }
 549 }
 550
 551
 552 /**
 553  * sdma_v5_0_gfx_stop - stop the gfx async dma engines
 554  *
 555  * @adev: amdgpu_device pointer
 556  *
 557  * Stop the gfx async dma ring buffers (NAVI10).
 558  */
 559 static void sdma_v5_0_gfx_stop(struct amdgpu_device *adev)
 560 {
 561         u32 rb_cntl, ib_cntl;
 562         int i;
 563
 564         amdgpu_sdma_unset_buffer_funcs_helper(adev);
 565
 566         for (i = 0; i < adev->sdma.num_instances; i++) {
 567                 rb_cntl = RREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL));
 568                 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_ENABLE, 0);
 569                 WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL), rb_cntl);
 570                 ib_cntl = RREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_IB_CNTL));
 571                 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_ENABLE, 0);
 572                 WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_IB_CNTL), ib_cntl);
 573         }
 574 }
 575
 576 /**
 577  * sdma_v5_0_rlc_stop - stop the compute async dma engines
 578  *
 579  * @adev: amdgpu_device pointer
 580  *
 581  * Stop the compute async dma queues (NAVI10).
 582  */
 583 static void sdma_v5_0_rlc_stop(struct amdgpu_device *adev)
 584 {
 585         /* XXX todo */
 586 }
 587
 588 /**
 589  * sdma_v5_0_ctx_switch_enable - stop the async dma engines context switch
 590  *
 591  * @adev: amdgpu_device pointer
 592  * @enable: enable/disable the DMA MEs context switch.
 593  *
 594  * Halt or unhalt the async dma engines context switch (NAVI10).
 595  */
 596 static void sdma_v5_0_ctx_switch_enable(struct amdgpu_device *adev, bool enable)
 597 {
 598         u32 f32_cntl = 0, phase_quantum = 0;
 599         int i;
 600
 601         if (amdgpu_sdma_phase_quantum) {
 602                 unsigned value = amdgpu_sdma_phase_quantum;
 603                 unsigned unit = 0;
 604
 605                 while (value > (SDMA0_PHASE0_QUANTUM__VALUE_MASK >>
 606                                 SDMA0_PHASE0_QUANTUM__VALUE__SHIFT)) {
 607                         value = (value + 1) >> 1;
 608                         unit++;
 609                 }
 610                 if (unit > (SDMA0_PHASE0_QUANTUM__UNIT_MASK >>
 611                             SDMA0_PHASE0_QUANTUM__UNIT__SHIFT)) {
 612                         value = (SDMA0_PHASE0_QUANTUM__VALUE_MASK >>
 613                                  SDMA0_PHASE0_QUANTUM__VALUE__SHIFT);
 614                         unit = (SDMA0_PHASE0_QUANTUM__UNIT_MASK >>
 615                                 SDMA0_PHASE0_QUANTUM__UNIT__SHIFT);
 616                         WARN_ONCE(1,
 617                         "clamping sdma_phase_quantum to %uK clock cycles\n",
 618                                   value << unit);
 619                 }
 620                 phase_quantum =
 621                         value << SDMA0_PHASE0_QUANTUM__VALUE__SHIFT |
 622                         unit  << SDMA0_PHASE0_QUANTUM__UNIT__SHIFT;
 623         }
 624
 625         for (i = 0; i < adev->sdma.num_instances; i++) {
 626                 if (!amdgpu_sriov_vf(adev)) {
 627                         f32_cntl = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_CNTL));
 628                         f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_CNTL,
 629                                                  AUTO_CTXSW_ENABLE, enable ? 1 : 0);
 630                 }
 631
 632                 if (enable && amdgpu_sdma_phase_quantum) {
 633                         WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_PHASE0_QUANTUM),
 634                                phase_quantum);
 635                         WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_PHASE1_QUANTUM),
 636                                phase_quantum);
 637                         WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_PHASE2_QUANTUM),
 638                                phase_quantum);
 639                 }
 640                 if (!amdgpu_sriov_vf(adev))
 641                         WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_CNTL), f32_cntl);
 642         }
 643
 644 }
 645
 646 /**
 647  * sdma_v5_0_enable - stop the async dma engines
 648  *
 649  * @adev: amdgpu_device pointer
 650  * @enable: enable/disable the DMA MEs.
 651  *
 652  * Halt or unhalt the async dma engines (NAVI10).
 653  */
 654 static void sdma_v5_0_enable(struct amdgpu_device *adev, bool enable)
 655 {
 656         u32 f32_cntl;
 657         int i;
 658
 659         if (!enable) {
 660                 sdma_v5_0_gfx_stop(adev);
 661                 sdma_v5_0_rlc_stop(adev);
 662         }
 663
 664         if (amdgpu_sriov_vf(adev))
 665                 return;
 666
 667         for (i = 0; i < adev->sdma.num_instances; i++) {
 668                 f32_cntl = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_F32_CNTL));
 669                 f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_F32_CNTL, HALT, enable ? 0 : 1);
 670                 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_F32_CNTL), f32_cntl);
 671         }
 672 }
 673
 674 /**
 675  * sdma_v5_0_gfx_resume - setup and start the async dma engines
 676  *
 677  * @adev: amdgpu_device pointer
 678  *
 679  * Set up the gfx DMA ring buffers and enable them (NAVI10).
 680  * Returns 0 for success, error for failure.
 681  */
 682 static int sdma_v5_0_gfx_resume(struct amdgpu_device *adev)
 683 {
 684         struct amdgpu_ring *ring;
 685         u32 rb_cntl, ib_cntl;
 686         u32 rb_bufsz;
 687         u32 doorbell;
 688         u32 doorbell_offset;
 689         u32 temp;
 690         u32 wptr_poll_cntl;
 691         u64 wptr_gpu_addr;
 692         int i, r;
 693
 694         for (i = 0; i < adev->sdma.num_instances; i++) {
 695                 ring = &adev->sdma.instance[i].ring;
 696
 697                 if (!amdgpu_sriov_vf(adev))
 698                         WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_SEM_WAIT_FAIL_TIMER_CNTL), 0);
 699
 700                 /* Set ring buffer size in dwords */
 701                 rb_bufsz = order_base_2(ring->ring_size / 4);
 702                 rb_cntl = RREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL));
 703                 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_SIZE, rb_bufsz);
 704 #ifdef __BIG_ENDIAN
 705                 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_SWAP_ENABLE, 1);
 706                 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL,
 707                                         RPTR_WRITEBACK_SWAP_ENABLE, 1);
 708 #endif
 709                 WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL), rb_cntl);
 710
 711                 /* Initialize the ring buffer's read and write pointers */
 712                 WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_RPTR), 0);
 713                 WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_RPTR_HI), 0);
 714                 WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR), 0);
 715                 WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_HI), 0);
 716
 717                 /* setup the wptr shadow polling */
 718                 wptr_gpu_addr = ring->wptr_gpu_addr;
 719                 WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_POLL_ADDR_LO),
 720                        lower_32_bits(wptr_gpu_addr));
 721                 WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_POLL_ADDR_HI),
 722                        upper_32_bits(wptr_gpu_addr));
 723                 wptr_poll_cntl = RREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i,
 724                                                          mmSDMA0_GFX_RB_WPTR_POLL_CNTL));
 725                 wptr_poll_cntl = REG_SET_FIELD(wptr_poll_cntl,
 726                                                SDMA0_GFX_RB_WPTR_POLL_CNTL,
 727                                                F32_POLL_ENABLE, 1);
 728                 WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_POLL_CNTL),
 729                        wptr_poll_cntl);
 730
 731                 /* set the wb address whether it's enabled or not */
 732                 WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_RPTR_ADDR_HI),
 733                        upper_32_bits(ring->rptr_gpu_addr) & 0xFFFFFFFF);
 734                 WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_RPTR_ADDR_LO),
 735                        lower_32_bits(ring->rptr_gpu_addr) & 0xFFFFFFFC);
 736
 737                 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RPTR_WRITEBACK_ENABLE, 1);
 738
 739                 WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_BASE),
 740                        ring->gpu_addr >> 8);
 741                 WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_BASE_HI),
 742                        ring->gpu_addr >> 40);
 743
 744                 ring->wptr = 0;
 745
 746                 /* before programing wptr to a less value, need set minor_ptr_update first */
 747                 WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_MINOR_PTR_UPDATE), 1);
 748
 749                 if (!amdgpu_sriov_vf(adev)) { /* only bare-metal use register write for wptr */
 750                         WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR),
 751                                lower_32_bits(ring->wptr << 2));
 752                         WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_HI),
 753                                upper_32_bits(ring->wptr << 2));
 754                 }
 755
 756                 doorbell = RREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_DOORBELL));
 757                 doorbell_offset = RREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i,
 758                                                 mmSDMA0_GFX_DOORBELL_OFFSET));
 759
 760                 if (ring->use_doorbell) {
 761                         doorbell = REG_SET_FIELD(doorbell, SDMA0_GFX_DOORBELL, ENABLE, 1);
 762                         doorbell_offset = REG_SET_FIELD(doorbell_offset, SDMA0_GFX_DOORBELL_OFFSET,
 763                                         OFFSET, ring->doorbell_index);
 764                 } else {
 765                         doorbell = REG_SET_FIELD(doorbell, SDMA0_GFX_DOORBELL, ENABLE, 0);
 766                 }
 767                 WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_DOORBELL), doorbell);
 768                 WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_DOORBELL_OFFSET),
 769                        doorbell_offset);
 770
 771                 adev->nbio.funcs->sdma_doorbell_range(adev, i, ring->use_doorbell,
 772                                                       ring->doorbell_index, 20);
 773
 774                 if (amdgpu_sriov_vf(adev))
 775                         sdma_v5_0_ring_set_wptr(ring);
 776
 777                 /* set minor_ptr_update to 0 after wptr programed */
 778                 WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_MINOR_PTR_UPDATE), 0);
 779
 780                 if (!amdgpu_sriov_vf(adev)) {
 781                         /* set utc l1 enable flag always to 1 */
 782                         temp = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_CNTL));
 783                         temp = REG_SET_FIELD(temp, SDMA0_CNTL, UTC_L1_ENABLE, 1);
 784
 785                         /* enable MCBP */
 786                         temp = REG_SET_FIELD(temp, SDMA0_CNTL, MIDCMD_PREEMPT_ENABLE, 1);
 787                         WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_CNTL), temp);
 788
 789                         /* Set up RESP_MODE to non-copy addresses */
 790                         temp = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_UTCL1_CNTL));
 791                         temp = REG_SET_FIELD(temp, SDMA0_UTCL1_CNTL, RESP_MODE, 3);
 792                         temp = REG_SET_FIELD(temp, SDMA0_UTCL1_CNTL, REDO_DELAY, 9);
 793                         WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_UTCL1_CNTL), temp);
 794
 795                         /* program default cache read and write policy */
 796                         temp = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_UTCL1_PAGE));
 797                         /* clean read policy and write policy bits */
 798                         temp &= 0xFF0FFF;
 799                         temp |= ((CACHE_READ_POLICY_L2__DEFAULT << 12) | (CACHE_WRITE_POLICY_L2__DEFAULT << 14));
 800                         WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_UTCL1_PAGE), temp);
 801                 }
 802
 803                 if (!amdgpu_sriov_vf(adev)) {
 804                         /* unhalt engine */
 805                         temp = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_F32_CNTL));
 806                         temp = REG_SET_FIELD(temp, SDMA0_F32_CNTL, HALT, 0);
 807                         WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_F32_CNTL), temp);
 808                 }
 809
 810                 /* enable DMA RB */
 811                 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_ENABLE, 1);
 812                 WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL), rb_cntl);
 813
 814                 ib_cntl = RREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_IB_CNTL));
 815                 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_ENABLE, 1);
 816 #ifdef __BIG_ENDIAN
 817                 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_SWAP_ENABLE, 1);
 818 #endif
 819                 /* enable DMA IBs */
 820                 WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_IB_CNTL), ib_cntl);
 821
 822                 if (amdgpu_sriov_vf(adev)) { /* bare-metal sequence doesn't need below to lines */
 823                         sdma_v5_0_ctx_switch_enable(adev, true);
 824                         sdma_v5_0_enable(adev, true);
 825                 }
 826
 827                 r = amdgpu_ring_test_helper(ring);
 828                 if (r)
 829                         return r;
 830
 831                 if (adev->mman.buffer_funcs_ring == ring)
 832                         amdgpu_ttm_set_buffer_funcs_status(adev, true);
 833         }
 834
 835         return 0;
 836 }
 837
 838 /**
 839  * sdma_v5_0_rlc_resume - setup and start the async dma engines
 840  *
 841  * @adev: amdgpu_device pointer
 842  *
 843  * Set up the compute DMA queues and enable them (NAVI10).
 844  * Returns 0 for success, error for failure.
 845  */
 846 static int sdma_v5_0_rlc_resume(struct amdgpu_device *adev)
 847 {
 848         return 0;
 849 }
 850
 851 /**
 852  * sdma_v5_0_load_microcode - load the sDMA ME ucode
 853  *
 854  * @adev: amdgpu_device pointer
 855  *
 856  * Loads the sDMA0/1 ucode.
 857  * Returns 0 for success, -EINVAL if the ucode is not available.
 858  */
 859 static int sdma_v5_0_load_microcode(struct amdgpu_device *adev)
 860 {
 861         const struct sdma_firmware_header_v1_0 *hdr;
 862         const __le32 *fw_data;
 863         u32 fw_size;
 864         int i, j;
 865
 866         /* halt the MEs */
 867         sdma_v5_0_enable(adev, false);
 868
 869         for (i = 0; i < adev->sdma.num_instances; i++) {
 870                 if (!adev->sdma.instance[i].fw)
 871                         return -EINVAL;
 872
 873                 hdr = (const struct sdma_firmware_header_v1_0 *)adev->sdma.instance[i].fw->data;
 874                 amdgpu_ucode_print_sdma_hdr(&hdr->header);
 875                 fw_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4;
 876
 877                 fw_data = (const __le32 *)
 878                         (adev->sdma.instance[i].fw->data +
 879                                 le32_to_cpu(hdr->header.ucode_array_offset_bytes));
 880
 881                 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_UCODE_ADDR), 0);
 882
 883                 for (j = 0; j < fw_size; j++) {
 884                         if (amdgpu_emu_mode == 1 && j % 500 == 0)
 885                                 msleep(1);
 886                         WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_UCODE_DATA), le32_to_cpup(fw_data++));
 887                 }
 888
 889                 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_UCODE_ADDR), adev->sdma.instance[i].fw_version);
 890         }
 891
 892         return 0;
 893 }
 894
 895 /**
 896  * sdma_v5_0_start - setup and start the async dma engines
 897  *
 898  * @adev: amdgpu_device pointer
 899  *
 900  * Set up the DMA engines and enable them (NAVI10).
 901  * Returns 0 for success, error for failure.
 902  */
 903 static int sdma_v5_0_start(struct amdgpu_device *adev)
 904 {
 905         int r = 0;
 906
 907         if (amdgpu_sriov_vf(adev)) {
 908                 sdma_v5_0_ctx_switch_enable(adev, false);
 909                 sdma_v5_0_enable(adev, false);
 910
 911                 /* set RB registers */
 912                 r = sdma_v5_0_gfx_resume(adev);
 913                 return r;
 914         }
 915
 916         if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) {
 917                 r = sdma_v5_0_load_microcode(adev);
 918                 if (r)
 919                         return r;
 920         }
 921
 922         /* unhalt the MEs */
 923         sdma_v5_0_enable(adev, true);
 924         /* enable sdma ring preemption */
 925         sdma_v5_0_ctx_switch_enable(adev, true);
 926
 927         /* start the gfx rings and rlc compute queues */
 928         r = sdma_v5_0_gfx_resume(adev);
 929         if (r)
 930                 return r;
 931         r = sdma_v5_0_rlc_resume(adev);
 932
 933         return r;
 934 }
 935
 936 static int sdma_v5_0_mqd_init(struct amdgpu_device *adev, void *mqd,
 937                               struct amdgpu_mqd_prop *prop)
 938 {
 939         struct v10_sdma_mqd *m = mqd;
 940         uint64_t wb_gpu_addr;
 941
 942         m->sdmax_rlcx_rb_cntl =
 943                 order_base_2(prop->queue_size / 4) << SDMA0_RLC0_RB_CNTL__RB_SIZE__SHIFT |
 944                 1 << SDMA0_RLC0_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT |
 945                 6 << SDMA0_RLC0_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT |
 946                 1 << SDMA0_RLC0_RB_CNTL__RB_PRIV__SHIFT;
 947
 948         m->sdmax_rlcx_rb_base = lower_32_bits(prop->hqd_base_gpu_addr >> 8);
 949         m->sdmax_rlcx_rb_base_hi = upper_32_bits(prop->hqd_base_gpu_addr >> 8);
 950
 951         m->sdmax_rlcx_rb_wptr_poll_cntl = RREG32(sdma_v5_0_get_reg_offset(adev, 0,
 952                                                   mmSDMA0_GFX_RB_WPTR_POLL_CNTL));
 953
 954         wb_gpu_addr = prop->wptr_gpu_addr;
 955         m->sdmax_rlcx_rb_wptr_poll_addr_lo = lower_32_bits(wb_gpu_addr);
 956         m->sdmax_rlcx_rb_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr);
 957
 958         wb_gpu_addr = prop->rptr_gpu_addr;
 959         m->sdmax_rlcx_rb_rptr_addr_lo = lower_32_bits(wb_gpu_addr);
 960         m->sdmax_rlcx_rb_rptr_addr_hi = upper_32_bits(wb_gpu_addr);
 961
 962         m->sdmax_rlcx_ib_cntl = RREG32(sdma_v5_0_get_reg_offset(adev, 0,
 963                                                         mmSDMA0_GFX_IB_CNTL));
 964
 965         m->sdmax_rlcx_doorbell_offset =
 966                 prop->doorbell_index << SDMA0_RLC0_DOORBELL_OFFSET__OFFSET__SHIFT;
 967
 968         m->sdmax_rlcx_doorbell = REG_SET_FIELD(0, SDMA0_RLC0_DOORBELL, ENABLE, 1);
 969
 970         return 0;
 971 }
 972
 973 static void sdma_v5_0_set_mqd_funcs(struct amdgpu_device *adev)
 974 {
 975         adev->mqds[AMDGPU_HW_IP_DMA].mqd_size = sizeof(struct v10_sdma_mqd);
 976         adev->mqds[AMDGPU_HW_IP_DMA].init_mqd = sdma_v5_0_mqd_init;
 977 }
 978
 979 /**
 980  * sdma_v5_0_ring_test_ring - simple async dma engine test
 981  *
 982  * @ring: amdgpu_ring structure holding ring information
 983  *
 984  * Test the DMA engine by writing using it to write an
 985  * value to memory. (NAVI10).
 986  * Returns 0 for success, error for failure.
 987  */
 988 static int sdma_v5_0_ring_test_ring(struct amdgpu_ring *ring)
 989 {
 990         struct amdgpu_device *adev = ring->adev;
 991         unsigned i;
 992         unsigned index;
 993         int r;
 994         u32 tmp;
 995         u64 gpu_addr;
 996         volatile uint32_t *cpu_ptr = NULL;
 997
 998         tmp = 0xCAFEDEAD;
 999
1000         if (ring->is_mes_queue) {
1001                 uint32_t offset = 0;
1002                 offset = amdgpu_mes_ctx_get_offs(ring,
1003                                          AMDGPU_MES_CTX_PADDING_OFFS);
1004                 gpu_addr = amdgpu_mes_ctx_get_offs_gpu_addr(ring, offset);
1005                 cpu_ptr = amdgpu_mes_ctx_get_offs_cpu_addr(ring, offset);
1006                 *cpu_ptr = tmp;
1007         } else {
1008                 r = amdgpu_device_wb_get(adev, &index);
1009                 if (r) {
1010                         dev_err(adev->dev, "(%d) failed to allocate wb slot\n", r);
1011                         return r;
1012                 }
1013
1014                 gpu_addr = adev->wb.gpu_addr + (index * 4);
1015                 adev->wb.wb[index] = cpu_to_le32(tmp);
1016         }
1017
1018         r = amdgpu_ring_alloc(ring, 20);
1019         if (r) {
1020                 DRM_ERROR("amdgpu: dma failed to lock ring %d (%d).\n", ring->idx, r);
1021                 amdgpu_device_wb_free(adev, index);
1022                 return r;
1023         }
1024
1025         amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) |
1026                           SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR));
1027         amdgpu_ring_write(ring, lower_32_bits(gpu_addr));
1028         amdgpu_ring_write(ring, upper_32_bits(gpu_addr));
1029         amdgpu_ring_write(ring, SDMA_PKT_WRITE_UNTILED_DW_3_COUNT(0));
1030         amdgpu_ring_write(ring, 0xDEADBEEF);
1031         amdgpu_ring_commit(ring);
1032
1033         for (i = 0; i < adev->usec_timeout; i++) {
1034                 if (ring->is_mes_queue)
1035                         tmp = le32_to_cpu(*cpu_ptr);
1036                 else
1037                         tmp = le32_to_cpu(adev->wb.wb[index]);
1038                 if (tmp == 0xDEADBEEF)
1039                         break;
1040                 if (amdgpu_emu_mode == 1)
1041                         msleep(1);
1042                 else
1043                         udelay(1);
1044         }
1045
1046         if (i >= adev->usec_timeout)
1047                 r = -ETIMEDOUT;
1048
1049         if (!ring->is_mes_queue)
1050                 amdgpu_device_wb_free(adev, index);
1051
1052         return r;
1053 }
1054
1055 /**
1056  * sdma_v5_0_ring_test_ib - test an IB on the DMA engine
1057  *
1058  * @ring: amdgpu_ring structure holding ring information
1059  * @timeout: timeout value in jiffies, or MAX_SCHEDULE_TIMEOUT
1060  *
1061  * Test a simple IB in the DMA ring (NAVI10).
1062  * Returns 0 on success, error on failure.
1063  */
1064 static int sdma_v5_0_ring_test_ib(struct amdgpu_ring *ring, long timeout)
1065 {
1066         struct amdgpu_device *adev = ring->adev;
1067         struct amdgpu_ib ib;
1068         struct dma_fence *f = NULL;
1069         unsigned index;
1070         long r;
1071         u32 tmp = 0;
1072         u64 gpu_addr;
1073         volatile uint32_t *cpu_ptr = NULL;
1074
1075         tmp = 0xCAFEDEAD;
1076         memset(&ib, 0, sizeof(ib));
1077
1078         if (ring->is_mes_queue) {
1079                 uint32_t offset = 0;
1080                 offset = amdgpu_mes_ctx_get_offs(ring, AMDGPU_MES_CTX_IB_OFFS);
1081                 ib.gpu_addr = amdgpu_mes_ctx_get_offs_gpu_addr(ring, offset);
1082                 ib.ptr = (void *)amdgpu_mes_ctx_get_offs_cpu_addr(ring, offset);
1083
1084                 offset = amdgpu_mes_ctx_get_offs(ring,
1085                                          AMDGPU_MES_CTX_PADDING_OFFS);
1086                 gpu_addr = amdgpu_mes_ctx_get_offs_gpu_addr(ring, offset);
1087                 cpu_ptr = amdgpu_mes_ctx_get_offs_cpu_addr(ring, offset);
1088                 *cpu_ptr = tmp;
1089         } else {
1090                 r = amdgpu_device_wb_get(adev, &index);
1091                 if (r) {
1092                         dev_err(adev->dev, "(%ld) failed to allocate wb slot\n", r);
1093                         return r;
1094                 }
1095
1096                 gpu_addr = adev->wb.gpu_addr + (index * 4);
1097                 adev->wb.wb[index] = cpu_to_le32(tmp);
1098
1099                 r = amdgpu_ib_get(adev, NULL, 256,
1100                                         AMDGPU_IB_POOL_DIRECT, &ib);
1101                 if (r) {
1102                         DRM_ERROR("amdgpu: failed to get ib (%ld).\n", r);
1103                         goto err0;
1104                 }
1105         }
1106
1107         ib.ptr[0] = SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) |
1108                 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR);
1109         ib.ptr[1] = lower_32_bits(gpu_addr);
1110         ib.ptr[2] = upper_32_bits(gpu_addr);
1111         ib.ptr[3] = SDMA_PKT_WRITE_UNTILED_DW_3_COUNT(0);
1112         ib.ptr[4] = 0xDEADBEEF;
1113         ib.ptr[5] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP);
1114         ib.ptr[6] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP);
1115         ib.ptr[7] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP);
1116         ib.length_dw = 8;
1117
1118         r = amdgpu_ib_schedule(ring, 1, &ib, NULL, &f);
1119         if (r)
1120                 goto err1;
1121
1122         r = dma_fence_wait_timeout(f, false, timeout);
1123         if (r == 0) {
1124                 DRM_ERROR("amdgpu: IB test timed out\n");
1125                 r = -ETIMEDOUT;
1126                 goto err1;
1127         } else if (r < 0) {
1128                 DRM_ERROR("amdgpu: fence wait failed (%ld).\n", r);
1129                 goto err1;
1130         }
1131
1132         if (ring->is_mes_queue)
1133                 tmp = le32_to_cpu(*cpu_ptr);
1134         else
1135                 tmp = le32_to_cpu(adev->wb.wb[index]);
1136
1137         if (tmp == 0xDEADBEEF)
1138                 r = 0;
1139         else
1140                 r = -EINVAL;
1141
1142 err1:
1143         amdgpu_ib_free(adev, &ib, NULL);
1144         dma_fence_put(f);
1145 err0:
1146         if (!ring->is_mes_queue)
1147                 amdgpu_device_wb_free(adev, index);
1148         return r;
1149 }
1150
1151
1152 /**
1153  * sdma_v5_0_vm_copy_pte - update PTEs by copying them from the GART
1154  *
1155  * @ib: indirect buffer to fill with commands
1156  * @pe: addr of the page entry
1157  * @src: src addr to copy from
1158  * @count: number of page entries to update
1159  *
1160  * Update PTEs by copying them from the GART using sDMA (NAVI10).
1161  */
1162 static void sdma_v5_0_vm_copy_pte(struct amdgpu_ib *ib,
1163                                   uint64_t pe, uint64_t src,
1164                                   unsigned count)
1165 {
1166         unsigned bytes = count * 8;
1167
1168         ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_COPY) |
1169                 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_COPY_LINEAR);
1170         ib->ptr[ib->length_dw++] = bytes - 1;
1171         ib->ptr[ib->length_dw++] = 0; /* src/dst endian swap */
1172         ib->ptr[ib->length_dw++] = lower_32_bits(src);
1173         ib->ptr[ib->length_dw++] = upper_32_bits(src);
1174         ib->ptr[ib->length_dw++] = lower_32_bits(pe);
1175         ib->ptr[ib->length_dw++] = upper_32_bits(pe);
1176
1177 }
1178
1179 /**
1180  * sdma_v5_0_vm_write_pte - update PTEs by writing them manually
1181  *
1182  * @ib: indirect buffer to fill with commands
1183  * @pe: addr of the page entry
1184  * @value: dst addr to write into pe
1185  * @count: number of page entries to update
1186  * @incr: increase next addr by incr bytes
1187  *
1188  * Update PTEs by writing them manually using sDMA (NAVI10).
1189  */
1190 static void sdma_v5_0_vm_write_pte(struct amdgpu_ib *ib, uint64_t pe,
1191                                    uint64_t value, unsigned count,
1192                                    uint32_t incr)
1193 {
1194         unsigned ndw = count * 2;
1195
1196         ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) |
1197                 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR);
1198         ib->ptr[ib->length_dw++] = lower_32_bits(pe);
1199         ib->ptr[ib->length_dw++] = upper_32_bits(pe);
1200         ib->ptr[ib->length_dw++] = ndw - 1;
1201         for (; ndw > 0; ndw -= 2) {
1202                 ib->ptr[ib->length_dw++] = lower_32_bits(value);
1203                 ib->ptr[ib->length_dw++] = upper_32_bits(value);
1204                 value += incr;
1205         }
1206 }
1207
1208 /**
1209  * sdma_v5_0_vm_set_pte_pde - update the page tables using sDMA
1210  *
1211  * @ib: indirect buffer to fill with commands
1212  * @pe: addr of the page entry
1213  * @addr: dst addr to write into pe
1214  * @count: number of page entries to update
1215  * @incr: increase next addr by incr bytes
1216  * @flags: access flags
1217  *
1218  * Update the page tables using sDMA (NAVI10).
1219  */
1220 static void sdma_v5_0_vm_set_pte_pde(struct amdgpu_ib *ib,
1221                                      uint64_t pe,
1222                                      uint64_t addr, unsigned count,
1223                                      uint32_t incr, uint64_t flags)
1224 {
1225         /* for physically contiguous pages (vram) */
1226         ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_PTEPDE);
1227         ib->ptr[ib->length_dw++] = lower_32_bits(pe); /* dst addr */
1228         ib->ptr[ib->length_dw++] = upper_32_bits(pe);
1229         ib->ptr[ib->length_dw++] = lower_32_bits(flags); /* mask */
1230         ib->ptr[ib->length_dw++] = upper_32_bits(flags);
1231         ib->ptr[ib->length_dw++] = lower_32_bits(addr); /* value */
1232         ib->ptr[ib->length_dw++] = upper_32_bits(addr);
1233         ib->ptr[ib->length_dw++] = incr; /* increment size */
1234         ib->ptr[ib->length_dw++] = 0;
1235         ib->ptr[ib->length_dw++] = count - 1; /* number of entries */
1236 }
1237
1238 /**
1239  * sdma_v5_0_ring_pad_ib - pad the IB
1240  * @ring: amdgpu_ring structure holding ring information
1241  * @ib: indirect buffer to fill with padding
1242  *
1243  * Pad the IB with NOPs to a boundary multiple of 8.
1244  */
1245 static void sdma_v5_0_ring_pad_ib(struct amdgpu_ring *ring, struct amdgpu_ib *ib)
1246 {
1247         struct amdgpu_sdma_instance *sdma = amdgpu_sdma_get_instance_from_ring(ring);
1248         u32 pad_count;
1249         int i;
1250
1251         pad_count = (-ib->length_dw) & 0x7;
1252         for (i = 0; i < pad_count; i++)
1253                 if (sdma && sdma->burst_nop && (i == 0))
1254                         ib->ptr[ib->length_dw++] =
1255                                 SDMA_PKT_HEADER_OP(SDMA_OP_NOP) |
1256                                 SDMA_PKT_NOP_HEADER_COUNT(pad_count - 1);
1257                 else
1258                         ib->ptr[ib->length_dw++] =
1259                                 SDMA_PKT_HEADER_OP(SDMA_OP_NOP);
1260 }
1261
1262
1263 /**
1264  * sdma_v5_0_ring_emit_pipeline_sync - sync the pipeline
1265  *
1266  * @ring: amdgpu_ring pointer
1267  *
1268  * Make sure all previous operations are completed (CIK).
1269  */
1270 static void sdma_v5_0_ring_emit_pipeline_sync(struct amdgpu_ring *ring)
1271 {
1272         uint32_t seq = ring->fence_drv.sync_seq;
1273         uint64_t addr = ring->fence_drv.gpu_addr;
1274
1275         /* wait for idle */
1276         amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_POLL_REGMEM) |
1277                           SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(0) |
1278                           SDMA_PKT_POLL_REGMEM_HEADER_FUNC(3) | /* equal */
1279                           SDMA_PKT_POLL_REGMEM_HEADER_MEM_POLL(1));
1280         amdgpu_ring_write(ring, addr & 0xfffffffc);
1281         amdgpu_ring_write(ring, upper_32_bits(addr) & 0xffffffff);
1282         amdgpu_ring_write(ring, seq); /* reference */
1283         amdgpu_ring_write(ring, 0xffffffff); /* mask */
1284         amdgpu_ring_write(ring, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) |
1285                           SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(4)); /* retry count, poll interval */
1286 }
1287
1288
1289 /**
1290  * sdma_v5_0_ring_emit_vm_flush - vm flush using sDMA
1291  *
1292  * @ring: amdgpu_ring pointer
1293  * @vmid: vmid number to use
1294  * @pd_addr: address
1295  *
1296  * Update the page table base and flush the VM TLB
1297  * using sDMA (NAVI10).
1298  */
1299 static void sdma_v5_0_ring_emit_vm_flush(struct amdgpu_ring *ring,
1300                                          unsigned vmid, uint64_t pd_addr)
1301 {
1302         amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr);
1303 }
1304
1305 static void sdma_v5_0_ring_emit_wreg(struct amdgpu_ring *ring,
1306                                      uint32_t reg, uint32_t val)
1307 {
1308         amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_SRBM_WRITE) |
1309                           SDMA_PKT_SRBM_WRITE_HEADER_BYTE_EN(0xf));
1310         amdgpu_ring_write(ring, reg);
1311         amdgpu_ring_write(ring, val);
1312 }
1313
1314 static void sdma_v5_0_ring_emit_reg_wait(struct amdgpu_ring *ring, uint32_t reg,
1315                                          uint32_t val, uint32_t mask)
1316 {
1317         amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_POLL_REGMEM) |
1318                           SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(0) |
1319                           SDMA_PKT_POLL_REGMEM_HEADER_FUNC(3)); /* equal */
1320         amdgpu_ring_write(ring, reg << 2);
1321         amdgpu_ring_write(ring, 0);
1322         amdgpu_ring_write(ring, val); /* reference */
1323         amdgpu_ring_write(ring, mask); /* mask */
1324         amdgpu_ring_write(ring, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) |
1325                           SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(10));
1326 }
1327
1328 static void sdma_v5_0_ring_emit_reg_write_reg_wait(struct amdgpu_ring *ring,
1329                                                    uint32_t reg0, uint32_t reg1,
1330                                                    uint32_t ref, uint32_t mask)
1331 {
1332         amdgpu_ring_emit_wreg(ring, reg0, ref);
1333         /* wait for a cycle to reset vm_inv_eng*_ack */
1334         amdgpu_ring_emit_reg_wait(ring, reg0, 0, 0);
1335         amdgpu_ring_emit_reg_wait(ring, reg1, mask, mask);
1336 }
1337
1338 static int sdma_v5_0_early_init(void *handle)
1339 {
1340         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1341
1342         sdma_v5_0_set_ring_funcs(adev);
1343         sdma_v5_0_set_buffer_funcs(adev);
1344         sdma_v5_0_set_vm_pte_funcs(adev);
1345         sdma_v5_0_set_irq_funcs(adev);
1346         sdma_v5_0_set_mqd_funcs(adev);
1347
1348         return 0;
1349 }
1350
1351
1352 static int sdma_v5_0_sw_init(void *handle)
1353 {
1354         struct amdgpu_ring *ring;
1355         int r, i;
1356         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1357
1358         /* SDMA trap event */
1359         r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_SDMA0,
1360                               SDMA0_5_0__SRCID__SDMA_TRAP,
1361                               &adev->sdma.trap_irq);
1362         if (r)
1363                 return r;
1364
1365         /* SDMA trap event */
1366         r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_SDMA1,
1367                               SDMA1_5_0__SRCID__SDMA_TRAP,
1368                               &adev->sdma.trap_irq);
1369         if (r)
1370                 return r;
1371
1372         r = sdma_v5_0_init_microcode(adev);
1373         if (r) {
1374                 DRM_ERROR("Failed to load sdma firmware!\n");
1375                 return r;
1376         }
1377
1378         for (i = 0; i < adev->sdma.num_instances; i++) {
1379                 ring = &adev->sdma.instance[i].ring;
1380                 ring->ring_obj = NULL;
1381                 ring->use_doorbell = true;
1382
1383                 DRM_DEBUG("SDMA %d use_doorbell being set to: [%s]\n", i,
1384                                 ring->use_doorbell?"true":"false");
1385
1386                 ring->doorbell_index = (i == 0) ?
1387                         (adev->doorbell_index.sdma_engine[0] << 1) //get DWORD offset
1388                         : (adev->doorbell_index.sdma_engine[1] << 1); // get DWORD offset
1389
1390                 ring->vm_hub = AMDGPU_GFXHUB(0);
1391                 sprintf(ring->name, "sdma%d", i);
1392                 r = amdgpu_ring_init(adev, ring, 1024, &adev->sdma.trap_irq,
1393                                      (i == 0) ? AMDGPU_SDMA_IRQ_INSTANCE0 :
1394                                      AMDGPU_SDMA_IRQ_INSTANCE1,
1395                                      AMDGPU_RING_PRIO_DEFAULT, NULL);
1396                 if (r)
1397                         return r;
1398         }
1399
1400         return r;
1401 }
1402
1403 static int sdma_v5_0_sw_fini(void *handle)
1404 {
1405         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1406         int i;
1407
1408         for (i = 0; i < adev->sdma.num_instances; i++)
1409                 amdgpu_ring_fini(&adev->sdma.instance[i].ring);
1410
1411         amdgpu_sdma_destroy_inst_ctx(adev, false);
1412
1413         return 0;
1414 }
1415
1416 static int sdma_v5_0_hw_init(void *handle)
1417 {
1418         int r;
1419         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1420
1421         sdma_v5_0_init_golden_registers(adev);
1422
1423         r = sdma_v5_0_start(adev);
1424
1425         return r;
1426 }
1427
1428 static int sdma_v5_0_hw_fini(void *handle)
1429 {
1430         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1431
1432         if (amdgpu_sriov_vf(adev)) {
1433                 /* disable the scheduler for SDMA */
1434                 amdgpu_sdma_unset_buffer_funcs_helper(adev);
1435                 return 0;
1436         }
1437
1438         sdma_v5_0_ctx_switch_enable(adev, false);
1439         sdma_v5_0_enable(adev, false);
1440
1441         return 0;
1442 }
1443
1444 static int sdma_v5_0_suspend(void *handle)
1445 {
1446         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1447
1448         return sdma_v5_0_hw_fini(adev);
1449 }
1450
1451 static int sdma_v5_0_resume(void *handle)
1452 {
1453         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1454
1455         return sdma_v5_0_hw_init(adev);
1456 }
1457
1458 static bool sdma_v5_0_is_idle(void *handle)
1459 {
1460         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1461         u32 i;
1462
1463         for (i = 0; i < adev->sdma.num_instances; i++) {
1464                 u32 tmp = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_STATUS_REG));
1465
1466                 if (!(tmp & SDMA0_STATUS_REG__IDLE_MASK))
1467                         return false;
1468         }
1469
1470         return true;
1471 }
1472
1473 static int sdma_v5_0_wait_for_idle(void *handle)
1474 {
1475         unsigned i;
1476         u32 sdma0, sdma1;
1477         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1478
1479         for (i = 0; i < adev->usec_timeout; i++) {
1480                 sdma0 = RREG32(sdma_v5_0_get_reg_offset(adev, 0, mmSDMA0_STATUS_REG));
1481                 sdma1 = RREG32(sdma_v5_0_get_reg_offset(adev, 1, mmSDMA0_STATUS_REG));
1482
1483                 if (sdma0 & sdma1 & SDMA0_STATUS_REG__IDLE_MASK)
1484                         return 0;
1485                 udelay(1);
1486         }
1487         return -ETIMEDOUT;
1488 }
1489
1490 static int sdma_v5_0_soft_reset(void *handle)
1491 {
1492         /* todo */
1493
1494         return 0;
1495 }
1496
1497 static int sdma_v5_0_ring_preempt_ib(struct amdgpu_ring *ring)
1498 {
1499         int i, r = 0;
1500         struct amdgpu_device *adev = ring->adev;
1501         u32 index = 0;
1502         u64 sdma_gfx_preempt;
1503
1504         amdgpu_sdma_get_index_from_ring(ring, &index);
1505         if (index == 0)
1506                 sdma_gfx_preempt = mmSDMA0_GFX_PREEMPT;
1507         else
1508                 sdma_gfx_preempt = mmSDMA1_GFX_PREEMPT;
1509
1510         /* assert preemption condition */
1511         amdgpu_ring_set_preempt_cond_exec(ring, false);
1512
1513         /* emit the trailing fence */
1514         ring->trail_seq += 1;
1515         amdgpu_ring_alloc(ring, 10);
1516         sdma_v5_0_ring_emit_fence(ring, ring->trail_fence_gpu_addr,
1517                                   ring->trail_seq, 0);
1518         amdgpu_ring_commit(ring);
1519
1520         /* assert IB preemption */
1521         WREG32(sdma_gfx_preempt, 1);
1522
1523         /* poll the trailing fence */
1524         for (i = 0; i < adev->usec_timeout; i++) {
1525                 if (ring->trail_seq ==
1526                     le32_to_cpu(*(ring->trail_fence_cpu_addr)))
1527                         break;
1528                 udelay(1);
1529         }
1530
1531         if (i >= adev->usec_timeout) {
1532                 r = -EINVAL;
1533                 DRM_ERROR("ring %d failed to be preempted\n", ring->idx);
1534         }
1535
1536         /* deassert IB preemption */
1537         WREG32(sdma_gfx_preempt, 0);
1538
1539         /* deassert the preemption condition */
1540         amdgpu_ring_set_preempt_cond_exec(ring, true);
1541         return r;
1542 }
1543
1544 static int sdma_v5_0_set_trap_irq_state(struct amdgpu_device *adev,
1545                                         struct amdgpu_irq_src *source,
1546                                         unsigned type,
1547                                         enum amdgpu_interrupt_state state)
1548 {
1549         u32 sdma_cntl;
1550
1551         if (!amdgpu_sriov_vf(adev)) {
1552                 u32 reg_offset = (type == AMDGPU_SDMA_IRQ_INSTANCE0) ?
1553                         sdma_v5_0_get_reg_offset(adev, 0, mmSDMA0_CNTL) :
1554                         sdma_v5_0_get_reg_offset(adev, 1, mmSDMA0_CNTL);
1555
1556                 sdma_cntl = RREG32(reg_offset);
1557                 sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE,
1558                                           state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0);
1559                 WREG32(reg_offset, sdma_cntl);
1560         }
1561
1562         return 0;
1563 }
1564
1565 static int sdma_v5_0_process_trap_irq(struct amdgpu_device *adev,
1566                                       struct amdgpu_irq_src *source,
1567                                       struct amdgpu_iv_entry *entry)
1568 {
1569         uint32_t mes_queue_id = entry->src_data[0];
1570
1571         DRM_DEBUG("IH: SDMA trap\n");
1572
1573         if (adev->enable_mes && (mes_queue_id & AMDGPU_FENCE_MES_QUEUE_FLAG)) {
1574                 struct amdgpu_mes_queue *queue;
1575
1576                 mes_queue_id &= AMDGPU_FENCE_MES_QUEUE_ID_MASK;
1577
1578                 spin_lock(&adev->mes.queue_id_lock);
1579                 queue = idr_find(&adev->mes.queue_id_idr, mes_queue_id);
1580                 if (queue) {
1581                         DRM_DEBUG("process smda queue id = %d\n", mes_queue_id);
1582                         amdgpu_fence_process(queue->ring);
1583                 }
1584                 spin_unlock(&adev->mes.queue_id_lock);
1585                 return 0;
1586         }
1587
1588         switch (entry->client_id) {
1589         case SOC15_IH_CLIENTID_SDMA0:
1590                 switch (entry->ring_id) {
1591                 case 0:
1592                         amdgpu_fence_process(&adev->sdma.instance[0].ring);
1593                         break;
1594                 case 1:
1595                         /* XXX compute */
1596                         break;
1597                 case 2:
1598                         /* XXX compute */
1599                         break;
1600                 case 3:
1601                         /* XXX page queue*/
1602                         break;
1603                 }
1604                 break;
1605         case SOC15_IH_CLIENTID_SDMA1:
1606                 switch (entry->ring_id) {
1607                 case 0:
1608                         amdgpu_fence_process(&adev->sdma.instance[1].ring);
1609                         break;
1610                 case 1:
1611                         /* XXX compute */
1612                         break;
1613                 case 2:
1614                         /* XXX compute */
1615                         break;
1616                 case 3:
1617                         /* XXX page queue*/
1618                         break;
1619                 }
1620                 break;
1621         }
1622         return 0;
1623 }
1624
1625 static int sdma_v5_0_process_illegal_inst_irq(struct amdgpu_device *adev,
1626                                               struct amdgpu_irq_src *source,
1627                                               struct amdgpu_iv_entry *entry)
1628 {
1629         return 0;
1630 }
1631
1632 static void sdma_v5_0_update_medium_grain_clock_gating(struct amdgpu_device *adev,
1633                                                        bool enable)
1634 {
1635         uint32_t data, def;
1636         int i;
1637
1638         for (i = 0; i < adev->sdma.num_instances; i++) {
1639                 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_SDMA_MGCG)) {
1640                         /* Enable sdma clock gating */
1641                         def = data = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_CLK_CTRL));
1642                         data &= ~(SDMA0_CLK_CTRL__SOFT_OVERRIDE7_MASK |
1643                                   SDMA0_CLK_CTRL__SOFT_OVERRIDE6_MASK |
1644                                   SDMA0_CLK_CTRL__SOFT_OVERRIDE5_MASK |
1645                                   SDMA0_CLK_CTRL__SOFT_OVERRIDE4_MASK |
1646                                   SDMA0_CLK_CTRL__SOFT_OVERRIDE3_MASK |
1647                                   SDMA0_CLK_CTRL__SOFT_OVERRIDE2_MASK |
1648                                   SDMA0_CLK_CTRL__SOFT_OVERRIDE1_MASK |
1649                                   SDMA0_CLK_CTRL__SOFT_OVERRIDE0_MASK);
1650                         if (def != data)
1651                                 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_CLK_CTRL), data);
1652                 } else {
1653                         /* Disable sdma clock gating */
1654                         def = data = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_CLK_CTRL));
1655                         data |= (SDMA0_CLK_CTRL__SOFT_OVERRIDE7_MASK |
1656                                  SDMA0_CLK_CTRL__SOFT_OVERRIDE6_MASK |
1657                                  SDMA0_CLK_CTRL__SOFT_OVERRIDE5_MASK |
1658                                  SDMA0_CLK_CTRL__SOFT_OVERRIDE4_MASK |
1659                                  SDMA0_CLK_CTRL__SOFT_OVERRIDE3_MASK |
1660                                  SDMA0_CLK_CTRL__SOFT_OVERRIDE2_MASK |
1661                                  SDMA0_CLK_CTRL__SOFT_OVERRIDE1_MASK |
1662                                  SDMA0_CLK_CTRL__SOFT_OVERRIDE0_MASK);
1663                         if (def != data)
1664                                 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_CLK_CTRL), data);
1665                 }
1666         }
1667 }
1668
1669 static void sdma_v5_0_update_medium_grain_light_sleep(struct amdgpu_device *adev,
1670                                                       bool enable)
1671 {
1672         uint32_t data, def;
1673         int i;
1674
1675         for (i = 0; i < adev->sdma.num_instances; i++) {
1676                 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_SDMA_LS)) {
1677                         /* Enable sdma mem light sleep */
1678                         def = data = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_POWER_CNTL));
1679                         data |= SDMA0_POWER_CNTL__MEM_POWER_OVERRIDE_MASK;
1680                         if (def != data)
1681                                 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_POWER_CNTL), data);
1682
1683                 } else {
1684                         /* Disable sdma mem light sleep */
1685                         def = data = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_POWER_CNTL));
1686                         data &= ~SDMA0_POWER_CNTL__MEM_POWER_OVERRIDE_MASK;
1687                         if (def != data)
1688                                 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_POWER_CNTL), data);
1689
1690                 }
1691         }
1692 }
1693
1694 static int sdma_v5_0_set_clockgating_state(void *handle,
1695                                            enum amd_clockgating_state state)
1696 {
1697         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1698
1699         if (amdgpu_sriov_vf(adev))
1700                 return 0;
1701
1702         switch (adev->ip_versions[SDMA0_HWIP][0]) {
1703         case IP_VERSION(5, 0, 0):
1704         case IP_VERSION(5, 0, 2):
1705         case IP_VERSION(5, 0, 5):
1706                 sdma_v5_0_update_medium_grain_clock_gating(adev,
1707                                 state == AMD_CG_STATE_GATE);
1708                 sdma_v5_0_update_medium_grain_light_sleep(adev,
1709                                 state == AMD_CG_STATE_GATE);
1710                 break;
1711         default:
1712                 break;
1713         }
1714
1715         return 0;
1716 }
1717
1718 static int sdma_v5_0_set_powergating_state(void *handle,
1719                                           enum amd_powergating_state state)
1720 {
1721         return 0;
1722 }
1723
1724 static void sdma_v5_0_get_clockgating_state(void *handle, u64 *flags)
1725 {
1726         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1727         int data;
1728
1729         if (amdgpu_sriov_vf(adev))
1730                 *flags = 0;
1731
1732         /* AMD_CG_SUPPORT_SDMA_MGCG */
1733         data = RREG32(sdma_v5_0_get_reg_offset(adev, 0, mmSDMA0_CLK_CTRL));
1734         if (!(data & SDMA0_CLK_CTRL__SOFT_OVERRIDE7_MASK))
1735                 *flags |= AMD_CG_SUPPORT_SDMA_MGCG;
1736
1737         /* AMD_CG_SUPPORT_SDMA_LS */
1738         data = RREG32(sdma_v5_0_get_reg_offset(adev, 0, mmSDMA0_POWER_CNTL));
1739         if (data & SDMA0_POWER_CNTL__MEM_POWER_OVERRIDE_MASK)
1740                 *flags |= AMD_CG_SUPPORT_SDMA_LS;
1741 }
1742
1743 const struct amd_ip_funcs sdma_v5_0_ip_funcs = {
1744         .name = "sdma_v5_0",
1745         .early_init = sdma_v5_0_early_init,
1746         .late_init = NULL,
1747         .sw_init = sdma_v5_0_sw_init,
1748         .sw_fini = sdma_v5_0_sw_fini,
1749         .hw_init = sdma_v5_0_hw_init,
1750         .hw_fini = sdma_v5_0_hw_fini,
1751         .suspend = sdma_v5_0_suspend,
1752         .resume = sdma_v5_0_resume,
1753         .is_idle = sdma_v5_0_is_idle,
1754         .wait_for_idle = sdma_v5_0_wait_for_idle,
1755         .soft_reset = sdma_v5_0_soft_reset,
1756         .set_clockgating_state = sdma_v5_0_set_clockgating_state,
1757         .set_powergating_state = sdma_v5_0_set_powergating_state,
1758         .get_clockgating_state = sdma_v5_0_get_clockgating_state,
1759 };
1760
1761 static const struct amdgpu_ring_funcs sdma_v5_0_ring_funcs = {
1762         .type = AMDGPU_RING_TYPE_SDMA,
1763         .align_mask = 0xf,
1764         .nop = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP),
1765         .support_64bit_ptrs = true,
1766         .secure_submission_supported = true,
1767         .get_rptr = sdma_v5_0_ring_get_rptr,
1768         .get_wptr = sdma_v5_0_ring_get_wptr,
1769         .set_wptr = sdma_v5_0_ring_set_wptr,
1770         .emit_frame_size =
1771                 5 + /* sdma_v5_0_ring_init_cond_exec */
1772                 6 + /* sdma_v5_0_ring_emit_hdp_flush */
1773                 3 + /* hdp_invalidate */
1774                 6 + /* sdma_v5_0_ring_emit_pipeline_sync */
1775                 /* sdma_v5_0_ring_emit_vm_flush */
1776                 SOC15_FLUSH_GPU_TLB_NUM_WREG * 3 +
1777                 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 6 * 2 +
1778                 10 + 10 + 10, /* sdma_v5_0_ring_emit_fence x3 for user fence, vm fence */
1779         .emit_ib_size = 5 + 7 + 6, /* sdma_v5_0_ring_emit_ib */
1780         .emit_ib = sdma_v5_0_ring_emit_ib,
1781         .emit_mem_sync = sdma_v5_0_ring_emit_mem_sync,
1782         .emit_fence = sdma_v5_0_ring_emit_fence,
1783         .emit_pipeline_sync = sdma_v5_0_ring_emit_pipeline_sync,
1784         .emit_vm_flush = sdma_v5_0_ring_emit_vm_flush,
1785         .emit_hdp_flush = sdma_v5_0_ring_emit_hdp_flush,
1786         .test_ring = sdma_v5_0_ring_test_ring,
1787         .test_ib = sdma_v5_0_ring_test_ib,
1788         .insert_nop = sdma_v5_0_ring_insert_nop,
1789         .pad_ib = sdma_v5_0_ring_pad_ib,
1790         .emit_wreg = sdma_v5_0_ring_emit_wreg,
1791         .emit_reg_wait = sdma_v5_0_ring_emit_reg_wait,
1792         .emit_reg_write_reg_wait = sdma_v5_0_ring_emit_reg_write_reg_wait,
1793         .init_cond_exec = sdma_v5_0_ring_init_cond_exec,
1794         .patch_cond_exec = sdma_v5_0_ring_patch_cond_exec,
1795         .preempt_ib = sdma_v5_0_ring_preempt_ib,
1796 };
1797
1798 static void sdma_v5_0_set_ring_funcs(struct amdgpu_device *adev)
1799 {
1800         int i;
1801
1802         for (i = 0; i < adev->sdma.num_instances; i++) {
1803                 adev->sdma.instance[i].ring.funcs = &sdma_v5_0_ring_funcs;
1804                 adev->sdma.instance[i].ring.me = i;
1805         }
1806 }
1807
1808 static const struct amdgpu_irq_src_funcs sdma_v5_0_trap_irq_funcs = {
1809         .set = sdma_v5_0_set_trap_irq_state,
1810         .process = sdma_v5_0_process_trap_irq,
1811 };
1812
1813 static const struct amdgpu_irq_src_funcs sdma_v5_0_illegal_inst_irq_funcs = {
1814         .process = sdma_v5_0_process_illegal_inst_irq,
1815 };
1816
1817 static void sdma_v5_0_set_irq_funcs(struct amdgpu_device *adev)
1818 {
1819         adev->sdma.trap_irq.num_types = AMDGPU_SDMA_IRQ_INSTANCE0 +
1820                                         adev->sdma.num_instances;
1821         adev->sdma.trap_irq.funcs = &sdma_v5_0_trap_irq_funcs;
1822         adev->sdma.illegal_inst_irq.funcs = &sdma_v5_0_illegal_inst_irq_funcs;
1823 }
1824
1825 /**
1826  * sdma_v5_0_emit_copy_buffer - copy buffer using the sDMA engine
1827  *
1828  * @ib: indirect buffer to copy to
1829  * @src_offset: src GPU address
1830  * @dst_offset: dst GPU address
1831  * @byte_count: number of bytes to xfer
1832  * @tmz: if a secure copy should be used
1833  *
1834  * Copy GPU buffers using the DMA engine (NAVI10).
1835  * Used by the amdgpu ttm implementation to move pages if
1836  * registered as the asic copy callback.
1837  */
1838 static void sdma_v5_0_emit_copy_buffer(struct amdgpu_ib *ib,
1839                                        uint64_t src_offset,
1840                                        uint64_t dst_offset,
1841                                        uint32_t byte_count,
1842                                        bool tmz)
1843 {
1844         ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_COPY) |
1845                 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_COPY_LINEAR) |
1846                 SDMA_PKT_COPY_LINEAR_HEADER_TMZ(tmz ? 1 : 0);
1847         ib->ptr[ib->length_dw++] = byte_count - 1;
1848         ib->ptr[ib->length_dw++] = 0; /* src/dst endian swap */
1849         ib->ptr[ib->length_dw++] = lower_32_bits(src_offset);
1850         ib->ptr[ib->length_dw++] = upper_32_bits(src_offset);
1851         ib->ptr[ib->length_dw++] = lower_32_bits(dst_offset);
1852         ib->ptr[ib->length_dw++] = upper_32_bits(dst_offset);
1853 }
1854
1855 /**
1856  * sdma_v5_0_emit_fill_buffer - fill buffer using the sDMA engine
1857  *
1858  * @ib: indirect buffer to fill
1859  * @src_data: value to write to buffer
1860  * @dst_offset: dst GPU address
1861  * @byte_count: number of bytes to xfer
1862  *
1863  * Fill GPU buffers using the DMA engine (NAVI10).
1864  */
1865 static void sdma_v5_0_emit_fill_buffer(struct amdgpu_ib *ib,
1866                                        uint32_t src_data,
1867                                        uint64_t dst_offset,
1868                                        uint32_t byte_count)
1869 {
1870         ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_CONST_FILL);
1871         ib->ptr[ib->length_dw++] = lower_32_bits(dst_offset);
1872         ib->ptr[ib->length_dw++] = upper_32_bits(dst_offset);
1873         ib->ptr[ib->length_dw++] = src_data;
1874         ib->ptr[ib->length_dw++] = byte_count - 1;
1875 }
1876
1877 static const struct amdgpu_buffer_funcs sdma_v5_0_buffer_funcs = {
1878         .copy_max_bytes = 0x400000,
1879         .copy_num_dw = 7,
1880         .emit_copy_buffer = sdma_v5_0_emit_copy_buffer,
1881
1882         .fill_max_bytes = 0x400000,
1883         .fill_num_dw = 5,
1884         .emit_fill_buffer = sdma_v5_0_emit_fill_buffer,
1885 };
1886
1887 static void sdma_v5_0_set_buffer_funcs(struct amdgpu_device *adev)
1888 {
1889         if (adev->mman.buffer_funcs == NULL) {
1890                 adev->mman.buffer_funcs = &sdma_v5_0_buffer_funcs;
1891                 adev->mman.buffer_funcs_ring = &adev->sdma.instance[0].ring;
1892         }
1893 }
1894
1895 static const struct amdgpu_vm_pte_funcs sdma_v5_0_vm_pte_funcs = {
1896         .copy_pte_num_dw = 7,
1897         .copy_pte = sdma_v5_0_vm_copy_pte,
1898         .write_pte = sdma_v5_0_vm_write_pte,
1899         .set_pte_pde = sdma_v5_0_vm_set_pte_pde,
1900 };
1901
1902 static void sdma_v5_0_set_vm_pte_funcs(struct amdgpu_device *adev)
1903 {
1904         unsigned i;
1905
1906         if (adev->vm_manager.vm_pte_funcs == NULL) {
1907                 adev->vm_manager.vm_pte_funcs = &sdma_v5_0_vm_pte_funcs;
1908                 for (i = 0; i < adev->sdma.num_instances; i++) {
1909                         adev->vm_manager.vm_pte_scheds[i] =
1910                                 &adev->sdma.instance[i].ring.sched;
1911                 }
1912                 adev->vm_manager.vm_pte_num_scheds = adev->sdma.num_instances;
1913         }
1914 }
1915
1916 const struct amdgpu_ip_block_version sdma_v5_0_ip_block = {
1917         .type = AMD_IP_BLOCK_TYPE_SDMA,
1918         .major = 5,
1919         .minor = 0,
1920         .rev = 0,
1921         .funcs = &sdma_v5_0_ip_funcs,
1922 };