drivers/tty/serial/samsung_tty.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Driver core for Samsung SoC onboard UARTs.
   4  *
   5  * Ben Dooks, Copyright (c) 2003-2008 Simtec Electronics
   6  *      http://armlinux.simtec.co.uk/
   7  */
   8
   9 /* Note on 2410 error handling
  10  *
  11  * The s3c2410 manual has a love/hate affair with the contents of the
  12  * UERSTAT register in the UART blocks, and keeps marking some of the
  13  * error bits as reserved. Having checked with the s3c2410x01,
  14  * it copes with BREAKs properly, so I am happy to ignore the RESERVED
  15  * feature from the latter versions of the manual.
  16  *
  17  * If it becomes aparrent that latter versions of the 2410 remove these
  18  * bits, then action will have to be taken to differentiate the versions
  19  * and change the policy on BREAK
  20  *
  21  * BJD, 04-Nov-2004
  22  */
  23
  24 #include <linux/dmaengine.h>
  25 #include <linux/dma-mapping.h>
  26 #include <linux/slab.h>
  27 #include <linux/math.h>
  28 #include <linux/module.h>
  29 #include <linux/ioport.h>
  30 #include <linux/io.h>
  31 #include <linux/platform_device.h>
  32 #include <linux/init.h>
  33 #include <linux/sysrq.h>
  34 #include <linux/console.h>
  35 #include <linux/tty.h>
  36 #include <linux/tty_flip.h>
  37 #include <linux/serial_core.h>
  38 #include <linux/serial.h>
  39 #include <linux/serial_s3c.h>
  40 #include <linux/delay.h>
  41 #include <linux/clk.h>
  42 #include <linux/cpufreq.h>
  43 #include <linux/of.h>
  44 #include <asm/irq.h>
  45
  46 /* UART name and device definitions */
  47
  48 #define S3C24XX_SERIAL_NAME     "ttySAC"
  49 #define S3C24XX_SERIAL_MAJOR    204
  50 #define S3C24XX_SERIAL_MINOR    64
  51
  52 #ifdef CONFIG_ARM64
  53 #define UART_NR                 12
  54 #else
  55 #define UART_NR                 CONFIG_SERIAL_SAMSUNG_UARTS
  56 #endif
  57
  58 #define S3C24XX_TX_PIO                  1
  59 #define S3C24XX_TX_DMA                  2
  60 #define S3C24XX_RX_PIO                  1
  61 #define S3C24XX_RX_DMA                  2
  62
  63 /* flag to ignore all characters coming in */
  64 #define RXSTAT_DUMMY_READ (0x10000000)
  65
  66 enum s3c24xx_port_type {
  67         TYPE_S3C24XX,
  68         TYPE_S3C6400,
  69         TYPE_APPLE_S5L,
  70 };
  71
  72 struct s3c24xx_uart_info {
  73         const char              *name;
  74         enum s3c24xx_port_type  type;
  75         unsigned int            port_type;
  76         unsigned int            fifosize;
  77         unsigned long           rx_fifomask;
  78         unsigned long           rx_fifoshift;
  79         unsigned long           rx_fifofull;
  80         unsigned long           tx_fifomask;
  81         unsigned long           tx_fifoshift;
  82         unsigned long           tx_fifofull;
  83         unsigned int            def_clk_sel;
  84         unsigned long           num_clks;
  85         unsigned long           clksel_mask;
  86         unsigned long           clksel_shift;
  87         unsigned long           ucon_mask;
  88
  89         /* uart port features */
  90
  91         unsigned int            has_divslot:1;
  92 };
  93
  94 struct s3c24xx_serial_drv_data {
  95         const struct s3c24xx_uart_info  info;
  96         const struct s3c2410_uartcfg    def_cfg;
  97         const unsigned int              fifosize[UART_NR];
  98 };
  99
 100 struct s3c24xx_uart_dma {
 101         unsigned int                    rx_chan_id;
 102         unsigned int                    tx_chan_id;
 103
 104         struct dma_slave_config         rx_conf;
 105         struct dma_slave_config         tx_conf;
 106
 107         struct dma_chan                 *rx_chan;
 108         struct dma_chan                 *tx_chan;
 109
 110         dma_addr_t                      rx_addr;
 111         dma_addr_t                      tx_addr;
 112
 113         dma_cookie_t                    rx_cookie;
 114         dma_cookie_t                    tx_cookie;
 115
 116         char                            *rx_buf;
 117
 118         dma_addr_t                      tx_transfer_addr;
 119
 120         size_t                          rx_size;
 121         size_t                          tx_size;
 122
 123         struct dma_async_tx_descriptor  *tx_desc;
 124         struct dma_async_tx_descriptor  *rx_desc;
 125
 126         int                             tx_bytes_requested;
 127         int                             rx_bytes_requested;
 128 };
 129
 130 struct s3c24xx_uart_port {
 131         unsigned char                   rx_claimed;
 132         unsigned char                   tx_claimed;
 133         unsigned char                   rx_enabled;
 134         unsigned char                   tx_enabled;
 135         unsigned int                    pm_level;
 136         unsigned long                   baudclk_rate;
 137         unsigned int                    min_dma_size;
 138
 139         unsigned int                    rx_irq;
 140         unsigned int                    tx_irq;
 141
 142         unsigned int                    tx_in_progress;
 143         unsigned int                    tx_mode;
 144         unsigned int                    rx_mode;
 145
 146         const struct s3c24xx_uart_info  *info;
 147         struct clk                      *clk;
 148         struct clk                      *baudclk;
 149         struct uart_port                port;
 150         const struct s3c24xx_serial_drv_data    *drv_data;
 151
 152         /* reference to platform data */
 153         const struct s3c2410_uartcfg    *cfg;
 154
 155         struct s3c24xx_uart_dma         *dma;
 156 };
 157
 158 static void s3c24xx_serial_tx_chars(struct s3c24xx_uart_port *ourport);
 159
 160 /* conversion functions */
 161
 162 #define s3c24xx_dev_to_port(__dev) dev_get_drvdata(__dev)
 163
 164 /* register access controls */
 165
 166 #define portaddr(port, reg) ((port)->membase + (reg))
 167 #define portaddrl(port, reg) \
 168         ((unsigned long *)(unsigned long)((port)->membase + (reg)))
 169
 170 static u32 rd_reg(const struct uart_port *port, u32 reg)
 171 {
 172         switch (port->iotype) {
 173         case UPIO_MEM:
 174                 return readb_relaxed(portaddr(port, reg));
 175         case UPIO_MEM32:
 176                 return readl_relaxed(portaddr(port, reg));
 177         default:
 178                 return 0;
 179         }
 180         return 0;
 181 }
 182
 183 #define rd_regl(port, reg) (readl_relaxed(portaddr(port, reg)))
 184
 185 static void wr_reg(const struct uart_port *port, u32 reg, u32 val)
 186 {
 187         switch (port->iotype) {
 188         case UPIO_MEM:
 189                 writeb_relaxed(val, portaddr(port, reg));
 190                 break;
 191         case UPIO_MEM32:
 192                 writel_relaxed(val, portaddr(port, reg));
 193                 break;
 194         }
 195 }
 196
 197 #define wr_regl(port, reg, val) writel_relaxed(val, portaddr(port, reg))
 198
 199 /* Byte-order aware bit setting/clearing functions. */
 200
 201 static inline void s3c24xx_set_bit(const struct uart_port *port, int idx,
 202                                    unsigned int reg)
 203 {
 204         unsigned long flags;
 205         u32 val;
 206
 207         local_irq_save(flags);
 208         val = rd_regl(port, reg);
 209         val |= (1 << idx);
 210         wr_regl(port, reg, val);
 211         local_irq_restore(flags);
 212 }
 213
 214 static inline void s3c24xx_clear_bit(const struct uart_port *port, int idx,
 215                                      unsigned int reg)
 216 {
 217         unsigned long flags;
 218         u32 val;
 219
 220         local_irq_save(flags);
 221         val = rd_regl(port, reg);
 222         val &= ~(1 << idx);
 223         wr_regl(port, reg, val);
 224         local_irq_restore(flags);
 225 }
 226
 227 static inline struct s3c24xx_uart_port *to_ourport(struct uart_port *port)
 228 {
 229         return container_of(port, struct s3c24xx_uart_port, port);
 230 }
 231
 232 /* translate a port to the device name */
 233
 234 static inline const char *s3c24xx_serial_portname(const struct uart_port *port)
 235 {
 236         return to_platform_device(port->dev)->name;
 237 }
 238
 239 static int s3c24xx_serial_txempty_nofifo(const struct uart_port *port)
 240 {
 241         return rd_regl(port, S3C2410_UTRSTAT) & S3C2410_UTRSTAT_TXE;
 242 }
 243
 244 static void s3c24xx_serial_rx_enable(struct uart_port *port)
 245 {
 246         struct s3c24xx_uart_port *ourport = to_ourport(port);
 247         unsigned long flags;
 248         unsigned int ucon, ufcon;
 249         int count = 10000;
 250
 251         spin_lock_irqsave(&port->lock, flags);
 252
 253         while (--count && !s3c24xx_serial_txempty_nofifo(port))
 254                 udelay(100);
 255
 256         ufcon = rd_regl(port, S3C2410_UFCON);
 257         ufcon |= S3C2410_UFCON_RESETRX;
 258         wr_regl(port, S3C2410_UFCON, ufcon);
 259
 260         ucon = rd_regl(port, S3C2410_UCON);
 261         ucon |= S3C2410_UCON_RXIRQMODE;
 262         wr_regl(port, S3C2410_UCON, ucon);
 263
 264         ourport->rx_enabled = 1;
 265         spin_unlock_irqrestore(&port->lock, flags);
 266 }
 267
 268 static void s3c24xx_serial_rx_disable(struct uart_port *port)
 269 {
 270         struct s3c24xx_uart_port *ourport = to_ourport(port);
 271         unsigned long flags;
 272         unsigned int ucon;
 273
 274         spin_lock_irqsave(&port->lock, flags);
 275
 276         ucon = rd_regl(port, S3C2410_UCON);
 277         ucon &= ~S3C2410_UCON_RXIRQMODE;
 278         wr_regl(port, S3C2410_UCON, ucon);
 279
 280         ourport->rx_enabled = 0;
 281         spin_unlock_irqrestore(&port->lock, flags);
 282 }
 283
 284 static void s3c24xx_serial_stop_tx(struct uart_port *port)
 285 {
 286         struct s3c24xx_uart_port *ourport = to_ourport(port);
 287         struct s3c24xx_uart_dma *dma = ourport->dma;
 288         struct dma_tx_state state;
 289         int count;
 290
 291         if (!ourport->tx_enabled)
 292                 return;
 293
 294         switch (ourport->info->type) {
 295         case TYPE_S3C6400:
 296                 s3c24xx_set_bit(port, S3C64XX_UINTM_TXD, S3C64XX_UINTM);
 297                 break;
 298         case TYPE_APPLE_S5L:
 299                 s3c24xx_clear_bit(port, APPLE_S5L_UCON_TXTHRESH_ENA, S3C2410_UCON);
 300                 break;
 301         default:
 302                 disable_irq_nosync(ourport->tx_irq);
 303                 break;
 304         }
 305
 306         if (dma && dma->tx_chan && ourport->tx_in_progress == S3C24XX_TX_DMA) {
 307                 dmaengine_pause(dma->tx_chan);
 308                 dmaengine_tx_status(dma->tx_chan, dma->tx_cookie, &state);
 309                 dmaengine_terminate_all(dma->tx_chan);
 310                 dma_sync_single_for_cpu(dma->tx_chan->device->dev,
 311                                         dma->tx_transfer_addr, dma->tx_size,
 312                                         DMA_TO_DEVICE);
 313                 async_tx_ack(dma->tx_desc);
 314                 count = dma->tx_bytes_requested - state.residue;
 315                 uart_xmit_advance(port, count);
 316         }
 317
 318         ourport->tx_enabled = 0;
 319         ourport->tx_in_progress = 0;
 320
 321         if (port->flags & UPF_CONS_FLOW)
 322                 s3c24xx_serial_rx_enable(port);
 323
 324         ourport->tx_mode = 0;
 325 }
 326
 327 static void s3c24xx_serial_start_next_tx(struct s3c24xx_uart_port *ourport);
 328
 329 static void s3c24xx_serial_tx_dma_complete(void *args)
 330 {
 331         struct s3c24xx_uart_port *ourport = args;
 332         struct uart_port *port = &ourport->port;
 333         struct circ_buf *xmit = &port->state->xmit;
 334         struct s3c24xx_uart_dma *dma = ourport->dma;
 335         struct dma_tx_state state;
 336         unsigned long flags;
 337         int count;
 338
 339         dmaengine_tx_status(dma->tx_chan, dma->tx_cookie, &state);
 340         count = dma->tx_bytes_requested - state.residue;
 341         async_tx_ack(dma->tx_desc);
 342
 343         dma_sync_single_for_cpu(dma->tx_chan->device->dev,
 344                                 dma->tx_transfer_addr, dma->tx_size,
 345                                 DMA_TO_DEVICE);
 346
 347         spin_lock_irqsave(&port->lock, flags);
 348
 349         uart_xmit_advance(port, count);
 350         ourport->tx_in_progress = 0;
 351
 352         if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
 353                 uart_write_wakeup(port);
 354
 355         s3c24xx_serial_start_next_tx(ourport);
 356         spin_unlock_irqrestore(&port->lock, flags);
 357 }
 358
 359 static void enable_tx_dma(struct s3c24xx_uart_port *ourport)
 360 {
 361         const struct uart_port *port = &ourport->port;
 362         u32 ucon;
 363
 364         /* Mask Tx interrupt */
 365         switch (ourport->info->type) {
 366         case TYPE_S3C6400:
 367                 s3c24xx_set_bit(port, S3C64XX_UINTM_TXD, S3C64XX_UINTM);
 368                 break;
 369         case TYPE_APPLE_S5L:
 370                 WARN_ON(1); // No DMA
 371                 break;
 372         default:
 373                 disable_irq_nosync(ourport->tx_irq);
 374                 break;
 375         }
 376
 377         /* Enable tx dma mode */
 378         ucon = rd_regl(port, S3C2410_UCON);
 379         ucon &= ~(S3C64XX_UCON_TXBURST_MASK | S3C64XX_UCON_TXMODE_MASK);
 380         ucon |= S3C64XX_UCON_TXBURST_1;
 381         ucon |= S3C64XX_UCON_TXMODE_DMA;
 382         wr_regl(port,  S3C2410_UCON, ucon);
 383
 384         ourport->tx_mode = S3C24XX_TX_DMA;
 385 }
 386
 387 static void enable_tx_pio(struct s3c24xx_uart_port *ourport)
 388 {
 389         const struct uart_port *port = &ourport->port;
 390         u32 ucon, ufcon;
 391
 392         /* Set ufcon txtrig */
 393         ourport->tx_in_progress = S3C24XX_TX_PIO;
 394         ufcon = rd_regl(port, S3C2410_UFCON);
 395         wr_regl(port,  S3C2410_UFCON, ufcon);
 396
 397         /* Enable tx pio mode */
 398         ucon = rd_regl(port, S3C2410_UCON);
 399         ucon &= ~(S3C64XX_UCON_TXMODE_MASK);
 400         ucon |= S3C64XX_UCON_TXMODE_CPU;
 401         wr_regl(port,  S3C2410_UCON, ucon);
 402
 403         /* Unmask Tx interrupt */
 404         switch (ourport->info->type) {
 405         case TYPE_S3C6400:
 406                 s3c24xx_clear_bit(port, S3C64XX_UINTM_TXD,
 407                                   S3C64XX_UINTM);
 408                 break;
 409         case TYPE_APPLE_S5L:
 410                 ucon |= APPLE_S5L_UCON_TXTHRESH_ENA_MSK;
 411                 wr_regl(port, S3C2410_UCON, ucon);
 412                 break;
 413         default:
 414                 enable_irq(ourport->tx_irq);
 415                 break;
 416         }
 417
 418         ourport->tx_mode = S3C24XX_TX_PIO;
 419
 420         /*
 421          * The Apple version only has edge triggered TX IRQs, so we need
 422          * to kick off the process by sending some characters here.
 423          */
 424         if (ourport->info->type == TYPE_APPLE_S5L)
 425                 s3c24xx_serial_tx_chars(ourport);
 426 }
 427
 428 static void s3c24xx_serial_start_tx_pio(struct s3c24xx_uart_port *ourport)
 429 {
 430         if (ourport->tx_mode != S3C24XX_TX_PIO)
 431                 enable_tx_pio(ourport);
 432 }
 433
 434 static int s3c24xx_serial_start_tx_dma(struct s3c24xx_uart_port *ourport,
 435                                       unsigned int count)
 436 {
 437         struct uart_port *port = &ourport->port;
 438         struct circ_buf *xmit = &port->state->xmit;
 439         struct s3c24xx_uart_dma *dma = ourport->dma;
 440
 441         if (ourport->tx_mode != S3C24XX_TX_DMA)
 442                 enable_tx_dma(ourport);
 443
 444         dma->tx_size = count & ~(dma_get_cache_alignment() - 1);
 445         dma->tx_transfer_addr = dma->tx_addr + xmit->tail;
 446
 447         dma_sync_single_for_device(dma->tx_chan->device->dev,
 448                                    dma->tx_transfer_addr, dma->tx_size,
 449                                    DMA_TO_DEVICE);
 450
 451         dma->tx_desc = dmaengine_prep_slave_single(dma->tx_chan,
 452                                 dma->tx_transfer_addr, dma->tx_size,
 453                                 DMA_MEM_TO_DEV, DMA_PREP_INTERRUPT);
 454         if (!dma->tx_desc) {
 455                 dev_err(ourport->port.dev, "Unable to get desc for Tx\n");
 456                 return -EIO;
 457         }
 458
 459         dma->tx_desc->callback = s3c24xx_serial_tx_dma_complete;
 460         dma->tx_desc->callback_param = ourport;
 461         dma->tx_bytes_requested = dma->tx_size;
 462
 463         ourport->tx_in_progress = S3C24XX_TX_DMA;
 464         dma->tx_cookie = dmaengine_submit(dma->tx_desc);
 465         dma_async_issue_pending(dma->tx_chan);
 466         return 0;
 467 }
 468
 469 static void s3c24xx_serial_start_next_tx(struct s3c24xx_uart_port *ourport)
 470 {
 471         struct uart_port *port = &ourport->port;
 472         struct circ_buf *xmit = &port->state->xmit;
 473         unsigned long count;
 474
 475         /* Get data size up to the end of buffer */
 476         count = CIRC_CNT_TO_END(xmit->head, xmit->tail, UART_XMIT_SIZE);
 477
 478         if (!count) {
 479                 s3c24xx_serial_stop_tx(port);
 480                 return;
 481         }
 482
 483         if (!ourport->dma || !ourport->dma->tx_chan ||
 484             count < ourport->min_dma_size ||
 485             xmit->tail & (dma_get_cache_alignment() - 1))
 486                 s3c24xx_serial_start_tx_pio(ourport);
 487         else
 488                 s3c24xx_serial_start_tx_dma(ourport, count);
 489 }
 490
 491 static void s3c24xx_serial_start_tx(struct uart_port *port)
 492 {
 493         struct s3c24xx_uart_port *ourport = to_ourport(port);
 494         struct circ_buf *xmit = &port->state->xmit;
 495
 496         if (!ourport->tx_enabled) {
 497                 if (port->flags & UPF_CONS_FLOW)
 498                         s3c24xx_serial_rx_disable(port);
 499
 500                 ourport->tx_enabled = 1;
 501                 if (!ourport->dma || !ourport->dma->tx_chan)
 502                         s3c24xx_serial_start_tx_pio(ourport);
 503         }
 504
 505         if (ourport->dma && ourport->dma->tx_chan) {
 506                 if (!uart_circ_empty(xmit) && !ourport->tx_in_progress)
 507                         s3c24xx_serial_start_next_tx(ourport);
 508         }
 509 }
 510
 511 static void s3c24xx_uart_copy_rx_to_tty(struct s3c24xx_uart_port *ourport,
 512                 struct tty_port *tty, int count)
 513 {
 514         struct s3c24xx_uart_dma *dma = ourport->dma;
 515         int copied;
 516
 517         if (!count)
 518                 return;
 519
 520         dma_sync_single_for_cpu(dma->rx_chan->device->dev, dma->rx_addr,
 521                                 dma->rx_size, DMA_FROM_DEVICE);
 522
 523         ourport->port.icount.rx += count;
 524         if (!tty) {
 525                 dev_err(ourport->port.dev, "No tty port\n");
 526                 return;
 527         }
 528         copied = tty_insert_flip_string(tty,
 529                         ((unsigned char *)(ourport->dma->rx_buf)), count);
 530         if (copied != count) {
 531                 WARN_ON(1);
 532                 dev_err(ourport->port.dev, "RxData copy to tty layer failed\n");
 533         }
 534 }
 535
 536 static void s3c24xx_serial_stop_rx(struct uart_port *port)
 537 {
 538         struct s3c24xx_uart_port *ourport = to_ourport(port);
 539         struct s3c24xx_uart_dma *dma = ourport->dma;
 540         struct tty_port *t = &port->state->port;
 541         struct dma_tx_state state;
 542         enum dma_status dma_status;
 543         unsigned int received;
 544
 545         if (ourport->rx_enabled) {
 546                 dev_dbg(port->dev, "stopping rx\n");
 547                 switch (ourport->info->type) {
 548                 case TYPE_S3C6400:
 549                         s3c24xx_set_bit(port, S3C64XX_UINTM_RXD,
 550                                         S3C64XX_UINTM);
 551                         break;
 552                 case TYPE_APPLE_S5L:
 553                         s3c24xx_clear_bit(port, APPLE_S5L_UCON_RXTHRESH_ENA, S3C2410_UCON);
 554                         s3c24xx_clear_bit(port, APPLE_S5L_UCON_RXTO_ENA, S3C2410_UCON);
 555                         break;
 556                 default:
 557                         disable_irq_nosync(ourport->rx_irq);
 558                         break;
 559                 }
 560                 ourport->rx_enabled = 0;
 561         }
 562         if (dma && dma->rx_chan) {
 563                 dmaengine_pause(dma->tx_chan);
 564                 dma_status = dmaengine_tx_status(dma->rx_chan,
 565                                 dma->rx_cookie, &state);
 566                 if (dma_status == DMA_IN_PROGRESS ||
 567                         dma_status == DMA_PAUSED) {
 568                         received = dma->rx_bytes_requested - state.residue;
 569                         dmaengine_terminate_all(dma->rx_chan);
 570                         s3c24xx_uart_copy_rx_to_tty(ourport, t, received);
 571                 }
 572         }
 573 }
 574
 575 static inline const struct s3c24xx_uart_info
 576         *s3c24xx_port_to_info(struct uart_port *port)
 577 {
 578         return to_ourport(port)->info;
 579 }
 580
 581 static inline const struct s3c2410_uartcfg
 582         *s3c24xx_port_to_cfg(const struct uart_port *port)
 583 {
 584         const struct s3c24xx_uart_port *ourport;
 585
 586         if (port->dev == NULL)
 587                 return NULL;
 588
 589         ourport = container_of(port, struct s3c24xx_uart_port, port);
 590         return ourport->cfg;
 591 }
 592
 593 static int s3c24xx_serial_rx_fifocnt(const struct s3c24xx_uart_port *ourport,
 594                                      unsigned long ufstat)
 595 {
 596         const struct s3c24xx_uart_info *info = ourport->info;
 597
 598         if (ufstat & info->rx_fifofull)
 599                 return ourport->port.fifosize;
 600
 601         return (ufstat & info->rx_fifomask) >> info->rx_fifoshift;
 602 }
 603
 604 static void s3c64xx_start_rx_dma(struct s3c24xx_uart_port *ourport);
 605 static void s3c24xx_serial_rx_dma_complete(void *args)
 606 {
 607         struct s3c24xx_uart_port *ourport = args;
 608         struct uart_port *port = &ourport->port;
 609
 610         struct s3c24xx_uart_dma *dma = ourport->dma;
 611         struct tty_port *t = &port->state->port;
 612         struct tty_struct *tty = tty_port_tty_get(&ourport->port.state->port);
 613
 614         struct dma_tx_state state;
 615         unsigned long flags;
 616         int received;
 617
 618         dmaengine_tx_status(dma->rx_chan,  dma->rx_cookie, &state);
 619         received  = dma->rx_bytes_requested - state.residue;
 620         async_tx_ack(dma->rx_desc);
 621
 622         spin_lock_irqsave(&port->lock, flags);
 623
 624         if (received)
 625                 s3c24xx_uart_copy_rx_to_tty(ourport, t, received);
 626
 627         if (tty) {
 628                 tty_flip_buffer_push(t);
 629                 tty_kref_put(tty);
 630         }
 631
 632         s3c64xx_start_rx_dma(ourport);
 633
 634         spin_unlock_irqrestore(&port->lock, flags);
 635 }
 636
 637 static void s3c64xx_start_rx_dma(struct s3c24xx_uart_port *ourport)
 638 {
 639         struct s3c24xx_uart_dma *dma = ourport->dma;
 640
 641         dma_sync_single_for_device(dma->rx_chan->device->dev, dma->rx_addr,
 642                                    dma->rx_size, DMA_FROM_DEVICE);
 643
 644         dma->rx_desc = dmaengine_prep_slave_single(dma->rx_chan,
 645                                 dma->rx_addr, dma->rx_size, DMA_DEV_TO_MEM,
 646                                 DMA_PREP_INTERRUPT);
 647         if (!dma->rx_desc) {
 648                 dev_err(ourport->port.dev, "Unable to get desc for Rx\n");
 649                 return;
 650         }
 651
 652         dma->rx_desc->callback = s3c24xx_serial_rx_dma_complete;
 653         dma->rx_desc->callback_param = ourport;
 654         dma->rx_bytes_requested = dma->rx_size;
 655
 656         dma->rx_cookie = dmaengine_submit(dma->rx_desc);
 657         dma_async_issue_pending(dma->rx_chan);
 658 }
 659
 660 /* ? - where has parity gone?? */
 661 #define S3C2410_UERSTAT_PARITY (0x1000)
 662
 663 static void enable_rx_dma(struct s3c24xx_uart_port *ourport)
 664 {
 665         struct uart_port *port = &ourport->port;
 666         unsigned int ucon;
 667
 668         /* set Rx mode to DMA mode */
 669         ucon = rd_regl(port, S3C2410_UCON);
 670         ucon &= ~(S3C64XX_UCON_RXBURST_MASK |
 671                         S3C64XX_UCON_TIMEOUT_MASK |
 672                         S3C64XX_UCON_EMPTYINT_EN |
 673                         S3C64XX_UCON_DMASUS_EN |
 674                         S3C64XX_UCON_TIMEOUT_EN |
 675                         S3C64XX_UCON_RXMODE_MASK);
 676         ucon |= S3C64XX_UCON_RXBURST_1 |
 677                         0xf << S3C64XX_UCON_TIMEOUT_SHIFT |
 678                         S3C64XX_UCON_EMPTYINT_EN |
 679                         S3C64XX_UCON_TIMEOUT_EN |
 680                         S3C64XX_UCON_RXMODE_DMA;
 681         wr_regl(port, S3C2410_UCON, ucon);
 682
 683         ourport->rx_mode = S3C24XX_RX_DMA;
 684 }
 685
 686 static void enable_rx_pio(struct s3c24xx_uart_port *ourport)
 687 {
 688         struct uart_port *port = &ourport->port;
 689         unsigned int ucon;
 690
 691         /* set Rx mode to DMA mode */
 692         ucon = rd_regl(port, S3C2410_UCON);
 693         ucon &= ~S3C64XX_UCON_RXMODE_MASK;
 694         ucon |= S3C64XX_UCON_RXMODE_CPU;
 695
 696         /* Apple types use these bits for IRQ masks */
 697         if (ourport->info->type != TYPE_APPLE_S5L) {
 698                 ucon &= ~(S3C64XX_UCON_TIMEOUT_MASK |
 699                                 S3C64XX_UCON_EMPTYINT_EN |
 700                                 S3C64XX_UCON_DMASUS_EN |
 701                                 S3C64XX_UCON_TIMEOUT_EN);
 702                 ucon |= 0xf << S3C64XX_UCON_TIMEOUT_SHIFT |
 703                                 S3C64XX_UCON_TIMEOUT_EN;
 704         }
 705         wr_regl(port, S3C2410_UCON, ucon);
 706
 707         ourport->rx_mode = S3C24XX_RX_PIO;
 708 }
 709
 710 static void s3c24xx_serial_rx_drain_fifo(struct s3c24xx_uart_port *ourport);
 711
 712 static irqreturn_t s3c24xx_serial_rx_chars_dma(void *dev_id)
 713 {
 714         unsigned int utrstat, received;
 715         struct s3c24xx_uart_port *ourport = dev_id;
 716         struct uart_port *port = &ourport->port;
 717         struct s3c24xx_uart_dma *dma = ourport->dma;
 718         struct tty_struct *tty = tty_port_tty_get(&ourport->port.state->port);
 719         struct tty_port *t = &port->state->port;
 720         struct dma_tx_state state;
 721
 722         utrstat = rd_regl(port, S3C2410_UTRSTAT);
 723         rd_regl(port, S3C2410_UFSTAT);
 724
 725         spin_lock(&port->lock);
 726
 727         if (!(utrstat & S3C2410_UTRSTAT_TIMEOUT)) {
 728                 s3c64xx_start_rx_dma(ourport);
 729                 if (ourport->rx_mode == S3C24XX_RX_PIO)
 730                         enable_rx_dma(ourport);
 731                 goto finish;
 732         }
 733
 734         if (ourport->rx_mode == S3C24XX_RX_DMA) {
 735                 dmaengine_pause(dma->rx_chan);
 736                 dmaengine_tx_status(dma->rx_chan, dma->rx_cookie, &state);
 737                 dmaengine_terminate_all(dma->rx_chan);
 738                 received = dma->rx_bytes_requested - state.residue;
 739                 s3c24xx_uart_copy_rx_to_tty(ourport, t, received);
 740
 741                 enable_rx_pio(ourport);
 742         }
 743
 744         s3c24xx_serial_rx_drain_fifo(ourport);
 745
 746         if (tty) {
 747                 tty_flip_buffer_push(t);
 748                 tty_kref_put(tty);
 749         }
 750
 751         wr_regl(port, S3C2410_UTRSTAT, S3C2410_UTRSTAT_TIMEOUT);
 752
 753 finish:
 754         spin_unlock(&port->lock);
 755
 756         return IRQ_HANDLED;
 757 }
 758
 759 static void s3c24xx_serial_rx_drain_fifo(struct s3c24xx_uart_port *ourport)
 760 {
 761         struct uart_port *port = &ourport->port;
 762         unsigned int ufcon, ch, flag, ufstat, uerstat;
 763         unsigned int fifocnt = 0;
 764         int max_count = port->fifosize;
 765
 766         while (max_count-- > 0) {
 767                 /*
 768                  * Receive all characters known to be in FIFO
 769                  * before reading FIFO level again
 770                  */
 771                 if (fifocnt == 0) {
 772                         ufstat = rd_regl(port, S3C2410_UFSTAT);
 773                         fifocnt = s3c24xx_serial_rx_fifocnt(ourport, ufstat);
 774                         if (fifocnt == 0)
 775                                 break;
 776                 }
 777                 fifocnt--;
 778
 779                 uerstat = rd_regl(port, S3C2410_UERSTAT);
 780                 ch = rd_reg(port, S3C2410_URXH);
 781
 782                 if (port->flags & UPF_CONS_FLOW) {
 783                         int txe = s3c24xx_serial_txempty_nofifo(port);
 784
 785                         if (ourport->rx_enabled) {
 786                                 if (!txe) {
 787                                         ourport->rx_enabled = 0;
 788                                         continue;
 789                                 }
 790                         } else {
 791                                 if (txe) {
 792                                         ufcon = rd_regl(port, S3C2410_UFCON);
 793                                         ufcon |= S3C2410_UFCON_RESETRX;
 794                                         wr_regl(port, S3C2410_UFCON, ufcon);
 795                                         ourport->rx_enabled = 1;
 796                                         return;
 797                                 }
 798                                 continue;
 799                         }
 800                 }
 801
 802                 /* insert the character into the buffer */
 803
 804                 flag = TTY_NORMAL;
 805                 port->icount.rx++;
 806
 807                 if (unlikely(uerstat & S3C2410_UERSTAT_ANY)) {
 808                         dev_dbg(port->dev,
 809                                 "rxerr: port ch=0x%02x, rxs=0x%08x\n",
 810                                 ch, uerstat);
 811
 812                         /* check for break */
 813                         if (uerstat & S3C2410_UERSTAT_BREAK) {
 814                                 dev_dbg(port->dev, "break!\n");
 815                                 port->icount.brk++;
 816                                 if (uart_handle_break(port))
 817                                         continue; /* Ignore character */
 818                         }
 819
 820                         if (uerstat & S3C2410_UERSTAT_FRAME)
 821                                 port->icount.frame++;
 822                         if (uerstat & S3C2410_UERSTAT_OVERRUN)
 823                                 port->icount.overrun++;
 824
 825                         uerstat &= port->read_status_mask;
 826
 827                         if (uerstat & S3C2410_UERSTAT_BREAK)
 828                                 flag = TTY_BREAK;
 829                         else if (uerstat & S3C2410_UERSTAT_PARITY)
 830                                 flag = TTY_PARITY;
 831                         else if (uerstat & (S3C2410_UERSTAT_FRAME |
 832                                             S3C2410_UERSTAT_OVERRUN))
 833                                 flag = TTY_FRAME;
 834                 }
 835
 836                 if (uart_handle_sysrq_char(port, ch))
 837                         continue; /* Ignore character */
 838
 839                 uart_insert_char(port, uerstat, S3C2410_UERSTAT_OVERRUN,
 840                                  ch, flag);
 841         }
 842
 843         tty_flip_buffer_push(&port->state->port);
 844 }
 845
 846 static irqreturn_t s3c24xx_serial_rx_chars_pio(void *dev_id)
 847 {
 848         struct s3c24xx_uart_port *ourport = dev_id;
 849         struct uart_port *port = &ourport->port;
 850
 851         spin_lock(&port->lock);
 852         s3c24xx_serial_rx_drain_fifo(ourport);
 853         spin_unlock(&port->lock);
 854
 855         return IRQ_HANDLED;
 856 }
 857
 858 static irqreturn_t s3c24xx_serial_rx_irq(int irq, void *dev_id)
 859 {
 860         struct s3c24xx_uart_port *ourport = dev_id;
 861
 862         if (ourport->dma && ourport->dma->rx_chan)
 863                 return s3c24xx_serial_rx_chars_dma(dev_id);
 864         return s3c24xx_serial_rx_chars_pio(dev_id);
 865 }
 866
 867 static void s3c24xx_serial_tx_chars(struct s3c24xx_uart_port *ourport)
 868 {
 869         struct uart_port *port = &ourport->port;
 870         struct circ_buf *xmit = &port->state->xmit;
 871         int count, dma_count = 0;
 872
 873         count = CIRC_CNT_TO_END(xmit->head, xmit->tail, UART_XMIT_SIZE);
 874
 875         if (ourport->dma && ourport->dma->tx_chan &&
 876             count >= ourport->min_dma_size) {
 877                 int align = dma_get_cache_alignment() -
 878                         (xmit->tail & (dma_get_cache_alignment() - 1));
 879                 if (count - align >= ourport->min_dma_size) {
 880                         dma_count = count - align;
 881                         count = align;
 882                 }
 883         }
 884
 885         if (port->x_char) {
 886                 wr_reg(port, S3C2410_UTXH, port->x_char);
 887                 port->icount.tx++;
 888                 port->x_char = 0;
 889                 return;
 890         }
 891
 892         /* if there isn't anything more to transmit, or the uart is now
 893          * stopped, disable the uart and exit
 894          */
 895
 896         if (uart_circ_empty(xmit) || uart_tx_stopped(port)) {
 897                 s3c24xx_serial_stop_tx(port);
 898                 return;
 899         }
 900
 901         /* try and drain the buffer... */
 902
 903         if (count > port->fifosize) {
 904                 count = port->fifosize;
 905                 dma_count = 0;
 906         }
 907
 908         while (!uart_circ_empty(xmit) && count > 0) {
 909                 if (rd_regl(port, S3C2410_UFSTAT) & ourport->info->tx_fifofull)
 910                         break;
 911
 912                 wr_reg(port, S3C2410_UTXH, xmit->buf[xmit->tail]);
 913                 uart_xmit_advance(port, 1);
 914                 count--;
 915         }
 916
 917         if (!count && dma_count) {
 918                 s3c24xx_serial_start_tx_dma(ourport, dma_count);
 919                 return;
 920         }
 921
 922         if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
 923                 uart_write_wakeup(port);
 924
 925         if (uart_circ_empty(xmit))
 926                 s3c24xx_serial_stop_tx(port);
 927 }
 928
 929 static irqreturn_t s3c24xx_serial_tx_irq(int irq, void *id)
 930 {
 931         struct s3c24xx_uart_port *ourport = id;
 932         struct uart_port *port = &ourport->port;
 933
 934         spin_lock(&port->lock);
 935
 936         s3c24xx_serial_tx_chars(ourport);
 937
 938         spin_unlock(&port->lock);
 939         return IRQ_HANDLED;
 940 }
 941
 942 /* interrupt handler for s3c64xx and later SoC's.*/
 943 static irqreturn_t s3c64xx_serial_handle_irq(int irq, void *id)
 944 {
 945         const struct s3c24xx_uart_port *ourport = id;
 946         const struct uart_port *port = &ourport->port;
 947         unsigned int pend = rd_regl(port, S3C64XX_UINTP);
 948         irqreturn_t ret = IRQ_HANDLED;
 949
 950         if (pend & S3C64XX_UINTM_RXD_MSK) {
 951                 ret = s3c24xx_serial_rx_irq(irq, id);
 952                 wr_regl(port, S3C64XX_UINTP, S3C64XX_UINTM_RXD_MSK);
 953         }
 954         if (pend & S3C64XX_UINTM_TXD_MSK) {
 955                 ret = s3c24xx_serial_tx_irq(irq, id);
 956                 wr_regl(port, S3C64XX_UINTP, S3C64XX_UINTM_TXD_MSK);
 957         }
 958         return ret;
 959 }
 960
 961 /* interrupt handler for Apple SoC's.*/
 962 static irqreturn_t apple_serial_handle_irq(int irq, void *id)
 963 {
 964         const struct s3c24xx_uart_port *ourport = id;
 965         const struct uart_port *port = &ourport->port;
 966         unsigned int pend = rd_regl(port, S3C2410_UTRSTAT);
 967         irqreturn_t ret = IRQ_NONE;
 968
 969         if (pend & (APPLE_S5L_UTRSTAT_RXTHRESH | APPLE_S5L_UTRSTAT_RXTO)) {
 970                 wr_regl(port, S3C2410_UTRSTAT,
 971                         APPLE_S5L_UTRSTAT_RXTHRESH | APPLE_S5L_UTRSTAT_RXTO);
 972                 ret = s3c24xx_serial_rx_irq(irq, id);
 973         }
 974         if (pend & APPLE_S5L_UTRSTAT_TXTHRESH) {
 975                 wr_regl(port, S3C2410_UTRSTAT, APPLE_S5L_UTRSTAT_TXTHRESH);
 976                 ret = s3c24xx_serial_tx_irq(irq, id);
 977         }
 978
 979         return ret;
 980 }
 981
 982 static unsigned int s3c24xx_serial_tx_empty(struct uart_port *port)
 983 {
 984         const struct s3c24xx_uart_info *info = s3c24xx_port_to_info(port);
 985         unsigned long ufstat = rd_regl(port, S3C2410_UFSTAT);
 986         unsigned long ufcon = rd_regl(port, S3C2410_UFCON);
 987
 988         if (ufcon & S3C2410_UFCON_FIFOMODE) {
 989                 if ((ufstat & info->tx_fifomask) != 0 ||
 990                     (ufstat & info->tx_fifofull))
 991                         return 0;
 992
 993                 return 1;
 994         }
 995
 996         return s3c24xx_serial_txempty_nofifo(port);
 997 }
 998
 999 /* no modem control lines */
1000 static unsigned int s3c24xx_serial_get_mctrl(struct uart_port *port)
1001 {
1002         unsigned int umstat = rd_reg(port, S3C2410_UMSTAT);
1003
1004         if (umstat & S3C2410_UMSTAT_CTS)
1005                 return TIOCM_CAR | TIOCM_DSR | TIOCM_CTS;
1006         else
1007                 return TIOCM_CAR | TIOCM_DSR;
1008 }
1009
1010 static void s3c24xx_serial_set_mctrl(struct uart_port *port, unsigned int mctrl)
1011 {
1012         unsigned int umcon = rd_regl(port, S3C2410_UMCON);
1013         unsigned int ucon = rd_regl(port, S3C2410_UCON);
1014
1015         if (mctrl & TIOCM_RTS)
1016                 umcon |= S3C2410_UMCOM_RTS_LOW;
1017         else
1018                 umcon &= ~S3C2410_UMCOM_RTS_LOW;
1019
1020         wr_regl(port, S3C2410_UMCON, umcon);
1021
1022         if (mctrl & TIOCM_LOOP)
1023                 ucon |= S3C2410_UCON_LOOPBACK;
1024         else
1025                 ucon &= ~S3C2410_UCON_LOOPBACK;
1026
1027         wr_regl(port, S3C2410_UCON, ucon);
1028 }
1029
1030 static void s3c24xx_serial_break_ctl(struct uart_port *port, int break_state)
1031 {
1032         unsigned long flags;
1033         unsigned int ucon;
1034
1035         spin_lock_irqsave(&port->lock, flags);
1036
1037         ucon = rd_regl(port, S3C2410_UCON);
1038
1039         if (break_state)
1040                 ucon |= S3C2410_UCON_SBREAK;
1041         else
1042                 ucon &= ~S3C2410_UCON_SBREAK;
1043
1044         wr_regl(port, S3C2410_UCON, ucon);
1045
1046         spin_unlock_irqrestore(&port->lock, flags);
1047 }
1048
1049 static int s3c24xx_serial_request_dma(struct s3c24xx_uart_port *p)
1050 {
1051         struct s3c24xx_uart_dma *dma = p->dma;
1052         struct dma_slave_caps dma_caps;
1053         const char *reason = NULL;
1054         int ret;
1055
1056         /* Default slave configuration parameters */
1057         dma->rx_conf.direction          = DMA_DEV_TO_MEM;
1058         dma->rx_conf.src_addr_width     = DMA_SLAVE_BUSWIDTH_1_BYTE;
1059         dma->rx_conf.src_addr           = p->port.mapbase + S3C2410_URXH;
1060         dma->rx_conf.src_maxburst       = 1;
1061
1062         dma->tx_conf.direction          = DMA_MEM_TO_DEV;
1063         dma->tx_conf.dst_addr_width     = DMA_SLAVE_BUSWIDTH_1_BYTE;
1064         dma->tx_conf.dst_addr           = p->port.mapbase + S3C2410_UTXH;
1065         dma->tx_conf.dst_maxburst       = 1;
1066
1067         dma->rx_chan = dma_request_chan(p->port.dev, "rx");
1068
1069         if (IS_ERR(dma->rx_chan)) {
1070                 reason = "DMA RX channel request failed";
1071                 ret = PTR_ERR(dma->rx_chan);
1072                 goto err_warn;
1073         }
1074
1075         ret = dma_get_slave_caps(dma->rx_chan, &dma_caps);
1076         if (ret < 0 ||
1077             dma_caps.residue_granularity < DMA_RESIDUE_GRANULARITY_BURST) {
1078                 reason = "insufficient DMA RX engine capabilities";
1079                 ret = -EOPNOTSUPP;
1080                 goto err_release_rx;
1081         }
1082
1083         dmaengine_slave_config(dma->rx_chan, &dma->rx_conf);
1084
1085         dma->tx_chan = dma_request_chan(p->port.dev, "tx");
1086         if (IS_ERR(dma->tx_chan)) {
1087                 reason = "DMA TX channel request failed";
1088                 ret = PTR_ERR(dma->tx_chan);
1089                 goto err_release_rx;
1090         }
1091
1092         ret = dma_get_slave_caps(dma->tx_chan, &dma_caps);
1093         if (ret < 0 ||
1094             dma_caps.residue_granularity < DMA_RESIDUE_GRANULARITY_BURST) {
1095                 reason = "insufficient DMA TX engine capabilities";
1096                 ret = -EOPNOTSUPP;
1097                 goto err_release_tx;
1098         }
1099
1100         dmaengine_slave_config(dma->tx_chan, &dma->tx_conf);
1101
1102         /* RX buffer */
1103         dma->rx_size = PAGE_SIZE;
1104
1105         dma->rx_buf = kmalloc(dma->rx_size, GFP_KERNEL);
1106         if (!dma->rx_buf) {
1107                 ret = -ENOMEM;
1108                 goto err_release_tx;
1109         }
1110
1111         dma->rx_addr = dma_map_single(dma->rx_chan->device->dev, dma->rx_buf,
1112                                       dma->rx_size, DMA_FROM_DEVICE);
1113         if (dma_mapping_error(dma->rx_chan->device->dev, dma->rx_addr)) {
1114                 reason = "DMA mapping error for RX buffer";
1115                 ret = -EIO;
1116                 goto err_free_rx;
1117         }
1118
1119         /* TX buffer */
1120         dma->tx_addr = dma_map_single(dma->tx_chan->device->dev,
1121                                       p->port.state->xmit.buf, UART_XMIT_SIZE,
1122                                       DMA_TO_DEVICE);
1123         if (dma_mapping_error(dma->tx_chan->device->dev, dma->tx_addr)) {
1124                 reason = "DMA mapping error for TX buffer";
1125                 ret = -EIO;
1126                 goto err_unmap_rx;
1127         }
1128
1129         return 0;
1130
1131 err_unmap_rx:
1132         dma_unmap_single(dma->rx_chan->device->dev, dma->rx_addr,
1133                          dma->rx_size, DMA_FROM_DEVICE);
1134 err_free_rx:
1135         kfree(dma->rx_buf);
1136 err_release_tx:
1137         dma_release_channel(dma->tx_chan);
1138 err_release_rx:
1139         dma_release_channel(dma->rx_chan);
1140 err_warn:
1141         if (reason)
1142                 dev_warn(p->port.dev, "%s, DMA will not be used\n", reason);
1143         return ret;
1144 }
1145
1146 static void s3c24xx_serial_release_dma(struct s3c24xx_uart_port *p)
1147 {
1148         struct s3c24xx_uart_dma *dma = p->dma;
1149
1150         if (dma->rx_chan) {
1151                 dmaengine_terminate_all(dma->rx_chan);
1152                 dma_unmap_single(dma->rx_chan->device->dev, dma->rx_addr,
1153                                  dma->rx_size, DMA_FROM_DEVICE);
1154                 kfree(dma->rx_buf);
1155                 dma_release_channel(dma->rx_chan);
1156                 dma->rx_chan = NULL;
1157         }
1158
1159         if (dma->tx_chan) {
1160                 dmaengine_terminate_all(dma->tx_chan);
1161                 dma_unmap_single(dma->tx_chan->device->dev, dma->tx_addr,
1162                                  UART_XMIT_SIZE, DMA_TO_DEVICE);
1163                 dma_release_channel(dma->tx_chan);
1164                 dma->tx_chan = NULL;
1165         }
1166 }
1167
1168 static void s3c24xx_serial_shutdown(struct uart_port *port)
1169 {
1170         struct s3c24xx_uart_port *ourport = to_ourport(port);
1171
1172         if (ourport->tx_claimed) {
1173                 free_irq(ourport->tx_irq, ourport);
1174                 ourport->tx_enabled = 0;
1175                 ourport->tx_claimed = 0;
1176                 ourport->tx_mode = 0;
1177         }
1178
1179         if (ourport->rx_claimed) {
1180                 free_irq(ourport->rx_irq, ourport);
1181                 ourport->rx_claimed = 0;
1182                 ourport->rx_enabled = 0;
1183         }
1184
1185         if (ourport->dma)
1186                 s3c24xx_serial_release_dma(ourport);
1187
1188         ourport->tx_in_progress = 0;
1189 }
1190
1191 static void s3c64xx_serial_shutdown(struct uart_port *port)
1192 {
1193         struct s3c24xx_uart_port *ourport = to_ourport(port);
1194
1195         ourport->tx_enabled = 0;
1196         ourport->tx_mode = 0;
1197         ourport->rx_enabled = 0;
1198
1199         free_irq(port->irq, ourport);
1200
1201         wr_regl(port, S3C64XX_UINTP, 0xf);
1202         wr_regl(port, S3C64XX_UINTM, 0xf);
1203
1204         if (ourport->dma)
1205                 s3c24xx_serial_release_dma(ourport);
1206
1207         ourport->tx_in_progress = 0;
1208 }
1209
1210 static void apple_s5l_serial_shutdown(struct uart_port *port)
1211 {
1212         struct s3c24xx_uart_port *ourport = to_ourport(port);
1213
1214         unsigned int ucon;
1215
1216         ucon = rd_regl(port, S3C2410_UCON);
1217         ucon &= ~(APPLE_S5L_UCON_TXTHRESH_ENA_MSK |
1218                   APPLE_S5L_UCON_RXTHRESH_ENA_MSK |
1219                   APPLE_S5L_UCON_RXTO_ENA_MSK);
1220         wr_regl(port, S3C2410_UCON, ucon);
1221
1222         wr_regl(port, S3C2410_UTRSTAT, APPLE_S5L_UTRSTAT_ALL_FLAGS);
1223
1224         free_irq(port->irq, ourport);
1225
1226         ourport->tx_enabled = 0;
1227         ourport->tx_mode = 0;
1228         ourport->rx_enabled = 0;
1229
1230         if (ourport->dma)
1231                 s3c24xx_serial_release_dma(ourport);
1232
1233         ourport->tx_in_progress = 0;
1234 }
1235
1236 static int s3c24xx_serial_startup(struct uart_port *port)
1237 {
1238         struct s3c24xx_uart_port *ourport = to_ourport(port);
1239         int ret;
1240
1241         ourport->rx_enabled = 1;
1242
1243         ret = request_irq(ourport->rx_irq, s3c24xx_serial_rx_irq, 0,
1244                           s3c24xx_serial_portname(port), ourport);
1245
1246         if (ret != 0) {
1247                 dev_err(port->dev, "cannot get irq %d\n", ourport->rx_irq);
1248                 return ret;
1249         }
1250
1251         ourport->rx_claimed = 1;
1252
1253         dev_dbg(port->dev, "requesting tx irq...\n");
1254
1255         ourport->tx_enabled = 1;
1256
1257         ret = request_irq(ourport->tx_irq, s3c24xx_serial_tx_irq, 0,
1258                           s3c24xx_serial_portname(port), ourport);
1259
1260         if (ret) {
1261                 dev_err(port->dev, "cannot get irq %d\n", ourport->tx_irq);
1262                 goto err;
1263         }
1264
1265         ourport->tx_claimed = 1;
1266
1267         /* the port reset code should have done the correct
1268          * register setup for the port controls
1269          */
1270
1271         return ret;
1272
1273 err:
1274         s3c24xx_serial_shutdown(port);
1275         return ret;
1276 }
1277
1278 static int s3c64xx_serial_startup(struct uart_port *port)
1279 {
1280         struct s3c24xx_uart_port *ourport = to_ourport(port);
1281         unsigned long flags;
1282         unsigned int ufcon;
1283         int ret;
1284
1285         wr_regl(port, S3C64XX_UINTM, 0xf);
1286         if (ourport->dma) {
1287                 ret = s3c24xx_serial_request_dma(ourport);
1288                 if (ret < 0) {
1289                         devm_kfree(port->dev, ourport->dma);
1290                         ourport->dma = NULL;
1291                 }
1292         }
1293
1294         ret = request_irq(port->irq, s3c64xx_serial_handle_irq, IRQF_SHARED,
1295                           s3c24xx_serial_portname(port), ourport);
1296         if (ret) {
1297                 dev_err(port->dev, "cannot get irq %d\n", port->irq);
1298                 return ret;
1299         }
1300
1301         /* For compatibility with s3c24xx Soc's */
1302         ourport->rx_enabled = 1;
1303         ourport->tx_enabled = 0;
1304
1305         spin_lock_irqsave(&port->lock, flags);
1306
1307         ufcon = rd_regl(port, S3C2410_UFCON);
1308         ufcon |= S3C2410_UFCON_RESETRX | S5PV210_UFCON_RXTRIG8;
1309         if (!uart_console(port))
1310                 ufcon |= S3C2410_UFCON_RESETTX;
1311         wr_regl(port, S3C2410_UFCON, ufcon);
1312
1313         enable_rx_pio(ourport);
1314
1315         spin_unlock_irqrestore(&port->lock, flags);
1316
1317         /* Enable Rx Interrupt */
1318         s3c24xx_clear_bit(port, S3C64XX_UINTM_RXD, S3C64XX_UINTM);
1319
1320         return ret;
1321 }
1322
1323 static int apple_s5l_serial_startup(struct uart_port *port)
1324 {
1325         struct s3c24xx_uart_port *ourport = to_ourport(port);
1326         unsigned long flags;
1327         unsigned int ufcon;
1328         int ret;
1329
1330         wr_regl(port, S3C2410_UTRSTAT, APPLE_S5L_UTRSTAT_ALL_FLAGS);
1331
1332         ret = request_irq(port->irq, apple_serial_handle_irq, 0,
1333                           s3c24xx_serial_portname(port), ourport);
1334         if (ret) {
1335                 dev_err(port->dev, "cannot get irq %d\n", port->irq);
1336                 return ret;
1337         }
1338
1339         /* For compatibility with s3c24xx Soc's */
1340         ourport->rx_enabled = 1;
1341         ourport->tx_enabled = 0;
1342
1343         spin_lock_irqsave(&port->lock, flags);
1344
1345         ufcon = rd_regl(port, S3C2410_UFCON);
1346         ufcon |= S3C2410_UFCON_RESETRX | S5PV210_UFCON_RXTRIG8;
1347         if (!uart_console(port))
1348                 ufcon |= S3C2410_UFCON_RESETTX;
1349         wr_regl(port, S3C2410_UFCON, ufcon);
1350
1351         enable_rx_pio(ourport);
1352
1353         spin_unlock_irqrestore(&port->lock, flags);
1354
1355         /* Enable Rx Interrupt */
1356         s3c24xx_set_bit(port, APPLE_S5L_UCON_RXTHRESH_ENA, S3C2410_UCON);
1357         s3c24xx_set_bit(port, APPLE_S5L_UCON_RXTO_ENA, S3C2410_UCON);
1358
1359         return ret;
1360 }
1361
1362 /* power power management control */
1363
1364 static void s3c24xx_serial_pm(struct uart_port *port, unsigned int level,
1365                               unsigned int old)
1366 {
1367         struct s3c24xx_uart_port *ourport = to_ourport(port);
1368         int timeout = 10000;
1369
1370         ourport->pm_level = level;
1371
1372         switch (level) {
1373         case 3:
1374                 while (--timeout && !s3c24xx_serial_txempty_nofifo(port))
1375                         udelay(100);
1376
1377                 if (!IS_ERR(ourport->baudclk))
1378                         clk_disable_unprepare(ourport->baudclk);
1379
1380                 clk_disable_unprepare(ourport->clk);
1381                 break;
1382
1383         case 0:
1384                 clk_prepare_enable(ourport->clk);
1385
1386                 if (!IS_ERR(ourport->baudclk))
1387                         clk_prepare_enable(ourport->baudclk);
1388                 break;
1389         default:
1390                 dev_err(port->dev, "s3c24xx_serial: unknown pm %d\n", level);
1391         }
1392 }
1393
1394 /* baud rate calculation
1395  *
1396  * The UARTs on the S3C2410/S3C2440 can take their clocks from a number
1397  * of different sources, including the peripheral clock ("pclk") and an
1398  * external clock ("uclk"). The S3C2440 also adds the core clock ("fclk")
1399  * with a programmable extra divisor.
1400  *
1401  * The following code goes through the clock sources, and calculates the
1402  * baud clocks (and the resultant actual baud rates) and then tries to
1403  * pick the closest one and select that.
1404  *
1405  */
1406
1407 #define MAX_CLK_NAME_LENGTH 15
1408
1409 static inline int s3c24xx_serial_getsource(struct uart_port *port)
1410 {
1411         const struct s3c24xx_uart_info *info = s3c24xx_port_to_info(port);
1412         unsigned int ucon;
1413
1414         if (info->num_clks == 1)
1415                 return 0;
1416
1417         ucon = rd_regl(port, S3C2410_UCON);
1418         ucon &= info->clksel_mask;
1419         return ucon >> info->clksel_shift;
1420 }
1421
1422 static void s3c24xx_serial_setsource(struct uart_port *port,
1423                         unsigned int clk_sel)
1424 {
1425         const struct s3c24xx_uart_info *info = s3c24xx_port_to_info(port);
1426         unsigned int ucon;
1427
1428         if (info->num_clks == 1)
1429                 return;
1430
1431         ucon = rd_regl(port, S3C2410_UCON);
1432         if ((ucon & info->clksel_mask) >> info->clksel_shift == clk_sel)
1433                 return;
1434
1435         ucon &= ~info->clksel_mask;
1436         ucon |= clk_sel << info->clksel_shift;
1437         wr_regl(port, S3C2410_UCON, ucon);
1438 }
1439
1440 static unsigned int s3c24xx_serial_getclk(struct s3c24xx_uart_port *ourport,
1441                         unsigned int req_baud, struct clk **best_clk,
1442                         unsigned int *clk_num)
1443 {
1444         const struct s3c24xx_uart_info *info = ourport->info;
1445         struct clk *clk;
1446         unsigned long rate;
1447         unsigned int cnt, baud, quot, best_quot = 0;
1448         char clkname[MAX_CLK_NAME_LENGTH];
1449         int calc_deviation, deviation = (1 << 30) - 1;
1450
1451         for (cnt = 0; cnt < info->num_clks; cnt++) {
1452                 /* Keep selected clock if provided */
1453                 if (ourport->cfg->clk_sel &&
1454                         !(ourport->cfg->clk_sel & (1 << cnt)))
1455                         continue;
1456
1457                 sprintf(clkname, "clk_uart_baud%d", cnt);
1458                 clk = clk_get(ourport->port.dev, clkname);
1459                 if (IS_ERR(clk))
1460                         continue;
1461
1462                 rate = clk_get_rate(clk);
1463                 if (!rate) {
1464                         dev_err(ourport->port.dev,
1465                                 "Failed to get clock rate for %s.\n", clkname);
1466                         clk_put(clk);
1467                         continue;
1468                 }
1469
1470                 if (ourport->info->has_divslot) {
1471                         unsigned long div = rate / req_baud;
1472
1473                         /* The UDIVSLOT register on the newer UARTs allows us to
1474                          * get a divisor adjustment of 1/16th on the baud clock.
1475                          *
1476                          * We don't keep the UDIVSLOT value (the 16ths we
1477                          * calculated by not multiplying the baud by 16) as it
1478                          * is easy enough to recalculate.
1479                          */
1480
1481                         quot = div / 16;
1482                         baud = rate / div;
1483                 } else {
1484                         quot = (rate + (8 * req_baud)) / (16 * req_baud);
1485                         baud = rate / (quot * 16);
1486                 }
1487                 quot--;
1488
1489                 calc_deviation = abs(req_baud - baud);
1490
1491                 if (calc_deviation < deviation) {
1492                         /*
1493                          * If we find a better clk, release the previous one, if
1494                          * any.
1495                          */
1496                         if (!IS_ERR(*best_clk))
1497                                 clk_put(*best_clk);
1498                         *best_clk = clk;
1499                         best_quot = quot;
1500                         *clk_num = cnt;
1501                         deviation = calc_deviation;
1502                 } else {
1503                         clk_put(clk);
1504                 }
1505         }
1506
1507         return best_quot;
1508 }
1509
1510 /* udivslot_table[]
1511  *
1512  * This table takes the fractional value of the baud divisor and gives
1513  * the recommended setting for the UDIVSLOT register.
1514  */
1515 static const u16 udivslot_table[16] = {
1516         [0] = 0x0000,
1517         [1] = 0x0080,
1518         [2] = 0x0808,
1519         [3] = 0x0888,
1520         [4] = 0x2222,
1521         [5] = 0x4924,
1522         [6] = 0x4A52,
1523         [7] = 0x54AA,
1524         [8] = 0x5555,
1525         [9] = 0xD555,
1526         [10] = 0xD5D5,
1527         [11] = 0xDDD5,
1528         [12] = 0xDDDD,
1529         [13] = 0xDFDD,
1530         [14] = 0xDFDF,
1531         [15] = 0xFFDF,
1532 };
1533
1534 static void s3c24xx_serial_set_termios(struct uart_port *port,
1535                                        struct ktermios *termios,
1536                                        const struct ktermios *old)
1537 {
1538         const struct s3c2410_uartcfg *cfg = s3c24xx_port_to_cfg(port);
1539         struct s3c24xx_uart_port *ourport = to_ourport(port);
1540         struct clk *clk = ERR_PTR(-EINVAL);
1541         unsigned long flags;
1542         unsigned int baud, quot, clk_sel = 0;
1543         unsigned int ulcon;
1544         unsigned int umcon;
1545         unsigned int udivslot = 0;
1546
1547         /*
1548          * We don't support modem control lines.
1549          */
1550         termios->c_cflag &= ~(HUPCL | CMSPAR);
1551         termios->c_cflag |= CLOCAL;
1552
1553         /*
1554          * Ask the core to calculate the divisor for us.
1555          */
1556
1557         baud = uart_get_baud_rate(port, termios, old, 0, 3000000);
1558         quot = s3c24xx_serial_getclk(ourport, baud, &clk, &clk_sel);
1559         if (baud == 38400 && (port->flags & UPF_SPD_MASK) == UPF_SPD_CUST)
1560                 quot = port->custom_divisor;
1561         if (IS_ERR(clk))
1562                 return;
1563
1564         /* check to see if we need  to change clock source */
1565
1566         if (ourport->baudclk != clk) {
1567                 clk_prepare_enable(clk);
1568
1569                 s3c24xx_serial_setsource(port, clk_sel);
1570
1571                 if (!IS_ERR(ourport->baudclk)) {
1572                         clk_disable_unprepare(ourport->baudclk);
1573                         ourport->baudclk = ERR_PTR(-EINVAL);
1574                 }
1575
1576                 ourport->baudclk = clk;
1577                 ourport->baudclk_rate = clk ? clk_get_rate(clk) : 0;
1578         }
1579
1580         if (ourport->info->has_divslot) {
1581                 unsigned int div = ourport->baudclk_rate / baud;
1582
1583                 if (cfg->has_fracval) {
1584                         udivslot = (div & 15);
1585                         dev_dbg(port->dev, "fracval = %04x\n", udivslot);
1586                 } else {
1587                         udivslot = udivslot_table[div & 15];
1588                         dev_dbg(port->dev, "udivslot = %04x (div %d)\n",
1589                                 udivslot, div & 15);
1590                 }
1591         }
1592
1593         switch (termios->c_cflag & CSIZE) {
1594         case CS5:
1595                 dev_dbg(port->dev, "config: 5bits/char\n");
1596                 ulcon = S3C2410_LCON_CS5;
1597                 break;
1598         case CS6:
1599                 dev_dbg(port->dev, "config: 6bits/char\n");
1600                 ulcon = S3C2410_LCON_CS6;
1601                 break;
1602         case CS7:
1603                 dev_dbg(port->dev, "config: 7bits/char\n");
1604                 ulcon = S3C2410_LCON_CS7;
1605                 break;
1606         case CS8:
1607         default:
1608                 dev_dbg(port->dev, "config: 8bits/char\n");
1609                 ulcon = S3C2410_LCON_CS8;
1610                 break;
1611         }
1612
1613         /* preserve original lcon IR settings */
1614         ulcon |= (cfg->ulcon & S3C2410_LCON_IRM);
1615
1616         if (termios->c_cflag & CSTOPB)
1617                 ulcon |= S3C2410_LCON_STOPB;
1618
1619         if (termios->c_cflag & PARENB) {
1620                 if (termios->c_cflag & PARODD)
1621                         ulcon |= S3C2410_LCON_PODD;
1622                 else
1623                         ulcon |= S3C2410_LCON_PEVEN;
1624         } else {
1625                 ulcon |= S3C2410_LCON_PNONE;
1626         }
1627
1628         spin_lock_irqsave(&port->lock, flags);
1629
1630         dev_dbg(port->dev,
1631                 "setting ulcon to %08x, brddiv to %d, udivslot %08x\n",
1632                 ulcon, quot, udivslot);
1633
1634         wr_regl(port, S3C2410_ULCON, ulcon);
1635         wr_regl(port, S3C2410_UBRDIV, quot);
1636
1637         port->status &= ~UPSTAT_AUTOCTS;
1638
1639         umcon = rd_regl(port, S3C2410_UMCON);
1640         if (termios->c_cflag & CRTSCTS) {
1641                 umcon |= S3C2410_UMCOM_AFC;
1642                 /* Disable RTS when RX FIFO contains 63 bytes */
1643                 umcon &= ~S3C2412_UMCON_AFC_8;
1644                 port->status = UPSTAT_AUTOCTS;
1645         } else {
1646                 umcon &= ~S3C2410_UMCOM_AFC;
1647         }
1648         wr_regl(port, S3C2410_UMCON, umcon);
1649
1650         if (ourport->info->has_divslot)
1651                 wr_regl(port, S3C2443_DIVSLOT, udivslot);
1652
1653         dev_dbg(port->dev,
1654                 "uart: ulcon = 0x%08x, ucon = 0x%08x, ufcon = 0x%08x\n",
1655                 rd_regl(port, S3C2410_ULCON),
1656                 rd_regl(port, S3C2410_UCON),
1657                 rd_regl(port, S3C2410_UFCON));
1658
1659         /*
1660          * Update the per-port timeout.
1661          */
1662         uart_update_timeout(port, termios->c_cflag, baud);
1663
1664         /*
1665          * Which character status flags are we interested in?
1666          */
1667         port->read_status_mask = S3C2410_UERSTAT_OVERRUN;
1668         if (termios->c_iflag & INPCK)
1669                 port->read_status_mask |= S3C2410_UERSTAT_FRAME |
1670                         S3C2410_UERSTAT_PARITY;
1671         /*
1672          * Which character status flags should we ignore?
1673          */
1674         port->ignore_status_mask = 0;
1675         if (termios->c_iflag & IGNPAR)
1676                 port->ignore_status_mask |= S3C2410_UERSTAT_OVERRUN;
1677         if (termios->c_iflag & IGNBRK && termios->c_iflag & IGNPAR)
1678                 port->ignore_status_mask |= S3C2410_UERSTAT_FRAME;
1679
1680         /*
1681          * Ignore all characters if CREAD is not set.
1682          */
1683         if ((termios->c_cflag & CREAD) == 0)
1684                 port->ignore_status_mask |= RXSTAT_DUMMY_READ;
1685
1686         spin_unlock_irqrestore(&port->lock, flags);
1687 }
1688
1689 static const char *s3c24xx_serial_type(struct uart_port *port)
1690 {
1691         const struct s3c24xx_uart_port *ourport = to_ourport(port);
1692
1693         switch (ourport->info->type) {
1694         case TYPE_S3C24XX:
1695                 return "S3C24XX";
1696         case TYPE_S3C6400:
1697                 return "S3C6400/10";
1698         case TYPE_APPLE_S5L:
1699                 return "APPLE S5L";
1700         default:
1701                 return NULL;
1702         }
1703 }
1704
1705 static void s3c24xx_serial_config_port(struct uart_port *port, int flags)
1706 {
1707         const struct s3c24xx_uart_info *info = s3c24xx_port_to_info(port);
1708
1709         if (flags & UART_CONFIG_TYPE)
1710                 port->type = info->port_type;
1711 }
1712
1713 /*
1714  * verify the new serial_struct (for TIOCSSERIAL).
1715  */
1716 static int
1717 s3c24xx_serial_verify_port(struct uart_port *port, struct serial_struct *ser)
1718 {
1719         const struct s3c24xx_uart_info *info = s3c24xx_port_to_info(port);
1720
1721         if (ser->type != PORT_UNKNOWN && ser->type != info->port_type)
1722                 return -EINVAL;
1723
1724         return 0;
1725 }
1726
1727 #ifdef CONFIG_SERIAL_SAMSUNG_CONSOLE
1728
1729 static struct console s3c24xx_serial_console;
1730
1731 static void __init s3c24xx_serial_register_console(void)
1732 {
1733         register_console(&s3c24xx_serial_console);
1734 }
1735
1736 static void s3c24xx_serial_unregister_console(void)
1737 {
1738         if (console_is_registered(&s3c24xx_serial_console))
1739                 unregister_console(&s3c24xx_serial_console);
1740 }
1741
1742 #define S3C24XX_SERIAL_CONSOLE &s3c24xx_serial_console
1743 #else
1744 static inline void s3c24xx_serial_register_console(void) { }
1745 static inline void s3c24xx_serial_unregister_console(void) { }
1746 #define S3C24XX_SERIAL_CONSOLE NULL
1747 #endif
1748
1749 #if defined(CONFIG_SERIAL_SAMSUNG_CONSOLE) && defined(CONFIG_CONSOLE_POLL)
1750 static int s3c24xx_serial_get_poll_char(struct uart_port *port);
1751 static void s3c24xx_serial_put_poll_char(struct uart_port *port,
1752                          unsigned char c);
1753 #endif
1754
1755 static const struct uart_ops s3c24xx_serial_ops = {
1756         .pm             = s3c24xx_serial_pm,
1757         .tx_empty       = s3c24xx_serial_tx_empty,
1758         .get_mctrl      = s3c24xx_serial_get_mctrl,
1759         .set_mctrl      = s3c24xx_serial_set_mctrl,
1760         .stop_tx        = s3c24xx_serial_stop_tx,
1761         .start_tx       = s3c24xx_serial_start_tx,
1762         .stop_rx        = s3c24xx_serial_stop_rx,
1763         .break_ctl      = s3c24xx_serial_break_ctl,
1764         .startup        = s3c24xx_serial_startup,
1765         .shutdown       = s3c24xx_serial_shutdown,
1766         .set_termios    = s3c24xx_serial_set_termios,
1767         .type           = s3c24xx_serial_type,
1768         .config_port    = s3c24xx_serial_config_port,
1769         .verify_port    = s3c24xx_serial_verify_port,
1770 #if defined(CONFIG_SERIAL_SAMSUNG_CONSOLE) && defined(CONFIG_CONSOLE_POLL)
1771         .poll_get_char = s3c24xx_serial_get_poll_char,
1772         .poll_put_char = s3c24xx_serial_put_poll_char,
1773 #endif
1774 };
1775
1776 static const struct uart_ops s3c64xx_serial_ops = {
1777         .pm             = s3c24xx_serial_pm,
1778         .tx_empty       = s3c24xx_serial_tx_empty,
1779         .get_mctrl      = s3c24xx_serial_get_mctrl,
1780         .set_mctrl      = s3c24xx_serial_set_mctrl,
1781         .stop_tx        = s3c24xx_serial_stop_tx,
1782         .start_tx       = s3c24xx_serial_start_tx,
1783         .stop_rx        = s3c24xx_serial_stop_rx,
1784         .break_ctl      = s3c24xx_serial_break_ctl,
1785         .startup        = s3c64xx_serial_startup,
1786         .shutdown       = s3c64xx_serial_shutdown,
1787         .set_termios    = s3c24xx_serial_set_termios,
1788         .type           = s3c24xx_serial_type,
1789         .config_port    = s3c24xx_serial_config_port,
1790         .verify_port    = s3c24xx_serial_verify_port,
1791 #if defined(CONFIG_SERIAL_SAMSUNG_CONSOLE) && defined(CONFIG_CONSOLE_POLL)
1792         .poll_get_char = s3c24xx_serial_get_poll_char,
1793         .poll_put_char = s3c24xx_serial_put_poll_char,
1794 #endif
1795 };
1796
1797 static const struct uart_ops apple_s5l_serial_ops = {
1798         .pm             = s3c24xx_serial_pm,
1799         .tx_empty       = s3c24xx_serial_tx_empty,
1800         .get_mctrl      = s3c24xx_serial_get_mctrl,
1801         .set_mctrl      = s3c24xx_serial_set_mctrl,
1802         .stop_tx        = s3c24xx_serial_stop_tx,
1803         .start_tx       = s3c24xx_serial_start_tx,
1804         .stop_rx        = s3c24xx_serial_stop_rx,
1805         .break_ctl      = s3c24xx_serial_break_ctl,
1806         .startup        = apple_s5l_serial_startup,
1807         .shutdown       = apple_s5l_serial_shutdown,
1808         .set_termios    = s3c24xx_serial_set_termios,
1809         .type           = s3c24xx_serial_type,
1810         .config_port    = s3c24xx_serial_config_port,
1811         .verify_port    = s3c24xx_serial_verify_port,
1812 #if defined(CONFIG_SERIAL_SAMSUNG_CONSOLE) && defined(CONFIG_CONSOLE_POLL)
1813         .poll_get_char = s3c24xx_serial_get_poll_char,
1814         .poll_put_char = s3c24xx_serial_put_poll_char,
1815 #endif
1816 };
1817
1818 static struct uart_driver s3c24xx_uart_drv = {
1819         .owner          = THIS_MODULE,
1820         .driver_name    = "s3c2410_serial",
1821         .nr             = UART_NR,
1822         .cons           = S3C24XX_SERIAL_CONSOLE,
1823         .dev_name       = S3C24XX_SERIAL_NAME,
1824         .major          = S3C24XX_SERIAL_MAJOR,
1825         .minor          = S3C24XX_SERIAL_MINOR,
1826 };
1827
1828 static struct s3c24xx_uart_port s3c24xx_serial_ports[UART_NR];
1829
1830 static void s3c24xx_serial_init_port_default(int index) {
1831         struct uart_port *port = &s3c24xx_serial_ports[index].port;
1832
1833         spin_lock_init(&port->lock);
1834
1835         port->iotype = UPIO_MEM;
1836         port->uartclk = 0;
1837         port->fifosize = 16;
1838         port->ops = &s3c24xx_serial_ops;
1839         port->flags = UPF_BOOT_AUTOCONF;
1840         port->line = index;
1841 }
1842
1843 /* s3c24xx_serial_resetport
1844  *
1845  * reset the fifos and other the settings.
1846  */
1847
1848 static void s3c24xx_serial_resetport(struct uart_port *port,
1849                                      const struct s3c2410_uartcfg *cfg)
1850 {
1851         const struct s3c24xx_uart_info *info = s3c24xx_port_to_info(port);
1852         unsigned long ucon = rd_regl(port, S3C2410_UCON);
1853
1854         ucon &= (info->clksel_mask | info->ucon_mask);
1855         wr_regl(port, S3C2410_UCON, ucon | cfg->ucon);
1856
1857         /* reset both fifos */
1858         wr_regl(port, S3C2410_UFCON, cfg->ufcon | S3C2410_UFCON_RESETBOTH);
1859         wr_regl(port, S3C2410_UFCON, cfg->ufcon);
1860
1861         /* some delay is required after fifo reset */
1862         udelay(1);
1863 }
1864
1865 static int s3c24xx_serial_enable_baudclk(struct s3c24xx_uart_port *ourport)
1866 {
1867         struct device *dev = ourport->port.dev;
1868         const struct s3c24xx_uart_info *info = ourport->info;
1869         char clk_name[MAX_CLK_NAME_LENGTH];
1870         unsigned int clk_sel;
1871         struct clk *clk;
1872         int clk_num;
1873         int ret;
1874
1875         clk_sel = ourport->cfg->clk_sel ? : info->def_clk_sel;
1876         for (clk_num = 0; clk_num < info->num_clks; clk_num++) {
1877                 if (!(clk_sel & (1 << clk_num)))
1878                         continue;
1879
1880                 sprintf(clk_name, "clk_uart_baud%d", clk_num);
1881                 clk = clk_get(dev, clk_name);
1882                 if (IS_ERR(clk))
1883                         continue;
1884
1885                 ret = clk_prepare_enable(clk);
1886                 if (ret) {
1887                         clk_put(clk);
1888                         continue;
1889                 }
1890
1891                 ourport->baudclk = clk;
1892                 ourport->baudclk_rate = clk_get_rate(clk);
1893                 s3c24xx_serial_setsource(&ourport->port, clk_num);
1894
1895                 return 0;
1896         }
1897
1898         return -EINVAL;
1899 }
1900
1901 /* s3c24xx_serial_init_port
1902  *
1903  * initialise a single serial port from the platform device given
1904  */
1905
1906 static int s3c24xx_serial_init_port(struct s3c24xx_uart_port *ourport,
1907                                     struct platform_device *platdev)
1908 {
1909         struct uart_port *port = &ourport->port;
1910         const struct s3c2410_uartcfg *cfg = ourport->cfg;
1911         struct resource *res;
1912         int ret;
1913
1914         if (platdev == NULL)
1915                 return -ENODEV;
1916
1917         if (port->mapbase != 0)
1918                 return -EINVAL;
1919
1920         /* setup info for port */
1921         port->dev       = &platdev->dev;
1922
1923         port->uartclk = 1;
1924
1925         if (cfg->uart_flags & UPF_CONS_FLOW) {
1926                 dev_dbg(port->dev, "enabling flow control\n");
1927                 port->flags |= UPF_CONS_FLOW;
1928         }
1929
1930         /* sort our the physical and virtual addresses for each UART */
1931
1932         res = platform_get_resource(platdev, IORESOURCE_MEM, 0);
1933         if (res == NULL) {
1934                 dev_err(port->dev, "failed to find memory resource for uart\n");
1935                 return -EINVAL;
1936         }
1937
1938         dev_dbg(port->dev, "resource %pR)\n", res);
1939
1940         port->membase = devm_ioremap_resource(port->dev, res);
1941         if (IS_ERR(port->membase)) {
1942                 dev_err(port->dev, "failed to remap controller address\n");
1943                 return -EBUSY;
1944         }
1945
1946         port->mapbase = res->start;
1947         ret = platform_get_irq(platdev, 0);
1948         if (ret < 0) {
1949                 port->irq = 0;
1950         } else {
1951                 port->irq = ret;
1952                 ourport->rx_irq = ret;
1953                 ourport->tx_irq = ret + 1;
1954         }
1955
1956         switch (ourport->info->type) {
1957         case TYPE_S3C24XX:
1958                 ret = platform_get_irq(platdev, 1);
1959                 if (ret > 0)
1960                         ourport->tx_irq = ret;
1961                 break;
1962         default:
1963                 break;
1964         }
1965
1966         /*
1967          * DMA is currently supported only on DT platforms, if DMA properties
1968          * are specified.
1969          */
1970         if (platdev->dev.of_node && of_find_property(platdev->dev.of_node,
1971                                                      "dmas", NULL)) {
1972                 ourport->dma = devm_kzalloc(port->dev,
1973                                             sizeof(*ourport->dma),
1974                                             GFP_KERNEL);
1975                 if (!ourport->dma) {
1976                         ret = -ENOMEM;
1977                         goto err;
1978                 }
1979         }
1980
1981         ourport->clk    = clk_get(&platdev->dev, "uart");
1982         if (IS_ERR(ourport->clk)) {
1983                 pr_err("%s: Controller clock not found\n",
1984                                 dev_name(&platdev->dev));
1985                 ret = PTR_ERR(ourport->clk);
1986                 goto err;
1987         }
1988
1989         ret = clk_prepare_enable(ourport->clk);
1990         if (ret) {
1991                 pr_err("uart: clock failed to prepare+enable: %d\n", ret);
1992                 clk_put(ourport->clk);
1993                 goto err;
1994         }
1995
1996         ret = s3c24xx_serial_enable_baudclk(ourport);
1997         if (ret)
1998                 pr_warn("uart: failed to enable baudclk\n");
1999
2000         /* Keep all interrupts masked and cleared */
2001         switch (ourport->info->type) {
2002         case TYPE_S3C6400:
2003                 wr_regl(port, S3C64XX_UINTM, 0xf);
2004                 wr_regl(port, S3C64XX_UINTP, 0xf);
2005                 wr_regl(port, S3C64XX_UINTSP, 0xf);
2006                 break;
2007         case TYPE_APPLE_S5L: {
2008                 unsigned int ucon;
2009
2010                 ucon = rd_regl(port, S3C2410_UCON);
2011                 ucon &= ~(APPLE_S5L_UCON_TXTHRESH_ENA_MSK |
2012                         APPLE_S5L_UCON_RXTHRESH_ENA_MSK |
2013                         APPLE_S5L_UCON_RXTO_ENA_MSK);
2014                 wr_regl(port, S3C2410_UCON, ucon);
2015
2016                 wr_regl(port, S3C2410_UTRSTAT, APPLE_S5L_UTRSTAT_ALL_FLAGS);
2017                 break;
2018         }
2019         default:
2020                 break;
2021         }
2022
2023         dev_dbg(port->dev, "port: map=%pa, mem=%p, irq=%d (%d,%d), clock=%u\n",
2024                 &port->mapbase, port->membase, port->irq,
2025                 ourport->rx_irq, ourport->tx_irq, port->uartclk);
2026
2027         /* reset the fifos (and setup the uart) */
2028         s3c24xx_serial_resetport(port, cfg);
2029
2030         return 0;
2031
2032 err:
2033         port->mapbase = 0;
2034         return ret;
2035 }
2036
2037 /* Device driver serial port probe */
2038
2039 static int probe_index;
2040
2041 static inline const struct s3c24xx_serial_drv_data *
2042 s3c24xx_get_driver_data(struct platform_device *pdev)
2043 {
2044         if (dev_of_node(&pdev->dev))
2045                 return of_device_get_match_data(&pdev->dev);
2046
2047         return (struct s3c24xx_serial_drv_data *)
2048                         platform_get_device_id(pdev)->driver_data;
2049 }
2050
2051 static int s3c24xx_serial_probe(struct platform_device *pdev)
2052 {
2053         struct device_node *np = pdev->dev.of_node;
2054         struct s3c24xx_uart_port *ourport;
2055         int index = probe_index;
2056         int ret, prop = 0;
2057
2058         if (np) {
2059                 ret = of_alias_get_id(np, "serial");
2060                 if (ret >= 0)
2061                         index = ret;
2062         }
2063
2064         if (index >= ARRAY_SIZE(s3c24xx_serial_ports)) {
2065                 dev_err(&pdev->dev, "serial%d out of range\n", index);
2066                 return -EINVAL;
2067         }
2068         ourport = &s3c24xx_serial_ports[index];
2069
2070         s3c24xx_serial_init_port_default(index);
2071
2072         ourport->drv_data = s3c24xx_get_driver_data(pdev);
2073         if (!ourport->drv_data) {
2074                 dev_err(&pdev->dev, "could not find driver data\n");
2075                 return -ENODEV;
2076         }
2077
2078         ourport->baudclk = ERR_PTR(-EINVAL);
2079         ourport->info = &ourport->drv_data->info;
2080         ourport->cfg = (dev_get_platdata(&pdev->dev)) ?
2081                         dev_get_platdata(&pdev->dev) :
2082                         &ourport->drv_data->def_cfg;
2083
2084         switch (ourport->info->type) {
2085         case TYPE_S3C24XX:
2086                 ourport->port.ops = &s3c24xx_serial_ops;
2087                 break;
2088         case TYPE_S3C6400:
2089                 ourport->port.ops = &s3c64xx_serial_ops;
2090                 break;
2091         case TYPE_APPLE_S5L:
2092                 ourport->port.ops = &apple_s5l_serial_ops;
2093                 break;
2094         }
2095
2096         if (np) {
2097                 of_property_read_u32(np,
2098                         "samsung,uart-fifosize", &ourport->port.fifosize);
2099
2100                 if (of_property_read_u32(np, "reg-io-width", &prop) == 0) {
2101                         switch (prop) {
2102                         case 1:
2103                                 ourport->port.iotype = UPIO_MEM;
2104                                 break;
2105                         case 4:
2106                                 ourport->port.iotype = UPIO_MEM32;
2107                                 break;
2108                         default:
2109                                 dev_warn(&pdev->dev, "unsupported reg-io-width (%d)\n",
2110                                                 prop);
2111                                 return -EINVAL;
2112                         }
2113                 }
2114         }
2115
2116         if (ourport->drv_data->fifosize[index])
2117                 ourport->port.fifosize = ourport->drv_data->fifosize[index];
2118         else if (ourport->info->fifosize)
2119                 ourport->port.fifosize = ourport->info->fifosize;
2120         ourport->port.has_sysrq = IS_ENABLED(CONFIG_SERIAL_SAMSUNG_CONSOLE);
2121
2122         /*
2123          * DMA transfers must be aligned at least to cache line size,
2124          * so find minimal transfer size suitable for DMA mode
2125          */
2126         ourport->min_dma_size = max_t(int, ourport->port.fifosize,
2127                                     dma_get_cache_alignment());
2128
2129         dev_dbg(&pdev->dev, "%s: initialising port %p...\n", __func__, ourport);
2130
2131         ret = s3c24xx_serial_init_port(ourport, pdev);
2132         if (ret < 0)
2133                 return ret;
2134
2135         if (!s3c24xx_uart_drv.state) {
2136                 ret = uart_register_driver(&s3c24xx_uart_drv);
2137                 if (ret < 0) {
2138                         pr_err("Failed to register Samsung UART driver\n");
2139                         return ret;
2140                 }
2141         }
2142
2143         dev_dbg(&pdev->dev, "%s: adding port\n", __func__);
2144         uart_add_one_port(&s3c24xx_uart_drv, &ourport->port);
2145         platform_set_drvdata(pdev, &ourport->port);
2146
2147         /*
2148          * Deactivate the clock enabled in s3c24xx_serial_init_port here,
2149          * so that a potential re-enablement through the pm-callback overlaps
2150          * and keeps the clock enabled in this case.
2151          */
2152         clk_disable_unprepare(ourport->clk);
2153         if (!IS_ERR(ourport->baudclk))
2154                 clk_disable_unprepare(ourport->baudclk);
2155
2156         probe_index++;
2157
2158         return 0;
2159 }
2160
2161 static int s3c24xx_serial_remove(struct platform_device *dev)
2162 {
2163         struct uart_port *port = s3c24xx_dev_to_port(&dev->dev);
2164
2165         if (port) {
2166                 uart_remove_one_port(&s3c24xx_uart_drv, port);
2167         }
2168
2169         uart_unregister_driver(&s3c24xx_uart_drv);
2170
2171         return 0;
2172 }
2173
2174 /* UART power management code */
2175 #ifdef CONFIG_PM_SLEEP
2176 static int s3c24xx_serial_suspend(struct device *dev)
2177 {
2178         struct uart_port *port = s3c24xx_dev_to_port(dev);
2179
2180         if (port)
2181                 uart_suspend_port(&s3c24xx_uart_drv, port);
2182
2183         return 0;
2184 }
2185
2186 static int s3c24xx_serial_resume(struct device *dev)
2187 {
2188         struct uart_port *port = s3c24xx_dev_to_port(dev);
2189         struct s3c24xx_uart_port *ourport = to_ourport(port);
2190
2191         if (port) {
2192                 clk_prepare_enable(ourport->clk);
2193                 if (!IS_ERR(ourport->baudclk))
2194                         clk_prepare_enable(ourport->baudclk);
2195                 s3c24xx_serial_resetport(port, s3c24xx_port_to_cfg(port));
2196                 if (!IS_ERR(ourport->baudclk))
2197                         clk_disable_unprepare(ourport->baudclk);
2198                 clk_disable_unprepare(ourport->clk);
2199
2200                 uart_resume_port(&s3c24xx_uart_drv, port);
2201         }
2202
2203         return 0;
2204 }
2205
2206 static int s3c24xx_serial_resume_noirq(struct device *dev)
2207 {
2208         struct uart_port *port = s3c24xx_dev_to_port(dev);
2209         struct s3c24xx_uart_port *ourport = to_ourport(port);
2210
2211         if (port) {
2212                 /* restore IRQ mask */
2213                 switch (ourport->info->type) {
2214                 case TYPE_S3C6400: {
2215                         unsigned int uintm = 0xf;
2216
2217                         if (ourport->tx_enabled)
2218                                 uintm &= ~S3C64XX_UINTM_TXD_MSK;
2219                         if (ourport->rx_enabled)
2220                                 uintm &= ~S3C64XX_UINTM_RXD_MSK;
2221                         clk_prepare_enable(ourport->clk);
2222                         if (!IS_ERR(ourport->baudclk))
2223                                 clk_prepare_enable(ourport->baudclk);
2224                         wr_regl(port, S3C64XX_UINTM, uintm);
2225                         if (!IS_ERR(ourport->baudclk))
2226                                 clk_disable_unprepare(ourport->baudclk);
2227                         clk_disable_unprepare(ourport->clk);
2228                         break;
2229                 }
2230                 case TYPE_APPLE_S5L: {
2231                         unsigned int ucon;
2232                         int ret;
2233
2234                         ret = clk_prepare_enable(ourport->clk);
2235                         if (ret) {
2236                                 dev_err(dev, "clk_enable clk failed: %d\n", ret);
2237                                 return ret;
2238                         }
2239                         if (!IS_ERR(ourport->baudclk)) {
2240                                 ret = clk_prepare_enable(ourport->baudclk);
2241                                 if (ret) {
2242                                         dev_err(dev, "clk_enable baudclk failed: %d\n", ret);
2243                                         clk_disable_unprepare(ourport->clk);
2244                                         return ret;
2245                                 }
2246                         }
2247
2248                         ucon = rd_regl(port, S3C2410_UCON);
2249
2250                         ucon &= ~(APPLE_S5L_UCON_TXTHRESH_ENA_MSK |
2251                                   APPLE_S5L_UCON_RXTHRESH_ENA_MSK |
2252                                   APPLE_S5L_UCON_RXTO_ENA_MSK);
2253
2254                         if (ourport->tx_enabled)
2255                                 ucon |= APPLE_S5L_UCON_TXTHRESH_ENA_MSK;
2256                         if (ourport->rx_enabled)
2257                                 ucon |= APPLE_S5L_UCON_RXTHRESH_ENA_MSK |
2258                                         APPLE_S5L_UCON_RXTO_ENA_MSK;
2259
2260                         wr_regl(port, S3C2410_UCON, ucon);
2261
2262                         if (!IS_ERR(ourport->baudclk))
2263                                 clk_disable_unprepare(ourport->baudclk);
2264                         clk_disable_unprepare(ourport->clk);
2265                         break;
2266                 }
2267                 default:
2268                         break;
2269                 }
2270         }
2271
2272         return 0;
2273 }
2274
2275 static const struct dev_pm_ops s3c24xx_serial_pm_ops = {
2276         .suspend = s3c24xx_serial_suspend,
2277         .resume = s3c24xx_serial_resume,
2278         .resume_noirq = s3c24xx_serial_resume_noirq,
2279 };
2280 #define SERIAL_SAMSUNG_PM_OPS   (&s3c24xx_serial_pm_ops)
2281
2282 #else /* !CONFIG_PM_SLEEP */
2283
2284 #define SERIAL_SAMSUNG_PM_OPS   NULL
2285 #endif /* CONFIG_PM_SLEEP */
2286
2287 /* Console code */
2288
2289 #ifdef CONFIG_SERIAL_SAMSUNG_CONSOLE
2290
2291 static struct uart_port *cons_uart;
2292
2293 static int
2294 s3c24xx_serial_console_txrdy(struct uart_port *port, unsigned int ufcon)
2295 {
2296         const struct s3c24xx_uart_info *info = s3c24xx_port_to_info(port);
2297         unsigned long ufstat, utrstat;
2298
2299         if (ufcon & S3C2410_UFCON_FIFOMODE) {
2300                 /* fifo mode - check amount of data in fifo registers... */
2301
2302                 ufstat = rd_regl(port, S3C2410_UFSTAT);
2303                 return (ufstat & info->tx_fifofull) ? 0 : 1;
2304         }
2305
2306         /* in non-fifo mode, we go and use the tx buffer empty */
2307
2308         utrstat = rd_regl(port, S3C2410_UTRSTAT);
2309         return (utrstat & S3C2410_UTRSTAT_TXE) ? 1 : 0;
2310 }
2311
2312 static bool
2313 s3c24xx_port_configured(unsigned int ucon)
2314 {
2315         /* consider the serial port configured if the tx/rx mode set */
2316         return (ucon & 0xf) != 0;
2317 }
2318
2319 #ifdef CONFIG_CONSOLE_POLL
2320 /*
2321  * Console polling routines for writing and reading from the uart while
2322  * in an interrupt or debug context.
2323  */
2324
2325 static int s3c24xx_serial_get_poll_char(struct uart_port *port)
2326 {
2327         const struct s3c24xx_uart_port *ourport = to_ourport(port);
2328         unsigned int ufstat;
2329
2330         ufstat = rd_regl(port, S3C2410_UFSTAT);
2331         if (s3c24xx_serial_rx_fifocnt(ourport, ufstat) == 0)
2332                 return NO_POLL_CHAR;
2333
2334         return rd_reg(port, S3C2410_URXH);
2335 }
2336
2337 static void s3c24xx_serial_put_poll_char(struct uart_port *port,
2338                 unsigned char c)
2339 {
2340         unsigned int ufcon = rd_regl(port, S3C2410_UFCON);
2341         unsigned int ucon = rd_regl(port, S3C2410_UCON);
2342
2343         /* not possible to xmit on unconfigured port */
2344         if (!s3c24xx_port_configured(ucon))
2345                 return;
2346
2347         while (!s3c24xx_serial_console_txrdy(port, ufcon))
2348                 cpu_relax();
2349         wr_reg(port, S3C2410_UTXH, c);
2350 }
2351
2352 #endif /* CONFIG_CONSOLE_POLL */
2353
2354 static void
2355 s3c24xx_serial_console_putchar(struct uart_port *port, unsigned char ch)
2356 {
2357         unsigned int ufcon = rd_regl(port, S3C2410_UFCON);
2358
2359         while (!s3c24xx_serial_console_txrdy(port, ufcon))
2360                 cpu_relax();
2361         wr_reg(port, S3C2410_UTXH, ch);
2362 }
2363
2364 static void
2365 s3c24xx_serial_console_write(struct console *co, const char *s,
2366                              unsigned int count)
2367 {
2368         unsigned int ucon = rd_regl(cons_uart, S3C2410_UCON);
2369         unsigned long flags;
2370         bool locked = true;
2371
2372         /* not possible to xmit on unconfigured port */
2373         if (!s3c24xx_port_configured(ucon))
2374                 return;
2375
2376         if (cons_uart->sysrq)
2377                 locked = false;
2378         else if (oops_in_progress)
2379                 locked = spin_trylock_irqsave(&cons_uart->lock, flags);
2380         else
2381                 spin_lock_irqsave(&cons_uart->lock, flags);
2382
2383         uart_console_write(cons_uart, s, count, s3c24xx_serial_console_putchar);
2384
2385         if (locked)
2386                 spin_unlock_irqrestore(&cons_uart->lock, flags);
2387 }
2388
2389 /* Shouldn't be __init, as it can be instantiated from other module */
2390 static void
2391 s3c24xx_serial_get_options(struct uart_port *port, int *baud,
2392                            int *parity, int *bits)
2393 {
2394         struct clk *clk;
2395         unsigned int ulcon;
2396         unsigned int ucon;
2397         unsigned int ubrdiv;
2398         unsigned long rate;
2399         unsigned int clk_sel;
2400         char clk_name[MAX_CLK_NAME_LENGTH];
2401
2402         ulcon  = rd_regl(port, S3C2410_ULCON);
2403         ucon   = rd_regl(port, S3C2410_UCON);
2404         ubrdiv = rd_regl(port, S3C2410_UBRDIV);
2405
2406         if (s3c24xx_port_configured(ucon)) {
2407                 switch (ulcon & S3C2410_LCON_CSMASK) {
2408                 case S3C2410_LCON_CS5:
2409                         *bits = 5;
2410                         break;
2411                 case S3C2410_LCON_CS6:
2412                         *bits = 6;
2413                         break;
2414                 case S3C2410_LCON_CS7:
2415                         *bits = 7;
2416                         break;
2417                 case S3C2410_LCON_CS8:
2418                 default:
2419                         *bits = 8;
2420                         break;
2421                 }
2422
2423                 switch (ulcon & S3C2410_LCON_PMASK) {
2424                 case S3C2410_LCON_PEVEN:
2425                         *parity = 'e';
2426                         break;
2427
2428                 case S3C2410_LCON_PODD:
2429                         *parity = 'o';
2430                         break;
2431
2432                 case S3C2410_LCON_PNONE:
2433                 default:
2434                         *parity = 'n';
2435                 }
2436
2437                 /* now calculate the baud rate */
2438
2439                 clk_sel = s3c24xx_serial_getsource(port);
2440                 sprintf(clk_name, "clk_uart_baud%d", clk_sel);
2441
2442                 clk = clk_get(port->dev, clk_name);
2443                 if (!IS_ERR(clk))
2444                         rate = clk_get_rate(clk);
2445                 else
2446                         rate = 1;
2447
2448                 *baud = rate / (16 * (ubrdiv + 1));
2449                 dev_dbg(port->dev, "calculated baud %d\n", *baud);
2450         }
2451 }
2452
2453 /* Shouldn't be __init, as it can be instantiated from other module */
2454 static int
2455 s3c24xx_serial_console_setup(struct console *co, char *options)
2456 {
2457         struct uart_port *port;
2458         int baud = 9600;
2459         int bits = 8;
2460         int parity = 'n';
2461         int flow = 'n';
2462
2463         /* is this a valid port */
2464
2465         if (co->index == -1 || co->index >= UART_NR)
2466                 co->index = 0;
2467
2468         port = &s3c24xx_serial_ports[co->index].port;
2469
2470         /* is the port configured? */
2471
2472         if (port->mapbase == 0x0)
2473                 return -ENODEV;
2474
2475         cons_uart = port;
2476
2477         /*
2478          * Check whether an invalid uart number has been specified, and
2479          * if so, search for the first available port that does have
2480          * console support.
2481          */
2482         if (options)
2483                 uart_parse_options(options, &baud, &parity, &bits, &flow);
2484         else
2485                 s3c24xx_serial_get_options(port, &baud, &parity, &bits);
2486
2487         dev_dbg(port->dev, "baud %d\n", baud);
2488
2489         return uart_set_options(port, co, baud, parity, bits, flow);
2490 }
2491
2492 static struct console s3c24xx_serial_console = {
2493         .name           = S3C24XX_SERIAL_NAME,
2494         .device         = uart_console_device,
2495         .flags          = CON_PRINTBUFFER,
2496         .index          = -1,
2497         .write          = s3c24xx_serial_console_write,
2498         .setup          = s3c24xx_serial_console_setup,
2499         .data           = &s3c24xx_uart_drv,
2500 };
2501 #endif /* CONFIG_SERIAL_SAMSUNG_CONSOLE */
2502
2503 #if defined(CONFIG_CPU_S3C6400) || defined(CONFIG_CPU_S3C6410)
2504 static const struct s3c24xx_serial_drv_data s3c6400_serial_drv_data = {
2505         .info = {
2506                 .name           = "Samsung S3C6400 UART",
2507                 .type           = TYPE_S3C6400,
2508                 .port_type      = PORT_S3C6400,
2509                 .fifosize       = 64,
2510                 .has_divslot    = 1,
2511                 .rx_fifomask    = S3C2440_UFSTAT_RXMASK,
2512                 .rx_fifoshift   = S3C2440_UFSTAT_RXSHIFT,
2513                 .rx_fifofull    = S3C2440_UFSTAT_RXFULL,
2514                 .tx_fifofull    = S3C2440_UFSTAT_TXFULL,
2515                 .tx_fifomask    = S3C2440_UFSTAT_TXMASK,
2516                 .tx_fifoshift   = S3C2440_UFSTAT_TXSHIFT,
2517                 .def_clk_sel    = S3C2410_UCON_CLKSEL2,
2518                 .num_clks       = 4,
2519                 .clksel_mask    = S3C6400_UCON_CLKMASK,
2520                 .clksel_shift   = S3C6400_UCON_CLKSHIFT,
2521         },
2522         .def_cfg = {
2523                 .ucon           = S3C2410_UCON_DEFAULT,
2524                 .ufcon          = S3C2410_UFCON_DEFAULT,
2525         },
2526 };
2527 #define S3C6400_SERIAL_DRV_DATA (&s3c6400_serial_drv_data)
2528 #else
2529 #define S3C6400_SERIAL_DRV_DATA NULL
2530 #endif
2531
2532 #ifdef CONFIG_CPU_S5PV210
2533 static const struct s3c24xx_serial_drv_data s5pv210_serial_drv_data = {
2534         .info = {
2535                 .name           = "Samsung S5PV210 UART",
2536                 .type           = TYPE_S3C6400,
2537                 .port_type      = PORT_S3C6400,
2538                 .has_divslot    = 1,
2539                 .rx_fifomask    = S5PV210_UFSTAT_RXMASK,
2540                 .rx_fifoshift   = S5PV210_UFSTAT_RXSHIFT,
2541                 .rx_fifofull    = S5PV210_UFSTAT_RXFULL,
2542                 .tx_fifofull    = S5PV210_UFSTAT_TXFULL,
2543                 .tx_fifomask    = S5PV210_UFSTAT_TXMASK,
2544                 .tx_fifoshift   = S5PV210_UFSTAT_TXSHIFT,
2545                 .def_clk_sel    = S3C2410_UCON_CLKSEL0,
2546                 .num_clks       = 2,
2547                 .clksel_mask    = S5PV210_UCON_CLKMASK,
2548                 .clksel_shift   = S5PV210_UCON_CLKSHIFT,
2549         },
2550         .def_cfg = {
2551                 .ucon           = S5PV210_UCON_DEFAULT,
2552                 .ufcon          = S5PV210_UFCON_DEFAULT,
2553         },
2554         .fifosize = { 256, 64, 16, 16 },
2555 };
2556 #define S5PV210_SERIAL_DRV_DATA (&s5pv210_serial_drv_data)
2557 #else
2558 #define S5PV210_SERIAL_DRV_DATA NULL
2559 #endif
2560
2561 #if defined(CONFIG_ARCH_EXYNOS)
2562 #define EXYNOS_COMMON_SERIAL_DRV_DATA()                         \
2563         .info = {                                               \
2564                 .name           = "Samsung Exynos UART",        \
2565                 .type           = TYPE_S3C6400,                 \
2566                 .port_type      = PORT_S3C6400,                 \
2567                 .has_divslot    = 1,                            \
2568                 .rx_fifomask    = S5PV210_UFSTAT_RXMASK,        \
2569                 .rx_fifoshift   = S5PV210_UFSTAT_RXSHIFT,       \
2570                 .rx_fifofull    = S5PV210_UFSTAT_RXFULL,        \
2571                 .tx_fifofull    = S5PV210_UFSTAT_TXFULL,        \
2572                 .tx_fifomask    = S5PV210_UFSTAT_TXMASK,        \
2573                 .tx_fifoshift   = S5PV210_UFSTAT_TXSHIFT,       \
2574                 .def_clk_sel    = S3C2410_UCON_CLKSEL0,         \
2575                 .num_clks       = 1,                            \
2576                 .clksel_mask    = 0,                            \
2577                 .clksel_shift   = 0,                            \
2578         },                                                      \
2579         .def_cfg = {                                            \
2580                 .ucon           = S5PV210_UCON_DEFAULT,         \
2581                 .ufcon          = S5PV210_UFCON_DEFAULT,        \
2582                 .has_fracval    = 1,                            \
2583         }                                                       \
2584
2585 static const struct s3c24xx_serial_drv_data exynos4210_serial_drv_data = {
2586         EXYNOS_COMMON_SERIAL_DRV_DATA(),
2587         .fifosize = { 256, 64, 16, 16 },
2588 };
2589
2590 static const struct s3c24xx_serial_drv_data exynos5433_serial_drv_data = {
2591         EXYNOS_COMMON_SERIAL_DRV_DATA(),
2592         .fifosize = { 64, 256, 16, 256 },
2593 };
2594
2595 static const struct s3c24xx_serial_drv_data exynos850_serial_drv_data = {
2596         EXYNOS_COMMON_SERIAL_DRV_DATA(),
2597         .fifosize = { 256, 64, 64, 64 },
2598 };
2599
2600 #define EXYNOS4210_SERIAL_DRV_DATA (&exynos4210_serial_drv_data)
2601 #define EXYNOS5433_SERIAL_DRV_DATA (&exynos5433_serial_drv_data)
2602 #define EXYNOS850_SERIAL_DRV_DATA (&exynos850_serial_drv_data)
2603
2604 #else
2605 #define EXYNOS4210_SERIAL_DRV_DATA NULL
2606 #define EXYNOS5433_SERIAL_DRV_DATA NULL
2607 #define EXYNOS850_SERIAL_DRV_DATA NULL
2608 #endif
2609
2610 #ifdef CONFIG_ARCH_APPLE
2611 static const struct s3c24xx_serial_drv_data s5l_serial_drv_data = {
2612         .info = {
2613                 .name           = "Apple S5L UART",
2614                 .type           = TYPE_APPLE_S5L,
2615                 .port_type      = PORT_8250,
2616                 .fifosize       = 16,
2617                 .rx_fifomask    = S3C2410_UFSTAT_RXMASK,
2618                 .rx_fifoshift   = S3C2410_UFSTAT_RXSHIFT,
2619                 .rx_fifofull    = S3C2410_UFSTAT_RXFULL,
2620                 .tx_fifofull    = S3C2410_UFSTAT_TXFULL,
2621                 .tx_fifomask    = S3C2410_UFSTAT_TXMASK,
2622                 .tx_fifoshift   = S3C2410_UFSTAT_TXSHIFT,
2623                 .def_clk_sel    = S3C2410_UCON_CLKSEL0,
2624                 .num_clks       = 1,
2625                 .clksel_mask    = 0,
2626                 .clksel_shift   = 0,
2627                 .ucon_mask      = APPLE_S5L_UCON_MASK,
2628         },
2629         .def_cfg = {
2630                 .ucon           = APPLE_S5L_UCON_DEFAULT,
2631                 .ufcon          = S3C2410_UFCON_DEFAULT,
2632         },
2633 };
2634 #define S5L_SERIAL_DRV_DATA (&s5l_serial_drv_data)
2635 #else
2636 #define S5L_SERIAL_DRV_DATA NULL
2637 #endif
2638
2639 #if defined(CONFIG_ARCH_ARTPEC)
2640 static const struct s3c24xx_serial_drv_data artpec8_serial_drv_data = {
2641         .info = {
2642                 .name           = "Axis ARTPEC-8 UART",
2643                 .type           = TYPE_S3C6400,
2644                 .port_type      = PORT_S3C6400,
2645                 .fifosize       = 64,
2646                 .has_divslot    = 1,
2647                 .rx_fifomask    = S5PV210_UFSTAT_RXMASK,
2648                 .rx_fifoshift   = S5PV210_UFSTAT_RXSHIFT,
2649                 .rx_fifofull    = S5PV210_UFSTAT_RXFULL,
2650                 .tx_fifofull    = S5PV210_UFSTAT_TXFULL,
2651                 .tx_fifomask    = S5PV210_UFSTAT_TXMASK,
2652                 .tx_fifoshift   = S5PV210_UFSTAT_TXSHIFT,
2653                 .def_clk_sel    = S3C2410_UCON_CLKSEL0,
2654                 .num_clks       = 1,
2655                 .clksel_mask    = 0,
2656                 .clksel_shift   = 0,
2657         },
2658         .def_cfg = {
2659                 .ucon           = S5PV210_UCON_DEFAULT,
2660                 .ufcon          = S5PV210_UFCON_DEFAULT,
2661                 .has_fracval    = 1,
2662         }
2663 };
2664 #define ARTPEC8_SERIAL_DRV_DATA (&artpec8_serial_drv_data)
2665 #else
2666 #define ARTPEC8_SERIAL_DRV_DATA (NULL)
2667 #endif
2668
2669 static const struct platform_device_id s3c24xx_serial_driver_ids[] = {
2670         {
2671                 .name           = "s3c6400-uart",
2672                 .driver_data    = (kernel_ulong_t)S3C6400_SERIAL_DRV_DATA,
2673         }, {
2674                 .name           = "s5pv210-uart",
2675                 .driver_data    = (kernel_ulong_t)S5PV210_SERIAL_DRV_DATA,
2676         }, {
2677                 .name           = "exynos4210-uart",
2678                 .driver_data    = (kernel_ulong_t)EXYNOS4210_SERIAL_DRV_DATA,
2679         }, {
2680                 .name           = "exynos5433-uart",
2681                 .driver_data    = (kernel_ulong_t)EXYNOS5433_SERIAL_DRV_DATA,
2682         }, {
2683                 .name           = "s5l-uart",
2684                 .driver_data    = (kernel_ulong_t)S5L_SERIAL_DRV_DATA,
2685         }, {
2686                 .name           = "exynos850-uart",
2687                 .driver_data    = (kernel_ulong_t)EXYNOS850_SERIAL_DRV_DATA,
2688         }, {
2689                 .name           = "artpec8-uart",
2690                 .driver_data    = (kernel_ulong_t)ARTPEC8_SERIAL_DRV_DATA,
2691         },
2692         { },
2693 };
2694 MODULE_DEVICE_TABLE(platform, s3c24xx_serial_driver_ids);
2695
2696 #ifdef CONFIG_OF
2697 static const struct of_device_id s3c24xx_uart_dt_match[] = {
2698         { .compatible = "samsung,s3c6400-uart",
2699                 .data = S3C6400_SERIAL_DRV_DATA },
2700         { .compatible = "samsung,s5pv210-uart",
2701                 .data = S5PV210_SERIAL_DRV_DATA },
2702         { .compatible = "samsung,exynos4210-uart",
2703                 .data = EXYNOS4210_SERIAL_DRV_DATA },
2704         { .compatible = "samsung,exynos5433-uart",
2705                 .data = EXYNOS5433_SERIAL_DRV_DATA },
2706         { .compatible = "apple,s5l-uart",
2707                 .data = S5L_SERIAL_DRV_DATA },
2708         { .compatible = "samsung,exynos850-uart",
2709                 .data = EXYNOS850_SERIAL_DRV_DATA },
2710         { .compatible = "axis,artpec8-uart",
2711                 .data = ARTPEC8_SERIAL_DRV_DATA },
2712         {},
2713 };
2714 MODULE_DEVICE_TABLE(of, s3c24xx_uart_dt_match);
2715 #endif
2716
2717 static struct platform_driver samsung_serial_driver = {
2718         .probe          = s3c24xx_serial_probe,
2719         .remove         = s3c24xx_serial_remove,
2720         .id_table       = s3c24xx_serial_driver_ids,
2721         .driver         = {
2722                 .name   = "samsung-uart",
2723                 .pm     = SERIAL_SAMSUNG_PM_OPS,
2724                 .of_match_table = of_match_ptr(s3c24xx_uart_dt_match),
2725         },
2726 };
2727
2728 static int __init samsung_serial_init(void)
2729 {
2730         int ret;
2731
2732         s3c24xx_serial_register_console();
2733
2734         ret = platform_driver_register(&samsung_serial_driver);
2735         if (ret) {
2736                 s3c24xx_serial_unregister_console();
2737                 return ret;
2738         }
2739
2740         return 0;
2741 }
2742
2743 static void __exit samsung_serial_exit(void)
2744 {
2745         platform_driver_unregister(&samsung_serial_driver);
2746         s3c24xx_serial_unregister_console();
2747 }
2748
2749 module_init(samsung_serial_init);
2750 module_exit(samsung_serial_exit);
2751
2752 #ifdef CONFIG_SERIAL_SAMSUNG_CONSOLE
2753 /*
2754  * Early console.
2755  */
2756
2757 static void wr_reg_barrier(const struct uart_port *port, u32 reg, u32 val)
2758 {
2759         switch (port->iotype) {
2760         case UPIO_MEM:
2761                 writeb(val, portaddr(port, reg));
2762                 break;
2763         case UPIO_MEM32:
2764                 writel(val, portaddr(port, reg));
2765                 break;
2766         }
2767 }
2768
2769 struct samsung_early_console_data {
2770         u32 txfull_mask;
2771         u32 rxfifo_mask;
2772 };
2773
2774 static void samsung_early_busyuart(const struct uart_port *port)
2775 {
2776         while (!(readl(port->membase + S3C2410_UTRSTAT) & S3C2410_UTRSTAT_TXFE))
2777                 ;
2778 }
2779
2780 static void samsung_early_busyuart_fifo(const struct uart_port *port)
2781 {
2782         const struct samsung_early_console_data *data = port->private_data;
2783
2784         while (readl(port->membase + S3C2410_UFSTAT) & data->txfull_mask)
2785                 ;
2786 }
2787
2788 static void samsung_early_putc(struct uart_port *port, unsigned char c)
2789 {
2790         if (readl(port->membase + S3C2410_UFCON) & S3C2410_UFCON_FIFOMODE)
2791                 samsung_early_busyuart_fifo(port);
2792         else
2793                 samsung_early_busyuart(port);
2794
2795         wr_reg_barrier(port, S3C2410_UTXH, c);
2796 }
2797
2798 static void samsung_early_write(struct console *con, const char *s,
2799                                 unsigned int n)
2800 {
2801         struct earlycon_device *dev = con->data;
2802
2803         uart_console_write(&dev->port, s, n, samsung_early_putc);
2804 }
2805
2806 static int samsung_early_read(struct console *con, char *s, unsigned int n)
2807 {
2808         struct earlycon_device *dev = con->data;
2809         const struct samsung_early_console_data *data = dev->port.private_data;
2810         int ch, ufstat, num_read = 0;
2811
2812         while (num_read < n) {
2813                 ufstat = rd_regl(&dev->port, S3C2410_UFSTAT);
2814                 if (!(ufstat & data->rxfifo_mask))
2815                         break;
2816                 ch = rd_reg(&dev->port, S3C2410_URXH);
2817                 if (ch == NO_POLL_CHAR)
2818                         break;
2819
2820                 s[num_read++] = ch;
2821         }
2822
2823         return num_read;
2824 }
2825
2826 static int __init samsung_early_console_setup(struct earlycon_device *device,
2827                                               const char *opt)
2828 {
2829         if (!device->port.membase)
2830                 return -ENODEV;
2831
2832         device->con->write = samsung_early_write;
2833         device->con->read = samsung_early_read;
2834         return 0;
2835 }
2836
2837 /* S3C2410 */
2838 static struct samsung_early_console_data s3c2410_early_console_data = {
2839         .txfull_mask = S3C2410_UFSTAT_TXFULL,
2840         .rxfifo_mask = S3C2410_UFSTAT_RXFULL | S3C2410_UFSTAT_RXMASK,
2841 };
2842
2843 static int __init s3c2410_early_console_setup(struct earlycon_device *device,
2844                                               const char *opt)
2845 {
2846         device->port.private_data = &s3c2410_early_console_data;
2847         return samsung_early_console_setup(device, opt);
2848 }
2849
2850 OF_EARLYCON_DECLARE(s3c2410, "samsung,s3c2410-uart",
2851                         s3c2410_early_console_setup);
2852
2853 /* S3C2412, S3C2440, S3C64xx */
2854 static struct samsung_early_console_data s3c2440_early_console_data = {
2855         .txfull_mask = S3C2440_UFSTAT_TXFULL,
2856         .rxfifo_mask = S3C2440_UFSTAT_RXFULL | S3C2440_UFSTAT_RXMASK,
2857 };
2858
2859 static int __init s3c2440_early_console_setup(struct earlycon_device *device,
2860                                               const char *opt)
2861 {
2862         device->port.private_data = &s3c2440_early_console_data;
2863         return samsung_early_console_setup(device, opt);
2864 }
2865
2866 OF_EARLYCON_DECLARE(s3c2412, "samsung,s3c2412-uart",
2867                         s3c2440_early_console_setup);
2868 OF_EARLYCON_DECLARE(s3c2440, "samsung,s3c2440-uart",
2869                         s3c2440_early_console_setup);
2870 OF_EARLYCON_DECLARE(s3c6400, "samsung,s3c6400-uart",
2871                         s3c2440_early_console_setup);
2872
2873 /* S5PV210, Exynos */
2874 static struct samsung_early_console_data s5pv210_early_console_data = {
2875         .txfull_mask = S5PV210_UFSTAT_TXFULL,
2876         .rxfifo_mask = S5PV210_UFSTAT_RXFULL | S5PV210_UFSTAT_RXMASK,
2877 };
2878
2879 static int __init s5pv210_early_console_setup(struct earlycon_device *device,
2880                                               const char *opt)
2881 {
2882         device->port.private_data = &s5pv210_early_console_data;
2883         return samsung_early_console_setup(device, opt);
2884 }
2885
2886 OF_EARLYCON_DECLARE(s5pv210, "samsung,s5pv210-uart",
2887                         s5pv210_early_console_setup);
2888 OF_EARLYCON_DECLARE(exynos4210, "samsung,exynos4210-uart",
2889                         s5pv210_early_console_setup);
2890 OF_EARLYCON_DECLARE(artpec8, "axis,artpec8-uart",
2891                         s5pv210_early_console_setup);
2892
2893 /* Apple S5L */
2894 static int __init apple_s5l_early_console_setup(struct earlycon_device *device,
2895                                                 const char *opt)
2896 {
2897         /* Close enough to S3C2410 for earlycon... */
2898         device->port.private_data = &s3c2410_early_console_data;
2899
2900 #ifdef CONFIG_ARM64
2901         /* ... but we need to override the existing fixmap entry as nGnRnE */
2902         __set_fixmap(FIX_EARLYCON_MEM_BASE, device->port.mapbase,
2903                      __pgprot(PROT_DEVICE_nGnRnE));
2904 #endif
2905         return samsung_early_console_setup(device, opt);
2906 }
2907
2908 OF_EARLYCON_DECLARE(s5l, "apple,s5l-uart", apple_s5l_early_console_setup);
2909 #endif
2910
2911 MODULE_ALIAS("platform:samsung-uart");
2912 MODULE_DESCRIPTION("Samsung SoC Serial port driver");
2913 MODULE_AUTHOR("Ben Dooks <[email protected]>");
2914 MODULE_LICENSE("GPL v2");