drivers/mmc/host/sdhci-pxav2.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * Copyright (C) 2010 Marvell International Ltd.
   4  *              Zhangfei Gao <[email protected]>
   5  *              Kevin Wang <[email protected]>
   6  *              Jun Nie <[email protected]>
   7  *              Qiming Wu <[email protected]>
   8  *              Philip Rakity <[email protected]>
   9  */
  10
  11 #include <linux/err.h>
  12 #include <linux/init.h>
  13 #include <linux/platform_device.h>
  14 #include <linux/clk.h>
  15 #include <linux/module.h>
  16 #include <linux/io.h>
  17 #include <linux/mmc/card.h>
  18 #include <linux/mmc/host.h>
  19 #include <linux/platform_data/pxa_sdhci.h>
  20 #include <linux/slab.h>
  21 #include <linux/of.h>
  22 #include <linux/of_device.h>
  23 #include <linux/mmc/sdio.h>
  24 #include <linux/mmc/mmc.h>
  25 #include <linux/pinctrl/consumer.h>
  26
  27 #include "sdhci.h"
  28 #include "sdhci-pltfm.h"
  29
  30 #define SD_FIFO_PARAM           0xe0
  31 #define DIS_PAD_SD_CLK_GATE     0x0400 /* Turn on/off Dynamic SD Clock Gating */
  32 #define CLK_GATE_ON             0x0200 /* Disable/enable Clock Gate */
  33 #define CLK_GATE_CTL            0x0100 /* Clock Gate Control */
  34 #define CLK_GATE_SETTING_BITS   (DIS_PAD_SD_CLK_GATE | \
  35                 CLK_GATE_ON | CLK_GATE_CTL)
  36
  37 #define SD_CLOCK_BURST_SIZE_SETUP       0xe6
  38 #define SDCLK_SEL_SHIFT         8
  39 #define SDCLK_SEL_MASK          0x3
  40 #define SDCLK_DELAY_SHIFT       10
  41 #define SDCLK_DELAY_MASK        0x3c
  42
  43 #define SD_CE_ATA_2             0xea
  44 #define MMC_CARD                0x1000
  45 #define MMC_WIDTH               0x0100
  46
  47 struct sdhci_pxav2_host {
  48         struct mmc_request *sdio_mrq;
  49         struct pinctrl *pinctrl;
  50         struct pinctrl_state *pins_default;
  51         struct pinctrl_state *pins_cmd_gpio;
  52 };
  53
  54 static void pxav2_reset(struct sdhci_host *host, u8 mask)
  55 {
  56         struct platform_device *pdev = to_platform_device(mmc_dev(host->mmc));
  57         struct sdhci_pxa_platdata *pdata = pdev->dev.platform_data;
  58
  59         sdhci_reset(host, mask);
  60
  61         if (mask == SDHCI_RESET_ALL) {
  62                 u16 tmp = 0;
  63
  64                 /*
  65                  * tune timing of read data/command when crc error happen
  66                  * no performance impact
  67                  */
  68                 if (pdata && pdata->clk_delay_sel == 1) {
  69                         tmp = readw(host->ioaddr + SD_CLOCK_BURST_SIZE_SETUP);
  70
  71                         tmp &= ~(SDCLK_DELAY_MASK << SDCLK_DELAY_SHIFT);
  72                         tmp |= (pdata->clk_delay_cycles & SDCLK_DELAY_MASK)
  73                                 << SDCLK_DELAY_SHIFT;
  74                         tmp &= ~(SDCLK_SEL_MASK << SDCLK_SEL_SHIFT);
  75                         tmp |= (1 & SDCLK_SEL_MASK) << SDCLK_SEL_SHIFT;
  76
  77                         writew(tmp, host->ioaddr + SD_CLOCK_BURST_SIZE_SETUP);
  78                 }
  79
  80                 if (pdata && (pdata->flags & PXA_FLAG_ENABLE_CLOCK_GATING)) {
  81                         tmp = readw(host->ioaddr + SD_FIFO_PARAM);
  82                         tmp &= ~CLK_GATE_SETTING_BITS;
  83                         writew(tmp, host->ioaddr + SD_FIFO_PARAM);
  84                 } else {
  85                         tmp = readw(host->ioaddr + SD_FIFO_PARAM);
  86                         tmp &= ~CLK_GATE_SETTING_BITS;
  87                         tmp |= CLK_GATE_SETTING_BITS;
  88                         writew(tmp, host->ioaddr + SD_FIFO_PARAM);
  89                 }
  90         }
  91 }
  92
  93 static u16 pxav1_readw(struct sdhci_host *host, int reg)
  94 {
  95         /* Workaround for data abort exception on SDH2 and SDH4 on PXA168 */
  96         if (reg == SDHCI_HOST_VERSION)
  97                 return readl(host->ioaddr + SDHCI_HOST_VERSION - 2) >> 16;
  98
  99         return readw(host->ioaddr + reg);
 100 }
 101
 102 static u32 pxav1_irq(struct sdhci_host *host, u32 intmask)
 103 {
 104         struct sdhci_pxav2_host *pxav2_host = sdhci_pltfm_priv(sdhci_priv(host));
 105         struct mmc_request *sdio_mrq;
 106
 107         if (pxav2_host->sdio_mrq && (intmask & SDHCI_INT_CMD_MASK)) {
 108                 /* The dummy CMD0 for the SDIO workaround just completed */
 109                 sdhci_writel(host, intmask & SDHCI_INT_CMD_MASK, SDHCI_INT_STATUS);
 110                 intmask &= ~SDHCI_INT_CMD_MASK;
 111
 112                 /* Restore MMC function to CMD pin */
 113                 if (pxav2_host->pinctrl && pxav2_host->pins_default)
 114                         pinctrl_select_state(pxav2_host->pinctrl, pxav2_host->pins_default);
 115
 116                 sdio_mrq = pxav2_host->sdio_mrq;
 117                 pxav2_host->sdio_mrq = NULL;
 118                 mmc_request_done(host->mmc, sdio_mrq);
 119         }
 120
 121         return intmask;
 122 }
 123
 124 static void pxav1_request_done(struct sdhci_host *host, struct mmc_request *mrq)
 125 {
 126         u16 tmp;
 127         struct sdhci_pxav2_host *pxav2_host;
 128
 129         /* If this is an SDIO command, perform errata workaround for silicon bug */
 130         if (mrq->cmd && !mrq->cmd->error &&
 131             (mrq->cmd->opcode == SD_IO_RW_DIRECT ||
 132              mrq->cmd->opcode == SD_IO_RW_EXTENDED)) {
 133                 /* Reset data port */
 134                 tmp = readw(host->ioaddr + SDHCI_TIMEOUT_CONTROL);
 135                 tmp |= 0x400;
 136                 writew(tmp, host->ioaddr + SDHCI_TIMEOUT_CONTROL);
 137
 138                 /* Clock is now stopped, so restart it by sending a dummy CMD0 */
 139                 pxav2_host = sdhci_pltfm_priv(sdhci_priv(host));
 140                 pxav2_host->sdio_mrq = mrq;
 141
 142                 /* Set CMD as high output rather than MMC function while we do CMD0 */
 143                 if (pxav2_host->pinctrl && pxav2_host->pins_cmd_gpio)
 144                         pinctrl_select_state(pxav2_host->pinctrl, pxav2_host->pins_cmd_gpio);
 145
 146                 sdhci_writel(host, 0, SDHCI_ARGUMENT);
 147                 sdhci_writew(host, 0, SDHCI_TRANSFER_MODE);
 148                 sdhci_writew(host, SDHCI_MAKE_CMD(MMC_GO_IDLE_STATE, SDHCI_CMD_RESP_NONE),
 149                              SDHCI_COMMAND);
 150
 151                 /* Don't finish this request until the dummy CMD0 finishes */
 152                 return;
 153         }
 154
 155         mmc_request_done(host->mmc, mrq);
 156 }
 157
 158 static void pxav2_mmc_set_bus_width(struct sdhci_host *host, int width)
 159 {
 160         u8 ctrl;
 161         u16 tmp;
 162
 163         ctrl = readb(host->ioaddr + SDHCI_HOST_CONTROL);
 164         tmp = readw(host->ioaddr + SD_CE_ATA_2);
 165         if (width == MMC_BUS_WIDTH_8) {
 166                 ctrl &= ~SDHCI_CTRL_4BITBUS;
 167                 tmp |= MMC_CARD | MMC_WIDTH;
 168         } else {
 169                 tmp &= ~(MMC_CARD | MMC_WIDTH);
 170                 if (width == MMC_BUS_WIDTH_4)
 171                         ctrl |= SDHCI_CTRL_4BITBUS;
 172                 else
 173                         ctrl &= ~SDHCI_CTRL_4BITBUS;
 174         }
 175         writew(tmp, host->ioaddr + SD_CE_ATA_2);
 176         writeb(ctrl, host->ioaddr + SDHCI_HOST_CONTROL);
 177 }
 178
 179 struct sdhci_pxa_variant {
 180         const struct sdhci_ops *ops;
 181         unsigned int extra_quirks;
 182 };
 183
 184 static const struct sdhci_ops pxav1_sdhci_ops = {
 185         .read_w        = pxav1_readw,
 186         .set_clock     = sdhci_set_clock,
 187         .irq           = pxav1_irq,
 188         .get_max_clock = sdhci_pltfm_clk_get_max_clock,
 189         .set_bus_width = pxav2_mmc_set_bus_width,
 190         .reset         = pxav2_reset,
 191         .set_uhs_signaling = sdhci_set_uhs_signaling,
 192         .request_done  = pxav1_request_done,
 193 };
 194
 195 static const struct sdhci_pxa_variant __maybe_unused pxav1_variant = {
 196         .ops = &pxav1_sdhci_ops,
 197         .extra_quirks = SDHCI_QUIRK_NO_BUSY_IRQ | SDHCI_QUIRK_32BIT_DMA_SIZE,
 198 };
 199
 200 static const struct sdhci_ops pxav2_sdhci_ops = {
 201         .set_clock     = sdhci_set_clock,
 202         .get_max_clock = sdhci_pltfm_clk_get_max_clock,
 203         .set_bus_width = pxav2_mmc_set_bus_width,
 204         .reset         = pxav2_reset,
 205         .set_uhs_signaling = sdhci_set_uhs_signaling,
 206 };
 207
 208 static const struct sdhci_pxa_variant pxav2_variant = {
 209         .ops = &pxav2_sdhci_ops,
 210 };
 211
 212 #ifdef CONFIG_OF
 213 static const struct of_device_id sdhci_pxav2_of_match[] = {
 214         { .compatible = "mrvl,pxav1-mmc", .data = &pxav1_variant, },
 215         { .compatible = "mrvl,pxav2-mmc", .data = &pxav2_variant, },
 216         {},
 217 };
 218 MODULE_DEVICE_TABLE(of, sdhci_pxav2_of_match);
 219
 220 static struct sdhci_pxa_platdata *pxav2_get_mmc_pdata(struct device *dev)
 221 {
 222         struct sdhci_pxa_platdata *pdata;
 223         struct device_node *np = dev->of_node;
 224         u32 bus_width;
 225         u32 clk_delay_cycles;
 226
 227         pdata = devm_kzalloc(dev, sizeof(*pdata), GFP_KERNEL);
 228         if (!pdata)
 229                 return NULL;
 230
 231         if (of_property_read_bool(np, "non-removable"))
 232                 pdata->flags |= PXA_FLAG_CARD_PERMANENT;
 233
 234         of_property_read_u32(np, "bus-width", &bus_width);
 235         if (bus_width == 8)
 236                 pdata->flags |= PXA_FLAG_SD_8_BIT_CAPABLE_SLOT;
 237
 238         of_property_read_u32(np, "mrvl,clk-delay-cycles", &clk_delay_cycles);
 239         if (clk_delay_cycles > 0) {
 240                 pdata->clk_delay_sel = 1;
 241                 pdata->clk_delay_cycles = clk_delay_cycles;
 242         }
 243
 244         return pdata;
 245 }
 246 #else
 247 static inline struct sdhci_pxa_platdata *pxav2_get_mmc_pdata(struct device *dev)
 248 {
 249         return NULL;
 250 }
 251 #endif
 252
 253 static int sdhci_pxav2_probe(struct platform_device *pdev)
 254 {
 255         struct sdhci_pltfm_host *pltfm_host;
 256         struct sdhci_pxa_platdata *pdata = pdev->dev.platform_data;
 257         struct sdhci_pxav2_host *pxav2_host;
 258         struct device *dev = &pdev->dev;
 259         struct sdhci_host *host = NULL;
 260         const struct sdhci_pxa_variant *variant;
 261
 262         int ret;
 263         struct clk *clk, *clk_core;
 264
 265         host = sdhci_pltfm_init(pdev, NULL, sizeof(*pxav2_host));
 266         if (IS_ERR(host))
 267                 return PTR_ERR(host);
 268
 269         pltfm_host = sdhci_priv(host);
 270         pxav2_host = sdhci_pltfm_priv(pltfm_host);
 271
 272         clk = devm_clk_get(dev, "io");
 273         if (IS_ERR(clk) && PTR_ERR(clk) != -EPROBE_DEFER)
 274                 clk = devm_clk_get(dev, NULL);
 275         if (IS_ERR(clk)) {
 276                 ret = PTR_ERR(clk);
 277                 dev_err_probe(dev, ret, "failed to get io clock\n");
 278                 goto free;
 279         }
 280         pltfm_host->clk = clk;
 281         ret = clk_prepare_enable(clk);
 282         if (ret) {
 283                 dev_err(dev, "failed to enable io clock\n");
 284                 goto free;
 285         }
 286
 287         clk_core = devm_clk_get_optional_enabled(dev, "core");
 288         if (IS_ERR(clk_core)) {
 289                 ret = PTR_ERR(clk_core);
 290                 dev_err_probe(dev, ret, "failed to enable core clock\n");
 291                 goto disable_clk;
 292         }
 293
 294         host->quirks = SDHCI_QUIRK_BROKEN_ADMA
 295                 | SDHCI_QUIRK_BROKEN_TIMEOUT_VAL
 296                 | SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN;
 297
 298         variant = of_device_get_match_data(dev);
 299         if (variant)
 300                 pdata = pxav2_get_mmc_pdata(dev);
 301         else
 302                 variant = &pxav2_variant;
 303
 304         if (pdata) {
 305                 if (pdata->flags & PXA_FLAG_CARD_PERMANENT) {
 306                         /* on-chip device */
 307                         host->quirks |= SDHCI_QUIRK_BROKEN_CARD_DETECTION;
 308                         host->mmc->caps |= MMC_CAP_NONREMOVABLE;
 309                 }
 310
 311                 /* If slot design supports 8 bit data, indicate this to MMC. */
 312                 if (pdata->flags & PXA_FLAG_SD_8_BIT_CAPABLE_SLOT)
 313                         host->mmc->caps |= MMC_CAP_8_BIT_DATA;
 314
 315                 if (pdata->quirks)
 316                         host->quirks |= pdata->quirks;
 317                 if (pdata->host_caps)
 318                         host->mmc->caps |= pdata->host_caps;
 319                 if (pdata->pm_caps)
 320                         host->mmc->pm_caps |= pdata->pm_caps;
 321         }
 322
 323         host->quirks |= variant->extra_quirks;
 324         host->ops = variant->ops;
 325
 326         /* Set up optional pinctrl for PXA168 SDIO IRQ fix */
 327         pxav2_host->pinctrl = devm_pinctrl_get(dev);
 328         if (!IS_ERR(pxav2_host->pinctrl)) {
 329                 pxav2_host->pins_cmd_gpio = pinctrl_lookup_state(pxav2_host->pinctrl,
 330                                                                  "state_cmd_gpio");
 331                 if (IS_ERR(pxav2_host->pins_cmd_gpio))
 332                         pxav2_host->pins_cmd_gpio = NULL;
 333                 pxav2_host->pins_default = pinctrl_lookup_state(pxav2_host->pinctrl,
 334                                                                 "default");
 335                 if (IS_ERR(pxav2_host->pins_default))
 336                         pxav2_host->pins_default = NULL;
 337         } else {
 338                 pxav2_host->pinctrl = NULL;
 339         }
 340
 341         ret = sdhci_add_host(host);
 342         if (ret)
 343                 goto disable_clk;
 344
 345         return 0;
 346
 347 disable_clk:
 348         clk_disable_unprepare(clk);
 349 free:
 350         sdhci_pltfm_free(pdev);
 351         return ret;
 352 }
 353
 354 static struct platform_driver sdhci_pxav2_driver = {
 355         .driver         = {
 356                 .name   = "sdhci-pxav2",
 357                 .probe_type = PROBE_PREFER_ASYNCHRONOUS,
 358                 .of_match_table = of_match_ptr(sdhci_pxav2_of_match),
 359                 .pm     = &sdhci_pltfm_pmops,
 360         },
 361         .probe          = sdhci_pxav2_probe,
 362         .remove         = sdhci_pltfm_unregister,
 363 };
 364
 365 module_platform_driver(sdhci_pxav2_driver);
 366
 367 MODULE_DESCRIPTION("SDHCI driver for pxav2");
 368 MODULE_AUTHOR("Marvell International Ltd.");
 369 MODULE_LICENSE("GPL v2");
 370