drivers/iio/dac/ad7293.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * AD7293 driver
   4  *
   5  * Copyright 2021 Analog Devices Inc.
   6  */
   7
   8 #include <linux/bitfield.h>
   9 #include <linux/bits.h>
  10 #include <linux/delay.h>
  11 #include <linux/device.h>
  12 #include <linux/gpio/consumer.h>
  13 #include <linux/iio/iio.h>
  14 #include <linux/mod_devicetable.h>
  15 #include <linux/module.h>
  16 #include <linux/regulator/consumer.h>
  17 #include <linux/spi/spi.h>
  18
  19 #include <asm/unaligned.h>
  20
  21 #define AD7293_R1B                              BIT(16)
  22 #define AD7293_R2B                              BIT(17)
  23 #define AD7293_PAGE_ADDR_MSK                    GENMASK(15, 8)
  24 #define AD7293_PAGE(x)                          FIELD_PREP(AD7293_PAGE_ADDR_MSK, x)
  25
  26 /* AD7293 Register Map Common */
  27 #define AD7293_REG_NO_OP                        (AD7293_R1B | AD7293_PAGE(0x0) | 0x0)
  28 #define AD7293_REG_PAGE_SELECT                  (AD7293_R1B | AD7293_PAGE(0x0) | 0x1)
  29 #define AD7293_REG_CONV_CMD                     (AD7293_R2B | AD7293_PAGE(0x0) | 0x2)
  30 #define AD7293_REG_RESULT                       (AD7293_R1B | AD7293_PAGE(0x0) | 0x3)
  31 #define AD7293_REG_DAC_EN                       (AD7293_R1B | AD7293_PAGE(0x0) | 0x4)
  32 #define AD7293_REG_DEVICE_ID                    (AD7293_R2B | AD7293_PAGE(0x0) | 0xC)
  33 #define AD7293_REG_SOFT_RESET                   (AD7293_R2B | AD7293_PAGE(0x0) | 0xF)
  34
  35 /* AD7293 Register Map Page 0x0 */
  36 #define AD7293_REG_VIN0                         (AD7293_R2B | AD7293_PAGE(0x0) | 0x10)
  37 #define AD7293_REG_VIN1                         (AD7293_R2B | AD7293_PAGE(0x0) | 0x11)
  38 #define AD7293_REG_VIN2                         (AD7293_R2B | AD7293_PAGE(0x0) | 0x12)
  39 #define AD7293_REG_VIN3                         (AD7293_R2B | AD7293_PAGE(0x0) | 0x13)
  40 #define AD7293_REG_TSENSE_INT                   (AD7293_R2B | AD7293_PAGE(0x0) | 0x20)
  41 #define AD7293_REG_TSENSE_D0                    (AD7293_R2B | AD7293_PAGE(0x0) | 0x21)
  42 #define AD7293_REG_TSENSE_D1                    (AD7293_R2B | AD7293_PAGE(0x0) | 0x22)
  43 #define AD7293_REG_ISENSE_0                     (AD7293_R2B | AD7293_PAGE(0x0) | 0x28)
  44 #define AD7293_REG_ISENSE_1                     (AD7293_R2B | AD7293_PAGE(0x0) | 0x29)
  45 #define AD7293_REG_ISENSE_2                     (AD7293_R2B | AD7293_PAGE(0x0) | 0x2A)
  46 #define AD7293_REG_ISENSE_3                     (AD7293_R2B | AD7293_PAGE(0x0) | 0x2B)
  47 #define AD7293_REG_UNI_VOUT0                    (AD7293_R2B | AD7293_PAGE(0x0) | 0x30)
  48 #define AD7293_REG_UNI_VOUT1                    (AD7293_R2B | AD7293_PAGE(0x0) | 0x31)
  49 #define AD7293_REG_UNI_VOUT2                    (AD7293_R2B | AD7293_PAGE(0x0) | 0x32)
  50 #define AD7293_REG_UNI_VOUT3                    (AD7293_R2B | AD7293_PAGE(0x0) | 0x33)
  51 #define AD7293_REG_BI_VOUT0                     (AD7293_R2B | AD7293_PAGE(0x0) | 0x34)
  52 #define AD7293_REG_BI_VOUT1                     (AD7293_R2B | AD7293_PAGE(0x0) | 0x35)
  53 #define AD7293_REG_BI_VOUT2                     (AD7293_R2B | AD7293_PAGE(0x0) | 0x36)
  54 #define AD7293_REG_BI_VOUT3                     (AD7293_R2B | AD7293_PAGE(0x0) | 0x37)
  55
  56 /* AD7293 Register Map Page 0x2 */
  57 #define AD7293_REG_DIGITAL_OUT_EN               (AD7293_R2B | AD7293_PAGE(0x2) | 0x11)
  58 #define AD7293_REG_DIGITAL_INOUT_FUNC           (AD7293_R2B | AD7293_PAGE(0x2) | 0x12)
  59 #define AD7293_REG_DIGITAL_FUNC_POL             (AD7293_R2B | AD7293_PAGE(0x2) | 0x13)
  60 #define AD7293_REG_GENERAL                      (AD7293_R2B | AD7293_PAGE(0x2) | 0x14)
  61 #define AD7293_REG_VINX_RANGE0                  (AD7293_R2B | AD7293_PAGE(0x2) | 0x15)
  62 #define AD7293_REG_VINX_RANGE1                  (AD7293_R2B | AD7293_PAGE(0x2) | 0x16)
  63 #define AD7293_REG_VINX_DIFF_SE                 (AD7293_R2B | AD7293_PAGE(0x2) | 0x17)
  64 #define AD7293_REG_VINX_FILTER                  (AD7293_R2B | AD7293_PAGE(0x2) | 0x18)
  65 #define AD7293_REG_BG_EN                        (AD7293_R2B | AD7293_PAGE(0x2) | 0x19)
  66 #define AD7293_REG_CONV_DELAY                   (AD7293_R2B | AD7293_PAGE(0x2) | 0x1A)
  67 #define AD7293_REG_TSENSE_BG_EN                 (AD7293_R2B | AD7293_PAGE(0x2) | 0x1B)
  68 #define AD7293_REG_ISENSE_BG_EN                 (AD7293_R2B | AD7293_PAGE(0x2) | 0x1C)
  69 #define AD7293_REG_ISENSE_GAIN                  (AD7293_R2B | AD7293_PAGE(0x2) | 0x1D)
  70 #define AD7293_REG_DAC_SNOOZE_O                 (AD7293_R2B | AD7293_PAGE(0x2) | 0x1F)
  71 #define AD7293_REG_DAC_SNOOZE_1                 (AD7293_R2B | AD7293_PAGE(0x2) | 0x20)
  72 #define AD7293_REG_RSX_MON_BG_EN                (AD7293_R2B | AD7293_PAGE(0x2) | 0x23)
  73 #define AD7293_REG_INTEGR_CL                    (AD7293_R2B | AD7293_PAGE(0x2) | 0x28)
  74 #define AD7293_REG_PA_ON_CTRL                   (AD7293_R2B | AD7293_PAGE(0x2) | 0x29)
  75 #define AD7293_REG_RAMP_TIME_0                  (AD7293_R2B | AD7293_PAGE(0x2) | 0x2A)
  76 #define AD7293_REG_RAMP_TIME_1                  (AD7293_R2B | AD7293_PAGE(0x2) | 0x2B)
  77 #define AD7293_REG_RAMP_TIME_2                  (AD7293_R2B | AD7293_PAGE(0x2) | 0x2C)
  78 #define AD7293_REG_RAMP_TIME_3                  (AD7293_R2B | AD7293_PAGE(0x2) | 0x2D)
  79 #define AD7293_REG_CL_FR_IT                     (AD7293_R2B | AD7293_PAGE(0x2) | 0x2E)
  80 #define AD7293_REG_INTX_AVSS_AVDD               (AD7293_R2B | AD7293_PAGE(0x2) | 0x2F)
  81
  82 /* AD7293 Register Map Page 0x3 */
  83 #define AD7293_REG_VINX_SEQ                     (AD7293_R2B | AD7293_PAGE(0x3) | 0x10)
  84 #define AD7293_REG_ISENSEX_TSENSEX_SEQ          (AD7293_R2B | AD7293_PAGE(0x3) | 0x11)
  85 #define AD7293_REG_RSX_MON_BI_VOUTX_SEQ         (AD7293_R2B | AD7293_PAGE(0x3) | 0x12)
  86
  87 /* AD7293 Register Map Page 0xE */
  88 #define AD7293_REG_VIN0_OFFSET                  (AD7293_R1B | AD7293_PAGE(0xE) | 0x10)
  89 #define AD7293_REG_VIN1_OFFSET                  (AD7293_R1B | AD7293_PAGE(0xE) | 0x11)
  90 #define AD7293_REG_VIN2_OFFSET                  (AD7293_R1B | AD7293_PAGE(0xE) | 0x12)
  91 #define AD7293_REG_VIN3_OFFSET                  (AD7293_R1B | AD7293_PAGE(0xE) | 0x13)
  92 #define AD7293_REG_TSENSE_INT_OFFSET            (AD7293_R1B | AD7293_PAGE(0xE) | 0x20)
  93 #define AD7293_REG_TSENSE_D0_OFFSET             (AD7293_R1B | AD7293_PAGE(0xE) | 0x21)
  94 #define AD7293_REG_TSENSE_D1_OFFSET             (AD7293_R1B | AD7293_PAGE(0xE) | 0x22)
  95 #define AD7293_REG_ISENSE0_OFFSET               (AD7293_R1B | AD7293_PAGE(0xE) | 0x28)
  96 #define AD7293_REG_ISENSE1_OFFSET               (AD7293_R1B | AD7293_PAGE(0xE) | 0x29)
  97 #define AD7293_REG_ISENSE2_OFFSET               (AD7293_R1B | AD7293_PAGE(0xE) | 0x2A)
  98 #define AD7293_REG_ISENSE3_OFFSET               (AD7293_R1B | AD7293_PAGE(0xE) | 0x2B)
  99 #define AD7293_REG_UNI_VOUT0_OFFSET             (AD7293_R1B | AD7293_PAGE(0xE) | 0x30)
 100 #define AD7293_REG_UNI_VOUT1_OFFSET             (AD7293_R1B | AD7293_PAGE(0xE) | 0x31)
 101 #define AD7293_REG_UNI_VOUT2_OFFSET             (AD7293_R1B | AD7293_PAGE(0xE) | 0x32)
 102 #define AD7293_REG_UNI_VOUT3_OFFSET             (AD7293_R1B | AD7293_PAGE(0xE) | 0x33)
 103 #define AD7293_REG_BI_VOUT0_OFFSET              (AD7293_R1B | AD7293_PAGE(0xE) | 0x34)
 104 #define AD7293_REG_BI_VOUT1_OFFSET              (AD7293_R1B | AD7293_PAGE(0xE) | 0x35)
 105 #define AD7293_REG_BI_VOUT2_OFFSET              (AD7293_R1B | AD7293_PAGE(0xE) | 0x36)
 106 #define AD7293_REG_BI_VOUT3_OFFSET              (AD7293_R1B | AD7293_PAGE(0xE) | 0x37)
 107
 108 /* AD7293 Miscellaneous Definitions */
 109 #define AD7293_READ                             BIT(7)
 110 #define AD7293_TRANSF_LEN_MSK                   GENMASK(17, 16)
 111
 112 #define AD7293_REG_ADDR_MSK                     GENMASK(7, 0)
 113 #define AD7293_REG_VOUT_OFFSET_MSK              GENMASK(5, 4)
 114 #define AD7293_REG_DATA_RAW_MSK                 GENMASK(15, 4)
 115 #define AD7293_REG_VINX_RANGE_GET_CH_MSK(x, ch) (((x) >> (ch)) & 0x1)
 116 #define AD7293_REG_VINX_RANGE_SET_CH_MSK(x, ch) (((x) & 0x1) << (ch))
 117 #define AD7293_CHIP_ID                          0x18
 118
 119 enum ad7293_ch_type {
 120         AD7293_ADC_VINX,
 121         AD7293_ADC_TSENSE,
 122         AD7293_ADC_ISENSE,
 123         AD7293_DAC,
 124 };
 125
 126 enum ad7293_max_offset {
 127         AD7293_TSENSE_MIN_OFFSET_CH = 4,
 128         AD7293_ISENSE_MIN_OFFSET_CH = 7,
 129         AD7293_VOUT_MIN_OFFSET_CH = 11,
 130         AD7293_VOUT_MAX_OFFSET_CH = 18,
 131 };
 132
 133 static const int dac_offset_table[] = {0, 1, 2};
 134
 135 static const int isense_gain_table[] = {0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10};
 136
 137 static const int adc_range_table[] = {0, 1, 2, 3};
 138
 139 struct ad7293_state {
 140         struct spi_device *spi;
 141         /* Protect against concurrent accesses to the device, page selection and data content */
 142         struct mutex lock;
 143         struct gpio_desc *gpio_reset;
 144         struct regulator *reg_avdd;
 145         struct regulator *reg_vdrive;
 146         u8 page_select;
 147         u8 data[3] __aligned(IIO_DMA_MINALIGN);
 148 };
 149
 150 static int ad7293_page_select(struct ad7293_state *st, unsigned int reg)
 151 {
 152         int ret;
 153
 154         if (st->page_select != FIELD_GET(AD7293_PAGE_ADDR_MSK, reg)) {
 155                 st->data[0] = FIELD_GET(AD7293_REG_ADDR_MSK, AD7293_REG_PAGE_SELECT);
 156                 st->data[1] = FIELD_GET(AD7293_PAGE_ADDR_MSK, reg);
 157
 158                 ret = spi_write(st->spi, &st->data[0], 2);
 159                 if (ret)
 160                         return ret;
 161
 162                 st->page_select = FIELD_GET(AD7293_PAGE_ADDR_MSK, reg);
 163         }
 164
 165         return 0;
 166 }
 167
 168 static int __ad7293_spi_read(struct ad7293_state *st, unsigned int reg,
 169                              u16 *val)
 170 {
 171         int ret;
 172         unsigned int length;
 173         struct spi_transfer t = {0};
 174
 175         length = FIELD_GET(AD7293_TRANSF_LEN_MSK, reg);
 176
 177         ret = ad7293_page_select(st, reg);
 178         if (ret)
 179                 return ret;
 180
 181         st->data[0] = AD7293_READ | FIELD_GET(AD7293_REG_ADDR_MSK, reg);
 182         st->data[1] = 0x0;
 183         st->data[2] = 0x0;
 184
 185         t.tx_buf = &st->data[0];
 186         t.rx_buf = &st->data[0];
 187         t.len = length + 1;
 188
 189         ret = spi_sync_transfer(st->spi, &t, 1);
 190         if (ret)
 191                 return ret;
 192
 193         if (length == 1)
 194                 *val = st->data[1];
 195         else
 196                 *val = get_unaligned_be16(&st->data[1]);
 197
 198         return 0;
 199 }
 200
 201 static int ad7293_spi_read(struct ad7293_state *st, unsigned int reg,
 202                            u16 *val)
 203 {
 204         int ret;
 205
 206         mutex_lock(&st->lock);
 207         ret = __ad7293_spi_read(st, reg, val);
 208         mutex_unlock(&st->lock);
 209
 210         return ret;
 211 }
 212
 213 static int __ad7293_spi_write(struct ad7293_state *st, unsigned int reg,
 214                               u16 val)
 215 {
 216         int ret;
 217         unsigned int length;
 218
 219         length = FIELD_GET(AD7293_TRANSF_LEN_MSK, reg);
 220
 221         ret = ad7293_page_select(st, reg);
 222         if (ret)
 223                 return ret;
 224
 225         st->data[0] = FIELD_GET(AD7293_REG_ADDR_MSK, reg);
 226
 227         if (length == 1)
 228                 st->data[1] = val;
 229         else
 230                 put_unaligned_be16(val, &st->data[1]);
 231
 232         return spi_write(st->spi, &st->data[0], length + 1);
 233 }
 234
 235 static int ad7293_spi_write(struct ad7293_state *st, unsigned int reg,
 236                             u16 val)
 237 {
 238         int ret;
 239
 240         mutex_lock(&st->lock);
 241         ret = __ad7293_spi_write(st, reg, val);
 242         mutex_unlock(&st->lock);
 243
 244         return ret;
 245 }
 246
 247 static int __ad7293_spi_update_bits(struct ad7293_state *st, unsigned int reg,
 248                                     u16 mask, u16 val)
 249 {
 250         int ret;
 251         u16 data, temp;
 252
 253         ret = __ad7293_spi_read(st, reg, &data);
 254         if (ret)
 255                 return ret;
 256
 257         temp = (data & ~mask) | (val & mask);
 258
 259         return __ad7293_spi_write(st, reg, temp);
 260 }
 261
 262 static int ad7293_spi_update_bits(struct ad7293_state *st, unsigned int reg,
 263                                   u16 mask, u16 val)
 264 {
 265         int ret;
 266
 267         mutex_lock(&st->lock);
 268         ret = __ad7293_spi_update_bits(st, reg, mask, val);
 269         mutex_unlock(&st->lock);
 270
 271         return ret;
 272 }
 273
 274 static int ad7293_adc_get_scale(struct ad7293_state *st, unsigned int ch,
 275                                 u16 *range)
 276 {
 277         int ret;
 278         u16 data;
 279
 280         mutex_lock(&st->lock);
 281
 282         ret = __ad7293_spi_read(st, AD7293_REG_VINX_RANGE1, &data);
 283         if (ret)
 284                 goto exit;
 285
 286         *range = AD7293_REG_VINX_RANGE_GET_CH_MSK(data, ch);
 287
 288         ret = __ad7293_spi_read(st, AD7293_REG_VINX_RANGE0, &data);
 289         if (ret)
 290                 goto exit;
 291
 292         *range |= AD7293_REG_VINX_RANGE_GET_CH_MSK(data, ch) << 1;
 293
 294 exit:
 295         mutex_unlock(&st->lock);
 296
 297         return ret;
 298 }
 299
 300 static int ad7293_adc_set_scale(struct ad7293_state *st, unsigned int ch,
 301                                 u16 range)
 302 {
 303         int ret;
 304         unsigned int ch_msk = BIT(ch);
 305
 306         mutex_lock(&st->lock);
 307         ret = __ad7293_spi_update_bits(st, AD7293_REG_VINX_RANGE1, ch_msk,
 308                                        AD7293_REG_VINX_RANGE_SET_CH_MSK(range, ch));
 309         if (ret)
 310                 goto exit;
 311
 312         ret = __ad7293_spi_update_bits(st, AD7293_REG_VINX_RANGE0, ch_msk,
 313                                        AD7293_REG_VINX_RANGE_SET_CH_MSK((range >> 1), ch));
 314
 315 exit:
 316         mutex_unlock(&st->lock);
 317
 318         return ret;
 319 }
 320
 321 static int ad7293_get_offset(struct ad7293_state *st, unsigned int ch,
 322                              u16 *offset)
 323 {
 324         if (ch < AD7293_TSENSE_MIN_OFFSET_CH)
 325                 return ad7293_spi_read(st, AD7293_REG_VIN0_OFFSET + ch, offset);
 326         else if (ch < AD7293_ISENSE_MIN_OFFSET_CH)
 327                 return ad7293_spi_read(st, AD7293_REG_TSENSE_INT_OFFSET + (ch - 4), offset);
 328         else if (ch < AD7293_VOUT_MIN_OFFSET_CH)
 329                 return ad7293_spi_read(st, AD7293_REG_ISENSE0_OFFSET + (ch - 7), offset);
 330         else if (ch <= AD7293_VOUT_MAX_OFFSET_CH)
 331                 return ad7293_spi_read(st, AD7293_REG_UNI_VOUT0_OFFSET + (ch - 11), offset);
 332
 333         return -EINVAL;
 334 }
 335
 336 static int ad7293_set_offset(struct ad7293_state *st, unsigned int ch,
 337                              u16 offset)
 338 {
 339         if (ch < AD7293_TSENSE_MIN_OFFSET_CH)
 340                 return ad7293_spi_write(st, AD7293_REG_VIN0_OFFSET + ch,
 341                                         offset);
 342         else if (ch < AD7293_ISENSE_MIN_OFFSET_CH)
 343                 return ad7293_spi_write(st,
 344                                         AD7293_REG_TSENSE_INT_OFFSET +
 345                                         (ch - AD7293_TSENSE_MIN_OFFSET_CH),
 346                                         offset);
 347         else if (ch < AD7293_VOUT_MIN_OFFSET_CH)
 348                 return ad7293_spi_write(st,
 349                                         AD7293_REG_ISENSE0_OFFSET +
 350                                         (ch - AD7293_ISENSE_MIN_OFFSET_CH),
 351                                         offset);
 352         else if (ch <= AD7293_VOUT_MAX_OFFSET_CH)
 353                 return ad7293_spi_update_bits(st,
 354                                               AD7293_REG_UNI_VOUT0_OFFSET +
 355                                               (ch - AD7293_VOUT_MIN_OFFSET_CH),
 356                                               AD7293_REG_VOUT_OFFSET_MSK,
 357                                               FIELD_PREP(AD7293_REG_VOUT_OFFSET_MSK, offset));
 358
 359         return -EINVAL;
 360 }
 361
 362 static int ad7293_isense_set_scale(struct ad7293_state *st, unsigned int ch,
 363                                    u16 gain)
 364 {
 365         unsigned int ch_msk = (0xf << (4 * ch));
 366
 367         return ad7293_spi_update_bits(st, AD7293_REG_ISENSE_GAIN, ch_msk,
 368                                       gain << (4 * ch));
 369 }
 370
 371 static int ad7293_isense_get_scale(struct ad7293_state *st, unsigned int ch,
 372                                    u16 *gain)
 373 {
 374         int ret;
 375
 376         ret = ad7293_spi_read(st, AD7293_REG_ISENSE_GAIN, gain);
 377         if (ret)
 378                 return ret;
 379
 380         *gain = (*gain >> (4 * ch)) & 0xf;
 381
 382         return ret;
 383 }
 384
 385 static int ad7293_dac_write_raw(struct ad7293_state *st, unsigned int ch,
 386                                 u16 raw)
 387 {
 388         int ret;
 389
 390         mutex_lock(&st->lock);
 391
 392         ret = __ad7293_spi_update_bits(st, AD7293_REG_DAC_EN, BIT(ch), BIT(ch));
 393         if (ret)
 394                 goto exit;
 395
 396         ret =  __ad7293_spi_write(st, AD7293_REG_UNI_VOUT0 + ch,
 397                                   FIELD_PREP(AD7293_REG_DATA_RAW_MSK, raw));
 398
 399 exit:
 400         mutex_unlock(&st->lock);
 401
 402         return ret;
 403 }
 404
 405 static int ad7293_ch_read_raw(struct ad7293_state *st, enum ad7293_ch_type type,
 406                               unsigned int ch, u16 *raw)
 407 {
 408         int ret;
 409         unsigned int reg_wr, reg_rd, data_wr;
 410
 411         switch (type) {
 412         case AD7293_ADC_VINX:
 413                 reg_wr = AD7293_REG_VINX_SEQ;
 414                 reg_rd = AD7293_REG_VIN0 + ch;
 415                 data_wr = BIT(ch);
 416
 417                 break;
 418         case AD7293_ADC_TSENSE:
 419                 reg_wr = AD7293_REG_ISENSEX_TSENSEX_SEQ;
 420                 reg_rd = AD7293_REG_TSENSE_INT + ch;
 421                 data_wr = BIT(ch);
 422
 423                 break;
 424         case AD7293_ADC_ISENSE:
 425                 reg_wr = AD7293_REG_ISENSEX_TSENSEX_SEQ;
 426                 reg_rd = AD7293_REG_ISENSE_0 + ch;
 427                 data_wr = BIT(ch) << 8;
 428
 429                 break;
 430         case AD7293_DAC:
 431                 reg_rd = AD7293_REG_UNI_VOUT0 + ch;
 432
 433                 break;
 434         default:
 435                 return -EINVAL;
 436         }
 437
 438         mutex_lock(&st->lock);
 439
 440         if (type != AD7293_DAC) {
 441                 if (type == AD7293_ADC_TSENSE) {
 442                         ret = __ad7293_spi_write(st, AD7293_REG_TSENSE_BG_EN,
 443                                                  BIT(ch));
 444                         if (ret)
 445                                 goto exit;
 446
 447                         usleep_range(9000, 9900);
 448                 } else if (type == AD7293_ADC_ISENSE) {
 449                         ret = __ad7293_spi_write(st, AD7293_REG_ISENSE_BG_EN,
 450                                                  BIT(ch));
 451                         if (ret)
 452                                 goto exit;
 453
 454                         usleep_range(2000, 7000);
 455                 }
 456
 457                 ret = __ad7293_spi_write(st, reg_wr, data_wr);
 458                 if (ret)
 459                         goto exit;
 460
 461                 ret = __ad7293_spi_write(st, AD7293_REG_CONV_CMD, 0x82);
 462                 if (ret)
 463                         goto exit;
 464         }
 465
 466         ret = __ad7293_spi_read(st, reg_rd, raw);
 467
 468         *raw = FIELD_GET(AD7293_REG_DATA_RAW_MSK, *raw);
 469
 470 exit:
 471         mutex_unlock(&st->lock);
 472
 473         return ret;
 474 }
 475
 476 static int ad7293_read_raw(struct iio_dev *indio_dev,
 477                            struct iio_chan_spec const *chan,
 478                            int *val, int *val2, long info)
 479 {
 480         struct ad7293_state *st = iio_priv(indio_dev);
 481         int ret;
 482         u16 data;
 483
 484         switch (info) {
 485         case IIO_CHAN_INFO_RAW:
 486                 switch (chan->type) {
 487                 case IIO_VOLTAGE:
 488                         if (chan->output)
 489                                 ret =  ad7293_ch_read_raw(st, AD7293_DAC,
 490                                                           chan->channel, &data);
 491                         else
 492                                 ret =  ad7293_ch_read_raw(st, AD7293_ADC_VINX,
 493                                                           chan->channel, &data);
 494
 495                         break;
 496                 case IIO_CURRENT:
 497                         ret =  ad7293_ch_read_raw(st, AD7293_ADC_ISENSE,
 498                                                   chan->channel, &data);
 499
 500                         break;
 501                 case IIO_TEMP:
 502                         ret =  ad7293_ch_read_raw(st, AD7293_ADC_TSENSE,
 503                                                   chan->channel, &data);
 504
 505                         break;
 506                 default:
 507                         return -EINVAL;
 508                 }
 509
 510                 if (ret)
 511                         return ret;
 512
 513                 *val = data;
 514
 515                 return IIO_VAL_INT;
 516         case IIO_CHAN_INFO_OFFSET:
 517                 switch (chan->type) {
 518                 case IIO_VOLTAGE:
 519                         if (chan->output) {
 520                                 ret = ad7293_get_offset(st,
 521                                                         chan->channel + AD7293_VOUT_MIN_OFFSET_CH,
 522                                                         &data);
 523
 524                                 data = FIELD_GET(AD7293_REG_VOUT_OFFSET_MSK, data);
 525                         } else {
 526                                 ret = ad7293_get_offset(st, chan->channel, &data);
 527                         }
 528
 529                         break;
 530                 case IIO_CURRENT:
 531                         ret = ad7293_get_offset(st,
 532                                                 chan->channel + AD7293_ISENSE_MIN_OFFSET_CH,
 533                                                 &data);
 534
 535                         break;
 536                 case IIO_TEMP:
 537                         ret = ad7293_get_offset(st,
 538                                                 chan->channel + AD7293_TSENSE_MIN_OFFSET_CH,
 539                                                 &data);
 540
 541                         break;
 542                 default:
 543                         return -EINVAL;
 544                 }
 545                 if (ret)
 546                         return ret;
 547
 548                 *val = data;
 549
 550                 return IIO_VAL_INT;
 551         case IIO_CHAN_INFO_SCALE:
 552                 switch (chan->type) {
 553                 case IIO_VOLTAGE:
 554                         ret = ad7293_adc_get_scale(st, chan->channel, &data);
 555                         if (ret)
 556                                 return ret;
 557
 558                         *val = data;
 559
 560                         return IIO_VAL_INT;
 561                 case IIO_CURRENT:
 562                         ret = ad7293_isense_get_scale(st, chan->channel, &data);
 563                         if (ret)
 564                                 return ret;
 565
 566                         *val = data;
 567
 568                         return IIO_VAL_INT;
 569                 case IIO_TEMP:
 570                         *val = 1;
 571                         *val2 = 8;
 572
 573                         return IIO_VAL_FRACTIONAL;
 574                 default:
 575                         return -EINVAL;
 576                 }
 577         default:
 578                 return -EINVAL;
 579         }
 580 }
 581
 582 static int ad7293_write_raw(struct iio_dev *indio_dev,
 583                             struct iio_chan_spec const *chan,
 584                             int val, int val2, long info)
 585 {
 586         struct ad7293_state *st = iio_priv(indio_dev);
 587
 588         switch (info) {
 589         case IIO_CHAN_INFO_RAW:
 590                 switch (chan->type) {
 591                 case IIO_VOLTAGE:
 592                         if (!chan->output)
 593                                 return -EINVAL;
 594
 595                         return ad7293_dac_write_raw(st, chan->channel, val);
 596                 default:
 597                         return -EINVAL;
 598                 }
 599         case IIO_CHAN_INFO_OFFSET:
 600                 switch (chan->type) {
 601                 case IIO_VOLTAGE:
 602                         if (chan->output)
 603                                 return ad7293_set_offset(st,
 604                                                          chan->channel +
 605                                                          AD7293_VOUT_MIN_OFFSET_CH,
 606                                                          val);
 607                         else
 608                                 return ad7293_set_offset(st, chan->channel, val);
 609                 case IIO_CURRENT:
 610                         return ad7293_set_offset(st,
 611                                                  chan->channel +
 612                                                  AD7293_ISENSE_MIN_OFFSET_CH,
 613                                                  val);
 614                 case IIO_TEMP:
 615                         return ad7293_set_offset(st,
 616                                                  chan->channel +
 617                                                  AD7293_TSENSE_MIN_OFFSET_CH,
 618                                                  val);
 619                 default:
 620                         return -EINVAL;
 621                 }
 622         case IIO_CHAN_INFO_SCALE:
 623                 switch (chan->type) {
 624                 case IIO_VOLTAGE:
 625                         return ad7293_adc_set_scale(st, chan->channel, val);
 626                 case IIO_CURRENT:
 627                         return ad7293_isense_set_scale(st, chan->channel, val);
 628                 default:
 629                         return -EINVAL;
 630                 }
 631         default:
 632                 return -EINVAL;
 633         }
 634 }
 635
 636 static int ad7293_reg_access(struct iio_dev *indio_dev,
 637                              unsigned int reg,
 638                              unsigned int write_val,
 639                              unsigned int *read_val)
 640 {
 641         struct ad7293_state *st = iio_priv(indio_dev);
 642         int ret;
 643
 644         if (read_val) {
 645                 u16 temp;
 646                 ret = ad7293_spi_read(st, reg, &temp);
 647                 *read_val = temp;
 648         } else {
 649                 ret = ad7293_spi_write(st, reg, (u16)write_val);
 650         }
 651
 652         return ret;
 653 }
 654
 655 static int ad7293_read_avail(struct iio_dev *indio_dev,
 656                              struct iio_chan_spec const *chan,
 657                              const int **vals, int *type, int *length,
 658                              long info)
 659 {
 660         switch (info) {
 661         case IIO_CHAN_INFO_OFFSET:
 662                 *vals = dac_offset_table;
 663                 *type = IIO_VAL_INT;
 664                 *length = ARRAY_SIZE(dac_offset_table);
 665
 666                 return IIO_AVAIL_LIST;
 667         case IIO_CHAN_INFO_SCALE:
 668                 *type = IIO_VAL_INT;
 669
 670                 switch (chan->type) {
 671                 case IIO_VOLTAGE:
 672                         *vals = adc_range_table;
 673                         *length = ARRAY_SIZE(adc_range_table);
 674                         return IIO_AVAIL_LIST;
 675                 case IIO_CURRENT:
 676                         *vals = isense_gain_table;
 677                         *length = ARRAY_SIZE(isense_gain_table);
 678                         return IIO_AVAIL_LIST;
 679                 default:
 680                         return -EINVAL;
 681                 }
 682         default:
 683                 return -EINVAL;
 684         }
 685 }
 686
 687 #define AD7293_CHAN_ADC(_channel) {                                     \
 688         .type = IIO_VOLTAGE,                                            \
 689         .output = 0,                                                    \
 690         .indexed = 1,                                                   \
 691         .channel = _channel,                                            \
 692         .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) |                  \
 693                               BIT(IIO_CHAN_INFO_SCALE) |                \
 694                               BIT(IIO_CHAN_INFO_OFFSET),                \
 695         .info_mask_shared_by_type_available = BIT(IIO_CHAN_INFO_SCALE)  \
 696 }
 697
 698 #define AD7293_CHAN_DAC(_channel) {                                     \
 699         .type = IIO_VOLTAGE,                                            \
 700         .output = 1,                                                    \
 701         .indexed = 1,                                                   \
 702         .channel = _channel,                                            \
 703         .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) |                  \
 704                               BIT(IIO_CHAN_INFO_OFFSET),                \
 705         .info_mask_shared_by_type_available = BIT(IIO_CHAN_INFO_OFFSET) \
 706 }
 707
 708 #define AD7293_CHAN_ISENSE(_channel) {                                  \
 709         .type = IIO_CURRENT,                                            \
 710         .output = 0,                                                    \
 711         .indexed = 1,                                                   \
 712         .channel = _channel,                                            \
 713         .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) |                  \
 714                               BIT(IIO_CHAN_INFO_OFFSET) |               \
 715                               BIT(IIO_CHAN_INFO_SCALE),                 \
 716         .info_mask_shared_by_type_available = BIT(IIO_CHAN_INFO_SCALE)  \
 717 }
 718
 719 #define AD7293_CHAN_TEMP(_channel) {                                    \
 720         .type = IIO_TEMP,                                               \
 721         .output = 0,                                                    \
 722         .indexed = 1,                                                   \
 723         .channel = _channel,                                            \
 724         .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) |                  \
 725                               BIT(IIO_CHAN_INFO_OFFSET),                \
 726         .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE)            \
 727 }
 728
 729 static const struct iio_chan_spec ad7293_channels[] = {
 730         AD7293_CHAN_ADC(0),
 731         AD7293_CHAN_ADC(1),
 732         AD7293_CHAN_ADC(2),
 733         AD7293_CHAN_ADC(3),
 734         AD7293_CHAN_ISENSE(0),
 735         AD7293_CHAN_ISENSE(1),
 736         AD7293_CHAN_ISENSE(2),
 737         AD7293_CHAN_ISENSE(3),
 738         AD7293_CHAN_TEMP(0),
 739         AD7293_CHAN_TEMP(1),
 740         AD7293_CHAN_TEMP(2),
 741         AD7293_CHAN_DAC(0),
 742         AD7293_CHAN_DAC(1),
 743         AD7293_CHAN_DAC(2),
 744         AD7293_CHAN_DAC(3),
 745         AD7293_CHAN_DAC(4),
 746         AD7293_CHAN_DAC(5),
 747         AD7293_CHAN_DAC(6),
 748         AD7293_CHAN_DAC(7)
 749 };
 750
 751 static int ad7293_soft_reset(struct ad7293_state *st)
 752 {
 753         int ret;
 754
 755         ret = __ad7293_spi_write(st, AD7293_REG_SOFT_RESET, 0x7293);
 756         if (ret)
 757                 return ret;
 758
 759         return __ad7293_spi_write(st, AD7293_REG_SOFT_RESET, 0x0000);
 760 }
 761
 762 static int ad7293_reset(struct ad7293_state *st)
 763 {
 764         if (st->gpio_reset) {
 765                 gpiod_set_value(st->gpio_reset, 0);
 766                 usleep_range(100, 1000);
 767                 gpiod_set_value(st->gpio_reset, 1);
 768                 usleep_range(100, 1000);
 769
 770                 return 0;
 771         }
 772
 773         /* Perform a software reset */
 774         return ad7293_soft_reset(st);
 775 }
 776
 777 static int ad7293_properties_parse(struct ad7293_state *st)
 778 {
 779         struct spi_device *spi = st->spi;
 780
 781         st->gpio_reset = devm_gpiod_get_optional(&st->spi->dev, "reset",
 782                                                  GPIOD_OUT_HIGH);
 783         if (IS_ERR(st->gpio_reset))
 784                 return dev_err_probe(&spi->dev, PTR_ERR(st->gpio_reset),
 785                                      "failed to get the reset GPIO\n");
 786
 787         st->reg_avdd = devm_regulator_get(&spi->dev, "avdd");
 788         if (IS_ERR(st->reg_avdd))
 789                 return dev_err_probe(&spi->dev, PTR_ERR(st->reg_avdd),
 790                                      "failed to get the AVDD voltage\n");
 791
 792         st->reg_vdrive = devm_regulator_get(&spi->dev, "vdrive");
 793         if (IS_ERR(st->reg_vdrive))
 794                 return dev_err_probe(&spi->dev, PTR_ERR(st->reg_vdrive),
 795                                      "failed to get the VDRIVE voltage\n");
 796
 797         return 0;
 798 }
 799
 800 static void ad7293_reg_disable(void *data)
 801 {
 802         regulator_disable(data);
 803 }
 804
 805 static int ad7293_init(struct ad7293_state *st)
 806 {
 807         int ret;
 808         u16 chip_id;
 809         struct spi_device *spi = st->spi;
 810
 811         ret = ad7293_properties_parse(st);
 812         if (ret)
 813                 return ret;
 814
 815         ret = ad7293_reset(st);
 816         if (ret)
 817                 return ret;
 818
 819         ret = regulator_enable(st->reg_avdd);
 820         if (ret) {
 821                 dev_err(&spi->dev,
 822                         "Failed to enable specified AVDD Voltage!\n");
 823                 return ret;
 824         }
 825
 826         ret = devm_add_action_or_reset(&spi->dev, ad7293_reg_disable,
 827                                        st->reg_avdd);
 828         if (ret)
 829                 return ret;
 830
 831         ret = regulator_enable(st->reg_vdrive);
 832         if (ret) {
 833                 dev_err(&spi->dev,
 834                         "Failed to enable specified VDRIVE Voltage!\n");
 835                 return ret;
 836         }
 837
 838         ret = devm_add_action_or_reset(&spi->dev, ad7293_reg_disable,
 839                                        st->reg_vdrive);
 840         if (ret)
 841                 return ret;
 842
 843         ret = regulator_get_voltage(st->reg_avdd);
 844         if (ret < 0) {
 845                 dev_err(&spi->dev, "Failed to read avdd regulator: %d\n", ret);
 846                 return ret;
 847         }
 848
 849         if (ret > 5500000 || ret < 4500000)
 850                 return -EINVAL;
 851
 852         ret = regulator_get_voltage(st->reg_vdrive);
 853         if (ret < 0) {
 854                 dev_err(&spi->dev,
 855                         "Failed to read vdrive regulator: %d\n", ret);
 856                 return ret;
 857         }
 858         if (ret > 5500000 || ret < 1700000)
 859                 return -EINVAL;
 860
 861         /* Check Chip ID */
 862         ret = __ad7293_spi_read(st, AD7293_REG_DEVICE_ID, &chip_id);
 863         if (ret)
 864                 return ret;
 865
 866         if (chip_id != AD7293_CHIP_ID) {
 867                 dev_err(&spi->dev, "Invalid Chip ID.\n");
 868                 return -EINVAL;
 869         }
 870
 871         return 0;
 872 }
 873
 874 static const struct iio_info ad7293_info = {
 875         .read_raw = ad7293_read_raw,
 876         .write_raw = ad7293_write_raw,
 877         .read_avail = &ad7293_read_avail,
 878         .debugfs_reg_access = &ad7293_reg_access,
 879 };
 880
 881 static int ad7293_probe(struct spi_device *spi)
 882 {
 883         struct iio_dev *indio_dev;
 884         struct ad7293_state *st;
 885         int ret;
 886
 887         indio_dev = devm_iio_device_alloc(&spi->dev, sizeof(*st));
 888         if (!indio_dev)
 889                 return -ENOMEM;
 890
 891         st = iio_priv(indio_dev);
 892
 893         indio_dev->info = &ad7293_info;
 894         indio_dev->name = "ad7293";
 895         indio_dev->channels = ad7293_channels;
 896         indio_dev->num_channels = ARRAY_SIZE(ad7293_channels);
 897
 898         st->spi = spi;
 899         st->page_select = 0;
 900
 901         mutex_init(&st->lock);
 902
 903         ret = ad7293_init(st);
 904         if (ret)
 905                 return ret;
 906
 907         return devm_iio_device_register(&spi->dev, indio_dev);
 908 }
 909
 910 static const struct spi_device_id ad7293_id[] = {
 911         { "ad7293", 0 },
 912         {}
 913 };
 914 MODULE_DEVICE_TABLE(spi, ad7293_id);
 915
 916 static const struct of_device_id ad7293_of_match[] = {
 917         { .compatible = "adi,ad7293" },
 918         {}
 919 };
 920 MODULE_DEVICE_TABLE(of, ad7293_of_match);
 921
 922 static struct spi_driver ad7293_driver = {
 923         .driver = {
 924                 .name = "ad7293",
 925                 .of_match_table = ad7293_of_match,
 926         },
 927         .probe = ad7293_probe,
 928         .id_table = ad7293_id,
 929 };
 930 module_spi_driver(ad7293_driver);
 931
 932 MODULE_AUTHOR("Antoniu Miclaus <[email protected]");
 933 MODULE_DESCRIPTION("Analog Devices AD7293");
 934 MODULE_LICENSE("GPL v2");