1 // SPDX-License-Identifier: GPL-2.0-only
4 * Copyright (C) 2014 Rose Technology
8 * Driver for following ADC chips from Microchip Technology's:
29 * Datasheet can be found here:
30 * https://ww1.microchip.com/downloads/en/DeviceDoc/21293C.pdf mcp3001
31 * https://ww1.microchip.com/downloads/en/DeviceDoc/21294E.pdf mcp3002
32 * https://ww1.microchip.com/downloads/en/DeviceDoc/21295d.pdf mcp3004/08
33 * http://ww1.microchip.com/downloads/en/DeviceDoc/21290D.pdf mcp3201
34 * http://ww1.microchip.com/downloads/en/DeviceDoc/21034D.pdf mcp3202
35 * http://ww1.microchip.com/downloads/en/DeviceDoc/21298c.pdf mcp3204/08
36 * https://ww1.microchip.com/downloads/en/DeviceDoc/21700E.pdf mcp3301
37 * http://ww1.microchip.com/downloads/en/DeviceDoc/21950D.pdf mcp3550/1/3
40 #include <linux/err.h>
41 #include <linux/delay.h>
42 #include <linux/spi/spi.h>
43 #include <linux/module.h>
44 #include <linux/mod_devicetable.h>
45 #include <linux/iio/iio.h>
46 #include <linux/regulator/consumer.h>
64 struct mcp320x_chip_info {
65 const struct iio_chan_spec *channels;
66 unsigned int num_channels;
67 unsigned int resolution;
68 unsigned int conv_time; /* usec */
72 * struct mcp320x - Microchip SPI ADC instance
73 * @spi: SPI slave (parent of the IIO device)
74 * @msg: SPI message to select a channel and receive a value from the ADC
75 * @transfer: SPI transfers used by @msg
76 * @start_conv_msg: SPI message to start a conversion by briefly asserting CS
77 * @start_conv_transfer: SPI transfer used by @start_conv_msg
78 * @reg: regulator generating Vref
79 * @lock: protects read sequences
80 * @chip_info: ADC properties
81 * @tx_buf: buffer for @transfer[0] (not used on single-channel converters)
82 * @rx_buf: buffer for @transfer[1]
85 struct spi_device *spi;
86 struct spi_message msg;
87 struct spi_transfer transfer[2];
88 struct spi_message start_conv_msg;
89 struct spi_transfer start_conv_transfer;
91 struct regulator *reg;
93 const struct mcp320x_chip_info *chip_info;
95 u8 tx_buf __aligned(IIO_DMA_MINALIGN);
99 static int mcp320x_channel_to_tx_data(int device_index,
100 const unsigned int channel, bool differential)
104 switch (device_index) {
107 return ((start_bit << 4) | (!differential << 3) |
113 return ((start_bit << 6) | (!differential << 5) |
120 static int mcp320x_adc_conversion(struct mcp320x *adc, u8 channel,
121 bool differential, int device_index, int *val)
125 if (adc->chip_info->conv_time) {
126 ret = spi_sync(adc->spi, &adc->start_conv_msg);
130 usleep_range(adc->chip_info->conv_time,
131 adc->chip_info->conv_time + 100);
134 memset(&adc->rx_buf, 0, sizeof(adc->rx_buf));
135 if (adc->chip_info->num_channels > 1)
136 adc->tx_buf = mcp320x_channel_to_tx_data(device_index, channel,
139 ret = spi_sync(adc->spi, &adc->msg);
143 switch (device_index) {
145 *val = (adc->rx_buf[0] << 5 | adc->rx_buf[1] >> 3);
150 *val = (adc->rx_buf[0] << 2 | adc->rx_buf[1] >> 6);
153 *val = (adc->rx_buf[0] << 7 | adc->rx_buf[1] >> 1);
158 *val = (adc->rx_buf[0] << 4 | adc->rx_buf[1] >> 4);
161 *val = sign_extend32((adc->rx_buf[0] & 0x1f) << 8
162 | adc->rx_buf[1], 12);
168 u32 raw = be32_to_cpup((__be32 *)adc->rx_buf);
170 if (!(adc->spi->mode & SPI_CPOL))
171 raw <<= 1; /* strip Data Ready bit in SPI mode 0,0 */
174 * If the input is within -vref and vref, bit 21 is the sign.
175 * Up to 12% overrange or underrange are allowed, in which case
176 * bit 23 is the sign and bit 0 to 21 is the value.
179 if (raw & BIT(22) && raw & BIT(23))
180 return -EIO; /* cannot have overrange AND underrange */
181 else if (raw & BIT(22))
182 raw &= ~BIT(22); /* overrange */
183 else if (raw & BIT(23) || raw & BIT(21))
184 raw |= GENMASK(31, 22); /* underrange or negative */
194 static int mcp320x_read_raw(struct iio_dev *indio_dev,
195 struct iio_chan_spec const *channel, int *val,
196 int *val2, long mask)
198 struct mcp320x *adc = iio_priv(indio_dev);
200 int device_index = 0;
202 mutex_lock(&adc->lock);
204 device_index = spi_get_device_id(adc->spi)->driver_data;
207 case IIO_CHAN_INFO_RAW:
208 ret = mcp320x_adc_conversion(adc, channel->address,
209 channel->differential, device_index, val);
216 case IIO_CHAN_INFO_SCALE:
217 ret = regulator_get_voltage(adc->reg);
221 /* convert regulator output voltage to mV */
223 *val2 = adc->chip_info->resolution;
224 ret = IIO_VAL_FRACTIONAL_LOG2;
229 mutex_unlock(&adc->lock);
234 #define MCP320X_VOLTAGE_CHANNEL(num) \
236 .type = IIO_VOLTAGE, \
240 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \
241 .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE) \
244 #define MCP320X_VOLTAGE_CHANNEL_DIFF(chan1, chan2) \
246 .type = IIO_VOLTAGE, \
248 .channel = (chan1), \
249 .channel2 = (chan2), \
250 .address = (chan1), \
252 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \
253 .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE) \
256 static const struct iio_chan_spec mcp3201_channels[] = {
257 MCP320X_VOLTAGE_CHANNEL_DIFF(0, 1),
260 static const struct iio_chan_spec mcp3202_channels[] = {
261 MCP320X_VOLTAGE_CHANNEL(0),
262 MCP320X_VOLTAGE_CHANNEL(1),
263 MCP320X_VOLTAGE_CHANNEL_DIFF(0, 1),
264 MCP320X_VOLTAGE_CHANNEL_DIFF(1, 0),
267 static const struct iio_chan_spec mcp3204_channels[] = {
268 MCP320X_VOLTAGE_CHANNEL(0),
269 MCP320X_VOLTAGE_CHANNEL(1),
270 MCP320X_VOLTAGE_CHANNEL(2),
271 MCP320X_VOLTAGE_CHANNEL(3),
272 MCP320X_VOLTAGE_CHANNEL_DIFF(0, 1),
273 MCP320X_VOLTAGE_CHANNEL_DIFF(1, 0),
274 MCP320X_VOLTAGE_CHANNEL_DIFF(2, 3),
275 MCP320X_VOLTAGE_CHANNEL_DIFF(3, 2),
278 static const struct iio_chan_spec mcp3208_channels[] = {
279 MCP320X_VOLTAGE_CHANNEL(0),
280 MCP320X_VOLTAGE_CHANNEL(1),
281 MCP320X_VOLTAGE_CHANNEL(2),
282 MCP320X_VOLTAGE_CHANNEL(3),
283 MCP320X_VOLTAGE_CHANNEL(4),
284 MCP320X_VOLTAGE_CHANNEL(5),
285 MCP320X_VOLTAGE_CHANNEL(6),
286 MCP320X_VOLTAGE_CHANNEL(7),
287 MCP320X_VOLTAGE_CHANNEL_DIFF(0, 1),
288 MCP320X_VOLTAGE_CHANNEL_DIFF(1, 0),
289 MCP320X_VOLTAGE_CHANNEL_DIFF(2, 3),
290 MCP320X_VOLTAGE_CHANNEL_DIFF(3, 2),
291 MCP320X_VOLTAGE_CHANNEL_DIFF(4, 5),
292 MCP320X_VOLTAGE_CHANNEL_DIFF(5, 4),
293 MCP320X_VOLTAGE_CHANNEL_DIFF(6, 7),
294 MCP320X_VOLTAGE_CHANNEL_DIFF(7, 6),
297 static const struct iio_info mcp320x_info = {
298 .read_raw = mcp320x_read_raw,
301 static const struct mcp320x_chip_info mcp320x_chip_infos[] = {
303 .channels = mcp3201_channels,
304 .num_channels = ARRAY_SIZE(mcp3201_channels),
308 .channels = mcp3202_channels,
309 .num_channels = ARRAY_SIZE(mcp3202_channels),
313 .channels = mcp3204_channels,
314 .num_channels = ARRAY_SIZE(mcp3204_channels),
318 .channels = mcp3208_channels,
319 .num_channels = ARRAY_SIZE(mcp3208_channels),
323 .channels = mcp3201_channels,
324 .num_channels = ARRAY_SIZE(mcp3201_channels),
328 .channels = mcp3202_channels,
329 .num_channels = ARRAY_SIZE(mcp3202_channels),
333 .channels = mcp3204_channels,
334 .num_channels = ARRAY_SIZE(mcp3204_channels),
338 .channels = mcp3208_channels,
339 .num_channels = ARRAY_SIZE(mcp3208_channels),
343 .channels = mcp3201_channels,
344 .num_channels = ARRAY_SIZE(mcp3201_channels),
348 .channels = mcp3201_channels,
349 .num_channels = ARRAY_SIZE(mcp3201_channels),
351 /* 2% max deviation + 144 clock periods to exit shutdown */
352 .conv_time = 80000 * 1.02 + 144000 / 102.4,
355 .channels = mcp3201_channels,
356 .num_channels = ARRAY_SIZE(mcp3201_channels),
358 .conv_time = 66670 * 1.02 + 144000 / 122.88,
361 .channels = mcp3201_channels,
362 .num_channels = ARRAY_SIZE(mcp3201_channels),
364 .conv_time = 73100 * 1.02 + 144000 / 112.64,
367 .channels = mcp3201_channels,
368 .num_channels = ARRAY_SIZE(mcp3201_channels),
370 .conv_time = 16670 * 1.02 + 144000 / 122.88,
374 static int mcp320x_probe(struct spi_device *spi)
376 struct iio_dev *indio_dev;
378 const struct mcp320x_chip_info *chip_info;
379 int ret, device_index;
381 indio_dev = devm_iio_device_alloc(&spi->dev, sizeof(*adc));
385 adc = iio_priv(indio_dev);
388 indio_dev->name = spi_get_device_id(spi)->name;
389 indio_dev->modes = INDIO_DIRECT_MODE;
390 indio_dev->info = &mcp320x_info;
391 spi_set_drvdata(spi, indio_dev);
393 device_index = spi_get_device_id(spi)->driver_data;
394 chip_info = &mcp320x_chip_infos[device_index];
395 indio_dev->channels = chip_info->channels;
396 indio_dev->num_channels = chip_info->num_channels;
398 adc->chip_info = chip_info;
400 adc->transfer[0].tx_buf = &adc->tx_buf;
401 adc->transfer[0].len = sizeof(adc->tx_buf);
402 adc->transfer[1].rx_buf = adc->rx_buf;
403 adc->transfer[1].len = DIV_ROUND_UP(chip_info->resolution, 8);
405 if (chip_info->num_channels == 1)
406 /* single-channel converters are rx only (no MOSI pin) */
407 spi_message_init_with_transfers(&adc->msg,
408 &adc->transfer[1], 1);
410 spi_message_init_with_transfers(&adc->msg, adc->transfer,
411 ARRAY_SIZE(adc->transfer));
413 switch (device_index) {
418 /* rx len increases from 24 to 25 bit in SPI mode 0,0 */
419 if (!(spi->mode & SPI_CPOL))
420 adc->transfer[1].len++;
422 /* conversions are started by asserting CS pin for 8 usec */
423 adc->start_conv_transfer.delay.value = 8;
424 adc->start_conv_transfer.delay.unit = SPI_DELAY_UNIT_USECS;
425 spi_message_init_with_transfers(&adc->start_conv_msg,
426 &adc->start_conv_transfer, 1);
429 * If CS was previously kept low (continuous conversion mode)
430 * and then changed to high, the chip is in shutdown.
431 * Sometimes it fails to wake from shutdown and clocks out
432 * only 0xffffff. The magic sequence of performing two
433 * conversions without delay between them resets the chip
434 * and ensures all subsequent conversions succeed.
436 mcp320x_adc_conversion(adc, 0, 1, device_index, &ret);
437 mcp320x_adc_conversion(adc, 0, 1, device_index, &ret);
440 adc->reg = devm_regulator_get(&spi->dev, "vref");
441 if (IS_ERR(adc->reg))
442 return PTR_ERR(adc->reg);
444 ret = regulator_enable(adc->reg);
448 mutex_init(&adc->lock);
450 ret = iio_device_register(indio_dev);
457 regulator_disable(adc->reg);
462 static void mcp320x_remove(struct spi_device *spi)
464 struct iio_dev *indio_dev = spi_get_drvdata(spi);
465 struct mcp320x *adc = iio_priv(indio_dev);
467 iio_device_unregister(indio_dev);
468 regulator_disable(adc->reg);
471 static const struct of_device_id mcp320x_dt_ids[] = {
472 /* NOTE: The use of compatibles with no vendor prefix is deprecated. */
473 { .compatible = "mcp3001" },
474 { .compatible = "mcp3002" },
475 { .compatible = "mcp3004" },
476 { .compatible = "mcp3008" },
477 { .compatible = "mcp3201" },
478 { .compatible = "mcp3202" },
479 { .compatible = "mcp3204" },
480 { .compatible = "mcp3208" },
481 { .compatible = "mcp3301" },
482 { .compatible = "microchip,mcp3001" },
483 { .compatible = "microchip,mcp3002" },
484 { .compatible = "microchip,mcp3004" },
485 { .compatible = "microchip,mcp3008" },
486 { .compatible = "microchip,mcp3201" },
487 { .compatible = "microchip,mcp3202" },
488 { .compatible = "microchip,mcp3204" },
489 { .compatible = "microchip,mcp3208" },
490 { .compatible = "microchip,mcp3301" },
491 { .compatible = "microchip,mcp3550-50" },
492 { .compatible = "microchip,mcp3550-60" },
493 { .compatible = "microchip,mcp3551" },
494 { .compatible = "microchip,mcp3553" },
497 MODULE_DEVICE_TABLE(of, mcp320x_dt_ids);
499 static const struct spi_device_id mcp320x_id[] = {
500 { "mcp3001", mcp3001 },
501 { "mcp3002", mcp3002 },
502 { "mcp3004", mcp3004 },
503 { "mcp3008", mcp3008 },
504 { "mcp3201", mcp3201 },
505 { "mcp3202", mcp3202 },
506 { "mcp3204", mcp3204 },
507 { "mcp3208", mcp3208 },
508 { "mcp3301", mcp3301 },
509 { "mcp3550-50", mcp3550_50 },
510 { "mcp3550-60", mcp3550_60 },
511 { "mcp3551", mcp3551 },
512 { "mcp3553", mcp3553 },
515 MODULE_DEVICE_TABLE(spi, mcp320x_id);
517 static struct spi_driver mcp320x_driver = {
520 .of_match_table = mcp320x_dt_ids,
522 .probe = mcp320x_probe,
523 .remove = mcp320x_remove,
524 .id_table = mcp320x_id,
526 module_spi_driver(mcp320x_driver);
529 MODULE_DESCRIPTION("Microchip Technology MCP3x01/02/04/08 and MCP3550/1/3");
530 MODULE_LICENSE("GPL v2");