drivers/iio/adc/imx93_adc.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * NXP i.MX93 ADC driver
   4  *
   5  * Copyright 2023 NXP
   6  */
   7
   8 #include <linux/bitfield.h>
   9 #include <linux/clk.h>
  10 #include <linux/completion.h>
  11 #include <linux/err.h>
  12 #include <linux/iio/iio.h>
  13 #include <linux/interrupt.h>
  14 #include <linux/io.h>
  15 #include <linux/iopoll.h>
  16 #include <linux/mod_devicetable.h>
  17 #include <linux/module.h>
  18 #include <linux/platform_device.h>
  19 #include <linux/pm_runtime.h>
  20 #include <linux/regulator/consumer.h>
  21
  22 #define IMX93_ADC_DRIVER_NAME   "imx93-adc"
  23
  24 /* Register map definition */
  25 #define IMX93_ADC_MCR           0x00
  26 #define IMX93_ADC_MSR           0x04
  27 #define IMX93_ADC_ISR           0x10
  28 #define IMX93_ADC_IMR           0x20
  29 #define IMX93_ADC_CIMR0         0x24
  30 #define IMX93_ADC_CTR0          0x94
  31 #define IMX93_ADC_NCMR0         0xA4
  32 #define IMX93_ADC_PCDR0         0x100
  33 #define IMX93_ADC_PCDR1         0x104
  34 #define IMX93_ADC_PCDR2         0x108
  35 #define IMX93_ADC_PCDR3         0x10c
  36 #define IMX93_ADC_PCDR4         0x110
  37 #define IMX93_ADC_PCDR5         0x114
  38 #define IMX93_ADC_PCDR6         0x118
  39 #define IMX93_ADC_PCDR7         0x11c
  40 #define IMX93_ADC_CALSTAT       0x39C
  41
  42 /* ADC bit shift */
  43 #define IMX93_ADC_MCR_MODE_MASK                 BIT(29)
  44 #define IMX93_ADC_MCR_NSTART_MASK               BIT(24)
  45 #define IMX93_ADC_MCR_CALSTART_MASK             BIT(14)
  46 #define IMX93_ADC_MCR_ADCLKSE_MASK              BIT(8)
  47 #define IMX93_ADC_MCR_PWDN_MASK                 BIT(0)
  48 #define IMX93_ADC_MSR_CALFAIL_MASK              BIT(30)
  49 #define IMX93_ADC_MSR_CALBUSY_MASK              BIT(29)
  50 #define IMX93_ADC_MSR_ADCSTATUS_MASK            GENMASK(2, 0)
  51 #define IMX93_ADC_ISR_ECH_MASK                  BIT(0)
  52 #define IMX93_ADC_ISR_EOC_MASK                  BIT(1)
  53 #define IMX93_ADC_ISR_EOC_ECH_MASK              (IMX93_ADC_ISR_EOC_MASK | \
  54                                                  IMX93_ADC_ISR_ECH_MASK)
  55 #define IMX93_ADC_IMR_JEOC_MASK                 BIT(3)
  56 #define IMX93_ADC_IMR_JECH_MASK                 BIT(2)
  57 #define IMX93_ADC_IMR_EOC_MASK                  BIT(1)
  58 #define IMX93_ADC_IMR_ECH_MASK                  BIT(0)
  59 #define IMX93_ADC_PCDR_CDATA_MASK               GENMASK(11, 0)
  60
  61 /* ADC status */
  62 #define IMX93_ADC_MSR_ADCSTATUS_IDLE                    0
  63 #define IMX93_ADC_MSR_ADCSTATUS_POWER_DOWN              1
  64 #define IMX93_ADC_MSR_ADCSTATUS_WAIT_STATE              2
  65 #define IMX93_ADC_MSR_ADCSTATUS_BUSY_IN_CALIBRATION     3
  66 #define IMX93_ADC_MSR_ADCSTATUS_SAMPLE                  4
  67 #define IMX93_ADC_MSR_ADCSTATUS_CONVERSION              6
  68
  69 #define IMX93_ADC_TIMEOUT               msecs_to_jiffies(100)
  70
  71 struct imx93_adc {
  72         struct device *dev;
  73         void __iomem *regs;
  74         struct clk *ipg_clk;
  75         int irq;
  76         struct regulator *vref;
  77         /* lock to protect against multiple access to the device */
  78         struct mutex lock;
  79         struct completion completion;
  80 };
  81
  82 #define IMX93_ADC_CHAN(_idx) {                                  \
  83         .type = IIO_VOLTAGE,                                    \
  84         .indexed = 1,                                           \
  85         .channel = (_idx),                                      \
  86         .info_mask_separate = BIT(IIO_CHAN_INFO_RAW),           \
  87         .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE) |  \
  88                                 BIT(IIO_CHAN_INFO_SAMP_FREQ),   \
  89 }
  90
  91 static const struct iio_chan_spec imx93_adc_iio_channels[] = {
  92         IMX93_ADC_CHAN(0),
  93         IMX93_ADC_CHAN(1),
  94         IMX93_ADC_CHAN(2),
  95         IMX93_ADC_CHAN(3),
  96 };
  97
  98 static void imx93_adc_power_down(struct imx93_adc *adc)
  99 {
 100         u32 mcr, msr;
 101         int ret;
 102
 103         mcr = readl(adc->regs + IMX93_ADC_MCR);
 104         mcr |= FIELD_PREP(IMX93_ADC_MCR_PWDN_MASK, 1);
 105         writel(mcr, adc->regs + IMX93_ADC_MCR);
 106
 107         ret = readl_poll_timeout(adc->regs + IMX93_ADC_MSR, msr,
 108                                  ((msr & IMX93_ADC_MSR_ADCSTATUS_MASK) ==
 109                                   IMX93_ADC_MSR_ADCSTATUS_POWER_DOWN),
 110                                  1, 50);
 111         if (ret == -ETIMEDOUT)
 112                 dev_warn(adc->dev,
 113                          "ADC do not in power down mode, current MSR is %x\n",
 114                          msr);
 115 }
 116
 117 static void imx93_adc_power_up(struct imx93_adc *adc)
 118 {
 119         u32 mcr;
 120
 121         /* bring ADC out of power down state, in idle state */
 122         mcr = readl(adc->regs + IMX93_ADC_MCR);
 123         mcr &= ~FIELD_PREP(IMX93_ADC_MCR_PWDN_MASK, 1);
 124         writel(mcr, adc->regs + IMX93_ADC_MCR);
 125 }
 126
 127 static void imx93_adc_config_ad_clk(struct imx93_adc *adc)
 128 {
 129         u32 mcr;
 130
 131         /* put adc in power down mode */
 132         imx93_adc_power_down(adc);
 133
 134         /* config the AD_CLK equal to bus clock */
 135         mcr = readl(adc->regs + IMX93_ADC_MCR);
 136         mcr |= FIELD_PREP(IMX93_ADC_MCR_ADCLKSE_MASK, 1);
 137         writel(mcr, adc->regs + IMX93_ADC_MCR);
 138
 139         imx93_adc_power_up(adc);
 140 }
 141
 142 static int imx93_adc_calibration(struct imx93_adc *adc)
 143 {
 144         u32 mcr, msr;
 145         int ret;
 146
 147         /* make sure ADC in power down mode */
 148         imx93_adc_power_down(adc);
 149
 150         /* config SAR controller operating clock */
 151         mcr = readl(adc->regs + IMX93_ADC_MCR);
 152         mcr &= ~FIELD_PREP(IMX93_ADC_MCR_ADCLKSE_MASK, 1);
 153         writel(mcr, adc->regs + IMX93_ADC_MCR);
 154
 155         imx93_adc_power_up(adc);
 156
 157         /*
 158          * TODO: we use the default TSAMP/NRSMPL/AVGEN in MCR,
 159          * can add the setting of these bit if need in future.
 160          */
 161
 162         /* run calibration */
 163         mcr = readl(adc->regs + IMX93_ADC_MCR);
 164         mcr |= FIELD_PREP(IMX93_ADC_MCR_CALSTART_MASK, 1);
 165         writel(mcr, adc->regs + IMX93_ADC_MCR);
 166
 167         /* wait calibration to be finished */
 168         ret = readl_poll_timeout(adc->regs + IMX93_ADC_MSR, msr,
 169                 !(msr & IMX93_ADC_MSR_CALBUSY_MASK), 1000, 2000000);
 170         if (ret == -ETIMEDOUT) {
 171                 dev_warn(adc->dev, "ADC do not finish calibration in 2 min!\n");
 172                 imx93_adc_power_down(adc);
 173                 return ret;
 174         }
 175
 176         /* check whether calbration is success or not */
 177         msr = readl(adc->regs + IMX93_ADC_MSR);
 178         if (msr & IMX93_ADC_MSR_CALFAIL_MASK) {
 179                 dev_warn(adc->dev, "ADC calibration failed!\n");
 180                 imx93_adc_power_down(adc);
 181                 return -EAGAIN;
 182         }
 183
 184         return 0;
 185 }
 186
 187 static int imx93_adc_read_channel_conversion(struct imx93_adc *adc,
 188                                                 int channel_number,
 189                                                 int *result)
 190 {
 191         u32 channel;
 192         u32 imr, mcr, pcda;
 193         long ret;
 194
 195         reinit_completion(&adc->completion);
 196
 197         /* config channel mask register */
 198         channel = 1 << channel_number;
 199         writel(channel, adc->regs + IMX93_ADC_NCMR0);
 200
 201         /* TODO: can config desired sample time in CTRn if need */
 202
 203         /* config interrupt mask */
 204         imr = FIELD_PREP(IMX93_ADC_IMR_EOC_MASK, 1);
 205         writel(imr, adc->regs + IMX93_ADC_IMR);
 206         writel(channel, adc->regs + IMX93_ADC_CIMR0);
 207
 208         /* config one-shot mode */
 209         mcr = readl(adc->regs + IMX93_ADC_MCR);
 210         mcr &= ~FIELD_PREP(IMX93_ADC_MCR_MODE_MASK, 1);
 211         writel(mcr, adc->regs + IMX93_ADC_MCR);
 212
 213         /* start normal conversion */
 214         mcr = readl(adc->regs + IMX93_ADC_MCR);
 215         mcr |= FIELD_PREP(IMX93_ADC_MCR_NSTART_MASK, 1);
 216         writel(mcr, adc->regs + IMX93_ADC_MCR);
 217
 218         ret = wait_for_completion_interruptible_timeout(&adc->completion,
 219                                                         IMX93_ADC_TIMEOUT);
 220         if (ret == 0)
 221                 return -ETIMEDOUT;
 222
 223         if (ret < 0)
 224                 return ret;
 225
 226         pcda = readl(adc->regs + IMX93_ADC_PCDR0 + channel_number * 4);
 227
 228         *result = FIELD_GET(IMX93_ADC_PCDR_CDATA_MASK, pcda);
 229
 230         return ret;
 231 }
 232
 233 static int imx93_adc_read_raw(struct iio_dev *indio_dev,
 234                                 struct iio_chan_spec const *chan,
 235                                 int *val, int *val2, long mask)
 236 {
 237         struct imx93_adc *adc = iio_priv(indio_dev);
 238         struct device *dev = adc->dev;
 239         int ret;
 240
 241         switch (mask) {
 242         case IIO_CHAN_INFO_RAW:
 243                 pm_runtime_get_sync(dev);
 244                 mutex_lock(&adc->lock);
 245                 ret = imx93_adc_read_channel_conversion(adc, chan->channel, val);
 246                 mutex_unlock(&adc->lock);
 247                 pm_runtime_mark_last_busy(dev);
 248                 pm_runtime_put_sync_autosuspend(dev);
 249                 if (ret < 0)
 250                         return ret;
 251
 252                 return IIO_VAL_INT;
 253
 254         case IIO_CHAN_INFO_SCALE:
 255                 ret = regulator_get_voltage(adc->vref);
 256                 if (ret < 0)
 257                         return ret;
 258                 *val = ret / 1000;
 259                 *val2 = 12;
 260                 return IIO_VAL_FRACTIONAL_LOG2;
 261
 262         case IIO_CHAN_INFO_SAMP_FREQ:
 263                 *val = clk_get_rate(adc->ipg_clk);
 264                 return IIO_VAL_INT;
 265
 266         default:
 267                 return -EINVAL;
 268         }
 269 }
 270
 271 static irqreturn_t imx93_adc_isr(int irq, void *dev_id)
 272 {
 273         struct imx93_adc *adc = dev_id;
 274         u32 isr, eoc, unexpected;
 275
 276         isr = readl(adc->regs + IMX93_ADC_ISR);
 277
 278         if (FIELD_GET(IMX93_ADC_ISR_EOC_ECH_MASK, isr)) {
 279                 eoc = isr & IMX93_ADC_ISR_EOC_ECH_MASK;
 280                 writel(eoc, adc->regs + IMX93_ADC_ISR);
 281                 complete(&adc->completion);
 282         }
 283
 284         unexpected = isr & ~IMX93_ADC_ISR_EOC_ECH_MASK;
 285         if (unexpected) {
 286                 writel(unexpected, adc->regs + IMX93_ADC_ISR);
 287                 dev_err(adc->dev, "Unexpected interrupt 0x%08x.\n", unexpected);
 288                 return IRQ_NONE;
 289         }
 290
 291         return IRQ_HANDLED;
 292 }
 293
 294 static const struct iio_info imx93_adc_iio_info = {
 295         .read_raw = &imx93_adc_read_raw,
 296 };
 297
 298 static int imx93_adc_probe(struct platform_device *pdev)
 299 {
 300         struct imx93_adc *adc;
 301         struct iio_dev *indio_dev;
 302         struct device *dev = &pdev->dev;
 303         int ret;
 304
 305         indio_dev = devm_iio_device_alloc(dev, sizeof(*adc));
 306         if (!indio_dev)
 307                 return dev_err_probe(dev, -ENOMEM,
 308                                      "Failed allocating iio device\n");
 309
 310         adc = iio_priv(indio_dev);
 311         adc->dev = dev;
 312
 313         mutex_init(&adc->lock);
 314         adc->regs = devm_platform_ioremap_resource(pdev, 0);
 315         if (IS_ERR(adc->regs))
 316                 return dev_err_probe(dev, PTR_ERR(adc->regs),
 317                                      "Failed getting ioremap resource\n");
 318
 319         /* The third irq is for ADC conversion usage */
 320         adc->irq = platform_get_irq(pdev, 2);
 321         if (adc->irq < 0)
 322                 return adc->irq;
 323
 324         adc->ipg_clk = devm_clk_get(dev, "ipg");
 325         if (IS_ERR(adc->ipg_clk))
 326                 return dev_err_probe(dev, PTR_ERR(adc->ipg_clk),
 327                                      "Failed getting clock.\n");
 328
 329         adc->vref = devm_regulator_get(dev, "vref");
 330         if (IS_ERR(adc->vref))
 331                 return dev_err_probe(dev, PTR_ERR(adc->vref),
 332                                      "Failed getting reference voltage.\n");
 333
 334         ret = regulator_enable(adc->vref);
 335         if (ret)
 336                 return dev_err_probe(dev, ret,
 337                                      "Failed to enable reference voltage.\n");
 338
 339         platform_set_drvdata(pdev, indio_dev);
 340
 341         init_completion(&adc->completion);
 342
 343         indio_dev->name = "imx93-adc";
 344         indio_dev->info = &imx93_adc_iio_info;
 345         indio_dev->modes = INDIO_DIRECT_MODE;
 346         indio_dev->channels = imx93_adc_iio_channels;
 347         indio_dev->num_channels = ARRAY_SIZE(imx93_adc_iio_channels);
 348
 349         ret = clk_prepare_enable(adc->ipg_clk);
 350         if (ret) {
 351                 dev_err_probe(dev, ret,
 352                               "Failed to enable ipg clock.\n");
 353                 goto error_regulator_disable;
 354         }
 355
 356         ret = request_irq(adc->irq, imx93_adc_isr, 0, IMX93_ADC_DRIVER_NAME, adc);
 357         if (ret < 0) {
 358                 dev_err_probe(dev, ret,
 359                               "Failed requesting irq, irq = %d\n", adc->irq);
 360                 goto error_ipg_clk_disable;
 361         }
 362
 363         ret = imx93_adc_calibration(adc);
 364         if (ret < 0)
 365                 goto error_free_adc_irq;
 366
 367         imx93_adc_config_ad_clk(adc);
 368
 369         ret = iio_device_register(indio_dev);
 370         if (ret) {
 371                 dev_err_probe(dev, ret,
 372                               "Failed to register this iio device.\n");
 373                 goto error_adc_power_down;
 374         }
 375
 376         pm_runtime_set_active(dev);
 377         pm_runtime_set_autosuspend_delay(dev, 50);
 378         pm_runtime_use_autosuspend(dev);
 379         pm_runtime_enable(dev);
 380
 381         return 0;
 382
 383 error_adc_power_down:
 384         imx93_adc_power_down(adc);
 385 error_free_adc_irq:
 386         free_irq(adc->irq, adc);
 387 error_ipg_clk_disable:
 388         clk_disable_unprepare(adc->ipg_clk);
 389 error_regulator_disable:
 390         regulator_disable(adc->vref);
 391
 392         return ret;
 393 }
 394
 395 static int imx93_adc_remove(struct platform_device *pdev)
 396 {
 397         struct iio_dev *indio_dev = platform_get_drvdata(pdev);
 398         struct imx93_adc *adc = iio_priv(indio_dev);
 399         struct device *dev = adc->dev;
 400
 401         /* adc power down need clock on */
 402         pm_runtime_get_sync(dev);
 403
 404         pm_runtime_disable(dev);
 405         pm_runtime_dont_use_autosuspend(dev);
 406         pm_runtime_put_noidle(dev);
 407
 408         iio_device_unregister(indio_dev);
 409         imx93_adc_power_down(adc);
 410         free_irq(adc->irq, adc);
 411         clk_disable_unprepare(adc->ipg_clk);
 412         regulator_disable(adc->vref);
 413
 414         return 0;
 415 }
 416
 417 static int imx93_adc_runtime_suspend(struct device *dev)
 418 {
 419         struct iio_dev *indio_dev = dev_get_drvdata(dev);
 420         struct imx93_adc *adc = iio_priv(indio_dev);
 421
 422         imx93_adc_power_down(adc);
 423         clk_disable_unprepare(adc->ipg_clk);
 424         regulator_disable(adc->vref);
 425
 426         return 0;
 427 }
 428
 429 static int imx93_adc_runtime_resume(struct device *dev)
 430 {
 431         struct iio_dev *indio_dev = dev_get_drvdata(dev);
 432         struct imx93_adc *adc = iio_priv(indio_dev);
 433         int ret;
 434
 435         ret = regulator_enable(adc->vref);
 436         if (ret) {
 437                 dev_err(dev,
 438                         "Can't enable adc reference top voltage, err = %d\n",
 439                         ret);
 440                 return ret;
 441         }
 442
 443         ret = clk_prepare_enable(adc->ipg_clk);
 444         if (ret) {
 445                 dev_err(dev, "Could not prepare or enable clock.\n");
 446                 goto err_disable_reg;
 447         }
 448
 449         imx93_adc_power_up(adc);
 450
 451         return 0;
 452
 453 err_disable_reg:
 454         regulator_disable(adc->vref);
 455
 456         return ret;
 457 }
 458
 459 static DEFINE_RUNTIME_DEV_PM_OPS(imx93_adc_pm_ops,
 460                                  imx93_adc_runtime_suspend,
 461                                  imx93_adc_runtime_resume, NULL);
 462
 463 static const struct of_device_id imx93_adc_match[] = {
 464         { .compatible = "nxp,imx93-adc", },
 465         { /* sentinel */ }
 466 };
 467 MODULE_DEVICE_TABLE(of, imx93_adc_match);
 468
 469 static struct platform_driver imx93_adc_driver = {
 470         .probe          = imx93_adc_probe,
 471         .remove         = imx93_adc_remove,
 472         .driver         = {
 473                 .name   = IMX93_ADC_DRIVER_NAME,
 474                 .of_match_table = imx93_adc_match,
 475                 .pm     = pm_ptr(&imx93_adc_pm_ops),
 476         },
 477 };
 478
 479 module_platform_driver(imx93_adc_driver);
 480
 481 MODULE_DESCRIPTION("NXP i.MX93 ADC driver");
 482 MODULE_AUTHOR("Haibo Chen <[email protected]>");
 483 MODULE_LICENSE("GPL");