drivers/platform/x86/intel/pmc/core.h

   1 /* SPDX-License-Identifier: GPL-2.0 */
   2 /*
   3  * Intel Core SoC Power Management Controller Header File
   4  *
   5  * Copyright (c) 2016, Intel Corporation.
   6  * All Rights Reserved.
   7  *
   8  * Authors: Rajneesh Bhardwaj <[email protected]>
   9  *          Vishwanath Somayaji <[email protected]>
  10  */
  11
  12 #ifndef PMC_CORE_H
  13 #define PMC_CORE_H
  14
  15 #include <linux/acpi.h>
  16 #include <linux/bits.h>
  17 #include <linux/platform_device.h>
  18
  19 #define PMC_BASE_ADDR_DEFAULT                   0xFE000000
  20
  21 /* Sunrise Point Power Management Controller PCI Device ID */
  22 #define SPT_PMC_PCI_DEVICE_ID                   0x9d21
  23 #define SPT_PMC_BASE_ADDR_OFFSET                0x48
  24 #define SPT_PMC_SLP_S0_RES_COUNTER_OFFSET       0x13c
  25 #define SPT_PMC_PM_CFG_OFFSET                   0x18
  26 #define SPT_PMC_PM_STS_OFFSET                   0x1c
  27 #define SPT_PMC_MTPMC_OFFSET                    0x20
  28 #define SPT_PMC_MFPMC_OFFSET                    0x38
  29 #define SPT_PMC_LTR_IGNORE_OFFSET               0x30C
  30 #define SPT_PMC_VRIC1_OFFSET                    0x31c
  31 #define SPT_PMC_MPHY_CORE_STS_0                 0x1143
  32 #define SPT_PMC_MPHY_CORE_STS_1                 0x1142
  33 #define SPT_PMC_MPHY_COM_STS_0                  0x1155
  34 #define SPT_PMC_MMIO_REG_LEN                    0x1000
  35 #define SPT_PMC_SLP_S0_RES_COUNTER_STEP         0x68
  36 #define PMC_BASE_ADDR_MASK                      ~(SPT_PMC_MMIO_REG_LEN - 1)
  37 #define MTPMC_MASK                              0xffff0000
  38 #define PPFEAR_MAX_NUM_ENTRIES                  12
  39 #define SPT_PPFEAR_NUM_ENTRIES                  5
  40 #define SPT_PMC_READ_DISABLE_BIT                0x16
  41 #define SPT_PMC_MSG_FULL_STS_BIT                0x18
  42 #define NUM_RETRIES                             100
  43 #define SPT_NUM_IP_IGN_ALLOWED                  17
  44
  45 #define SPT_PMC_LTR_CUR_PLT                     0x350
  46 #define SPT_PMC_LTR_CUR_ASLT                    0x354
  47 #define SPT_PMC_LTR_SPA                         0x360
  48 #define SPT_PMC_LTR_SPB                         0x364
  49 #define SPT_PMC_LTR_SATA                        0x368
  50 #define SPT_PMC_LTR_GBE                         0x36C
  51 #define SPT_PMC_LTR_XHCI                        0x370
  52 #define SPT_PMC_LTR_RESERVED                    0x374
  53 #define SPT_PMC_LTR_ME                          0x378
  54 #define SPT_PMC_LTR_EVA                         0x37C
  55 #define SPT_PMC_LTR_SPC                         0x380
  56 #define SPT_PMC_LTR_AZ                          0x384
  57 #define SPT_PMC_LTR_LPSS                        0x38C
  58 #define SPT_PMC_LTR_CAM                         0x390
  59 #define SPT_PMC_LTR_SPD                         0x394
  60 #define SPT_PMC_LTR_SPE                         0x398
  61 #define SPT_PMC_LTR_ESPI                        0x39C
  62 #define SPT_PMC_LTR_SCC                         0x3A0
  63 #define SPT_PMC_LTR_ISH                         0x3A4
  64
  65 /* Sunrise Point: PGD PFET Enable Ack Status Registers */
  66 enum ppfear_regs {
  67         SPT_PMC_XRAM_PPFEAR0A = 0x590,
  68         SPT_PMC_XRAM_PPFEAR0B,
  69         SPT_PMC_XRAM_PPFEAR0C,
  70         SPT_PMC_XRAM_PPFEAR0D,
  71         SPT_PMC_XRAM_PPFEAR1A,
  72 };
  73
  74 #define SPT_PMC_BIT_PMC                         BIT(0)
  75 #define SPT_PMC_BIT_OPI                         BIT(1)
  76 #define SPT_PMC_BIT_SPI                         BIT(2)
  77 #define SPT_PMC_BIT_XHCI                        BIT(3)
  78 #define SPT_PMC_BIT_SPA                         BIT(4)
  79 #define SPT_PMC_BIT_SPB                         BIT(5)
  80 #define SPT_PMC_BIT_SPC                         BIT(6)
  81 #define SPT_PMC_BIT_GBE                         BIT(7)
  82
  83 #define SPT_PMC_BIT_SATA                        BIT(0)
  84 #define SPT_PMC_BIT_HDA_PGD0                    BIT(1)
  85 #define SPT_PMC_BIT_HDA_PGD1                    BIT(2)
  86 #define SPT_PMC_BIT_HDA_PGD2                    BIT(3)
  87 #define SPT_PMC_BIT_HDA_PGD3                    BIT(4)
  88 #define SPT_PMC_BIT_RSVD_0B                     BIT(5)
  89 #define SPT_PMC_BIT_LPSS                        BIT(6)
  90 #define SPT_PMC_BIT_LPC                         BIT(7)
  91
  92 #define SPT_PMC_BIT_SMB                         BIT(0)
  93 #define SPT_PMC_BIT_ISH                         BIT(1)
  94 #define SPT_PMC_BIT_P2SB                        BIT(2)
  95 #define SPT_PMC_BIT_DFX                         BIT(3)
  96 #define SPT_PMC_BIT_SCC                         BIT(4)
  97 #define SPT_PMC_BIT_RSVD_0C                     BIT(5)
  98 #define SPT_PMC_BIT_FUSE                        BIT(6)
  99 #define SPT_PMC_BIT_CAMREA                      BIT(7)
 100
 101 #define SPT_PMC_BIT_RSVD_0D                     BIT(0)
 102 #define SPT_PMC_BIT_USB3_OTG                    BIT(1)
 103 #define SPT_PMC_BIT_EXI                         BIT(2)
 104 #define SPT_PMC_BIT_CSE                         BIT(3)
 105 #define SPT_PMC_BIT_CSME_KVM                    BIT(4)
 106 #define SPT_PMC_BIT_CSME_PMT                    BIT(5)
 107 #define SPT_PMC_BIT_CSME_CLINK                  BIT(6)
 108 #define SPT_PMC_BIT_CSME_PTIO                   BIT(7)
 109
 110 #define SPT_PMC_BIT_CSME_USBR                   BIT(0)
 111 #define SPT_PMC_BIT_CSME_SUSRAM                 BIT(1)
 112 #define SPT_PMC_BIT_CSME_SMT                    BIT(2)
 113 #define SPT_PMC_BIT_RSVD_1A                     BIT(3)
 114 #define SPT_PMC_BIT_CSME_SMS2                   BIT(4)
 115 #define SPT_PMC_BIT_CSME_SMS1                   BIT(5)
 116 #define SPT_PMC_BIT_CSME_RTC                    BIT(6)
 117 #define SPT_PMC_BIT_CSME_PSF                    BIT(7)
 118
 119 #define SPT_PMC_BIT_MPHY_LANE0                  BIT(0)
 120 #define SPT_PMC_BIT_MPHY_LANE1                  BIT(1)
 121 #define SPT_PMC_BIT_MPHY_LANE2                  BIT(2)
 122 #define SPT_PMC_BIT_MPHY_LANE3                  BIT(3)
 123 #define SPT_PMC_BIT_MPHY_LANE4                  BIT(4)
 124 #define SPT_PMC_BIT_MPHY_LANE5                  BIT(5)
 125 #define SPT_PMC_BIT_MPHY_LANE6                  BIT(6)
 126 #define SPT_PMC_BIT_MPHY_LANE7                  BIT(7)
 127
 128 #define SPT_PMC_BIT_MPHY_LANE8                  BIT(0)
 129 #define SPT_PMC_BIT_MPHY_LANE9                  BIT(1)
 130 #define SPT_PMC_BIT_MPHY_LANE10                 BIT(2)
 131 #define SPT_PMC_BIT_MPHY_LANE11                 BIT(3)
 132 #define SPT_PMC_BIT_MPHY_LANE12                 BIT(4)
 133 #define SPT_PMC_BIT_MPHY_LANE13                 BIT(5)
 134 #define SPT_PMC_BIT_MPHY_LANE14                 BIT(6)
 135 #define SPT_PMC_BIT_MPHY_LANE15                 BIT(7)
 136
 137 #define SPT_PMC_BIT_MPHY_CMN_LANE0              BIT(0)
 138 #define SPT_PMC_BIT_MPHY_CMN_LANE1              BIT(1)
 139 #define SPT_PMC_BIT_MPHY_CMN_LANE2              BIT(2)
 140 #define SPT_PMC_BIT_MPHY_CMN_LANE3              BIT(3)
 141
 142 #define SPT_PMC_VRIC1_SLPS0LVEN                 BIT(13)
 143 #define SPT_PMC_VRIC1_XTALSDQDIS                BIT(22)
 144
 145 /* Cannonlake Power Management Controller register offsets */
 146 #define CNP_PMC_SLPS0_DBG_OFFSET                0x10B4
 147 #define CNP_PMC_PM_CFG_OFFSET                   0x1818
 148 #define CNP_PMC_SLP_S0_RES_COUNTER_OFFSET       0x193C
 149 #define CNP_PMC_LTR_IGNORE_OFFSET               0x1B0C
 150 /* Cannonlake: PGD PFET Enable Ack Status Register(s) start */
 151 #define CNP_PMC_HOST_PPFEAR0A                   0x1D90
 152
 153 #define CNP_PMC_LATCH_SLPS0_EVENTS              BIT(31)
 154
 155 #define CNP_PMC_MMIO_REG_LEN                    0x2000
 156 #define CNP_PPFEAR_NUM_ENTRIES                  8
 157 #define CNP_PMC_READ_DISABLE_BIT                22
 158 #define CNP_NUM_IP_IGN_ALLOWED                  19
 159 #define CNP_PMC_LTR_CUR_PLT                     0x1B50
 160 #define CNP_PMC_LTR_CUR_ASLT                    0x1B54
 161 #define CNP_PMC_LTR_SPA                         0x1B60
 162 #define CNP_PMC_LTR_SPB                         0x1B64
 163 #define CNP_PMC_LTR_SATA                        0x1B68
 164 #define CNP_PMC_LTR_GBE                         0x1B6C
 165 #define CNP_PMC_LTR_XHCI                        0x1B70
 166 #define CNP_PMC_LTR_RESERVED                    0x1B74
 167 #define CNP_PMC_LTR_ME                          0x1B78
 168 #define CNP_PMC_LTR_EVA                         0x1B7C
 169 #define CNP_PMC_LTR_SPC                         0x1B80
 170 #define CNP_PMC_LTR_AZ                          0x1B84
 171 #define CNP_PMC_LTR_LPSS                        0x1B8C
 172 #define CNP_PMC_LTR_CAM                         0x1B90
 173 #define CNP_PMC_LTR_SPD                         0x1B94
 174 #define CNP_PMC_LTR_SPE                         0x1B98
 175 #define CNP_PMC_LTR_ESPI                        0x1B9C
 176 #define CNP_PMC_LTR_SCC                         0x1BA0
 177 #define CNP_PMC_LTR_ISH                         0x1BA4
 178 #define CNP_PMC_LTR_CNV                         0x1BF0
 179 #define CNP_PMC_LTR_EMMC                        0x1BF4
 180 #define CNP_PMC_LTR_UFSX2                       0x1BF8
 181
 182 #define LTR_DECODED_VAL                         GENMASK(9, 0)
 183 #define LTR_DECODED_SCALE                       GENMASK(12, 10)
 184 #define LTR_REQ_SNOOP                           BIT(15)
 185 #define LTR_REQ_NONSNOOP                        BIT(31)
 186
 187 #define ICL_PPFEAR_NUM_ENTRIES                  9
 188 #define ICL_NUM_IP_IGN_ALLOWED                  20
 189 #define ICL_PMC_LTR_WIGIG                       0x1BFC
 190 #define ICL_PMC_SLP_S0_RES_COUNTER_STEP         0x64
 191
 192 #define LPM_MAX_NUM_MODES                       8
 193 #define LPM_DEFAULT_PRI                         { 7, 6, 2, 5, 4, 1, 3, 0 }
 194
 195 #define GET_X2_COUNTER(v)                       ((v) >> 1)
 196 #define LPM_STS_LATCH_MODE                      BIT(31)
 197
 198 #define TGL_PMC_SLP_S0_RES_COUNTER_STEP         0x7A
 199 #define TGL_PMC_LTR_THC0                        0x1C04
 200 #define TGL_PMC_LTR_THC1                        0x1C08
 201 #define TGL_NUM_IP_IGN_ALLOWED                  23
 202 #define TGL_PMC_LPM_RES_COUNTER_STEP_X2         61      /* 30.5us * 2 */
 203
 204 #define ADL_PMC_LTR_SPF                         0x1C00
 205 #define ADL_NUM_IP_IGN_ALLOWED                  23
 206 #define ADL_PMC_SLP_S0_RES_COUNTER_OFFSET       0x1098
 207
 208 /*
 209  * Tigerlake Power Management Controller register offsets
 210  */
 211 #define TGL_LPM_STS_LATCH_EN_OFFSET             0x1C34
 212 #define TGL_LPM_EN_OFFSET                       0x1C78
 213 #define TGL_LPM_RESIDENCY_OFFSET                0x1C80
 214
 215 /* Tigerlake Low Power Mode debug registers */
 216 #define TGL_LPM_STATUS_OFFSET                   0x1C3C
 217 #define TGL_LPM_LIVE_STATUS_OFFSET              0x1C5C
 218 #define TGL_LPM_PRI_OFFSET                      0x1C7C
 219 #define TGL_LPM_NUM_MAPS                        6
 220
 221 /* Extended Test Mode Register 3 (CNL and later) */
 222 #define ETR3_OFFSET                             0x1048
 223 #define ETR3_CF9GR                              BIT(20)
 224 #define ETR3_CF9LOCK                            BIT(31)
 225
 226 /* Extended Test Mode Register LPM bits (TGL and later */
 227 #define ETR3_CLEAR_LPM_EVENTS                   BIT(28)
 228
 229 /* Alder Lake Power Management Controller register offsets */
 230 #define ADL_LPM_EN_OFFSET                       0x179C
 231 #define ADL_LPM_RESIDENCY_OFFSET                0x17A4
 232 #define ADL_LPM_NUM_MODES                       2
 233 #define ADL_LPM_NUM_MAPS                        14
 234
 235 /* Alder Lake Low Power Mode debug registers */
 236 #define ADL_LPM_STATUS_OFFSET                   0x170C
 237 #define ADL_LPM_PRI_OFFSET                      0x17A0
 238 #define ADL_LPM_STATUS_LATCH_EN_OFFSET          0x1704
 239 #define ADL_LPM_LIVE_STATUS_OFFSET              0x1764
 240
 241 /* Meteor Lake Power Management Controller register offsets */
 242 #define MTL_LPM_EN_OFFSET                       0x1798
 243 #define MTL_LPM_RESIDENCY_OFFSET                0x17A0
 244
 245 /* Meteor Lake Low Power Mode debug registers */
 246 #define MTL_LPM_PRI_OFFSET                      0x179C
 247 #define MTL_LPM_STATUS_LATCH_EN_OFFSET          0x16F8
 248 #define MTL_LPM_STATUS_OFFSET                   0x1700
 249 #define MTL_LPM_LIVE_STATUS_OFFSET              0x175C
 250
 251 extern const char *pmc_lpm_modes[];
 252
 253 struct pmc_bit_map {
 254         const char *name;
 255         u32 bit_mask;
 256 };
 257
 258 /**
 259  * struct pmc_reg_map - Structure used to define parameter unique to a
 260                         PCH family
 261  * @pfear_sts:          Maps name of IP block to PPFEAR* bit
 262  * @mphy_sts:           Maps name of MPHY lane to MPHY status lane status bit
 263  * @pll_sts:            Maps name of PLL to corresponding bit status
 264  * @slps0_dbg_maps:     Array of SLP_S0_DBG* registers containing debug info
 265  * @ltr_show_sts:       Maps PCH IP Names to their MMIO register offsets
 266  * @slp_s0_offset:      PWRMBASE offset to read SLP_S0 residency
 267  * @ltr_ignore_offset:  PWRMBASE offset to read/write LTR ignore bit
 268  * @regmap_length:      Length of memory to map from PWRMBASE address to access
 269  * @ppfear0_offset:     PWRMBASE offset to read PPFEAR*
 270  * @ppfear_buckets:     Number of 8 bits blocks to read all IP blocks from
 271  *                      PPFEAR
 272  * @pm_cfg_offset:      PWRMBASE offset to PM_CFG register
 273  * @pm_read_disable_bit: Bit index to read PMC_READ_DISABLE
 274  * @slps0_dbg_offset:   PWRMBASE offset to SLP_S0_DEBUG_REG*
 275  *
 276  * Each PCH has unique set of register offsets and bit indexes. This structure
 277  * captures them to have a common implementation.
 278  */
 279 struct pmc_reg_map {
 280         const struct pmc_bit_map **pfear_sts;
 281         const struct pmc_bit_map *mphy_sts;
 282         const struct pmc_bit_map *pll_sts;
 283         const struct pmc_bit_map **slps0_dbg_maps;
 284         const struct pmc_bit_map *ltr_show_sts;
 285         const struct pmc_bit_map *msr_sts;
 286         const struct pmc_bit_map **lpm_sts;
 287         const u32 slp_s0_offset;
 288         const int slp_s0_res_counter_step;
 289         const u32 ltr_ignore_offset;
 290         const int regmap_length;
 291         const u32 ppfear0_offset;
 292         const int ppfear_buckets;
 293         const u32 pm_cfg_offset;
 294         const int pm_read_disable_bit;
 295         const u32 slps0_dbg_offset;
 296         const u32 ltr_ignore_max;
 297         const u32 pm_vric1_offset;
 298         /* Low Power Mode registers */
 299         const int lpm_num_maps;
 300         const int lpm_num_modes;
 301         const int lpm_res_counter_step_x2;
 302         const u32 lpm_sts_latch_en_offset;
 303         const u32 lpm_en_offset;
 304         const u32 lpm_priority_offset;
 305         const u32 lpm_residency_offset;
 306         const u32 lpm_status_offset;
 307         const u32 lpm_live_status_offset;
 308         const u32 etr3_offset;
 309 };
 310
 311 /**
 312  * struct pmc_dev - pmc device structure
 313  * @base_addr:          contains pmc base address
 314  * @regbase:            pointer to io-remapped memory location
 315  * @map:                pointer to pmc_reg_map struct that contains platform
 316  *                      specific attributes
 317  * @pdev:               pointer to platform_device struct
 318  * @dbgfs_dir:          path to debugfs interface
 319  * @pmc_xram_read_bit:  flag to indicate whether PMC XRAM shadow registers
 320  *                      used to read MPHY PG and PLL status are available
 321  * @mutex_lock:         mutex to complete one transcation
 322  * @check_counters:     On resume, check if counters are getting incremented
 323  * @pc10_counter:       PC10 residency counter
 324  * @s0ix_counter:       S0ix residency (step adjusted)
 325  * @num_lpm_modes:      Count of enabled modes
 326  * @lpm_en_modes:       Array of enabled modes from lowest to highest priority
 327  * @lpm_req_regs:       List of substate requirements
 328  * @core_configure:     Function pointer to configure the platform
 329  *
 330  * pmc_dev contains info about power management controller device.
 331  */
 332 struct pmc_dev {
 333         u32 base_addr;
 334         void __iomem *regbase;
 335         const struct pmc_reg_map *map;
 336         struct dentry *dbgfs_dir;
 337         struct platform_device *pdev;
 338         int pmc_xram_read_bit;
 339         struct mutex lock; /* generic mutex lock for PMC Core */
 340
 341         bool check_counters; /* Check for counter increments on resume */
 342         u64 pc10_counter;
 343         u64 s0ix_counter;
 344         int num_lpm_modes;
 345         int lpm_en_modes[LPM_MAX_NUM_MODES];
 346         u32 *lpm_req_regs;
 347         void (*core_configure)(struct pmc_dev *pmcdev);
 348 };
 349
 350 extern const struct pmc_bit_map msr_map[];
 351 extern const struct pmc_bit_map spt_pll_map[];
 352 extern const struct pmc_bit_map spt_mphy_map[];
 353 extern const struct pmc_bit_map spt_pfear_map[];
 354 extern const struct pmc_bit_map *ext_spt_pfear_map[];
 355 extern const struct pmc_bit_map spt_ltr_show_map[];
 356 extern const struct pmc_reg_map spt_reg_map;
 357 extern const struct pmc_bit_map cnp_pfear_map[];
 358 extern const struct pmc_bit_map *ext_cnp_pfear_map[];
 359 extern const struct pmc_bit_map cnp_slps0_dbg0_map[];
 360 extern const struct pmc_bit_map cnp_slps0_dbg1_map[];
 361 extern const struct pmc_bit_map cnp_slps0_dbg2_map[];
 362 extern const struct pmc_bit_map *cnp_slps0_dbg_maps[];
 363 extern const struct pmc_bit_map cnp_ltr_show_map[];
 364 extern const struct pmc_reg_map cnp_reg_map;
 365 extern const struct pmc_bit_map icl_pfear_map[];
 366 extern const struct pmc_bit_map *ext_icl_pfear_map[];
 367 extern const struct pmc_reg_map icl_reg_map;
 368 extern const struct pmc_bit_map tgl_pfear_map[];
 369 extern const struct pmc_bit_map *ext_tgl_pfear_map[];
 370 extern const struct pmc_bit_map tgl_clocksource_status_map[];
 371 extern const struct pmc_bit_map tgl_power_gating_status_map[];
 372 extern const struct pmc_bit_map tgl_d3_status_map[];
 373 extern const struct pmc_bit_map tgl_vnn_req_status_map[];
 374 extern const struct pmc_bit_map tgl_vnn_misc_status_map[];
 375 extern const struct pmc_bit_map tgl_signal_status_map[];
 376 extern const struct pmc_bit_map *tgl_lpm_maps[];
 377 extern const struct pmc_reg_map tgl_reg_map;
 378 extern const struct pmc_bit_map adl_pfear_map[];
 379 extern const struct pmc_bit_map *ext_adl_pfear_map[];
 380 extern const struct pmc_bit_map adl_ltr_show_map[];
 381 extern const struct pmc_bit_map adl_clocksource_status_map[];
 382 extern const struct pmc_bit_map adl_power_gating_status_0_map[];
 383 extern const struct pmc_bit_map adl_power_gating_status_1_map[];
 384 extern const struct pmc_bit_map adl_power_gating_status_2_map[];
 385 extern const struct pmc_bit_map adl_d3_status_0_map[];
 386 extern const struct pmc_bit_map adl_d3_status_1_map[];
 387 extern const struct pmc_bit_map adl_d3_status_2_map[];
 388 extern const struct pmc_bit_map adl_d3_status_3_map[];
 389 extern const struct pmc_bit_map adl_vnn_req_status_0_map[];
 390 extern const struct pmc_bit_map adl_vnn_req_status_1_map[];
 391 extern const struct pmc_bit_map adl_vnn_req_status_2_map[];
 392 extern const struct pmc_bit_map adl_vnn_req_status_3_map[];
 393 extern const struct pmc_bit_map adl_vnn_misc_status_map[];
 394 extern const struct pmc_bit_map *adl_lpm_maps[];
 395 extern const struct pmc_reg_map adl_reg_map;
 396 extern const struct pmc_reg_map mtl_reg_map;
 397
 398 extern void pmc_core_get_tgl_lpm_reqs(struct platform_device *pdev);
 399 extern int pmc_core_send_ltr_ignore(struct pmc_dev *pmcdev, u32 value);
 400
 401 void spt_core_init(struct pmc_dev *pmcdev);
 402 void cnp_core_init(struct pmc_dev *pmcdev);
 403 void icl_core_init(struct pmc_dev *pmcdev);
 404 void tgl_core_init(struct pmc_dev *pmcdev);
 405 void adl_core_init(struct pmc_dev *pmcdev);
 406 void mtl_core_init(struct pmc_dev *pmcdev);
 407 void tgl_core_configure(struct pmc_dev *pmcdev);
 408 void adl_core_configure(struct pmc_dev *pmcdev);
 409 void mtl_core_configure(struct pmc_dev *pmcdev);
 410
 411 #define pmc_for_each_mode(i, mode, pmcdev)              \
 412         for (i = 0, mode = pmcdev->lpm_en_modes[i];     \
 413              i < pmcdev->num_lpm_modes;                 \
 414              i++, mode = pmcdev->lpm_en_modes[i])
 415
 416 #define DEFINE_PMC_CORE_ATTR_WRITE(__name)                              \
 417 static int __name ## _open(struct inode *inode, struct file *file)      \
 418 {                                                                       \
 419         return single_open(file, __name ## _show, inode->i_private);    \
 420 }                                                                       \
 421                                                                         \
 422 static const struct file_operations __name ## _fops = {                 \
 423         .owner          = THIS_MODULE,                                  \
 424         .open           = __name ## _open,                              \
 425         .read           = seq_read,                                     \
 426         .write          = __name ## _write,                             \
 427         .release        = single_release,                               \
 428 }
 429
 430 #endif /* PMC_CORE_H */